text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 24, 1981
|Filing date
|Nov 2, 1979
|Priority date
|Nov 6, 1978
|Also published as
|Publication number
|Vittorio Zanchi, Tiziano Maccianti
|Original Assignee
|Honeywell Information Systems Italia
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (17), Referenced by (29), Classifications (10)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates to data processing systems and more particularly to the transfer of information over a common input/output bus.
In systems having a plurality of devices coupled over a common channel or BUS some means must be provided by which an orderly transfer of information over such channel may be provided and the conflicts and the interferences rising in the use of such bus may be solved.
In general, the previously adopted solutions provide for a privileged device or MASTER, which may be a central unit, a control unit with such specific function, or the system working memory, having the task of controlling the channel use so as to solve the conflicts. To this end, a pre-established priority is assigned to each unit which asks to access the BUS. The MASTER detects periodically if BUS access requests are present and, in case of two or more contemporaneous requests, it assigns the BUS to the requesting unit having greater priority. Such solutions have the disadvantage of assigning the priorities in a rigid way and the risk exists that the unit with greater priority monopolizes the access to the BUS at disadvantage of the other units.
According to some prior art embodiments, such risk is avoided by assigning to the units a variable priority which is changed in accordance with the circumstances: in such case the MASTER assigns the relative priority among the various units according to the different needs. However, the MASTER is required to supervise the different operations made by the several units in order to know the real needs of such units. Therefore, such solutions are not suitable to solve the conflicts in a system where various units are coupled through a BUS and a plurality of intelligent autonomous units act together, as for instance in the Multiprocessor systems. In addition, in such a case, the priority network, which must handle the conflicts, must be particularly complex.
According to other prior art embodiments, each unit can send, in accordance with its needs, access requests at different priority levels using several signals on a plurality of leads. This requires the use of a great number of leads, as well as the use of a very complex priority network in the MASTER: practically, it is as if the MASTER had to handle as much apparent units as the real number of such units multiplied by the different types of requests which can be sent by each unit. Then, the handling problem of the access requests to BUS is further complicated by the intervention of other elements, such as: the synchronous and the asynchronous nature of the access requests and the synchronous or asynchronous operation of the MASTER.
It is therefore one of the purposes of the present invention to supply an apparatus for the handling of data transfer requests in data processing systems formed by a plurality of autonomous units which want, at the same time, the access to a working memory or, in general, to a MASTER through a common BUS to which all units are connected, said apparatus being simple and economical.
Another purpose of the present invention is to provide an interrupt handling apparatus which makes use of a reduced number of leads and, at the same time, which enables the several units to send access requests at different priority levels thus avoiding the risks of BUS monopolization by the unit with the highest priority.
Another purpose of the present invention is to supply an interrupt handling apparatus where the several units (MASTER and working memory included) exchange information in an asynchronous way.
These and other invention purposes are achieved by the apparatus according to the invention which can be said to be characterised in that it comprises: a simple priority network for fixed priority assignment to several requesting units (such a simplified priority network is part of the working memory or of the MASTER); means suitable to produce BUS access requests at different priority or urgency levels in each unit; and a priority network distributed in each unit which enables the different units to mask their possible access requests with lower priority or urgency level, if at least an access request with higher priority level is present. In other words, the MASTER and its coupled priority network receive only a level of access request each time and only a type of access request from each unit. This makes it possible to greatly simplify the priority network coupled to the MASTER and to reduce the number of leads used for the access request transfer, with the only restriction that the respective priority assigned to the several units must be the same for the different levels.
These and other features of the invention will appear more clearly from the following description of a preferred embodiment of the invention and by the enclosed drawings in which:
FIG. 1 shows in block diagram the structure of a data processing system including the device of the invention;
FIG. 2 shows in block diagram, with more details, the structure of the units or processors forming the system of FIG. 1;
FIG. 3 shows the conventional diagram used in the following figures to show JK flip-flops;
FIG. 4 shows the circuits of the interface dialogue unit included in each unit or processor shown in FIG. 2;
FIG. 5 shows the circuits of a memory and BUS address control unit of the system of FIG. 1; and
FIG. 6 is a timing diagram showing an example of a dialogue which occurs among the memory unit of FIG. 5 and the several system units or processors.
FIG. 1 shows in block diagram the structure of the system and of the BUS interconnecting several units. For instance, the system consists of three units or processors 1, 2, and 3 (generally N processors) and a working memory 4 to which a memory access controller GAM 5 is coupled. The units 1, 2, and 3 and GAM 5 are interconnected by means of a single system BUS comprising a suitable number of leads.
The system BUS comprises:
(1) A lead group 6 for the transfer of data, commands, addresses and possibly check bits, such group totally comprising, for instance, 72 leads (4 data bytes, 2 address bytes, 1 command byte and 1 check bit for each byte) This lead group 6, named DAC-BUS, is bidirectional: each unit such as 1, 2, 3, and 4, is coupled to DAC-BUS by means of interface circuits which may both receive and transmit signals. In rest condition, the transmitting circuits present a virtually infinite output impedance so that the DAC-BUS leads are virtually disconnected from the several units. In work condition, that is when the transmitting circuits of only one unit are active, the transmitting circuits may apply to the leads one of two electric levels corresponding to two logic levels 0 or 1. Later on, unless it is differently specified, the convention will be used for which the logic level 1 corresponds to an electric high level and the logic level 0 to an electric low or zero level. Such logic levels can be detected by all receiving units. Transmitter logic circuits of such type are know as TRISTATE-DRIVERS and are available on the market so that any further information is not essential for understanding the present invention.
(2) A group of leads 7,8, and 9 for the transfer of dialogue controlling signals, such signals being respectively named ENCY, PROCOL, and MECOL. These leads couple the several units 1, 2, 3, and 4 with a connection of the type known as an "open collector": as it will be seen later on, this type of connection requires that the connecting lead be connected to a voltage source through a resistor. In each unit the line is connected to a receiver with relatively high impedence; in at least one unit such line is connected to an open collector transmitter, which may connect said line to ground or virtually disconnect it so as to apply to such line an electric and logic level 0 or 1 respectively. Clearly it suffices that only one of the several transmitters connects the line to ground to obtain an electric logic level 0 on all the line and to have it detected by the different receivers.
(3) A lead 10 for the transfer of a signal CHART; such lead, when at electric logic level 0, indicates that one unit wishes to access the BUS with a high priority level request. This lead interconnects the several units 1, 2, and 3 (but not necessarily GAM 5 too) with an open collector connection.
(4) A group of leads 11, 12, and 13 with individually couple each unit 1, 2, and 3 with GAM 5, by means of an open collector coupling; such leads are used to send to GAM 5 a BUS access request signal respectively named BURE 1, BURE 2, and BURE 3 and to receive from GAM 5 its assent.
FIG. 2 shows in block diagram the structure of a processor such as unit 1, 2 or 3 in FIG. 1. The unit comprises a set of interface registers for storing the received information or the information to be transmitted on BUS, particularly on DAC-BUS 6. As it is purported that the units can enter into BUS with two priority levels, it is convenient, even if generally not essential, that such registers are specifically dedicated to a priority level. Therefore, FIG. 2 shows a register 14 (LPO-REG) used as an output data register for low priority access requests, a register 15 (HPO-REG) for high priority data output, a register 16 (HPI-REG) for high priority data reception and a register 17 (LPI-REG) for low priority data reception. The outputs of registers 14 and 15 are respectively coupled to the inputs of two TRISTATE transmitter sets 18, 19 whose outputs are coupled to DAC-BUS. The inputs of registers 16 and 17 are coupled to the DAC-BUS through a set of receivers 20.
The processor comprises further a control unit 21, an operating unit 22, a working register set 23, and an interface dialogue unit 24. The control unit 21 sends through leads 14A and 15A some control signals to the registers and respectively to registers 14 and 15 to enable them to be loaded and sends suitable commands to the operating unit, to the working registers and to the interface dialogue unit 24 receiving in turn suitable signals from them. The communications paths are shown as 200 and 201. The interface registers communicate through suitable paths, not shown, with the working registers and the operating unit. On its part, the dialogue unit 24 is connected to the system BUS leads already referenced in FIG. 1 with numerals 10, 7, 8, 9, 11 (or 12 or 13). In addition, the dialogue unit enables the groups of transmitters 19 and 18 through signals on leads 76 and 77 and the loading of registers 16 and 17, through a signal on leads 78 and 79.
As a detailed description of the structure of a processor such as the one in FIG. 2 is not essential for understanding the invention, and as such structure can be made in several ways, even very different from each other, such description is omitted. A more detailed description of the embodiment can be found, for instance in U.S. Pat. No. 3,710,324.
On the contrary, for the purposes of the present invention only the architecture of dialogue and priority unit 24, contained in each processor, as well as of the working memory 4 with reference to GAM 5, will be considered in detail. Before going on we will briefly describe the operation of J-K flip-flops because these will be largely used later.
FIG. 3 shows the conventional representation generally used for such a flip-flop which has been available in the market for a long time as an integrated circuit. The J-K flip-flop is a bistable circuit provided with a timing clock input CK, with two direct or set-reset asynchronous inputs S and R with two synchronous or clock conditioned inputs J and K and with two outputs Q and Q. A signal applied to S or R inputs activates the flip-flop putting it permanently in one of two possible electrical states, while the signals at the J and K inputs activate the flip-flop only when the trailing edge of a positive electrical/logic pulse is applied to CK input. The following table summarizes the J-K flip-flop operation.
______________________________________INPUTS OUTPUTSS R CK J K Q -Q______________________________________L H X X X H LH L X X X L HL L X X X H HH H L L L Qo -QoH H L H L H LH H L L H L HH H L H H commutatesH H H X X Qo -Qo______________________________________
In the above table L stands for a logic/electric level 0 present at the corresponding output-input;
H for a logic electric level 1;
X for an indifference condition;
Qo and Qo stand for the state of the Q and Q outputs before the signals are applied.
For instance, it can be seen that both S and R inputs must be at logic level 1 to have the flip-flop activated by a clock pulse (CK=L). Later on, for the sake of clarity, the J-K flip-flops will be shown in the several figures as in FIG. 3 without reference letters.
Always for sake of clearness, the possible leaving out of any indication on some inputs, particularly J or K, will designate that an appropriate electrical signal "1" or "0", suitable to obtain the desired behaviour, is permanently applied to such inputs.
FIG. 4 shows in detail a preferred embodiment of dialogue and priority assignment unit 24 contained in each processor 1, 2 or 3 of FIG. 1 and particularly referring to processor 1. The unit 24 comprises two J-K flip-flops 25 and 26 (BURE-HP and BURE-LP) which receive at the clock input a microcommand MC through two NAND gates 25A and 26A enabled by a signal state HP and HP respectively. MC and HP and HP come from control unit 21 (FIG. 2). The inverted output Q of flip-flop 25 is connected to the J input of a J-K flip-flop 40. The direct output of flip-flop 25 is connected to a first input of a two input NOR gate 27, to a J input of a J-K flip-flop 39, to a first input of a two inputs OR gate 80 and to the input of an open collector inverter/driver 31. The output of inverter/driver 31 is connected to the system BUS lead 10; such lead is kept at logic level 1 by a resistor 32, connected to a +V voltage source, if all driver circuits 31 connected to such lead are opened, say driven with an input signal at logical level 0. It is therefore clear that, when flip-flop 25 is set, lead 10 falls to logic level 0 while it is normally at logic level 1.
The output of NOR gate 27 is connected to an open collector inverter/driver circuit 29 whose output is connected to the system BUS lead 11. As already said, lead 11 is connected to a +V voltage source through a resistor 30, and it is coupled with GAM 5 at the other end. The direct output of flip-flop 26 is connected to a first input of an AND gate 33 whose output is connected to the second input of NOR gate 27. The second input of AND gate 33 is connected to the Q output of a flip-flop 54 (MASK) normally reset.
Flip-flops 25 and 26 are normally reset: it is therefore clear that the respective direct outputs are at logic level 0 and that the output of NOR 27 is at logic level 1, thus lead 11 (BURE 1) is normally at logic level 0. When processor 1 requests access to the BUS, its control unit produces, in an asynchronous way relative to the system operation (though inside the processor the event may occur at a predetermined instant of its machine cycle), a command pulse MC, accompanied by a signal state HP or HP according to whether the requested access has high or low priority. Thus one of the two flip-flops 25 or 26 is set. Since one of the two flip-flops 25 or 26 is set, lead 11 rises to logic level 1 and signals to GAM 5 that processor 1 wants access to the BUS (signal BURE at 1). Moreover, if flip-flop 25 is set, lead 10 goes to logic/electrical level 0 (signal CHART at 0) and signals to the other processors, such as 2 and 3, that a high priority access request has been presented in consequence of which they must mask their possible pending low priority access request, until the high priority request has been carried out.
Going on with the unit 24 description, it will be noted that lead 11 is coupled through receiver/inverter 34 and NOT circuit 35 to the clock input of a J-K flip-flop 36 (flip-flop ASCY). This is because, in the preferred embodiment, lead 11 is used for a bidirectional exchange of signals to minimize the number of BUS leads as described in Italian Patent Application Ser. No. 23037 A/78 filed on May 5, 1978 by the assignee of the present application. As described in this prior application and reconsidered later on, GAM 5 answers to the requesting processor, when it decides to allow such processor to access the BUS, dropping again BURE signal on lead 11 to logic level 0. This causes flip-flop 36 (ASCY) to be set. The set is conditioned by the presence of a logic level 1 at the J input which is connected to the output of OR 80. It is however clear that the answer to such processor could be sent on a separate lead other than lead 11.
The direct output Q of flip-flop 36 is connected to a first input of a three input NAND gate 37 whose output is connected to the clock input of a J-K flip-flop 38 (flip-flop EXCY). Enabling signals which will be considered later on are applied at the second and third input of NAND gate 37. They enable the signal transfer from output Q of flip-flop 36 to the clock input of flip-flop 38 only when the BUS is really free. In fact, in the described embodiment, to maximize the information transfer rate on the BUS, the cycle assignment operations overlap the execution and the finishing of the possible previous cycle. Then, when flip-flop 36 (ASCY) is set, once the execution of the possible previous cycle is completed, flip-flop 38 is set and BUS occupation and information transfer start. The Q output of EXCY is connected to the clock input of two J-K flip-flops 39 and 40 (ASCY-HP and ASCY-LP). Said flip-flops 39 and 40 receive at the J input the signal present at direct output Q and at inverted output Q of flip-flop 25 (BURE-HP), respectively, indicating or not the high priority state in which the dialogue unit 24 is. Depending on the state of flip-flop 25, one of two flip-flops 39 and 40 is set. The Q output of EXCY is further connected to the input of a delay line 41 having output taps 42, 43, and 44. Therefore the signal trailing edge at the Q output of EXCY (consequent to the setting of EXCY) propagates along such line. Output 42 is connected to the input of a NOT circuit 45. Output 43 and the NOT circuit 45 output are connected to the inputs of a two input NAND gate 46. When the delay line is inactive (EXCY reset), the outputs 43 and 42 are at logic level 1; and the NOT circuit 45 output is at logic level 0. Thus, the NAND gate 46 output is normally at logic level 1. When a trailing edge propagates along line 41, output 42 drops to a logic level 0 before output 43. Thus, the NOT circuit 45 output rises to logic level 1, while output 43 is still at logic level 1, and a pulse at logic level 0 appears at the NAND gate 46 output.
The NAND gate 46 output is connected to the reset input of flip-flop 36 (ASCY) by means of lead 47 and to the reset input of flip-flop 26 (BURE-LP) and flip-flop 25 (BURE-HP) through an OR gate 28 and an OR gate 58 respectively. A second input of gate 28 is connected to the Q output of flip-flop 40 (ASCY-LP), and a second input of gate 58 is connected to the Q output of flip-flop 39 (ASCY-HP). Therefore, when flip-flop 40 is reset, a logic level 1 is permanently applied to the reset input of flip-flop 26 which cannot be reset by a signal on lead 47 dropping to logic level 0. Likewise, when flip-flop 39 is reset, a logic level 1 is permanently applied at the reset input of flip-flop 25 which cannot be reset by a signal on lead 47 passing to logic level 0.
The output 44 of delay line 41, is connected to the clock input of flip-flop 49 (PROCO). Therefore, with the set of flip-flop EXCY the following events occur: (a) either flip-flop 39 or 40 is set, depending on the state of flip-flop 25 (BURE-HP); (b) flip-flop 36 (ASCY) is reset; flip-flop 25 is reset if it was previously set and if flip-flop 39 had been set immediately before; otherwise flip-flop 25 stays in reset; flip-flop 26 is reset if flip-flop 40 had been set immediately before; otherwise its state does not change; (c) flip-flop 49 (PROCO) is set. The direct output Q of flip-flop 49 (PROCO) is connected to the input of an open collector inverter/driver 50 whose output is connected to system BUS lead 8 to apply the PROCOL signal thereto. Lead 8 is connected to a +V voltage source through a resistor 51; therefore it is normally at logic level 1, but it goes to a logic level 0 when flip-flop 49 is set. It is to be noted that if PROCOL was previously at logic level 0, the set of flip-flop 38 (EXCY) and 49 (PROCOL) would have been prevented till PROCOL should have gone to logic level 1. In fact, lead 8 is connected to the input of an inverter/receiver 52 whose output is connected to the input of a NOT circuit 53. The output of NOT circuit 53 is connected to the second input of NAND gate 37, already considered, whose output controls the set of flip-flop 38. Therefore, the set of flip-flop 38 is conditioned (inter alia) by the presence of logic level 1 on lead 8 (PROCOL).
The NOT circuit 53 output is further connected to the clock input of J-K flip-flop 54 (MASK). Such flip-flop receives at its J and K inputs two signals obtained from lead 10 (CHART). In fact, lead 10 is connected to the input of a receiver/inverter 55, whose output is directly connected to the J input of flip-flop 54 and to the K input of the same flip-flop through a NOT circuit 56. The flip-flop MASK is normally reset, but every time the signal PROCOL goes to logic level 0 such flip-flop may go to a state defined by the level present over J and K inputs. Then it will be noted that, if the signal CHART on lead 10 is at logic level 1, that is no high priority BUS access request is present in the system, the J input is at logic level 0 and the K input at logic level 1. The flip-flop MASK stays then in reset. Whereas, if the signal CHART is at logic level 0, the flip-flop MASK is set. The MASK inverted output Q is connected, as before said, to the second input of AND gate 33 as well as to the second input of OR gate 80. Therefore, when MASK is set, AND gate 33 is inhibited and any BUS access request coming from flip-flop 26 (BURE-LP) is inhibited or masked. Likewise, if flip-flop 25 (BURE-HP) is reset and MASK is set, the possible clock pulses applied to the clock input of flip-flop 36 (ASCY) leave such flip-flop in reset.
It is to be noted that the logic level 0 on lead 10 may be imposed by any one of the several system processors, and that such level is detected at the same time by all system processors, which all place their corresponding flip-flop MASK in set. Therefore, if low priority access requests were present on system leads such as 11, 12, and 13, these access requests are masked or inhibited untill flip-flop MASK is reset in each processor. On the other hand, the dropping to 0 of the logic level present on leads 11, 12, or 13 is not interpreted within each processor as a BUS assignment, because the state of flip-flop 25 (BURE-HP) and of flip-flop 54 (MASK) inhibit the set of flip-flop 36 (ASCY). It is to be noted that in this masking process, GAM 5 and the relative priority assignment network do not intervene at all and ignore completely the difference between high and low priority level. It is to be further noted that, if the low priority BUS access requests are masked, the possible high priority access requests are not masked. Therefore, more high priority requests may be present at the same time on BUS leads as 11, 12, and 13. Then, it can be concluded that leads 11, 12, and 13 are used for transmitting access requests with two different priority levels and that such two levels are mutually exclusive. In fact, high priority access requests cause the masking of any possible low priority request, while the presence of a low priority access request presupposes the absence of high priority access requests.
In the embodiment here described, there is only a predetermined time interval in which requests with two different priority levels may be present at the same time; such time interval is the one elapsing between the signal CHART generation (totally asynchronous) at level 0 on lead 10 and the dropping of signal PROCOL to logic level 0 on lead 8 with the consequent set of flip-flop MASK. Later on the reasons why the set of flip-flop MASK is deferred will be explained.
In order to conclude the description of the priority selection and dialogue unit 24, the reset circuits used for resetting flip-flops 54 (MASK), 38 (EXCY), 49 (PROCOL), 39 (ASCY-HP), and 40 (ASCY-LP) will be described. Lead 7 ends in each processor with a receiver/inverter 59. Lead 7 is normally held by GAM 5 at logic level 1. This level drops to 0 near the end of a BUS occupation cycle and rises again to 1 at the cycle end. The output of receiver/inverter 59 is connected to the input of a delay line 60 having output taps 61 and 62. Intermediate tap 61 is connected to a first input of a two input OR gate 64. Tap 62 is connected to the input of a NOT circuit 63, whose output is connected to the second input of OR gate 64. The output of OR gate 64 is connected to the reset input of flip-flops 38, 49, 39, and 40. When delay line 60 is at rest (ENCY at logic level 1) its outputs are at logic level 0 and the output of OR gate 64 is at logic level 1. When ENCY falls to logic level 0, the rising edge at the receiver 59 output propagates from the input to the outputs of line 60 bringing output 61 to logic level 1 before output 62 goes to 0. The output of OR gate 64 remains at 0. On the contrary, when ENCY rises again to logic level 1, it is easy to see that a short pulse at logic level 0 appears at the OR gate 64 ouput. Such pulse is suitably delayed relative to the ENCY leading edge and resets those of flip-flops 38, 49, 39, and 40 which were set. It is clear that only one processor at a time will have flip-flops such as 38 and 39 and one of flip-flops 39 and 40 set, but the ENCY command is clearly forwarded to all the processors.
The above description of the dialogue unit, even if this is not necessary for understanding the present invention, is completed with reference to flip-flops 39 and 40 and to the control function that the dialogue unit performs on the interface registers. It has been already said that Q output of flip-flops 39 and 40 is connected to an input of OR gate 58 and OR gate 28, respectively, for masking the reset of flip-flops 25 and 26 respectively. Direct output Q of flip-flop 39 is connected to the K input of a flip-flop 66, to the J input of a flip-flop 67 and to a first input of an AND gate 74. Direct output Q of flip-flop 40 is connected to the K input of a flip-flop 68, to the J input of a flip-flop 69 and to a first input of an AND gate 75. Flip-flops 66, 67, 68, and 69 indicate with their state the state of interface registers 14, 15, 16, and 17. Flip-flops 66 and 68 have their clock input connected to the output of a NOT circuit 70 whose input is connected to the output of a receiver/inverter 71. Flip-flops 67 and 69 have their clock input directly connected to the output of the receiver/inverter 71. The input of receiver 71 is connected to lead 9 on which a MECOL signal, normally at logic level 1, is received from GAM 5. Lead 9 is normally held at logic level 1 by pull up resistor 51A connected to voltage source +V. The set input of flip-flop 66 and reset input of flip-flop 67 are connected to the output of a two input NAND gate 72, which receives on its inputs the HP state signal and the MC microcommand, both coming from control unit 21. The set input of flip-flop 68 and reset input of flip-flop 69 are connected to the output of a two input NAND gate 73. NAND gate 73 receives on its inputs from control unit 21 the HP state signal and the MC microcommand.
When flip-flops 66 and 68 are in set, they indicate to control unit 21, through respective direct outputs ORBUZ-HP and ORBUZ-LP at logic level 1, that output registers 14 and 15 respectively have been loaded and they are busy. In fact, such flip-flops are selectively set by signals HP and MC, or HP and MC. Thus, when the processor wants access to the BUS, it provides to load the suitable information into register 14 or 15 (according to whether the request has a low or high priority level) and at the same time it sets one of two flip-flops 25 and 26 (BURE-HP, BURE-LP) and one of two flip-flops 66 and 68 (ORBUZ-HP, ORBUZ-LP). When the BUS is assigned to the requesting processor (flip-flop 39 or 40 set), the information in register 14 or 15 is transferred on DAC-BUS through TRISTATE circuits 18 or 19, respectively, which are enabled by the output of AND gate 75 or 74, respectively, (leads 77 and 76 respectively, FIGS. 2 and 4). AND gate 74 has its two inputs connected to the direct outputs of flip-flops 39 and 66 and enables TRISTATE circuits 19. AND gate 75 has its two inputs connected to the direct outputs of flip-flops 40 and 68 and enables TRISTATE circuits 18. Therefore, information is present on DAC-BUS since signal PROCOL is lowered until when memory 4 answers lowering signal MECOL (thus causing the reset of the one of the two flip-flops 66 and 68 which was set). Likewise, flip-flops 67 and 69, when set, having direct outputs connected to leads 78 and 79 respectively, at logic level 1, provide outputs to load registers 16 and 17 and give indication of that to the control unit. Such flip-flops are selectively set by the rising edge of the MECOL signal, which occurs when Memory 4 has put on DAC-BUS the data which are to be loaded into registers 16 or 17.
Having described in detail the dialogue handling and priority level selection unit of the several processors, it is now useful to describe the system memory unit 4 with particular reference to GAM 5 of said unit. This is shown in FIG. 5. Lead 11 is connected to the input of a receiver/inverter circuit 131, lead 12 is connected to the input of a receiver/inverter circuit 132, and similarly lead 13 is connected to the input of a receiver/inverter circuit 133. Outputs of receivers 131, 132, and 133 are coupled both to as many inputs of a NAND gate 135 and to data inputs (D1, D2, D3 respectively) of a register 134. The output of NAND gate 135 is connected to an input of a two input AND gate 136. AND gate 136 receives to a second input, through lead 137, an enabling signal emitted by output Q of a J-K flip-flop 138. The output of AND gate 136 is connected to the input of a multitapped delay line 139, as well as to the clock input of register 134, through lead 140. The first output tap of delay line 139 is connected to the input of an inverter NOT circuit 141, whose output is connected to the SET input of J-K flip-flop 138. A second tap of delay line 139 is connected to the input of a NOT circuit 142, whose output is connected to the SET input of a J-K flip-flop 143. Direct output Q of flip-flop 143 is connected through lead 144 to the enabling input of three inverter/driver NAND gates 145, 146, and 147. The outputs of such three inverters/drivers 145, 146, and 147 are connected, respectively, to leads 11, 12, and 13. The signal input of three inverters drivers 145, 146, and 147 is connected respectively to three outputs U1, U2, and U3 of an exclusion logic matrix or priority network 148. The inputs of priority network 148 are coupled to the outputs O1, O2, and O3 of register 134.
In FIG. 5, the priority network comprises three NOT circuits 149, 150, and 151 and two AND gates 152 and 153 with three and two inputs, respectively. Output O1 of register 134 is connected through inverter 151 to output U1 of network 148. In turn, U1 is connected to the signal input of inverter/driver 145. Output O1 is also connected to a first input of the two AND gates 152 and 153. Output O2 of register 134 is connected through inverter 150 to a second input of AND gate 153, whose output U2 is connected to the signal input of inverter/driver 146. Output O2 is also connected to a second input of AND gate 152. Output O3 of register 134 is connected through inverter 149 to the third input of AND gate 152, whose output U3 is connected to the signal input of inverter/driver 147. The function of the exclusion logic matrix or priority network 148 is the one of assigning a relative priority to the memory access requests received by several processors through leads 11, 12, and 13 and of enabling the output from the network of the request with higher priority in case of several simultaneous requests. The priority network shown assigns for instance higher priority to access requests coming from processor 1 through lead 11, intermediate priority to access requests coming from processor 2 through lead 12 and lower priority to requests coming from processor 3 through lead 13. It can be noted that a signal at logic level 0 present on terminal O1 is transferred to output U1, where it appears in inverted form (because of NOT circuit 151), that is as a signal at logic level 1, without any conditioning. On the contrary, a signal at logic level 0 present on terminal O2 is transferred to output U2, only if a signal at logic level 1 is present at the same time to terminal O1 ; such signal at logic level 1 indicates that an access request with greater priority is not present. Likewise, a signal at logic level 0 present on terminal O3 is transferred to output U3 only if a signal at logic level 1 is present at the same time on both terminals O2 and O1. Terminals O1, O2, and O3 are coupled to the outputs of the register 134 cells, corresponding respectively to inputs D1, D2, and D3 and storing access requests received on leads 11, 12, and 13, respectively, as information at logic level 0. The operation of the memory interface circuits hitherto described is therefore clear: when a processor, for instance processor 2, wants to access the memory it rises to 1 the logic level of signal present on lead 12. Therefore the output of receiver/inverter 132 falls to logic level 0 and the output of NAND gate 135 rises to logic level 1. If AND circuit 136 is enabled because J-K flip-flop 138 is reset (as will be seen later on, this means that memory cycles are not already in progress), logic level 1 is transferred to the output of AND gate 136 and it activates the loading of register 134 through lead 140. Therefore logic level 0 present at the output of NAND gate 132 is loaded into the register together with the logic level present to the output of the other NAND gates 131 and 133. At the same time, logic level 1, present to the output of AND gate 136, is applied to delay line 139 and propagates along such line. When logic level 1 reaches the first tap, the output of NOT circuit 141 falls to logic level 0 and J-K flip-flop 138 is set. Thus, output Q of flip-flop 138 falls to logic level 0, and this has the effect of inhibiting AND gate 136. Therefore the possible and following access requests are not transferred to the output of AND gate 136 and then taken into account until flip-flop 138 is reset again. When logic level 1 which propagates along delay line 139 reaches the second tap, flip-flop 143 is set too, through NOT circuit 142. Thus, direct output Q of such flip-flop rises to logic level 1 enabling the AND/DRIVERS circuits 145, 146, and 147. The access request with greater priority among the ones memorized before by register 134 has been in the meantime presented to the output of the priority network 148 as logic level 1. Supposing logic level 1 is present at output U2, the output of the open collector NAND DRIVER 146 falls to logic level 0. Therefore logic level 1 present on lead 12 is forced to 0, as answer and acceptance of the access request. At this point, it is to be borne in mind that flip-flops 138 and 143 are in set, that is they have not been put in initial rest condition. However, when the processor whose request has been accepted receives the acceptance answer, it brings to logic level 0 the signal PROCOL on lead 8, thus indicating that it really accesses the memory.
Logic level 0 present on lead 8 is received by the memory through receiver/inverter 154, whose output rises to logic level 1. The output of receiver/inverter 154 is connected, through lead 155, to an input 156 of a memory command logic block, represented by block 157, and activates it. Details of block 57 are not represented, because they are beyond the purpose of the invention and are not necessary for understanding it. Block 157 also receives through DAC-BUS 6 an information set representative of commands (for instance, write/read, diagnostic test), and of memory addresses, of data to be written in the memory. The DAC-BUS, which is bidirectional, will be used also for sending back to the requesting processor memory state signals and the readout data. DAC-BUS is connected through a receiver/inverter set 101 to inputs of an input register set 102 (I-REG.). Another output register set 103 (O-REG.) in the logic block 157 has its outputs connected to inputs of a tristate NAND/DRIVER set 104, whose outputs are connected to DAC-BUS 6. As soon as logic block 157 receives the signal at logic level 1 on lead 155, it allows the loading of registers 102 and starts the memory operations defined by the content of such registers. At the same time logic block 157 produces on output lead 105 a signal at level 1, indicating the beginning of a memory cycle. Lead 105 is connected to the input of an inverter/driver 106 whose output is connected to lead 9 of the BUS. Therefore signal MECOL on such lead falls to logic level 0 and informs the processor which has received access to the BUS that the memory cycle has started and that the information present on DAC-BUS can be removed. In fact, as already seen with reference to FIG. 4, signal MECOL at 0 causes the reset of flip-flop 66 or 68 and the inhibition of driver set 18 or 19 (FIG. 2). When the requested operation is completed (for instance, in case of data reading), such data are loaded together with other useful information into register set 103 (O-REG.); logic block 157 enables the drivers set 104 to transfer such data and information on DAC-BUS and at the same time it lowers again to 0 the signal present on lead 105. Signal MECOL on BUS lead 9 rises to 1. As already seen, this has the effect of setting flip-flop 67 or 69 (FIG. 4) of the processor to which the cycle has been assigned and of enabling the loading of information present on DAC-BUS into register group 16 or 17 (FIG. 2). The output of receiver/inverter 154 is connected through inverter 160 to the clock input of flip-flop 143. Therefore as soon as PROCOL falls to logic level 0, the output of inverter 160 falls to logic level 0 and flip-flop 143 is reset. Consequently the logic level at the direct output Q of such flip-flop falls to 0 and NAND/drivers 145, 146, 147 are inhibited so that their outputs are disconnected from ground and resume again the normal rest state (it is to be recalled that elements 145, 146, and 147 are of the "open collector" type).
At the end of the memory cycle or preferably some time before (the reasons will be stated later on), the memory command logic block 157 produces on output lead 161 a cycle-end signal at logic level 1. Such signal is applied through lead 162 and inverter 163 to clock input of flip-flop 138 and resets it, thus allowing the transfer of new or still pending access requests through AND circuit 136. Moreover, the signal on lead 161 is sent by means of lead 164 to the input of the inverter/driver 165 whose output is connected to BUS lead 7. Then signal ENCY on lead 7 falls to logic level 0, and it signals to the system processors that the memory cycle in progress is ending. Signal ENCY is suitably held at logic level 0 until the end of the memory cycle, that is it rises to 1 when the memory is ready to begin a new cycle. As before described, the reset of flip-flops 38 and 39 or 40 and 49 of the dialogue unit in the processor to which the cycle had been assigned occurs with ENCY rising again to 1.
It is to be noted that in the previous description of memory circuits 4 and of GAM 5, possible connections with BUS lead 10 or possible effects of the signal CHART present on such lead have not been mentioned. In fact signal CHART is totally invisible to GAM 5 and to memory 4. Therefore, GAM 5 ignores completely whether the requests presented by several processors on leads 11, 12, 13 have a low or high priority level: it recognises only the access requests and assignes to such requests a fixed relative priority, for which lead 11 (and therefore processor 1) has higher priority relative to leads 12 and 13 (and therefore relative to processors 2 and 3) and lead 12 (and therefore processor 2) has higher priority relative to lead 13 (and therefore to processor 3). This is also true for N processors (N>3) with an obvious extension and modification of the priority circuits. Conversely, there are several processors which are just recognising if one of them at least has presented a high level priority access request; and they mask themselves, that is each of them inhibits the transfer on interface leads of its possible low priority access requests until the high priority signal (CHART at logic level 0) is removed. Therefore each processor has in its dialogue unit means comprised by flip-flop 25 for generating a high priority access signal which is suitably transferred on a single communication lead for all processors as well as means substantially comprised by flip-flop 54 (MASK) which, when signal CHART is detected, mask possible low priority access requests which they have already presented or intend to present to GAM 5.
This embodiment allows for considerable structural simplifications and cost reductions and offers a greater versatility compared to the prior art. In fact, the problem of assigning the access to a common BUS as a function of two distinct priority levels might be solved by providing that each processor send on two separate leads access requests with two distinct priority levels. This requires the doubling of leads used for sending access requests and involves therefore a not indifferent tradeoff as to cost of cables, connectors, driving and receiving circuits. In addition, the priority network in GAM 5 should be accordingly designed and would require more than a doubling in number of logic components for its embodiment.
Having described the circuital aspects of a preferred form of embodiment of the invention and the operation of such circuits, it is useful, for a better understanding of the invention, to reconsider in the whole the working of the priority selection and dialogue unit of the various processors with reference to the timing diagrams of FIG. 6. Diagram BURE 1 shows the logic level present on lead 11 at the output from processor 1. Diagram BURE 2 shows the logic level present on lead 12 at the output from processor 2. Diagram BURE 3 shows the logic level present on lead 13 at the output from processor 3. It is recalled that the dialogue unit circuits of processors 2 and 3 are indentical to the dialogue unit circuits of processor 1 described with reference to FIG. 4. Diagram CHART shows the logic level present on lead 10. Diagram MASK shows the logic level present at the output Q of flip-flop MASK of the several processors, as for instance flip-flop 54 of processor 1. Diagram PROCOL shows the logic level present on lead 8. Diagram ENCY shows the logic level on lead 7. Diagram MECOL shows the logic level present on lead 9. Diagram OUT EN1 shows the logic level present at the output of AND gates 74 or 75 of the dialogue unit of processor 1. Diagram OUT EN3 shows the logic level present at output of the AND circuits such as 74 or 75 but belonging to processor 3. Diagram DAC-BUS shows the DAC-BUS state. Diagram DR 1 shows the logic level present at the output of flip-flop 67 or 69 of FIG. 4 belonging to processor 1. Diagram DR 3 shows the logic level present at the output of processor 3 flip-flops corresponding to processor 1 flip-flops 67 and 69. The chaining arrows from edge to edge of the several diagrams show the chaining of the events.
At an initial time t0 processor 1 produces a low priority access request: register 14 (FIG. 2) is loaded and flip-flops 26 and 28 are set. Because MASK is at logic level 1, BURE 1 rises to logic level 1 and propagates across lead 11. When BURE 1 is received by GAM 5, it activates through logic elements 131, 135, and 136 the loading of register 134, the delay line 139, the set of flip-flop 138 and finally the set of flip-flop 143 which enables the several outputs of logic elements 145, 146, and 147. The output of inverter/driver 145 is grounded and BURE 1 falls to level 0. Level 0 propagates across lead 11 and at time t3 it is received by processor 1, informing such processor that its request is accepted.
In the meanwhile at time t1 also processor 2 has presented a low priority access request bringing to level 1 signal BURE 2. Even processor 3 at time t2 presents an high priority request bringing to level 1 signal BURE 3 and bringing to level 0 signal CHART. In such case, the flip-flop corresponding to flip-flop 25 is set. Such events are completely asynchronous. It will be to be noted that MASK does not fall to 0 at the same time of CHART. Should this occur, BURE 1 would go to level 0 at time t2 and at the same time flip-flop 36 (ASCY) would be locked and made insensible to trailing edge of BURE 1. Such action would interfere with the decision taken before by GAM 5 of acknowledging the request of processor 1 and with the signalling produced by GAM 5 lowering BURE 1. In order to prevent such interferences it is necessary to defer the masking action at a time known by all processors in which it is sure that BUS assignments are not in progress because is such time the BUS has been already assigned. Such time coincides with the falling to 0 of signal PROCOL. It is to be noted that such problem occurs only because in the described preferred embodiment a single lead is used for transferring from processor to GAM an access request and for transferring from GAM to processor an accepted request signal as it has been clearly shown in the above mentioned Italian Patent Application. On the contrary, it is perfectly possible to use two separate leads for the two functions in which case the masking action could be immediate. The circuit changes required for such case are obvious to the expert in the art.
In continuation of the description, the fall of BURE 1 sets flip-flop 36 activating the BUS occupation. In order, first flip-flops 38 and 40 are set, then flip-flop 26 reset and flip-flop 47 set. At time t4, OUT EN1 rises to level 1 allowing the transfer of information from register 14 onto DAC-BUS (time t5). Logic level 1 on the DAC-BUS diagram shows that meaningful binary information is present on DAC-BUS.
When flip-flop 49 is set, PROCOL falls to level 0 (time t6). This causes in all processors the set of the flip-flop corresponding to 54 in processor 1, since CHART is at 0; and consequently it causes also the passage to 0 of MASK and the masking of BURE 2, which indicates a low priority request. On the contrary BURE 3 is kept at level 1 because it refers to a high priority request. When GAM 5 receives signal PROCOL at 0, it resets flip-flop 143, loads registers 102 with information present on DAC-BUS and lowers signal MECOL to 0 (time t9) starting a memory cycle (or more generally operations specified by the received information). When processor 1 receives MECOL at level 0, flip-flop 68 is reset and signal OUT EN1 (time t10) falls to 0 removing the information from DAC-BUS. In the other processors MECOL produces no effect.
Near the memory cycle end, GAM 5 lowers signal ENCY to 0 (time t12). At the same time GAM 5 reset flip-flop 138 (FIG. 5) and allows the recognition of pending access requests and the loading of register 134. Because the low priority access requests are masked (particularly BURE 2), BURE 3 is recognized (time t13) as being at logic level 1 and driver 147 is grounded lowering BURE 3 to level 0. Such operation occurs before the memory cycle is ended, so that the propagation time of signals in the priority network and associated circuits, and then along leads 11, 12, and 13 up to the processors, overlaps the cycle already in progress. As a result, the selected processor will be already prepared to access the BUS without delay from the beginning of the new cycle. Near the memory cycle end, GAM 5 raises signal MECOL to 1 (time t14) and at the same time it allows the transfer of the information contained into register 103 (for example data readout from memory) on DAC-BUS. In processor 1, the rising to 1 of MECOL causes the set of flip-flop 69 with consequent loading of the information present on DAC-BUS into register 17. Meanwhile, the new fall of BURE 3 to 0 causes the set of flip-flop ASCY corrisponding to 36 in processor 1; such flip-flop is not locked by MASK being at level 0, because its J input is held at level 1 by a flip-flop corresponding to 25 in set (time t14). The set of ASCY does not act immediately on the flip-flop corrisponding to 38 because the cycle in progress is not terminated yet (PROCOL and ENCY are still at level 0).
At the memory cycle end, GAM 5 again raises ENCY to level 1 and it rids DAC-BUS of present information (time t15). As soon as processor 1 receives the rising edge of ENCY flip-flops, 38, 49 and 40 are reset; and PROCOL rises again to 1 (time t16). The new rising of ENCY does not have any effect on the other processors. As soon as PROCOL rises again to 1, processor 3, which has its flip-flop corresponding to 36 in set, sets the flip-flops corresponding to 38 and 39, then resets the flip-flop corresponding to 25 and sets the flip-flop corresponding to 49. Therefore in order: (a) OUT EN3 rises to 1 and the information to be sent to GAM 5 is loaded on DAC-BUS; (b) signal CHART rises again to 1 (since in the example only processor 3 was imposing the condition CHART to 0 with its flip-flop corresponding to 25 in set); (c) finally PROCOL falls again to 0 (time t17).
The fall to 0 of PROCOL resets flip-flop MASK corresponding to 54 in several processors, because the previous return to 1 of CHART applies now to J and K inputs a logic 0 and a logic 1 respectively. MASK goes again to logic level 1; and it causes signal BURE 2 at logic level 1, masked previously, to appear again on lead 12. The fall of PROCOL received by GAM 5 activates the memory cycle. Therefore MECOL is brought to level 0; this causes the reset of the flip-flop corresponding to 66 in processor 3, the fall to 0 of OUT EN3, and the removal from DAC-BUS of the information therein.
Meanwhile, in a totally independent and asynchronous way with respect to the dialogue between processor 3 and GAM 5, the assumption is made that processor 1 presents another access request to the BUS by raising signal BURE 1 to 1 and resetting at the same time its flip-flop 69. Near the memory cycle end, the fall of ENCY and the consequent reset of flip-flop 138 in GAM 5 produces the recognition of pending access requests and the assignment of the following cycle to the request with higher priority, in such case BURE 1. Then the above explained events occur again in memory 4 and in processor 1.
It is assumed now that, meanwhile, in a totally independent and asynchronous manner, processor 2, which had already presented a low priority access request during the course of its working, requires now a high priority access. Therefore processor 2 sets its flip-flop corresponding to 25, thus lowering to 0 signal CHART (time t19).
On the other hand, because BURE 2 is already at level 1, no level changes occurs on such lead.
Before the following return of ENCY to 0 (time t20) and then before the recognition of pending requests in GAM and the BUS assignment to the requesting processor with higher priority, the assumption is made that both processor 3 and processor 1 present a low priority access request. High and low priority requests presented by all processors are present with the ENCY fall, since MASK is still at logic level 1. Therefore the following cycle is assigned to processor 1 which has greater priority (time t21); but with the following fall of PROCOL to 0 (time t22) flip-flop MASK of several processors is set, and MASK goes to level 0, so masking the pending request of processor 1. Then the only high priority requests (BURE 2) appear on leads 11, 12, and 13. Therefore the following cycle is assigned to processor 2; and during the dialogue, the several flip-flops and the register involved in BUS access with high priority level are reset. On the other hand, the flip-flops and the registers involved in BUS access with low priority level stay set in processor 2, because the corresponding request has not been accepted yet. Once the cycle assigned to processor 2 for the high priority access request is ended, if in the meanwhile no other high priority access requests or a low priority access request of processor 1 (which has greater priority for assumption) are presented, the low priority request of processor 2 will be finally honored.
Having described a preferred form of embodiment of the invention and its way of operating, it is convenient to stress that many various changes can be made to such form of embodiment without departing from the scope of the invention. For instance, as above said, separate leads for each processor may be used for sending access requests and for receiving the related access grant. Likewise, it is possible to consider systems with more than two priority levels having therefore intermediate masking levels. Likewise, it is possible to consider systems with two or more priority levels which are used in part by part of the system processors. In other words some processors or system units may send access requests with one priority level. Such changes are only exemplary changes.
|Cited Patent
|Filing date
|Publication date
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|Communication arrangement in data processing system
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|Oct 14, 1969
|Gen Electric
|Apparatus providing access to storage device on priority-allocated basis
|Aug 24, 1967
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|U.S. Classification
|710/116, 710/264
|International Classification
|Cooperative Classification
|European Classification


text:
Bagaz OuJepara, ID
I love creat some voices.. Ita so much fun
English (North American), English
North American
Child, Middle Aged, Senior, Teen, Young Adult
Special Skills
Audiobooks, Business, Cartoons, Documentaries, Educational, Internet, Jingles, Movie Trailers, Music, Podcasting, Radio, Telephone, Television, Videogames
I'm beginner for voice over, but u have to trust me I can work faster than u think..why ? Because I love to change my voice and enjoying all my time for work,Wanna try ?
I'm major in Animation and I know that process, so voices its very important to make animation life, this s my reason why im choosing to be voice over, I want to help u make a good voice on ur work.
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subset: commoncrawl


text:
George Clooney Declares His Love For Amal Alamuddin On Stage (AKA Further Evidence Of His Future Run For Public Office)
God, I am still SO ON TO YOU, George Clooney. While I'm sure the Cloons is totally, madly in love with fiancee Amal Alamuddin (why wouldn't he be? She's gorgeous, smart and accomplished, by all accounts) I've thought for awhile that his sudden embrace of long-term monogamy and the institute of matrimony (which he has long declared a disinterest in) has an ulterior motive — political power. I predicted a few months ago, shortly after Clooney and Alamuddin announced their engagement, that Clooney would at some point in the not-so-distant future declare his intent to run for public office, and that being married is part of his get elected strategy. And I stand by that! The American public prefers to vote for people who at least posture to have "traditional" values, like a stable family life, and George Clooney who parties with D-list actresses on his houseboat on Lake Como is less electable than George Clooney, devoted husband of a smarty-pants London lawyer. I'm not saying Clooney and Alamuddin aren't a legit couple, I'm just suggesting Clooney is performing his love in a different way than he has before for a reason. I mean, dudebro has never been one to talk about his relationships or significant others, yet earlier this week, while on stage accepting a humanitarian award, Clooney gushed about his bride-to-be, declaring his love and being all "I can't wait to be your husband" etc. etc. It's totally sweet, don't get me wrong, but mark my words, the Clooney Campaign has begun. [Dlisted]


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Prince William and Kate Middleton Might Be Coming to New York
Most Popular
THE BRITISH ARE COMING, THE BRITISH ARE COMING! Specifically, Prince William and maybe Kate Middleton. According to People, Wills is scheduled to make a trip to NYC later this fall, and depending on her health, Kate might join him. Though she's had to cancel her previously planned trips due to hyperemesis gravidarum, the Duchess of Cambridge and the royal staff are apparently keeping an "open mind" and taking her schedule "day by day," sources tell People. SO YOU'RE SAYING THERE'S A CHANCE!?
Advertisement - Continue Reading Below
Though the palace won't confirm any plans (pleaaaase), a spokesperson said an announcement "will be made in due course" if the tour does happen.
So, here are the questions we have: What will she wear? Will she bring George? Will Harry be joining? WILL SHE INTRODUCE US?
Via ELLE
Related Links:
25 Stunning Photos of Kate Middleton
Kate Middleton's Hyperemesis Gravidarum Isn't Just Morning Sickness
More from Marie Claire:


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Baghdad: From the battlefield near Baiji, an Islamic State jihadist fired a heat-seeking missile and blew an Iraqi Army Mi-35M attack helicopter out of the sky this month, killing its two crew members.
Days later, the Islamic State released a chilling series of images from a video purporting to capture the attack in northern Iraq: a jihadist hiding behind a wall with a Chinese-made missile launcher balanced on his shoulder; the missile blasting from the tube, its contrail swooping upward as it tracked its target; the fiery impact and the wreckage on a rural road.
The helicopter was one of several Iraqi military helicopters that the militants claim to have shot down this year, and the strongest evidence yet that Islamic State fighters in Iraq are using advanced surface-to-air missile systems that pose a serious threat to aircraft flown by Iraq and the United States-led coalition.
As the counteroffensive against the Islamic State enters a more aggressive phase in Iraq, allied air strikes will also intensify.
US officials say they expect that the push will bring out more proof of the jihadists' anti-aircraft abilities, with potentially serious consequences for how the Iraqis and their coalition partners wage their war.
"Based on past conflicts, [the missiles] are game changers out there," said one senior US military official, who spoke on condition of anonymity.
The proliferation of anti-aircraft weaponry has also heightened concerns about the vulnerability of Iraq's airports, particularly Baghdad International Airport, the country's most important transportation hub and a lifeline for military supplies and reinforcements to Iraq.
Signalling its intent to challenge US supremacy in the skies, the Islamic State recently published an online guide describing how to use shoulder-fired missiles to shoot down an Apache attack helicopter, one of the most fearsome weapons in the US Army's conventional arsenal.
"Choosing the launching spot: Preferably somewhere high," the guide says in Arabic. "The roof of a building or a hill with a solid surface to prevent the appearance of dust following launching."
The authors urged "strong confidence in God and composure", and certainty "that this operation will cause a disaster to the foes and destroy their arrogance".
The US has stationed about six Apaches at Baghdad International Airport. However, they have been used rarely in the aerial campaign against the Islamic State, in part because of worries about their vulnerability to ground fire and a lack of US search and rescue teams in Iraq that could respond to downed crews.
The concerns also reflect the White House's insistence on limiting the number of American troops in Iraq and their exposure to hostile fire.
This month, Apaches entered the battle for the first time, in co-ordination with US Air Force jets, to carry out four air strikes on a large Islamic State force north-east of Fallujah, in the sprawling desert and agricultural province of Anbar.
The militants have established several strongholds there, and have continued to gain ground against Iraq's security forces in recent weeks.
Now, the Iraqi military is beginning to mount larger and more complex efforts around the country to retake territory from the Islamic State, including a counteroffensive that began more than a week ago to break the militants' stranglehold on a key refinery in Baiji, north of Baghdad.
The new phase will mean an increase in the frequency of combat missions by coalition aircraft, and will likely demand a greater use of lower-flying US attack helicopters and gunships, which have important advantages in urban warfare.
Since much of the most difficult fighting in the coming months is expected to unfold in the towns and cities of Anbar, US generals may be inclined to order more Apaches to support Iraqi ground troops. They may also make greater use of AC-130 gunships, a lumbering, propeller-driven plane bristling with cannons that circles at altitudes at the outer limits of some shoulder-fired missiles.
As Iraqi and US officials weigh the added risk to their aircrews and, potentially, to civilian aircraft, they are particularly concerned about the threat of shoulder-fired heat-seeking missiles, commonly known as Manpads, short for Man-Portable Air Defence Systems.
Syrian rebels have amassed multiple Manpad models since 2012, and the Islamic State has, generally, had little trouble acquiring any weapon used by Syrian rebels either through purchase or capture, military analysts say.
While the Pentagon's Central Command acknowledged this concern, it said it had no conclusive evidence yet that the Islamic State had such weapons.
The maximum ranges and altitudes of Manpads vary from system to system but they are, generally, used against low-flying aircraft, such as fixed-wing aircraft soon after take-off or shortly before landing, or helicopters.
Sunni militants in Iraq long maintained a limited, ageing stock of SA-7 Manpads, a ubiquitous Soviet-designed system that they periodically used during the American occupation from 2003 to 2011, said Charles Lister, a visiting fellow at the Brookings Doha Centre in Qatar.
However, since at late 2013, the Islamic State forces in Iraq appear to have acquired more sophisticated anti-aircraft missile systems, including the Chinese-made FN-6, originally provided by Qatar and possibly also Saudi Arabia to Syrian rebels.
In the images purporting to show the shooting down of the Iraqi attack helicopter, on October 3 in Baiji, the militant, a scarf wrapped around his face, was wielding a Chinese-made FN-6 missile system; apparently the first documented use of the weapon by Islamic State jihadists in Iraq, analysts said.
The militants claimed to have shot down several other Iraqi military helicopters this year, most recently a Bell 407 on a surveillance mission near Baiji on October 8.
"Judging by reports from Iraq, and, in particular, Anbar province, over the past three to four months, it would seem IS have been using Manpads far more frequently and more successfully than Syrian rebels have ever done," Mr Lister said.
An even greater potential concern was that militants might get their hands on SA-24s, a more sophisticated system that Russia recently sold to Iraq, and first showed up in militant videos in September, said Matthew Schroeder, a missile proliferation analyst at Small Arms Survey, an independent research project based in Geneva.
He said the SA-24s had a longer range than older models and use faster and more manoeuvrable missiles.
Newer systems also have a greater ability to hit targets from a wider range of angles, such as a perpendicular shot at a moving target like a plane on its approach to a runway.
As Iraqi and US officials have weighed the threats to their military aircraft, they have also taken steps to safeguard the nation's airports.
The protection of Baghdad International Airport, on the western edge of the capital, was of special concern, especially since the early summer when the Islamic State's advances in Anbar and on the western fringes of greater Baghdad brought them to within 24 kilometres of the airport.
New York Times


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Homework, homework, won't you go away? Oh, I'll never miss you when you are gone, in fact I'll sing of your demise! I-
Oh. Um, hey. I was just singing about how wonderful the demise of homework would be. Anyways… I'm updating! I finished this chapter in school the other day and had to post it.
PoisonIvy1998: I know, right? Just one word, and bam! Story!
Rawr52: More K-Unit! Only Eagle, but still…
DarthZ: Yeah! I'm glad you liked it.
ADayWithNoLaughterIsADayWast ed: Still love the name! And nigh means near.
So… new chapter! This one takes place after Scorpia Rising, Alex never left with the Pleasures, instead he joined MI6. Funny how most of mine are like that, huh? Also, ignore how Q-Unit just gives out info without much proof… doesn't make sense, but…
Alex Rider shuffled forward, his stocking feet making no sound on the tile floor. He paused, glanced around the corner, and waved his hand behind him. Director Tulip Jones, gadgeteer Smithers, and MI6 agents Tamara Knight –transferred from the CIA, Ben Daniels – ex-SAS, and Tom Harris – the junior agent there – moved forward. The Deputy Head of MI6 lead the way, gun in hand, prepared for anything.
- 15 minutes later –
Rose Rothman, daughter of Julia Rothman, stared angrily out the window of her helicopter at her demolished HQ. Somehow, during the hour she was gone, her prisoners – whom she had captured after 10 years of careful planning! – had escaped. On top of that, they found the explosives.
- three miles away –
Tom rolled on the ground, cracking up. The other people from MI6 watched him, barely keeping grins off their faces. Tom always made them laugh, and when they were off duty, it was ok. But after being kidnapped and escaping, they had to focus.
After another minute, Jones snapped, "Agent Harris! Collect yourself!"
Jumping to attention, the 25-year-old man calmed himself.
"Mrs. Jones?" Agent Daniels questioned. "What are your orders?"
"We are only twenty miles from Brecon Beacons," she noted. "We will go there and take command of two cars and 18 guns with extra ammunition. Then, we will o home in those cars. After organizing a raid, of course."
Tom bounced excitedly. "And explosives?"
Mrs. Jones nodded, but added, "In Agent Daniels' hands unless we are attacked."
Agent Harris made a face, but nodded.
Everyone else gave sighs of relief. Tom plus explosives equaled disaster.
Then, Alex and Ben gave gasps of horror as they realized were they were headed. Hell.
Five minutes later, Alex gave a sigh of annoyance as they walked on the highway. "Really? Do we have to be on the highway to Hell?"
Tom frowned. "Huh?"
"The old song," Ben explained. "And Brecon Beacons is Hell."
"Huh?" came again.
Alex groaned. "Remind me again how you became an agent?"
"Well, first-"
'Aha! A car!" Smithers interrupted, pointing at an army jeep driving down the highway.
Mrs. Jones smiled satisfactorily and stepped into the road, holding her hand out in the universal sign for stop.
- in the car –
Cheetah screamed, "Watch out!"
Falcon, who had been having a conversation with Bear, twisted around and, seeing the woman standing in the middle of the road, stomped on the brakes. Cobra and Bear squawked like chickens as their heads slammed into the seat in front of them. Cheetah pulled a face of annoyance as he pushed the passenger seat airbag back into the compartment and out of his face. Falcon breathed a sigh of relief when he saw the woman still standing, unharmed.
This all lasted until Bear, known for his short temper, saw the cause of everything and exploded out of the car, clutching his throbbing head.
"What do you think you were doing?!" He yelled at the woman, not even noticing that she didn't flinch, avert her eyes in shame, or take a step back. "You could have been killed! We could have been killed! And all because you didn't look both ways!"
This went on for a while until Alex lost his patience and yelled, "Calm yourself soldier!"
The leader of Q-Unit was shocked into silence. Falcon, Cobra, and Cheetah stopped laughing at Bear's outburst abruptly.
"Thank you, Agent Rider," the woman said calmly. Then, turning to the SAS unit, she snapped, "Names, unit and rank." When their mouths didn't move, she roared, "NOW!"
Rocketing to attention in record time, Bear saluted. "Bear of Q-Unit, Captain."
Cheetah quickly followed his leader's example. "Cheetah of Q-Unit, Medic Lieutenant."
"Falcon of Q-Unit, Soldier," the sharpshooter saluted.
The explosive expert also saluted and announced himself, "Cobra of Q-Unit , Soldier."
The woman, obviously of high rank now that they took her in, examined them before saying, "At ease."
The four SAS men of Q-Unit moved into a relaxed position.
Mrs. Jones stated, "Jones, Head of MI6."
Bear's mouth almost dropped in horror. He had been yelling at her!
"Agent Rider, Deputy Head of MI6," interrupted his thoughts.
"Agent Daniels, Senior Agent," a familiar voice said. This time, Bear's mouth did drop.
"Fox?" he cried.
The ex-SAS soldier nodded and grinned. "Good to see you again, Bear."
As said man opened his mouth to reply, a voice said, "Nice as this reunion is…" the new woman trailed off before stating, "Agent Knight, Senior Agent."
"Agent Harris, Junior Agent."
"Smithers, Gadgeteer."
Q-Unit took them in, and then Bear asked, "What are you doing here, and why did you stop us?"
Agent Harris opened his mouth to answer, beaming at them, when Agent Rider cut the man off. "We were in the area, making sure no one was doing anything illegal around the base. Unfortunately, someone is, so we need a faster ride to get there. Once there, we'll organize a raid and leave."
Falcon, the best of Q-Unit at uncovering lies, scrutinized Alex. The man stared back evenly. Eventually, Falcon nodded to Bear. His leader gave a sigh of relief as he motioned the MI6 people into the jeep. He did not want to say no the heads of MI6. Turning, he froze. How were they all going to fit?
- three hours later –
Eagle of K-Unit was mad. He had turned the sergeant's clothes pink and been caught. As punishment, he had gate duty. And everyone hated gate duty. You had to stand in a little hut that did nothing to block the cold. If someone came, you had to step out, rain or shine, to check their id. Plus, it was incredibly boring. You sat for hours on end with no entertainment, as hardly anyone came through.
Eagle was playing tic-tac-toe (hard when your by yourself) in the dirt when he heard the sound of a straining motor. Almost shouting to the heavens in joy, he hurried to the door. Laughing, he stared at the sight before him.
Falcon was driving. Next to him was Cheetah, who was sitting awkwardly between the front seats. Next to him was a young man and an older woman, sharing the passenger seat. In the back was Cobra and Bear, sharing the left seat. Next to them was another young man and a woman. Next to them was a large, bubbly man who was taking up the whole right seat. On the floor was a familiar man that Eagle couldn't place.
Bear growled, "Stop laughing, Eagle, and let us in."
Eagle continued to laugh for another minute, just to annoy the man, before saying, "Id, Bear. For all of you. Can't let you in without 'em."
Bear growled again but handed his over. So did everyone else. Eagle glanced at all of them before holding them under a scanner. 'Captain Bear, Q-Unit'. 'Medic Lieutenant Cheetah, Q-Unit'. 'Soldier Falcon, Q-Unit'. 'Soldier Cobra, Q-Unit'. 'Classified, Head of MI6'. Eagle started, glancing at the woman in the passenger seat. 'Classified, Deputy Head of MI6'. The guard looked up again, once more to that seat. 'Agent Harris, MI6'. 'Agent Knight, MI6'. "Agent Daniels, MI6'. 'Gadgeteer Smithers, MI6'.
- in car –
Ben stared at his old comrade, praying he didn't recognize him. He was also thankful that their ids were sewed into hidden pockets that Rothman hadn't found.
Ben watched as Eagle finally handed over their ids. "Go," he said, sighing. "But bring my case to the sergeant. Please. I'll be lucky if anyone else comes."
"We will, my friend," Cobra sighed. He understood where Eagle was coming from, having been there himself.
Bear shook his head, "Tough luck, Eagle. We can't, we have business to do." The leader then kicked the back of the driver's seat and Falcon, startled, put his foot on the gas.
Eagle cried out in despair as the car drove away. As he did, Ben laughed. The man still in K-Unit stopped abruptly, staring after the car, his mouth forming the name, "Fox?"
- Sergeant's office –
Sergeant Hayes looked up, startled, when his office door slammed open. He jolted to his feet and saluted when he saw who was coming in. "Mrs. Jones," he gasped. "You are unexpected, so I apologize for not being prepared –"
"I am taking over your troops for a few days, Sergeant," the Head of MI6 interrupted him.
"What?" The poor man was completely bewildered.
"Out," Jones said simply.
The sergeant exited the room – his office! – and met with a confused Q-Unit. "What is going on?" He demanded. "I've just been kicked out of my office! My office!"
Bear shook his head, "We met them on the road and gave them a ride here because they had discovered some kind of cult near here. That's all we know."
That knowledge grew only a little as time passed. This was because the spies stayed hold up in the sergeant's office. Occasionally they came out and gave orders, but that was it. As the orders grew, however, a picture began to form.
By the end of the third day, by which everyone was tired, the terrorists had been captured and the spies gone. Along with them were two cars, 18 guns, and extra ammo. The soldiers guarding the weapons shed had no idea how that happened.
Eagle, when he was finally relieved from guard duty at the gate after being forgotten till the second day after the spies left due to all the commotion and confusion – he was lucky to have taken enough food and water to last for weeks for a normal person's stomach, said only one thing before collapsing into sleep after learning what happened, "The trouble with spies is when they over occupy."
There! Finished. Not very good, but finished. Please review!


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Shawne Jackson
Shamonj always knew that she wanted to be a creative designer. So she decided to start her own company called Shamonj Gifts, LLC. She also dreamed of creating her own talk show so she created ShamonjTV1. As time went by Shamonj decided that she wanted to go back to school after fasting and praying. She enrolled at University of Phoenix and received her Masters in Science of Psychology. At that point in her life she realized that she wanted to do something more meaningful. She wanted to understand the human mind and understand and interpret people's behaviors. After graduating with her Master's Degree in Psychology she decided that she really wanted to become an counselor. She contacted Walden University because she wanted to get her Doctorates Degree in Counseling. However, a person in the admission office informed her that she would have to get a Master's Degree in Mental Health Counseling before she could get an PHD. She didn't let that stop her! She enrolled into Walden University and is currently working towards receiving her Master's Degree in Science of Mental Health Counseling.
Shamonj has written and published several books. Shamonj published a book titled "The Only One I Love", published in English and in French (paperback and electronically). Shamonj also published My Vision Journal which is a Journal that helps people to plan out their lives. Shamonj recently published a book titled The Lady Blue's Story written by Movie Geek. Shamonj has also recently published a book titled Inspiring Moments: Encouragement for the Soul written by Crystal H. Holdipp. Shamonj has also published several papers and plans to publish several other papers, books, and journals. Shamonj is currently working on her novel titled "The Power to Make A Difference". The Power to Make A Difference will be published in November. Shamonj is also working on publishing a book titled "The Meek Russell Story" which is a sequel to the Power to Make A Difference. Shamonj also plans to publish several books called "The Love of my Father", "Captured Image", "Love Thyself"and several other Novels. Shamonj plans to publish some non-fiction as well. She is currently working on some non-fiction as well titled "100 Reasons Singles Should Keep Their Legs Closed", "Christian Chronicles", "Christian, Family & Inspirational Films" , "Resources for Graphic Designers", "Shamonj Gifts' Blue Print For Success & Fulfillment" and many other titles.
Shamonj is a member of several organizations such as the American Counseling Association and The Association For Creative in Counseling Division. Shamonj plans to become an Licensed Mental Health Counselor starting her own private practice. She also plans to become a published author, motivational speaker, and a talk show host. After Shamonj gets her second Master's Degree, she plans to go back to college and receive her PHD in Counselor Education and Supervision.
Shamonj's biggest goals in life are to please God and to make a difference in the lives of people throughout the nation through words, pictures, multimedia and deeds.


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Eg. First FZR250R is done on all the first post, after 5 images the remaining images just appear as placeholders.
If you right click the image placholder and choose 'load in new tab' the image displays fine, thus not a failure with the source image or proxy being able to find it in cache.
My image proxy settings are;
Lifetime = 60 days
Refresh = 0 days
Cache max size = 10240 (Kb)
I see the same in the Image Proxy Log too .... after the first 5 or 6 records on the log page, the remaining images do not display/load. Click to open though, and it works fine.
Anyone know what the issue could be?


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- Description
This accent table has a found look with it's design and New York letting on the front. The table top lifts up revealing a storage space below. This table has a unique, vintage feel that will get people talking.Includes
1 CabinetDimensions
19"L x 16"W x 28"H
- Additional Information
Additional Information
SKU 12691186 GTIN N/A Finish N/A Collection N/A Assemble Length 19 Assemble Width 16 Assemble Height 28 Assembly Required Yes Material Wood Styles Traditional Color N/A Shipping Time 1-2 Weeks Free Shipping Yes
- Reviews
Disclaimer: Pictures displayed may include optional products not included in the price. Computer monitors often display color variations. Color swatches are shown if alternative colors are available. Please call us or email us if you have any questions!


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…that Paul Newman has passed away at age 83. My God, this sucks.
Sometimes when my father is at the wheel and I'm riding shotgun, we'll pass a county mountie writing out a ticket to some speeding scofflaw, and that will prompt me to remark (in my best Jackie Gleason impression): "What we're dealing with here is a complete lack of respect for the law." This is my father's cue to resurrect the famous line spoken by warden Strother Martin in Cool Hand Like (1967): "What we have here is…failure…to communicate." I've lost count how many times he and I have sat down and watched that movie—but it seems like every time he went channel surfing and discovered it on, say, AMC…well, it wouldn't budge until the movie was over.
In the NY Times obituary, they reprint one of Newman's most memorable observations: ''I was always a character actor. I just looked like Little Red Riding Hood.'' While I love Newman's earlier vehicles—The Hustler (1961), Hud (1963), Hombre (1967), Luke, Butch Cassidy and the Sundance Kid (1969), The Sting (1973)—I think the performances that came later in his career (Fat Man and Little Boy [1989], Nobody's Fool [1994]) had a great deal more nuance and depth. My all-time favorite Newman performance (and the one that should have nabbed him the Oscar, Ben Kingsley be damned) is in The Verdict (1982); his portrayal of drunk and disgraced attorney Frank Galvin, who reclaims his soul in a controversial trial involving the death of a woman at the hands of a negligent hospital staff, leaves me emotionally drained every time I see it. (Newman eventually won a "legitimate" Oscar for The Color of Money [1986], after collecting first an honorary statuette and later the prestigious Jean Hersholt Humanitarian Award for his charitable work.)
There's another great Newman quote in the Times obit; a comment on his long-term marriage to wife Joanne Woodward, with whom Newman appeared in several films and who also starred in several vehicles directed by her husband (including the Oscar-winning Rachel, Rachel [1968]). "I have steak at home—why go out for hamburger?" (I'll bet if a lot of couples sat down and really meditated on that phrase the divorce rate would precipitously plunge in a good way.)
Faithful TDOY readers might be aware that I'm the only member of my family who really has an affinity for classic movies (well, my Mom sometimes does—as long as it's one of the Universal horror films or Casablanca). My father refuses to watch anything in black-and-white (unless there are cowboys and injuns involved) and sister Kat says "classic movies" in the same tone of voice one would use if the words "Nazi Germany" came tripping off one's tongue. But one night, my other sister (Debbie) called me up when I was still living in Morgantown, WV and she asked me what I was doing; I replied that I was watching Paul Newman in Somebody Up There Likes Me (1956).
"Hmm," was her response. "I haven't seen that one…I'll have to check it out sometime." I thought this might be her way of making idle chit-chat, but she told me she really liked Newman a lot.
For that…and for so many other reasons…R.I.P, Mr. Newman. You will be sorely missed.


text:
Integral Packaging of High Temperature Sensors for In-Situ Measurements
Award Information
Small Business Information
Makel Engineering, Inc.
CA, Chico, CA, 95973-9064
Principal Investigator
Name: Susana Carranza
Title: Ms.
Phone: (512) 589-0718
Email: email@example.com
Title: Ms.
Phone: (512) 589-0718
Email: email@example.com
Business Contact
Name: Darby Makel
Title: Dr.
Phone: (530) 895-2771
Email: email@example.com
Title: Dr.
Phone: (530) 895-2771
Email: email@example.com
Research Institution
Name: Stub
AbstractOne of the key requirements to efficiently and safely operate advanced power generation systems is to have knowledge of the process conditions. In addition to physical measurements (e.g., pressure, temperature), real-time knowledge of gas compositions at critical locations enables optimizing operational conditions. The goal of this project is to develop an integrated package to enable operation of MEMS sensors in the harsh environments associated with advanced power systems. This standard package will enable placement of a variety of chemical sensors in the process, and to quickly adjust for process variations (e.g. feedstock energy content, intake air humidity, etc.). In Phase I, Makel Engineering developed two integral probe designs for harsh environments, meeting the requirements for a wide range of applications within advanced power generation. The T-Style integral packaging was developed for installation in stationary turbines. The R- Style was developed for installation in refractory lined walls. Probes were fabricated and tested in simulated environments. Phase II will focus on testing chemical sensors in turbine and gasifier systems at a wide range of end user facilities that include DOE coal-fired facilities as well as facilities operated by Sacramento Municipal Utility District (SMUD) and turbine manufactures. This will demonstrate how advanced sensors can play an important role in characterizing the physical and chemical environments within gas turbines and other components present in emerging clean coal technology power systems. Advanced stationary gas turbines is the primary application for the technology, requiring. Measurement of species such as NOx, CO and O2 at elevated temperatures to optimize operational conditions. On a related application, temperature is the primary limiting factor in the placement of chemical sensor in aircraft engines.
* information listed above is at the time of submission.


text:
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2 x Palmer's Cocoa Butter Formula Purifying Mask 120g
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- With green clay and sweet almond oil
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- Kaolin gently dries to detox and purify skin
- Suitable for all skin types
- Please note: product must be used within 12 months of opening


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De Standaard [krant] (30 items)
Welcome back! Whilst you were away we added the functionality to view auctions and bid in pounds.
De Standaard [krant]: Information on the Catawiki site about 60 jaar Nero, 2007.
At its heart, Catawiki is an online catalogue with images of, and information on, collectibles. Our catalogue is compiled by users in a similar way to Wikipedia.


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Lomography + Violet & Daisy: Beautiful & Badasss rumble2013-05-20 6 37 Share Tweet
We've partnered with the new flick "Violet & Daisy" starring Saoirse Ronan and Alexis Bledel. This film's all about being edgy in style, so send us your photos that are "beautiful and badass" for some sick prizes!
Directed by Academy Award winner Geoffrey Fletcher, Violet & Daisy is the story of Daisy (Saorise Ronan) and her surreal and violent journey through New York city with her volatile partner-in-crime, Violet (Alexis Bledel). These two young assassins face a series of opponents, including one unusually mysterious man, in a life-altering encounter. Be sure to catch the movie on June 7!
We love the cinematography in the movie—an edgy, comic-book-like film that takes place in NYC. Join this pair of gum-chewing teenage rebels by shooting analog photographs with the theme "beautiful and badass." It could be anything from the dark, dive bars in the city to a stealthy portrait you've captured. Surprise us!
One grand prize winner will receive:
- One special edition poster (never before printed!) signed by director Geoffrey Fletcher
- Inclusion of winning photos in iTunes Extras of the digital release of "Violet & Daisy"
- Teaser and final theatrical one-sheet signed by Geoffrey Fletcher
- One Diana F+ Mr. Pink
Five runner ups will each receive:
- One theatrical one-sheet signed by Geoffrey Fletcher
- 15 piggies
Some rules to keep in mind:
- Film/Camera Type: Any analogue photo not digitally enhanced or manipulated.
- Upload Limit: 10 images
- Minimum Photo Dimensions: Submissions must be at least 768px in either width or height. You must have a high resolution image available (minimum 300 dpi)
Best of luck, and show us what you've got! To get the latest news from "Violet & Daisy," be sure to follow them on Facebook and Twitter .
written by angelab_log on 2013-05-20 #videos #news #competition #rumble #movie #diana-f-mr-pink #violet-daisy #geoffrey-fletcher