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The news rolled over Opal like a steamroller---Palmer was leaving her. Fortunately things weren't as dire as Opal first believed. Palmer announced that he'd be flying to Japan to handle some trade agreement problems between the Land of the Rising Sun and Cortlandt Electronics. Opal begged her husband to have one of his assistants handle the matter, but Palmer felt that he was the only man for the job. Palmer told Opal that he'd call their son, Petey, to talk to him as soon as he settled into his hotel room. Opal's voice cracked as she tried her best to convince Palmer that he needed to stay at home and work out their problems. Palmer hushed Opal, snapping that she'd already made enough of a scene at The Valley Inn. Opal apologized for her outburst. She admitted that she'd jumped to the wrong conclusion and asked Palmer if he could forgive her mistake. Palmer explained that Opal had embarrassed herself at the restaurant---not him. And Opal's claims that she didn't feel embarrassed only made Palmer even angrier. "You're slipping through my fingers," Opal sobbed openly, "and there isn't a blasted thing I can do." Palmer stared back at Opal without a so much as a glimmer of emotion on his face. In fact, he coldly noted that his numbing of emotion towards his wife "has nothing to do with [her] taste." The problem, of course, was Opal's erratic behavior. Opal again apologized for her spectacle at The Valley Inn unaware that her odd behavior began back when she interfered in Kevin and Kelsey's love life. Opal lowered her head and continued to weep. She told Palmer that she couldn't remember the last time they touched or kissed. Opal feared that if Palmer left for Japan, he'd walk out of her life forever. Palmer assured her that he'd be back and that once he returned they could deal with their crumbling marriage. "How did we get here," Opal asked in a voice just above a whisper. "If I knew that," Palmer replied, "I'd certainly know a way for us to get back." Palmer took his coat and walked out the front door.
Hayley once again turned to God for help in bringing Mateo out of his coma. Back in Mateo's dreamlike state, the haunting sounds of demonic laughter filled the carnival atmosphere. Hayley screamed in horror as the shadowy figure lowered the sledgehammer. Mateo raced to Hayley, but he was too late. He held her lifeless body in his arms. Something in the dream poured into the real world as Mateo once again squeezed Hayley's hand. Hayley looked down at her husband's body and watched in awe as his eyes slowly opened. Although blurry, Mateo was finally able to see his surroundings. Hayley immediately fell into a frenzy as she called out her husband's name and asked him if he could hear her. Mateo remained unable to speak, but he blinked his eyes as a signal that he could, in fact, hear Hayley's voice. Hayley had faced disappointment before and wanted to make sure that Mateo's blinking was not another reflex action. She encouraged Mateo to blink two more times and every time her request was met with a blink from Mateo. Hayley asked Mateo to keep his eyes open while she phoned Jake. Hayley held on to Mateo's hand and stretch across the room towards the phone. Her arms weren't long enough to make the reach. She lunged across the room, grabbed the phone, and raced back to Mateo's side. There was no chance of Hayley losing her husband again. By the time Jake showed up, Mateo had stopped blinking. There was a marked change in Mateo's condition, but it wasn't enough to warrant celebration. Jake explained that Mateo's pupils were now responding to light. Hayley was certain that it was only a matter of time before Matt woke up. Jake, who prefaced his comments with a disclaimer about his lack of expertise in coma research, told Hayley that Mateo had made a great leap up the progress scale... but added that there was still no way of knowing when---or even if---Mateo would pull out of the coma. Jake could see that his grim outlook had stifled Hayley's jubilance. He made an abrupt one-eighty and changed his prognosis. Now, Jake assured Hayley that it would only be a matter of time before Mateo was pouring him a beer at Holidays. Mateo blinked, echoing Jake's forecast.
Erica was haunted by the possibility of having had a stranger lurking in her house. She slipped downstairs and called out to the supposed intruder. Meanwhile, Jack had rolled over in bed and realized that Erica was missing. Jack wandered downstairs and put an end to Erica's search just as she was closing in on Mike's position. In an attempt to ease Erica's concerns, Jack agreed to search the house for signs of a prowler or, as Erica believed, an obsessed fan. Jack's search turned up empty. A few seconds later, a frenzied pounding sounded on the door along with the cries of a familiar voice. Opal, distraught from her fight with Palmer, burst into the house as soon as Erica opened the door and begged her gal pal for advice. Opal looked around and eventually noticed that Erica was not alone. Now Opal had doubled her feeling of guilt, seeing that she'd probably interrupted Jack and Erica's night of passion. Erica and Jack welcomed Opal into the house and asked her to explain what had happened. "Palmer is gone," Opal said as she sobbed uncontrollably. Opal's high level of emotion led the couple to believe that Palmer had died! Needless to say, they were relieved to learn that he'd only left for Japan. Opal explained her debacle at The Valley Inn and told Erica that she believes Palmer will leave her for good. Opal was urged to go the airport and stop Palmer from getting on his flight. Opal was ready to zoom out the door until Jack demanded that he be allowed to present the male perspective on the situation. Jack explained that racing to the airport would probably only make things worse. He urged Opal to wait for Palmer to return from his trip and then work on sorting out their problems. Erica concurred and wished Opal the best of luck in getting things back on track. After Opal left, however, Erica and Jack were left to wonder if their relationship would weaken over time. That prompted Erica to evaluate her current feelings for Jack. When she realized that she didn't want marriage to ruin their love for one another, Erica suggested that they break off their engagement. Jack cocked his head to one side and assured Erica that they need not break off their engagement in order to prevent their feelings from diminishing. Content that they would remain in love for the rest of their lives, Erica and Jack went back upstairs to bed. Meanwhile, Mike stepped out of the shadows with a frown planted on his face.
Dimitri's surprise attack easily earned him the upper hand. In a desperate attempt to fend off his attacker, Jim reached for his flashlight. He waved it feverishly hoping to catch a break and connect with Dimitri's head. It didn't work, but it allowed Jim a chance to break free of Dimitri's grip and make a run for it. Dimitri caught up to Jim, but not before Jim could pull a knife from his pocket. Jim flashed the blade and made a lunge at Dimitri's chest. Dimitri stepped aside and grabbed Jim's knife-wielding arm. Dimitri twisted Jim's arm behind his back and smashed his head against a rock several times. Jim tumbled to the ground... out cold. Dimitri was about to slash Jim's throat with the knife, but Edmund's desperate pleas for help captured and diverted his attention. Dimitri raced into the viaduct to see what had happened to his brother. Upon seeing the handcuffs, Dimitri knew that he could probably free Edmund---but only if he could find Jim's keys. Dimitri raced back to Jim's lifeless body and searched for the keys but couldn't find them. Dimitri went back into the chamber to tell Edmund that he was going to head to a small, nearby town to ask for police assistance. Back on the beach, in what can best be compared to a horror movie, Jim's eyes suddenly opened and a maniacal look crept across his face. From inside the viaduct, bot Edmund and Dimitri could hear the sounds of the rusty iron gate closing. Dimitri tried to race to the entrance before Jim could padlock the gate, but he was too late. Jim, weak from this battle with Dimitri, took great pleasure in outfoxing the brothers. Jim explained that since Dimitri had botched his opportunity to kill him, it was now his turn to get a shot at Dimitri's life---and he wasn't going to let it slip by. Dimitri watched as Jim walked away from the gate. He shouted "No!" at the top of his lungs hoping that it would somehow make Jim change his mind. It didn't. In fact, it brought about the return of Jim's evil wit. For each time that Dimitri yelled, "no," Jim yelled "Yes!" Edmund was content to die as his body couldn't fight any longer. Dimitri refused to give up, but saw no way out of their dilemma. Edmund asked his brother if he still carried his "apple peeler thingamajig." Dimitri's face lit up and he pulled his pocketknife from his pocket.
Back In Pine Valley, Brooke had fallen asleep on the sofa. A hand gently rubbed her shoulder and roused her from her sleep. Brooke looked at Jim in astonishment and asked him how he'd gotten into the house. Jim held up a set of keys that he'd had made. Brooke, now fully awake, looked at Jim's bruised and bloodied face and asked him what had happened to him. Jim claimed that he'd overheard two "punks" talking about Laura's pornographic photos and that after he asked them to stop, they jumped him. Brooke then asked Jim about his meeting with Dimitri. Jim smiled and said that it seemed to go well---but added that Dimitri was acting rather strangely and oddly "chummy." Jim rubbed Brooke's hand and assured her that after tonight Dimitri would "no longer be a problem." Jim returned to The Valley Inn to wash up. Brooke knew that things had gone wrong... terribly wrong.


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Martyn Brice
We have a kitten that is getting aggressive towards our 13 year old cat, who is a little frail. Our kitten has now calmed down a bit and there are less fights
Elizabeth Dicker
This has calmed my two teenage sibling cats down. Much less aggression than previously. Would reccommend.
Jenny Mead
Having bought the starter kit, to see if the statements made by Feliway lived up to the reality - I can recommend this product if you have kittens that seem to be always fighting. No longer!! I am now on my refill, and will be continuring use of this great product.
Carole Ashworth
This definitely seems to do the job it's meant to do and has a calming effect on my 2 cats.

subset: commoncrawl


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login with
Is Tylenol safe in the beginning and the end of pregnancy
I tried to avoid all medications in the first trimester when the baby is the most sensitive. If I had a fever I did take Tylenol though because the side effects of a high fever on the baby are higher than any possible risk of Tylenol. My doctor told me that Tylenol should be safe during any stage of pregnancy and is one of the safest medications that can be taken during pregnancy. My doctor did advice though that I should only take it if necessary and to only use regular Tylenol (not to use Tylenol cold, or flu, or extra strength or migraine).
I don't remember taking any Tylenol during pregnancy, maybe with my first two, but I remember being prescribed it for pain after a couple of births.
That or Advil/ibuprofen.
I HAD to take Tylenol EVERY DAY in my 3rd trimester because of back pain. I couldn't sleep if I didn't take it.
I've always been told that Tylenol is the only pain medication safe during pregnancy.
I took Tylenol perhaps 2 times during my whole pregnancy.. but I barely take medication for anything NOT being pregnant.. I also used peppermint oil in place of the Tylenol :)
Moms also like
About Katie
Birth: November 24
On Moms.com since: Jan 21, 2014
***Community Manager of Moms.com*** Mom to four amazing children. I am passionate about helping and supporting new moms as they enter into motherhood. I am a certified doula, certified childbirth educator and an accredited breastfeeding counselor.


text: what is the meaning of pandiwa in filipino Retrieved from "http://answers.wikia.com/wiki/What_is_pandiwa_in_parts_of_speech_in_filipino?oldid=3745945" Ad blocker interference detected! Wikia is a free-to-use site that makes money from advertising. We have a modified experience for viewers using ad blockers Wikia is not accessible if you've made further modifications. Remove the custom ad blocker rule(s) and the page will load as expected. Categories: Answered questions Parts of speech Add category Cancel Save


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No cover art on CD source, so Advance. Inspired by Spacemen 3, Skygreen Leopards, Galaxie 500, the band combines warm Farfisa drones with hazy guitars and bright vocal harmonies to create something similar without sounding redundant.
The Magic Castles - The Magic Castles
A Records / CD
Magic Castles had self-released three albums (two in 2009), all of which are currently out of print, before fans landed a You Tube video in the hands of the legendary Anton Newcombe (Brian Jonestown Massacre) via the We Are The Radio/Dead TV experimental social media phenomenon in 2010.
On hearing the tracks Anton quickly asked the band to sign to his label which they did in 2011. Magic Castles are a band from Minneapolis Minnesota that was abruptly formed in 2006 by Jason Edmonds, with the help of guitar-ace Jeremiah Doering and a rotating cast of players and friends. Lyrically concerned with trolls, golden birds, and other creatures conjured from the lands of the mushroomed mind, the band takes a journey-is-better-than-the destination approach.
Track List:
01. Death Dreams 5:02
02. Now I m A Little Cloud 6:19
03. Imaginary Friends 3:47
04. Ballad Of The Golden Bird 7:59
05. All My Prayers 8:25
06. Songs Of The Forest 5:55
07. 10 100 3:08
08. Letterbox 4:26
09. Big Sur 5:13
10. Mystical Sage Warrior 5:39
11. Emery Memories 5:40


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Independent Oil and Gas plc has been advised by ATP Oil and Gas UK Ltd ('ATP UK') that it no longer has a rig contract in place for the drilling of the planned Skipper appraisal well, which was scheduled for Q3, 2014. IOG has consequently commenced the process to replace ATP UK as the operator of the Skipper and Blythe licences, under the Joint Operating Agreements. IOG has also commenced the process with the Department of Energy and Climate Change ("DECC") to meet their requirements to take over as operator.
IOG remains committed to the original drilling schedule, subject to contracting with an alternative rig provider. With the support of ATP UK, IOG has been in discussions with AGR Well Management Ltd ("AGR") with regards to the ordering of long lead items for the Skipper appraisal well, based on the original timetable. AGR is now also assisting IOG in securing a replacement rig slot.
Independent Oil and Gas plc
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Editor: Michael Rogers
Copyright 1973-2016. Scandinavian Oil-Gas Online. ISSN 1500-709X.
Tel: +47 22 44 72 70, Fax: +47 22 44 72 87


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Welcome "Tomorrow", good-bye "Monokai"
We have, once again, updated our default theme. Our new default theme is Tomorrow. So, what was wrong with our previous theme Monkai then? Well, actually nothing. It is a beautiful by itself. However, at times, we noticed that some of the colors appeared too bright, especially at a higher display brightness. Now, that is fine for most people. However, we wanted to make sure, that all our users have an experience that is relatively more soothing to their eyes, especially since the default background is dark.
The light theme stays the same though. So, if you do not like our new default theme, then just click the Night Vision toggle switch.


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Krzysztof Penderecki
Krzysztof Penderecki is a composer and conductor. He has studied at the Krakow Conservatory under Artur Malawski and Stanislaw Wiechowicz and graduated in 1958. In 1959, he composed Threnody for the Victims of Hiroshima. For this, one of his best known and most often performed compositions, he received the UNESCO prize. This piece was followed by a series of success: in 1960 at the Donaueschinger Musiktage with Anaklasis, the following year with Polymorphia, Phonograms, and Psalm, and in 1966, St. Luke Passion, the first major work of his career. The following year brought the composition and performance of another major choral work, Dies Irae, known also as the Auschwitz Oratorio. He has received numerous prizes for his life's work and he is the honorary member of various universities and music academies. In 2005 Krzysztof Penderecki was awarded the Order of the White Eagle — Poland's highest decoration. He is an active conductor and often also conducts his own works. In September 1997 Krzysztof Penderecki became the musical director of the Sinfonia Varsovia orchestra.


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Dr Will Herrington
Contact information
|+44 (0)1865 743926
|http://Twitter feed: @willkidney
Will Herrington
Senior Clinical Research Fellow, Renal Studies Group, Clinical Trial Service Unit and Epidemiological Studies Unit
Will Herrington studied medicine at University of Cambridge and University College London (1997-2003) and has practised in nephrology since 2006. He was appointed an Honorary Consultant Nephrologist at Oxford Kidney Unit in 2014. He joined the Renal Studies Group at CTSU in 2010 as a Clinical Research Fellow and worked on SHARP and 3C, two landmark trials in nephrology. He was awarded an MD from the University of Cambridge in 2013 for his thesis entitled 'The effects of lowering LDL cholesterol on stroke in chronic kidney disease' and retains a key interest in the safety and efficacy of lowering LDL cholesterol on both renal and vascular outcomes in people with chronic kidney disease.
His current research also focuses on understanding the key determinants of developing kidney disease and cardiovascular disease and the use of routine healthcare data and mobile technology for large-scale renal epidemiology and streamlined randomized trials.
He works with the SHARP, the Mexico City Prospective Study, the Cholesterol Treatment Trialists' Collaboration, UK Biobank, Clincal Practice Research Datalink data, China-Kadooire Biobank, and the Prospective Studies Collaboration, and aims to understand how adiposity and diabetes (and associated risk factors including lipids and blood pressure) impact on renal and cardiovascular health in a wide range of populations.
He is module co-lead for the Record Linkage and Bioinformatics module in the department's MSc in Global Health Science, is a subject editor for the Clinical Kidney Journal, an adviser to the Kidney Health Initiative and Clinical Trials Transformation Initiative and Scientific Co-ordinator for the KDIGO Controversies Conference on Challenges in the Conduct of Clinical Trials in Nephrology.
Key publications5
Diabetes and Cause-Specific Mortality in Mexico City
Herrington W. et al, New England Journal of Medicine
The effects of lowering LDL cholesterol with simvastatin plus ezetimibe in patients with chronic kidney disease (Study of Heart and Renal Protection): a randomised placebo-controlled trial.
Baigent C. et al, (2011), Lancet, 377, 2181 - 2192
Impact of renal function on the effects of LDL cholesterol lowering with statin-based regimens: a meta-analysis of individual participant data from 28 randomised trials
Herrington W. et al, (2016), The Lancet Diabetes and Endocrinology
Evidence for reverse causality in the association between blood pressure and cardiovascular risk in patients with chronic kidney disease
Herrington W. et al, Hypertension
Association between diabetes and cause-specific mortality in rural and urban China
Bragg F. et al, (2017), JAMA
Recent Publications5
Tightening our understanding of intensive glycaemic control.
Herrington WG. and Preiss D., (2017), Lancet Diabetes Endocrinol
The Role of Emerging Risk Factors in Cardiovascular Outcome
Lacey BWH. et al, (2017), Current Atherosclerosis Reports
Body-mass index and risk of advanced chronic kidney disease: Prospective analyses from a primary care cohort of 1.4 million adults in England
Herrington WG. et al, (2017), PLoS One
Association between diabetes and cause-specific mortality in rural and urban China
Bragg F. et al, (2017), JAMA
Prognostic utility of estimated albumin excretion rate in chronic kidney disease: results from the Study of Heart and Renal Protection.
Mafham MM. et al, (2017), Nephrol Dial Transplant


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Flac lossless cv313 - Dimensional Space (Alchemy Edition) (2017) FLAC download
Artist: cv313
Album: Dimensional Space (Alchemy Edition)
Released: 2017
Label: echospace [detroit]
Genre: Ambient, Dub Techno
Duration: 02:10:22
1. Luna Petra [Alchemy Remaster] (09:54)
2. Clouds Beyond [Reprise] (14:33)
3. Clouds Beyond [Alchemy Remastered Mix] (10:08)
4. Sella Bay [Unreleased] Edit (11:11)
5. Beyond Dreams [Unreleased] (20:07)
6. Cloudburst [Unreleased] (05:54)
7. Isis [Remake] Unreleased Mix (06:40)
8. Beyond The Clouds (Seconds To Forever Live Mix) (21:52)
9. Jasna Gora [Lost Tape Session] (08:20)
10. Beyond Dreams [Live In Munich] Unreleased (21:43)
We've spent years now going through the analog tapes from the cv313 project archives and we're excited to have the long sold out, "Dimensional Space" (LP Edition) from cv313 finally available on CD. We had to pay tribute to the brilliant artwork from Lindsay Todd @ Firecracker/House Of Traps and the superbly mastered recordings from Bazza @ Alchemy Mastering, London. This edition features selected content from the LP set and unreleased versions of, "Isis", a killer new cut from the "Beyond The Clouds" sessions titled, "Beyond Dreams", this edition also features 2 unreleased cuts which were scheduled to come out on the LP edition of the album but were omitted due to budgetary concerns, never to be heard - until now. This might be the soundtrack to the other side of the galaxy, a place where space meets bass. Epic in every sense of the word!
The Digital Edition will feature the entire content of the CD and a bonus track culled from the original tape session and a special live version culled from a live performance in Munich, DE, last June.
Flac download cv313 - Dimensional Space (Alchemy Edition) (2017) FLAC
More Flac Lossless music download
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text: Home Open Source Slideshow Romancing Development: How to Avoid Feeling Vulnerable With Open Source Black Duck Software presents 5 tips for a secure enterprise relationship with open source. By Steve Ragan, Senior Staff Writer, CSO | Feb 11, 2015 2:39 PM PT Share All Slides SLIDEFEATURED PRODUCTS Feeling Vulnerable? Matchmaking Dating Honeymoon Phase Soul Mates Maintaining That Relationship Share this Slideshow Direct link: Shutterstock Feeling Vulnerable? Avoid a bleeding heart. Black Duck Software presents 5 tips for a secure enterprise relationship with open source. Shutterstock Matchmaking Find the perfect match: Combine collaboration and crowd-sourcing with community-based vulnerability reporting (National Vulnerability Database + proprietary open source databases = perfect open source match).Use resources like OpenHub.net and GitHub to learn about and compare the history and activity of projects of interest and the developers behind them.The perfect project match needs to combine stability with community activity, strong development with user engagement, and a history that matches your organization's risk tolerance. Mazel-tov! Shutterstock Dating Hygiene Matters: Ensure only the latest and safest open source components are integrated into apps (Open source hygiene is the safe sex equivalent).Safe sex, appsec – same difference. Frequent checkups ensure healthy open source relationships too. And no need to be version-promiscuous – code scanning tools and accompanying policies and processes make it straightforward to keep your software stack clear of old and vulnerable versions of software components, and to clear up confusing and resource-sapping version proliferation in your software catalog. Shutterstock Honeymoon Phase My, don't you clean up nice!: Implement methods, tools and best practices for improving code quality as a means to more secure code. Code quality issues account for up to half of all security vulnerabilities.Rigorous team-based code reviews (for internal code) and early exposure to community eyeballs (for OSS) complement automation from tools like Coverity, Fortify, Klocwork and the Black Duck Suite. Shutterstock Soul Mates Know when you've found "the one": Not just many eyes, but the right eyes are needed to make bugs shallow and eliminate vulnerabilities (expand on the underpinnings of open source security).Having a well-peopled community isn't enough – the developers and users have to be the "right" people with the right eyeballs. Any project involving critical infrastructure or developing public-facing software needs to recruit security-savvy developers to complement domain experts and generalists that build and sustain the project. Shutterstock Maintaining That Relationship Avoid relationship pitfalls: Strike the ever so important balance between developer needs and security goals. Security regimes, like so many relationships, fail from lack of flexibility.Hardheaded security policy always seems like the antidote to softhearted or sloppy user behavior, but too strict a regime will either be ignored by users and developers or drive them away from a project or technology. Security policy needs to reflect the level and scope of actual threats but not make technology unusable, to say nothing of unlovable. Next Up: Check out these related slideshows 10 screen-sharing apps offer easy collaboration FBI's top 10 most wanted cybercriminals Incident response is like tracking down a perpetrator How to counteract another 'Dyn-like' attack Hottest news from OpenStack Summit 26% off Qwerkywriter BlueTooth Mechanical Keyboard with Integrated Tablet... $150 Price Drop on Pico Pro Craft Beer Brewing Appliance - Deal Alert 63% off Anker SoundCore 2 Bluetooth Speaker with 24-Hour Playtime - Deal Alert Related Slideshows 10 screen-sharing apps offer easy collaboration FBI's top 10 most wanted cybercriminals Incident response is like tracking down a perpetrator How to counteract another 'Dyn-like' attack Hottest news from OpenStack Summit 6 things you need to know about IoT security You Might Like Email a friend To Use commas to separate multiple email addresses From Privacy Policy Thank you Your message has been sent. Sorry There was an error emailing this page.


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Morgan Stanley was the first international financial company to offer mutual funds in India. It was incorporated in 1993 and was operational till 2014. In 2014, Morgan Stanley Mutual Fund handed over all its assets to HDFC Asset Management. The company was subsequently de-registered by the Securities and Exchange Board of India (SEBI) in the same year.
HDFC Asset Management merged with Morgan Stanley in December 2013. The merger, valued at over Rs.3,090 crores, increased the investor and asset base of the largest mutual funds company in India, HDFC Mutual Fund. The merger was largely seen as a consolidation exercise by HDFC in the highly dispersed Indian mutual funds market.
Morgan Stanley funds were either absorbed or rechristened by HDFC MF as the following products:Schemes with fundamental changes
Morgan Stanley Growth – HDFC Large Cap
Morgan Stanley A.C.E. – HDFC Small and Mid Cap
Morgan Stanley Gilt Fund – HDFC Inflation Indexed Bonds
Morgan Stanley Multi Asset (Plan A and B) – HDFC Dynamic PE Ratio FOFs.Schemes that were merged
Morgan Stanley Liquid – HDFC Liquid
Morgan Stanley Ultra Short Term Fund – HDFC Cash Management Fund - Treasury
Morgan Stanley Active Bond – HDFC High Interest Fund - Dynamic
Morgan Stanley Short Term Fund – HDFC Short Term Bond
Other Products
Display of any trademarks, tradenames, logos and other subject matters of intellectual property belong to their respective intellectual property owners. Display of such IP along with the related product information does not imply BankBazaar's partnership with the owner of the Intellectual Property or issuer/manufacturer of such products.
News About Morgan Stanley Mutual Fund
JPMorgan Seeks Investor Approval for Delinking Amtek-based funds
JPMorgan has sought investor approval to segregate its Amtek-based funds. SEBI meanwhile has asked mutual fund houses about their exposure to funds linked to Jindal Steel and Power (JSPL), after the rating agency ICRA downgraded JSPL ratings on non-convertible debentures (NCD), term loans, commercial papers, and fund and non fund-based limits of the company.
SEBI had recently sent notifications to various fund houses regarding their investments as a few debt funds have recently turned liquid after downgrade by credit rating agencies. Majority of fund houses tend to keep corporate debt till maturity however pressure of sudden redemptions can give rise to crises.
As a result of the moves of SEBI as well as news of selling of non-core business, Amtek Auto shares have surged by more than 13%. SEBI has asked different houses to give reports on the downgrades of bonds they have invested in on a real time basis.
22nd September 2015
Morgan Stanley India Investment Fund shares on a high
Morgan Stanley Invest Fund Inc shares, which have been on a roller coaster ride over the last few months ended on a high this week, as they appreciated by 1.23% over the last week. This high was, however, overshadowed by a 9.58% loss over the last 4 weeks.
The performance of these shares are negative when compared to S&P 500, with a 0.83% loss registered against their names. The shares have underperformed over the last 4 weeks, with a 3.56% drop compared to its index. Shares have fluctuated from a high of $25.7242 to a low of $25.25 this season. This fund is a non-diversified close-ended fund which invests primarily in equity securities like food products, pharmaceuticals, construction, etc.
14th September 2015
JP Morgan's AMC faces heat over redemption restrictions on debt schemes
JP Morgan's AMC is facing heat over redemption restrictions placed on two of its debt schemes viz. the Short Term Income Fund and India Treasury Fund, as investors liquidate holdings to avoid being locked-into the fund. The schemes had invested about Rs.200 in Amtek Auto which faced financial credibility issues yet held a strong credit rating on its debt paper.
This incident has led to doubts on the dependency placed on ratings awarded by leading agencies. Care Ratings faced heat over its decision to continue with an A+ rating on short-term paper from DCHL despite clear liability defaults on the part of the company. However, the general consensus among fund managers is that investment responsibility lies with the fund manager of the two schemes. Ratings alone cannot suffice in supporting investment decisions.
2nd September 2015
GST rate of 18% applicable for all financial services effective July 1, 2017.


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I'm decidedly against breaking your budget on wedding cake. There are plenty of ways to save on cake and still have it look and taste great! From the sheet cake/dummy cake swap to finding a pastry student to help, or simply keeping the design simple – wedding cakes can easily be made budget-friendly. Or, maybe you're like us, and aren't so attached to the cake tradition and so opt for an alternative dessert.
Usually, I'm also against the notion of people DIYing their own wedding cake. Spells trouble, almost every time. Hey, guess what you don't really need right around your wedding day? The stress of baking and icing your freaking wedding cake! Unless you're one of those type A-ers that gets off on the thrill of that kind of thing…. in which case, have at it.
Then I saw this. And my universe expanded. It's the perfect, affordable, DIY friendly alt-cake, people!
I mean, imagine the possibilities…… (watch out for falling drool!)
•Add 1 cup M&Ms per 6 cups rice krispies for fun pops of color and random chocolate bites
•Use Cocoa Krispies if you're cuckoo for chocolate, or if brown is one of your wedding colors.
• Don't even get me started on how delicious peanut butter is mixed in with your treats; but melt together a dollop of peanut butter into 1.5 cups of chocolate chips and spread it on top…. you'll die!
• For a very colorful and whimsical cake, Fruity Pebbles would be adorable. Customize your color level by combining Fruity Pebbles with plain Rice Krispies.
Don't forget, you can substitute your favorite cereal for rice krispies for scrumptiously unexpected results. I use Corn Flakes during the holidays, with green food coloring and red sugar sprinkles, and make treats in the shape of a wreath. Yumaliciously festive!
PLEASE someone make this. (Better yet, have a friend make it for you). Also, invite me to your wedding.
How would you customize your krispy cake?


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Texas Instruments announced their TPS27081A high-side load switch. The device integrates a power PFET and a control NFET in a tiny 6-pin package. The TPS27081A is a flexible replacement for discrete FET switches. The load switch features adjustable slew-rate control so designers can implement the device in any application that requires load switching or power sequencing. The TI TPS27081A is available in a 2.9-mm x 1.6-mm x 0.75-mm thin SOT-23 (DDC) package. The suggested retail price is $0.12 in 1000-unit quantities. It is ideal for notebooks, tablets, LCD televisions, global positioning systems (GPS) and set-top boxes.
The TI TPS27081A IC features industry-standard ESD protection on all pins to provide better ESD compatibility with other on-board components. The TPS27081A level shifts ON/OFF logic signal to VIN levels and supports as low as 1.0V CPU or MCU logic to control higher voltage power supplies without requiring an external level-shifter.
Texas Instruments TPS27081A Features
- Low ON resistance, high current PFET
- RDS(ON) = 32mΩ at VGS = -4.5V
- RDS(ON) = 44mΩ at VGS = -3.0V
- RDS(ON) = 82mΩ at VGS = -1.8V
- RDS(ON) = 93mΩ at VGS = -1.5V
- RDS(ON) = 155mΩ at VGS = -1.2V
- Adjustable turn-on and turn-off slew rate control via external R1, R2, and C1
- Supports a wide range of 1.2V up to 8V supply inputs
- Integrated NMOS for PFET control
- NMOS ON/OFF supports a wide range of 1.0V up to 8V control logic interface
- Full ESD protection (all pins)
- HBM 2kV, CDM 500V
- Ultra low leakage current in stand-by (100nA typical)
- Available in tiny 6-pin packages
- 2.9mm x 1.6mm x 0.75mm Thin SOT-23 (DDC)
- 2mm x 2mm SON-6 (DRV)
More info: Texas Instruments TPS27081A PFET High Side Load Switch (pdf)


text:
"Unacceptable delays in childs prognosis"
About: St Peter's Hospital (Chertsey) St Peter's Hospital (Chertsey) Chertsey KT16 0PZ
Posted by Anonymous
We attended an EEG at the Neurology department on 7th Feb with our 3 year old son to be told that there would be delays in feedback on findings due to the consultant being away on holiday. I appreciate that holiday cover can be an issue but to then be told 36 days later that there is still no feedback and when results are in the consultant will have to write a letter, which goes to the GP instead of to the patient's parents I am seething! When will the NHS haul themselves into the 21st century and communicate through email and phones as opposed to this archaic methodology? Parents are forced to self diagnose through the internet more and more due to these types of delays only to worry more as advice is normally to seek professional help and if your child does have x then ensure that treatment is started quickly! A classic juxtaposition if ever there was one.
Response from St Peter's Hospital 3 years ago
We are very sorry to read your comments about the delays you experienced with our EEG service and Neurology Department. As you mention, we have been experiencing staffing issues within the department, which has led to some delays in issuing reports. We are trying to catch up and do appreciate that waiting for results, especially for a child, can be an anxious time. When EEG reports are issued they would not routinely be sent directly to our paitents, their guardian or their GP - but rather to the consultant who initially requested the test. This is because the information given can be quite complex and difficult to interpret and is best discussed during a follow-up visit with the consultant. We apologise if the process was not explained to you very well and have fed this back to the team - so that we can ensure that future patients are clear on how they will be receiving their results. I would welcome the opportunity to speak with you in more detail about your son's care and your experiences. If you would like to do so, please contact me directly on 01932 722190. Justine Hillier Associate Director of Nursing for Medicine
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Most Helpful Girl
For me has to be right now. I found dealing with my dad going to rehab for alcoholism a lot easier than my current phase of not being financially secure enough to move out of my parents and do something for myself. I'm not fond of my job, I don't get out much because pay is not great and even when I do I can't stop worrying about stupid things. I can't relax anymore and I'm tired of worrying 24/7, its physically and emotionally drained at this stage. I think my friends are getting fed up of me not going out anymore with the no money excuse.00|00|0
Most Helpful Guy
Right now. After having been successful my whole life at everything I did, I suddenly have founded myself in unchartered waters.
My career/practice/business ended in a day and took almost a year to start up again... from scratch. But I'm doing it. What doesn't kill you, makes you stronger.00|00|0
Thanks 👊
My worst phase of life is I cannot express my feelings that how much I love the women of my life. She is miles away from me but still I love her the most.


text:
Mr. Peters begins when you look at the Introduction exposing their preferred trader, Marjorie Bradt.
No, you've never ever been aware of the girl. She ended up being litigant associated with the brokerage he as soon as worked for as an assistant. Ms. Bradt's daddy provided the girl around $6,000 well worth of stocks of AT&T stock when you look at the late 1950s and very early sixties. She signed up for AT&T's dividend reinvestment program, and simply held to the stocks and continued reinvesting dividends. In 1984 a court bought AT&T to split up into the "Baby Bells," and they've got since spun off different companies. Many of them spend dividends which she proceeded to reinvest. By 1999 the girl portfolio ended up being worth over $1 million dollars. Oddly, given the topic of this guide, Mr. Peters does not reveal exactly what the girl yearly dividend income ended up being.
I need to wish he'd had the opportunity to provide united states more understanding of Ms. Bradt. Performed she also remembered she had this stock? Performed she ever feel tempted to liquidate the stock? Eventually she along with her spouse should have felt the necessity for more cash. The reason why don't she add more cash on portfolio?
However, it is outstanding story. It isn't readily duplicatable, because $6,000 ended up being a ton of cash back in those day — a decent middle-class yearly income, believe it or not. And because AT&T's record is unique. Only a few stocks will have carried out so well, also over forty many years.
Unfortuitously, Mr. Peters himself does not display as much persistence. He mentions selling stocks that do not fulfill their objectives.
And he's definitely into the analysis of specific stocks. Early on he dismisses the value of mutual funds and exchange traded funds, and later criticizes the concept of diversification which, of course, is the reason for investors putting their money into mutual funds and exchange traded funds.
I find this only a little odd in a book by a worker of Morningstar, that was started to provide investors assistance with mutual funds. (Mr. Peters is the editor of Morningstar DividendInvestor, their particular publication on dividend investing.)
Which is the guide's weakness, to my brain. Mcdougal is a monetary analyst and plainly knows plenty in regards to the companies that usually spend dividends and just how to crunch their particular numbers.
But this is why the whole procedure look extremely tough on average trader that is maybe not a CFA. They may spend much time of these spare-time trying to replicate exactly what he does, and will not come near. They truly are maybe not compensated to get it done as a full-time task, while he is.
Most readers will not also attempt. They will often give up dividend investing or subscribe to DividendInvestor getting Mr. Peters' suggestions about an everyday, continuous foundation. And it's difficult to think that someone at Morningstar, perhaps the author or otherwise not, is certainly not dreaming about that outcome.
I really do salute the writer in making a place I was thinking only I comprehended — that spending threat is certainly not price volatility but real life activities that push companies to cut or end paying dividends.
On the whole, I recommend this guide to any or all wondering whether spending for dividends is a good idea.


text:
On my to College today, i had some boy coming to me and taking the piss out of me, so i went like " You're alright" and then he went like "I shit myself" i mean, i couldn't keep myself from laughing. Anyone else has had such experience?
Has anyone else got harassed by kids?
Have an opinion?
What Girls Said 1
I was buying phone credit one day and this little lad (literally he was like 7) comes up to me and says, and I quote (let's go b*itch, you wanna fight? Cause I'll f*ucking fight Ya) AND HIS MOTHER WAS RIGHT BESIDE HIM LAUGHING!!! I was like what the hell? Are you talking to me? And then him and his mother just left... without saying another word... deffinitly the weirdest experience of my life00|00|0
What Guys Said 1
No, but i have worked with many annoying evil kids.00|00|0
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|Publication number
|Publication type
|Application number
|Publication date
|Apr 10, 2001
|Filing date
|Sep 30, 1998
|Priority date
|Sep 30, 1998
|Fee status
|Publication number
|Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo
|Original Assignee
|Compaq Computer Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (6), Referenced by (12), Classifications (6), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Field of the Invention
This invention relates to a computer and, more particularly, to a bus interface unit which can stall read and non-postable write cycles issued to a peripheral bus until the peripheral bus becomes available or a cycle occurs to system memory. If a cycle is issued to system memory, then the bus interface unit either defers or retries the prior cycles to the peripheral bus after the cycle to system memory completes.
2. Description of the Related Art
Modem computers are called upon to execute instructions and transfer data at increasingly higher rates. Many computers employ CPUs which operate at clocking rates exceeding several hundred MHz, and further have multiple busses connected between the CPUs and numerous input/output devices. The busses may have dissimilar protocols depending on which devices they link. For example, a CPU local bus connected directly to the CPU preferably transfers data at a faster rate than a peripheral bus connected to slower input/output devices. A mezzanine bus may be used to connect devices arranged between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture ("ISA") bus, an enhanced ISA ("EISA") bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interconnect ("PCI") bus to which higher speed input/output devices can be connected.
Coupled between the various busses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the "north bridge". Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the "south bridge".
The north bridge, henceforth termed a bus interface unit, serves to link specific busses within the hierarchical bus architecture. Preferably, the bus interface unit couples data, address and control signals forwarded between the CPU local bus, the PCI bus and the memory bus. Accordingly, the bus interface unit may include various buffers and/or controllers situated at the interface of each bus linked by the interface unit. In addition, the bus interface unit may receive data from a dedicated graphics bus, and therefore may include an advanced graphics port ("AGP"). As a host device, the bus interface unit may be called upon to support both the PCI portion of the AGP (or graphics-dedicated transfers associated with PCI, henceforth is referred to as a graphics component interconnect, or "GCI"), as well as AGP extensions to the PCI protocol.
There are numerous tasks performed by the bus interface unit. For example, the bus interface unit must orchestrate timing differences between a faster CPU local bus and a slower mezzanine bus, such as a PCI bus. The bus interface unit should also give priority to certain types of transfers. For example, a cycle initiated by the CPU to memory must, in most instances, be completed quickly. If not, the processor-to-memory queue may not be optimally filled and instructions may not be expeditiously executed.
One mechanism in which to account for timing differences involves, for example, stalling cycles within the CPU local bus to allow the peripheral bus to catch up. This, however, penalizes CPU throughput and should be used only sparingly and judiciously. Stalling the CPU bus typically occurs during a particular transaction phase of the CPU bus pipeline. It is noted that modem CPUs utilize an extensive pipeline which can store multiple cycles of multiple transactions upon the CPU local bus. For example, a Pentium� Pro processor bus includes a decoupled, 12-stage super pipelined implementation. A transaction relating to a single bus request can sequentially pipeline through numerous phases: arbitration, request, error, snoop, response and data transfer.
Stalling the CPU local bus generally involves stalling one or more cycles in the snoop phase. This affords the earlier phases to receive cycles and have those cycles available in the snoop phase. If called upon, those cycles can be released in a timely fashion to the subsequent response and data transfer phases.
FIG. 3 illustrates a timing diagram of exemplary transaction phases of the Pentium� Pro processor bus. In the example shown, a cycle 8 a of a first transaction 8 requires approximately three bus clock cycles to obtain mastership of the CPU local bus. Approximately two clock cycles later, cycle 8 a proceeds from the arbitration phase to a request phase 8 b. As shown, the cycle 8 c begins in the error phase approximately three clocks after the request phase. Cycle 8 d occurs approximately four clocks after the request phase or approximately three clocks after the previous transaction snoop cycle, whichever is later. The cumulative number of clock cycles needed to place a transaction within the snoop phase is shown to be approximately ten clock cycles, in the example provided. Of course, as transaction 8 progresses to the snoop phase, a cycle 9 d of another transaction 9 can subsequently arrive in the snoop phase as well.
If the first transaction 8 is initiated from the CPU to a peripheral device as its final destination, then it may be necessary to delay the transaction in the snoop phase to allow the peripheral bus to clear and/or data upon the peripheral bus to become available. For example, if a transaction preceding the first transaction 8 is a non-postable write to the peripheral device, then it is necessary that the peripheral device and the peripheral bus become available before data of transaction 8 is presented upon the bus. Alternatively, if transaction 8 is a read transaction, it is necessary that the data to be read from the peripheral device be present on the peripheral bus before the local CPU bus can transfer that data during the data transfer phase. For at least these reasons, cycles within the CPU bus destined for a slower peripheral bus must occasionally be stalled in the snoop phase of the CPU bus until the peripheral bus clears and/or data therein is available.
Stalling the CPU bus at the snoop phase is typically done a fixed number of clock cycles. That is, historical differences between the peripheral bus (and peripheral device) and the CPU bus speed indicates that the peripheral bus or data on the peripheral bus will be made available some time after a transaction is completed on the CPU bus. The next transaction to the peripheral is then stalled a fixed amount of time mandated by the historically derived differences in the bus speeds. Thus, regardless of destinations for the subsequent transactions, the current transactions are stalled a fixed number of clock cycles to allow the peripheral bus to clear. This, unfortunately, will penalize throughput of all subsequent cycles (including memory cycles).
In an attempt to immediately service transactions to local memory (and i.e., system memory of substantially contiguous semiconductor memory space) many conventional techniques allow memory cycles to be completed through the CPU bus ahead of cycles to peripheral devices. This involves a technique known as cycle "deferral" of preceding, slower peripheral-destined cycles, and allowing faster, memory-destined cycles to be drawn from the in-order queue of the pipeline.
Referring to FIG. 3 and the two-transaction example shown, deferral of first transaction 8 may occurs at the snoop phase by tagging transaction 8 and allowing the second transaction 9 to proceed as cycles 9 e and 9 f within respective response and data transfer phases. In this manner, priority is given to a transaction which must be quickly serviced over that of another transaction which need not be transferred as quickly, possibly due to the slower nature of its destination device. Accordingly, the example shown in FIG. 3 illustrates a first transaction 8 destined for a slower peripheral device coupled to either a mezzanine bus or a peripheral bus, whereas the second transaction 9 is destined for semiconductor memory.
An unfortunate result of deferral technique is that the transaction being deferred at the snoop phase must be re-initiated at a later time beginning at the arbitration phase. As shown in FIG. 3, the ten cycles needed to place the transaction in the snoop phase must be re-initiated for a penalty of approximately ten CPU bus cycles. Many conventional pipeline schemes immediately defer any cycles destined for a peripheral device. The destination is detected at the snoop phase by the snoop agent. When the snoop agent is a peripheral device, that agent will return a signal causing the snoop phase to initiate a DEFER# signal. DEFER# removes the transaction from the in-order queue by generating the appropriate response. All peripheral-destined transactions will then be automatically deferred in favor of memory-destined transactions. Thus, there may be multiple transactions being deferred unless the snoop agent indicates the peripheral bus and/or device is available. In this manner, each transaction must undergo a ten clock cycle penalty if the peripheral bus, peripheral device, or data is not available when snoop occurs. When the peripheral bus, device or data later becomes available, then the peripheral-destined transaction will proceed through the remaining phases, beginning with the arbitration phase.
The aforementioned, conventional algorithm pays a rather large penalty for each deferral which may not be necessary. It would be more beneficial to simply stall the transaction at the snoop phase, but to do so only under certain conditions. Likewise, deferral of peripheral-destined transactions must be minimized and made dependent on the timing and type of transactions subsequently arriving in the pipeline.
The problems outlined above are in large part solved by a computer employing an improved bus interface unit. The bus interface unit includes a processor interface which can selectively defer one or more cycles received on the local CPU bus. The bus interface unit is therefore configured between the CPU (or processor) local bus, a graphics bus (e.g., AGP), a PCI bus and a memory bus. The CPU bus can link at least one and certainly more CPUs and associated cache storage locations within those CPUs. Additionally, the memory bus links a memory controller within the bus interface unit to system memory denoted as semiconductor memory. Examples of suitable system memory include, for example, DRAM or synchronous DRAM (SDRAM). If the graphics bus is an AGP/PCI bus then it may be linked to the bus interface unit by an AGP interface to effectuate e.g. 66 MHz 1� AGP transfers or 133 MHz 2� AGP data transfers. The bus interface unit maintains a PCI interface which is synchronous to the CPU interface and supports PCI burst cycles.
The bus interface unit is suited to account for timing differences between the CPU local bus and the slower PCI or AGP bus. The processor controller within the bus interface unit also gives priority to memory cycles. In this manner, the processor controller can stall cycles destined for the peripheral device a multiple number of (e.g., a multiple of two) CPU clock cycles. The amount of stall occurring in the snoop phase of the CPU bus depends on many factors, some of which are the availability of the peripheral bus, availability of data within the peripheral bus, or subsequent memory-destined cycles arriving in the pipeline and in the snoop phase.
The processor controller within the present bus interface unit can therefore dynamically alter the amount of snoop stall depending on when it is optimally desired to either terminate snoop stall or defer one or more cycles being stalled. If a memory-destined cycle is placed on the pipeline and arrives on the snoop phase before the previous cycle or cycles complete on the peripheral bus, then the current cycle will be deferred to allow the memory-destined cycle to run as fast as possible and complete on the CPU bus. Beneficially, peripheral-destined cycles will be snoop stalled as long as possible depending on the status of subsequent cycles, and the peripheral bus. Furthermore, deferral of cycles will only occur if the cycle cannot be further stalled due to a need for transferring a memory-destined cycle immediately to the memory controller and then to memory. In this fashion, cycles which need to complete quickly (e.g., memory-destined cycles) are serviced ahead of peripheral-destined cycles if the peripheral-destined cycles are being stalled. The peripheral-destined cycles are stalled as long as possible without having to pay the penalty for deferring those cycles except if deferral is not needed. The present deferral technique is therefore dynamic, where cycle deferrals are minimized and snoop stalls for transactions can vary an almost unlimited number of bus clock cycles.
Broadly speaking, a computer is presented. The computer includes a bus interface unit arranged on a printed circuit board. Also included with the computer is a peripheral device coupled to a printed circuit board outside that which accommodates the bus interface unit. The bus interface unit is coupled between a processor bus, a peripheral bus, and a memory bus. Embodied upon the bus interface unit is a processor control interface adapted to receive a peripheral cycle issued from the processor bus to the peripheral bus. The processor control interface is further adapted to stall the peripheral cycle during a snoop phase of the processor bus until the peripheral bus becomes available or a memory cycle is pipelined onto the snoop phase. The peripheral cycle can be deferred when the memory cycle is pipelined onto the snoop phase. Accordingly, the peripheral cycle is deferred during the snoop phase for a time period after which the memory cycle has at least partially completed phases subsequent to the snoop phase. If the peripheral cycle is non-deferrable, it can be forwarded to a response phase and re-tried by the processor after the memory cycle has completed phases subsequent to the snoop phase.
According to another embodiment, a processor bus is presented. The processor bus includes a plurality of phases which can accommodate a plurality of cycles of dissimilar transactions pipelined in sequential order upon the bus. A peripheral cycle is destined for a peripheral device, and a memory cycle is destined for semiconductor memory. The peripheral cycle is clocked through a subset of the plurality of phases and into a snoop phase of the plurality of phases. The memory cycle is clocked entirely through the plurality of phases while the peripheral cycle is stalled within the snoop phase and then deferred from the snoop phase to an initial phase of the sequential order of phases.
According to yet another embodiment, a method is provided for servicing a memory cycle ahead of a peripheral cycle. The method includes stalling the peripheral cycle within a snoop phase of a processor bus. The peripheral cycle may then be deferred when the memory cycle arrives within the snoop phase. The memory cycle may be allowed to continue at least partially through the remaining phases of the processor bus before re-issuing the peripheral cycle from an initial phase of the processor bus. The step of stalling the peripheral cycle may continue a variable number of, e.g., two clock cycles until data from a non-posted write transaction has been completed on the peripheral bus or data from a read transaction has arrived from the peripheral bus. Stalling may also continue until the memory cycle arrives within the snoop phase and, if the peripheral cycle is non-deferrable, the peripheral cycle can be re-tried from the initial phase of the sequence of phases.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a computer system comprising various buses and bus interface units;
FIG. 2 is a block diagram of a bus interface unit containing address and data queues coupled between a processor bus, a PCI bus, a graphics bus and a system memory;
FIG. 3 is a timing diagram of transactions pipelined through transaction phases of the processor bus;
FIG. 4 is a diagram of transactions occurring in timed order, wherein the pipeline is stalled during the snoop phase to allow transactions which occur earlier than a pipelined memory transaction to be deferred until after the memory transaction is at least partially completed;
FIG. 5 is a diagram of transactions occurring in timed order, wherein the pipeline is stalled during the snoop phase to allow a non-deferrable transaction which occur earlier than a pipelined memory transaction to be retried after the memory transaction is at least partially completed;
FIG. 6 is a flow diagram of decisional activities occurring within a snoop phase depending on the type of cycle presented to the snoop phase and/or the type of cycles subsequently presented to the pipeline.
While the invention may be modified and have alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Turning now to FIG. 1, a computer 10 is illustrated having multiple busses, including a CPU bus, a mezzanine or PCI bus, and a peripheral bus or ISA/EISA bus. The CPU bus connects a CPU or processor 12 to a bus interface unit or north bridge 14. A cache memory 16 is preferably embodied within processor 12 and/or linked to processor 12 by the CPU bus. Bus interface unit 14 provides an interface between components clocked at similar rates. Bus interface unit 14 preferably contains a memory controller which allows communication to and from system memory 18. A suitable system memory 18 comprises DRAM or SDRAM. Interface unit 14 may also include a graphics port to allow communication to a graphics accelerator 20. A graphics port, such as AGP, provides a high performance, component level interconnect targeted at three dimensional graphics display applications and is based on performance extensions or enhancements to PCI. AGP interfaces are generally standard in the industry, the description of which is available from Intel Corporation.
Generally speaking, AGP is physically, logically, and electrically independent of the PCI bus and is intended for the exclusive use of a display device 22 coupled to the graphics port (AGP) by a graphics accelerator and local memory or frame buffer 24. The form and function of a typical graphics accelerator is generally known in the art to render three dimensional data structures which can be effectively shifted into and from system memory 18 to alleviate increased costs of local graphics memory. Frame buffer 24 is generally understood as any buffer which can capture a frame of memory, defined as a still picture. Display 22 is any electronic display upon which an image or text can be presented. A suitable display 22 includes a cathode ray tube ("CRT") a liquid crystal display ("LCD"), etc.
Interface unit 14 is generally considered an application specific chip set or application specific integrated circuit ("ASIC") that provides connectivity to various busses, and integrates other system functions such as memory interface and P1394. Systems memory 18 is considered the main memory and refers to a portion of the addressable memory that the majority of memory accesses target. System memory is accessed via interface unit 14, and is considered the largest continuous memory space of computer 10.
Unlike the CPU bus which runs at speeds comparable to CPU 120, PCI bus generally runs at speeds of, e.g., 33 MHz or lower. Another bus interface unit 28 is coupled between two dissimilar peripheral busses (i.e., the PCI bus and the ISA/EISA bus). Similar to unit 14, unit 28 is an ASIC or group of ASICs that provide connectivity between various busses, and may also include system function which can possibly integrate one or more serial ports. Attributed to the PCI bus are input/output ("I/O") devices 30, one of which can be a SCSI controller link between, for example, a secondary disk drive and the PCI bus. I/O devices 30 generally operate at higher speeds than I/O devices 32, examples of which include a floppy disk drive, a keyboard, etc.
Turning to FIG. 2, details regarding bus interface unit 14 are shown. The various sub-components of interface unit 14 can be connected on a monolithic substrate for high end computer applications. Interface unit 14 operates in conjunction with other bus interface units such as interface unit 28, and preferably includes at least four interfaces and multiple address and data queues. Each interface is unique to the specific bus protocol of the bus to which is connects. As shown, the PCI interface ("PCI IF") includes a PCI controller 40 which enables transfer of information (control, address and data) to and from the PCI bus.
Attributed to each of the other busses is a respective controller which provides an interface for information sent across the respective bus. Thus, in addition to the PCI controller 40, a processor controller 42, a memory controller 44 and an AGP controller 46 are embodied within interface controller 14, as shown in FIG. 6. In addition to the various controllers, there are multiple address and data queues. Each controller operates independent of the others, and cycles are passed between controllers using queues which link respective controllers. FIG. 2 illustrates ten queues: processor-to-memory queue (P2M queue) 50 a, processor-to-PCI/AGP queue (P2I/A queue) 50 b, memory-to-processor queue (M2P queue) 50 c, memory-to-PCI queue (M2I queue) 50 d, PCI-to-memory queue (I2M queue) 50 e, PCI/AGP-to-processor queue (I/A2P queue) 50 f, AGP-to-memory queue (A2M queue) 50 g, memory-to-AGP queue (M2A queue) 50 h, and PCI-to-AGP queue (I2A queue) 50 i, and memory-to-GCI queue (M2GCI2 queue) 50 j. It is recognized, that if needed, an additional graphics interface (i.e., GCI) beyond AGP can be used for graphics intensive applications. Each of the queues 50 shown in FIG. 2 communicate with each other through the various controllers and/or control signals routed directly between respective queues. Separating the major blocks as shown allows for a significant amount of concurrency.
Processor controller 42 controls the CPU interface and the various queues 50 linked to the CPU interface. Processor controller 42 allows the CPU (or processor) to pipeline cycles and allows several cycles to be stored within the processor controller. Additionally, processor controller 42 schedules accesses to cache storage locations within one or more processors.
Memory controller 44 controls possibly multiple banks of SDRAMs, as well as the CS, DQM, RAS, CAS, WE and CKE signals sent to those banks. In addition, memory controller 44 generates several control signals to respective queues 50 for memory data bus control. Memory controller 44 arbitrates among processor writes, processor reads, PCI writes, PCI reads, AGP writes, AGP reads, and refresh. Arbitration for each cycle is pipelined into the current memory cycle which ensures that the next memory address is available on the memory bus before the current cycle is complete. This results in minimum delay, if any, between memory cycles. Memory controller 44 is capable of reading ahead on PCI master reads and will do so if the PCI master issues a read multiple command. Interface unit 14 can then continue providing data to the PCI master at a high rate.
PCI controller 40 ensures compatible interface to the PCI bus protocol. When the processor accesses the PCI bus, PCI controller 40 operates as a PCI master. When a PCI master, (e.g., PCI I/O device) accesses memory, PCI controller 40 acts as a PCI slave. Processor-to-PCI cycles are buffered in queue 50 b and then presented to controller 40. Controller 40 must determine when this queue needs to be emptied before running in a slave mode.
Processor controller 42 can also be thought of as any device responsible for decoding processor cycles, running snoops to the processor cache storage locations, and providing miscellaneous logic such as soft reset. Functionality of a processor controller used in the bus interface unit is one which can accept cycles from the CPU bus and then parses out those cycles to the appropriate controllers 40, 44, 46 and/or queues 50. It is recognized that the processor controller consists of a number of sub-modules that can be grouped into various logic subsystems such as a processor bus tracker/queue cycle manager, a processor bus master state machine, snoop control, etc. Similar to processor controller 42, the PCI controller 40 (or the AGP controller 46) is also well known as containing a series of state machines which control the PCI/AGP interface. Data passing through the PCI controller 40 is preferably broken into three basic sub-modules: PCI master interface, PCI target (slave) interface and PCI glue logic. PCI controller 40 communicates with memory controller 44, processor controller 42 and queues 50 through various control signals internal to interface unit 14. AGP controller 46 interfaces externally to a 66 MHz, 32 bit AGP/PCI bus and interfaces internally to controllers and queues. Memory controller 44 supports AGP master reads and writes to the system memory using AGP or PCI protocol. Processor controller 42 initiates PCI protocol reads and writes to the AGP master frame buffer and registers. The various queues 50 provide data flow buffers between interfaces.
The various queues 50 can be classified as address and data queues or merely data queues depending on the flow direction of information and the controllers being linked by the respective queues. The following Table I represents a list of the various data and address queues 50, their size, and the data/address flow of each queue:
Queue Name
No. Locations
4 slots
4 cache lines
8 slots
PCI or GCI
8 quad words
PCI or GCI
2 cache lines
2 cache lines
PCI or GCI
4 slots
4 cache lines
2 cache lines
8 cache lines
2 cache lines
8 cache lines
GCI or AGP
8 slots
GCI or AGP
8 slots
8 quad words
It is recognized that numerous other queues can be employed. It is also recognized that for a PCI or AGP peripheral device to write to memory, the respective I2M queue and A2M queue transfer both address and data information before presenting that information to the memory controller 44. Information sent from PCI controller 40 (or AGP controller 46) to processor controller 42 is buffered merely as data within the I/A2P queue 50 f, and information sent from the processor controller 42 to memory controller 44 is buffered as address and data within the P2M queue 50 a.
FIG. 4 illustrates transactions occurring across the CPU bus and presented to the processor controller in timed order. More specifically, various phases of the CPU local bus is shown accommodating cycles introduced into those phases and pipelined (sequential) order. FIG. 4 indicates transaction "1" is stalled 60 when it arrives in the snoop phase. Since transaction 1 is stalled 60, all subsequent transactions are also stalled. Shown in FIG. 4 is three occurrences of stall, 60, 62 and 64 prior to the snoop phase receiving transaction 4 into the arbitration phase, as indicated by reference numeral 66. In the example shown, transaction 66 may be a transaction which must be completed through the CPU local bus as quickly as possible. According to one embodiment, transaction 66 is a cycle to local memory, and the previous cycles 1, 2 and 3 are cycles to a peripheral device connected to the PCI bus, the AGP bus or, for example, the ISA bus. Stalling the first transaction indicated by reference numerals 60, 62 and 64 allows transaction 66 to pipeline to the snoop phase, whereby the first, second and third transactions can then be deferred or retried, as indicated by reference numerals 68, 70 and 72, respectively.
Deferring or retrying the first, second and third transaction to a peripheral device places those transactions outside the in-order queue of the pipeline and affords the transaction of interest, i.e., the 4th transaction 66 to arrive on the snoop phase. Transaction 66 may then be allowed to continue throughout the pipeline to the response and data transfer phases, as shown. Being that transaction 66 is possibly a memory cycle, all caching agents are required to perform an internal snoop operation and appropriately return a hit or miss signal. Those signals are used to indicate that the cache line is either valid or invalid in the snooping agent, whether the cache line is in a modified (dirty) state within the cache line agent, or whether the snoop phase needs to be extended. The snoop phase is extended (stalled) if both the hit and hit modified (i.e., HIT# and HITM#) are sampled asserted together in the snoop phase. If both are sampled together, then the caching agent is deemed not ready to indicate snoop status, and that agent needs to stall the snoop phase. The snoop signals (HIT#, HITM# and DEFER#) are sampled again two clocks later. This process continues as long as the stall state is sampled. The snoop stall is provided to stretch the completion of the snoop as needed by any agent that needs to block further progress of snoops. As shown in FIG. 4, snoop stall is performed on the first transaction and can occur for multiple pairs of clock cycles as shown by reference numerals 62 and 64.
The DEFER# is deasserted to indicate that the transaction can be guaranteed in-order completion. An agent asserting DEFER# insures proper removal of the transaction from the in-order queue by generating the appropriate response. In FIG. 4, the transactions which are removed from the in-order queue are indicated as transactions 68, 70 and 72. There are three valid responses when DEFER# is sampled asserted (and HITM# is sampled deasserted): a deferred response implies that the operation will be completed at a later time, a retry response implies that the transaction must be completed at a later time but cannot be deferred, or a hard error response.
The transactions which are deferred are presented with a tag which indicates the responses which must be re-initiated, beginning at the arbitration phase. Those transactions are often referred to as deferred response transactions or deferred reply transactions. DEFER# is preferably asserted by an addressed input/output agent (peripheral device) if the agent is unable to guarantee in-order completion of the requested transaction. If DEFER# is sampled asserted, and HITM# is inactive, the agent asserting DEFER# must reply with a defer or retry response for that transaction. Only the addressed agent can assert DEFER#. The requesting agent must not begin another order-dependent transaction until either DEFER# is sample negated in the snoop phase, or the deferred transaction receives a successful completion via a deferred reply or a retry. FIG. 4 illustrates a deferred reply 74 progressing through the various phases subsequent to completing the non-deferred, memory-destined transaction 66. According to one implementation, and not shown in FIG. 4, deferred cycles continue to the response phase even though the data transfer is deferred relative to data transfers associated with later-presented requests. Thus, the response phase of cycles being deferred causes a "returned" response to occur. According to another implementation, a maximum of only two cycles can be deferred.
FIG. 5 illustrates an instance where a transaction is retried instead of being deferred. In the example shown, the first transaction is allowed to continue from the initial, arbitration phase through the snoop phase and onto the response phase. The first transaction is initially stalled 78, 80 and 82 until a memory-destined cycle 84 is about to enter the snoop phase. If first transaction 76 is non-deferrable, then transaction 76 progresses to the response phase 76. The response agent is then the agent responsible for completing the transaction at the top of the in-order queue (i.e., the first transaction within the response phase queue, as noted by reference numeral 76). The response agent is therefore the agent addressed by the first transaction, whereby the response agent asserts a response which indicates one of the valid transactions responses available to that agent. At least one valid transaction response is that the addressed response agent sends a retry response to the processor which can then re-initiates that transaction, as shown by reference numeral 88.
FIG. 5 indicates that if the first cycle or transaction 76 is retried, the second and third cycles do not need to be retried if they can be deferred. If the processor initiates a cycle before the end of the snoop phase of a previous cycle, the processor is indicating that there is no dependency between those cycles. Accordingly, cycles before the memory-destined cycle 84 can be deferred retried. If the cycles get retried, the processor keeps track of the order in which the transactions must be initiated back across the processor local bus. If cycles get deferred, once the cycle that got deferred completes on either the PCI or AGP bus, the bus interface unit initiates a deferred reply transaction to notify the CPU that the transaction is complete and returns data if the original cycle is a read cycle.
FIG. 6 illustrates a flow diagram of decisional activities occurring within a snoop phase. A decision must be made based on the type of cycle entering the snoop phase, as indicated by reference numeral 90. If the cycle is destined for the peripheral bus (e.g., PCI or AGP bus), and is a read cycle or a non-postable write cycle, then examination of activities 92 on the peripheral bus is needed. However, if the transaction is not destined for a peripheral bus or is a postable write, then the snoop phase is allowed to complete 94. In other words, only peripheral read cycles or non-postable write cycles can be snoop stalled.
Snoop stalling certain peripheral-destined cycles occurs only if the peripheral bus is not available, or data from the peripheral bus is not available. If the non-postable write is complete on the peripheral bus or if data arrives from the peripheral bus as a result of a read operation, then the peripheral bus is available and the snoop phase is allowed to complete. However, if those conditions do not apply, then a further inquiry 96 must be made on whether a memory cycle is present within the pipeline. If a memory cycle is not present, then the peripheral cycles are snoop stalled 98. However, if a memory cycle is present, then determination must be made on whether the peripheral cycle is deferrable 100.
Instituting a defer cycle begins by issuing 102 a DEFER# signal from the snoop agent, which causes the peripheral cycle to be drawn from the in-order queue. The snoop phase will complete and a defer response will be issued in the response phase. If the peripheral cycle is not deferrable, then the snoop phase is allowed to complete for that cycle 104. Once the snoop phase is completed, the non-deferrable cycle enters the response phase. The response agent can then assert a retry response 106.
Not only is the present deferral mechanism dynamic in that a variable snoop stall can be achieved, but also deferred transactions occur only when absolutely necessary. Transactions and/or cycles are deferred or retried only if a memory cycle is encountered. In this manner, the clock delay penalty associated with deferred or retried transactions are minimized. Accordingly, the present bus interface unit and the snoop stall, defer, and retry mechanism thereof presents faster throughput of peripheral-destined transactions relative to conventional defer operations.
It will be appreciated to those skilled in the art having the benefit of this disclosure that this inventions is believed to be capable of performing efficient transfer of peripheral-destined cycles across a CPU bus from the CPU. Various modifications and changes may be made as would be obvious to a person skilled in the art having the benefit of this disclosure. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
|Cited Patent
|Filing date
|Publication date
|Mar 1, 1994
|Nov 5, 1996
|Intel Corporation
|Method and apparatus for snoop stretching using signals that convey snoop results
|Apr 4, 1997
|Apr 7, 1998
|Intel Corporation
|Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
|Jul 29, 1996
|Aug 18, 1998
|Intel Corporation
|Highly pipelined bus architecture
|Dec 31, 1996
|Nov 10, 1998
|Compaq Computer Corporation
|Bus-to-bus bridge in computer system, with fast burst memory range
|Dec 31, 1996
|Feb 9, 1999
|Compaq Computer Corporation
|Delayed transaction protocol for computer system bus
|Mar 28, 1997
|Oct 5, 1999
|Intel Corporation
|Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
|Citing Patent
|Filing date
|Publication date
|Jul 13, 1999
|Apr 30, 2002
|Micron Technology, Inc.
|Method for supporting multiple delayed read transactions between computer buses
|Jul 13, 1999
|May 7, 2002
|Micron Technology, Inc.
|Apparatus for supporting multiple delayed read transactions between computer buses
|Feb 15, 2002
|Oct 5, 2004
|Lsi Logic Corporation
|Interface shutdown mode for a data bus slave
|Jun 25, 2002
|Dec 14, 2004
|Hewlett-Packard Development Company, L.P.
|Memory auto-precharge
|Apr 30, 2002
|Sep 20, 2005
|Lsi Logic Corporation
|Apparatus for arbitrating non-queued split master devices on a data bus
|Jun 1, 2004
|Jan 31, 2006
|Broadcom Corporation
|Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent
|Feb 28, 2002
|Feb 6, 2007
|Lsi Logic Corporation
|Look ahead split release for a data bus
|Feb 15, 2002
|Aug 21, 2003
|Stuber Russell B.
|Interface shutdown mode for a data bus slave
|Apr 30, 2002
|Oct 30, 2003
|Stuber Russell B.
|Apparatus for arbitrating non-queued split master devices on a data bus
|Jun 25, 2002
|Dec 25, 2003
|Johnson Jerome J.
|Memory auto-precharge
|Jun 1, 2004
|Nov 11, 2004
|Kruckemyer David A.
|Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent
|Feb 28, 2002
|Dec 30, 2004
|Stuber Russell B
|Look ahead split release for a data bus
|U.S. Classification
|710/311, 710/315, 711/146
|International Classification
|Cooperative Classification
|European Classification
|Sep 30, 1998
Owner name: COMPAQ COMPUTER CORPORATION, TEXAS
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text:
ROSEMONT, Ill. -- The Big Ten Experience, an interactive museum on the first floor of the league's offices, doesn't contain a Nick Saban voodoo doll or a dartboard with the SEC's logo in the bull's-eye.
I checked.
This may disappoint our friends in the South, including my ESPN colleague Paul Finebaum, but the Big Ten isn't completely obsessed with the SEC. To be clear, the Big Ten is acutely aware of the SEC's recent success in football, an unprecedented run that largely coincided with a Big Ten nosedive. Big Ten officials, including commissioner Jim Delany, understand that the Big Ten and SEC are, by far, the richest, most powerful and most popular conferences in college sports.
There's no shortage of rivalry kindling, from location to history to philosophy to coaches to results to massive fan bases incited by the mere mention of the other conference. Satellite camps, as insignificant as they are, became the latest wedge.
The Big Ten-SEC rivalry isn't going anywhere. But many Big Ten officials don't view the two leagues as diametrically opposed, even if it's how they're portrayed.
"There's a good bit of collaboration," Delany said Wednesday after the Big Ten concluded its spring meetings. "It doesn't get covered very much."
Delany, finishing his 27th year as Big Ten commissioner, recalls working with former SEC commissioner Roy Kramer to arrange bowl matchups in the early 1990s. He says there was more cooperation than discord between the leagues in shaping the College Football Playoff model. He praised the SEC for experimenting with centralized replay review this coming football season, adding that while the Big Ten isn't quite ready to take the step, it will be watching closely.
"It's natural to have a little healthy, competitive rivalry," Purdue athletic director Morgan Burke said. "But knowing most of those guys down there, they're going to compete and try to beat you on the field, but I also know they understand the importance of getting these kids educated.
"I doubt we're as far apart as people think we are."
There's a gap between the two leagues on the football field, at least in winning national championships, as the SEC boasts nine titles since 2003 (claimed by four different teams) while the Big Ten has just one in the same span. Another gulf exists with resource allocation. On average, the SEC devotes significantly more money to coach salaries and overall staff than the Big Ten.
This past offseason, two successful Big Ten defensive coordinators, Wisconsin's Dave Aranda and Penn State's Bob Shoop, left for similar posts in the SEC. Aranda more than doubled his salary by going to LSU, which will pay him approximately $1.3 million this season.
Excessive or justified, the SEC's commitment to football reflects the passion of its constituency.
"They're from a different geography than ours," Michigan State athletic director Mark Hollis said, "and maybe that geography creates some of that perceived separation, but we probably do things a little bit differently more so because of that than anything else."
Given the SEC's success in football, some argue the Big Ten should be doing more, especially with a lucrative new TV contract on the horizon. But Big Ten athletic directors like Wisconsin's Barry Alvarez don't feel that tug, whether it's paying coordinators seven-figure salaries or hiring massive staffs like Alabama's.
"Everybody wants to coach, everybody wants to have their fingers in it," said Alvarez, who coached Wisconsin from 1990 to 2005. "I don't know how you keep track of responsibilities and hold people accountable when you have so many of them around. I like to have a staff that's manageable, the number of people, whether it's recruiting, quality control. I don't even know what some of the titles are anymore. You have to be careful with that."
But other than the head-to-head competitions, like Wisconsin's season opener against LSU at Lambeau Field, its third straight against an SEC power, Alvarez isn't wrapped up in "measuring one league to another league." He and his Big Ten colleagues remain focused on building athletic programs with an array of sports, without compromising academic standards.
"Those two things," Alvarez said, "really separate us."
Big Ten athletic directors, especially those in national leadership roles, hope the regionalism that largely defines and often hamstrings college sports will erode in the coming months. They think major reforms are on the horizon, especially in areas like recruiting.
"The day of the region, I get it if you're in a region that has a population and talent, it might be a little bit different, but a majority of us don't have that," said Nebraska athletic director Shawn Eichorst, a member of the Division I football oversight committee. "You need to look at it as a national platform, just like our institutions recruiting regular students to our campuses. It's not only national. It's global. As you look at that, you have to have rules that reconcile with that and create some fundamental fairness."
It might sound like sour grapes from a school in a conference that has struggled to match the SEC on the recruiting trail. But Big Ten ADs think their SEC counterparts are more in line with the need to reform the sport.
"I know it makes for a great story, and there are situations where there's some conflict between the two conferences, but I also think there's some collegiality," said Northwestern athletic director Jim Phillips, chair of the NCAA's Division I Council. "There's mutual respect for each other and the programs that we offer. Ultimately, this is, has to be, must be, can't be anything other than what's good for college football, not what's good for a particular conference, not what's good for a particular program or a certain region.
"I'm incredibly optimistic that we're going to get there."


text:
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I'm 21 and never done it before, and not that I'm going around yammering about my lack of sexual experience, but if a girl found out would she be turned off by it and automatically rule me out?
Most Helpful Girl
I don't think so, it wouldn't bother me. Some women only want "experienced" partners but there are many others who don't care or would even prefer their partner to be inexperienced or a virgin. It's just a matter of finding the right person and someone you are compatible with. :)10|10|0


text: Glasst City was a location on the human colony Nocturne. It was known as a place of art and culture, the centre of what the Seventh Doctor termed the "Far Renaissance". Glasst City was also famed for its enclave of artists including painters, sculptors, poets, writers and composers. (AUDIO: Nocturne)


text:
"The dentist showed great patience"
About: Specialist services / Special needs dental service/Community Dental Service Specialist services Special needs dental service/Community Dental Service
Posted by Aislyn (as ),
My daughter is 16 and has a needle phobia. She was told she needed 4 teeth out so she could have a brace. After struggling to find out about a service for children with needle phobias as our dentist was either quite unhelpful or oblivious to what services are available, we were referred to the special needs dental service at Park House practice in Carlton Nottingham by her orthodontist Dr Kaur at 'Orthoworld' Nottingham.
My daughter had two visits with two extractions at each and her dentist 'Lauren' was so lovely. She along with her nurse 'Loz' made my daughter feel relaxed and calm by taking the time to explain everything to her clearly and showed great patience with her anxiety.
We both just want to thank them sincerely and say what a great service they offer. I never would have expected her to go through with it but she did and it was totally painless for her and not at all traumatic. Thank you so much! !
Response from Jane Walker, Dental Nurse Manager, Integrated Dental Unit, County Health Partnerships 2 years ago
Thank you for taking the time to give such wonderful feedback regarding your daughter treatment at Park House Carlton.
It is good to hear that Lauren and Loz were able to explain everything and show patience with your daughter to enable her to have her extractions carried out.
I will share your kind words with the team at Park House
- {{helpful}} of {{total()}} people think this response is helpful
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text:
West Hollywood Russian Vodka Protest Was Fake
WeHo Bars Protest Against Anti-Gay Legislation in Russia This Thursda.
The Boston Tea Party saw protesters dump valuable and beloved tea into the harbor Dec.16, 1773. Americans were tired of British "taxation without representation," and they put their principles into action by throwing the imported elixirs into the sea.
Today protesters are mirroring that historic day with a protest against imported vodka: Russia recently enacted a law against gay "propaganda," and the country has seen violence and hostility toward the LGBT community:
What better way to say nyet to that shit than with a boycott against Stoli and Russian Standard, beverages that today are valuable and beloved? The spirits were to be poured down the gutter at 11 a.m. today.
Except that it was all fake:
The pricey vodka was not actually poured into the gutter. Organizers said in a statement that "bottles will actually contain water due to environmental regulations."
Uh. Yeah.
We asked, What regulations? There are no such things. After all, cops will tell you to pour your beer out in a heartbeat if they catch you brown-bagging it on the street.
A spokesman pointed us to a list of state restrictions on sewage dumping that contained a section on ethanol, adding:
Sure. Maybe they were also concerned with the bottom line.
The City of West Hollywood, L.A. Pride producer Christopher Street West, bar owners and other LGBT activists gathered in front of Micky's bar in Boys Town to do the deed this morning "as a symbol of support for the Russian LGBT community and its allies," according to a statement.
Of course it was all -- oh, what's the technical term for a fake protest? -- bullshit.
So the next time you're in a WeHo bar drinking Stoli and cran, you'll know why there was no short supply.
Send feedback and tips to the author. Follow Dennis Romero on Twitter at @dennisjromero. Follow LA Weekly News on Twitter at @laweeklynews.
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