text:
|Publication number
|Publication type
|Application number
|Publication date
|Oct 17, 2000
|Filing date
|Oct 23, 1997
|Priority date
|Oct 23, 1997
|Fee status
|Publication number
|Nanda Gopal
|Original Assignee
|Intel Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (10), Non-Patent Citations (10), Referenced by (31), Classifications (6), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention is in the field of circuit simulation. More particularly, the present invention is in the field of simulating very large, hierarchical resistive circuits.
The performance of today's very large scale integrated circuits is improved by employing combinations of increased operating frequencies and increased circuit complexity as well as by decreasing on-chip feature dimensions and supply voltages. The consequential increase in the resistive nature of the power supply network, easily one of the most critical networks in the circuit, results in an increased susceptibility to serious problems such as electromigration, overheating, and drop in voltage levels in power rails toward the center of the integrated circuit ("voltage droop"). These problems have been well known in the industry to adversely effect the reliability and operation of the circuit. For these reasons, reliability verification prior to fabrication is recognized as an essential stage in the design process.
A consequence of increasing size and complexity in integrated circuits is that existing reliability verification tools are literally overwhelmed when presented with some of today's very large scale integrated circuits.
In the case of verifying power networks, reliability verification tools typically comprise computer programs for circuit simulation. These circuit simulation tools operate on a model of the power network as a description of hierarchical resistive circuits. Hierarchical resistive circuits are characterizations of a circuit as networks of resistances connected by nodes. As is known in the art, such networks are connected to voltage supplies, or source voltages, and in operation have particular currents flowing through each resistance and certain voltages at each node. The currents are known as branch currents, where a branch connects two nodes, and the voltages are known as node voltages. Hierarchical resistive networks are divided into levels of hierarchy, usually on the basis of particular functions of subcircuits. The subcircuits are known as macro circuits or macros. For example, a macro circuit with the function of a comparator would contain within it, at lower level(s) of hierarchy, the circuits representing the logic gates that make up the comparator. The circuit simulation tools simulate the behavior of the model circuit under actual source voltages with the object of obtaining branch currents and node voltages. Once branch currents and node voltages are obtained it is possible to determine power levels at various area in the circuit using well known equations. Thus, it can be determined if there will be overheating problems, voltage droop problems or electromigration problems. In this way, a circuit designer tries to obtain enough information to adjust the design of the circuit before the cost of fabrication is incurred.
Current simulation tools simulate the behavior of the resistive circuit only by removing all hierarchical information (flattening the circuit) and solving for node voltages and branch currents by constructing and solving a matrix according to well known circuit analysis techniques. As circuits become larger and more complex, however, the matrix becomes prohibitively large to store and solve. Very large matrices require not only large amounts of storage space but also long periods of time to solve. For example, a circuit with 1000 nodes (a modest number in comparison to the total number of nodes in a very large integrated circuit), the size of a full admittance matrix, such as is commonly used with current simulation tools, is one million numbers. It is currently possible, according to known techniques, to partition the flattened circuit into more manageable chunks. This partitioning, however, is very dependent on circuit topology and suffers from other disadvantages, such as loss of original hierarchical information, as further described below.
Loss of original hierarchical information is a serious disadvantage of present simulation tools. For instance, when existing simulation tools flatten the hierarchical resistive circuit, no hierarchical information is saved. For this reason, when voltage droop is discovered at a particular node or electromigration is discovered at a particular resistance, even though the resistance or node may be eventually identified, its original hierarchical name or identifier has been lost and can only be recovered through the development and use of software tools designed for the purpose. This is costly in terms of time and effort. Very large integrated circuits are commonly designed using teams of designers, each working on different parts of the integrated circuit. When problems that require re-design, such as voltage droop or electromigration, are discovered the designer or team of designers that owns the part of the overall integrated circuit must be identified. It may be difficult to identify the owners of the problematic part of the circuit when original hierarchical information is no longer available.
Another significant limitation of existing simulation tools is their inability to identify and handle floating nodes before simulation actually takes place. This is significant because when floating nodes exist in the circuit (that is, nodes which are not connected to a reference voltage via a direct current (DC) path) current simulators fail completely. In addition, such a failure may not be immediately traceable to the floating node or nodes. Floating nodes are a possible cause of, for example, anomalous results of timing simulation. Because floating nodes are such a problem, it is commonly necessary to write scripts to try to identify floating nodes before they cause testing to fail. Although floating nodes are undesirable because they can introduce capacitive effects that seriously affect integrated circuit performance, they are commonly introduced by accident in the design process.
Another disadvantage of existing simulation tools is their inability to efficiently and accurately handle short circuits in the resistive circuit. Typically, existing simulation tools identify shorts and handle them by inserting an extremely small resistance in the place of each short. This method of handling shorts has at least two problems. First, the resistance that is used in these methods does not accurately reflect the resistance in a short circuit. Short circuits have zero resistance and zero voltage. For instance, because voltages are arrived at by dividing current by resistance, a very large, but inaccurate, current will be assigned to short circuits. Second, because the typical method of obtaining node voltages and branch currents for resistive circuits is to solve a matrix, the extremely small resistance numbers will cause the matrix to be ill conditioned, thus introducing potentially significant numerical errors.
The present invention overcomes the problems described above by employing efficient recursive techniques that avoid the solution of large matrices, handle shorts and floating nodes effectively, and retain hierarchical information in a final solution of an entire resistive circuit.
A computer implemented method for simulating a resistive circuit, including a plurality of macro circuits that are arranged hierarchically is described. The method includes the steps of reading a netlist description of the resistive circuit and recursively traversing the resistive circuit starting from terminal nodes of a macro circuit at a highest level of hierarchy using precharacterizations of each of the plurality of macro circuits to determine node voltages and branch currents of the resistive circuit.
FIG. 1 is a circuit diagram of a resistive circuit according to one embodiment of the present invention.
FIG. 2 is an example of the syntax of an input file operated on according to an embodiment.
FIG. 3 is an overview flow diagram of a simulation method according to one embodiment.
FIG. 4 is a flow diagram of reading an input netlist and translating the input netlist according to one embodiment.
FIG. 5 is an example of a node map according to an embodiment.
FIG. 6 is a flow chart of compiling node information for each macro according to one embodiment.
FIG. 7 is an example of a shorted node map according to one embodiment.
FIG. 8 is a flow diagram of detecting floating node clusters according to one embodiment.
FIG. 9 is a flow diagram of labeling flat nodes with IDs based on connectivity according to the embodiment of FIG. 8.
FIG. 10 is a flow diagram of detecting floating node clusters according to one embodiment.
FIG. 11 is a flow diagram of computing a direct current ("DC") solution for the entire resistive circuit according to one embodiment.
FIG. 12 is a flow diagram of precharacterizing a macro using a DC solution technique.
FIG. 13 is a flow diagram of a DC solution technique of one embodiment.
FIG. 14 is a diagram of compressed circuit generated from a y-parameter matrix.
FIG. 15 is a flow diagram of a DC solution technique of another embodiment.
FIG. 16 is an example of matrix elements selected for storage according to one embodiment.
FIG. 17 is an example of an output file according to one embodiment.
FIG. 18 is another example of an output file according to one embodiment.
A circuit simulation method for evaluating the performance and reliability of a very large microelectronic circuit or system prior to its fabrication is described. The method includes the transformation, storage, and analysis in a computer of a representation of a hierarchical resistive network with independent voltage and current sources. Subcircuits, or macros, representing hierarchical blocks are transformed into macro models based on terminal parameters, which are temporarily stored on disk in a more compact manner than in conventional methods.
In one embodiment, an efficient recursive procedure is employed to compute node voltages and branch currents through every element (herein an element is a resistance) in the network, without actual instantiation of each macro along with its internal elements and nodes, as required in a conventional circuit simulation. A complete DC solution of an entire circuit is obtained by performing an ordered traversal of the circuit hierarchy and employing a series of local solutions computed at each level of hierarchy using the macro models.
The present invention provides the ability to handle the serious problems of floating nodes and short circuits. In the case of floating nodes, for example, floating nodes are identified in a preprocessing step and connected to a voltage source so that singularities that are typically fatal to the analysis process are avoided.
The resulting output contains all the voltages and currents in the network in association with all the hierarchical information of the original network.
FIG. 1 is a circuit diagram of a hierarchical resistive network analyzable using the simulation method of one embodiment of the present invention. Circuit 100 of FIG. 1 is an example that is useful for illustrative purposes, but actual resistive networks representing models of power networks in actual high performance very large microelectronic integrated circuits are much larger and include many more levels of hierarchy and many more resistors than are shown in FIG. 1.
Resistive circuit 100 includes two levels of hierarchy. A top level of hierarchy, labeled "top", includes one instance of macro M2. A macro is typically a subcircuit performing a particular function in the overall integrated circuit. A particular macro may be repeated many times on an integrated circuit. Each time a particular macro occurs it is an instance of the macro. For example, in resistive circuit 100 the occurrence of macro M2 is denoted "top". At the next level of hierarchy, that is, the level of hierarchy below top, occur two instances of macro M1. These are instances 1 and 2, labeled I1 and I2. Resistive circuit 100 has three independent voltage sources 1, 3, and 4, and one ground, GND. The primary terminals of instance top of macro M2 are terminals 1, 2, 3, 4 and 5. Terminals, or nodes, internal to instance top of macro M2 but not internal to instances of macro M1 have two node labels. These are symbolic node labels that both enumerate the node and convey hierarchical information. For example, node 1, which is primary terminal 1 in instance top of macro M2, is also node NN1 of macro M2. Similarly, primary node N1 of instance 1 of macro M1 is node NN6 of macro M2. All nodes of resistive circuit 100 are similarly labeled with hierarchical information. Resistive circuit 100 includes four nodes which are not connected to any voltage source. An example of such a node is node DUM1 of instance 1 of macro M1 which is also node NDUM1 of instance top of macro M2. Resistive circuit 100 also includes some circuit anomalies. These are a short circuit between nodes NN4 and NN9 of instance top of macro M2, and a floating node cluster between nodes NN2 and NN13 of instance top of macro M2. Resistive circuit 100 will be used as an example herein to illustrate embodiments of the present inventions.
FIG. 2 is a text description of a circuit to be analyzed according to one embodiment of the present invention The text description of FIG. 2 is a description of resistive circuit 100 and constitutes the input operated upon in one embodiment of the present invention. The present invention operates upon text descriptions, such as the description of FIG. 2, that are generated by commercially available network extractors. Description 200 is a description of macro M1. Description 200 shows primary terminals 202 labeled with their names as they appear with respect to macro M1. Description 200 also shows all the resistances present in macro 1, for example R1 is situated between nodes N1 and N5 and is a resistance of 15 ohms. When macro M1 has been fully described, the end of macro (EOM) designation is written. Description 204 is the text description for macro M2 of resistive circuit 100. It is described in the same syntax as description 200. It is seen in description 204 that macro M2 and instances of macro M1 share common nodes with different names. For instance, primary node N1 of instance @ I1 of macro M1 is designated node NN6 in macro M2 (which is one terminal of resistor R1 in macro M2). Macro M2, as shown in description 204, includes two instances of M1, labeled @ I1 M1 and @ I2 M1. The descriptions of the two instances of M1 include only the external nodes of M1, that is the nodes seen by macro M2. Description 208 describes independent voltage sources V1, V3 and V4. Voltage source V1 is described as a DC voltage source between node 1 of macro M2 and ground, with a value of one volt. Voltage sources V3 and V4 are similarly described. Finally, description 210 shows the instantiation of instance top of macro M2, designated @ top M2. This instance description includes primary terminals 1, 2, 3, 4 and 5 of instance top of macro M2. The word END designates the end of the entire description of resistive circuit 100.
FIG. 3 is an overview flow diagram of a method of simulating resistive circuit 100 according to one embodiment of the present invention. The process of simulating resistive circuit 100 begins at step 300. The input netlist of FIG. 2 is translated into internal data structures at step 302.
Next, at step 304, node information is compiled for each macro defined. Next, at step 306, floating node clusters in the circuit are detected. At step 308, a DC solution is computed for the entire resistive circuit using a DC solution technique. As will be explained more fully below, different embodiments use different DC solution techniques. The chosen DC solution technique is first used to find "local" or macro level solutions for terminal node voltages using unit voltage sources. At step 308, actual node voltages are applied to external nodes of the resistive network and the local solutions are used in a recursive traversal of the resistive circuit until all node voltages and branch currents are determined. When all node voltages and branch currents are determined, the process goes to end 310.
FIG. 4 is a flow diagram showing in more detail the steps included in step 302 of FIG. 3, reading and translating the input netlist. The start of step 302 is shown as block 402. At block 404 it is stated that the subordinate steps, steps 406, 408, 410, 412 and 414 are executed for each macro definition. For each macro definition, at step 406, symbolic nodes are mapped to numeric nodes.
Referring now to FIG. 5, an example of a node map for resistive circuit 100 is shown. Symbolic node names are mapped into consecutive numeric indices for easy manipulation and analysis. Each macro description, as well as the top level circuit, has a separate node map. As shown in FIG. 5, node map 502 is the node map for macro M1, and includes the symbolic node names of macro M1 on the right and the consecutive numeric indices corresponding thereto on the left. Similar node maps 504 and 506 are included for macros M2 and for the top level circuit, respectively.
Referring again to FIG. 4, after symbolic nodes are mapped to numeric nodes at step 406, a primary terminal list is created at step 408. The primary terminal list includes only primary terminals for each macro of resistive circuit 100 and for the top level circuit 100 itself. Next, at step 410, a list of resistors that do not have a zero resistance value is created. At step 412 a list of instances is created. For example this would include instances @ I1 and @ I2 of M1 and instant @ top of macro M2. At step 414 a list of shorts is created. This list includes all resistances that have a value of zero. After the creation of the short list, the translation that occurs for each macro definition is at end 426.
Following start 402, block 416 designates that following steps 418, 420, 422 and 424, occur for each instance definition. At step 418 a pointer is set to an associated macro definition. Next, a terminal list for each instance is created at step 420. For example, instances @ I1 and @ I2 of macro M1 would have their own terminal lists. Next, at step 422, the terminal count is verified with macro definitions. Next at step 424, the terminal count is appended to the appropriate instance list, and the processing of each instance definition for step 302 is at end 426.
FIG. 6 is a flow diagram showing detail of step 304 from FIG. 2, compiling node information for each macro definition. Block 606 is the start of compiling node information for each macro definition. First, at step 608, an equivalency node vector is created with all entries initialized to -1. -1 is an arbitrary choice and could be any other designation. -1 is chosen in this case because it is not easily confused with other designators used in data structures of the present invention because other designators are typically nonnegative. Next, at step 610, it is determined whether there are any shorts in resistive circuit 100. If resistive circuit 100 contains no shorts, the process goes to end 624. If resistive circuit 100 does contain shorts, the process moves to block 612 where procedures are followed for each shorting resistance. Steps 612, 614, 616 and 618 constitute a loop that is repeated for each shorting resistance. At step 614 the i-th entry in the equivalency node vector is set to j (or its equivalent node if is part of a short circuit). At step 616 terminal nodes i and j are fetched and at step 618 there is a check for a self loop, and a check for whether nodes i and j are already shorted. At step 619 it is determined whether all shorts have been processed. If all shorts have not been processed, then the loop of steps 612, 614, 616 and 618 is repeated for another set of nodes. If all shorts have been processed, the process moves to step 620 where primary terminals are renumbered with equivalent node numbers. At step 622 element terminals with equivalent node numbers are renumbered. In this embodiment, elements are resistors. After renumbering, the process is at end 624.
FIG. 7 is an example of a shorted node map produced by the process described in FIG. 6. Shorted node map 700 is a shorted node map for macro M2. As shown, all nodes are labeled on the left with their sequential numbers. These are the sequential numbers that replace the symbolic numbers used earlier in the process. On the right hand side, a -1 corresponds to each node that is not equivalent to another node. As shown in resistive circuit 100, there is a short circuit between nodes NN9 and NN4 of macro M2, which have been renumbered 9 and 4. Therefore, node 9 is listed in the shorted node map as being equivalent to node 4.
Two methods of performing step 306 of FIG. 3 according to two embodiments will be described. FIG. 8 is a flow diagram showing detail of method 306a of performing step 306 of FIG. 3 according to one embodiment. Method 306a detects floating nodes by performing a efficient recursive traversals of the circuit hierarchy. Node maps are created, and all nodes are mapped to flat nodes. It is then possible to label nodes with IDs based on their connectivity. Then a traversal of the circuit is started from a ground node. In a fully connected circuit, all nodes will have a same ID as the ground node after a complete traversal. If there are floating nodes, however, the floating nodes will have different IDs from the ground node, and clusters of floating nodes will share a same ID. According to this embodiment, only a single vector of length equal to the total number of flat nodes is sufficient to store the IDs of the flat nodes, making this embodiment very storage efficient. The method of FIG. 8 can be viewed as "virtual" flattening of the circuit because no resources are used to store a flattened circuit.
From start 1600, nodes are instantiated and instance nodes are mapped to flat nodes at step 1602. Next, flat nodes are labeled with IDs based on connectivity at step 1604. For each floating node cluster detected, as shown in step 1606, the node at the highest level of circuit hierarchy is found at step 1608, and the process comes to end 1610.
FIG. 9 is a flow diagram showing detailed steps included in step 1604 of FIG. 8 (labeling flat nodes with IDs based on connectivity). From start 1612, a ground node is labeled with an ID of "1". The actual ID is arbitrarily chosen and could be any other ID. For each level of hierarchy, as indicated by step 1616, steps are performed for each element at the level of hierarchy as indicated by step 1618. An element herein is a resistive element. At step 1620, terminal nodes and associated flat nodes are determined, where flat nodes are denoted n1, n2, and so on. At decision block 1622, it is determined whether node n1 has a label L1. The label L1 is arbitrarily chosen and could be any label previously given to node n1. If node n1 has label L1, then, at step 1624, occurrences of label L2 are changed to label L1. If n2 does not have label L2, then, at step 1628, node n2 is labeled as L1. Referring again to decision block 1622, if node n1 does not have label L1, then it is determined at step 1630 whether node n2 has label L2. If node n2 has label L2, then at step 1632, node n2 is labeled as L2. If node n2 does not have label L2, then at step 1634, nodes n1 and n2 are labeled with a new label. Step 1622 and the steps performed after the decision of step 1622 assure that connected nodes that are encountered during a walkthrough of the circuit from a ground node have the same labels. For example, in the case of step 1626, the labels are found to be different and so they are merged. In the case of step 1634, a label could not be determined for either node, so the nodes are given a same new label.
For each instance as shown starting with step 1636, it is next ensured that each terminal of each instance has a label. Each terminal must have a label or the labels cannot be propagated internally as required, for instance, in order to determine which nodes are connected to ground at higher levels of hierarchy. Unlabeled nodes are identified by another arbitrary ID, for example "0". When such a node is encountered, it is given a new, previously unused label.
FIG. 10 is a flow diagram showing detail of method 306b of performing step 306 of FIG. 3 according to a different embodiment from the embodiment of FIGS. 8 and 9. Method 306b includes flattening the entire circuit and temporarily storing a connectivity graph. This method therefore requires more storage than method 306a and also incurs the performance penalty of allocating and deallocating memory for storage of the connectivity graph.
From start 802, the circuit is flattened and a connectivity graph of the circuit is built at step 804. As is known, a connectivity graph merely shows what each node in the circuit is connected to. Next, at step 806, the connectivity graph is traversed from ground and all nodes encountered are labeled with subgraph identifiers (ids). Then, at step 808, all subgraphs with ids that are not equal to the ground subgraph id are printed for later reference. At step 810, the circuit graph is deallocated from system memory before end 812. This frees memory for other purposes.
According to this embodiment, a connectivity graph is used rather than a walkthrough of nodes labeled according to connectivity, as in the previously described embodiment. Therefore, in this embodiment, is necessary to flatten the circuit in order to detect floating nodes because floating nodes cannot be detected by examination of a macro circuit alone. This is because, based on the connection of the macro and its containing macro and so on, a node cluster that is not floating at one level of hierarchy may, in fact, be floating at another level of hierarchy. In the example of resistive circuit 100, nodes NN2, NN7 and NN13 of instance top of macro M2 and nodes N3, N6 and N4 of instance I1 of macro M1 are not connected to the ground or to any input voltage source, and are hence floating. During traversal of the graph as in step 806, all of the nodes in the floating node cluster will receive the same label, or subgraph id. Therefore, each floating node cluster will have its own subgraph id which is not the same as the ground subgraph id. These floating node clusters are handled by grounding the node at the topmost level. It is not necessary to ground every node. In this way, numerical singularities in the circuit matrix to be developed later are prevented. For the particular node cluster of resistive circuit 100 it is only necessary to store node 2 at the topmost level.
FIG. 15 is a flow diagram showing detailed step of step 308 of FIG. 3, computing a DC solution for the entire resistive circuit using a DC solution technique. The process begins at block 902. For each instance of a macro at the top level of hierarchy, as indicated by block 904, multiple steps are followed. For each instance at the top level, external voltage stimuli are applied at the primary terminals of the instance at step 906. The voltage stimuli are actual operating voltage known to be applied at the terminals of the top level instances when the circuit is operational. At step 908, a macro definition for the instance is acquired from a storage device. For each instance J in the macro M, as indicated in step 910, several subordinate steps are taken. "J" and "M" denote variables that take on progressively greater values in the recursive procedure of FIG. 11. For each instance J in macro M, an associated macro definition is acquired at step 912. Then, at step 914, it is determined whether a macromodel MJ exists. If the macromodel does exist, the process returns to step 910 to get a next macro definition M. If the macromodel does not exist. The macromodel MJ is precharacterized using a DC solution technique at step 916. Steps 910, 912, 914, and 916 are repeated for all macro definitions M.
After all macromodels are acquired and all macros not having macromodels are precharacterized, for each top level macro a solution is found giving all internal node voltages of the instance using the DC solution technique at step 920. All node voltages and element currents are then written to a file. For each instance J in macro MI, as indicated at step 924, voltage stimuli are applied at all terminals of instance J from the solution found in step 920. As indicated by arrows from step 920, appropriate steps are repeated for each top level instance and for each macro definition. The process is then at end 902.
FIG. 12 shows detailed steps of step 916 of precharacterizing a macro using a DC solution technique. From start 1002 of FIG. 12, zero voltage sources are assigned to primary terminals of the macro. Next, for each voltage source at a terminal, as indicated at step 1016, several subordinate steps are taken. At step 1018, a unit voltage source is assigned with all other sources shut off. The system is then solved for currents through all terminal voltage sources at step 1020. It is determined at step 1022 whether there is current flowing from the voltage source to the terminal. If there is voltage lowing, then at step 1024 the y-parameter matrix for the macro is written to a macromodel file and another voltage source is acquired at step 1016. If there is no current flowing, then the terminal is marked as isolated at step 1026 and another voltage source is acquired at step 1016. When all voltage sources have been handled, the process is at end 1028.
FIG. 13 is a flow diagram showing the steps of DC solution technique 1020a of one embodiment. From start 1500, a path trace entry is created for each resistance at step 1502. A path trace entry is an internal data structure, typically a vector, that represents the resistance. Next, at step 1504, a compressed circuit is created from a y-parameter from the macromodel file for each instance. At step 1506, a path trace entry is created for the voltage source for each terminal. A path trace is then performed according to known methods at step 1508, and the process goes to end 1510.
FIG. 14 is a diagram of a compressed circuit generated from a y-parameter matrix. Y-parameter matrix 1702 is an example of an y-parameter matrix created for a macromodel. Circuit diagram 1704 is an equivalent, compressed circuit created using y-parameter matrix 1702. The resistance values are shown as equations derived from y-parameter matrix 1702. Compressed circuit 1704 represents one of many small compressed circuits that make up a typical resistive circuit. According to the path tracing technique of the presently described embodiment, the nodes of compressed circuit 1704 are stepped through for the purpose of determining node voltages and branch currents. According to this method of generating a compressed circuit, the resistive circuit has no more nodes than the number of terminal nodes of the macro, which makes the analysis process faster and simpler than alternate methods that include nodes internal to a macro.
FIG. 15 is a flow diagram showing the steps of DC solution technique 1020b of another embodiment. DC solution technique 1020b, in general, uses a matrix solution technique. The decision whether to use a path tracing technique or a matrix solution is dependent on several factor, including circuit size and topology. System limitations may also be a factor. For example, matrix solutions employ sparse matrices that are not very efficient in terms of speed, but consume slightly less storage.
The process of DC solution technique 1020b begins at block 1102. Note that 4 parameters refers to "admittance of a circuit such as current/voltage including phase therebetween." First, at step 1104 a sparse matrix is initialized. Next at loop 1106, for each resistor in the macro, step 1108 of stenciling an admittance model into the matrix is performed. The admittance model is arrived at by using the resistances, which are known, and the well known equation for admittance, and constructing a matrix according to well known techniques. The next loop in the process is loop 1110, in which step 112 of stenciling a y-parameter macromodel of an associated macro MJ into the matrix is performed for each instance J in the macro. Next, loop 1114 is performed, wherein step 1116, stenciling a voltage source model into the matrix, is performed for each terminal in the macro. Finally, the matrix is factored at step 1118 and the process is at end 1120.
The present invention has been described with respect to a particular embodiments demonstrating that a very large hierarchical resistive circuit is analyzed and simulated much more quickly and with much less memory usage than is possible with conventional simulation tools. As has been shown, the present invention exploits the hierarchical nature of the resistive circuit by characterizing each macro in terms of behavior at its primary terminals. In this way, it is not necessary to flatten the entire circuit or create huge, unmanageable matrices with impossibly large numbers of nodes.
An advantage of the present invention is the way in which memory usage is reduced. One way in which memory usage is minimized is that data structures which are not required throughout the entire process are not stored. For instance, when the circuit is flattened during handling of floating nodes according to the embodiment of FIG. 10, the flattened circuit characterization is not stored after the floating nodes have been detected. In addition, when y-parameter macromodels have been created, they can be written to disk and later referenced rather than using local memory. Further, macromodel storage is made as economical as possible by storing only nonzero, nonredundant elements of the matrix. This is illustrated by FIG. 16.
FIG. 16 shows an exemplary 8�8 y-parameter matrix. It is not necessary for the cases encountered in analysis of resistive circuits to store all the entries of the y-parameter matrix. For the cases considered herein, the y-parameter matrix is symmetric about the diagonal. As such, this reduces the size of the matrix almost by half because it is only necessary to store the diagonal and the lower triangle of the matrix. In addition, due to the nature of connections typically encountered in the circuits considered, the y-parameter matrix has entries clustered mostly about the diagonal. Therefore, when each column of the y-parameter matrix, rather than the entire column below the diagonal is stored, the highest row in the column that has a nonzero entry is located. Only entries up to that point are stored. This method has been extremely effective as a data reduction heuristic, yielding reductions in data size of up to ninety (90) percent.
In FIG. 16, Xs in the matrix denote the presence of nonzero entries. To store the matrix in its entirety would require storage for sixty-four (64) numbers. Since the matrix is symmetric, storing only the diagonal and the lower triangle would require storage for only eight (8) plus twenty-eight (28), or thirty-six (36) numbers. This represents a reduction of storage space required of 43.75%. Further, recognizing that in each column it is unnecessary to store zero values, only the shaded subcolumns need to be stored, as explained previously. In this case, the total number of entries would be seventeen (17), representing a reduction of over 73% in storage space required. Each column also requires an additional integer to be stored specifying the number of entries below the diagonal that are stored. In one embodiment, y-parameters are written out to disk rather than stored in memory, and are reused as needed. This allows for fast reads and writes and further reduces demands on computation resources.
As previously mentioned, the present invention as described yields node voltages and branch currents for resistive circuit 100 or any resistive circuit that is simulated. The present invention provides distinct advantages over conventional methods because the output information retains hierarchical information as it appears in the input text description, or netlist. FIG. 17 shows output file 1300. Output file 1300 reflects the results of performing the steps of FIG. 3 on resistive circuit 100. As shown, output file 1300 displays instance name, macro name, original resistance number, original voltage source number, and corresponding current and resistance information. For example, instance top of macro M2 shows a current of 1.2346 e-02 amperes through resistor R1. Upon examining output file 1300, a designer can observe unacceptable results, for example an excess of current through a particular resistor, and re-design accordingly. The location of the particular anomaly is easily identified because the original hierarchical information is intact.
FIG. 18 shows output file 1400, which is another example of output resulting from execution of the steps of FIG. 3. Output file 1400 lists DC voltages in association with hierarchical information, including a particular instance, index, and node name for each DC node voltage.
Although the present invention has been described in terms of specific embodiments. For example, the embodiment described produces branch current and node voltages for a resistive circuit. Various modification and alterations might be made by those skilled in the art, however, without departing from the spirit and scope of the invention as set forth in the following claims.
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|Micron Technology, Inc.
|System and method for scoping global nets in a hierarchical netlist
|Behrens et al., Computer Aided Design, 1996, ICCAD 96, IEEE/ACM Int. Conf., Hierarchical partitioning , pp. 470 477, Nov. 1996.
|Behrens et al., Computer-Aided Design, 1996, ICCAD-96, IEEE/ACM Int. Conf., "Hierarchical partitioning", pp. 470-477, Nov. 1996.
|Grebene, Northcon/94, "A methodical approach for macromodeling of analog circuits", pp. 205-210, Oct. 1994.
|Grebene, Northcon/94, A methodical approach for macromodeling of analog circuits , pp. 205 210, Oct. 1994.
|Karnik et al, ASIC Conf. and Exhibit, 1994, Proc. 7th Annual IEEE Int., Hierarchical mixed level simulation of VHDL decriptions, pp. 170 173, Aug. 1994.
|Karnik et al, ASIC Conf. and Exhibit, 1994, Proc. 7th Annual IEEE Int., Hierarchical mixed-level simulation of VHDL decriptions, pp. 170-173, Aug. 1994.
|Schulz et al., European Test Conf., 1989, "Hierarchical fault simulation in combinational circuits", pp. 33-40, Apr. 1989.
|Schulz et al., European Test Conf., 1989, Hierarchical fault simulation in combinational circuits , pp. 33 40, Apr. 1989.
|Yoon, Circuits and Systems, 1994, Proc. of 37th Midwest Symposium, "Electrical simulation and analysis of large complex electrical systems", vol. 1, pp. 697-700, Aug. 1994.
|Yoon, Circuits and Systems, 1994, Proc. of 37th Midwest Symposium, Electrical simulation and analysis of large complex electrical systems , vol. 1, pp. 697 700, Aug. 1994.
|Citing Patent
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|Oct 19, 2010
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|Method for symbolic simulation of circuits having non-digital node voltages
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|International Business Machines Corporation
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|Simulation of circuits with repetitive elements
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|May 8, 2003
|Goetz Leonhardt
|Automatic generation of reduced-size circuit models including inductive interaction
|Sep 5, 2002
|Mar 11, 2004
|Sun Microsystems, Inc., A Delaware Corporation
|Self adjusting linear MOSFET simulation techniques
|Jul 29, 2003
|Feb 3, 2005
|Telefonaktiebolaget Lm Ericsson (Publ)
|Symbolic analysis of electrical circuits for application in telecommunications
|Dec 17, 2003
|Jun 23, 2005
|International Business Machines Corporation
|Method, system, and product for verifying voltage drop across an entire integrated circuit package
|Feb 15, 2005
|Jun 30, 2005
|Cadence Design Systems, Inc.
|Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
|Feb 15, 2005
|Jul 7, 2005
|Cadence Design Systems, Inc.
|Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
|Feb 15, 2005
|Jul 7, 2005
|Cadence Design Systems, Inc.
|Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
|Jan 13, 2006
|Jul 20, 2006
|Legend Design Technology, Inc.
|Methods for fast and large circuit simulation
|Aug 17, 2005
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|Synopsys, Inc.
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|U.S. Classification
|703/14, 703/18, 703/17
|International Classification
|Cooperative Classification
|European Classification
|Oct 23, 1997
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GOPAL, NANDA;REEL/FRAME:008870/0577
Effective date: 19971021
|Apr 19, 2004
|Fee payment
Year of fee payment: 4
|Apr 11, 2008
|Fee payment
Year of fee payment: 8
|Apr 11, 2012
|Fee payment
Year of fee payment: 12


text:
1.North America is the continent
2.when it comes to Barbados exports, it is estimated than the annual amount is around $385 million. Accounting for this are various stuff to include sugar/molasses, rum, manufactured goods, electrical components, and chemicals.
3.The commodities imported include foods, materials for construction, consumer goods, machinery, electrical components, fuel, and chemicals.
4.national anthem
In plenty and in time of need
In plenty and in time of need
When this fair land was young
Our brave forefathers sowed the seed
From which our pride is sprung
A pride that makes no wanton boast
Of what it has withstood
That binds our hearts from coast to coast
The pride of nationhood
We loyal sons and daughters all
Do hereby make it known
These fields and hills beyond recall
Are now our very own
We write our names on history's page
With expectations great
Strict guardians of our heritage
Firm craftsmen of our fate
The Lord has been the people's guide
For past three hundred years
With him still on the people's side
We have no doubts or fears
Upward and onward we shall go
Inspired, exulting, free
And greater will our nation grow
In strength and unity
5.electricity-The voltage on Barbados is 110 volts. Adapters for electrical equipment are not necessary.
6.Currency-bajan dollar, coins 1, 5, 10, 25 cents and 1$
dollars 2, 5, 10, 20, 50, and 100 dollar bills
1 bajan equals 50 cents in the US
The price of stuff in Barbados is more than the US by 2 to 3 USD (American dollars)
7.Religion-Religion in Barbados. According to the 2000 official census, more than 95 percent of the population of Barbados is considered Christian, although persons may not be active in any particular denomination.
8.the official language of Barbados is english
9.The best time to visit Barbados is July to November. Hurricanes they rarely hit the island, and you could attend one of the lively festivals if you vacation at that time of year. Temperatures stay between the mid 70s and mid 80s year-round, so there's really very little reason to travel during the peak season from December to April.
10.passports and visa-Every person entering Barbados, including all North American citizens (Americans and Canadians),should be in possession of a valid passport and a valid return ticket.
11.natural hazards-infrequent hurricanes; periodic landslides
12.Barbados is about the size of a county in Kansas
13.population- is 283,221
14.The capital is bridgetown
15.Barbados is a constitutional monarchy
16.The time in barbados is 1 hour faster than kansas
17.The island's national dish cou-cou and flying fish, consist of this very fish. Cou-Cou is a combination of cornmeal and okra that are further combined with salt, pepper and Barbados' very own hot pepper sauce. This unique staple food is complimented with flying fish.
18.Barbados is mostly a tropical island
19.mostly males yet almost all females live 2-3 years longer than men
20. per capita is 14917.1 usd

subset: commoncrawl


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HANSGROHE 98519000 - HansHg Covers Raindance Unica'S
HANSGROHE 98519000 - HansHg Covers Raindance Unica'S
HVAC.com takes pride in offering only brand new genuine Hansgrohe parts & supplies.
If you have any questions regarding this product please feel free to email [email protected] or call 1-855-932-4822 and one of our friendly Customer Experience Representatives will be more than happy to help.


text:
Voices of Episcopal Split
Va. Traditionalist Represents Developing World
Friday, February 16, 2007
Shortly after becoming an Episcopal priest in the late 1970s, Martyn Minns visited Tanzania and was changed forever.
"I was just blown away by the faith, the commitment, the cost of being a Christian" on a continent where the religion's followers are an embattled minority in some places.
The image of an intense, miracle-working God worth fighting for has fueled the conservative Fairfax City priest for decades as he and those like him have felt increasingly sidelined in the Episcopal Church, with its progressive politics and sometimes staid worship style.
But the dry-witted native Brit isn't feeling isolated lately.
With bonds growing between conservative Protestants in the West and the booming, traditional Christian churches in the developing world, Minns has become an international power player. This week, the 63-year-old former Mobil Oil executive is in Tanzania at a meeting of top leaders of the Anglican Communion, which includes the Episcopal Church. He is there as an adviser to clergy from African, Asian and Latin American countries.
The notion of a 6-foot-4 white man from the affluent, suburban Truro Church in Fairfax representing the developing world may seem odd, but it is quite natural as U.S. conservatives seek support abroad.
Minns has quickly become one of the best-known, most colorful conservative Episcopal figures in the United States, leading 11 Virginia congregations -- including 1,300-member Truro -- in the past few months to leave the Episcopal Church to join the Church of Nigeria. In a twist on the paradigm, the congregations joined a Nigerian "mission" set up in the United States for conservatives; Minns is its bishop.
To his supporters, Minns's alliance with charismatic, deeply traditional African Christians is the way of Christianity's future, linking followers to the part of the world where Jesus is very vibrant -- not the coldly intellectualized God of the West. Minns ecstatically plays tambourine in church and is comfortable with faith healings and speaking in tongues.
But to his detractors, Minns is a divisive figure, exploiting a romanticized, oversimplified version of the developing world to pump energy into a conservative, anti-gay theology.
He is also a public face in the escalating property dispute between conservatives who left the U.S. church and Episcopal officials.
Regardless, some church observers view him as one who stands for those who look at Africa and see the early, passionate, embattled days of Christianity.
"Historically the church has prospered best when it's been a persecuted minority," said the Rev. Milind Sojwal of All Angels Church in New York City, where Minns worked from 1988-91.


text:
Free Samples, Coupons and Competitions for Women in the UK – Get your Free Stuff Here.
March 31, 2016 | Just For You
At this time of year, blustery winds, icy temperatures, and heavy rain makes it hard to pick an outfit for the day. If you've been longing to wear your leggings, here's how to get away with it without getting frozen in the process. Slip into a cozy sweater dress that complements your figure, keeps you toasty warm, and is easily matched with your favourite knee-high riding boots and blanket scarf!
Here's a few of my favourite sweater dresses from Pinterest. Maybe it will inspire you to get one for yourself!
Chic Cowl Neck with Belt
Pretty Schoolgirl Knit
Lightweight, Cool, and Comfy
Skater Dress
Dressy Sheath
Floor-Length Maxidress
Urban Chic with Scarf
Credit: Atlantic Pacific
Slim Slip-On
Best of Bohemian
Credit: Wachabuy
Casual Turtleneck
Credit: Refinery29
Go All Out
Bring Out Some Colour
Sweet and Girly
Looks so Comfy
Credit: Glamour


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Ноутбук для интерактивной записи
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Interactive Writing Notebook for First Grade - First Grade Centers and More. First lesson is topic sentence with two reason sentences; progresses to 3 reason sentences; then includes a closing sentence as the year progresses.
This writing interactive notebook will engage your language arts classroom with templates for common core that include grammar, writing, setting up, organization, lesson plans, and so much more. Teach 4th, 5th, 6th, 7th, and 8th grade Use these graphic organizers as anchor charts with students to promote learning. Complete with 24 lesson plans! Writing | Interactive Notebooks | Reading | Templates | Kids | Foldables
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FREE writing printables to use in interactive writing notebooks or in writing toolkits.
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First Grade Writing Notebook Projects. This notebook is jam-packed with writing lessons for the whole year. Includes ideas for beginning writers, grammar, opinion, narrative, informative, how-to, and much more!
Interactive Writing Notebooks WRITING CCSS for 3rd-6th Grade from Barnett's School House on TeachersNotebook.com - (104 pages) - I have compiled all of my interactive lessons and activities that I use to teach the Common Core Writing Standards to my fourth graders. This is an interactive Writing Notebook aligned to CCSS.
Detailed instructions and pictures on how to set up an interactive notebook in your classroom


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Cuatro Leches
There's nothing fit about this dessert, I know, but I decided to enter a competition by Bravo for a chance to win a kitchen makeover. Wish me luck!
To see the full recipe, click the "Read More" link under the picture.
makes 16 cakes
For the cake:
1 c unsalted butter, softened (2 sticks)
3 c all-purpose flour
2 c granulated sugar
4 eggs
1 tsp vanilla
½ c whole milk
1 ½ tsp baking powder
¼ tsp salt
For the cuatro leches:
1 - 14oz can sweetened condensed milk
1 - 12oz can evaporated milk
12 oz whole milk, plus extra for dulce de leche topping
1 - 14oz can dulce de leche
For the strawberries:
1 lb fresh strawberries, rinsed and dried
1/2 tbsp granulated sugar
2 tsp fresh orange zest
For the meringue:
4 egg whites
¾ c granulated sugar
To make the cake:
1. Preheat the oven to 350 degrees.
2. Sift the flour, baking powder and salt into a bowl. Set aside.
3. In a stand mixer or with a hand mixer, beat the butter and sugar on medium-high speed until fluffy. Add the vanilla, and the eggs, one by one, until well combined. Stop the mixer and scrape the sides of the bowl with a spatula to make sure all ingredients are well incorporated.
4. Add the dry ingredients into the wet ingredients in thirds, alternating with splashes of milk. Do not over mix. Stop the mixer to scrape the edges of the bowl, digging all the way down to the bottom. Mix another 10 seconds.
5. Evenly pour the batter into two greased 8-mini loaf pans, filling each one until there is a ¾-inch space at the top.
6. Bake for 30 minutes, or until a pick inserted into a cake comes out clean. The cake should be more on the overdone side, therefore a bit more dry than usual and a little browned around the edges, so that it stands up to the leches.
7. Remove the pans from the oven, and wait 5 minutes before transferring the cakes to a cooling rack.
8. When the cakes are cooled, carefully cut off the tops with a pairing knife. Do this on a slight angle so you create a small dent in the bottom half. Carefully remove some of the excess cake from the top.
9. Line each mold in the loaf pans with cling wrap and place the cakes back into the pan.
10.Pour the condensed milk, evaporated milk, and whole milk in a blender, and blend until well combined.
11.One by one, remove the tops of the cakes and gently poke holes with a fork in the cakes. This will help the milk seep into the cakes faster.
12.Transfer some of the milk mixture into a liquid measuring cup so it's easier to control. Pour 1-2 tbsp of milk in the first cake. When the milk is absorbed, pour another tablespoon and immediately place the top back on the cake so it absorbs some of the milk as well. Repeat with the rest of the cakes. You'll have milk left over – start with the first cake again, pouring another tablespoon or so over each one.
13.Cover the pans with cling wrap and refrigerate until you're ready to serve, at least 30 minutes to 1 hour.
1. Rinse and dry the strawberries, then cut them into ¼-inch slices.
2. Add the granulated sugar and orange zest. Mix well with a spoon and set aside.
To make the meringue:
1. Preheat the oven to 250 degrees.
2. Make sure the egg whites are at room temperature. Add them to the mixing bowl and start beating them on high until the whites become frothy.
4. Line a baking sheet with parchment paper. Transfer 1/3 cup of the meringue to the parchment paper and spread evenly into a thin layer, using the back of a small spoon, until it's about ¼-inch thick. Bake the meringue until crispy, but still light in color and chewy inside, about 20-25 minutes. Remove from the oven and let it cool.
5. Break the meringue into small pieces and set aside.
1. Remove the pans from the refrigerator. Gently remove one cake from the pan, helping yourself with the cling wrap, and place the cake on the serving dish.
2. Remove the top of the cake and set aside. Spread a thick layer of the unbaked meringue, about 2-3 tbsp on top of the cake. Top with an even layer of strawberries, using a slotted spoon to drain the berries. Then top with baked meringue crumbles. Gently place the top of the cake over the layers.
3. Add the dulce de leche to a microwavable bowl. Heat for 15-20 seconds, until smoother. If the dulce de leche isn't runny, mix in some milk, little by little, until it reaches a smooth consistency. Drizzle the top of the cake with the warm dulce de leche and serve immediately.
Note: to make this a tres leches cake, simply omit the dulce de leche topping.


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Tales of cash being exported from Afghanistan to calmer climes such as Gulf Emirates have been ongoing but the pace of the transfer is apparently speeding up. A common theory is that the rich are worried about losing power when their western defenders leave or that civil conflict will make their future uncertain.
Many analysts doubt that the Taliban actually have the power to take over government again. What is more likely is that they will be an influential group within the government. They along with others may insist on clearing out some of the corrupt politicians within the Karzai regime. No doubt many of the rich fear that might include them!
Afghan officials are supposedly trying to find a way to prevent this export of hard currency that includes U.S. dollars, Euros, and scrip from Gulf emirates. Much of the money going back out of the country may have come from the U.S. A U.S. government audit discovered that they were unable to track much of the billions spent on both security and development projects over the years.
A favorite place for rich Afghans to stash their wealth is in Dubai. An estimated 8 billion U.S. has come from Afghanistan.
The West has provided security and opportunities for profit for a long time now. As the West reduces its aid and military presence those who have profited from the west's favorite pastime of fighting terrorism by taking on radicals who were their former allies can relax in the luxury of the man made Palm Jumeirah Island in Dubai. For more see this article.
Tuesday, February 14, 2012
Afghan rich exporting their riches to calmer climes
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text:
This warm and cosy holiday farmhouse sits in an ideal secluded setting on a working farm, amid far reaching hill views. Enjoy wonderful walks from the doorstep. The Elan Valley with its stunning reservoirs and superb mountain biking, is the area's main attraction; fishing is also available here and on the River Wye or Llyngwyn Lake. A great location for birdwatchers and walkers with the Glyndwr's Way or the Cistercian Way. Visit the Offa's Dyke Centre at Knighton, Llandrindod Wells and Builth Wells close by. For children, the indoor play barn and adventure park are nearby, as well as cycle hire and pony trekking. Cardigan Bay and the beaches at Aberdovey make great day trips. Shop 5 miles, pub 4 miles.
Ground floor: Living/dining room/kitchen with wooden floor and beams. Utility room. 2 double bedrooms, one 6ft zip and link. Bathroom with shower over bath and toilet. Shower room with toilet. Narrow stairs to first floor: 1 double (5ft) with en-suite bathroom with shower attachment and toilet. Second narrow staircase to first floor: Games room with low beams.
Woodburner in living room (initial fuel inc). Solid fuel CH, elec heaters, elec, bed linen and towels inc. T/cot. H/chair. Freeview TV. DVD. CD. Solid fuel Rayburn. Elec cooker. M/wave. Washer/dryer. D/washer. F/freezer. Garden with patio, terrace and furniture. BBQ. Parking (2 cars). Cycle store. Hot tub. Games room with table tennis/air hockey and table football. Natural water supply from spring. No smoking. Friday to Friday.


text:
BKJ 12 String Guitar
invented by Bryce Jacobs
BKJ 12 String Guitar
The BKJ is a 12 string electric guitar with a greatly enhanced range (7 octaves) that can almost cover the same number of octaves as a piano (about 8 octaves), allowing for a much wider range of music to be played. It also opens up the scope of guitar composition, by offering the composer a wider range of notes to play with.
About the Inventor
BRYCE JACOBS is a 26 year old musician from Sydney with a broad range of talents. He is a singer, guitarist, drummer, keyboard player and is currently undertaking a masters degree in composition at the Sydney Conservatorium.
For more information about BKJ 12 String Guitar, contact the following:
Online Discussion
Read what others have said or have your say.
While studying guitar at the Conservatorium as part of his first degree in performance, he was constantly troubled by the fact that so much music was beyond the reach of guitar players, particularly piano music which has to be heavily re-arranged to be able to be played on a guitar.
He began working on a new guitar that would be capable of playing music written for piano, without the need to change a note.
The aims of the inventor when developing the BKJ 12 String Guitar were as follows:
1. Create a guitar with a somewhat equal range to an 88 key piano.
2. Have a standard tuning that other tunings could be derived from. The object of the tuning was to allow much easier arrangement of piano and orchestral music for guitar.
3. The sound quality, while hopefully unique, must be at least that of a standard guitar.
4. The spacing between strings should not exceed what is physically comfortable for a player with averaged sized hands.
5. The guitar should be as harmonically stable as a standard guitar.
6. It should be no heavier than a standard guitar, for comfort of the player.
7. The playing technique required should not be out of reach of the average guitar player.
This standard tuning gave the guitar a natural range of approximately 5 octaves. In order to increase the range to 7 octaves, electronic pitch shifting devices had to be added.
The way these pitch shifting devices work on the prototype is as follows:
- The guitar is fitted with 2 sets of Humbucker pickups, one set on the 6 higher strings and one on the 6 lower.
- These pickups take the signal, via a stereo lead, into 2 separate pedal operated pitch shifting devices, called Polyphonic Octave Generators, or POGs for short.
- The six higher strings can be shifted up one octave and the six lower can be shifted down an octave, thus allowing the guitar to achieve a range of 7 octaves.
- The shifted sound is then fed to the amp.
The 2 signals can also be modified using volume and tone knobs as on a standard guitar.
By contrast, a normal electric guitar setup would have one set of pickups with tone and volume control going via a mono lead, directly into the amp.
On the prototype the pitch shifting devices are separate to the guitar, but Bryce hopes eventually to be able to incorporate them into the body of the guitar.
The guitar neck has two truss rods as opposed to one in a standard guitar. These are necessary to balance the neck against the tension of the strings, and in order to keep the tuning stable. (If the neck bends at all then the tuning and intonation of the instrument will be out).
It is somewhat wider than a standard guitar neck in order to accommodate the 12 equally spaced strings. The inventor hopes that in subsequent designs, the neck can be made slightly narrower to facilitate ease of playing.
The body is made from alder wood to keep it relatively light, and is basically a standard guitar shape, though again slightly wider for the reasons mentioned above.
The cut-away shape of the body around the neck allows the left hand to reach right up the neck to play the highest notes on each string.
The guitar is fitted with a strap and is held and played in basically the same way as a standard guitar. The only difference is that the left hand must come further around the fret-board to access the lower 6 strings.
Interestingly, Bryce has found that rather than being a disadvantage, this has actually encouraged him to use more of a whole arm technique rather than just stretching his hand around the neck. Playing with his whole arm has actually alleviated some hand problems that had started to develop from playing ordinary guitars in his second year of uni.
Quote of the Week
"I can't understand why people are frightened of new ideas. I'm frightened of the old ones." - musical innovator John Cage


text:
"Athena's Song" is the first song in the 2008 prequel, The Little Mermaid: Ariel's Beginning. The song is sung by Queen Athena before she died. It is later played by the music box, which was later thrown by King Triton after Athena's death.
Oh, the waves roll low,
And the waves roll high,
And so it goes
Under a bright blue endless sky.
Waves try to measure
The days that we treasure
Wave hello, and wave goodbye...


text:
Keyword Research Trends In B2b
Keeping the Marketing Pipeline full is a difficult task in today's fast-paced B2B market. In order to accelerate pipeline growth you need to start paying attention to one of the top keyword research trends this year: Top of Funnel. Thinking Top of Funnel will allow you to stay ahead of your competition - and deliver your audience with a solution that responds to a broader range of search terms than ever before.
The Captora platform was built to fill this Top of Funnel knowledge gap. Watch this video to learn how easily you can:
- Identify the best content and conversion opportunities
- Build, launch, and optimize campaign portfolios at scale
- Report success, measure ROI and drive growth across the funnel
Digital Marketing Acceleration Video


text:
What is JotForm?
JotForm is a free online form builder which helps you create online forms without writing a single line of code. No sign-up required.
At JotForm, we want to make sure that you're getting the online form builder help that you need. Our friendly customer support team is available 24/7.
We believe that if one user has a question, there could be more users who may have the same question. This is why many of our support forum threads are public and available to be searched and viewed. If you'd like help immediately, feel free to search for a similar question, or submit your question or concern.
Set Email Field as the Notification Sender Email AddressAsked by morcio on September 04, 2015 at 04:52 PM
Hello Jotform team!
Since 2008 im been using your service and its amazing, but right now i have a big problem with a client. He wants the Sender E-MAIL field would be the Field {email} cuz in he Gmail account he got a lot of emails just in the same email (firstname.lastname@example.com) and he want different emails (example: email@example.com firstname.lastname@example.com, email@example.com) i dont know if this is possible, i dont care if i need to pay a different plan, i just want a solution of this problem the more soon possible.
Thanks a lot for your time and sorry for my bad english.
Best greetings,
Morcio D'Achiardi
This would be awesome!!
this would be my aha moment, my best user experience :)
JotForm Support
There is a workaround you can implement to set the Email field as the Notification Sender Email Address, please check this guide: https://www.jotform.com/help/240-Set-Email-Field-as-the-Notification-Sender-Email-Address-with-Mandrill
JotForm Support
If you want to set the Email field in your form as Sender E-mail, unfortunately, this is currently not possible. The only workaround for this is by using the instructions provided by my colleague (by using Mandrill). Setting a custom email as a Sender E-mail needs SMTP settings for it to work. So dynamic changing of Sender E-mail (based on the Email fied in the form) is not currently possible because we need the SMTP details and permission for the email to work.
Do let us know if you need further assistance.
JotForm Support
We will resolve your issue separately here https://www.jotform.com/answers/1019155


text:
• Sterling silver clasp bracelet
• White agate gemstones
• Bracelet has an adjustable toggle closure to fit most wrists
• Designed and crafted in America with gemstones from around the world
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text:
Is police brutality a problem in America and why or why not?
- YesVote A
- NoVote B
Most Helpful Guy
Yes, and because no one is holding cops accountable for their actions. When teachers fuck up, they get fired. When doctors fuck up, they get sued for malpractice. When cops fuck up, they get a free vacation paid for by our tax dollars and not only do they NOT get fired from their jobs, but they get a fucking RAISE.
Obviously not all cops are corrupt, racist pieces of shit. But that doesn't make this any less of a problem. That doesn't excuse the fact that not only did dozens of medical schools across the world deem it a "public health risk", but almost the entire UN shatted on the US for not handling this the right way.00|00|0


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Mollie The Collie Gamblin
Nov. 20, 1999
Jan. 22, 2011
Mollie was a gift on Christmas morning 1999 and was my best friend and constant companion for 11 years. As soon as she saw me pick up my purse she knew we were going for a ride somewhere and would bound out to wait my the vehicle door so she wouldn't be forgotten.
She loved the water and would swim out and fetch sticks as long as you would throw them and got really excited when we hooked up the boat to go fishing. She was a good cattle dog and in later life kept her paw in the game by barking at the cows from the front seat of the Kawasaki Mule.
Later in her life she had many medical problems, but no matter how sick she became she always bounced back. Even when she went blind from diabetes it didn't stop her from chasing the ball and going for walks.
Sadly this time when I took to the vet, she said "Not this time, she is too tired". So I let her go.
Good-bye my friend, you will always be the best doggie in the whole world.
Cremated, Ashes given to family or friend.
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Thelma Gamblin
Record added: Jan 22, 2011
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I'm trying to change my domain from blackout-gaming.net to blackout-ro.com
Everything seems to be working fine, except I can't use the login feature for XenForo.
This is the error I receive after attempting to login.
I've tried all sorts of things with no success. Please help.
Thank you in advance.


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Night School is a program for new collectors and contemporary art enthusiasts, an introductory contemporary art survey that is intentionally accessible, intelligent and engaging. Through a curriculum built from the history of exhibitions at the CAG, participants will learn about common themes in recent visual arts and ways in which they are interpreted and discussed. Lectures by instructor Lee Plested will introduce work by important artists from Vancouver and around the world. A suggested reading list will complement the discussion program. Along with the lectures, the participants will also engage in three studio visits with internationally recognized local artists including: Vikky Alexander, Gareth Moore, Elizabeth McIntosh, and tours of exhibitions by Lawrence Paul Yuxweluptun – Unceded Territories at the Museum of Anthropology and upcoming exhibition, MashUp: The Birth of Modern Culture at the Vancouver Art Gallery.
Wednesday March 16, 7:30-9:00 pm
Lecture 1 – The French Salon
Sunday March 20, 3:30-5:00 pm
Studio Visit 1 with Vikky Alexander
Wednesday March 23, 7:30-9:00 pm
Lecture 2 – Matter Is Meaning
March 23 – April 2
Easter Reading Week Break (no session)
Sunday April 3, 3:00-4:00 pm
Exhibition Visit – MashUp: The Birth of Modern Culture
Vancouver Art Gallery
Sunday April 10, 3:30-5:00 pm
Studio Visit 2 with Elizabeth McIntosh
Wednesday April 13, 7:30-9:00 pm
Lecture 3 – Absorbing Abstractions
Sunday April 24, 3:30-5:00 pm
Studio Visit 3 with Gareth Moore
Wednesday April 27, 7:30-9:00 pm
Lecture 4 – Surrealism and Other Truths
Friday May 6, 6:00-7:00 pm
Exhibition preview for Jochen Lempert
Sunday May 15, 12:30
Curator's Tour – Lawrence Paul Yuxweluptun
Museum of Anthropology
Cost: $375, includes a complimentary CAG membership.
Payments can also be made by monthly installments.
Space is limited – 20 seats – filling up fast!
To register contact Kristin Cheung, Development Officer at [email protected] or call 604 681 2700.


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Jan 2017 Special Offer - 15% Off Furniture Sales
My Rooms Furniture Gallery's furniture stores in Augusta GA, Savannah GA, Charleston SC, & Columbia SC are proud to announce our January 2017 special offer.
January Special Offer - Furniture Inventory Sale!
During January 2017, purchase item (furniture, electronics, home decor, etc.) from your local My Rooms Furniture Gallery and get 15% off the listed price! Visit one of our showroom locations and choose from our selection of rocking chairs, dining room tables, living room furniture, sofas, sectionals, bedroom furniture, and a lot more. Choose from traditional, farm house, contemporary, transitional, coastal, or formal.
- You must finalize your purchase between 1/1/17 an 1/31/17
- Purchase must be paid-in-full at the time of the order (discounts not available if purchase is financed)
- This special offer is not retroactive - you must reference this offer prior to your purchase.
- Offer may not be combined with any other discounts of coupons
- Offer applies to in-store sales only (for in-stock items)


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ecofeminism timeline
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Sarah Spenceron 31 January 2013
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Transcript of ecofeminism timeline
The term ecofeminism was introduced by Francoise d'Eaubonne in her book Le Feminisme ou la Mortl. 1974 1981 Women's Pentagon Actions: an anti-nuclear, anti-militant campain. 1980-81 Greenham Women's Peace Camp: first all women peace camp, a European anti-nuclear, antimilitarization campain. 1981 Lois Gibbs of Love Canal New York establishes Citizens' Clearinghouse for Hazardous Waste, a national network to protest local communities from toxic waste. U.N.'s Environmental Programme's (UNEP) Global Assembly on Women and the Environment held in Miami World Women's Congress for a Healthy Planet held in Miami 1991 Women Healing Earth: Third World Women on Ecology, Feminism, and Religion by Rosemary Radford Ruether is published giving wimmin of the global south a voice in the dicussion of an issue effecting them directly. 1996 1962 Silent Springs by marine biologist Rachel Carson calls for government reform in it's treament of nature specificly through toxic pestisides such as DDT. Early 1970s Wife of local contactor of commercial developement rallys other wimmin in tree hugging to protect from deforrestion and soil erosion in Adwani; the moment when the "Chickpo movement became 'ecological and feminist'". 1977 The Kenyan Green Belt movement plants its first trees on World Environmental Day; a grassroots movement to prevent desertification and soil erosion by planting at least one thousand trees around each villageFull transcript


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Good Karma Finds You
Rewards for good deeds are returned when you least expect it.
Twists of fate occur that you could never imagine.
This man was kind to others just for the sake of being kind. He helped a young boy whose mother was ill and provided a meal to a hungry man. Why? Just because… Not for a gift in return or to be owed a favor.
This video brings out a lot of emotion. The selfless actions of this man are a good lesson for all viewers. He gives from his heart – without any expectations that he will be repaid with money or gestures. The good karma finds him 30 years later when he is in need.
In the strange twist of fate his doctor is the young boy he helped so many years ago. Paying it forward, the doctor takes care of all the medical bills that were burdening the family. It is amazing to see how being kind to people helps encourage these same people to be kind to others.
This is a classic story of what goes around comes around and "do onto others as you would have done onto you". Who knows – it could save your life!
About: This video was originally seen on the TrueMoveH YouTube channel. It is a classic paying-it-forward story that inspires you to be the best person you can be, while also giving you goose bumps and a few tears.


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Listing Courtesy of Re/Max 10 in the Park
Listing information
- Beds: 3
- Total Rooms: 8
- Parking Type Description: Attached 3 cars
- Total Square Footage: 2,500 ($155.96 per sq. foot)
- County: Will
- Elementary School: Nelson Ridge/Nelson Prairie Elem
- Style: 1-Story
- Baths: 2 (Full: 2 3/4: 0 1/2: 0 Other: 0)
- Stories: 0
- New Construction: No
- Estimated Annual Taxes: $8,810
- High School: Lincoln-Way West High School
- Subdivision: Horizon Meadows
- Year Built: 2005
- Status: Active with Contingency
- Fireplaces: 1
- Foreclosure: No
- Association Fee: $250
- Middle School: Liberty Junior High School
Additional Rooms Den
Age 11-15 Years
Air Conditioning Central Air
Appliances Dishwasher, Dryer, Microwave, Oven-Double, Oven/Range, Refrigerator, Washer
Area New Lenox
Assessment Includes None
Attic Full, Unfinished
Basement Full
Basement Bathrooms (Y/N) No
Basement Description Unfinished
Bath Amenities Double Sink, Garden Tub, Separate Shower, Steam Shower, Whirlpool
Built Before 1978 (Y/N) No
Contingency Flag Short Sale
Dining Room Combined w/ FamRm
Disability Access and/or Equipped No
Driveway Concrete
Electricity 200+ Amp Service, Circuit Breakers
Exterior Building Type Brick
Exterior Property Features Deck, Porch
Fireplace Details Gas Starter, Wood Burning
Fireplace Location Family Room
Foundation Concrete
Garage Details 7 Foot or more high garage door, Garage Door Opener(s), Transmitter(s)
Garage On-Site Yes
Garage Ownership Owned
Garage Type Attached
General Information School Bus Service
Heat/Fuel Forced Air, Gas
Interior Property Features 1st Floor Laundry, Vaulted/Cathedral Ceilings
Is Parking Included in Price Yes
Kitchen Type Eating Area-Breakfast Bar, Island, Pantry-Walk-in
Lot Description Irregular
Lot Size Less Than .25 Acre
Master Association Fee No
Master Bedroom Bath Full
Other Bedrooms (Below Grade) - 0, Special Service Area - N, Tax Year - 2016, Total Full/Half Baths - 2, Township - New Lenox
Ownership Fee Simple w/ HO Assn.
Parking Garage
Possession Closing
Property Type Detached Single
Recent Rehab (Y/N) No
Roof Type Asphalt/Glass (Shingles)
Sale Terms Conventional, FHA, VA
Sewer Sewer-Public
Special Assessments N
Tax Exemptions Homeowner
Type Detached 1 Story
Virtual Tour Circlepix
Water Lake Michigan
Waterfront (Y/N) No
Bedroom 2 Main Level 12X14
Bedroom 3 Main Level 14X12
Den Main Level 14X10
Dining Room Main Level 14X14
Family Room Main Level 19X21
Kitchen Main Level 14X16
Laundry Room Main Level 13X09
Living Room Main Level 14X15
Master Bedroom Main Level 15X15
Listing Courtesy of Re/Max 10 in the Park


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Interpreting Database Unit Test Results
When you run a database unit test, test results are automatically produced, saved to disk, and summarized in the Test Results window. As soon as you start a test run, the Test Results window appears and displays the progress of the test run. This display includes tests that are running and tests that have completed.
To see detailed information about a test result, double-click it in the Test Results window to display the Test Results Details page. For more information about a test result, double-click it.
For more information about how to change the display of the Test Results window, see How to: Add or Remove Columns in Test Windows.
Results of database unit tests are automatically stored on your hard disk in files that have the extension .trx. A .trx file is an XML file that contains the details of a test run. You can load .trx files from previous test runs to review the results from those test runs or to re-run earlier tests. For more information, see How to: Rerun a Test.
You cannot run database unit tests remotely, that is, by using a rig.
If your team is using a Visual Studio Team Foundation Server team project to help manage its work, you can also publish your test data to a Microsoft SQL Server database known as an operational store.
For more information about how to save test results, re-use them, and share them with your team, see How to: Save and Open Test Results in Visual Studio.


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It was unfortunate for a couple of films which released on May 16, since people were stuck before their TV sets and only a marginal crowds visited theatres. So new releases like 'Amrutham Chandamam lo' and 'A K Rao P K Rao', had poor collections on day one, says a distributor. The former managed 20 lakhs, while the later had worse openings.
'Amrutham' was a popular TV sitcom, so collections could slowly improve in next few days, but poor promotion of Ak Rao… starring Dhanraj and Ramesh, is affecting its collections' says the distirbutor, who declares 'Pyar Me Padipoyane' into the flop list. 'We don't expect big openings for 'Dillunondu' today since Sairam shankar is reeling under super flops, if the story is good enough, may be it could pull some crowds' he adds.
Nevertheless, 1600-odd theatres in Andhra Pradesh are eagerly awaiting for the releases of two big films 'Manam' and 'Vikramasimha' to revive crowds at the ticket counters. With more than 50-crores invested on these two films by Telugu distributors, it should take good openings. 'We hope that Akkineni family will have better openings than Rajni', since its last film of legendary actor ANR and also for the first time in 80-year-old Telugu cinema three generation stars have acted in a film, that its USP' feels trade analyst.


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Hotel Marina, Shimla
Hotel Marina Mall Road Shimla 171001 (H.P) India
Hotel Marina Details
Set amidst magical landscapes and the serene atmosphere of Shimla is Hotel Marina which is one of the most sought-after luxury hotels in the hill-station. Offering to its guests a range of accommodation, hospitality and wellness facilities that are unparalleled to any other, Hotel Marina has earned itself a name as one of the best boutique hotels in the region.
Located at a convenient distance of 25 km from Shimla airport, 1.5 km away from the railway station and 2.5 km away from the bus stop, Hotel Marina offers some of the most splendid views of the natural beauty around which consists of majestic snow-covered mountains, lush greenery, pine groves and deodar forests.
While holidaying at Hotel Marina, which is established on a property which is more than a 100 years old, one can expect a treatment for for royals. This prestigious hotel has also been frequented by famous politicians, artists and bollywood actors for its charm.
Hotel Marina is a mix of traditional hospitality and modern style. At this hotel one can experience the best of luxury, services and hospitality. The guests' needs are met with utmost attention at the Marina Hotel and it uses rich, warm colors in its decor to create a relaxing ambience for the visitors.
With its inviting comforts, modern amenities, great service, tasteful decor and fantastic views, Hotel Marina definitely makes for a worthwhile and memorable stay for the guests.


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RESTAURANTS IN LONDONCovent Garden restaurantsKnightsbridge restaurantsMayfair restaurantsNotting Hill restaurants
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Organisers keen on hosting an event to remember will love the West End theatre experiences available from Encore Hospitality. Packages range from VIP access to sold-out shows to private entertaining rooms flush with champagne. The Hamlet hospitality package at the Barbican includes an exclusive champagne reception with canapés at the private bar adjacent to the auditorium and up to 24 prime-seats for the show, starring Benedict Cumberbatch. Packages at the Garrick theatre include exclusive seats – up to 12 premium dress circle seats – and access to the Royal Retiring Room for champagne and canapés. The package also includes interval drinks and desserts. Expect the likes of seabass gravadlax with lemon zest and parmesan shortbread with creamed goat's cheese on the menu.
Bookers can bag tickets for groups to catch Lily James and Richard Madden in Romeo & Juliet at The Garrick from 12 May until 13 August. Packages include a champagne and canapé reception, prime seats, interval refreshments and after-show drinks in the Royal Retiring Room.


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Hey there, time traveller!
This article was published 2/9/2013 (1449 days ago), so information in it may no longer be current.
Heads have rolled from the executive offices right down to the men in the locker room. And it's clear more changes are on the horizon.
Three different quarterbacks have started games and, still, there appears to be no clear-cut answer to the franchise's most glaring need.
The secondary is under attack from the head coach -- again -- and the squealing about the competence of the offensive line has reached an excruciating pitch.
They are on a seven-game losing skid that has dropped them to 1-8, their worst run since an 0-10 start in 1998.
'It's not about taking the positives out of a could-have-won game. That can go on for maybe two or three games but when it keeps happening... what positives can you take out of that?'-- Bombers running back Chad Simpson, seen here pulling in a pass Sunday
And through it all the Winnipeg Blue Bombers frustrated faithful are asking one pertinent question in the wake of Sunday's annual Labour Day Classic loss to the Saskatchewan Roughriders:
You mean this nightmare of a 2013 season is only HALF over?
The Bombers exited Regina late Sunday night grasping for positives in another defeat -- the ninth straight on Labour Day -- that looked and smelled like so many others over the last little while. They led the Riders by a score of 18-14 at halftime but -- predictably -- came unravelled in the game's critical moments.
And so despite some brief flashes -- a 9-for-9 start for Justin Goltz, an Henoc Muamba tackle of Kory Sheets for a safety and later an interception by the Bombers middle linebacker -- the script unfolded pretty much as everyone had predicted.
Backed into a corner on their own turf, the Riders came out swinging and outscored the Bombers 41-8 in the final 32 minutes -- including 10-0 in the third quarter. (For those of you tracking these things -- and there are many -- Winnipeg has now been outscored 43-2 in third quarters since their season opener).
Essentially, the Labour Day Classic became akin to watching a dog work over a chew toy for three hours -- at first the toy offers up some resistance but, ultimately, the thing is completely devoured.
Afterwards we suggested on Twitter that if Bombers could find silver linings in all this, then they deserve special consideration from the big man upstairs.
Some folks managed to sift through the wreckage and find something salvageable, like the Bombers holding Kory Sheets to only 91 yards rushing, the occasional moments of glory from Goltz and Muamba's pick -- the first thrown by Darian Durant this season.
But we also received a succinct email from a reader that also sums up the sentiment of so many fans who have watched this club go 7-20 over the past two years and 10-27 since Labour Day 2011.
"Why do you even attempt to put lipstick on this pig anymore?" the fan wrote. "At least hockey season starts soon."
And that's why the Bombers are entering some dangerous territory here. The number of diehards who made the Labour Day trek to Regina was down significantly and, if there isn't some sense that things are going to change, those totals could start affecting the turnstiles here in Winnipeg after the Banjo Bowl.
Quite clearly, all this losing has an impact on the bottom line.
Right now the Bombers are being run by a new CEO and acting GM pushing to make change, a head coach trying to hang on to his job and 50-plus players who are still trying to sell -- both to the public and themselves -- that they aren't far off from being competitive.
But that was an old sales pitch a year ago. More than anything fans simply want a sense this downward spiral will end soon. They want hope, someone to step up and say, "this is what we are going to build around for 2014." And right now the list of components for a solid foundation is thin.
"This game isn't about hanging with people. We've got to win," said running back Chad Simpson in a morose Bomber locker room Sunday. "There were a couple of moments in the game where we could have taken over and won. That's what pro ball comes down to, single plays. You practice all week for that single play that can change the game and then we didn't come up with what we needed to come up with.
"You always try to find positives. Yes, we did good. But we've done good against B.C. and fought against real good teams before. We did it last year, we did it this year. It's not about taking the positives out a could-have-won game. That can go on for maybe two or three games but when it keeps happening... what positives can you take out of that?"
Great question. And right now the Bombers are still lost for an answer.
firstname.lastname@example.com Twitter: WFPEdTait


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Sorry, the book that you are looking for is not available right now.
We did a search for other books with a similar title, and found some results for you that may be helpful.
One long stretch of cloth is what Mother always wears - elegant yet so graceful. The mystery of the sari can be magic for a child, winding and weaving, just like the connection between a child and its mother.
The style, the motifs, the interplay of children, colours, and textures, create the rich, mood-filled, and dreamy world of
REVIEW SNAPSHOT®by PowerReviews
Reviewed by 2 customers
Best Uses
Comments about My Mother's Sari:
This book looked like a nice idea! But there is no storyline. Just a bunch of nice pictures with random sentences. I wanted to like it but it just wasn't very well written.
Best Uses
Comments about My Mother's Sari:
perfect for the children in my care. cuter and typical of all children's behavior
In this simple story, minimal text explains what a sari looks like and describes some of the uses to which a child might put it. As children dance, hide, climb, wipe their noses and sleep in their mothers' long and brightly colored saris, it becomes clear that saris-and by extension, their children's mothers-play an important part in the children's lives. Originally published in India, the story does not explain that saris are worn as clothing, although the endpapers do include visual and written instructions on how to tie a sari in the traditional manner. Overall, the text feels a bit vague and random, and it is unclear whether a sari is a multi-purpose object or whether the children are simply playing with saris in different ways. The accompanying collages, which combine photographs of saris with drawings and paintings of Indian children, are generally appealing but sometimes awkward. Nonetheless, readers whose mothers wear saris will find something familiar here and identify with the youngsters pictured, while others may find their interest piqued. (Picture book. 3-5) (Kirkus Reviews)
Audience: Children
For Ages: 3 - 8 years old
Format: Hardcover
Language: English
Number Of Pages: 28
Published: 1st September 2006
Country of Publication: US
Dimensions (cm): 26.0 x 20.0 x 0.8
Weight (kg): 0.313


text:
found a new home!
Plenty of my friends are looking
for one too. Find a pet to adopt.
I am already neutered, housetrained, a special needs pet, in need of an experienced adopter, up to date with shots, good with kids, not good with dogs, and not good with cats.
ID No. 94 Available to RESCUE ONLY OR APPROVED NO DOG HOME
SHELTER NAME: O'Malley
Weight: 71 lbs
Condition on Intake: GOOD
Age: 2-3 years Gender: MALE ALTERED
Breed: Pitbull Terrier mix
Intake Date: 3-24-16 Microchip: NO
Collar: NO
Intake Type: STRAY
Date Available: 3-28-16
Road Found:
Illness/Injury: None
Good With Adults: YES BUT NEED TO BE FAMILIAR WITH THE BREED
Good With Kids: YES
Good With Other Dogs: YES, but slow introductions
Good With Cats: NO
Housebroken: UNKNOWN BUT APPEARS TO BE
Energy Level: HIGH
Can be touched/handled: YES BUT WATCH, OKAY WITH HEAD PETTING AND HAND ON BODY BUT NOT WHEN EATING. HE WILL SNAP AND GROWL AT YOU IF THERE IS FOOD IN A BOWL PRESENT
Barker: NO
Escape Artist: NO
Food Aggressive: YES - WILL SNAP AT YOU IF YOU TOUCH HIM OR HIS FOOD BOWL WHEN EATING
Food Type: BOTH
Heartworm Status: POSITIVE - ON SLOW KILL METHOD AT SHELTER
Allergies: UNKNOWN
Walks on Leash: YES BUT PULLS HEAVILY AND WANTS TO TAKE THE LEASH IN HIS MOUTH AND PULL. WORKING WITH HIM HE IS MUCH BETTER NOW.
Lewisburg Animal Shelter
300 Woodside
Lewisburg TN 37091
931-359-5948 Adoptions/rescue inquiries
931-359-7215 Strays/welfare checks/nuisance dog calls for ACOs
Follow us on facebook under Lewisburg Animal Shelter Volunteers to see more candid photos of the dogs in our photo Albums. The current adoption fee is $75 which includes the dogs spay or neuter and Rabies vaccination at a local vet, and covers the distemper/parvo vaccine and bordetella vaccine and dewormings it receives here at our shelter. No dog will leave the shelter to an adopter without being vetted first.
By TN state law stray dogs are held for 3 days so they can be found by their owners before being put up for adoption or rescue. A dog found as a stray wearing a collar is held for 5 days before it is put up for adoption or rescue. Our shelter is a first come first adopt/rescue facility.There are no holds placed on dogs for potential adopters/rescue, however if a party is interested in a particular dog before it becomes available they may send an inquiry to email@example.com and those inquiries will be kept track of in order of received once dog becomes available. Adopters/rescues will be notified what order they are in in regards to each dog. They are available at 8am on the day they are available. Non vetted dogs will have an appointment scheduled and will be available for pickup for adoption the day after their surgery. Approved rescues may pull a dog and have vetted at their own expense once available to the public.
O'Malley, a Lewisburg Pit Bull Terrier dog was adopted! Here's how you can benefit by looking at adoption as an option to buying a Pit Bull Terrier for sale in Lewisburg, or seeking a Pit Bull Terrier dog from a breeder in Lewisburg.