text:
|Publication number
|Publication type
|Application number
|Publication date
|Dec 27, 2011
|Filing date
|Oct 26, 2009
|Priority date
|May 30, 2003
|Fee status
|Also published as
|Publication number
|Steven J. Frank, Shigeki Imai, Terumasa Yoneda
|Original Assignee
|Steven J. Frank, Sharp Kabushiki Kaisha
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (34), Non-Patent Citations (14), Referenced by (6), Classifications (35), Legal Events (1)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of, and claims the benefit of priority of, U.S. patent application Ser. No. 10/449,732, filed May 30, 2003, and entitled "Virtual Processor Methods And Apparatus With Unified Event Notification And Consumer-Produced Memory Operations," now U.S. Pat. No. 7,653,912, the teachings of which are incorporated herein by reference.
The invention pertains to digital data processing and, more particularly, to virtual processor methods and apparatus with unified event notification and consumer-producer memory operations.
There have been three broad phases to computing and applications evolution. First, there was the mainframe and minicomputer phase. This was followed by the personal computer phase. We are now in the embedded processor or "computers in disguise" phase.
Increasingly, embedded processors are being used in digital televisions, digital video recorders, PDAs, mobile phones, and other appliances to support multi-media applications (including MPEG decoding and/or encoding), voice and/or graphical user interfaces, intelligent agents and other background tasks, and transparent internet, network, peer-to-peer (P2P) or other information access. Many of these applications require complex video, audio or other signal processing and must run in real-time, concurrently with one another.
Prior art embedded application systems typically combine: (1) one or more general purpose processors, e.g., of the ARM, MIPs or x86 variety, for handling user interface processing, high level application processing, and operating system, with (2) one or more digital signal processors (DSPs) (including media processors) dedicated to handling specific types of arithmetic computations, at specific interfaces or within specific applications, on real time/low latency bases. Instead or in addition to the DSPs, special-purpose hardware is often provided to handle dedicated needs that a DSP is unable to handle on a programmable basis, e.g., because the DSP cannot handle multiple activities at once or because the DSP cannot meet needs for a very specialized computational element.
A problem with the prior art systems is hardware design complexity, combined with software complexity in programming and interfacing heterogeneous types of computing elements. The result often manifests itself in embedded processing subsystems that are under-powered computationally, but that are excessive in size, cost and/or electrical power requirements. Another problem is that both hardware and software must be re-engineered for every application. Moreover, prior art systems do not load balance; capacity cannot be transferred from one hardware element to another.
An object of this invention is to provide improved apparatus and methods for digital data processing.
A more particular object is to provide improved apparatus and methods that support applications that have high computational requirements, real-time application requirements, multi-media requirements, voice and graphical user interfaces, intelligence, background task support, interactivity, and/or transparent Internet, networking and/or P2P access support. A related object is to provide such improved apparatus and methods as support multiple applications meeting having one or more of these requirements while executing concurrently with one another.
A further object of the invention is to provide improved apparatus and methods for processing (embedded or otherwise) that meet the computational, size, power and cost requirements of today's and future appliances, including by way of non-limiting example, digital televisions, digital video recorders, video and/or audio players, PDAs, personal knowledge navigators, and mobile phones, to name but a few.
Yet another object is to provide improved apparatus and methods that support a range of applications, including those that are inherently parallel.
A further object is to provide improved apparatus and methods that support multi-media and user interface driven applications.
Yet a still further object provide improved apparatus and methods for multi-tasking and multi-processing at one or more levels, including, for example, peer-to-peer multi-processing.
Still yet another object is to provide such apparatus and methods which are low-cost, low-power and/or support robust rapid-to-market implementations.
These and other objects are attained by the invention which provides, in one aspect, a virtual processor that includes one or more virtual processing units. These execute on one or more processors, and each executes one or more processes or threads (collectively, "threads"). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time.
By way of example, an embedded virtual processor according to the invention for use in a digital LCD television comprises a processor module executing multiple virtual processing units, each processing a thread that handles a respective aspect of digital LCD-TV operation (e.g., MPEG demultiplexing, video decoding, user interface, operating system, and so forth). An event delivery mechanism associates hardware interrupts, software events (e.g. software-initiated events in the nature of interrupts) and memory events with those respective threads. When an event occurs, the event delivery mechanism delivers it to the appropriate thread, regardless of which virtual processing unit it is executing on at the time.
Related aspects of the invention provide a virtual processor as described above in which selected threads respond to notifications from the event delivery mechanism by transitioning from a suspended state to an executing state. Continuing the above example, a user interface thread executing on a virtual processing unit in the digital LCD TV-embedded virtual processor may transition from waiting or idle to executing in response to a user keypad interrupt delivered by the event delivery mechanism.
Still further related aspects of invention provide a virtual processor as described above in which the event delivery mechanism notifies a system thread executing on one of the virtual processing units of an occurrence of an event associated with a thread that is not resident on a processing unit. The system thread can respond to such notification by transitioning a thread from a suspended state to an executing state.
Still other related aspects of invention provide a virtual processor as described above wherein at least selected active threads respond to respective such notifications concurrently with one another and/or without intervention of an operating system kernel.
Yet further aspects of invention provide a virtual processor as described above in which the event delivery mechanism includes a pending memory operation table that establishes associations between pending memory operations and respective threads that have suspended while awaiting completion of such operations. The event delivery mechanism signals a memory event to a thread for which all pending memory operations have completed. Related aspects of the invention provide such a virtual processor that includes an event-to-thread lookup table mapping at least hardware interrupts to threads.
In still other aspects, invention provide a virtual processor as described above wherein one or more threads execute an instruction for enqueuing a software event to the event queue. According to related aspects one or more threads that instruction specify which thread is to be notified of the event.
Other aspects of invention provide a virtual processor as described above wherein at least one of the threads responds to a hardware interrupt by suspending execution of a current instruction sequence and executing an error handler. In related aspect, that thread further responds to the hardware interrupt by at least temporarily disabling event notification during execution of the error handler. In a further related aspect, that thread responds to the hardware interrupt by suspending the current instruction sequence following execution of the error handler.
In still other aspects, the invention provides digital data processors with improved data-flow-based synchronization. Such a digital data processor includes a plurality of processes and/or threads (again, collectively, "threads"), as well as a memory accessible by those threads. At least selected memory locations have an associated state and are capable of storing a datum for access by one or more of the threads. The states include at least a full state and an empty state. A selected thread executes a first memory instruction that references a selected memory location. If the selected location is associated with the empty state, the selected thread suspends until the selected location becomes associated with the full state.
A related aspect of invention provides an improved such digital data processor wherein, if the selected location is associated with the full state, execution of the first instruction causes a datum stored in the selected location to be read to the selected thread and causes the selected location to become associated with the empty state. According to a further related aspect of invention, the plurality of executing threads are resident on one or more processing units and the suspended thread is made at least temporarily nonresident on those units.
The invention provides, is further aspects, a digital data processor as described above wherein the selected or another thread executes a second of memory instruction that references a selected memory location. If the selected location is associated with the empty state, execution of that second memory operation causes a selected data to be stored to the selected location and causes the selected location to become associated with the full state.
Still other aspects, the invention provide a virtual processor comprising a memory and one or more virtual processing units that execute threads which access that memory. A selected thread executes a first memory instruction directed to a location in the memory. If that location is associated with an empty state, execution of instruction causes the thread to suspend until that location becomes associate with a full state.
Related aspects invention provide a virtual processor as described above that additionally includes an event delivery mechanism as previously described.
Further aspects of the invention provide digital LCD televisions, digital video recorders (DVR) and servers, MP3 servers, mobile phones, and/or other devices incorporating one or more virtual processors as described above. Related aspects of the invention provide such devices which incorporate processors with improved dataflow synchronization as described above.
Yet further aspects of the invention provide methods paralleling the operation of the virtual processors, digital data processors and devices described above.
These and other aspects invention are evident in the drawings and the description follows.
A more complete understanding of the invention may be attained by reference to the drawings, in which:
The module 5, which may be used singly or in combination with one or more other such modules, is suited inter alia for devices or systems whose computational requirements are parallel in nature and that benefit from multiple concurrently executing applications and/or instruction level parallelism. This can include devices or systems with real-time requirements, those that execute multi-media applications, and/or those with high computational requirements, such as image, signal, graphics and/or network processing. The module is also suited for integration of multiple applications on a single platform, e.g., where there is concurrent application use. It provides for seamless application execution across the devices and/or systems in which it is embedded or otherwise incorporated, as well as across the networks (wired, wireless, or otherwise) or other medium via which those devices and/or systems are coupled. Moreover, the module is suited for peer-to-peer (P2P) applications, as well as those with user interactivity. The foregoing is not intended to be an extensive listing of the applications and environments to which the module 5 is suited, but merely one of examples.
Examples of devices and systems in which the module 5 can be embedded include inter alia digital LCD-TVs, e.g., type shown in
The module 5 includes thread processing units (TPUs) 10-20, level one (L1) instruction and data caches 22, 24, level two (L2) cache 26, pipeline control 28 and execution (or functional units) 30-38, namely, an integer processing unit, a floating-point processing unit, a compare unit, a memory unit, and a branch unit. The units 10-38 are coupled as shown in the drawing and more particularly detailed below.
By way of overview, TPUs 10-20 are virtual processing units, physically implemented within processor module 5, that are each bound to and process one (or more) process(es) and/or thread(s) (collectively, thread(s)) at any given instant. The TPUs have respective per-thread state represented in general purpose registers, predicate registers, control registers. The TPUs share hardware, such as launch and pipeline control, which launches up to five instructions from any combination of threads each cycle. As shown in the drawing, the TPUs additionally share execution units 30-38, which independently execute launched instructions without the need to know what thread they are from.
By way of further overview, illustrated L2 cache 26 is shared by all of the thread processing units 10-20 and stores instructions and data on storage both internal (local) and external to the chip on which the module 5 is embodied. Illustrated L1 instruction and data caches 22, 24, too, are shared by the TPUs 10-20 and are based on storage local to the aforementioned chip. (Of course, it will be appreciated that, in other embodiments, the level1 and level2 caches may be configured differently—e.g., entirely local to the module 5, entirely external, or otherwise).
The design of module 5 is scalable. Two or more modules 5 may be "ganged" in an SoC or other configuration, thereby, increasing the number of active threads and overall processing power. Because of the threading model used by the module 5 and described herein, the resultant increase in TPUs is software transparent. Though the illustrated module 5 has six TPUs 10-20, other embodiments may have a greater number of TPUs (as well, of course, as a lesser number). Additional functional units, moreover, may be provided, for example, boosting the number of instructions launched per cycle from five to 10-15, or higher. As evident in the discussion below of L1 and L2 cache construction, these too may be scaled.
Illustrated module 5 utilizes Linux as an application software environment. In conjunction with multi-threading, this enables real-time and non-real-time applications to run on one platform. It also permits leveraging of open source software and applications to increase product functionality. Moreover, it enables execution of applications from a variety of providers.
As noted above, TPUs 10-20 are virtual processing units, physically implemented within a single processor module 5, that are each bound to and process one (or more) thread(s) at any given instant. The threads can embody a wide range applications. Examples useful in digital LCD-TVs, for example, include MPEG2 signal demultiplexing, MPEG2 video decoding, MPEG audio decoding, digital-TV user interface operation, operating system execution (e.g., Linux). Of course, these and/or other applications may be useful in digital LCD TVs and the range of other devices and systems in which the module 5 may be embodied.
The threads executed by the TPUs are independent but can communicate through memory and events. During each cycle of processor module 5, instructions are launched from as many active-executing threads as necessary to utilize the execution or functional units 30-38. In the illustrated embodiment, a round robin protocol is imposed in this regard to assure "fairness" to the respective threads (though, in other embodiments, priority or other protocols can be used instead or in addition). Although one or more system threads may be executing on the TPUs (e.g., to launch application, facilitate thread activation, and so forth), no operating system intervention is required to execute active threads.
The underlying rationales for supporting multiple active threads (virtual processors) per processor are:
Functional Capability
Multiple active threads per processor enables a single multi-threaded processor to replace multiple application, media, signal processing and network processors. It also enables multiple threads corresponding to application, image, signal processing and networking to operate and interoperate concurrently with low latency and high performance. Context switching and interfacing overhead is minimized. Even within a single image processing application, like MP4 decode, threads can easily operate simultaneously in a pipelined manner to for example prepare data for frame n+1 while frame n is being composed.
Multiple active threads per processor increases the performance of the individual processor by better utilizing functional units and tolerating memory and other event latency. It is not unusual to gain a 2� performance increase for supporting up to four simultaneously executing threads. Power consumption and die size increases are negligible so that performance per unit power and price performance are improved. Multiple active threads per processor also lowers the performance degradation due to branches and cache misses by having another thread execute during these events. Additionally, it eliminates most context switch overhead and lowers latency for real-time activities. Moreover, it supports a general, high performance event model.
Multiple active threads per processor leads to simplification of pipeline and overall design. There is no need for a complex branch predication, since another thread can run. It leads to lower cost of single processor chips vs. multiple processor chips, and to lower cost when other complexities are eliminated. Further, it improves performance per unit power.
In contrast, referring to
Events and Threads
In the illustrated embodiment, events include hardware (or device) events, such as interrupts; software events, which are equivalent to device events but are initiated by software instructions and memory events, such as completion of cache misses or resolution of memory producer-consumer (full-empty) transitions. Hardware interrupts are translated into device events which are typically handled by an idle thread (e.g., a targeted thread or a thread in a targeted group). Software events can be used, for example, to allow one thread to directly wake another thread.
Each event binds to an active thread. If a specific thread binding doesn't exist, it binds to the default system thread which, in the illustrated embodiment, is always active. That thread then processes the event as appropriate including scheduling a new thread on a virtual processor. If the specific thread binding does exist, upon delivery of a hardware or software event (as discussed below in connection with the event delivery mechanism), the targeted thread is transitioned from idle to executing. If the targeted thread is already active and executing, the event is directed to default system thread for handling.
In the illustrated embodiment, threads can become non-executing (block) due to: Memory system stall (short term blockage), including cache miss and waiting on synchronization; Branch miss-prediction (very short term blockage); Explicitly waiting for an event (either software or hardware generated); and System thread explicitly blocking application thread.
In preferred embodiments of the invention, events operate across physical processors modules 5 and networks providing the basis for efficient dynamic distributed execution environment. Thus, for example, a module 5 executing in an digital LCD-TV or other device or system can execute threads and utilize memory dynamically migrated over a network (wireless, wired or otherwise) or other medium from a server or other (remote) device. The thread and memory-based events, for example, assure that a thread can execute transparently on any module 5 operating in accord with the principles hereof. This enables, for example, mobile devices to leverage the power of other networked devices. It also permits transparent execution of peer-to-peer and multi-threaded applications on remote networked devices. Benefits include increased performance, increased functionality and lower power consumption
Threads run at two privilege levels, System and Application. System threads can access all state of its thread and all other threads within the processor. An application thread can only access non-privileged state corresponding to itself. By default thread 0 runs at system privilege. Other threads can be configured for system privilege when they are created by a system privilege thread.
Referring to
Idle (or Non-Active)
Waiting (or Active Waiting)
Executing (or Active, Executing)
A thread enable bit (or flag or other indicator) associated with each TPU disables thread execution without disturbing any thread state for software loading and unloading of a thread onto a TPU.
The processor module 5 load balances across active threads based on the availability of instructions to execute. The module also attempts to keep the instruction queues for each thread uniformly full. Thus, the threads that stay active the most will execute the most instructions.
In the illustrated embodiment, there are five different event types that can be signaled to a specific thread:
Thread Delivery
Thread wait
The timeout value from a wait
instruction executed by
threadn has expired
Executing instruction has
signaled exception.
HW Event
Event (like interrupt)
threadn as determined by
generated by hardware device.
event to thread lookup
SW Event
Event (like sw interrupt)
instruction specifies thread.
signaled by sw event
If that thread is not Active,
Waiting or Idle delivered
to default system thread
All pending memory
operations for a threadn have
Illustrated Event Queue 40 stages events presented by hardware devices and software-based event instructions (e.g., software "interrupts") in the form of tuples comprising virtual thread number (VTN) and event number:
Privilege that the event will be signaled at:
0. System privilege
1. Application privilege
Specifies how the event is signaled if the thread is
not in idle state. If the thread is in idle state, this
field is ignored and the event is directly signalled
0. Wait for thread in idle state. All events after
this event in the queue wait also.
1. Trap thread immediately
Specifies the logical number for this event. The
value of this field is captured in detail field of the
system exception status or application exception
status register.
Specifies the logical thread number that this event is
signaled to.
Of course, it will be appreciated that the events presented by the hardware devices and software instructions may be presented in other forms and/or containing other information.
The event tuples are, in turn, passed in the order received to the event-to-thread lookup table (also referred to as the event table or thread lookup table) 42, which determines which TPU is currently handling each indicated thread. The events are then presented, in the form of "TPU events" comprised of event numbers, to the TPUs (and, thereby, their respective threads) via the event-to-thread delivery mechanism 44. If no thread is yet instantiated to handle a particular event, the corresponding event is passed to a default system thread active on one of the TPUs.
The event queue 40 can be implemented in hardware, software and/or a combination thereof. In the embedded, system-on-a-chip (SoC) implementation represented by module 5, the queue is implemented as a series of gates and dedicated buffers providing the requisite queuing function. In alternate embodiments, it is implemented in software (or hardware) linked lists, arrays, or so forth.
The table 42 establishes a mapping between an event number (e.g., hardware interrupt) presented by a hardware device or event instruction and the preferred thread to signal the event to. The possible cases are:
The table 42 may be a single storage area, dedicated or otherwise, that maintains an updated mapping of events to threads. The table may also constitute multiple storage areas, distributed or otherwise. Regardless, the table 42 may be implemented in hardware, software and/or a combination thereof. In the embedded, SoC implementation represented by module 5, the table is implemented by gates that perform "hardware" lookups on dedicated storage area(s) that maintains an updated mapping of events to threads. That table is software-accessible, as well—for example, by system-level privilege threads which update the mappings as threads are newly loaded into the TPUs 10-20 and/or deactivated and unloaded from them. In turn embodiments, the table 42 is implemented by a software-based lookup of the storage area that maintains the mapping.
The event-to-thread delivery mechanism 44, too, may be implemented in hardware, software and/or a combination thereof. In the embedded, SoC implementation represented by module 5, the mechanism 44 is implemented by gates (and latches) that route the signaled events to TPU queues which, themselves, are implemented as a series of gates and dedicated buffers 46-48 for queuing be delivered events. As above, in alternate embodiments, the mechanism 44 is implemented in software (or other hardware structures) providing the requisite functionality and, likewise, the queues 46-48 are implemented in software (or hardware) linked lists, arrays, or so forth.
An outline of a procedure for processing hardware and software events (i.e., software-initiated signalling events or "software interrupts") in the illustrated embodiment is as follows:
Memory-related events are handled only somewhat differently. The Pending (Memory) Event Table (PET) 50 holds entries for memory operations (from memory reference instructions) which transition a tread from executing to waiting. The table 50, which may be implemented like the event-to-thread lookup table 42, holds the address of the pending memory operation, state information and thread ID which initiated the reference. When a memory operation is completed corresponding to an entry in the PET and no other pending operations are in the PET for that thread, an PET event is signaled to the corresponding thread.
An outline of memory event processing according to the illustrated embodiment is as follows:
As further shown in the drawing, in the illustrated embodiment, thread wait timeouts and thread exceptions are signalled directly to the threads and are not passed through the event-to-thread delivery mechanism 44.
The goal of multi-threading and events is such that normal program execution of a thread is not disturbed. The events and interrupts which occur get handled by the appropriate thread that was waiting for the event. There are cases where this is not possible and normal processing must be interrupted. SEP supports trap mechanism for this purpose. A list of actions based on event types follows, with a full list of the traps enumerated in the System Exception Status Register.
Event Type
Thread State
Privilege Level
Application event
Application or
Recognize event by
transitioning to
execute state, application
System event
Application or
System trap to
recognize event,
transition to execute
Application event
Waiting or executing
Application or
Event stays queued
(wait for idle)
until idle
Application event
Waiting or executing
Application or
Application trap to
(trap if not idle)
recognize event
System event
Waiting or executing
System trap to
recognize event
System event (wait
Waiting or executing
Event stays queued
for idle)
until idle
System event (trap if
Waiting or executing
System trap to
not idle)
recognize event
Application trap
Application Trap
System trap
System Trap
System trap, system
privilege level
System Trap
System trap
Illustrated processor module 5 takes the following actions when a trap occurs:
The illustrated processor module 5 utilizes a virtual memory and memory system architecture having a 64-bit Virtual Address (VA) space, a 64-bit System Address (SA) (having different characteristics than a standard physical address), and a segment model of virtual address to system address translation with a sparsely filled VA or SA.
All memory accessed by the TPUs 10-20 is effectively managed as cache, even though off-chip memory may utilize DDR DRAM or other forms of dynamic memory. Referring back to
In addition to the foregoing the virtual memory and memory system architecture of the illustrated embodiment has the following additional features: Direct support for distributed shared: Memory (DSM), Files (DSF), Objects (DSO), Peer to Peer (DSP2P); Scalable cache and memory system architecture; Segments that can be shared between threads; Fast level1 cache, since lookup is in parallel with tag access, with no complete virtual-to-physical address translation or complexity of virtual cache.
Virtual Memory Overview
A virtual address in the illustrated system is the 64-bit address constructed by memory reference and branch instructions. The virtual address is translated on a per segment basis to a system address which is used to access all system memory and IO devices. Each segment can vary in size from 224 to 248 bytes. More specifically, referring to
Illustrated segment table 52 comprises 16-32 entries per thread (TPU). The table may be implemented in hardware, software and/or a combination thereof. In the embedded, SoC implementation represented by module 5, the table is implemented in hardware, with separated entries in memory being provided for each thread (e.g., a separate table per thread). A segment can be shared among two or more threads by setting up a separate entry for each thread that points to the same system address. Other hardware or software structures may be used instead, or in addition, for this purpose.
Cache Memory System Overview
As noted above, the Level1 cache is organized as separate level1 instruction cache 22 and level1 data cache 24 to maximize instruction and data bandwidth.
Referring to
The extended L2 cache 26 b is, as noted above, DDR DRAM-based, though other memory types can be employed. In the illustrated embodiment, it is up to 1 gbyte in size, 256-way associative, with 16 k byte pages and 128 byte subpages. For a configuration of 0.5 mbyte L2 cache 26 a and 1 gbyte L2 extended cache 26 b, only 12% of on-chip L2 cache is required to fully describe L2 extended. For larger on-chip L2 or smaller L2 extended sizes the percentage is lower. The aggregation of L2 caches (on-chip and extended) make up the distributed SEP memory system.
In the illustrated embodiment, both the L1 instruction cache 22 and the L1 data cache 24 are 8-way associative with 32 k bytes and 128 byte blocks. As shown in the drawing, both level1 caches are proper subsets of level2 cache. The level2 cache consists of an on-chip and off chip extended L2 Cache.
The Cache Tag Array Groups 72 a-72 p, Tag Compare elements 74 a-74 p, corresponding Data Array Groups 76 a-76 p may be implemented in hardware, software and/or a combination thereof. In the embedded, SoC implementation represented by module 5, these are implemented in as shown in
The logic element 190 is further coupled with DDR DRAM control interface 26 c which provides an interface to the off-chip portion 26 b of the L2 cache. It is likewise coupled to AMBA interface 26 d providing an interface to AMBA-compatible components, such as liquid crystal displays (LCDs), audio out interfaces, video in interfaces, video out interfaces, network interfaces (wireless, wired or otherwise), storage device interfaces, peripheral interfaces (e.g., USB, USB2), bus interfaces (PCI, ATA), to name but a few. The DDR DRAM interface 26 c and AMBA interface 26 d are likewise coupled to an interface 196 to the L1 instruction and data caches by way of L2 data cache bus 198, as shown.
The Data Array Groups 82 a-82 p and Tag Compare elements 84 a-84 p may be implemented in hardware, software and/or a combination thereof. In the embedded, SoC implementation represented by module 5, these are implemented in gates and dedicated memory providing the requisite lookup and tag comparison functions. Other hardware or software structures may be used instead, or in addition, for this purpose.
The following is a pseudo-code illustrates L2 and L2E cache operation in the illustrated embodiment:
Referring to
Depending on the embodiment, there can be from 48 (or fewer) to 128 (or greater) general-purpose registers, with the illustrated embodiment having 128; 24 (or fewer) to 64 (or greater) predicate registers, with the illustrated embodiment having 32; six (or fewer) to 256 (or greater) active threads, with the illustrated embodiment having 8; a pending memory event table of 16 (or fewer) to 512 (or greater) entries, with the illustrated embodiment having 16; a number of pending memory events per thread, preferably of at least two (though potentially less); an event queue of 256 (or greater, or fewer); and an event-to-thread lookup table of 16 (or fewer) to 256 (or greater) entries, with the illustrated embodiment having 32.
General Purpose Registers
In the illustrated embodiment, each thread has up to 128 general purpose registers depending on the implementation. General Purpose registers 3-0 (GP[3:0]) are visible at system privilege level and can be utilized for event stack pointer and working registers during early stages of event processing.
Predication Registers
The predicate registers are part of the general purpose SEP predication mechanism. The execution of each instruction is conditional based on the value of the reference predicate register.
The SEP provides up to 64 one-bit predicate registers as part of thread state. Each predicate register holds what is called a predicate, which is set to 1 (true) or reset to 0 (false) based on the result of executing a compare instruction. Predicate registers 3-1 (PR[3:1]) are visible at system privilege level and can be utilized for working predicates during early stages of event processing. Predicate register 0 is read only and always reads as 1, true. It is by instructions to make their execution unconditional.
Control Registers
Thread State Register
System trap enable. On reset cleared. Signalling
of system trap resets this bit and atrapen
until it is set again by software when it is once
again re-entrant.
0 - System traps disabled
1 - Events enabled
Application trap enable. On reset cleared.
Signalling of application trap resets this bit
until it is set again by software when it is once
again re-entrant. Application trap is cause by
an event that is marked as application level
when the privilege level is also application
0 - Events disabled (events are disabled
on event delivery to thread)
1 - Events enabled
Thread Enable. On reset set for thread 0,
cleared for all other threads
0 - Thread operation is disabled. System
thread can load or store thread state.
1 - Thread operation is enabled.
Privilege level. On reset cleared.
0 - System privilege
1 - Application privilege
Thread State. On reset set to "executing" for
thread0, set to "idle" for all other threads.
0 - Idle
1 - reserved
2 - Waiting
3 - Executing
GP Registers Modified. Cleared on reset.
bit 8 registers 0-15
bit 9 registers 16-31
bit 10 registers 32-47
bit 11 registers 48-63
bit 12 registers 63-79
bit 13 registers 80-95
bit 14 registers 96-111
bit 15 registers 112-127
Endian Mode-On reset cleared.
0 - little endian
1 - big endian
Alignment check-When clear, unaligned
memory references are allowed. When set, all
un-aligned memory references result in
unaligned data reference fault. On reset
Instruction address translation enable. On
reset cleared.
0 - disabled
1 - enabled
Data address translation enable. On reset
0 - disabled
1 - enabled
ID Register
Processor type and
read only
Processor ID[7:0]- Virtual
read only
processor number
Thread ID[15:0]
Instruction Pointer Register
Specifies the 64-bit virtual address of the next instruction to be executed.
Address of instruction
Indicates which instructions
within instruction doubleword
remain to be executed.
Bit1- first instruction
doubleword bit[40:00]
Bit2- second instruction
doubleword bit[81:41]
Bit3- third instruction
doubleword, bit[122:82]
Always read as zero
System Exception Status Register
Exception Type
read only
0. none
1. event
2. timer event
3. SystemCall
4. Single Step
5. Protection Fault
6. Protection Fault, system call
7. Memory reference Fault
8. SW event
9. HW fault
10. others
Fault details- Valid for the following
exception types:
Memory reference fault details
(type 5)
1. None
2. waiting for fill
3. waiting for empty
4. waiting for completion of cache
5. memory reference error
event (type 1) - Specifies the 12 bit
event number
Application Exception Status Register
Exception Type
read only
0. none
1. event
2. timer event
3. SystemCall
4. Single Step
5. Protection Fault
6. Protection Fault, system call
7. Memory reference Fault
8. SW event
9. HW fault
10. Others
Protection Fault details - Valid for the
following exception types:
event (type 1) - Specifies the 12 bit
event number
System Exception IP
Address of instruction corresponding to signaled exception to system privilege. Bit[0] is the privilege level at the time of the exception.
Address of instruction doubleword which signaled
Indicates which instructions within instruction
doubleword remain to be executed.
Bit1 - first instruction doubleword bit [40:00]
Bit2 - second instruction doubleword bit [81:41]
Bit3 - third instruction doubleword, bit [122:82]
Privilege level of thread at time of exception
Address of instruction corresponding to signaled exception. Bit[0] is the privilege level at the time of the exception.
Application Exception IP
Address of instruction corresponding to signaled exception to application privilege.
Address of instruction doubleword which signaled
Indicates which instructions within instruction
doubleword remain to be executed.
Bit1 - first instruction doubleword bit [40:00]
Bit2 - second instruction doubleword bit [81:41]
Bit3 - third instruction doubleword, bit [122:82]
Address of instruction corresponding to signaled exception. Bit[0] is the privilege level at the time of the exception.
Exception Mem Address
Address of memory reference that signaled exception. Valid only for memory faults. Holds the address of the pending memory operation when the Exception Status register indicates memory reference fault, waiting for fill or waiting for empty.
Instruction Seg Table Pointer (ISTP), Data Seg Table Pointer (DSTP)
Utilized by ISTE and ISTE registers to specify the step and field that is read or written.
Specifies the low (0) or high (1)
portion of Segment Table Entry
ste number
Specifies the STE number that is
read into STE Data Register.
Instruction Segment Table Entry (ISTE), Data Segment Table Entry (DSTE)
When read the STE specified by ISTE register is placed in the destination general register. When written, the STE specified by ISTE or DSTE is written from the general purpose source register. The format of segment table entry is specified in Chapter 6—section titled Translation Table organization and entry description.
Instruction or Data Level1 Cache Tag Pointer (ICTP, DCTP)
Specifies the Instruction Cache Tag entry that is read or written by the ICTE or DCTE.
Specifies the bank that is read from
Level1 Cache Tag Entry. The first
implementation has valid banks
Specifies the index address within a
bank that is read from Level1 Cache
Tag Entry
Instruction or Data Level1 Cache Tag Entry (ICTE, DCTE)
When read the Cache Tag specified by ICTP or DCTP register is placed in the destination general register. When written, the Cache Tag specified by ICTP or DCTP is written from the general purpose source register. The format of cache tag entry is specified in Chapter 6-section titled Translation Table organization and entry description.
Event Queue Control Register
The Event Queue Control Register (EQCR) enables normal and diagnostic access to the event queue. The sequence for using the register is a register write followed by a register read. The contents of the reg_op field specifies the operation for the write and the next read. The actual register modification or read is triggered by the write.
Specifies the register operation for that write and the
next read. Valid for register read.
0- read
1- write
2- push onto queue
3- pop from queue
For writes and push specifies the event number
written or pushed onto the queue. For read and pop
operations contains the event number read or popped
from the queue
Indicates whether the queue was empty prior to the
current operation.
Specifies the address for read and write queue operations.
Address field is don't care for push and pop
Event-Thread Lookup Table Control
The Event to Thread lookup table establishes a mapping between an event number presented by a hardware device or event instruction and the preferred thread to signal the event to. Each entry in the table specifies an event number with a bit mask and a corresponding thread that the event is mapped to.
Specifies the register operation for that write and the
next read. Valid for register read.
0- read
1- write
For writes specifies the event number written at the
specified table address. For read operations contains
the event number at the specified table address
Specifies whether the corresponding event bit is
0- significant
1- don't care
Specifies the table address for read and write operations.
Address field is don't care for push and pop
Timers and Performance Monitor
In the illustrated embodiment, all timer and performance monitor registers are accessible at application privilege.
Number of clock cycles
since processor reset
Instructions Executed
Saturating count of the number of
instruction executed. Cleared on read.
Value of all 1's indicates that the
count has overflowed.
Thread Execution Clock
Saturating count of the number of
cycles the thread is in active-
executing state. Cleared on read.
Value of all 1's indicates that the
count has overflowed.
Wait Timeout Counter
Count of the number of cycles
remaining until a timeout event is
signaled to thread. Decrements by
one, each clock cycle.
Virtual Processor and Thread ID
In the illustrated embodiment, each active thread corresponds to a virtual processor and is specified by a 8-bit active thread number (activethread[7:0]). The module 5 supports a 16-bit thread ID (threaded[15:0]) to enable rapid loading (activation) and unloading (de-activation) of threads. Other embodiments may support thread IDs of different sizes.
Thread-Instruction Fetch Abstraction
As noted above, the TPUs 10-20 of module 5 share L1 instruction cache 22, as well as pipeline control hardware that launches up to live instructions each cycle from any combination of the threads active in those TPUs.
As shown in that drawing, during each cycle, instructions are fetched from the L1 cache 22 and placed in instruction queues 10 a-20 a associated with each respective TPU 10-20. This is referred to as the fetch stage of the cycle. In the illustrated embodiment, three to six instructions are fetch for each single thread, with an overall goal of keeping thread queues 10 a-20 a at equal levels. In other embodiments, different numbers of instructions may be fetched and/or different goals set for relative filling of the queues. Also during the fetch stage, the module 5 (and, specifically, for example, the event handling mechanisms discussed above) recognize events and transition corresponding threads from waiting to executing.
During the dispatch stage—which executes in parallel with the fetch and execute/retire stages—instructions from each of one or more executing threads are dispatched to the functional units 30-38 based on a round-robin protocol that takes into account best utilization of those resources for that cycle. These instructions can be from any combination of threads. The compiler specifies, e.g., utilizing "stop" flags provided in the instruction set, boundaries between groups of instructions within a thread that can be launched in a single cycle. In other embodiments, other protocols may be employed, e.g., ones that prioritize certain threads, ones that ignore resource utilization, and so forth.
During the execute & retire phase—which executes in parallel with the fetch and dispatch stages—multiple instructions are executed from one or more threads simultaneously. As noted above, in the illustrated embodiment, up to five instructions are launched and executed each cycle, e.g., by the integer, floating, branch, compare and memory functional units 30-38. In other embodiments, greater or fewer instructions can be launched, for example, depending on the number and type of functional units and depending on the number of TPUs.
An instruction is retired after execution if it completes: its result is written and the instruction is cleared from the instruction queue.
On the other hand, if an instruction blocks, the corresponding thread is transitioned from executing to waiting. The blocked instruction and all instructions following it for the corresponding thread are subsequently restarted when the condition that caused the block is resolved.
Referring to that drawing, an instruction queue and a set of three pointers is maintained for each TPU 10-20. Here, only a single such queue 110 and set of pointers 112-116 is shown. The queue 110 holds instructions fetched, executing and retired (or invalid) for the associated TPU—and, more particularly, for the thread currently active in that TPU. As instructions are fetched, they are inserted at the queue's top, which is designated by the Insert (or Fetch) pointer 112. The next instruction for execution is identified by the Extract (or Issue) pointer 114. The Commit pointer 116 identifies the last instruction whose execution has been committed. When an instruction is blocked or otherwise aborted, the Commit pointer 116 is rolled back to quash instructions between Commit and Extract pointers in the execution pipeline. Conversely, when a branch is taken, the entire queue is flushed and the pointers reset.
Though the queue 110 is shown as circular, it will be appreciated that other configurations may be utilized as well. The queuing mechanism depicted in
Processor Module Implementation
Pipeline Control Unit
In the illustrated embodiment, pipeline control 130 contains the per-thread queues discussed above in connection with
The instruction dispatch 144 evaluates and determines, each cycle, the schedule of available instructions in each of the thread class queues. As noted above, in the illustrated embodiment the queues are handled on a round robin basis with account taken for queues that are retiring instructions more rapidly. The instruction dispatch 144 also controls the output side of the thread class queues 142. In this regard, it manages the Extract and Commit pointers discussed above in connection with
The longword decode unit 146 decodes incoming instruction longwords from the L1 instruction cache 22. In the illustrated embodiment, each such longword is decoded into the instructions. This can be parameterized for decoding one or two longwords, which decode into three and six instructions, respectively. The decode unit 146 is also responsible for decoding the instruction class of each instruction.
Unit queues 148 a-148 e queue actual instructions which are to be executed by the functional units 30-38. Each queue is organized on a per-thread basis and is kept consistent with the class queues. The unit queues are coupled to the thread class queue control 140 and to the instruction dispatch 144 for control purposes, as discussed above. Instructions from the queues 148 a-148 e are transferred to corresponding pipelines 150 a-150 b en route to the functional units themselves 30-38. The instructions are also passed to the register file pipeline 152.
Referring back to
Referring, now, back to
The control logic drives 160 unit 38 based on a command signal from the pipeline control 130. It also takes as input the instruction cache 22 state and the L2 cache 26 acknowledgment, as illustrated. The logic 160 outputs a thread switch to the pipeline control 130, as well as commands to the instruction cache 22 and the L2 cache, as illustrated. The thread state stores 162 a-162 e store thread state for each of the respective TPUs 10-20. For each of those TPUs, it maintains the general-purpose registers, predicate registers and control registers shown in
Address information obtained from the thread state stores is routed to the thread selector, as shown, which selects the thread address from which and address computation is to be performed based on a control signal (as shown) from the control 160. The address adder 166 increments the selected address or performs a branch address calculation, based on output of the thread selector 164 and addressing information supplied by the register file (labelled register source), as shown. In addition, the address adder 166 outputs a branch result. The newly computed address is routed to the segment translation memory 168, which operates as discussed above in connection with
Functional Units
Turning back to
The control logic drives 170 unit 36 based on a command signal from the pipeline control 130. It also takes as input the data cache 22 state and the L2 cache 26 acknowledgment, as illustrated. The logic 170 outputs a thread switch to the pipeline control 130 and branch unit 38, as well as commands to the data cache 24 and the L2 cache, as illustrated. The address adder 172 increments addressing information provided from the register file 136 or performs a requisite address calculation. The newly computed address is routed to the segment translation memory 174, which operates as discussed above in connection with
Returning, again, to
Each instance 200 a-200 e has five write ports, as illustrated by the arrows coming into the top of each instance, via which each of the functional units 30-38 can simultaneously write output data (thereby insuring that the instances retain consistent data). Each provides a varying number of read ports, as illustrated by the arrows emanating from the bottom of each instance, via which their respective functional units obtain data. Thus, the instances associated with the integer unit 30, the floating point unit 32 and the memory unit all have three read ports, the instance associated with the compare unit 34 has two read ports, and the instance associated with the branch unit 38 has one port, as illustrated.
The register file instances 200-200 e can be optimized by having all ports read for a single thread each cycle. In addition, storage bits can be folded under wires to port access.
Consumer-Producer Memory
In prior art multiprocessor systems, the synchronization overhead and programming difficulty to implement data-based processing flow between threads or processors (for multiple steps of image processing for example) is very high. The processor module 5 provides memory instructions that permit this to be done easily, enabling threads to wait on the availability of data and transparently wake up when another thread indicates the data is available. Such software transparent consumer-producer memory operations enable higher performance fine grained thread level parallelism with an efficient data oriented, consumer-producer programming style.
The illustrated embodiment provides a "Fill" memory instruction, which is used by a thread that is a data producer to load data into a selected memory location and to associate a state with that location, namely, the "full" state. If the location is already in that state when the instruction is executed, an exception is signalled.
The embodiment also provides an "Empty" instruction, which is used by a data consumer to obtain data from a selected location. If the location is associated with the full state, the data is read from it (e.g., to a designated register) and the instruction causes the location to be associated with an "empty" state. Conversely, if the location is not associated with the full state at the time the Empty instruction is executed, the instruction causes the thread that executed it to temporarily transition to the idle (or, in an alternative embodiment, an active, non-executing) state, re-transitioning it back to the active, executing state—and executing the Empty instruction to completion—once it is becomes so associated. Using the Empty instruction enables a thread to execute when its data is available with low overhead and software transparency.
In the illustrated embodiment, it is the pending (memory) event table (PET) 50 that stores status information regarding memory locations that are the subject of Fill and Empty operations. This includes the addresses of those locations, their respective full or empty states, and the identities of the "consumers" of data for those locations, i.e., the threads that have executed Empty instructions and are waiting for the locations to fill. It can also include the identities of the producers of the data, which can be useful, for example, in signalling and tracking causes of exceptions (e.g., as where to successive Fill instructions are executed for the same address, with no intervening Empty instructions).
The data for the respective locations is not stored in the PET 50 but, rather, remains in the caches and/or memory system itself, just like data that is not the subject of Fill and/or Empty instructions. In other embodiments, the status information is stored in the memory system, e.g., alongside the locations to which it pertains and/or in separate tables, linked lists, and so forth.
Thus, for example, when an Empty instruction is executed on a given memory location, the PET is checked to determine whether it has an entry indicating that same location is currently in the full state. If so, that entry is changed to empty and a read is effected, moving data from the memory location to the register designated by the Empty instruction.
If, on the other hand, when the Empty instruction is executed, there no entry in the PET for the given memory location (or if any such entry indicates that the location is currently empty) then an entry is created (or updated) in the PET to indicate that the given location is empty and to indicate that the thread which executed the Empty instruction is a consumer for any data subsequently stored to that location by a Fill instruction.
When a Fill instruction is subsequently executed (presumably, by another thread), the PET is checked is checked to determine whether it has an entry indicating that same location is currently in the empty state. Upon finding such an entry, its state is changed to full, and the event delivery mechanism 44 (
In the illustrated embodiment, this use of the PET for consumer/producer-like memory operations is only effected with respect to selected memory instructions, e.g., Fill and Empty, but not with the more conventional Load and Store memory instructions. Thus, for example, even if a Load instruction is executed with respect to a memory location that is currently the subject of an Empty instruction, no notification is made to the thread that executed that Empty instruction so that the instruction can be reexecuted. Other embodiments may vary in this regard.
To accommodate data streaming from the source 236 in real-time, each of the threads 230-234 continually process data provided by its upstream source and does so in parallel with the other threads.
Referring to the drawing, arrows 240 a-240 g indicate fill dependencies between the threads and, particularly, between data locations written to (filled) by one thread and read from (emptied) by another thread. Thus, thread 230 processes data destined for address A0, while thread 232 executes an Empty instruction targeted to that location and thread 234 executes an Empty instruction targeted to address B0 (which thread 232 will ultimately Fill). As a result of the Empty instructions, thread 232 enters a wait state (e.g., active, non-executing or idle) while awaiting completion of the Fill of location A0 and thread 234 enters a wait state while awaiting completion of the Fill of location B0.
On completion of thread 230's Fill of A0, thread 232's Empty completes, allowing that thread to process the data from A0, with the result destined for B0 via a Fill instruction. Thread 234 remains in a wait state, still awaiting completion of that Fill. In the meanwhile, thread 230 begins processing data destined for address A1 and thread 232 executes the Empty instruction, placing it in a wait state while awaiting completion of the Fill of A1.
When thread 232 executes the Fill demand for B0, thread 234's Empty completes allowing that thread to process the data from B0, with the result destined for C0, whence it is read by the LCD interface (not shown) for display to the TV viewer. The three threads 230, 232, 234 continue process and executing Fill and Empty instruction in this manner—as illustrated in the drawing—until processing of the entire MPEG2 stream is completed.
A further appreciation of the Fill and Empty instructions may be attained by review of their instruction formats.
Format: ps EMPTY.cache.threads dreg, breg, ireg {,stop}
Description: Empty instructs the memory system to check the state of the effective address. If the state is full, empty instruction changes the state to empty and loads the value into dreg. If the state is already empty, the instruction waits until the instruction is full, with the waiting behavior specified by the thread field.
Operands and Fields:
ps The predicate source register that specifies whether the instruction is executed. If true the instruction is executed, else if false the instruction is not executed (no side effects). stop 0 Specifies that an instruction group is not delineated by this instruction. 1 Specifies that an instruction group is delineated by this instruction. thread 0 unconditional, no thread switch 1 unconditional thread switch 2 conditional thread switch on stall (block execution of thread) 3 reserved scache 0 tbd with reuse cache hint 1 read/write with reuse cache hint 2 tbd with no-reuse cache hint 3 read/write with no-reuse cache hint im 0 Specifies index register (ireg) for address calculation 1 Specifies disp for address calculation ireg Specifies the index register of the instruction. breg Specifies the base register of the instruction. disp Specifies the two-s complement displacement constant (8-bits) for memory reference instructions dreg Specifies the destination register of the instruction.
Format: ps FILL.cache.threads s1reg, breg, ireg {,stop}
Description: Register s1reg is written to the word in memory at the effective address. The effective address is calculated by adding breg (base register) and either ireg (index register) or disp (displacement) based on the im (immediate memory) field. The state of the effective address is changed to full. If the state is already full an exception is signaled.
Operands and Fields:
ps The predicate source register that specifies whether the instruction is executed. If true the instruction is executed, else if false the instruction is not executed (no side effects). stop 0 Specifies that an instruction group is not delineated by this instruction. 1 Specifies that an instruction group is delineated by this instruction. thread 0 unconditional, no thread switch 1 unconditional thread switch 2 conditional thread switch on stall (block execution of thread) 3 reserved scache 0 tbd with reuse cache hint 1 read/write with reuse cache hint 2 tbd with no-reuse cache hint 3 read/write with no-reuse cache hint im 0 Specifies index register (ireg) for address calculation 1 Specifies disp for address calculation ireg Specifies the index register of the instruction. breg Specifies the base register of the instruction. disp Specifies the two-s complement displacement constant (8-bits) for memory reference instructions s1reg Specifies the register that contains the first operand of the instruction.
Software Events
A more complete understanding of the processing of hardware and software events may be attained by review of their instruction formats:
Format: ps EVENT s1reg{,stop}
Description: The EVENT instruction polls the event queue for the executing thread. If an event is present the instruction completes with the event status loaded into the exception status register. If no event is present in the event queue, the thread transitions to idle state.
Operands and Fields:
ps The predicate source register that specifies whether the instruction is executed. If true the instruction is executed, else if false the instruction is not executed (no side effects). stop 0 Specifies that an instruction group is not delineated by this instruction. 1 Specifies that an instruction group is delineated by this instruction. s1reg Specifies the register that contains the first source operand of the instruction.
SW Event
Format: ps SWEVENT s1reg{,stop}
Description: The SWEvent instruction en-queues an event. onto the Event Queue to be handled by a thread. See xxx for the event format.
Operands and Fields:
ps The predicate source register that specifies whether the instruction is executed. If true the instruction is executed, else if false the instruction is not executed (no side effects). stop 0 Specifies that an instruction group is not delineated by this instruction. 1 Specifies that an instruction group is delineated by this instruction. s1reg Specifies the register that contains the first source operand of the instruction.
Ctl Fld
Format: ps.CtlFld.ti cfield, {,stop}
Description: The Control Field instruction modifies the control field specified by cfield. Other fields within the control register are unchanged.
Operands and Fields:
The predicate source register that specifies whether the instruction is executed.
If true the instruction is executed, else if false the instruction is not executed (no
side effects).
0 Specifies that an instruction group is not delineated by this instruction.
1 Specifies that an instruction group is delineated by this instruction.
0 Specifies access to this threads control registers.
1 Specifies access to control register of thread specified by ID.t_indirect
field. (thread indirection) (privileged)
cfield[4:0] control field privilege
000nn Thread state application nn value 00 idle 01 reserved 10 waiting 11 executing 0010S System trap enable system 0011S Application trap enable application 0100S Thread Enable system 0101S Privilege Level System 0110S Registers Modified application 0111S Instruction address translation enable system 1000S Data address translation enable system 1001S Alignment Check System 1010S Endian Mode system 1011S reserved 11**S S = 0 clear, S = 1 set
Devices Incorporating Processor Module 5
The illustrated subsystem further includes a plurality of modules 5, e.g., from one to twenty such modules (or more) that are coupled via an interconnect that interfaces with and, preferably, forms part of the off-chip L2 cache 26 b utilized by the modules 5. That interconnect may be in the form of a ring interconnect (RI) comprising a shift register bus shared by the modules 5 and, more particularly, by the L2 caches 26. Alternatively, it may be an interconnect of another form, proprietary or otherwise, that facilitates the rapid movement of data within the combined memory system of the modules 5. Regardless, the 1.2 caches are preferably coupled so that the L2 cache for any one module 5 is not only the memory system for that individual processor but also contributes to a distributed all cache memory system for all of the processor modules 5. Of course, as noted above, the modules 5 do not have to physically sharing the same memory system, chips or buses and could, instead, be connected over a network or otherwise.
Described above is are apparatus, systems and methods meeting the desired objects. It will be appreciated that the embodiments described herein are examples of the invention and that other embodiments, incorporating changes therein, fall within the scope of the invention, of which we claim:
|Cited Patent
|Filing date
|Publication date
|Mar 28, 1983
|Aug 25, 1987
|Xerox Corporation
|Method for providing priority interrupts in an electrophotographic machine
|Mar 31, 1994
|Nov 25, 1997
|Nec Research Institute, Inc.
|Software architecture for control of highly parallel computer systems
|Jul 12, 1996
|Feb 24, 1998
|Intel Corporation
|Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
|Oct 27, 1998
|Apr 17, 2001
|International Business Machines Corporation
|Circuit arrangement and method of dispatching instructions to multiple execution units
|Jul 21, 1995
|May 29, 2001
|Compaq Computer Corporation
|Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read
|Dec 31, 1997
|Aug 7, 2001
|Intel Corporation
|Method for detecting thread switch events
|Oct 1, 1999
|Jun 18, 2002
|Hitachi, Ltd.
|Mechanism for fast access to control space in a pipeline processor
|Jun 13, 2000
|Jul 30, 2002
|Hewlett-Packard Company
|Thread local cache memory allocator in a multitasking operating system
|Mar 14, 2000
|Oct 22, 2002
|Compaq Computer Corporation
|Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information
|Oct 1, 1999
|Dec 10, 2002
|Compaq Information Technologies Group, L.P.
|Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
|Jun 8, 1999
|Dec 2, 2003
|Microsoft Corporation
|Method and system for multi-threaded processing
|Jun 27, 2000
|Sep 28, 2004
|International Business Machines Corporation
|Interrupt mechanism for shared memory message passing
|Mar 30, 2001
|Dec 7, 2004
|Microsoft Corporation
|High performance interprocess communication
|Sep 28, 2000
|Jun 28, 2005
|International Business Machines Corportion
|Apparatus and method for creating instruction bundles in an explicitly parallel architecture
|Jun 28, 2001
|Jan 17, 2006
|International Business Machines Corporation
|Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry
|Apr 6, 2001
|May 23, 2006
|Sun Microsystems, Inc.
|Method and apparatus for polling multiple sockets with a single thread and handling events received at the sockets with a pool of threads
|Oct 1, 2002
|Jul 25, 2006
|Ubicom, Inc.
|System and method for instruction level multithreading scheduling in a embedded processor
|Dec 31, 2001
|Apr 22, 2008
|Intel Corporation
|Method and apparatus for suspending execution of a thread until a specified memory access occurs
|May 30, 2003
|Jan 26, 2010
|Steven Frank
|Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations
|Dec 12, 2003
|Mar 23, 2010
|Steven Frank
|General purpose embedded processor
|Apr 18, 2001
|Aug 23, 2001
|Hitachi, Ltd.
|Multi OS configuration method and computer system
|Jun 29, 2001
|Jun 26, 2003
|Jason Gosior
|System on chip architecture
|Jun 2, 2003
|Mar 11, 2004
|Vincent Nollet
|System and method for hardware-software multitasking on a reconfigurable computing platform
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Mar 2, 2000
|Nov 23, 2000
|International Business Machines Corporation
|Event-driven communications interface for logically-partitioned computer
|Oct 12, 2000
|Jun 14, 2001
|Intel Corporation
|Method and apparatus for entering and exiting multiple threads within a multithreaded processor
|"Microsoft Computer Dictionary," Fifth Edition, Microsoft Press, 2002; page including "branch instruction" definition; retrieved on Aug. 27, 2008.
|Hirata, H. et al. "An Elementary Processor Architecture With Simultaneous Instruction Issuing From Multiple Threads," ISCA '92: Proceedings of the 19th Annual International Symposium on Computer Architecture, USA, ACM Apr. 1992, vol. 20, Issue 2, pp. 136-1450.
|Hirata, H. et al., "A Resourch-Shared Processor Architecture With a Multiple Control-Flow Mechanism," Information Processing Society of Japan, Jun. 12, 1992, p. 2-11.
|Japanese Office Action issued Apr. 22, 2009 in JP 2004-158420, 5 pages.
|Japanese Office Action issued Apr. 4, 2011 in JP 2004-158420, 4 pages.
|Japanese Office Action issued Jul. 29, 2010 in JP 2004-158420, 9 pages.
|Japanese Office Action, dated Mar. 19, 2010, Application No. 2004-359188, 5 pages.
|Japanese Office Action, issued Apr. 22, 2009, in corresponding application of the instant case, 4 pages.
|Notice of Allowance issued Oct. 27, 2011 for Japanese Application No. 2004-158420.
|Silberschatz, Avi, Peter Galvin and Greg Gagne; "Applied Operating System Concepts." First Edition, John Wiley & Sons, Inc., 2000; pp. 19-41.
|Sugawara et al., "Table-based QoS Control for Embedded Real-Time Systems," ACM, May 1999, pp. 65-72.
|Susan J. Eggers, et al. "Simultaneous Multithreading: A Platform for Next-Generation Processors," IEEE Micro (Sep./Oct. 1997) pp. 12-19.
|Tanenbaum, Andrew S., "Structured Computer Organization," Second Edition, Prentice-Hall, Inc., 1984; pp. 1-17.
|Yang et al., "Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems," ISSS'02, Oct. 2-4, 2002 pp. 112-119.
|Citing Patent
|Filing date
|Publication date
|Nov 14, 2011
|Dec 31, 2013
|Steven J. Frank
|Virtual processor methods and apparatus with unified event notification and consumer-producer memory operations
|Aug 23, 2012
|Oct 28, 2014
|Dell Products L.P.
|Network traffic control by association of network packets and processes
|Jun 29, 2012
|Apr 25, 2017
|Zte Corporation
|Intelligence cache and intelligence terminal
|Feb 4, 2010
|Sep 9, 2010
|Steven Frank
|General purpose embedded processor
|Aug 23, 2012
|Apr 25, 2013
|Matthew L. Domsch
|Method Of Handling Network Traffic Through Optimization Of Receive Side Scaling
|Sep 30, 2014
|Jan 15, 2015
|Dell Products, Lp
|Network Traffic Control by Association of Network Packets and Processes
|U.S. Classification
|719/318, 718/102, 711/147, 710/260, 711/148, 718/104
|International Classification
|Cooperative Classification
|European Classification


text:
As shown. This is a great piece of Vietnam era militaria. US Navy or US Air Force.
3 7/8" by 2 3/4" Paperweight commemorating the building of the 1000th T-38 Jet on January 7, 1969.
The paperweight is in excellent / perfect condition with writing on the bottom related to the pilot / owner of the paperweight W.E. Jones - call sign "ROAD AGENT" with dates relating to accomplishments between 1965 and 1970.
2 other shoppers have this item in their Cart or Wish List .
See something you like - make us an offer! We are clearing inventory and considering all offers!
We will consider offers on nearly all of our items - please contact us!

subset: commoncrawl


text:
I've done some early testing with it, and it discovers the majority of the servers, computers, appliances, etc.. just fine. I've got Help Desk email coming in, but for some reason I'm not seeing any notifications going out. I only have one account at the moment configured to log in (and its the admin for the installation).
So, what I want it to do, and I'm obviously overlooking something easy is, if a user emails a help desk ticket, I want it to CC me so that I get a message in my Outlook instead of having to constantly stay logged into Spiceworks and watch the interface for anything new. I think I have it configured correctly, but something else of note is that when I assign one of these test tickets or do some other event that should create a notification, I don't see anything. So, can someone point me into the right direction?
This topic was created during version 4.7.
The latest version is 7.5.00101.
11 Replies
Oct 7, 2010 at 3:49 UTC
You need to create a user for yourself in the Settings --> User section, with your email address etc. Make yourself an admin & then you should start to get notifications.
Oct 7, 2010 at 3:53 UTC
Yeah, my account is in there with my email addy. I'm actually the only user at the moment. Admin rights, and I've clicked the "notify me" box. It looks right, but I'm not getting notifications to Outlook when new test tickets arrive.
Oct 7, 2010 at 3:56 UTC
Did you test the settings to make sure that your SMTP server is set up correctly? (it should send you a test message).
If so, go to the Settings --> Help Desk Settings & make sure that all of the notifications are as expected.
Oct 7, 2010 at 3:56 UTC
You need to have a dedicated user/mailbox for the email functionality for Spiceworks. This account will NOT be a user (admin or regular) in your application. You just enter this account information in 'Settings ->Email Settings'.
Admins then need their own accounts in the User settings with their email to use for notification. Be sure 'Notify Me' is checked to get emails.
Then configure your Helpdesk notification settings for who get's what and when in the Help Desk settings section.
Oct 7, 2010 at 4:15 UTC
I have an exchange mailbox (firstname.lastname@example.com) dedicated to this. So I can send an email to email@example.com from anywhere, and it will show up in the unassigned tickets within Spiceworks, as advertised. And it appears that I have full functionality with assigning the ticket to myself, changing importance, adding notes, etc.. One thing of note, I used this account for both incoming and outgoing mail settings during the initial setup. I wanted end users to send to this address for tickets, but also wanted it to be who they got the messages from as well. I assumed this was legal. During the initial setup, it passed auth to the exchange box both directions and seemed to be happy.
My personal account (email@example.com ) is the admin account for the installation. Its the only account in spiceworks at the moment. It does have the "notify me" checked.
Oct 7, 2010 at 4:30 UTC
Then it sounds like something to do with the outbound settings. Honestly - I would use IMAP & SMTP for your setup, it is faster than Exchange & less "error prone". I do not support IMAP or SMTP in my company, but I opened it just for the Spiceworks IP.
Oct 7, 2010 at 4:38 UTC
The way you describe it Nathan it sounds correct. Using the same account for both in and out is just fine.
Just verify your notification settings are correct in 'Settings->Help Desk Settings' are correct for notifications.
Oct 7, 2010 at 4:45 UTC
I changed my outbound from an exchange connection to smtp and my confirmation email came immediately. When it was set as an exchange connection, it would take quite a while (I suppose that is if it woulc come through at all). I only got maybe one of those to show up when saving my email settings. I'll tinker with it some more and report back. Thank you for the advice, good call on that.
Oct 7, 2010 at 4:46 UTC
I changed my outbound from an exchange connection to smtp and my confirmation email came immediately. When it was set as an exchange connection, it would take quite a while (I suppose that is if it woulc come through at all). I only got maybe one of those to show up when saving my email settings. I'll tinker with it some more and report back. Thank you for the advice, good call on that.
Yeah, I was really hesitant, but after doing it, I was shocked how much faster Spiceworks as a whole went.
Did you get any ticket notifications yet? Also - make sure that there isn't a rule or anything in your support exchange account that is catching emails.
Oct 7, 2010 at 4:50 UTC
Rusty, I think that may have fixed alot of my problems. Must have been something goofy happening with the outbound connection when set as an exchange. As soon as I made it smtp and turned the refresh time down to 60 seconds, I got my test promptly in my inbox. Thats interesting that the exchange connection would be that flawed, even though it passes account tests during setup.
I still have my inbound set as exchange and it seems fine, at least thus far. I suppose if it becomes problematic, I will try it with imap going forward. Anyway, good call on that. Thanks everyone for your input.
Oct 7, 2010 at 4:56 UTC
Cool - glad it worked. I would switch to IMAP now just for performance.
When I had Exchange, it worked perfectly, but I think some people have issues with newer version of Exchange (2007, 2010), if that's what you're running.
This discussion has been inactive for over a year.
You may get a better answer to your question by starting a new discussion.


text:
Latest SimpleCove Video
How To Make A Dovetailed Blanket Chest
Latest Blog Posts
If you plan on working with veneer, you're going to need to know how to flatten it. Let me show you how I do it.
This 2 step recipe makes this inexpensive lumber look great.
Learn How To Make This
Follow along as Sean shows you how to build a beautiful dovetailed blanket chest!


text:
user functions
Current Ithaca College community members may contribute stories and comments as well as view additional topics by logging in.
related links
Writing Intensive Workshop - Register Now
Contributed by Wade Pickren on 09/19/12
Monday, September 24, 2012
What do we mean by "writing intensive?" And how can a faculty member effectively manage the "paper load" that accompanies writing in a course? This workshop will introduce the core principles of writing across the curriculum (WAC) and review the ICC description of writing intensive courses. Faculty will have the opportunity to workshop a major assignment, crafting a sequence of writing activities that is both manageable and pedagogically sound.
© Copyright Ithaca College. All rights reserved; unauthorized use prohibited. All material on this server is produced by our community but, except for designated pages, is neither approved nor verified by Ithaca College.


text:
Bernstein Litowitz Berger & Grossmann LLP
1251 Avenue of the Americas
10020 New York
Mr. Graziano is widely recognized as one of the top securities litigators in the country. He has served as lead trial counsel in a wide variety of major securities fraud class actions, recovering billions of dollars on behalf of institutional investors and hedge fund clients.
Over the course of his distinguished career, Mr. Graziano has successfully litigated many high-profile cases, including: Merck & Co., Inc. (Vioxx) Sec. Litig.(D.N.J.); In re Schering-Plough Corp./ENHANCE Sec. Litig. (D.N.J.); New York State Teachers' Retirement System v. General Motors Co. (E.D. Mich.); In re MF Global Holdings Limited Sec. Litig. (S.D.N.Y); In re Raytheon Sec. Litig. (D. Mass.); In re Refco Sec. Litig. (S.D.N.Y.); In re MicroStrategy, Inc. Sec. Litig. (E.D. Va.); In re Bristol Myers Squibb Co. Sec. Litig. (S.D.N.Y.); and In re New Century Sec. Litig. (C.D. Cal.).
Industry observers, peers and adversaries routinely honor Mr. Graziano for his accomplishments. He is one of the "Top 100 Trial Lawyers" in the nation according to Benchmark Litigation, which credits him for performing "top quality work." Chambers USA describes Mr. Graziano as "wonderfully talented…a smart, aggressive lawyer who works hard for his clients," while Legal 500 praises him as a "highly effective litigator." Heralded as one of a handful of Class Action MVPs in the nation by Law360, he is also one of Lawdragon's 500 Leading Lawyers in America, named as a leading mass tort and plaintiff class action litigator by Best Lawyers®, and as a New York Super Lawyer.
A managing partner of the firm, Mr. Graziano has previously served as the President of the National Association of Shareholder & Consumer Attorneys, and has served as a member of the Financial Reporting Committee and the Securities Regulation Committee of the Association of the Bar of the City of New York. He regularly lectures on securities fraud litigation and shareholder rights.
Prior to entering private practice, Mr. Graziano served as an Assistant District Attorney in the Manhattan District Attorney's Office.


text:
You see, I had plans to make salade frisée aux lardons. Unfortunately, it is impossible to make salade frisée aux lardons when you can find neither frisée nor lardons, nor anything resembling an acceptable substitute for either. My local supermarket kind of, well... sucks.
Granted, I'm being a little unfair. After all, it's not Whole Foods, and it can't do anything about the fact that it's located in Boston and not Paris. But it is very frustrating to not be able to make salade frisée aux lardons, or any approximation thereof, when you've spent the better part of Torts class thinking about crisp, bitter curlicues of lettuce and smoky little cubes of cured pork.
Coming up with a new salad idea was problematic. I didn't want mixed baby greens with apples and blue cheese, or spinach with almonds and strawberries, and even a rabbit would probably have turned up its nose at the arugula languishing in the herb section, so I didn't want arugula with olive oil and balsamic vinegar, either. I wanted something crisp and savory that could be made in a bowl large enough to swim in. I wanted Caesar salad.
So I bought hearts of romaine, a wedge of Parmesan, and a tin of anchovies, and figured I'd sort out the dressing by looking it up on Google. It turned out to be remarkably simple.
Caesar dressing, it turns out, it is basically mayonnaise, flavored with garlic and Worcestershire sauce (or anchovies, if you're not concerned about authenticity.) Tableside performances notwithstanding, it can be made in the blender with perfectly decent results.
I should have tried this ages ago. Damn the frisée. I'm off to buy more romaine. I need to make up for lost time.
Caesar Salad Big Enough To Swim In
Not authentic, just tasty.
(Serves four hungry people.)
Take six hearts of romaine and cut or tear into bite-size pieces. Dump them into the biggest salad bowl you've got. If that's not big enough, use a wok or frying pan, or even a stock pot, if necessary.
For the dressing, begin by bringing a pan of water to boil, then remove it from heat. Coddle two eggs by immersing them in the water for one minute. Crack the eggs into a bowl. Whisk in the juice from one lemon, six minced garlic cloves, and six mashed-up anchovies. Continue whisking, and pour in a generous glug of olive oil a little at a time, until the mixture looks creamy. It shouldn't be too thick. (You can also do this in a blender.)
Dress the romaine. Add a dusting of black pepper and a huge heap of freshly grated Parmesan. Toss. Serve with crusty bread.
Note: This doesn't contain croutons, because I don't like the commercial stuff, and I never seem to have any stale bread on hand to make them myself. Don't let that stop you from adding them, though.
*A great Caesar salad is better than sex. Great Caesar salad may be found at Frankie and Johnny's in Cape Neddick, Maine.


text:
Sign up for Equitymaster's free daily newsletter, The 5 Minute WrapUp and get access to our latest Multibagger guide (2017 Edition) on picking money-making stocks.This is an entirely free service. No payments are to be made.
Here is the latest stock price and chart of MODERN MALLEABLES. For a sector overview, read our power sector report.
|Live BSE Quotes
|Not listed
|Live NSE Quotes
|Not listed
|BSE Sensex | CNX Nifty
Benchmark indices in US corrected marginally by 0.8% during the week. Minutes of Federal Reserve's July meeting are out and the situation looks to be in favor of the emerging markets.
NTPC declared results for the quarter ended December 2016. The company reported revenue growth of 10.9% while profits declined by 7.5% YoY.More Views on News
The data tells us quite a different story from the one the government is trying to project.
Don't miss these proxy bets on growing companies or in a few years you will be looking back with regret.
Bharat-22 is one of the most diverse ETFs offered so far by the Government. Know here if you should invest...
The India VIX is up 36% in the last week. Fear has gone up but is still low by historical standards.
Raksha Bandhan signifies the brother-sister bond. Here are 7 thoughtful financial gifts for sisters...More


text:
I Don't Like Promises
Personal Stories, Advice, and Support 186 People
I Dont Ask People To Promise MeAnd i find it scary, and am more aware, if they promise me things without me asking them to.
Candybitch 18-21, F 1 Response 1 Mar 11, 2010
My bf promised to never leave me... Now his saying we been together for a week I can't make any promises to u... Its like the promises he did make to me were lies and he might break up with me soon right? He was meant to go to my sti test today but i feel like I should just go alone and not tell him as he said...
sabzzzz 18-21, F 2 Nov 20, 2015
My entire relationship was built on emptypromises. I just now realized this, and it's too late for me now.
cbnfvr 26-30, F 1 Response 1 Jun 7, 2014
Too Easy to Break.I try not to make promises to people since it's too easy to no follow through. Instead of telling someone that I "promise" to do something or make sure something gets done, I say "I'll try" to do something or make sure something...
Pointless.A certain fragility becomes associated with something once it is branded with those words - 'I Promise' Plans and dreams suddenly hold a greater weight, yet are balancing on a thinner line as the very act of the promise itself becomes reflective on the promise giver's...
PromisesPromises,Hate 'em,Made to be broken,Usual bull,I'm tired of it,that's why I make 'em,No more!
lazycrazybasket 46-50, M 0 Dec 12, 2011
I Hate When People Make Promises to MeIt seems every time someone promises me something, it usually doesn't happen. Drives me crazy.
SmotherMe 26-30, F 1 Response 0 Nov 16, 2008
Making Or Hearing ThemI try to avoid promises in every capacity. It's just my way.
Broken PromisesI hear your best intentions, to the point of getting bored, when you make such promises, it leaves your game unscored. It's better not to mention it, then give me a surprise, when I heard your excuses, they sounded more like lies. If you have respect for...
emmasharn 31-35, F 0 Jan 28, 2010
I don't like them because the love of my lifepromised she wouldn't leave me but she did.
23fly41 18-21, F 1 Response 0 May 19, 2015
Promises Were Meant To Be BrokenI really dislike promises every one that has promised me something has broken them I myself use the term but thats all it really is promises are the biggest let down and if you really feel like I'm being a little harsh here people really think back on the promises made to you...
drkiris 26-30, F 0 May 1, 2010
Too Easily BrokenI don't make promises or committments I don't keep, and I don't say "I love you" when I don't mean it. It's hard when few others play by the same rules.
zillaron 51-55, M 5 Responses 0 Jan 28, 2010
Promises Scare MeI hate promises because I'm afraid of the future and don't believe anyone will ever be there for me always. Promises and plans are only heartbreak waiting to happen, though, admittedly, I have made plans that happened and knowing they would was thrilling. But I'm...
psychesuicide 18-21, F 1 Response 0 Mar 25, 2009
I don't like making promises.Time is so fragile and unexpected that i don't even know if i'll wake up tomorrow morning. Promises become broken promises which ultimately lead to heartbreak #dontpromise
Appleshavefeelingstoo 18-21, F 0 Jan 12, 2014
Yes I Do! ...Yes i do! only if they are kept, i hate making a promise and then breaking them,. When i make a promise then friends and aquaintences, know i will keep them!
welshbabe 46-50, F 1 Response 0 May 19, 2009


text:
I feel as if my best guy friend (4 years) and I have a slight chance of being more than friends. I was just curious as to how you would transition to a relationship. Or is there really no transition?
Most Helpful Guy
I would just straight up tell him, hey I think I may be starting to have feelings for you. Do it kinda slow though, making sure that he knows if he does not want to be more than friends then you can remain friends (If you can). He may or may not like you back, some guys will wait that long if they think its worth it.
But if that is not the way you want to do it you could also just invite him over and grab and hold his had and see how he reacts haha but that could either end really awesomely or kind of awkwardly.11|00|0
I can say we've done a lot for each other. Like he's always there for me and recently this guy I was crushing on cut me out and I told him. I felt like that brought us closer.
He also always tells me we'll go out to restaurants around the area or just hang out. There was a time when we were in a busy area with a lot of people and I told him he might lose me so he grabbed my hand and once we got to a calmer area I let go because I was scared. Yeah, I know. I'm stupid. I don't know if what he's doing is because we're best friends or... We also call each other bae and boo. It started out as a joke but it kind of stuck.


text:
Forgot your password?
Don't have an account? Get Started
Already have an account? Log in here
By Deep Trekker Inc.
By Fusion Marine Limited
http://www.tmcfluidsystems.com Email us at: firstname.lastname@example.com We specialize in the supply of Pressure Systems, Vacuum Systems, and Airknife Drying and Blow-off Systems. Our Blowers are being used extensively for aquaculture, fish farming, and in the hydroponics industry. Biogas Blowers, Bio Gas Blowers, Roots Blowers, Gas Blowers, Airknives, Pressure Systems, Vacuum ...
By TMC Fluid Systems, Inc.
715-262-4488 http://www.kascomarine.com Joe Holz describes how easy it is to change the zinc anode on Kasco fountains, circulators, de-icers and aerators. He explains when it's time to change the zinc anode, and how to properly change and re-install it. About Kasco Kasco, a leader in the water management and aquaculture industries, specializes in providing innovative solutions for aeration, ...
By Kasco Marine, Inc.
FIAP profiwork Salmofix -- FIAP's original -- has been in practical use for decades. Being a slaughtering aide for fish farms as well as for small to medium-sized production plants, FIAP profiwork Salmofix has been tried and tested. FIAP profiwork Salmofix facilitates ready-to-kipper gutting and perfect cleaning of food fish in one single working step. Food fish (of 200 -- 1300 grams of weight) ...
By FIAP GmbH
Wet type fish feed machine is widely used for producing grains into aquatic feed pellets for fish, catfish, shrimps, crab, cat, dog and etc. Grain materials are such as wheat, soybean, cake and other leftovers and etc.. puffing pellets produced by pellet machine can float on the water surface without dissolution for over 12 hours. Wet type feed extruder is mainly employed in medium or large size ...
By Azeus Fertilizer Machinery Co.,Ltd.
1. A wide range of raw materials such as corn, wheat bran, paddy, soybean meal, paddy rice, sorghum, etc. The raw material is experienced by the high temperature and high pressure, which can kill the salmonellosis and bacterial infections. 2. Besides floating fish feed and sinking fish feed, this production line can also produce high quality feed for pet like dog, cat and etc., application for ...
By Zhengzhou Azeus Machinery Co.
By FishFarmFeeder
The US2 seal scrammer, is a seal deterrent, designed by John Ace-Hopkins of Ace Aquatec. www.aceaquatec.com. This is a silent scramming device that protects commercial fisheries from seal predation. Currently most fish farmers shoot seals on sight, an inhumane and destructive practice. Other companies also sell seal scaring devices however they are highly prone to seal habituation due to the ...
By Ace Aquatec Ltd
Need help finding the right suppliers? Try XPRT Sourcing. Let the XPRTs do the work for you
Minimum 250 characters
Already have an account? Login here


text:
I've been learning Swedish for a while now, and I'm getting to the point where I can understand both Swedish and Norwegian, but I'm still far from conversational, and that's where I'm struggling as there aren't many Scandinavians in these parts. Tack!
Most Helpful Girl
Im Swedish and I can barely understand Norwegian AT ALL... 😂 But sure... Skicka meddelande om du vill prata. 😊10|10|0


text:
Using our website
Our website adheres to the Web Content Accessibility Guidelines (WCAG), which are used to ensure websites are designed and written in a way that makes them as accessible as possible whilst maintaining the highest levels of usability.
This statement explains the facilities provided and how to use them. Should you experience any difficulty in accessing the Barclays website, please don't hesitate to contact us.
Across the site we have adhered to the following accessibility guidelines:
Our service helps you call and talk to us safely using British Sign Language (BSL). We connect you to an interpreter who communicates your sign language to the adviser.
Logging in to your account on our website is a two-step process:
For security reasons, these identifiers are presented as images without alt text. For users that can't see the images, we have provided a link to audio assistance immediately after the 2 password input fields.
Skip links
At the top of every page are two skip links:
Global navigation
Our website is primarily navigated via a menu, which is present on every page immediately after the page header. Each menu item (except the first, a link to the homepage) has a submenu that is a set of links to deeper within the site. Individual links may be followed by additional descriptive text and are grouped together under headings.
When the cursor focus is on a top-level menu item, pressing the 'Tab' key will move the focus to the first link in that menu item's submenu. You can also use the key combination 'Shift + Cursor Left/Right' to move directly to adjacent top-level menu items.
Local navigation
Top-level menu items remain clickable and lead to overview pages that highlight and link to key subsections of content within that area of the site. Pages within these subsections then feature local navigation: a list of links to each of the other pages within that subsection.
Tabbing through the Deal form follows a natural progression of decisions from, for example, finding a stock, opting to buy or sell, selecting a type of order and finally entering an amount of pounds or shares to trade. Each step includes a link to further help.
To select a stock, fund or structured product, type a stock symbol or name and a filtered list of stocks that match your input will appear. Navigate this list using the 'Up/Down' cursor keys, and press the 'Tab' or 'Enter' key to select that entry.
Similarly, to enter an expiry date for a limit, stop or trailing stop order, an interactive calendar is presented to select a valid date. The calendar opens to the last selected date (if one exists), or to the current date. You can navigate to adjacent dates by pressing the 'Control' key and using the cursor keys. Use the 'Enter' key to select a date. It is not possible to type in a date directly, the calendar must be used.
To change font and colour settings:
Text with a sans serif font (such as Arial) is easier to read than a serif font (such as Times New Roman). To change the text font:
To enlarge the text:
To change the text colour and background colour:
To prevent graphics displaying:
To change the size of the window:
If you're having trouble finding what you're looking for on the site, please our Site Map or 'Search' box at the top of every page.
System requirements
If you're unable to view our site correctly, please ensure that your system meets our minimum recommended system requirements.
If you're still having trouble, please contact us.
If you would like to know more about accessibility and the Internet, you may be interested in the following websites:


text:
Eworld Blogs
Leather saddle antique bicycle classical vintage, headlight rood brakes roadster pinstriping .. decals restoration rims chainguard mudguard frame crank cotter pin bell chrome grips coil
Owner: reciclone
Listed in: Arts
"To help you choose your smart choice
Owner: LORD25
Listed in: Technology
US based leading media and entertainment player, Lafango, the owner of world's biggest online.. multimedia talent platform has launched first of its kind innovative international beauty pageant,.. "Miss eWorld 2010
Owner: gauravpassy
Listed in: Arts
Other Tags: lafango.com,gauravpassy,eworld
Cahayapoker.com Situs Agen Judi Poker Dan Domino Uang Asli Online Terpercaya Indonesia
Owner: idrpokerdomino
Listed in: Entertainment
Other Tags: Agen Poker, Poker Online, Judi Poker, Agen Domino, Domino Online
5. ZIPCodeWorld
United States ZIP codes, Canadian Postal codes, Mexican Postal codes, NPA NXX Area Codes and Store.. Locator
Owner: zipcodeworld
Listed in: Internet
Other Tags: zip codes, zip code database, united state zip codes, canadian postal codes, Mexico Código Postal
A unique view from a Bangkok-based blogger, Joe, coloured w/ tales & anecdotes from across the.. planet and, at times, yonder!
Owner: happyjoeworld
Listed in: Personal
We enable users to upload and share PowerPoint presentations online and embed slideshows in own.. personal blogs, convert to video and share on various social media platforms to get more online.. visibility.
Owner: allystercampbell
Listed in: Computers
Other Tags: Upload Powerpoint Presentation, share Powerpoint Presentation, Powerpoint Presentation
8. igoseeworld
A friendly travel blog with useful travel information and first-hand experience on trips around the.. world.
Owner: igoseeworld
Listed in: Travel
Other Tags: Travel, Adventure, Trekking, Sightseeing, Nepal
9. BraveJeWorld
Terrorism and Counter-Terrorism in Israel and the Middle East
Owner: BraveJeWorld
Listed in: Politics
Other Tags: Terrorism, Israel, Middle East
10. Cherry's Eworld
a magic castle electronics
Owner: aboutyxm2005
Listed in: Technology
Other Tags: seekic, chinaicmart