text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 7, 2006
|Filing date
|Feb 13, 2001
|Priority date
|Aug 24, 2000
|Fee status
|Publication number
|Michael D. Hutton
|Original Assignee
|Altera Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Non-Patent Citations (23), Referenced by (14), Classifications (11), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
This application claims priority of (i) provisional U.S. Patent Application Ser. No. 60/228,066 filed Aug. 24, 2000, titled "Method for Adaptive Critical Path Delay Estimation During Timing-Driven Placement for Hierarchical Programmable Logic Devices", and (ii) provisional U.S. Patent Application Ser. No. 60/261,523 filed Jan. 12, 2001, titled "Method for Adaptive Critical Path Delay Estimation During Timing-Driven Placement for Hierarchical Programmable Logic Devices" which are each incorporated by reference in their entireties.
The present invention relates to computer-assisted methods and apparatus for generating or compiling electronic designs such as designs for digital integrated circuits. More specifically, the invention relates to improvements in using timing information while compiling electronic designs.
Electronic design automation ("EDA") is becoming increasingly complicated and time consuming, due in part to the greatly increasing size and complexity of the electronic devices designed by EDA tools. Such devices include general purpose microprocessors as well as custom logic devices including Application Specific Integrated Circuits ("ASICs"). The design of even the simplest of these devices typically involves generation of a high level design, logic simulation, generation of a network, timing simulation, etc.
Meeting timing requirements is essential to the correct operation of an integrated circuit. For example, for a plurality of D-type flip-flops ("DFFs") to feed through some logic to another plurality of DFFs, it is generally required that the signals from the first set of DFFs must finish propagating through any intermediate logic and have settled to their final state on the D-input of each of the destination DFFs before the next rising edge of the clock. If the delay through the resulting logic is greater than the time between rising clock edges, then the state that the destination DFFs will hold on the next clock edge will be undefined.
In order to meet timing requirements optimization methods are applied. Optimizing a circuit can occur at any time during synthesis, technology mapping, clustering, placement, or routing. Most optimization methods require an identification of "critical connections" between circuit elements or blocks. Emphasis is made during optimization to optimize the timing of those connections having the greatest criticality. For example, during placement, the placement algorithm will attempt to keep those elements or blocks having a critical connection in a configuration where the connection would be made with as little delay as possible. A critical path is a path that has the longest delay. In fact, there may be several critical paths in a circuit. The cycle time of the clock that controls the DFF's at the beginning and end of the path cannot be any less than this delay. A critical path may consist of one or more connections, and all those connections will be critical.
Several different methods are used in circuit optimization to determine which connections are critical and therefore need to be made via fast wiring lines to avoid slowing down the circuit. Optimization is typically required in the conversion or placement of an electronic design in the form of a netlist into a physical device, such as an FPGA or CPLD. A traditional recursive partitioning algorithm will recursively divide an electronic design in half and repeat the division until the design is fully placed into the device. Partitioning methods may be applied to flat architectures such as gate arrays but are especially suitable for hierarchical architectures such as Altera's APEX 20K family of devices. In hierarchical architectures, crossing center boundaries involves significant costs in the form of delays added. Typically, as an electronic design is divided in half and again in half, the placement tool will attempt to minimize the wires which cross between physical half A and physical half B of the physical device to avoid lengthy delays across critical paths. As the wire placement or "cut" crosses boundaries lower in the hierarchy, smaller delays are added for each cut until the point where the wire placement between two cells occurs entirely within a cell and no additional delay is added.
The goal of this process is to obtain a faster circuit, generally when the longest delay of the placed design into the physical device is minimized. This measure is often stated in terms of a faster frequency for the circuit. After every cut of the design into the physical part the user or tool will know the actual delays contributed by that cut since for any such physical electronic device, the logic delays across the boundaries are known for that architecture. Since interconnect delays for the architecture are known for a fixed distance and load, a fully placed netlist has a deterministic timing analysis. A partially placed netlist, however, has a known timing analysis only if the placement algorithm gives the timing analyzer an estimate of unknown interconnect delays for edges not yet routed or placed.
A netlist with nodes and edges annotated with their electrical delay allows the user to compute, for each node and edge, the maximum delay from a source or to a destination, and hence the length of the longest path through that node or edge. Given a target delay (constraint) on an A to B path, the slack delay for that path is the (most stringent) constraint minus the actual delay of the path For a given node or edge, the slack of the node or edge is the minimum slack over all paths which contain the node or edge. All these values are well-defined in a synchronous netlist, and computable in linear time with several graph traversals.
A critical path is one which has the minimum slack over all paths. In a single-clock system with a single global fmax (register—register) delay constraint, this is equivalent to the path with the maximum delay. In a multi-clock system with different fmax specifications for different clocks, or with specific point-to-point path constraints, minimum slack is not equivalent to maximum delay. The goal of a timing driven compilation is to maximize the worst-case (minimum) slack.
One problem with the use of recursive partitioning as an algorithm for timing-driven placement is that the true path delays are not known in the early stages of placement. Therefore identifying the critical paths before the netlist has been placed is difficult. The partitioning algorithm can minimize the number of critical nets which are cut early on, yet these nets may not be the true critical nets by the time the partitioning tool has proceeded several levels deep in the placement, due to the delays added by the cuts. This problem is intrinsic whether or not the target architecture is hierarchical, but is exacerbated by non-uniform delays in a hierarchical part.
What is needed therefore is an improved method for estimating the delays for edges or connections which have not yet been placed in order to identify accurately the critical paths.
The present invention provides a method for more accurately estimating delays for connections which have not yet been placed. Partitioning places a source design into a target device and divides the design in half, followed by successive divisions of the source design until the entire source design has been cut or placed in the device and all connections in the source design correspond to wires in the physical device. The objective in the process is to avoid placing connections which require fast wires across slow boundaries. As a partition proceeds in phases, determining which connections are critical (and therefore require faster wires) is done based on actual delay data for cuts already placed and estimated data for the connections which have not yet been cut in the device. The present invention provides a method for estimating delay data comprising receiving a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized.
In yet another embodiment, the partitioning and estimation of delays on the paths is repeated successively prior to a next phase of partition.
Another aspect of the invention pertains to computer program products including a machine readable medium on which is stored program instructions, tables or lists, and/or data structures for implementing a method as described above. Any of the methods, tables, or data structures of this invention may be represented as program instructions and/or data structures that can be provided on such computer readable media.
Yet another aspect of the present invention pertains to a computer system comprising at least one CPU, memory, and an interface for communicating with an individual. The computer system is configured to receive the electronic representation of the design, estimate the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and to revise the electronic representation toward a state in which high criticality connections are changed in a manner that reduces delay.
These and other features and advantages of the present invention are described below with reference to the drawings.
Introduction and Overview
Reference will now be made in detail to some specific embodiments of the invention. Examples of specific embodiments are illustrated in the accompanying drawings. While the invention will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to any particular specific embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
Some of the terms used herein are not commonly used in the art. Other terms have multiple meanings in the art Therefore, the following definitions are provided as an aid to understanding the description that follows. The invention as set forth in the claims should not necessarily be limited by these definitions.
The term "compiler" is used throughout this specification to refer to software and apparatus for running such software that compiles an electronic design. Its functions may include extracting and synthesizing a netlist, mapping the design to a given hardware architecture, placing and routing the design, simulating the design, etc.
The term "source electronic design" generically refers to the logical structure of an electronic device such as an integrated circuit. It may be implemented on hardware (usually referred to herein generically as a "target hardware device"). During the design and development effort, an electronic design may exist in various states or stages. It may be provided as a high level Boolean representation (encoded in a hardware design language for example), a schematic or circuit representation, or any other form representing the logical arrangement of a device. It may include other facets such as floor-plan constraints, wave-form constraints, timing constraints, fitting constraints, etc. At the gate level, it may exist as a netlist (whether synthesized or not) prior to placement on a target hardware device. It may even include completed place and route assignments.
A "netlist" is used to describe the functionality of a digital circuit design that can be implemented on a programmable logic device or other target hardware device. The netlist is represented as hierarchical collection of gates, state machines, high level constructs such as counters or adders, or any other means of defining a collection of outputs based on a collection of inputs. The nodes of the netlist (gates, state machines, etc.) are connected together via nets. Each of these nets is associated with a named digital signal. A netlist may be synthesized to remove redundant logic, simplify the gate layout provided by a user, etc.
When in the form of a synthesized netlist, a source electronic design may be divided into "logic cells" representing various logic functions within the electronic design. During compilation, these logic cells are mapped onto physical structures known as "logic elements" which reside on the target hardware device. The criteria for mapping gates into logic cells is that the resulting logic cell must be able to be put into one logic element. An example of a logic cell is a collections of gates (connected in some way and implemented in a look-up table) combined with a register and configured to implement a multiplexer.
The term "target hardware device" refers to a hardware device on which an electronic design is implemented. Examples include circuit boards and systems including multiple electronic devices and multi-chip modules, as well as integrated circuits. Specific examples of integrated circuits include traditional multi-purpose microprocessors, traditional integrated circuits with full custom layouts, hardwired ASICs (e.g., gate arrays) designed with high level design tools, and programmable integrated circuits such as FPGAs and PLDs. In the case of non-programmable integrated circuits such as gate arrays, the electronic design defines the arrangement of metal lines on one or more metallization layers of the target hardware device. In the case of programmable integrated circuits such as PLDs, the electronic design defines the gates as well as interconnects to be programmed on the target hardware device.
In the context of this invention, a target hardware device typically includes a plurality of logic elements which house logic cells from an electronic design in order to implement the logic functions specified by these cells. The logic elements are typically a fundamental element of the hardware device's architecture on which different logic gates can be defined. These elements may be grouped into blocks such that each logic element is associated with a block (or other arbitrary containment entity). There may be higher level organization in the device such that logic blocks are grouped into rows or some other arbitrary entity.
A "connection" is an electrical link from the output of one block to the input of another block. Often, a connection is embodied as a conductive strip (e.g. a metal strip) or a switch together with a conductive strip. Examples of these blocks include logic gates, registers, memory, logic cells, I/O pads, groups of logic elements such as logic array blocks, etc.
A "path" is several connections in series. A path could include the circuit elements as well as the connections lying between them. The timing analysis tool will measure between points to establish a set of paths. The points measured could be input to output, input to register, register to register, or register to output.
The term "fitting" is used throughout this specification to describe a process whereby a compiler fits an electronic design onto a target hardware device. The term "fit" may be used interchangeably with the phrase "place and route." As this synonym suggests, fitting can be divided into two phases: a placement phase and a routing phase. The present invention can be applied to all phases of the design process, including but not limited to placement and routing. In placement, a compiler positions logic cells of the electronic design with respect to logic elements of a target hardware device. The invention may employ generic place and route algorithms—including many conventional and commercially available algorithms—employed during design development.
In a specific embodiment, the compiler is divided into software submodules. Referring to
A user can enter an initial or source electronic design by various methods. For example, a schematic editor program allows the user to enter and/or modify a schematic diagram of the electronic design using the display screen, generating a net list (summary of connections between components) in the process. This is commonly referred to as a schematic capture method. An equivalent method for entering an electronic design involves providing a description of the design in a Hardware Description Language (HDL). Examples of HDLs include Verilog and VHDL. The syntax of a VHDL description is described in IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987). Like the schematic representation, the HDL representation also provides a net list.
A common goal in partitioning is to partition or divide a design to minimize the number of input/output pins on the devices. During placement of the design by partitioning methods, actual delays for connections are only known for the connections already placed across boundaries. As shown in
An example of a programmable logic hardware device to demonstrate the role of partitioning is shown in
To fit a logic design onto a target hardware device such as that shown in
Often, a multilevel hierarchical structure such as that shown in PLD 300 includes multiple levels of routing lines (interconnects). These connect the uniquely placed logic cells to complete circuits. In PLD 300, for example, four levels of interconnect are provided, one for each of the four hierarchy levels.
The basic logic-element (LE) 302 is a 4-input LUT and DFF pair. Groups of 10 LEs are grouped into a logic-array-block or LAB 304. Interconnect within an LAB 304 is complete, meaning that a connection from the output of any LE 302 to the input of another LE 302 in its LAB always exists, and any signal entering the input region can reach every LAB.
Groups of 16 LABs form a MegaLab 306. Interconnect within a MegaLab requires an LE to drive a GH 308 (MegaLab global H) line, a horizontal line the width of the MegaLab, which switches into the input region of any other LAB in the same MegaLab. Adjacent LABs have the ability to interleave their input regions, so an LE in LAB i can usually drive LAB i+1 without using a GH line 308. A 20K400 MegaLab, for example, contains 279 GH lines.
The top-level architecture is a 4 by 26 array 300 of MegaLabs. Communication between MegaLabs is accomplished by global H 310 (horizontal) and V 312 (vertical) wires, which switch at their intersection points. The H and V lines are segmented by a bi-directional segmentation buffer, 311 and 313, at the horizontal and vertical centers of the chip. The use of a single (half-chip) H or V line as H or V and a double or full-chip line through the segmentation buffer is denoted as HH 314 or VV 316. In the APEX architecture, H 310 and V 312 lines cannot drive LEs directly; they drive a GH which then functions as in the MegaLab case above (so an H delay implies an additional GH delay). Because of segmentation of the H and V lines, further hierarchies of same-row, same-MegaLab-column and same-quadrant are implied for both routability and timing purposes. The 20K400 contains 100H lines per MegaLab row, and 80 V lines per LAB-column (80*16 per MegaLab column).
The delay of a point-to-point connection can be categorized as "local" for same-LAB connections, GH+local for same-MegaLab, H+GH+local for adjacent horizontal MegaLabs, V+GH+local for same octant of the chip, and V+H+GH+local for same-quadrant of the chip. The maximum (worst-case) delay is an HH+VV+GH+local connection.
A local interconnect consumes approximately 1 unit of delay, a GH 2 units of delay, H or V 2 units of delay, and an HH or VV 4 units of delay. Thus the ratio of the shortest (local) to longest (HH+VV+GH+local) connection is roughly 1 to 11.
In a target hardware device, there will be many paths available for routing a given signal. Each of the interconnects identified above is a connection responsible for conveying signals between groups, as in the case of "global horizontal" or "global vertical" interconnects, or to interconnect elements within a group as for example accomplished by local interconnects 318 shown in
Each MegaLab 306 also has a 2K-bit configurable RAM, which is accessible in much the same way as a LAB. The delay through a RAM is also considered to be a fixed value independent of placement However the choice of which MegaLab contains a particular logical RAM and the routing of address and data lines to the RAM are part of the placement problem.
Placement Algorithm
The natural way to place a netlist in this type of part is to do a recursive k-way partition. Each step will be referred to as a phase in the overall algorithm. Though the effectiveness of this type of algorithm is greatly affected by implementation details, the basic recursive partitioning flow is as follows and as illustrated in
Phase 1: Partition the netlist into a left 402 and right 404 horizontal halves, minimizing the overall cut-size (number of HH wires).
Phase 2: Bi-partition each half independently, dividing the netlist into horizontal quarters 406, 407, 408, and 409 (MegaLab columns) to minimize cut-size (H lines).
Phase 3: Partition the entire netlist into a top half and bottom half, minimizing cut-size (VV wires) while respecting the MegaLab columns previously assigned. The result is 8 octants 421–428.
Phase 4: Partition the top and bottom netlists 13-ways into rows (430–442) to minimize the number of connections (V wires) while respecting the previous vertical partitions.
Phase 5: Partition MegaLabs into LABs, trying to balance V-line usage in individual columns, and the input-region of each LAB.
In each of these partitioning steps, the implementation details must count and balance secondary signals (clock, clear, enable), RAMs, and logic cells separately, as the resulting partition must be correct for all types of logic. Because carry-chains and other data-path elements have regular output, care must be taken to balance their relative placement to balance local congestion.
A recursive partitioning approach has a number of advantages. The complexity of the algorithm is buried in the partitioning subroutine, a well understood problem in CAD which can be regularly updated independent of multiple architecture families. Graph partitioning algorithms are typically fast (linear) time, and thus the overall algorithm is also linear. Further, the partitioner can be de-coupled from the architecture-specific details and easily updated with new partitioning technology. The overall algorithm is simple and easy to maintain, even in the presence of heterogeneous resources and other constraints. Because the production system has to deal with numerous such additions to deal with a real architecture, and is regularly modified to deal with new architecture families and devices, these latter issues are particularly important. This method permits the introduction of a timing-driven algorithm within the context of the existing place and route flow.
In hierarchical programmable logic architectures such as the Altera APEX and FLEX families, the standard algorithm for automatic placement is based on recursive partitioning of the netlist into more and more refined bins in the physical device. In the more hierarchical APEX architecture, the design goes through approximately 5 different stages or phases of partitioning. In early partitioning phases, signals need to be identified as critical if they lie on a critical path. However, due to the unknown effects of later partitioning phases, it is extremely difficult to determine in advance which paths or portions of the netlist will after full placement of the source electronic design into the target device lie on the placed critical path. Paths initially thought to be non-critical based on the number of connections in the path may, after several cuts, turn out to be critical because of the delays added by the cuts, i.e. wiring across the physical boundaries of the device. The present invention provides more accurate information as to the delays anticipated from future cuts by using statistical prediction for the delays on uncut segments of paths which have not yet been placed. The statistical estimate of delays from future cuts is based on empirical data developed from placement of other designs using conventional partitioning techniques. The statistical data is generated for each phase of the partition process and is defined for the purposes of this application as a phase-local for each partitioning phase.
Phase Local
For a hierarchical architecture with h levels of hierarchy the phase-local for phase i is defined to be a weighted average of the probabilistic delays of all stages i+1 to h.
For a range of benchmark designs, a statistical distribution is generated, representing for each "local" connection after phase i, the resulting average number of H, V, GH and local wires occurring for that connection after complete placement Though not crucial, it is of practical benefit to calculate this value statistically.
For the example of the APEX 20K400, for the first 2 phases of the 5 partitioning phases involved,
phase_local(1)=f 1(HH+VV+gh+loc, H+W+gh+loc, H+V+gh+loc, . . . , gh+loc, loc),
phase_local(2)=f 2(H+VV+gh+loc, H+V+gh V+gh+loc, . . . , gh+loc, loc),
where the value phase_local(i) refers to the value of a local delay in the i'th partitioning phase. As the partitioning process proceeds through the hierarchy, the phase locals will represent smaller delays since the subsequent cuts after the first two will not cross major boundaries in the device.
In one embodiment the statistical estimate is a simple linear combination of future cut-delays weighted by their empirical probability of occurrence. The function f1 is prob(HH)*delay(HH)+prob(VV)*delay(VV), . . . For phase f2 the HH cuts are now known exactly (they occurred in a previous cut or phase of the partitioning process and their associated delays are known for the device) and do not appear in the calculation. All probabilities adjust accordingly. As described further below, in addition to the phase-local based on average expected delays, pessimistic and optimistic phase locals can be generated form the experimental results from the sample designs.
It should be understood that the present invention is not limited to the above described hierarchical architecture or any other hardware architecture for that matter. In fact, it is not even limited to programmable logic devices. It may be employed generically in target hardware devices as broadly defined above and including applications such as ASIC's, circuit boards, full custom chips, and PLD's. PLDs are just one example of integrated circuits that can benefit from application of the present invention.
At this point the estimate of delays attributable to future cuts is based on a unit delay for all future cuts. In other words, since all connections of the source electronic design are uncut, the probabilistic measure equates to each path having an estimated delay proportional to the number of connections in the path, i.e. the length of the path. Determining the criticalities for the paths (504) allow the critical paths to be identified in preparation for another partitioning cut To the extent feasible, first cuts are avoided or minimized on these critical paths when the hardware device is partitioned with the first cut (506). As described above, the wires across the first cut will typically constitute a connection across the device's segmentation buffer (e.g. an HH or VV line) and will experience one of the worst delays in the device. The net effect of the initial cut is that some paths which previously may have appeared as non-critical may become critical because of the added delays due at lest in part from crossing this major boundary.
After the first cut, critical paths are identified based on actual delay data from the known cuts and probabilistic estates generated from the evaluation of other designs using traditional partitioning algorithms (508). The probabilistic estimates constitute the phase-local for that phase. For example, since the first cut may have placed the source design into left and right halves of the target device, HH delays from this cut are known. For those paths crossing the vertical boundary of the device, the total path delay will be a sum of the cuts and non-cuts. The cuts represent the delays using RH interconnects whereas the non-cuts represent the probabilistic estimate of future cuts. For example, for a given path comprising 7 connections and cut once by a partition, the estimated delay is the sum of the actual cuts (1 HH connection) and 6 non-cuts (6 times the phase local for this phase). This method permits a more accurate estimation of the delays to be expected from future cuts tan provided by the mere use of a unit-delay. The combination of actual delays for cut connections and statistical estimates as applied to non-cut connections allows the tool to more accurately identify the critical paths. The source design is then partitioned with another cut using this revised critical path data (510), again attempting to minimize or avoid cuts across the newly identified critical paths. In one embodiment, a determination would follow as to whether the source design was fully placed (518), such as, for example, in the APEX 20K device described, whether the partitioning had proceeded through the 5 different phases or levels of hierarchy. Where the design had not yet been fully placed, the method would proceed to estimate the criticalities of connections (508), this time based on the new data, i.e. actual data from another cut or phase of partitioning and a new phase local for the upcoming phase. The new phase local would be a function of the probabilities applicable to the levels of cuts not yet made. These probabilities are determined by examining a sampling of electronic designs placed by conventional techniques and determined the percentage of cuts attributable to each level of cut. Following each partition phase, this loop, which includes estimating criticalities based on the new delay data (508) and partitioning to avoid or minimize cuts on critical pats so determined (510) is repeated until full placement of the source design.
In another embodiment, after each partition cut, a determination is made as to whether the delays from the partition meet or beat the previous estimate (512). The previous estimate is the estimate of the critical path delays before the most recently performed partitioning cut. For example, after a phase 2 partition, critical paths to be avoided in the next partition are identified by calculating path delays as a sum of actual delays generated by previous cuts and the statistical estimates as to delays from future cuts. Where the looping option represented by block 512 is incorporated into the process, the estimated critical path delays calculated after the last partitioning cut are compared with the previous estimate of critical path delays based on the statistical data or phase-local for that type of cut. If there is a sufficient difference, i.e. the critical path delays are getting worse, the phase local will be adjusted to reflect the proportionate share of actual delays experienced in the most recent partitioning phase and appropriate adjustments made to the probabilistic estimates for the lower levels of hierarchical connections to develop a new phase local. The adjusted phase local would in this case show an increased delay to reflect the actual observations from the most recent partition attempt where the delays from the cut were longer than previously estimated (before the cut). Using the new phase local data, the design will be repartitioned with the same level cut (516) followed by a determination as to whether the new delays correspond to the most recent estimate, (512). If the estimate of critical path delay does not meet or beat a previous estimate, an estimate of delays from future cuts is adjusted, (514). This loop can repeat until satisfactory correspondence between the actual and estimated delays for that partition level occurs. This process continues until the design is fully placed (518).
The statistical data for delays to be attributed to fixture cuts ensures a more accurate delay estimate than provided by estimates based only on the length of paths. As illustrated in the flowchart of
In the embodiment described above, the statistical estimates (or phase-local) gathered from the experimental results from implementing the sample designs is based on the typical or expected phase local, i.e., the 50th percentile wires. For example, after partitioning with type 1 (HH and type 2(H) wires in an APEX device as illustrated in
phase local=0.2*(2 ns)+0.3*(1 ns)+0.5*(0.5 ns)+0.95 ns (50th percentile)
In one embodiment, rather than using a 50th percentile phase local, a pessimistic phase local is used to estimate the delays from future cuts. The pessimistic phase-local determines the resulting delays based on connections on the path receiving worse than average behavior in future cuts. For example, the pessimistic phase-local may be defined as the weighted average based on the 95th percentile wires in the experimental results form the sample designs. In similar fashion, and in another embodiment, an optimistic phase local is used to estimate future delays. For example, a user might select the weighted average based on the 25th percentile wires from the experimental results of the sample designs. This would provide an estimate as to future delays based on an assumption that the wires will have delays better (shorter) than average. The actual percentages described are for illustration purposed only and the invention should not be construed as limiting the invention. Variations and modifications will be apparent to those of skill in the art.
Implementation Apparatus
Embodiments of the present invention relate to an apparatus for performing the above-described operations. This apparatus may be specially constructed for the required purposes, or it may be a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. The processes presented herein are not inherently related to any particular computer or other apparatus. In particular, various general-purpose machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required method. The required structure for a variety of these machines will appear from the description given above.
In addition, embodiments of the present invention further relate to computer readable media that include program instructions for performing various computer-implemented operations. The media may also include, alone or in combination with the program instructions, data files, data structures, and the like. The media and program instructions may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to, magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM disks; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory devices (ROM) and random access memory (RAM). The media may also be a transmission medium such as optical or metallic lines, wave guides, etc. including a carrier wave transmitting signals specifying the program instructions, data structures, etc. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter.
CPU 702 is also coupled to an interface 710 that includes one or more input/output devices such as such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers. Finally, CPU 702 optionally may be coupled to a computer or telecommunications network using a network connection as shown generally at 712. With such a network connection, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method. The above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.
The hardware elements described above may be configured (usually temporarily) to act as multiple software modules for performing the operations of this invention. For example, instructions for running an optimizing method and/or compiler may be stored on mass storage device 708 or 714 and executed on CPU 708 in conjunction with primary memory 706.
In one specified embodiment this invention also relates to programmable logic devices programmed with a design prepared in accordance with the above-described methods. The invention further relates to systems employing such programmable logic devices.
The system 802 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable logic (including reprogrammable logic) is desirable. The PLD 800 can be used to perform a variety of different logic functions. For example, PLID 800 can be configured as a processor or controller that works in cooperation with processor 804. The PLD 800 may also be used as an arbiter for arbitrating access to a shared resource in the system 802. In yet another example, the PLD 800 can be configured as an interface between the processor 904 and one of the other components in the system 802. It should be noted that the system 802 is only exemplary.
The foregoing describes the instant invention and its presently preferred embodiments. Numerous modifications and variations in the practice of this invention are expected to occur to those skilled in the art. For instance, the techniques and systems of the present invention are suitable for use with a wide variety of EDA tools and methodologies for programming a device. Therefore, the described embodiments should be taken as illustrative and not restrictive, and the invention should not be limited to the details given herein but should be defined by the following claims and their full scope of equivalents.
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|Carl Ebeling et al., "Placement and Routing Tools for theTriptych FPGA", IEEE Trans. On VLSI, vol. 3, No. 4, pp. 473-481, Dec. 1995.
|Hutton et al., "Applications of Clone Circuits to Issue in Physical-Design" 1999. p. VI-448 to VI-451 IEEE.
|Hutton et al., "Characterization and Parameterized Generation of Synthetic Combination Benchmark Circuits" 1998. p. 985-996 IEEE.
|Hutton et al., "Characterization and Parameterized Random Generation of Digital Circuit" 33<SUP>rd </SUP>Design Automation Conference 1996 Las Vegas, Nev. p. 94-99.
|Hutton et al., "Characterization and Parameterized Random Generation of Digital Circuit" Thesis 1997 University of Toronto. p. 123 pages.
|Hutton et al., "Characterization and Parameterized Random Generation of Digital Circuits" 1996 DAC. p. 94-99.
|Hutton et al., "Equivalence Classes of Clone Circuits for Physical-Design Benchmarking" 1999. p. VI-428 to VI-431 IEEE.
|Hutton et al., "Timing-Driven Placement for Hierarchical Programmable Logic Devices". Talk describing aspects of the invention. Monterey, California -Feb. 11, 2001 (paper attached).
|Hutton et al., "Timing-Drivent Placement for Hierarchical Programmable Logic Devices" 2001. p. 3-11 FPGA 2001.
|Jason Cong et al., "Large Scale Circuit Partitioning with Loose/Stable Net Removal and Signal Flow Based Clustering", Proc. IEEE Int'l Conference on Computer-Aided Design, pp. 441-446, Nov. 1997.
|Jon Frankle, "Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGE Routing", in Proc. 29<SUP>th </SUP>ACM/IEEE Design Automation Conference, pp. 536-542, 1992.
|Laura A. Sanchis, "Multiple-way network partitioning", IEEE Trans. On Computers, vol. 38, No. 1, Jan. 1989.
|P. Leventis, "Placement algorithms and routing architecture for long-line based FPGA's", Bachelor thesis, University of Toronto 1999.
|Prashant Sawkar and Donald Thomas, "Multi-Way Partitioning for Minimum Delay for Look-Up Table Based FPGAs". In Proc. 32<SUP>nd </SUP>ACM/IEEE Design Automation Conference, pp. 201-205, 1995.
|S. Sutanthavibul and E. Shragowitz, "Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement", in Proc. 28<SUP>th </SUP>ACM/IEEE Design Automation Conference, pp. 632-635, 1991.
|S.A. Senouci et al., "Timing-Driven Floorplanning on Programmable Hierarchical Targets", in Proc. ACM/SIGDA FPGA Conference, FPGA98, pp. 85-92, 1998.
|Shih-Lian Ou and Massoud Pedram, "Timing-Driven Placement Based on Partitioning with Dynamic Cut-net Control", in Proc. 37<SUP>th </SUP>ACM/IEEE Design Automation Conference, pp. 472-476, 2000.
|Sudip K. Nag and Rob A. Rutenbar, "Performance-Driven Simultaneous Placement and Routing for FPGA's". IEEE Trans. On CAD for Integrated Circuits and Systems, vol. 17, No. 6, pp. 499-518, Jun. 1998.
|V. Betz, Architecture and CAD for Speed and Area Optimization of FPGA's, Ph.D. Dissertation, University of Toronto, 1998.
|W. Swartz and C. Sechen, "Timing-Driven Placement for Large Standard Cell Circuits", in Proc. 32<SUP>nd </SUP>ACM/IEEE Design Automation Conference, pp. 211-215, 1995.
|W.E. Donath et al., "Timing Driven Placement Using Complete Path Delays", in Proc. 27<SUP>th </SUP>ACM/IEEE Design Automation Conference, pp. 84-89, 1990.
|Wilton.S.J.E., "Heterogenous Technology Mapping for Area Reduction in FPGA's with Embedded Memory Arrays" 2000. IEEE p. 56-68.
|Citing Patent
|Filing date
|Publication date
|Feb 9, 2004
|Apr 17, 2007
|Altera Corporation
|Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool
|Apr 30, 2001
|Sep 18, 2007
|Xilinx, Inc.
|Method and system for re-targeting integrated circuits
|Jun 24, 2003
|Oct 21, 2008
|National Semiconductor Corporation
|Method for creating, modifying, and simulating electrical circuits over the internet
|Sep 27, 2007
|Mar 16, 2010
|Lattice Semiconductor Corporation
|Weight based look up table collapsing for programmable logic devices
|Mar 17, 2005
|Dec 28, 2010
|Altera Corporation
|Power-driven timing analysis and placement for programmable logic
|Oct 11, 2007
|Dec 28, 2010
|International Business Machines Corporation
|Method and apparatus for incrementally computing criticality and yield gradient
|Nov 24, 2010
|Jan 17, 2012
|Altera Corporation
|Power-driven timing analysis and placement for programmable logic
|Aug 11, 2009
|Feb 7, 2012
|Altera Corporation
|Early timing estimation of timing statistical properties of placement
|Apr 10, 2007
|Apr 3, 2012
|Cadence Design Systems, Inc.
|System and method of computing pin criticalities under process variations for timing analysis and optimization
|Oct 29, 2007
|Apr 10, 2012
|Altera Corporation
|Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing
|Oct 9, 2007
|Feb 19, 2013
|Altera Corporation
|Using a timing exception to postpone retiming
|Jun 24, 2003
|Dec 30, 2004
|National Semiconductor Corporation
|Method for creating, modifying, and simulating electrical circuits over the internet
|Oct 11, 2007
|Apr 16, 2009
|Chandramouli Visweswariah
|Method and apparatus for incrementally computing criticality and yield gradient
|Aug 8, 2011
|Feb 14, 2013
|International Business Machines Corporation
|Critical path delay prediction
|U.S. Classification
|703/19, 716/124, 716/121, 716/134, 716/113
|International Classification
|Cooperative Classification
|European Classification
|Aug 20, 2001
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUTTON, MICHAEL D.;REEL/FRAME:012097/0119
Effective date: 20010810
|Apr 22, 2010
|Fee payment
Year of fee payment: 4
|Apr 24, 2014
|Fee payment
Year of fee payment: 8


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Listen to the Amazing Playlist From the Louis Vuitton Show
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The Louis Vuitton show was not just a feast for the eyes—the music was awesome as well. While the fashion crowd is not known to bust a move at such an inopportune time, we saw a lot of head-bobbing and toe-tapping going on. And how could you not? I mean, Beyoncé was playing.
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The New Louis Vuitton: Nicolas Ghesquière's Stellar First Collection
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subset: commoncrawl


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This is based on my personal opinion, I don't know if someone already came up with this theory and this is my first time doing something like this.
We all know that Gray will kill Frosch in the near future but let me elaborate the difference in the timeline of future Rouge and the present timeline. Future Rouge's timeline is different because in that timeline Ultear didn't grow old because of future Rouge's actions in the present timeline. In my guess, Ultear would do something significant like snap some sense to gray,and would probably say something related to I too was consume in darkness in the past blah, blah , blah, don't let yourself get dragged to darkness. You get the point.
Also, some plot holes. I just want to add these.
First, in Future Rouge's timeline why didn't they destroy the Eclipse Gate or destroyed when Achnologia became active sometime after frosch's death. Considering the fact that future Lucy told of what would happen if the gate would open.
Second, Future Rouge's appearance is a dead giveaway that Tartarus failed with their plan. When I first read the Tartarus arc I remembered F. Rouge, seven years from the future and can still use MAGIC.
I apoligize for any mistakes I made in this post.


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As a progressive relationship marketing company solely focused on the automotive aftermarket space, Xceleration Media understands the marketing needs of automotive companies small and large. Web, print, email, social, video – Xceleration Media provides one easy-to-coordinate program that includes it all and delivers your message directly to the most qualified customers.
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We help you find a Sheerness bass guitar tutor. Bass Guitar lessons are an excellent method to start a stimulating new hobby, acquire a new talent and attain confidence with bass guitar. Please use our service to find Sheerness bass guitar teachers and determine which best suits your requirements so you can begin your bass guitar tuition in Sheerness immediately!
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text: Due to the unanticipated plant downtime, and subject to timely completion of our new gas lines, we expect full-year 2012 production to be 2,800 MBoe – 3,000 MBoe.Third Quarter 2012 Commodity Prices Preliminary, average realized prices for third quarter 2012, before the effect of commodity derivatives, were $86.38 per Bbl of oil, $30.50 per Bbl of NGLs and $2.73 per Mcf of natural gas, compared to $81.51 per Bbl of oil, $52.08 per Bbl of NGLs and $3.99 per Mcf of natural gas for third quarter 2011. Our preliminary, average realized price, including the effect of commodity derivatives, was $44.78 per Boe for third quarter 2012, compared to $47.98 per Boe for third quarter 2011. Third Quarter 2012 Capital Expenditures Preliminary, unaudited estimates of capital expenditures during third quarter 2012 totaled $77.1 million, and included $60.3 million for drilling and completions, $11.7 million for pipeline and infrastructure projects, $4.4 million for acreage acquisitions and $0.7 million for 3-D seismic data acquisition. During third quarter 2012, the Company drilled 12 wells and completed 10 wells, including five of eight wells that were waiting on completion at June 30, 2012. At September 30, 2012, we had eight wells waiting on completion. Conference Call Scheduled for November 6, 2012 Approach will host a conference call on Tuesday, November 6, 2012, at 10:00 a.m. Central Time (11:00 a.m. Eastern Time) to discuss third quarter 2012 financial and operating results. The Company plans to issue third quarter 2012 results after market close on Monday, November 5, 2012. To participate in the conference call, domestic participants should dial (800) 901-5217 and international participants should dial (617) 786-2964 approximately 15 minutes before the scheduled conference time. To access the simultaneous webcast of the conference call, please visit the Calendar of Events page under the Investor Relations section of the Company's website, www.approachresources.com, 15 minutes before the scheduled conference time to register for the webcast and install any necessary software. The webcast will be archived for replay on the Company's website until February 4, 2013. In addition, the Company will host a telephone replay of the call, which will be available for one week. U.S. callers may access the telephone replay by dialing (888) 286-8010 and international callers may dial (617) 801-6888. The passcode is 64514392.


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Visit Us
Welcome to Tempe
In the heart of Sun Devil territory, we look to make cleaner skies. We provide air quality and environmental services to a wide range of clients including the mining industry; power plants; lime and cement production; oil, gas and pipeline industries; food production and all levels of government from state to county, municipal and native tribes.
With three mobile emissions testing labs, our team has the technology and mobility to get the job done right and done quickly. In Norfolk, New England we conducted a complicated air standards project that included quantifying actual emissions in 1975, 1988, 2010, as well as predicting future potential emissions.
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Racine just can't catch a break.
SC Johnson announced this afternoon that instead of cutting 100 to 200 as they said they would do last October, they will be cutting more like 300, up to 400 jobs.
Having tried mightily to get Beloit to at least share the title of top unemployment in the state for part of the time - it seems the title may stick with Racine for the foreseeable future. (With no additional hope for a casino approval either.)
As we reported back in October - SCJ has maintained record profits for the last 5 years, their business is NOT suffering and the family members themselves are worth billions. In a statement SCJ said:
"It's not about cost cutting," she said. "This is about organizational redesign and growth for the long term."More like long term wealth for the Johnson's.


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Most Helpful Guy
haha SOOOO different.
I was shy, awkward, skinny, a total pussy lol. Then I decided to just grow balls and transform.41|30|0
pretty nerdy too. thanks God i got into business school barely.
- Show AllShow Less
@Kingfrosty what?
Nothing ^^
Most Helpful Girl
I was shy, focused on doing well in classes, not popular, but not completely alone either. I had a good group of friends and could talk to pretty much anyone.32|10|0
Thanks for MHO. :)


text:
Yo Mama's Big Fat Booty Band – Bostons Red White and Blues Festival 2012
Anyone who knows me knows I love the funk. This band is all about funky. They bring it hardcore and dirty, full throttle in your face badonkadonk funk. Translation: they kick serious ass. I bought 2 cd's and I've been playing the hell out of them, can't wait for another opportunity to see them live. […]
Roll the Stones – Live at Pineapple Groove in Delray, FL
Live music photos of "Roll the Stones" in Delray, FL.


text:
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Below is our collection of tidbits, odds 'n ends for Williams Ferry.
This page contains two sections:
We spend a lot of time looking through Gazetteers & Almanacs that were published in the late 1800's and early 1900's. Many of the Gazetteers include the distance from a community such as Williams Ferry to various places of note, such as the White House.
With a nod to our favorite Gazetteers, the straight-line distance<1> beginning in Williams Ferry to:
We have found 2 communities that share the name Williams Ferry.
While the name Williams Ferry is unique within Alabama, we know of another 2 communities with the same name in the United States.
Communities Outside of Alabama
Attala County
Our profile page for Williams Ferry, Attala County [Map]Distance: About 166 miles [267.2 km] to the West Southwest
Loudon County
Our profile page for Williams Ferry, Loudon County [Map]Distance: About 223 miles [358.9 km] to the Northeast
Find a Community located in Alabama
About Jefferson County
About Alabama
Unfortunately, we don't know of a website for Williams Ferry. If you can help, please contact us through our Feedback Page.
The official website for Jefferson County: www.jeffcointouch.com/
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text:
Latest News
digiKam 5.6.0 is released// digiKam Team
Following the 5th release 5.5.0 published in March 2017, the digiKam team is proud to announce the new release 5.6.0 of digiKam Software Collection. With this version the HTML gallery and the video slideshow tools are back, database shrinking (e.g. purging stale thumbnails) is also supported on MySQL, grouping items feature has been improved, the support for custom sidecars type-mime have been added, the geolocation bookmarks introduce fixes to be fully functional with bundles, the support for custom sidecars, and of course a lots of bug has been fixed.
Call to Test the Pre-Release of 5.6.0// Simon Frei
Once again a lot has been going on behind the scenes since the last release. The HTML gallery tool is back, database shrinking (e.g. purging stale thumbnails) is also supported on MySQL, grouping has been improved and additional sidecars can now be specified. Therefore the release of 5.6.0 will be (is already) delayed, as we would like to invite you to test all these features. As usual they are available in the pre-release bundles or obviously directly from the git repository.


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North Carolina Gov. Roy Cooper's visit to UNC Charlotte on Wednesday, April 19, provided a hands-on opportunity for the state's chief executive to experience the power of Big Data.
University leaders discussed how UNC Charlotte's Data Science Initiative is a collaborative, multidisciplinary effort with transformational implications for the economic growth of the greater Charlotte region and the entire state. With data sets increasing in size, scope and number, there is almost unlimited potential, especially when it comes to industry applications.
To see the entiire article and view the video Click Here


text:
YSL Corail Intuitive (15) Rouge Volupte Shine
YSL Corail Intuitive (15) Rouge Volupte Shine
YSL Corail Intuitive (15) Rouge Volupte Shine ($35.00 for 0.15 oz.) is described as a "smoky soft coral." It's a light-medium, pink-coral with warm undertones and a glossy shine. YSL Peach Passion (13) (P, $34.00) is warmer, brighter. MAC Reel Sexy (LE, $16.00) is very similar but less glossy. MAC Ever Hip (LE, $16.00) is slightly darker. MAC Coral Bliss (LE, $16.00) is less glossy, more muted. YSL Tender Peach (26) (P, $34.00) is lighter, warmer. See comparison swatches.
The Rouge Volupte Shine formula is supposed to "leave lips visibly softer and smoother with up to eight hours of hydration." It also has "dazzling color, extreme comfort, and luminous shine." It has a high-shine, glossy finish with a lighter look and feel compared to the original Rouge Volupte range, which looks very creamy but is a thicker, heavier formula overall. The consistency is still very slick and emollient, so it glides on easily and doesn't drag at all, but it can sometimes look a little uneven. It had mostly opaque color coverage, but you can see a hint of my lip freckle coming through. The color lasts for three hours on me, and it is moderately hydrating over time, though I can't say it stretches as far as eight hours. It's more hydrating than the average lipstick, less hydrating than a good lip balm.


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You will be required to comply with the Clinical Practice Protocols if you provide non-emergency patient transport services. This involves transporting patients who require clinical monitoring for the duration of the journey:
The Clinical Practice Protocols describe medically approved protocols for the provision of non-emergency patient transport. It provides a consistent framework for officer knowledge, education and training.
You must also ensure that all your staff are provided with annual training in these Protocols.
Please consult the responsible agency for more information and to ascertain the level of compliance (if any) that may be required.
A code of practice can be either a legal requirement or non-legal requirement. Legal codes of practice are defined as a result of legislation. Non-legal codes of practice are defined by industry regulators and bodies.
Department of Health and Human ServicesPrivate Hospitals Branch
Non-Emergency Patient Transport Act 2003 (Victoria)
Non-Emergency Patient Transport Regulations 2016 (Victoria)
NEPT Legislation and Clinical Practice Protocols
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3D Printing Mini Project
This 3D printed project is meant as a sort of jewelry organizer that can store various types of rings, earrings, bracelets, necklaces, etc. I wanted something that could serve a useful purpose at home while also being of a creative shape.
At first, I wasn't aware of a lot of tools in Tinkercad, so I had difficulty placing objects on the other objects. But others knew the solution, so I eventually learned that I had to switch where the workplane was.
I enjoyed tinkering away in a 3-dimensional setting. It made me more acutely aware of different regions of space and how to work in that kind of program. It's also nice to see a design translate into a tangible object.
Because I mainly focused on the functions of this tool, I didn't really make it as aesthetically pleasing. Next time, I'll flesh it out and create a more intricate design.


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|Turtle Cannon Competition
| Season 1, Episode 6
|Production Code:
|March 3, 2010
|Pongo Kuo, Trevor Wall, and John Fountain
| Written &
Storyboarded by:
|Kent Redeker
Parrot Castle
Pandaffe Castle
Turtle Cannon Competition is episode six of season one of Hero: 108.
First and Second Squads compete for the Golden cup of the Turtle and the title of "First Squad."
First squad is called to deploy by Mr.NoHands. Second squad is called to deploy by Alpha Girl. They both slide down the pipes and each fall on Turtles 2 at a time. They immediately conflict and battle with their counterparts, until Commander ApeTrully calls them to stop. He decides to settle this with a Turtle Cannon Competition, and whoever wins will win the Golden Turtle Cup and will be known as first squad.
Down at the stadium, they are told that to win this round,they have to be the fastest to cross the finish line. They all race and each time someone from each squad wins. Apetrully gets very confused due to all the winnings. In the next round, Woo the Wise says that to win this round, they have to be the slowest and cross the finish line in more than a minute. Mighty Ray remarks that it will be easy, but then they see the track they have to race alone, and it is covered in ice. Each time they try to go along it, they slide and end up finishing first. Kowloon even smugly asks Lin Chung if he is scared, but then when Kowloon tries to go down the track, he slides and ends up finishing first. They try different methods, like Archer Lee goes backwards, and Mighty Ray goes sideways,but they don't work. Woo tells them to work together. Second squad interpret this wrong and pile all on one turtle , which doesn't work. Then Lin Chung says to the others that they can go slower by putting wind beneath their wings, before farting. Mystique Sonia asks him what he is on about, and Lin Chung says he has a plan.
They put 2 turtles on top of each other, the bottom one upside down, so the tracks are facing each other. Sonia pushing Mighty Ray through, which squished him into a kite . Sonia, Mr NoHands, and Lin Chung all do likewise. Lin Chung then says to Jumpy Ghostface it's up to him now. Jumpy ties them with strings and jumps on the turtle. They still whizz along too fast, even when they all connect together as a big kite. Jumpy then has an idea, he ties the strings to the turtles tail,and ties a string around himself and jumps under the turtles tracks, squashing himself into a kite too. This slows the turtle down and they cross the finishing line at the last minute, winning the game. They are all happy they've won, and then Mighty Ray kite flies off, shouting help.
At the awards ceremony, Jumpy asks Lin Chung if he did good, and Lin Chung responds by hugging Jumpy and rubbing him in the head, saying "very good Jumpy, very good" Mighty Ray is getting pulled out of his kite form by Alpha Girl and Golden Eye Husky. He then shoves them aside and grabs the turtle cup. Apetrully says that they deserve to be called first squad. Second squad then says they will win next time and they all fight amongst each other again. The Cup goes flying and bonks Apetrully on the head, knocking him unconscious.
- Lin Chung farts after he says his idea of putting wind beneath their wings.
- This was the first turtle cannon competition that they held, and the first time that Jumpy and Lin Chung hugged.
- Mr. No Hands initiated the fight by hitting Alpha Girl's hand. When Golden Eye Husky was about to breathe Mr. No Hands with fire, Jumpy Ghostface then protected him by his skipping rope, thus contradicting Husky. Mighty Ray then threw Husky to the wall and attempted to eat a banana, but it was shot by Archer Lee through his arrows. The arrows then were caught up by Yaksha and Mystique Sonia attacks Archer Lee. Alpha Girl was about to attack her as well, but was then stopped by Jumpy. Alpha Girl beckons Jumpy and Sonia, but the two were harassed by Hurricane Lee's Spiked Buns. The spiked buns were shot by Lin Chung's bamboo shoots, but Kowloon suddenly assailed him, and the two attempted to fight each other. Until Commander Apetrully comes from the ceiling. This scene has somehow shown individual rivalries between each members of First and Second Squads: Mr. No Hands to Alpha Girl, Jumpy Ghostface to Golden Eye Husky, Mighty Ray to Archer Lee, Mystique Sonia to Hurricane Lee, and Lin Chung to Kowloon.
- First appearance of Second Squad.


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text:
Report summaryThe property was mined until by Magma Copper who ceased production in 1999. Quadra purchased the property in 2004 and production restarted for an estimated capital cost of US$60M. In 2010 Quadra merged with FNX Mining to become Quadra FNX Mining Ltd. In February 2012, KGHM acquired Quadra FNX. Dewatering of the Ruth Pit.In 2010, mining commenced from the Ruth Pit which intersects the water table. Dewatering will be required to allow mining through to 2018; as activities move deeper into the...
What's included?
This report includes 2 file(s)
- Robinson (Ely) copper mine PDF - 718.70 KB 8 Pages, 1 Tables, 1 Figures
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Float Chair, Brown Mohair Fabric, Walnut Wood & Clear Acrylic
$600.00 $720.00
Product Details
A stylish twist on a traditional lounge, the LumiSource Float Chair is a gorgeous choice for adding a dash of modern style to your home. This original design was constructed for enduring strength and body-hugging comfort. The sleek and unique shape of this piece will to be sure to turn heads wherever it sits. Constructed with flawless acrylic the LumiSource Float Chair is upholstered with a chic, faux fur fabric and accented with a striking wood veneer. Available in brown and white, the sleek and distinct shape of this piece will be sure to turn heads wherever it sits.
- Contemporary style
- Mohair fabric upholstery
- Cushioned seat and backrest
- Winglike acrylic armrests
- Walnut wood finish
- Color: Walnut, Brown
- Material: Acrylic, Fabric, Foam, Wood
- Dimensions: 32" W x 35.75" D x 30" H
- Weight: 61.5 lbs
- Seat Dimensions: 24" W x 19" D
- Seat to Floor: 16.5"
- Seat Back Angle: 107 degrees
- Armrest Dimensions: 15" L x 6.5" H
- Capacity: 250 lbs
- Intended Use: Indoor Use Only
- Room Use: Living Room, Bedroom, Office


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The premise is pretty much the same as the first two. If you receive a call from yourself in the future, it's a very bad thing. The difference with this one is that, well, it's not nearly as good. It starts off ok. It has a decent creepy level. Then, the unthinkable happens - it gets cheesy. Seriously, this movie got about as cheesy as drippy nachos.
I really wanted to like it much better than I did. Unfortunately, it got to the point that if I weren't reading subtitles, I would have sworn I was watching a not-so-great American remake of a Japanese horror movie. The first movie is really good. The second, not as much, but not bad. The third is definitely skip-worthy. I give it 4/10 kupos.


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Ernst Golder, 13 July 1921, Vienna, Austria, d. 17 March 1999, Santa Monica, California, USA. A composer, conductor and arranger for movies from the 40s through to the 80s, Gold was a child prodigy and wrote a full-length opera when he was only 13. After studying at the State Academy of Music in Vienna, he fled with his family to the USA in 1938 when the Nazis gained control of Austria. A year later his first symphony was performed by the NBC Orchestra. After writing a few popular songs such as Practice Makes Perfect (with Don Roberts), which became popular on record for both Bob Chester and Al Lavelin in 1940, Gold moved to Hollywood in 1945, where he worked with George Antheil and began writing scores for a series of small budget films. These included The Girl Of The Limberlost (1945), Smooth As Silk (1946), The Falcons Alibi (1946), G.I. War Brides (1947), Lighthouse (1947), Wyoming (1947), Exposed (1947), Old Los Angeles (1948), Unknown...
- MatchErnest Gold
- 100%Alfred Newman
- 90%Franz Waxman
- 88%Victor Young
- 71%John Scott
- 32%David Raksin
- 32%Jay Chattaway


text: The future of the crossing will be a central issue in indirect, Egyptian-brokered negotiations between Israel and Hamas. Under the cease-fire, Israel made a vague commitment to ease its closing of Gaza. But the details must be negotiated.With Hamas rejecting Israel's key demand â¿¿ that arms smuggling into Gaza be halted â¿¿ it remains far from certain whether Hamas will get what it wants. Egypt also has not been clear how far it is willing to open its border, fearing that this will allow Israel to "dump" Gaza on Egypt and undermine hopes for reconciliation between Hamas and Abbas' rival government in the West Bank. Ayman el-Kholi, whose two-story home was destroyed in an Israeli airstrike aimed at militants, said Hamas government representatives and fighters, including Hamas strongman Mahmoud Zahar, visited him and promised compensation. "They promised that after things calm down, they will begin to reconstruct all homes destroyed and not just ours," he said. In the meantime, the 41-year-old banker has sent his six children to sleep at various relatives' homes, and he is staying with a friend. The rubble from the destroyed building was still in a heap on Sunday as he waited for the only government tractor to come remove it. The entire block was damaged by airstrike. Shops were buried and a nearby workshop for electrical appliances was severely damaged. "We don't save in banks. All my money was in the house. All of it is now under the rubble, around $10,000 plus my wife's gold," el-Kholi said. "We are waiting for an opening of the crossing. We are waiting for donor countries, from Arab countries, to help us rebuild the house again."


text: Photos (1) Map and Directions Street View Commute Time Walk Score Driving Walking Transit Get Directions Close No driving directions were found. Please adjust your search. To: 11 Flora Drive, Torbay From: Via: Directions turn left on street 4 minutes 2.5 miles Driving Directions - View this Property Today 11 Flora Drive - 3/4 acre lot in beautiful Scenic View Ridge subdivision in Torbay just off Indian Meal Line, minutes away from Stavanger Drive and all amenities. Turnkey packages available through JWR New Home Construction & Renovations. Property Details ID: 1150281 Storeys: 0 Style: Other New Construction: No Status: Active County: Canada Features Other Fireplace Present - False Sewer Septic Tank Transaction Type For sale Listed By Coldwell Banker ProCo


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Mars Bar Cake
Recipe by Grandmas a good coo
This recipe came from the Toronto Star Life Page on July 17th 2006.
Top Review by joynewman007
This is such a yummy caramel cake!!! The cake is not sweet at all which is a perfect balance to the icing. Many thanks for a tried and true, wonderfully-scrumptious mars mar cake recipe! Just a note, if you dont have buttermilk just take a cup of milk (i use light blue) and add 1 tablespoon of vinegar. I do this all the time and its just perfect. Edit, just thought I's share some tips on the method I use with this cake. I dont use tube pan with the removable base, I just use a normal cake tin with a large piece of baking paper (that covers the entire baking dish, and I just leave about a extra cm over the rim - not enough to burn down the house :) Then all you need to do is let the cake sit in the tin after being cooked for 10 - 15 minutes then lift the whole cake out, by the paper. Also, in the method, it says to cream the butter and sugar - no sugar in the recipe. I use about 1/4 to 1/3 of a cup, I must stress that the cake will not be sweet at all, but it is in a perfect balance with the icing (well perfect for us anyway) The topping of the thinly sliced mars bar...it looks lovely but much better to eat (in my opinion) without - not to mention that its a bit of a pain trying to get 'thin slices' of mars bars without it squashing up on you
See Discussion:3 Reviews
Ingredients Nutrition
- 3 (58 g) Mars bars, coarsely chopped
- 1⁄4 cup unsalted butter
- 2 cups all-purpose flour
- 1⁄2 teaspoon baking powder
- 1⁄2 teaspoon baking soda
- 3 large eggs
- 1 teaspoon vanilla extract
- 1 cup buttermilk
- 2 (58 g) Mars bars, coarsely chopped
- 1⁄2 cup unsalted butter
- 1 1⁄2 cups icing sugar
- 1 teaspoon vanilla extract
- 1 tablespoon milk
- 1 (58 g) Mars bars, thinly sliced
Directions See How It's Made
- For cake.
- Grease and flour 10-inch tube pan with removable bottom.
- In small pan on low heat, melt bars stirring frequently until blended.Set aside.
- In medium bowl,sift together flour, baking powder and baking soda.
- In large bowl, use electric hand mixer on medium low speed, then medium speed ,to beat together sugar and shortening until fluffy, about 5 minutes.Beat in eggs 1 at a time thoroughly incorporating each one. Beat in vanilla and Mars bar mixture until blended.Beat in a third of flour mixture.
- Beat in half of the buttermilk.Beat in the remaining flour mixture. Beat in the remaining buttermilk.
- Pour batter into prepared pan ,bake in preheated 325 oven 55 minutes or until tester comes out clean. Cool on wire rack 15 minutes.Turn out of pan on to serving plate.Cool completely.
- For icing, melt bars and butter on low heat, stirring frequently until blended.Remove from heat. Cool 5 minutes. Add icing sugar, milk and vanilla. Whisk vigorously until smooth. Spoon over cake,allowing it to drip down sides.
- For topping arrange Mars slices decoratively on top of cake.


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CSU BAKERSFIELD (15-7) vs. NM State (22-2)
|Points Per Game
|Field Goal Pct.
|3-point FG Pct.
|Free throw Pct.
|Rebounds Per Game
|Assists Per Game
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BAKERSFIELD. Calif.- In a rematch of last season's Western Athletic Conference Tournament Championship game, the CSUB Roadrunners (15-7, 6-1 WAC) and NM State (22-2, 8-0 WAC) will meet Thursday night at the Icardo Center at 7 P.M. with first-place on the line in the WAC.
The Roadrunners won that game last season in Las Vegas 57-54 but the Aggies won the first meeting in Las Cruces, N.M. this season 63-58. The Roadrunners led for much of that game before the Aggies managed a key three-pointer and several free-throws down the stretch to earn the win. The Roadrunners are coming off a 6-1 start to conference play and have won four-straight games after Saturday night's 65-62 win at Grand Canyon.
The Aggies, at 8-0 in WAC play hold a 1.5 game lead over CSUB for first place, a Roadrunners win would create a virtual-tie for the top spot with six conference games to play. NM State is in the midst of a 20-game winning streak, the second-longest active streak in the nation behind top-ranked Gonzaga (24).
CSUB is led by senior Jaylin Airington who is leading four Roadrunners in double figures with his 15 ppg. Damiyne Durham adds 14 ppg while Dedrick Basile is averaging 13 points per contest as well. Senior forward Matt Smith is chipping in 11 ppg this season but has averaged 15 ppg over the first six WAC games including a career-high 23 at Chicago State two weeks ago. Smith is also shooting a team-high 59% from the field.
NM State is led by senior guard Ian Baker's 16 ppg. Baker led NM State with 13 points in the first matchup on Jan. 14. Baker was just 2-6 from the field but 8-9 from the free-throw line. Braxton Huggins adds 14 per contest while Eli Chuha chips in 12 per contest for the Aggies.
Both teams rank near the top of the WAC in a variety of categories. NM State leads the WAC in scoring margin (13.4), field goal percentage (47.3), three-point field goal percentage defense (28.7), rebounding (39.8), rebounding defense (32.5), rebounding margin (7.2) and blocks (4.08). CSUB is tops in scoring defense allowing opponents just 64.1 ppg., field goal percentage defense (38.9), steals (8.23) and offensive rebounds (13.27). The Roadrunners rank 33rd in the NCAA with their 64.1 ppg allowed while the 17 turnovers forced per game is 10th-most in the nation.
Thursday's game will be broadcast live on ESPN 3 as part of the WAC Digital Network's 'Game of the Week' coverage. It will also be carried on Newstalk 1180/96.1 FM KERN. The 'Dignity Health Pregame Show' begins at 6:30 P.M., tipoff is scheduled for 7 P.M. at the Icardo Center.


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like a (hot) knife through butter
Definition of like a (hot) knife through butter
: very quickly and easily The bill passed through the senate like a hot knife through butter.
Word by Word Definitions
: having a relatively high temperature
: capable of giving a sensation of heat or of burning, searing, or scalding
: having heat in a degree exceeding normal body heat
: hotly
: fast, quickly
: a period of relatively high temperature : a period of heat
: one that is hot (such as a hot meal or a horse just after a workout)
: heat, warm
: a cutting instrument consisting of a sharp blade fastened to a handle
: a weapon or tool resembling a knife
: a sharp cutting blade or tool in a machine
: to use a knife on
: to stab, slash, or wound with a knife
: to cut, mark, or spread with a knife
: a solid emulsion of fat globules, air, and water made by churning milk or cream and used as food
: a buttery substance: such as
: any of various fatty oils remaining nearly solid at ordinary temperatures
: to spread with or as if with butter
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text:
Past platter: fish, fish and more fish.
Present preference: chicken, chicken and more chicken.
Calcuttas gastronomic graph is showing a tectonic shift with murgi-bhaat matching machh-bhaat, munch for munch.
Figures released by the poultry trade on Friday revealed Calcutta and its suburbs consuming 1.5 million birds a week, up from 0.7 million recorded a little over five years ago.
The day is not far off when we in Calcutta will cease to be known only as fish-eaters, said animal resources development minister Anisur Rahman. Chicken has already replaced fish in several households. In another 10 years, it will be the dominant factor, he added.
Powering the demand for chicken is a combination of factors: the reluctance of the new generation to experiment with fish and the hunt for an affordable alternative to fish that figures high on the price list and mutton that invariably tops the doctors not-to-eat list.
The present figures do not tell you the real story about how young children from fish-eating families are taking to chicken in a big way, says P.K. Roy, managing director of Arambagh Hatcheries Limited.
With 140 outlets and an investment of over Rs 100 crore, Arambagh boasts a big bite of the chicken market.
And the projections explain why private players have decided not to chicken out. Rahmans department is convinced that chicken consumption in Calcutta will touch 3.5 million a week in five years time.
We are here because of the high growth factor. No other market offers 15 per cent growth potential, said Lakshmi Kumar, business development officer of Coimbatore-based Suguna Poultry Farm, currently in talks with the animal resources department for hatchery land.
Tracking the trend, hatcheries and suppliers of eggs and chicken from Karnataka, Andhra Pradesh, Tamil Nadu and Maharashtra are targeting the Calcutta market.
According to a poultry trade survey, the per capita chicken consumption in Calcutta is about 1.5 kg, as against the all-India average of 1 kg.
Compared to Calcutta, other metros like Mumbai records 1.6 kg, Chennai 1.4 kg and Delhi 1.2 kg.
The spiralling prices of various varieties of fish has led to an overwhelming growth in demand for chicken, said Tapas Bandopadhyay, general secretary of West Bengal Poultry Welfare Association.
As far as cost-to-consumer goes, a dressed chicken from an Arambagh outlet moves on a price band of Rs 50-Rs 55 a kg, while a live bird sold by vendors in city markets ranges between Rs 45 and Rs 50 a kg. Varieties of fish like topshe, pabda, bhekti and parshe cost between Rs 140 and Rs 180 a kg.
Chicken is not eating into the fish market because of the price factor only; the white meat is also perceived to be more healthy, said Suman Madan, deputy general manager of Hyderabad-based Venkateswar Hatcheries.


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We help you find a Melton Constable bassoon tutor. Bassoon tuition are a brilliant method to learn a fun new hobby, pick up a new skill and attain confidence in bassoon. Try our service to find Melton Constable bassoon tutors and determine which best suits your needs so you can begin your bassoon tuition in Melton Constable today!
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Color Choices
Posts - 31 ProShield Choices
Clamps - 31 ProShield Choices
Components - 31 ProShield Choices
Polyethylene - 11 Choices
Permalene - 14 Choices
TenderTuff - 2 Choices
Color is an important decision, and our playgrounds are available in many color options. Use our carefully curated palettes like Color Palette AV shown above, or work with our design team to create your own color combination. Contact your local playground consultant to learn more.See more color palettes
Product Lines
Project Price Range
Age Ranges
- 5 to 12 Years
Design Standards
The Anoka Parks Department and Park Board designed the newest rocket-themed PlayBooster® playstructure in Anoka, Minnesota. This multi-level rocket ship, complete with Permalene® rocket fins, is U.S.A.-all-the-way in both its color scheme and signage. Kids can try different climbers to get to each level, then select from several slides—some windy and some straight—to soar back down. Children ages 5 to 12 enjoy creative play at this imaginative playground along with a good workout.
Product Lines Featured in this Playground
Ages 5 to 12 Years
The PlayBooster® playground structure, the original post-and-clamp system, combines exciting ground-level components with climbing events and overhead activities for kids ages 5 to 12. The PlayBooster family includes the interconnected cables of Netplex®, the contemporary Vibe®, the nature-inspired Tree House and the double-decker PlayOdyssey® Tower.
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We can help you create playground designs unique to your community! Everything in our custom design process is driven by your goals and ideas. Together, we'll create a destination playground that's as individual as your imagination!
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Proud to partner with our playground consultant covering Minnesota! (Zips: all except 565 & 567) We're proud to be local to you with our Minnesota-made playgrounds!
Flagship Recreation
275 East 4th St
St Paul, MN 55101
Phone 763-550-7860


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Home > Product Categories > Pro-Audio > Studio Tools & Problem Solvers > Audio Hum & Noise Eliminators > LLS
Item #: LLS MFG #: LLS
List Price:$166.00Our Price:$83.00Quantity Pricing
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The LLS-8 allows you to use equipment with different line level requirement at their correct gain settings. This reduces noise and makes -10dBv equipment compatible with +4dBu equipment. It is bidirectional and works with balanced or unbalanced signals at either end. This is made simple with Ebtech's TRS SmartJacks¬, just plug and go. All passive design guarantees you the best possible performance. It is available in a 2 channel mini box as the LLS and as an 8 channel RU1 unit as the LLS-8. Give yourself more signal and extra gain with correct line level matching!
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(1 of 1 customers found this review helpful)
Solved my problem
By kolekatkrush
from Oakland, CA
About Me Experienced
Best Uses
Comments about Ebtech LLS-2 2-Channel Line Level Shifter with 1/4in Smart Jacks:
I needed to convert a long balanced mic line to unbalanced phono to match the input of a wireless hearing-assist system. This product did only what I needed it to do (and not a lot of other unwanted functions which would bump up the price); it was compact, and the price fit my budget. It was recently installed, so I don't know about longevity. Audio quality was fine for my purposes; I didn't put it under the microscope, because it's not in a critical recording path.
Bottom Line Yes, I would recommend this to a friend
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text: EnvironmentAustralia's south expects floods Towns in the state of Victoria ready themselves for flood waters heading their way. 24 Jan 2011 15:31 GMT | Environment, Humanitarian crises, Asia Pacific, Australia " /> Towns in Victoria in southern Australia are preparing for the worst as flood waters head their way. Meanwhile in Queensland, where around 30 people died in the recent floods, things are slowly returning to normal. Azhar Sukri reports.Source: Al Jazeera


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Get an overview of this hotel3-star Winnipeg hotel in St. James with free parking
Popular property highlights
Located in St. James, this hotel is within 2 mi (3 km) of Living Prairie Museum, Canadian Forces Base Winnipeg, and Pavilion Gallery Museum. Assiniboine Park Zoo and Assiniboine Park are also within 2 mi (3 km).
Hotel Features
A restaurant, an indoor pool, and a fitness center are available at this hotel. Free WiFi in public areas, free self parking, and a free airport shuttle are also provided. Additionally, a bar/lounge, a spa tub, and a 24-hour business center are onsite.
Room Amenities
All 226 rooms provide free WiFi and free wired Internet, flat-screen TVs with satellite channels, and conveniences like refrigerators and microwaves. Other amenities available to guests include room service, coffee makers, and pillow menus.Information missing or incorrect? Tell us!Opens in a new window
Holiday Inn Winnipeg-Airport West
Hotel Amenities
Hotel Amenities
In addition to an indoor pool, Holiday Inn Winnipeg-Airport West provides a spa tub and a fitness center. The hotel offers a restaurant. A bar/lounge is on site where guests can unwind with a drink. A computer station is located on site and wired and wireless Internet access is complimentary.
This 3-star property offers access to a 24-hour business center. 14 meeting rooms are available. This business-friendly hotel also offers an arcade/game room, multilingual staff, and gift shops/newsstands. A roundtrip airport shuttle is complimentary to guests (available 24 hours). Complimentary self parking is available on site.
- 24-hour front desk
- Free airport transportation
- Arcade/game room
- ATM/banking
- Number of floors - 14
- Bar/lounge
- Breakfast available (surcharge)
- Free newspapers in lobby
- Conference space
- Dry cleaning/laundry service
- Elevator/lift
- Fitness facilities
- Gift shops or newsstand
- Free WiFi
- Free wired Internet
- Computer station
- Laundry facilities
- Multilingual staff
- Total number of rooms - 226
- Porter/bellhop
- Luggage storage
- Restaurant
- Safe-deposit box at front desk
- 24-hour business center
- Conference space size (feet) - 9012
- Long-term parking (surcharge)
- Free RV, bus, truck parking
- Number of meeting rooms - 14
- Conference center
- Free self parking
- Number of buildings/towers - 1
- Spa tub
- Indoor pool
Family Friendly Amenities
- Family Hotel
- Indoor pool
- Free Wi-Fi
- Laundry facilities
- Arcade/game room
- Refrigerator
- Microwave
- Cribs/infant beds (complimentary)
Available in all rooms: Free WiFi , Free wired Internet
Available in some public areas: Free WiFi , Free wired Internet
Long-term parking (surcharge), Free self parking, Free RV, bus, truck parking
Room Amenities
- Air conditioning
- Phone
- Microwave
- Satellite TV service
- Coffee/tea maker
- Free newspaper
- Desk
- Free local calls
- Hair dryer
- Daily housekeeping
- Iron/ironing board
- Flat-panel TV
- Free WiFi
- Free wired Internet
- Pay movies
- Private bathroom
- Refrigerator
- Video-game console
- Room service (limited hours)
- Pillow menu
- Free cribs/infant beds
- Connecting/adjoining rooms available
- Rollaway/extra beds (surcharge)
Where to Eat
Belbottoms - This restaurant specializes in American cuisine and serves breakfast, lunch, and dinner.
SOS Lounge - This bar specializes in American cuisine and serves lunch and dinner.
Room service (during limited hours) is available.
Nearby Things to Do
An indoor pool and a spa tub are on site. Other recreational amenities include a fitness center.
- Golfing nearby
If you have requests for specific accessibility needs, please note them at check-out when you book your room.
- Accessible bathroom
- Roll-in shower
- In-room accessibility
Hotel Policies
Check-in time starts at 3 PM
Minimum check-in age is 19
Special check-in instructions:
Check-out time is noon
Payment types
Children and extra beds
- Children are welcome.
- Rollaway/extra beds are available.
- Free cribs (infant beds)!
- Pets not allowed
You need to know
Extra-person charges may apply and vary depending on property policy.
Optional extras
- Breakfast fee: between CAD 5 and CAD 15 per person (approximately)
- Rollaway beds are available for an additional fee
Hotel Name
- Holiday Inn Hotel Winnipeg-Airport West
- Holiday Inn Winnipeg-Airport West
- Holiday Inn Winnipeg - Airport West Hotel Winnipeg
- Holiday Inn Winnipeg - Airport West Manitoba
- Winnipeg Holiday Inn
- Holiday Inn Winnipeg-Airport West Hotel
We should mention
The property has connecting/adjoining rooms, which are subject to availability and can be requested by contacting the property using the number on the booking confirmation.