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The Opteron 6276: a closer lookby Johan De Gelas on 2/9/2012 6:00 AM EST
- Posted in
- CPUs
- IT Computing
- Bulldozer
- Opteron
- Cloud Computing
- Interlagos
46 Comments
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tech6 - Thursday, February 09, 2012 - linkWe have a number of these in our data center and they have been a disappointment. Single threaded performance is low and the memory sharing performance under VMWare is poor. That leaves it only competitive for DB and web servers work which is OK but it doesn't make a compelling case for the architecture as similar Intel offerings perform well in all tasks. AMD still has a small price advantage, but once you add the VMWare licensing and data center costs the percentage difference is negligible. Reply
duploxxx - Thursday, February 09, 2012 - linkTypical answers, I debate such results all the time with many IT departments all over the world so called "standardized on and runs bette on" statements. So you have a large number of these new Opteron 6200 series already in datacenter and already got this info out of it, yeah right. Our virtual datacenters with approx 1000 servers exist out of AMD based systems, the only time i thought about swapping to intel after performance/price/power review was when intel released the Nehalem (oh and perhaps the Socket R but can't disclose that yet, neither do I want to swap that fast knowing that abu dhabi is about to go in Beta samples already). In the low price 2s-4s (not talking about the over expensive EX versions) the AMD are still owning the virtualization with there multicore and more memory channels with lower price.
Poor single thread has indeed been an issue for magny cours to a certain extend but not that it is noticable on a normal level of applications (you sound like a superpi user that only looks at theoretical results), poor memory sharing, care that to explain :). I suggest you have a look at general best practices on power settings for virtualized environments before complaining about response and throughput.
These response time result measured here are not noticable in any general application and once adding some kernel overhead from NFS/iscsi or whatever in medium - high load servers forcing these tasks to HT cores will show quite a bit different result in platform performance. Anandtech Vapp results from are nice but are still not a full reflection of datacenter performance and the results are heavy influenced by the webapp which clearly seems to favor the Intel architecture. Neither does have the Vapp testing any iscsi/nfs kernel related tasks which many sites do have (to reduce infrastructure cost)
Vmware licensing cost more for AMD? only for the enterprise edition, the abandoned vmware license version which was introduced again for v4 because of OEM pressure... time to investigate more before buying anything... advanced - enterprise plus has no difference for any core you would select and neither does v5 have. Reply
JohanAnandtech - Thursday, February 09, 2012 - linkNFS/iSCSI: you seem to ignore the fact that besides OLTP, many apps (especially OLAP and web) run mostly out of memory. The whole idea of good data management is to make sure that your requests come out of memory. We have webcaches, database caches, file system caches, RAID caches and on disk caches...all these caches are made to make sure that the response time is NOT dominated by NFS/iSCSI.
We have 5 years of experience building our vAPUS stresstesting client (not vApp) so don't discard our results so quickly. Reply
duploxxx - Thursday, February 09, 2012 - linkI won't discard them as I said they are a of great value just like these testing posted today, but that doesn't change the fact that in current vApus stresstesting there is no use of NAS/ISCSI datastores which is very common these days now that 10G is affordable and creates additional overhead on systems, mostly not accounted for when selecting a platform. Sure for the review real performance conclusion are needed from cpu architectures and then this setup remains totally applicable. But you get people which i tried to answer before who take this final score result for granted and leverage it over a total platform as if that is the best choice.
Second remains the fact that the final vApus calculation is based on all scores and the web based VM score is unbalancing the final score. I mentioned that years ago when the vApus1 and 2 were introduced, back in the old days. Reply
haplo602 - Friday, February 10, 2012 - linknothing that features heavy modifications will run out of memory .... do you cache your database redologs ? bad idea.
similar for web servers that get heavy modifications.
all the caches exist to only make the transition between respons time jumps less painfull, but they never remove those limits.
if you have a static system (reads 99% of the time) then you can use caches a lot. untill the data set grows too large to cache and is sufficiently random. Reply
Iketh - Thursday, February 09, 2012 - linkThis was a fun read. Unfortunately, the thought still in the back of my mind while reading was why in the hell did AMD reinvent the P4??? I just don't get it.
I hope the coorporate players who resigned fired some engineers prior... Reply
duploxxx - Thursday, February 09, 2012 - linkvery interesting info as usual, thx for the indepth review.
In general I think it would be added value to mention what exact BIOS and power mngmnt settings have been set. Since the option exist of using PCC controlled power (BIOS - OEM) or through the OS, also settings like CE6 etc does influence the final results a lot on turbo etc, mainly towards your preliminary review and this one it's not always clear what exactly you have been using.
result wise it is very strange that the 16core does not scale further then the 12core in SQL, for the reference testing that would give clear results when you could have tested the 6234-6238 which are also 12core versions. It is hard to believe that these 16core do not scale further, that they lack about 10-15% IPC @ same ghz sure but not raw performance in core count.
Debatable is the fact that while using Dual rank 4MC on AMD and using 2 rows Dual rank 3MC on the intel, dual row dual rank will give more bandwidth, its not AMD fault they have 4MC vs intel only 3MC.... even Intel next gen will have a serie of 3MC and 4MC..... but this should not result in major differences.
Last point, which IS a fact --> the price compare. While listed price might be comparable, reallity is quite a bit different in retail sales price. For large volume handling the discount between vendor is huge, the discount that Intel allows on it's CPU is way less then AMD, this changes the final cost price a lot.
JohanAnandtech - Thursday, February 09, 2012 - link"In general I think it would be added value to mention what exact BIOS and power mngmnt settings have been set"
Most of them can be seen at:
C6 was enabled
"dual row dual rank will give more bandwidth"
You can easily reverse that argument: if I use 4 GB DIMMs on the AMD, the clockspeed of the DIMMs will throttle back to 1333. The AMD IMC can only use 1600 MHz with 1 DIMM per channel. So this is really the best case for AMD.
"For large volume handling the discount between vendor is huge"
ok. 1. those people are probably 0.001% of our readership. 2. Those prices are a moving and unknown target. Reply
duploxxx - Thursday, February 09, 2012 - linkyes I have seen those settings, but during the review with so many back and forth testing showing issues on the power and bios settings from a reader perspective it is no longer clear what exact bios settings have been used (ms os - hypervisor) and what has been used and if results were updated with the right BIOS settings.
I am not yet convinced that the 1600 is really added value for the 6200 series, perhaps it will be more added value on piledriver with enhancements. While 8GB ram prices did drop it is still not a default selection certainly not on 1600 speed. I did mention debatable memory :) did you test the difference in the Database benchmarks?
Its not only large volume where the discount is even greater, just look at the HP website and order 3 "similar" designs from the same vendor:
dl380 dual E5649 - 8gb ram : 5953$ (add 8gb ram + 150$ approx)
dl380 dual X5660 - 24gb ram: 7178$ (remove 8 gb ram -150$, identical PSU -100$)
dl385 dual 6272 - 16GB ram: 5202$
so you can see quite a bit different price range.
http://h71016.www7.hp.com/dstore/MiddleFrame.asp?p... Reply
alpha754293 - Thursday, February 09, 2012 - linkJohan:
I know that you and I have spoke a little bit offline about possibly doing more HPC and HPC-related testing.
I, for one, would still like to see more of that because I think that's one area that a) is underserved by hardware review sites (sometimes with good reason), b) I think that it stresses the CPUs more/harder, and c) you can create/do/use a consistent benchmark test cases or suite of applications (like you mentioned about the SPEC OpenMP (although they have an MPI one as well, which I think is probably going to be even better).
I think that the biggest downside is that the HPC applications DO take a fairly significant time to run. (Some of them runs for days on end - just to do one pass).
And you can always throw more Hypervisors onto these systems, but I don't think that they're nearly as taxing as when you're running a computationally heavy/demanding application like simulating a car crashing into a wall at 35 mph. :oD
And it's quite possible that you might be able to script the entire benchmarking process... Reply
Jaguar36 - Thursday, February 09, 2012 - linkI too would love to see more HPC related benchmarks. Finite Element Analysis (FEA) or Computational Fluid Dynamic (CFD) programs scale very well with increased core count, and are something that is highly CPU dependent. I've found it very difficult to find good performance information for CPUs under this load.
I'd be happy to help out developing some benchmark problems if need be. Reply
dcollins - Thursday, February 09, 2012 - linkThese would indeed be interesting benchmarks to see. These workloads are very floating point heavy so I imagine that the new Opterons will perform poorly. 16 modules won't matter when they only have 8 FPUs. Of course, I am speculating here.
Going forward, these types of workloads should be moving toward GPUs rather than CPUs, but I understand the burden of legacy software. Reply
silverblue - Friday, February 10, 2012 - linkThey have 8 FPUs capable of 16x 128-bit or 8x 256-bit instructions per clock. On that level, it shouldn't be at a disadvantage. Reply
bnolsen - Sunday, February 12, 2012 - linkGPUs are pretty poor for general purpose HPC. If someone wants to fork out tons of $$$ to hack their problem onto a gpu (or they get lucky and somehow their problem fits a gpu well) that's fine but not really smart considering how short release cycles are, etc.
I have access to a quad socket magny cours built mid last year. In december I put together a sandy-e 3930k portable demo system. Needless to say the 3930k had at least 10% more throughput on heavy processing tasks (enabling all intel sse dropped in another 15%). It also handily beat our dual xeon nehalem development system as well. With mixed IO and cpu heavy loads the advantage dropped but was still there.
I'd love to be able to test these new amds just to see but its been much easier telling customers to stick with intel, especially with this new amd cpu. Reply
MySchizoBuddy - Friday, March 09, 2012 - link"GPUs are pretty poor for general purpose HPC."
tell that to the #2, #4 and #5 most powerful supercomputers in the world. I'm sure no one told them. Reply
hooflung - Thursday, February 09, 2012 - linkI think I'd rather see some benchmarks based around Java EE6 and an appropriate container such as Jboss AS 7. I'd also like to see some Java 7 application benchmarks ( server oriented ).
I'd also like to see some custom Java benchmarks using Akka library so we can see some Software transactional memory benchmarks. Possibly a node.js benchmark as well to see if these new technologies can scale.
What I've seen here is that the enterprise circa 2006 has a love hate relationship with AMD. I'd also like to see some benchmarks of the Intel vs AMD vs SPARC T4 in both virtualized and non virtualized J2EE environments. But this article does have some really interesting data. Reply
jibberegg - Thursday, February 09, 2012 - linkThanks for the great and informative article! Minor typo for you...
"Using a PDU for accurate power measurements might same pretty insane"
should be
"Using a PDU for accurate power measurements might seem pretty insane" Reply
phoenix_rizzen - Thursday, February 09, 2012 - linkMySQL has to be the absolute worst possible choice for testing multi-core CPUs (as evidenced in this review). It just doesn't scale beyond 4-8 cores, depending on CPU choice and MySQL version.
A much better choice for "alternative SQL database" would be PostgreSQL. That at least scales to 32 cores (possibly more, but I've never seen a benchmark beyond 32). Not to mention it's a much better RDBMS than MySQL.
MySQL really is only a toy. The fact that many large websites run on top of MySQL doesn't change that fact. Reply
PixyMisa - Friday, February 10, 2012 - linkThis is a very good point. While it can be done, it's very fiddly to get MySQL to scale to many CPUs, much simpler to just shard the database and run multiple instances of MySQL. (And replication is single-threaded anyway, so if you manage to get one MySQL instance running with very high inserts/updates, you'll find replication can't keep up.)
Same goes for MongoDB and, of course, Redis, which is single-threaded.
We have ten large Opteron servers running CentOS 6, five 32-core and five 48-core, and all our applications are sharded and virtualised at a point where the individual nodes still have room to scale. Since our applications are too large to run un-sharded anyway, and the e7 Xeons cost an absolute fortune, the Opteron was the way to go.
The only back-end software we've found that scales smoothly to large numbers of CPUs is written in Erlang - RabbitMQ, CouchDB, and Riak. We love RabbitMQ and use it everywhere; unfortunately, while CouchDB and Riak scale very nicely, they start out pretty darn slow.
We actually ran a couple of 40-core e7 Xeon systems for a few months, and they had some pretty serious performance problems for certain workloads too - where the same workload worked fine on either a dual X5670 or a quad Opteron. Working out why things don't scale is often more work than just fixing them so that they do; sometimes the only practical thing to do is know what platform works for what workload, and use the right hardware for the task at hand.
Having said all that, the MySQL results are still disappointing. Reply
JohanAnandtech - Friday, February 10, 2012 - link"It just doesn't scale beyond 4-8 cores, depending on CPU choice and MySQL version."
You missed something: it does scale beyond 12 Xeon cores, and I estimate that scaling won't be bad until you go beyond 24 cores. I don't see why the current implementation of MySQL should be called a toy.
PostgreSQL: interesting several readers have told me this too. I hope it is true, because last time we test PostgreSQL was worse than the current MySQL. Reply
sonofgodfrey - Thursday, February 09, 2012 - linkHave you explicitly tested one socket vs. two sockets? We've found an immense increase in contention once a cache-line has to be shared between sockets on some systems. Reply
JohanAnandtech - Friday, February 10, 2012 - linkThat is one suggestion I will try out next week. Thanks! Reply
Klimax - Thursday, February 09, 2012 - linkHello.
Nice tests.
However I would like to see MySQL tested on Windows Server 2008 R2
Would be interesting comparsion.
(Especially due to http://channel9.msdn.com/shows/Going+Deep/Arun-Kis... ) Reply
Klimax - Thursday, February 09, 2012 - linkTitle of post is wrong... (I have deleted second thing and forgot to fix title) Reply
Scali - Thursday, February 09, 2012 - linkUnless I'm mistaken, the Xeon 5650 is a 1.17B transistor chip, where the Interlagos 6276 is a 2.4B transistor chip.
In that light, doesn't that make Intel's SMT implementation a lot better than CMT?
I mean, yes CMT may give more of a performance boost when you increase the threadcount. But considering the fact that AMD spends more than twice the number of transistors on the chip... well, that's pretty obvious.
AMD might as well just have used conventional cores.
The true strength of SMT is not so much that it improves performance in multithreaded scenarios, but that it does so at virtually no extra cost in terms of transistors (and with little or no impact on the single-threaded performance either). Reply
JohanAnandtech - Friday, February 10, 2012 - linkInterlagos is 1.2 billion chip (maybe 1.3 but anyway). Most of those transistors are spend on the L3 cache: about 0.5 billion. Only 213 million transistors are in a module and each module contains a 2 MB L2-cache, probably good for 120 million transistors. That leaves 90 million transistors to the core, and it has been stated that the second cluster added 12%. So that second cluster costs about 12 million transistors, or 48 million on the total 4 module die. That is less than 5% of the total transistor count but you get a 30-90% performance boost!
So for AMD, this was clearly a great choice.
SMT is perfect for Intel, as the Intel architecture puts all instructions in one big ROB.
For very low IPC serverworkloads, I think the CMT approach gives better results. Unfortunately AMD lowered some of the CMT benefits by keeping the datacache so small and the low associativity of the Icache. Reply
Scali - Friday, February 10, 2012 - linkUhhh, I think you're wrong here... the 4-module Bulldozer is a 1.2B chip (Zambezi). But you tested the 8-module Interlagos (16 threads), which is TWO Zambezi dies in one package.
Hence 2*1.2 = 2.4B transistors. Reply
JohanAnandtech - Friday, February 10, 2012 - linkOk, it is two chips of 1.2 billion. That doesn't change anything about our analyses of CMT. Reply
Scali - Friday, February 10, 2012 - linkNot in the article, because you did not factor in transistor count (which is the flaw I tried to point out in the first place... comparing two chips, where once is twice the transistor count of the other, is quite the apples-to-oranges comparison. One would expect a chip with twice the transistorcount to be considerably better in multithreading scenarios, not 'catching up' to the smaller chip).
But in your above post, I think it changes everything about your analysis. All your figures have to be done times two.
Which makes it a very poor comparison, not only to Intel, but also to AMD's own previous line of CPUs.
The 6174 Magny Cours is actually beating Interlagos, with 'only' 12 threads, no kind of CMT/SMT, and 'only' 1.8B transistors.
How does that make CMT look like a great choice for AMD? Reply
slycer.tech - Friday, February 10, 2012 - linkWhat i read on benchmark configuration page, Anand used 2x Intel Xeon X5650. So 2x 1.17B = 2.34B. I think it is comparable to AMD CPU used in this test. Am I right? Reply
Scali - Friday, February 10, 2012 - linkNo, because if you read the ENTIRE benchmark configuration page, you'd see that all the AMD systems had 2 CPUs as well. Reply
Scali - Saturday, February 11, 2012 - linkOh, and while we're at it... the Intel system had only 48 GB of 1333 memory, where the AMDs had 64 GB of 1600 memory.
(Yes, Bulldozer is THAT bad) Reply
PixyMisa - Saturday, February 11, 2012 - linkOr rather, MySQL scales that poorly.
What we can tell from this article is that if you want to run a single instance of MySQL as fast as possible and don't want to get involved with subtle performance tuning options, the Opteron 6276 is not the way to go.
For other workloads, the result can be very different. Reply
JohanAnandtech - Saturday, February 11, 2012 - linkFeel free to send me a suggestion on how to setup another workload. We know how to tune MySQL. So far none of these settings helped. The issue discussed (spinlocks) can not be easily solved. Reply
Scali - Saturday, February 11, 2012 - linkI'm not sure if you bothered to read the entire article, because MySQL was not the only database that was tested.
There were also various tests with MS SQL, and again, Interlagos failed to impress compared to both Magny Cours-based Opterons and the Xeon system. Reply
JohanAnandtech - Saturday, February 11, 2012 - linkThe clockspeed of the RAM has a small impact here. 64 vs 48 GB does not matter. Reply
Scali - Saturday, February 11, 2012 - linkNot saying it does... Just pointing out that the AMD system had more impressive specs on paper, yet failed to deliver the performance. Reply
JohanAnandtech - Saturday, February 11, 2012 - linkAgain, it is not CMT that makes AMD's transistor count explode but the combination of 2x L3 caches and 4x 2M L2-caches. You can argue that AMD made poor choices concerning caches, but again it is not CMT that made the transistor count grow.
I am not arguing that AMD's performance/billion transistors is great. Reply
Scali - Saturday, February 11, 2012 - linkI think you are looking at it from the wrong direction.
You are trying to compare SMT and CMT, but contrary to what AMD wants to make everyone believe, they are not very similar technologies.
You see, SMT enables two threads to run on one physical core, without adding any kind of execution units, cache or anything. It is little more than some extra logic so that the OoOE buffers can handle two thread contexts at the same time, rather than one.
So the thing with SMT is that it REDUCES the transistorcount required for running two threads. By nearly 100%.
CMT on the other hand does not reduce the transistorcount nearly as much. So if you are merely looking at an 'exposion of transistor count', you are missing the point of what SMT really does.
Other than that, your argument is still flawed. Even an 8-thread Bulldozer has a higher transistor count than the 12-thread Xeon here. It's not just cache. CMT just doesn't pack as many threads per transistor as SMT does... and to make matters worse, CMT also has a negative impact on single-threaded performance (which again, if you are looking at it from the wrong direction, may look like better scaling in threadcount... but effectively, both with low and high threadcounts, the Xeon is the better option... and this is just a midrange Xeon compared to a high-end Interlagos. The Xeon can scale to higher clockspeeds, improving both single-threaded and multithreaded performance for the same transistorcount).
So what your article says is basically this:
CMT, which is nearly the same as having full cores, especially in integer-only tasks such as databases, since you have two actual integer cores, has nearly the same scaling in threadcount as conventional multicore CPUs.
Which has a very high 'duh'-factor, since it pretty much *is* conventional multicore.
It does not reduce transistorcount, nor does it improve performance, so what's the point? Reply
JohanAnandtech - Friday, February 10, 2012 - linkSemantics :-). I can call it a core with CMT, or a module with 2 cores. Both are valid. Reply
Scali - Saturday, February 11, 2012 - link"It also reduces throughput."
No, it improves throughput, assuming we are talking from improvement going from 1 physical core to 2 logical cores.
Clearly two logical cores (on the same physical core) have less throughput than two physical cores, but that's obvious since you only have half the hardware.
And that, together with the fact that Intel's SMT chips have far better single-threaded performance to begin with, results in very good performance per die area (you know, that thing that people used to praise AMD GPUs for).
"Yes, it does, via the implementation of all that shared hardware on the chip."
You can't say that, since there is no non-modular version of Bulldozer (just as there is no non-HT version of the Intel architectures).
However, if you compare a 4-core HT architecture with a non-HT architecture, be that a Core2 Quad or a Phenom X4, Intel's transistorcount is clearly in the same ballpark, so HT does not add much in terms of transistorcount.
With CMT we see little or no indication of reduced transistorcount. AMD's 4-module chips are MUCH larger than regular 4-core chips have been. In fact, AMD"s 4-module design is even larger than Intel's 6-core design with HT.
"Two different approaches to the same idea."
I disagree. SMT is a very different idea from CMT (which is a bogus marketing term invented by AMD anyway). CMT is more of a marketing excuse for not having proper SMT, and shows no merit in actual silicon.
"but I don't think we can label one as inherently better than the other yet."
Well clearly we disagree on that then.
I think SMT is clearly inherently better than CMT. SMT has far more flexible sharing of resources than AMD's half-baked approach.
And any theoretical disadvantages (fighting over resources and all that) can be put to bed with benchmarking such as in this review: the disadvantages may exist, but the net performance is unbeatable anyway. A midrange Xeon schools a CMT-based chip of twice the size. Reply
Andexxx - Wednesday, February 15, 2012 - linkWell, there are a lot of factors affecting single-threaded performance in real life. So CMT indeed has its scaling advantages as tests suggested. At least most of the things should be constant when comparing CMT-on and CMT-off, while comparing SMT and CMT on different implementations is not. Lack of single-threaded performance is not a valid point of blaming CMT.
If you want to *proof* CMT is a half-baked marketing crap while SMT is the only solution, what you need is a SMT-based AMD BD monolithic core or a CMT-based Intel monolithic module for comparison.
For the transistors counting, well, that's their choice of making such a cache and uncore configuration. You can keep telling 4-module chip is blahblahblah, but in some cases it beats a 4C8T Xeon chips. Transistors is not a big matter from customer viewpoint but just the producer viewpoint. If you want to argue with GPU's performance metrics, GPU is a data-parallel processor with bunch of logic units, while CPU is a latency-sensitive girlfriend of caches. Large amount of cache can make your Performance/mm^2 or Performance/transistors look worse. So trade-offs on the amount of cache should have been done before they started to design the chip. Reply
Scali - Wednesday, February 15, 2012 - linkWell, one of the reasons why AMD's current CPUs have such poor single-threaded performance is because they moved from 3 ALUs per thread to 2 ALUs per thread.
This is part of the whole CMT design.
So in that sense, CMT can be blamed for the poor single-threaded performance at least.
And since single-threaded performance is so bad, it is only logical that scaling to more threads is relatively good.
On a CPU with faster single-threaded performance, you run into IO limits sooner (memory, disk etc), so it is more difficult to maintain similar scaling with increased thread count.
The strength of SMT is that Intel did not have to cut any ALUs when implementing HT. Pentium 4 Northwood with HT still had two double-pumped ALUs, like the non-HT Willamette that went before it.
Likewise, Core i7 still has 3 ALUs, like Core2.
Another strength of SMT is that even with one less ALU per 2 threads than CMT, it still reaches similar performance in multithreaded scenarios. CMT can not share these ALUs between threads, while SMT can.
Conclusion: CMT is nonsense.
For the full version, see: http://scalibq.wordpress.com/2012/02/14/the-myth-o... Reply
slycer.tech - Monday, February 13, 2012 - linkIf Bulldozer arc really bad, how about this?
Can someone prove this award is a big liar? Reply
duploxxx - Tuesday, February 14, 2012 - linkread the article, the baseline they use for price/performance is based on spec results....lots of companies still use these results to decide on a platform.
but then again, benchmarks don't always show the real world value or even hard to compare since many have in house applications that don't scale or scale different like the ones benchmarked in reviews. 90% of the datacenters don't even require more then any midrange cpu, anything above midrange is wasted money and both vendors provide more then adequate solutions to that. It's the human mind that is often blocking sanity. Investing that wasted money in other solutions often provide a better total performing solution. Reply
anti_shill - Monday, April 02, 2012 - linkshill_detector by anti_shill on Monday, April 02, 2012
Here's a more accurate reflection of Bulldozer/ interlagos performance, untainted by intel ad bucks...
But if u really want to see what the true story is, have a look at AMD's stock price lately, and their server wins. They absolutely smoke intel on virtualization, and anything that requires a lot of threads. It's not even close. Reply


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Quinoa Breakfast Bars!
We were treatless this week. Specifically, breakfast treatless. No Pear Polenta Muffins were hiding in the freezer. No Apple Cake with Cranberries. In fact, the only food items in the freezer were a solo bottle of organic vodka and a bag of frozen cranberries (does vodka count as food?). Which turned out to be a good thing. Because we had to bake. [Had to!] So we experimented (send smooches to Steve for initiating said experiment; if it were not for him, Dear Reader, you'd be looking at an archived recipe today).
As the breakfast treats were baking I started thinking (always dangerous). I started pondering (even more dangerous) why certain people believe they have things AFO. All Figured Out. And they'll tell you so, of course, spooning out advice in words that taste metallic. Like teeth fillings. They have all the neat little answers for you, judged and predigested, wrapped snug in tidy psychic ribbons.
If only life were that simple.
Don't get me wrong. I'm not yearning for simple.
I'm not six years old.
I can handle complicated. I can chew for hours on ideas that are tough and wiggly and mysterious, and arrive at no final conclusion whatsoever. I can sleep on it and wake up with nothing but songs and dreams in my head that will color the day with glimpses of what might be possible. I don't need to hammer the challenging and mysterious into a mold I can easily grasp so I can feel more comfortable in the world, believing it is fixed. So I can stop asking questions. So I can say, I have the answer.
I can handle complicated. I can chew for hours on ideas that are tough and wiggly and mysterious, and arrive at no final conclusion whatsoever. I can sleep on it and wake up with nothing but songs and dreams in my head that will color the day with glimpses of what might be possible. I don't need to hammer the challenging and mysterious into a mold I can easily grasp so I can feel more comfortable in the world, believing it is fixed. So I can stop asking questions. So I can say, I have the answer.
I am, in fact, okay hanging in the tension of opposites.
I don't need only good, only pretty, only nice, only light, only clean, only sweet, only happy. And isn't that a valuable thing? Because the last time I checked the world was a mash-up of good and bad, beautiful and ugly, gentle and cruel, luminous and dark and cool and filthy and calm and angry and laughable and profoundly, deeply sad. And often, really ironic.
So here's the thing.
The older I get, the more I learn, the less certain I am. Of anything. I don't have all the answers. I don't always know what is best or what is true. And what is right for me may not be right for you. And what may be right for me today may be wrong for me tomorrow.
But one thing I do know?
But one thing I do know?
There are places on this earth where you feel you belong. And places you will always feel like a stranger. An outsider. A tourist. There are places and people and days that grind you down. And harden you. And there are places and people and days that soften you. Soften your heart. And you know what?
I want that.
Quinoa Breakfast Bars Recipe
By Karina Allrich September 2009, modified for less sugar 2016.
Quinoa flakes give these breakfast treats a texture that is a cross between a blondie bar and a breakfast bar. We add mini dark chocolate chips to ours because we like the flavor combo of quinoa and chocolate. And if you like nuts, you could also add chopped pecans or walnuts for even more protein.
In a mixing bowl, whisk together:
1 cup sorghum flour
1/2 cup organic quinoa flour
1/2 cup potato starch or tapioca starch
1 cup Ancient Harvest Quinoa Flakes
1 teaspoon xanthan gum
3/4 teaspoon sea salt
1 teaspoon baking soda
1 1/2 teaspoons baking powder
1 teaspoon cinnamon
1 cup organic light brown sugar
In a large measuring cup blend:
1/2 cup coconut oil
1 tablespoon honey
1/2 teaspoon Authentic Foods Vanilla Powder (or vanilla extract)
Combine the wet and dry ingredients with a sturdy wooden spoon until you get a sticky batter.
Make your egg replacement (or use 2 organic eggs):
1 tablespoon Ener-G Egg Replacer
4 tablespoons warm water
Whip the egg replacer ingredients till foamy and frothy. [If you are adding eggs instead, beat two large free-range organic eggs; and omit the egg replacement formula.]
Add the egg replacer to the batter and combine well. The dough should be thick and rather sticky.
2 to 4 tablespoons of warm water, as needed to achieve a dough that sticks together when you pinch it- much like cookie dough.
Now add in and stir to combine:
1/2 cup golden raisins or chopped dried fruit, if desired
2/3 cup dairy-free chocolate chips or chopped nuts
Preheat the oven to 350ºF. Line a 11x9-inch baking pan with lightly greased parchment.
Spread the batter into the prepared baking pan, and using wet hands, smooth the surface evenly. Place the pan into the center of a pre-heated oven and bake until golden and set - about 22 to 30 minutes until the top is golden brown and the center if firm. Insert s thin knife to check if you are unsure to make certain the center has baked thoroughly.
Cool on a wire rack, darling. Using a thin sharp knife, cut into squares; wrap them in foil; bag in a freezer storage bag. Freeze. Delicious slightly chilled.
Makes 15 to 18 bars, aka breakfast brownies.
Recipe Source: glutenfreegoddess.blogspot.com
All images & content are copyright protected, all rights reserved. Please do not use our images or content without prior permission. Thank you.
Karina's Tips:
The dough for this should be sturdy- like a cookie dough.
If you prefer a more cakey treat, add a tablespoon or two of vanilla milk- or more- to make the dough lighter and sticky.

subset: commoncrawl


text:
Intel Arrandale: 32nm for Notebooks, Core i5 540M Reviewedby Anand Lal Shimpi on 1/4/2010 12:00 AM EST
- Posted in
- Laptops
38 Comments
Back to Article
silverblue - Friday, January 08, 2010 - linkHmm. Reply
silverblue - Friday, January 08, 2010 - linkNope, it's just me (damned similar names)... however, the Clarkdale article has vanished from the front page. :| Reply
dnenciu - Thursday, January 07, 2010 - linkI don't know why are reviewers so happy about Arrandale.
You basically get 20% improvement compared to the same "clockspeed" c2d.
What about the fact that Arrandale only goes 2.53Ghz and 2.66 for the extreme edition.
C2D already goes to 3.33Ghz
Yes turbo boost increases the 2.53Ghz to 3.06 but that is only if one core is used and the laptop has proper cooling.
The c2d at 3.06 Ghz can run two cores at that speed.
So what we are seeing is last years performance and same battery life.
And also last years integrated GPU. That now you don't even have a choice to replace with a 9400m.
I really feel underwhelmed by this chip release.
Lets hope that they can improve it in the next release because for me this one is a big flop. :( Reply
iwodo - Monday, January 04, 2010 - linkI record CoreiX series was proved to be much more efficient then C2D in some previous Anand article. Now we are actually getting different results. So Westmere gets more performance by using more energy and transistors.
And this isn't an fair comparison either, C2D platform uses an 65nm of IGP and 45nm of CPU. While Westmere gets one process node improvement in both.
So in terms of pure Power / Peformance, it looks like C2D still has an edge. I would love Intel make an 32nm of C2D. ( Which would play well with ION2 and Apple would love it. )
I hope SandyBridge would come soon as an True successor to C2D. Nahamlem to me is just an CPU made for Server.
Side Notes - Intel GPU, although performance is fast enough in lowest settings, still gives worst Image Quality compare to other IGP. Which gains an unfair advantage. I hope some Internet review will point this out. Reply
JarredWalton - Monday, January 04, 2010 - linkOn the desktop, Core i7 (and particularly Lynnfield) provided great idle power results. My testing of Core i7 notebooks on the other hand shows that the quad-core variant is a power guzzler. Reply
zicoz - Monday, January 04, 2010 - linkHow does this compare to the Clarkdale on the HTPC front? Does it support LPCM and bitstreaming? I have this dream of building a HTPC from laptop parts, and if this supports the same stuff as the Clarkdale then this could be it. Reply
jasperjones - Monday, January 04, 2010 - linkAnand writes:
"The first mainstream Arrandale CPUs are 35W TDP, compared to the 25W TDP of most thin and light notebooks based on mobile Core 2. Granted the 35W includes the graphics, but it's not always going to be lower total power consumption."
From the benches shown here I infer: the 540M is substantially faster than the fastest available C2D. Which is to say, the T9900 (unless I forget some Core 2 Extreme model) whose TDP is 35W. There is no P-series C2D that provides the performance of the 540M. Thus, an apples-to-apples comparison is really vs. a T9900 (or Core 2 Extreme) which has 35W TDP and *no* integrated graphics.
And even if you aren't d'accord with my statement above: logically, you can't just compare the P8xxx/P9xxx models' TDP of 25W with Clarksfield's TDP of 35W. After all, Clarksfield includes essentially all Northbridge functionality. The Northbridge for Penryn is rated 12W TDP. So, really, 35W < 25W + 12W = 37W (or, 35W < 35W + 12W = 47W). Reply
jasperjones - Monday, January 04, 2010 - link^^^ of course, I mean Arrandale, not Clarksfield. Reply
JarredWalton - Monday, January 04, 2010 - linkEven then, TDP ratings aren't actual power requirements. They're more like a limit on the thermal output, so you need 35W of cooling on a 35W CPU, even though at idle it probably uses only 5W.
As far as performance, Arrandale in most cases is about 20% faster. The T9900 is 3.06GHz compared to 2.53GHz on the P8700, which is a 20% performance boost. That would make the T9900 about equal to a 540M. At that level of performance, I would expect the battery life advantage to be more like 5-10% for Arrandale. (Despite the 35W vs. 25W TDP, my experience is that for typical battery life testing scenarios, the 35W TDP CPUs are not substantially worse than 25W CPUs.) Reply
Wolfpup - Monday, January 04, 2010 - linkI'm still surprised that we don't get 32nm quads yet, though I suppose from Intel's perspective it makes sense-probably make the most from their mid range "high end dual cores".
I'm glad to see there are some new chipsets with this too. PM55 has USB problems, that OEMs don't seem to be addressing super well. There's some talk that the newest drivers from Intel combined with a hotfix from Microsoft that isn't even for this chipset fixes it, but not 100% sure if it really does. Reply
Alberto - Monday, January 04, 2010 - linkAccording to www.legitreviews.com/article/1169/15/ and www.legitreviews.com/article/1169/16/ the idle power is very interesting, lower then the older plataform of around 30%.
Likely the difference between the two articles is due to a different bios. Moreover Legit has done a lot of tweaks to make the two plataforms comparable (cpu apart). In the battery test, the Monteniva laptop has a 6 cell battery instead of a 8 cell, but the 30% figure seem confirmated. Reply
HotFoot - Monday, January 04, 2010 - linkOne thing I've often wondered about battery tests is variability in the batteries themselves. Of course, over time batteries wear out and life goes down - but what about the difference between new batteries, even ones of the same rated capacities?
I would be interested to see a review such as this one, but where the battery life is tested twice - swapping batteries between platforms and taking the average. Some adaptation will probably be needed. Or, maybe a standard battery testbench used for all battery life tests - which would involve adapters for each notebook.
My point is uncertainty. I know it's not an academic paper, but if the variability in results is 10% or higher (which my gut tells me it very well may be with batteries), the conclusions drawn from the results could be radically different. Maybe it's not that bad, and a few tests into the subject would demonstrate that. Reply
JarredWalton - Monday, January 04, 2010 - linkI had http://www.anandtech.com/mobile/showdoc.aspx?i=361...">two Gateway laptops that had the same battery design, only one was Intel-based and the other was AMD-based. After a request similar to yours, I swapped the batteries and retested. Variability was less than 2%, which is the same variability between test runs. Reply
kazuha vinland - Monday, January 04, 2010 - linkYour unit was obviously just a prototype, but can we expect to see the first Arrendale laptops arriving this or next month? Reply
webmastir - Monday, January 04, 2010 - linklove reading your reviews - very insightful. thanks. Reply
8steve8 - Monday, January 04, 2010 - linkwhen can we expect reviews of these ULV processors?
when can we expect laptops with these ULV processors? Reply
strikeback03 - Monday, January 04, 2010 - linkAnd seriously, wtf was intel thinking with these names? 5 processors, all at different speeds, with either 640 or 620 in the name. If a 620LM was the same speed as a 620UM but just used less power I could see it, but there are 3 processors with 620 in the name, running at 1.06, 2.0, and 2.66GHz. The consumer also has to know that a 620M is faster than a 640LM. Reply
ET - Monday, January 04, 2010 - linkI'd love to see more comprehensive mobile benchmarks, but it looks like finally Intel graphics isn't the complete crap it used to be. Reply
yuhong - Monday, January 04, 2010 - linkOn Intel codenames, "Clarksfield" can be easily confused with the desktop "Clarkfield". Reply
yuhong - Monday, January 04, 2010 - linkOops, I mean Clarkdale by Clarkfield. Reply
bsoft16384 - Monday, January 04, 2010 - linkThe biggest problem with Intel graphics isn't performance - it's image quality. Intel's GPUs don't have AA and their AF implementation is basically useless.
Add in the fact that the Intel recently added a 'texture blurring' feature to their drivers to improve performance (which is, I believe, on by default) and you end up with quite a different experience compared with a Radeon 4200 or GeForce 9400M based solution, even if the performance is nominally similar.
Also, I've noticed that Intel graphics do considerably better in benchmarks than they do in the real world. The Intel GMA X4500MHD in my CULV-based Acer 1410 does around ~650 in 3DMark06, which is about 50% "faster" than my friend's 3-year-old GeForce 6150-based AMD Turion notebook. But get in-game, with some particle effects going, and the Intel pisses all over the floor (~3-4fps) while the GeForce 6150 still manages to chug along at 15fps or so. Reply
bobsmith1492 - Monday, January 04, 2010 - linkThat is, Intel's integrated graphics are so slow that even if they offered AA/AF they are too slow to actually be able to use them. The same goes for low-end Nvidia integrated graphics as well. Reply
bsoft16384 - Tuesday, January 05, 2010 - linkNot true for NV/AMD. WoW, for example, runs fine with AA/AF on GeForce 9400. It runs decent with AF on the Radeon 3200 too.
Remember that 20fps is actually pretty playable in WoW with hardware cursor (so the cursor is always 20fps). Reply
bobsmith1492 - Monday, January 04, 2010 - linkDo you really think you can actually use AA/AF on an integrated Intel video processor? I don't believe your point is relevant. Reply
MonkeyPaw - Monday, January 04, 2010 - linkYes, since AA and AF can really help the appearance of older titles. Some of us don't expect an IGP to run Crysis. Reply
JarredWalton - Monday, January 04, 2010 - linkThe problem is that AA is really memory intensive, even on older titles. Basically, it can double the bandwidth requirements and since you're already sharing bandwidth with the CPU it's a severe bottleneck. I've never seen an IGP run 2xAA at a reasonable frame rate. Reply
bsoft16384 - Tuesday, January 05, 2010 - linkNewer AMD/NV GPUs have a lot of bandwidth saving features, so AA is pretty reasonable in many less demanding titles (e.g. CS:S or WoW) on the HD4200 or GeForce 9400. Reply
bsoft16384 - Tuesday, January 05, 2010 - linkAnd, FYI, yes, I've tried both. I had a MacBook Pro (13") briefly, and while I ultimately decided that the graphics performance wasn't quite good enough (compared with, say, my old T61 with a Quadro NVS140m), it was still night and day compared with the GMA X4500.
The bottom line in my experience is that the GMA has worse quality output (particularly texture filtering) and that it absolutely dies with particle effects or lots of geometry.
WoW is not at all a shader-heavy game, but it can be surprisingly geometry and texture heavy for low-end cards in dense scenes. The Radeon 4200 is "only" about 2x as fast as the GMA X4500 in most benchmarks, but if you go load up demanding environments in WoW you'll notice that the GMA is 4 or 5 times slower. Worse, the GMA X4500 doesn't really get any faster when you lower the resolution or quality settings.
Maybe the new generation GMA solves these issues, but my general suspicion is that it's still not up-to-par with the GeForce 9400 or Radeon 4200 in worst-case performance or image quality, which is what I really care about. Reply
JarredWalton - Tuesday, January 05, 2010 - linkWell, that's the rub, isn't it: GMA 4500MHD is not the same as the X4500 in the new Arrandale CPUs. We don't know everything that has changed, but performance alone shows a huge difference. We went from 10 shader units to 12 and performance at times more than doubled. Is it driver optimizations, or is it better hardware? I'm inclined to think it's probably some of both, and when I get some Arrandale laptops to test I'll be sure to run more games on them. :-) Reply
dagamer34 - Monday, January 04, 2010 - linkSounds like while performance increased, battery life was just "meh". However, does the increased performance factor in the Turbo Boost that Arrandale can perform or was the clock speed locked at the same rate as the Core 2 Duo?
And what about how battery life is affected by boosting performance with Turbo Boost? I guess we'll have to wait for production models for more definitive answers (I'm basically waiting for the next-gen 13.3" MacBook Pro to replace my late-2006 MacBook Pro). Reply
MonkeyPaw - Monday, January 04, 2010 - linkPersonally, I'm disappointed with the "unchanged" battery life. The reality is, most IGP-based notebooks don't need to be faster to most people. A few friends of mine recently bought notebooks, and they have what I call average requirements: email, browser, iTunes, office, photo management. My advice to them was that anything they buy today will be more than fast enough for their needs (they were currently running outdated machines), and that their decision should be based on things like battery life and bonus features. Even my own notebook purchase was based less on total processing power and more on price, then battery life.
I think Intel had it backwards. Start by improving battery life, then slowly improve performance. That may have been their plan, but it looks like 32nm has a ways to go for them before that can happen. Reply
JarredWalton - Monday, January 04, 2010 - linkI would expect the LV versions to be competitive, but it wouldn't surprise me if the initial 32nm parts are not where they would like in terms of power use. The rev 2 of Arrandale will hopefully address that shortcoming. Reply
secretanchitman - Monday, January 04, 2010 - linkthats the thing though - who knows what apple is going to do now, since they currently use ion/9400m in the macbooks/macbook pros. they do use intel + discrete ati in the current imacs, yet the lowest end imac has a 9400 in it. the problem with arrandale is that it has the gpu integrated on, and traditionally...intel integrated graphics suck compared to nvidia and ati gpus.
im hoping that intel made special versions of arrandale without the built in gpu, or they are able to turn it off, and use separate graphics instead. lets be honest, the 9400m is much better than anything intel offers now. Reply
taltamir - Thursday, February 04, 2010 - linkwhat does it matter? apple can't run games anyways... neither can any laptop.
The difference between intel and nvidia/ati is that a laptop with nvidia/ati can get playable FPS on the absolute LOWEST settings which look like crap. the intel can NOT get playable FPS, period.
Either would be a horrid experience for a gamer... get a desktop if you want to game. Reply
filotti - Tuesday, January 05, 2010 - linkActually, the article says that the performance of the integrated GPU is equal to the performance of the 790GX IGP. This means that it should be equivalent to the 9400m too. Reply
mino - Saturday, January 09, 2010 - linkRaw performance? Probably comparable to 785G in 3D benchmarketing.
Drivers to be able to use the performance. Non existent.
This is pretty much a beefed up HD4500. Nothing less, nothing more. Reply
marc1000 - Monday, January 04, 2010 - linkThe desktop versions have a 16xPCIe slot, so I believe it IS possible to pair the mobile versions with discrete grapchis too. Not that manufacturers will be that much interested in doing so. After all, it seems that Intel aimed for the same level of performance that 9400 has, so Apple would not have reasons to go "non-Intel". I guess this is the primary reason why they made the GPU perform exactly at this level. It's the "good enough" philosophy. Reply
Penti - Tuesday, January 05, 2010 - linkOf course you can, HM/QM/QS57 supports switchable graphics too and has x16 or the same 16 (maybe) lanes on-die as the desktop parts for discrete graphics. It also has 8 lanes on the chipset. Apple, HP, Dell, Fujitsu etc will be interested in more high-end business models and consumer products. Reply


text:
AMD Core Counts and Bulldozer: Preparing for an APU Worldby Anand Lal Shimpi on 11/30/2009 12:00 AM EST
- Posted in
- CPUs
94 Comments
Back to Article
mattclary - Monday, December 14, 2009 - link[quote]
Think of each twin Integer core Bulldozer module as a single unit, so correct.
It's no wonder you misinterpreted what he said. This is vague at best! "Is it either or? - Correct!" Reply
aj28 - Thursday, December 03, 2009 - linkAlright, so here's the quote from the article. Take note of the parts in bold...
[QUOTE]Also, just to confirm, when your roadmap refers to 4 bulldozer cores that is four of these cores:
Or does each one of those cores count as two? I think it's the former but I just wanted to confirm.[/QUOTE]
And AMD's response...
[QUOTE]Think of each twin Integer core Bulldozer module as a single unit, so correct.[/QUOTE]
So to me this reads, "Correct, the former, meaning..."
[QUOTE]...when your roadmap refers to 4 bulldozer cores that is four of these cores:
There's a good chance that the majority is correct and I am in fact wrong, but... Well, that's just how I read their response. I feel there is a good chance of some more confusion afoot, much like the percentages being thrown around in the original article. Reply
aj28 - Thursday, December 03, 2009 - linkI think it's also worth noting that I fail at quoting... Evidently... Sorry! Reply
swindelljd - Wednesday, December 02, 2009 - linkI bet Oracle is salivating over the new core count technique since it is sure to create a huge surge in their revenue because they charge per core on the x86 platform. Reply
Sivar - Tuesday, December 01, 2009 - linkIf FP performance is given the backseat, it could impact game performance for well multi-threaded games. Reply
JumpingJack - Wednesday, December 02, 2009 - linkDepends on how effectively the designers are able to share the FP in this arrangement, but yeah -- gaming will be a question mark. I am pretty confident it will be better not worse. Reply
nirmv - Tuesday, December 01, 2009 - linkFor what I understand, AMD figured out how to reduce core size by 25% without impacting performance.
Each 2 cores will now share the same fetch/decode units (using SMT like Intel), and also the same FP unit (but doubled for 256 bits so actually it's 2 128 bit unit), but seperate Int unit like before). So actually they share half of the logic of two cores together, so they now use 150% of the die area of one core for 2 cores, or in other words save 25% of each core (75% * 2 = 150%).
But, it will still have 1/2 the throuput of Sandy Bridge in FP, and they still will have 1/2 the bandwidth of the fetch/decode because they use 1 for two cores instead using 1 per each.
Nevertheless it looks like a wise decision in terms of power/performance. So nice, but it won't give AMD the performance crown.
Seramics - Tuesday, December 01, 2009 - linkFrom the way it seems, I'm afraid the badly delayed, highly anticipated, much hyped and AMD's only hope to retake the performance crown from Intel will fall short of expectations. Unless they really come up with a competitive n powerful processor, I'm afraid the AMD we know from A64 days will continue to be history till the next major architecture after bulldozer which could well be 5 years or so after 2011. AMD to be budget player till then. Reply
Alberto - Tuesday, December 01, 2009 - linkBuldozer seems too late against Intel upcoming offerings.
An eight core Buldozer will be clearly slower than an eight core Sandy Bridge, in both integer and Fp.
This cpu implementation seems done to fight Nehalem ( two 128 bit units, both possibly utilized from one core only ).
Sandy Bridge will have two times Fp power and threads per die,
assuming the article right.
The only manner to be competitive is to consider a single "block"
like a monolitic core. Intel can answer with 50% more cores/die,
performing a complessive better integer and Fp performance.
Still we don't know what will be the new integer performance of the
Sandy Bridge integer unit. I believe it will be higher than in Nehalem.
epobirs - Tuesday, December 01, 2009 - linkI don't buy this claim that FP will be eliminated from CPUs in favor of doing it all on a GPU. There are too many situations where FP is still needed on a per core basis with a primarily integer load. About two minutes after the first systems ship with no integrated FP in the CPU (Bulldozer SX?) there will be engineers thinking themselves clever by proposing to boost FP performance by integrating it into the CPU die!
What will happen instead is the FP and onboard low-end graphics solution will merge. The monster GPUs will be there for high-end FP as needed and the die area consumed by the FP and IGA minimized so as to be beneath concern. FP may be external to the cores but they won't be sold without at least one FP/IGA module in the mix. That way you have a chip that is versatile for a wide range of different boxes but also cost competitive. Reply
Alberto - Tuesday, December 01, 2009 - linkYou are right.
The eight core Sandy Bridge will have over 200 Gflops Double Precision with a power budget of 130W in 32nm and 95W in 22nm.
In these conditions the "dream" to throw away the Fp unit from the CPU it's only a Nvidia desire.....to survive.
gruffi - Sunday, December 06, 2009 - linkGive me your calculation please. I see Sandy Bridge nowhere near 200 GFLOPS in DP.
Sandy Bridge may have up to 8 cores/16 threads (the known die shot shows only 4 cores), probably clocked around 3 GHz.
4 DP (AVX/256-bit) * 1 op/cycle (no FMA) * 8 cores * 3 GHz = 96 GFLOPS
OTOH, AMD may have twice as much FP throughput with "Interlagos" (8 modules/16 cores/16 threads) if we assume similar clock rates.
4 DP (AVX/256-bit) * 2 ops/cycle (FMA4) * 8 modules * 3 GHz = 192 GFLOPS
psychobriggsy - Tuesday, December 01, 2009 - linkThat certainly beats AMD's ~100GFLOPS in double precision from an 8-core Bulldozer.
Calculation: 3GHz * 2 (FMA) * 2 (units) * 2 DP (128-bit unit) * 4 (modules).
Clearly AMD are providing enough CPU power for OpenCL, etc, to run "well", but if you need "serious" power then you'll plug in an RV900 series GPU that will probably try to get near 1TFLOP in DP in the same timeframe. With OpenCL, the exact same code will run (AMD's OpenCL driver can switch between CPU and GPU without any application changes). Reply
epobirs - Tuesday, December 01, 2009 - linkIt looks like AMD is engaging in another word of words instead of performance. Remember when they claimed ownership of what was or was not 'dual core' and 'quad core?' While AMD declared the C2Q line as 'not true quad-core' the Intel product was actually shipping and available for use a year before AMD's 'true' chips came out with less performance and some serious bugs for added enjoyment.
This gets tiresome to the point where I hold AMD in great suspicion when they lead with a new official vocabulary instead of the product and how it actually performs.
I truly don't give a damn about your modules, AMD. Take your new architecture and define the smallest portion that could be sold as a discrete product to run a PC. That is a core. It doesn't matter how many threads it runs. It is a core. If we cannot have meaningful definition to which all companies adhere, the conversation is dead and all that remains is useless PR blather. Reply
Nehemoth - Tuesday, December 01, 2009 - linkWell said. At the end of the day users don't care about the elegance of the architecture they'll care about performance, performance per watt, etc, etc.
PD : Where is the Z Ram technology they're licensed back time ago for the Cache Memory?
What about the license for XDR from Rambus?
At less for some servers should have a value. Reply
Nehemoth - Tuesday, December 01, 2009 - linkWell said. At the end of the day users don't care about the elegance of the architecture they'll care about performance, performance per watt, etc, etc.
PD : Where is the Z Ram technology they're licensed back time ago for the Cache Memory?
What about the license for XDR from Rambus?
At less for some servers should have a value. Reply
Milleman - Monday, November 30, 2009 - linkIt's good to see that the existance of AMD is healthy for the competition, progress and innovation. The existance of AMD is even good for the Intel fan-boys. The Inte CPU's wouldent be half that fast today, if there wasn't any competition on the market. Reply
jmurbank - Monday, November 30, 2009 - linkAn AMD representative said that the picture you provided is one core, but it has two integer units. These two integer units are hardware basis of a similar feature of Intel's Hyperthreading. The following picture is a dual core.
The four core is the following image.
This is all assuming the Bulldozer core is for their enthusiasts or high end setups. For the low end, these pictures will not include two integer units. Though it all depends what AMD has in store for the microcode for their Bulldozer core because it can be one way and other or it can be both that can take advantage of both features by including a switch in the BIOS or software, but it is too soon. Reply
Milleman - Monday, November 30, 2009 - linkLooks like the AMD CPU's are slowly getting structures "borrowed" from ATI GPU's, which is very interrresting. The traditional CPU strukture from the seventies are on the way out. The future looks really exciting! Reply
tatertot - Monday, November 30, 2009 - linkAMD marketing made a mistake (Fruehe, on his blog) when referring to an AMD engineering claim made by Moore.
The claim is on slide 4:
80% more throughput (integer work) for 50% more (core) area.
Fruehe LOLed this into 80% more performance for 5% more area (ooops!), and now this meme has taken hold.
It's wrong. Each module is 50% larger to get 80% more integer throughput, and even adding in all the "uncore" portions on a chip does not get this number anywhere NEAR 5%. (The uncore is nowhere near 10x the area of all the core area combined) Reply
vsary6968 - Tuesday, December 01, 2009 - linkthis slide was 2005. This is not the latest slide. you need to do more research. Reply
vsary6968 - Tuesday, December 01, 2009 - linkthis slide was 2005. This is not the latest slide. you need to do more research. Reply
Anand Lal Shimpi - Monday, November 30, 2009 - linkYou're very right, AMD responded and said that the 5% figure was incorrect. Unfortunately it looks like both Johan and I were given the same incorrect info.
The real figure is closer to 50%, I've updated the article accordingly.
Thanks again :)
Take care,
Anand Reply
piesquared - Monday, November 30, 2009 - linkI think i'd investigate a little further. Judging by the block diagrams each integer core is no where near 50% of the die, so obviously that number can't be correct.... Reply
JumpingJack - Tuesday, December 01, 2009 - linkAnd as we all know, these power point block diagrams are carefully scaled to ensure that blocks are exactly proportional to the actual units located on the floor plan of the die.
From this, one may extrapolate the L3 cache is not much more the 512 KB.
Thanks for the knee slapper.
Jack Reply
GaiaHunter - Monday, November 30, 2009 - linkI'm still not sure. JF arguing is solid.
That 5% and 50% could be just semantics.
Because JF said, distinctly and repeatedly, he was talking about total die size, while the 50% is referring to the area of the module, sans L3$/IMC/NB/etc. And more specifically the Int-core area, which clearly doubles when going from 1 Int-core to 2 Int-cores.
So, while to get up to 180% increase in integer performance you need to double the area (or 50% of the total integer area)dedicated to integer operations, that relatively to the total die size may well take only 5% of the die space.
GaiaHunter - Monday, November 30, 2009 - linkI really think this is semantics again.
Module and Die.
Module is 50% bigger but die is only 5% bigger. Reply
psychobriggsy - Tuesday, December 01, 2009 - linkA single integer core (just the unique per-core parts, not the shared functionality in the module) takes up 5% of a typical quad-core Bulldozer die (including uncore and L3)? Or maybe even an octo-core die.
Also assume rounding up and down and nearest. Could be 47% and 5.4%, etc.
It's a way away yet. Let's see what happens. Reply
smilingcrow - Monday, November 30, 2009 - link5% always sounded very unrealistic as that would mean a remarkable increase in IPC for such a small increase in 'core' size.
If it was only 5% we would expect to see a native 8 module version being for the desktop if looked at purely from die size or on a cost basis. But at 50% extra it means that all other things being equal 4 modules = 6 'simple' cores in space terms ignoring the uncore.
I'm still not 100% clear on the 50% thing. If a die is 50% cores and 50% un-core and measures 100 sq mm. When we add the 50% larger cores to the equation the cores become 75 sq mm and the die becomes 25% larger or 125 sq mm. Or is there another portion of the module/core that is excluded so the total size increase is less than 25 sq mm?
Zool - Monday, November 30, 2009 - linkThat 50% sounds much more realistic.
On the k10 die are http://en.wikipedia.org/wiki/File:K10h.jpg">http://en.wikipedia.org/wiki/File:K10h.jpg u can see
that doubling the integer pipeline, data cache and load store unit is clearly more than 5% :P.
The thing is that L2 cache and L3 cache are in the buldozer module picture and they are several times bigger die area than the core. And there are also other things in the uncore like memory controler, hypertransport. The whole die vs core is quite diferent than the whole die vs module. They say 50% more core area invested not module or die area. Reply
Zool - Monday, November 30, 2009 - linkThis is the K10 core from wikipedia with integer pipeline highlited (and other areas too) http://en.wikipedia.org/wiki/File:K10h.jpg">http://en.wikipedia.org/wiki/File:K10h.jpg .
The 5% are is quite realistic if count in the shared L1 and L2 cache for one module. Reply
psychobriggsy - Tuesday, December 01, 2009 - linkThe L1 caches are duplicated however. Also the Load/Store units I presume, but maybe there is a way to share some resource there.
What that diagram does show is that there are two 64-bit SIMDs (one of which can do x87) in K10 (not K10.5).
In Bulldozer there are two 128-bit SIMDS (that can also do FMA). I presume that they can each do x87 if they deign to lower themselves to the task.
That's why the FP performance has gone up. FMA counts as two operations when it comes to Linpack. :D FP is doubled compared to K10, even on a per-BDcore basis.
Will we refer to a Bulldozer module as K11? Reply
GaiaHunter - Monday, November 30, 2009 - linkIn the guy own words
[quote]I think the difference between 50% and 5% might be the difference between marketing and engineering. Engineers tend to be very literal.
If 2 cores get you 180% performance of 1, then in simple terms, that extra core is 50% that gets you the 80%.
What I asked the engineering team was "what is the actual die space of the dedicated integer portion of the module"? So, for instance, if I took an 8 core processor (with 4 modules) and removed one integer core from each module, how much die space would that save. The answer was ~5%.
Simply put, in each module, there are plenty of shared components. And there is a large cache in the processor. And a northbridge/memory controller. The dies themselves are small in relative terms.[/quote] Reply
tatertot - Monday, November 30, 2009 - linkThe guy is wrong, or his engineering team misunderstood.
Moore (the lead designer) said about 50% increase to double the integer resources, L1D, etc. That sounds about right.
What I COULD believe is this:
Q: "If I took an 8 core processor (with 4 modules) and removed 1 integer core from ONE module, how much die space would that save?" A: 5%
In other words, if you removed them from all 4, you'd save 20%.
If you figure that the uncore takes up a bit more than half of the die, that would be totally consistent with Moore's 50% larger core figure.
For example (totally made up numbers):
Die size 300 mm2
uncore 160 mm2
4 BD modules 140mm^2
1 BD module 35 mm2
1 BD module without extra integer units: 23 mm2
(Savings from lopping 1 BD module: 12mm^2)
4 BD modules without extra integer units: 93 mm2
(Savings from lopping 4 BD modules: 47mm^2)
12/300 is 4%, which is what his engineers thought he was asking.
But really he was asking about 47/300 or ~16%.
So as stated, the 5% is wrong. It's the area cost of 1 of the module's extra int resources on a 4 module die. All 4 of them cost more.
And this would be consistent with Moore's estimate that relative to JUST the module, it is a 50% area increase.
psychobriggsy - Tuesday, December 01, 2009 - linkThanks for doing the example maths.
Yes, it looks like adding a single core to each module adds around 15%-20% to the die size of a dual-module/quad-core Bulldozer.
So 20% die space for 80% performance increase. Well, until you decide to make the L2 larger because there will be more contention for it.
Of course the 5% die area for SMT in Nehalem is negligable when you start factoring in the uncore portions as above... Reply
GaiaHunter - Monday, November 30, 2009 - linkMeh, I miss-clicked and reported your post by mistake, sorry about that. :(
Anyway, imagine a int core is 5% area of a total module and that a module size is 100 (size units not mm^2), so the int core size is 5. 4 modules will then be 400 and 4 int cores will be 20. 20 is 5% of 400, not 20%. Same for 8 modules.
You have to see, that they do need 50% more area to get 80% Int boost performance as they are using a second Int core to accomplish that. So the dedicated area of module to do Int operations is 2x the size of a regular Int core. Reply
GaiaHunter - Monday, November 30, 2009 - linkMeh, I miss-clicked and reported your post by mistake, sorry about that. :(
Anyway, imagine a int core is 5% area of a total module and that a module size is 100 (size units not mm^2), so the int core size is 5. 4 modules will then be 400 and 4 int cores will be 20. 20 is 5% of 400, not 20%. Same for 8 modules.
You have to see, that they do need 50% more area to get 80% Int boost performance as they are using a second Int core to accomplish that. So the dedicated area of module to do Int operations is 2x the size of a regular Int core. Reply
HolKann - Monday, November 30, 2009 - linkNah, you don't understand him. His assumptions are:
1. one int core is about 5% of the whole die (including uncore).
2. one int core is about 50% of a module.
3. the uncore makes up about half of the core.
Put this in numbers:
Take a module as 100 size units. 4 modules means 400 size units, adding the uncore makes the size of the whole die 800. 5% of 800 is 40 size units. And tadaa, this makes an int core 40% of the size of a module ;) The number gets closer to 50% if one takes the uncore bigger.
If his assumptions are correct, a 25% total die increase (4*5% to 80%) results in 80% extra performance. This is about as good as Intel's 5% die increase for 15-20% extra performance (I know, this is a bold statement, a lot of unknown variables could alter this situation drastically). Reply
GaiaHunter - Monday, November 30, 2009 - linkThe data we have is: Removing 1 int core 5% from each module would result on 5% reduction of total die size. 1 int core = 50% of the total area dedicated to integer operations.
So, for a total die of lets say 1000 units with 8 int cores, 4 int cores represent 5% of the total die size or 50 size units.
So each int core is 12,5 size units and the 8 int cores take 100 size units or 10% of the core.
Assuming sizes for total die size or what is the Bulldozer Module size relative to total size is pure speculation, as we don't have any numbers other than that JF affirmation.
To remember:
"What I asked the engineering team was "what is the actual die space of the dedicated integer portion of the module"? So, for instance, if I took an 8 core processor (with 4 modules) and removed one integer core from each module, how much die space would that save. The answer was ~5%. "
That was the affirmation.
In no way this contradicts the affirmation that AMD increased the Module area dedicated to integer operations by 50% to achieve 80% performance.
Main point is DIE SIZE ? BULLDOZER MODULE. Reply
tatertot - Monday, November 30, 2009 - linkI am disputing the JF claim: " Removing 1 int core 5% from each module would result on 5% reduction of total die size. "
I suspect that his engineers misunderstood his question, and it is actually the removal of the "extra core" from ONE BD module that would result in 5% overall die savings.
You can take it to the bank that Moore is correct that adding another integer execution unit group , L1D, etc to the core (thus making 2 cores, or a 'module') increased the size by 50%. Moore is the designer, not a marketing guy.
In order for Fruehe's claim to be correct, the uncore area would have to be VERY large:
Some more (different numbers):
Assume BD module is 30 mm2, (thus increased by 10 mm2, or 50% from 20 mm2 to add the second 'core', per Moore)
If 5% were actually the correct estimation of the area added for 4 BD modules (4 * 10 mm2 increase = 40 mm2 increase), then the overall die size would need to be... 800 mm^2.
This is nuts.
On the other hand, if "5% of the total die area" is the estimate of the space needed to add the integer resources to just 1 BD module, then the overall die can be 200 mm^2, so uncore 80 mm^2, 4 BD modules at 120 mm^2, and then Moore's numbers can be consistent with what JF heard back from the engineers.
So, my theory is that his engineers thought they were being asked how much of the total die (for a 4 BD module part) the increase in integer units to 1 BD module resulted in, while JF thought he was asking how much the increase to ALL 4 modules would be. This would be an easy misunderstanding to have, and I don't see another way to reconcile Moore's information (which I trust), with JF's claim.
GaiaHunter - Monday, November 30, 2009 - linkYou start assuming the BM is 30mm^2.
But both integer cores are exactly the same size. So if the resources you add are 10mm^2, that means that 2 int cores take 20mm^2 and 8 is 80 mm^2.
GaiaHunter - Monday, November 30, 2009 - linkYou start assuming the BM is 30mm^2.
But both integer cores are exactly the same size. So if the resources you add are 10mm^2, that means that 2 int cores take 20mm^2 and 8 is 80 mm^2.
Now each integer core is 10mm^2 and represents 5% total die size - bam 200mm^2 die as you said.
You had 50% resources to the BM and end with each int core at 5% of the die size and even get your 200mm^2 die. Reply
GaiaHunter - Tuesday, December 01, 2009 - linkNow lets go the other way.
Lets assume JF is right and Moore is also right.
Grab a 8 core bulldozer CPU, shave 4 cores and save 5% die space.
CPU die size is 200mm^2.
5% is 10mm^2, so each int core is 2.5mm^2 and 8 of these will take 20mm^2.
Now, Deneb is 260mm^2.
If 8 core Bulldozer is 300mm^2, you end with 3.75mm^2 int cores.
Around half of the die will be L3$.
Northbridge circuits stay. Memory controller and the HT PHY also stay. L2$, fetch, decode and FPU are also shared.
So basically you are just removing a very small portion.
The question would be if you would need as much of those resources in the first place. Reply
GaiaHunter - Monday, November 30, 2009 - linkMoore affirmation is only related to the INTEGER AREA of the BULLDOZER Module.
Fruehe's claim is about total die size.
If Moore's claim is about Integer Area of the Bulldozer module and Fruehe's claim is about die size, then, these claims don't have to be mutually exclusive.
Additionally, there is no BULLDOZER MODULE. Forget about it. It isn't a unit by itself.
2 (or more) of those bulldozer modules will share L2$ and L3$ for example, so you can't even define a damn size for a frigging module to start with.
ThaHeretic - Monday, November 30, 2009 - linkI really hate the move to call each "module" 2 "cores." AMD is shooting themselves in the foot when it comes to software licensing, in particular, Oracle DB licensing where they charge .5 CPU license for each x86 "multi-core." AMD's decision will double the cost of software running on Bulldozer.
Bad move AMD, bad move. Reply
cfaalm - Monday, November 30, 2009 - linkReally? This issue popped up for OS licenses when x86 dual cores were first introduced. Microsoft decided to go on a "per socket" base, not counting cores. Reply
Calin - Monday, November 30, 2009 - linkMicrosoft requests licensing per mainboard socket. Oracle requests a decreased licensing cost per core, if the core is a part of a socket. Meanwhile, some other companies requests licensing costs per core.
Everyone with its own ways. Reply
cfaalm - Tuesday, December 01, 2009 - linkFair enough. So indeed this is a concern when buying this new stuff. I'd rather have AMD not call a this module 2 cores for the simple reason that is a sort of siamese twincore, not a true dual core. Though that is just the naming game. It looks promising nonetheless. Hopefully AMD/Oracle can enlighten the big system buyers by the time the decisions need to be made. Reply
ThaHeretic - Tuesday, December 01, 2009 - linkA lot of licenses and MRCs are based on socket count, unfortunately, many of the most expensive software packages licensing arrangements are derived from core-count. Since Oracle changed their multi-core licensing near the end of 2006, quad-core x86 processors have counted as two licenses, six-cores as three licenses, etc. A Bulldozer quad-module die will therefore need 4 licenses for OracleDB.
Does this suck? Yes. Is SQLServer's licensing model better for end-users? Yes. Is SQLServer anywhere near as awesome as Oracle Database? Hell no, not even close. Reply
DominionSeraph - Monday, November 30, 2009 - link"AMD claims that the performance benefit from the second integer core on a single Bulldozer module is up to 80% on threaded code."
Yet their performance graph has FP gains outrunning integer. Reply
Lifted - Monday, November 30, 2009 - linkThis. Maybe this takes into account the moving of FP off the die to a add on module or GPU.
I never could have imagined we'd be going back to the add on FP modules. Reply
GodisanAtheist - Monday, November 30, 2009 - linkI believe that's because Interlagos gets the integrated GPU core, which in terms of theoretical performance will send FP performance through the roof. Reply
DominionSeraph - Monday, November 30, 2009 - linkBut then the performance is underwhelming. Current-gen GPUs would be off the chart. Reply
medi01 - Monday, November 30, 2009 - linkCould someone decrypt the following text for me please:
[quote]It all started about two weeks ago when I got a request from AMD to have a quick conference call about Bulldozer. I get these sorts of calls for one of two reasons. Either:
1) I did something wrong, or
2) Intel did something wrong.
This time it was the former. I hate when it's the former.[/quote] Reply
GaiaHunter - Monday, November 30, 2009 - linkIt means Anand get these calls ("short conference calls") requested by AMD when:
1) Anand makes a mistake
2) Intel is being naughty (like telling OEM to not sell AMD).
I asked Anand in the Bulldozer article if a quad-core zambezi meant 4cores/8 threads or 4cores/4 threads.
He said (and I was convinced at that time it was the correct answer too)that a zambezi quad-core meant 4 cores/8 threads and an octo-core would be 8cores/16 threads. Or if you prefer 4Modules/8cores/8threads and 8Modules/16cores/16threads.
But it seems it is 2Modules/4cores/4threads and 4modules/8cores/8threads.
Sincerely, I can't really blame Anand - this shit is confusing. Reply
Kiijibari - Monday, November 30, 2009 - linkYes .. for desktops. However for Servers there will be again an MCM with two dies, i.e. 8 modules, 16 cores, 16 threads, called Interlagos. Reply
piesquared - Monday, November 30, 2009 - linkWhich makes a person wonder, if AMD has a 16 core Intelagos in the server space, how nice and cool and efficient will an 8 core Zambezi be. Reply
GaiaHunter - Monday, November 30, 2009 - linkU can see it in there
And also we can see that this new designation was causing quite a confusion in the forums.
http://forums.anandtech.com/showthread.php?t=20230...">http://forums.anandtech.com/showthread.php?t=20230... Reply
pcfxer - Monday, November 30, 2009 - linkThe first with L3 cache was Intel Pentium 4 EXTREME EDITION.
Phenom just had the most logical use of L3 in the sense that it served as a "community" buffer. Reply
JimmiG - Monday, November 30, 2009 - linkThe first with L3 cache was actually the AMD K6-III released in 1999. Of course, the L3 was actually on the mobo, while the L2 was on-die. But it did use a tri-level cache, making it outperform the Pentium III Katmai on integer workloads. Reply
Calin - Monday, November 30, 2009 - linkOnly on instructions per clock - the K6-3 was available at 400 and 450 MHz, while the Pentium !!! was available at (much later) up to 1300 MHz.
However, the K6-3 was in the competition against Pentium !!! at up to 550-600 MHz, as the original K7 appeared around those times. Reply
mino - Sunday, January 17, 2010 - linkK6-2+ and K6-3 were PII competitors that were able to outperform PII and even early PIII purely thanks to ON-DIE L2 and 3Dnow.
L3 was on motherboard back then, was slow, and had little to do with K6-2+/3 performance gains.
Also K6-2+/3 was the top AMD CPU for a very short time as K7 came righ afterward.
K6-2+/3 was the notebook & low cost bussiness desktop solution of the times while K6-2 (without cache) was the budget solution. Reply
medi01 - Monday, November 30, 2009 - linkWas it shared? Reply
Zool - Monday, November 30, 2009 - linkAny info on the amount of transistors for each module ?
At least they can make a decent notebook cpu from the modules. Mobile nehalem and phenons are everything with 4 cores just not low power notebook cpu-s. Reply
Zool - Monday, November 30, 2009 - linkSomething like 1 module no L3 cache for netbooks,notebooks.
2 modules with L3 cache for average notebooks and 4 or more modules for desktop replacement notebooks. They could play with the cache sizes too.
The 1 module no L3 cache for example would kill atom in performance. And the power usage could be still quite good. There is no meaning for 2-4 W slow cpu in netbook when the mainboard,hdd,display eats several times more electric power together than the cpu itself. Reply
JVLebbink - Monday, November 30, 2009 - linkI am wondering about the shared FPU. Does one thread really have to be purely integer for the other thread to use the 2 FMACs at the same time, or can one thread use the 2 FMACs if the other one is currently not sending FPU instructions. "if one thread is purely integer, the other can use all of the FP execution resources to itself." sounds like the first, but that would (1) waste FPU resources, (2) give problems with threads switching cores. (how does the not witched thread know it can now use all of the FPU resources?)
My presumption is that AMD chose the former and that if 2 (FMAC) instructions of different 'cores' reach the FPU (at that point in time) they will be executed using an FMAC each and if 2 instructions of one core reach the FPU without the other core sending any (at that point in time) they will be executed in parallel using both FMACs.
If my presumption is correct AMD decided not to HyperThread their ALUs but did HyperThread their FPU. Reply
Kiijibari - Monday, November 30, 2009 - linkYou do not have to switch anything.
The shared FPU has ONE common scheduler. Both threads can issue Ops into the scheduler queue. If there are no FPU Ops from the first thread then - of course - the second thread has the power of the whole FPU.
Very simple ... it's like a chat room. Several people type in messages and you can see it serialized in the chat window (that would be equivalent to the queue).
You will read the messages one after another, according to their posted time / when they were issued. It is the same for the Bulldozer FPU.
You do not need to switch from one chat member to another to read their messages. Neither does the FPU has to switch ;-) Reply
kobblestown - Monday, November 30, 2009 - linkI hope AMD regain their common sense and use the term "core" in amore conventional sense. According to their definition a quad core will only have 2 FP pipelines. What I see in a quad core Bulldozer is dual core with 2 Int and 1 FP pipeline each. I wish them the very best in their effort to regain the performance crown but abusing existing terminology will not help in that. Reply
Zool - Monday, November 30, 2009 - linkOS , drivers, API layers trashing the cpu constantly are usualy integer loads. For average math in code the curent fpus are fast enough. Things that realy need paralel FP performance (multimedia things,graphic) are using SIMD SSE units and those things should run much faster on gpus anyway. For 5% extra die area the extra integer pipeline rocks. Reply
fitten - Tuesday, December 01, 2009 - linkExcept it isn't 5% additional die area. Reply
Calin - Monday, November 30, 2009 - linkThis was started by Sun's Niagara (I think) processor - 32 "int cores" and only one FP unit. A physical integer core ran four threads at a time (one instruction from each, with instant context switching between them), so one would have had eight physical integer cores with only one FP unit.
The Niagara 2 would have had one FP unit for each of those integer cores, so one FP for each four int cores. Reply
defter - Monday, November 30, 2009 - linkThis confusion has nothing to do with int or fp cores. By a common definition, a core a standalone unit, which can function on it's own if necessary.
For example, each of Niagara's 8 cores had an own fetch and decode unit. In AMD's case, the "module" is the unit with it's own fetch and decode units, and integer ALU clusters only have own scheduler. Therefore, it's very confusing to call these clusters "cores".
AMD seems to learned confusing marketing from from ATI and it's 320/800/1600 shader GPUs (which have actually have 64/160/320 shader units) :) Reply
Spoelie - Monday, November 30, 2009 - linkYou're abusing the term pipelines and cores as well.
Trying to describe an unconventional design with conventional terms might not always be very clear, but there is no right or wrong on this issue, just different viewpoints. Reply
kobblestown - Monday, November 30, 2009 - linkFair enough. The use of the term "core" is still confusing though. There seems to be only one complete pipeline which branches after instruction decode. It's interesting whether the Icache is trace cache, i.e. contains decoded instructions or is a regular cache that needs to be fed back via the fetch/decode bottleneck. In the latter case I see no merit in calling the two integer (for lack of a better term) pipelines separate cores. Reply
Penti - Monday, November 30, 2009 - linkUhm, the Sun UltraSPARC T1 was a 8-core eight integer-units and one floating point unit, and with CMT - eight threads per core 32-thread. It was still called a 8-core CPU, but the T2 included a fp unit for every integer unit, so I doubt AMD will use this config for long. But who knows. It's impressive if its up to 30% faster then a PII with twich the number of FPU's.
Also one integer unit already includes three ALU's. They (the core/scheduler) seems independent enough. Reply
blyndy - Monday, November 30, 2009 - linkI also don't like their mixing of definitions. Let's just skirt that issue for now by call them by their thread number ie: 4-thread bulldozer, 8-thread bulldozer etc. Reply
blyndy - Monday, November 30, 2009 - linkFrom a marketing standpoint, '8 cores' would be more desirable to the laymen buyer than '4 cores', so that's one reason why they might have chosen to do it. Indeed I think Intel will quickly be following AMDs definition so as not to have 'less cores'. Reply
lyeoh - Wednesday, December 02, 2009 - link8 cores is not automatically more desirable than 4 cores to someone who buys stuff like Oracle. They get charged per _core_. Reply
heulenwolf - Monday, November 30, 2009 - linkIts a poor choice of words. Unfortunately, since the term "core" was never fully defined, everyone gets to have their own understanding of what it means. I took core to mean a complete processor that could, if packaged alone, perform all the functions of a processor (both integer and floating point). I think AMD should have taken the high road and called "modules" "dual-integer cores" instead of splitting them into two "cores" with this extraneous, shared FPU tacked on like an afterthought. It makes the term core meaningless. I would guess that making the term "Core" meaningless would be advantageous to AMD, however, since that is the term Intel uses for their entire architecture. Reply
Nocturnal - Monday, November 30, 2009 - linkVery interesting. I hope that AMD will one day regain their edge they once held against. Oh how I miss those days. I embrace Intel nonetheless. Reply
Alouette Radeon - Wednesday, March 10, 2010 - linkHow the hell could you embrace Intel after all the harm they've caused AMD, nVidia, VIA and ultimately us, the consumers with their criminal tactics? They don't give a damn about you, they just want your money. A lot of people say that AMD is no different (I know nVidia sure is the same as Intel in that regard) but at least they operate with integrity. They've never been accused of anything underhanded or sneaky. For that matter, neither has VIA. Intel and nVidia on the other hand, while nVidia has never done anything downright CRIMINAL, they've still been dishonest as hell. Intel on the other hand, has stooped about as low as you can go. So go ahead, embrace Intel, just like a stupid biatch who won't leave her abusive spouse. She just keeps going back for more and people like me who have brains can only shake our heads and wonder. Reply
AmbroseAthan - Monday, November 30, 2009 - linkWhile I agree Intel has the performance crown now, I can't knock AMD for being the value right now. Picked up an AMD x4 955 BE and Asus motherboard (full ATX/crossfire) for $230 to build my parents a computer with (Newegg combo). Intel can't compete in that price space easily. Reply
dilidolo - Monday, November 30, 2009 - linkIntel can't compete in that price range? No, Intel doesn't want to. Manufacturing capacity is limited, if I can sell more higher margin products, why should I go after lower margin segment? Leave that segment to AMD, the more AMD sells in that segment, the more money AMD looses. If Intel wants to compete in that segment, they can easily kill AMD, that's not what Intel wants to do. Reply
siuol11 - Tuesday, December 01, 2009 - linkAh, the ravings of the marginally informed... How the internet loves them! Reply
blyndy - Monday, November 30, 2009 - linkI'm very excited about AMD's brand-new design and how it's new ideas translate into performance, however:
"The quad-core Zambezi should have roughly 10 - 35% better integer performance than a similarly clocked quad-core Phenom II"
That sounds a bit low, I hope the final comparable CPUs can manage something more like 15 - 40% better integer performance over their PhII counterparts. Then again perhaps that's just because of Intels large performance increases between their recent architectures making us expect more -- they are more the exception than the rule, so 10 - 35 % shouldn't be sneezed at, although that just may not be competitive on their release in 2011. Reply
mczak - Monday, November 30, 2009 - linkConsidering that the int cores actually have less execution units (used to be 3 alus (plus shared load/store, but can do two operations per clock), bulldozer only 2 alus (+ load and separate store)) I think 10-35% better integer performance is amazing. More than that would be a miracle imho... Reply
Zool - Monday, November 30, 2009 - linkFrom the previous article "The extra integer core (schedulers, D-cache and pipelines) adds only 5% die space".
So the quad core Zambezi (2 modules, 4 integer pipelines)should have roughly 10-35% better integer performance than a similarly clocked quad-core Phenom II. Thats a super boost per transistor count. Reply
nafhan - Monday, November 30, 2009 - linkBased on AMD's re-defining of the word core that's actually a HUGE improvement. A quad core Zambezi has a similar transistor budget as a dual core Phenom II, and a 10-35% performance improvement.
In other words, quad core integer performance for dual core price. Reply
psychobriggsy - Tuesday, December 01, 2009 - linkA quad-core Bulldozer has the same transistor budget as a tri-core Phenom II (if they existed natively), yet performs around 20% better than a quad-core.
I think that SMT would have provided easier performance pickings (20% for 5% die space). I don't understand why AMD have been avoiding SMT so far. Sure, 80% more performance for 50% die space isn't to be sneezed at, but it's not so easy pickings.
In addition there are more integer resources than in a Phenom II core, and the FPU has two 128-bit FMAs, so each core could be reasonably bigger. In effect it could be that 1 Bulldozer module is the same size as two Phenom II cores - so all you have then is the 10-35% performance increase. I hope this is per-clock... Reply
titan7 - Sunday, December 06, 2009 - linkPerhaps the k7/k8 didn't make sense to add SMT? The p4 was really designed for it and had it enabled in genII. Look how long it took Intel to get SMT into the Pentium Pro/Core/i7.
I suspect AMD is designing for SMT right now, but gen1 is just "get to market ASAP because Intel is faster right now" and genII will have SMT enabled. Reply
gost80 - Monday, November 30, 2009 - linkJudging apparent benefit of this architecture over Intel's can be done only if the die size per _module_ is also made available. So, how about it? Reply
Zool - Thursday, December 03, 2009 - linkThe thing is that the picture in this article contains shared L2 cache and L3 cache too and its quite unclear from the picture if L2 is shared to one module or all modules.(sharing all modules 2 times with L2 and L3 would be quite useless)
The bulldozer picture in the other article from anandtech http://it.anandtech.com/IT/showdoc.aspx?i=3681&...">http://it.anandtech.com/IT/showdoc.aspx?i=3681&... shows clearly that the L2 cache belongs to module.
So clearly ading 50% to the core(which is everything till L1) is much less than 2 whole cores each with its own same size L2 cache ( Nehalem has only tiny 256KB cache per core from die area reasons).
If we take whole die size with 8MB L3 cache and 1MB L2 cache per module/core (+ things like memmory controler,hypertransport core/module conects) the final die increase could end in 10-15% or even less. Reply
Zool - Thursday, December 03, 2009 - linkSo a 4 module Bulldozer core with 512KB L2 cache and 6MB L3 cache could be something like 10-15% bigger than a 4 core PhenomII with 512KB L2 cache per core and same 6MB L3 cache. For 80% more integer performance that wouldnt be bad.
And about Oracle , the server cpu-s from both intel and AMD are running in ranges from few hundred dolars to over 2k dolars with minimal performance increase just more sockets suported and everyone is buying them. So i wouldnt care less for them than a fly on my window. It will end on final pricing per core for cpu not core/modul license price. Reply
swindelljd - Wednesday, December 02, 2009 - linkI bet Oracle is salivating over the new core count technique since it is sure to create a huge surge in their revenue because they charge per core on the x86 platform. Reply


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Paintings by Florida-based artist Jason John. See more images below.
Paintings by Florida-based artist Jason John. See more images below.
"Happy Breakfast" is a psychedelic zine by set designer and artist Gary Card. Filled with colourful and chaotic images that blur the line between cute and creepy, what began as a commission for Japanese magazine Them, has turned into something of an ongoing experiment thanks to London-based publishers Katie Bagley and Ferry Gouw of New World International. See more images below.
Paintings by Seattle-based artist and illustrator Kelly Bjork (previously featured here). See more images below.
Collages by artist Rachael Jablo, currently living and working in Berlin. Informed by the work of English botanist and photographer Anna Atkins, Jablo tears up photograms of flowers, piecing them back together to create new shapes and patterns. See more images from "Where are you going, where have you been?" below.
A selection of playful work by Bristol-based artist and illustrator Ed Cheverton, including several animations based on some of his 3D toys! See more images below.
Paintings by Los Angeles-based artist Daniel Bilmes. See more images below.


text: NEW YORK ( TheStreet) -- There is a special "loophole" in the Tax Code that allows one spouse in a married couple who file separate returns to file as "Married Filing Separate" and the other spouse to file as "Head of Household." To be "considered unmarried" and be able to file a separate return as "Head of Household" -- and pay less tax -- one of the spouses must have paid more than half the cost of maintaining his or her home that was the principal residence for more than half of the year for a child, stepchild, adopted child or foster child of the couple who is claimed as a dependent by that spouse (unless the noncustodial parent is allowed the dependency deduction via Form 8332). And the couple must have lived apart for at least the last six months of the year. John and Jane, who have two minor children, decided to split up in 2012. In April Jim moved out of the family home and into his own apartment. The two children remained with Jane in the family home for the rest of the year. After the split John gave Jane a check for his share of expenses most weeks, and Jane paid the mortgage payments on the home and the expenses of the household from her own checking account. They decide to file separately for 2012. John has no choice but to file as Married Filing Separately with no dependents, but Jane can file as Head of Household and claim the two children. It is very important that the two spouses do not live, or sleep, in the same home at any time during the last six months of the year.