text:
|Publication number
|Publication type
|Application number
|Publication date
|Aug 19, 2008
|Filing date
|Oct 24, 2003
|Priority date
|Oct 24, 2003
|Fee status
|Also published as
|Publication number
|Kreg A. Martin, Ronald K. Kreuzenstein, John M. Terry
|Original Assignee
|Brocade Communications, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (23), Referenced by (3), Classifications (13), Legal Events (8)
|External Links: USPTO, USPTO Assignment, Espacenet
This application relates to the following commonly assigned applications entitled: "Fibre Channel Switching System and Method," U.S. Pat. No. 6,160,813, issued Dec. 12, 2000; "Time Slot Memory Management," Ser. No. 10/658,900, filed Sep. 10, 2003, "Virtual Channel Remapping," Ser. No. 10/667,081, filed Sep. 18, 2003.
Many types of devices comprise a plurality of circuits. Such devices may include network switches, hubs, and routers. The circuits in the device may perform specific tasks, such as storing, routing, and manipulating data. For the device to properly operate, the timing of the circuits may need to be aligned with each other. The process of aligning the timing of circuits to ensure proper operation may be referred to as synchronization. Efficient techniques that synchronize circuits are desirable.
A device that synchronizes circuits over asynchronous links is disclosed. Some embodiments of the invention include a device that comprises a plurality of circuits. One of the plurality of circuits is designated as a "master" circuit. The master circuit is configured to send a first synchronization signal to one or more of the plurality of circuits, and each circuit that receives the first synchronization signal is configured to responsively send a second synchronization signal to one or more of the plurality of circuits.
A better understanding of the disclosed systems and methods may be obtained in conjunction with the following drawings, in which:
While the invention is susceptible to various modifications and alternative forms, embodiments of the invention are shown by way of examples in the drawings and described herein. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Certain terms are used throughout the following description and claims to refer to particular components and systems. Different companies may refer to components by different names. This document does not intend to distinguish between components and systems that differ in name but not function.
In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to . . . ". Also, the term "couple" or "couples" is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The subject matter herein generally is directed to device architectures that include multiple circuits. When asynchronous links are used to connect the multiple circuits, the disclosed synchronization procedure may be employed to align the circuits, thereby permitting proper operation.
One example of such a device is a network switch with a Central Memory Architecture (CMA). In accordance with various preferred embodiments, CMA switches utilize two types of application specific integrated circuits (ASICs), referred to as "front-end" and "back-end" ASICs. Front-end ASICs may send and receive data packets of variable lengths and may use the back-end ASICs as a routing mechanism. For simplification the back-end ASICs may be considered multi-port random access memories (RAMs).
Each front-end ASIC 118, 120, 122, and 124 in switch 100 may contain external connection hardware, referred to as "external ports". These external ports are the mechanism by which data is sent into and out of the switch. Although the switch architect may employ any number of such ports, in the preferred embodiment eight external ports 125 are coupled to each front-end ASIC in switch 100. In alternative embodiments, the front-end ASICs 118, 120, 122, and 124 may be used solely for manipulation of data that is stored in the back-end ASICs 102, 104, 106, and 108.
When a packet is received on one of the ports 125 from an external device, the packet is transferred over the internal links during an assigned time interval, referred to as a "timeslot". The timeslots facilitate the storing and retrieving of data in a CMA-based switch. Uplink timeslots take data from front-end ASICs and store the data into back-end ASICs, whereas downlink timeslots transfer data from back-end ASICs to front-end ASICs.
Timeslots may be assigned in such a way that no two uplink timeslots associated with any two front-end ASICs can concurrently access the same back-end ASIC. To achieve this alignment, a timeslot table containing the timing information associated with every timeslot in a switch is utilized to assign the timeslots.
In accordance with preferred embodiments, synchronization control logic (not specifically shown) aligns the internal "clocks" associated with each ASIC. Each ASIC preferably receives a clock from a common crystal oscillator. Numerous types of crystal oscillators (e.g. temperature compensating, voltage controlled) may be utilized as the common oscillator. The clocks transition from a high value to a low value and back to a high value in a period of time referred to as a "cycle". The internal clocks associated with each ASIC in switch 100 preferably operate at substantially equal clock rates and thus equal cycle periods. In alternative embodiments, each ASIC receives a clock from one or more phase-locked-loop (PLL) circuits. Each PLL circuit is locked to the same crystal oscillator and thus does not "slip" cycles relative to the other PLL circuits.
Preferably coupled to each clock is a multi-bit register, referred to as a "word counter". Typically, the word counter increments once per cycle based upon input from an associated internal clock. In accordance with preferred embodiments, the word counter associated with each ASIC may be "set" by the synchronization control logic to a value that permits the timeslots of the switch 100 to function properly. The process of setting the word counters of the ASICs by the synchronization control logic may be referred to as "chip-to-chip synchronization". The factors that determine the value to set each word counter are discussed below.
Data sent from one ASIC to another ASIC through an internal link does not arrive at its destination instantaneously. Numerous delays occur when transferring data between the ASICs. These delays may be classified as "deterministic" or "nondeterministic" delays. Deterministic delays are fixed throughout the lifetime of the switch and thus do not vary from reset to reset whereas nondeterministic delays typically vary from reset to reset of a switch. Examples of deterministic delays are discussed after the nondeterministic delays below.
To allow internal links to transfer data in a serial fashion, a serializer-deserializaser (SerDes) device (not specifically shown) may serialize data. Accordingly, two serializers may be included in, or be associated with, each internal link 110, 112, 114, and 116. A first serializer may exist in the back-end ASICs 102-108 associated with a particular internal link and a second serializer may exist in the front-end ASICs 118-124 associated with a particular internal link. When switch 100 is powered off, the states (i.e. positions) of the serializers in the switch 100 may differ. Upon power up, different time intervals are required to initialize the serializer to a common state and carry out serializations of data. These differing time intervals create nondeterministic delays that vary from reset to reset of the switch 100.
As opposed to the varying nature of nondeterministic delays, deterministic delays are fixed delays associated with the data paths in a switch. For example, deterministic delays occur from the pipelining of the detection logic in a CMA-based switch. This detection logic distinguishes the type of data in the data path and controls the low-level operations of the ASICs. For example, a data type referred to as a "write address" has a defined format that the detection logic identifies to determine which low-level operation needs to be preformed. Since the number of pipeline stages utilized in the detection logic is fixed, the delay associated with the detection logic remains constant from reset to reset. In addition, the length of the internal links 110, 112, 114, and 116 may differ depending upon the exact design of the switch 100. The synchronization procedure described herein compensates for any such differences to ensure the proper operation of the switch 100.
In accordance with preferred embodiments, an upper bound to the round-trip latency in a device may be calculated. The upper bound may account for both deterministic and nondeterministic delays and may be referred to as the "synchronization advance time". The calculation of the synchronization advance time is discussed below.
Advance Value=2*D D+3*D N (1)
where DD represents the deterministic delay and DN represents the nondeterministic delay. Since these delays are typically well under one microsecond, the deterministic and nondeterministic delays are preferably measured in clock cycles. The advance value may be determined by the system designer and stored as a constant value in a non-volatile register. The complete derivation of equation (1) is provided in Appendix A.
In accordance with the preferred embodiments, the synchronization advance value is utilized to set the word counters of each front-end ASIC to permit synchronization of the circuits in a CMA-based switch.
Referring to
In accordance with the preferred embodiment, one back-end ASIC 32 or 44 acts as a "master" ASIC. The master ASIC preferably initiates the synchronization process and preferably is selected by asserting a programmable bit in the synchronization control logic associated with the back-end ASIC. The bit may be programmed initially by the switch architect and thereafter programmed by a network administrator. The master ASIC is considered to be "in sync" at all times and thus may never have its word counter set. The disclosed method may synchronize the other ASICs by setting the word counters associated with the other ASICs to a value that enables the proper operation of the switch 30.
For exemplary purposes, back-end ASIC 32 may be designated as the master ASIC in switch 30. Once the bit in the synchronization control logic of back-end ASIC 32 has been set, a synchronization signal referred to as the "master sync" signal may be sent on all downlinks associated with the master ASIC 32. The master sync signal preferably is initiated by the synchronization control logic of the master ASIC when a synchronization event occurs. The synchronization event may include a system reset, a power on procedure, or any other suitable event detected by the synchronization control logic of the master ASIC that requires switch synchronization.
In the exemplary first synchronization stage shown in
When a front-end ASIC receives the master sync signal, the synchronization control logic within each front-end ASIC preferably recognizes the signal and extracts the multi-bit master word counter value. The value is added to the calculated synchronization advance value (CSAV). The calculated synchronization advance value preferably is obtained from equation (11) above and placed into a register (not specifically shown) coupled to the synchronization control logic of each front-end ASIC 56 and 70. Alternatively, the calculated synchronization advance value may be placed into a single register or into non-volatile memory that is accessible by all front-end ASICs.
Each front-end ASIC 56 and 70, upon receiving the master sync signal, may set its respective word counter to the value extracted from the master sync signal plus the calculated synchronization advance value. Accordingly, front-end ASIC 56 extracts the value from the master sync signal and adds to the value the calculated synchronization advance value 66. This sum is then used to set word counter 68. In addition, front-end ASIC 70 extracts the count value from the master sync signal and adds to the value the calculated synchronization advance value 80. This sum is then used to set word counter 82. The word counters 68 and 82 now operate "ahead" of the master word counter.
By way of example, assume the deterministic delay (DD) associated with the switch 30 to be ten cycles and the nondeterministic delay (DN) to be one cycle. Per equation (11), the synchronization advance value of switch 30 is calculated to be 23 cycles. Since the transport latency incurred in the transmission of the master sync signal required 10 cycles for front-end ASIC 56 and 11 cycles for front-end ASIC 70, word counters 68 and 82 operate ahead of the master word counter by 23 cycles−10 cycles=13 cycles and 23 cycles−11 cycles=12 cycles, respectively.
Upon receiving the two slave sync signals, back-end ASIC 44 preferably sets word counter 46 to the value contained in the "latest" slave sync signal received. For example, the slave sync signal from port 76 may arrive later than the slave sync from port 62 since 11 cycles of transport latency are incurred by this slave sync signal. The word counter 46 preferably is set to the value contained in this slave sync signal when the signal arrives from port 76. Thus, the word counter 46 is set to a value one cycle ahead of the master counter 34 in ASIC 32. (Recall that the word counter 82 is running 12 cycles ahead of the master ASIC and the transport latency associated with the slave sync signal is 11 cycles). The master ASIC 32, upon receiving the slave sync signal, does not set associated word counter 34 since the master ASIC 32 is considered "in sync" at all times and has its control bit asserted, indicating that ASIC 32 is assigned the master ASIC in the synchronization process.
When a back-end ASIC receives the slave sync signal, the synchronization control logic recognizes the signal and carries out a procedure that aligns internal ports. This procedure may be referred to as "port-to-port synchronization". Port-to-port synchronization aligns each internal port by adding or subtracting, if necessary, a delay to the FIFO receive buffers of an ASIC that received a slave sync signal. This delay is based upon the value of the word counter associated with an ASIC and the received word counter value in the slave sync signal.
As previously discussed, the word counters 68 and 82 associated with front-end ASICs 56 and 70 operate in advance of the master word counter by 13 and 12 cycles respectively. During port-to-port synchronization, delays are added to FIFO receive buffers 36 and 42 associated with master ASIC 32 to ensure that data sent from a front-end ASIC at a respective word counter value is received by master ASIC 32 at an equivalent word counter value. The synchronization control logic coupled to the master ASIC 32 may detect word counter discrepancies and compensate by adjusting the FIFO receive buffers 36 and 42. In the exemplary case provided, the word counter 68 associated with the front-end ASIC 56 operates 13 cycles ahead of the master ASIC and the transport latency incurred by the slave sync signal from the front-end ASIC 56 to the FIFO receive buffer 36 is 10 cycles. Thus, the slave sync signal is received by FIFO receive buffer 36 at a value of master word counter plus an additional three cycles. Word counter 82 associated with front-end ASIC 70 operates 12 cycles ahead of the master word counter and the transport latency incurred by the slave sync signal from the front-end ASIC 70 to the FIFO receive buffer 42 also is 10 cycles. Therefore, the slave sync signal is received by FIFO receive buffer 42 at a value of master word counter plus an additional two cycles. To compensate for the discrepancy, three cycles of latency are added to the FIFO receive buffer 36 and two cycles of latency are added to FIFO receive buffer 42. Now data sent from either front-end ASIC 56 or 70 emerges from FIFOs 36 and 42 at equivalent word counter values.
With respect to back-end ASIC 44, the slave sync signals received by FIFO receive buffers 48 and 54 from front-end ASICs 56 and 70 arrive with a value of master word counter plus an additional three cycles and master word counter plus an additional one cycle, respectively. Therefore, two cycles of latency may be added to FIFO receive buffer 48 by the synchronization control logic to compensate for the difference with word counter 46, which is running at master word counter plus one cycle. Thus, data sent from the front-end ASIC 56 and 70 may emerge from FIFOs 48 and 54 at equivalent word counter values.
The additional cycles of latency during port-to-port synchronization preferably are incorporated in a FIFO receive buffer by setting one or more control bits in the associated synchronization control logic. The control bits preferably determine the wait time (in cycles) a piece of data is held in the FIFO receive data buffer before being received from the FIFO. The synchronization control logic coupled to an ASIC is responsible for setting the control bits to the appropriate values.
Referring now to
Referring now to
Although specific transport latencies and configurations were given in the exemplary synchronization procedure to facilitate discussion, the disclosed synchronization procedure may similarly operate under different configurations and delays. In particular, a front-end ASIC may be designated as the master ASIC for the purpose of synchronization.
Referring now to
In addition to a system reset and power on procedure, a subset of the disclosed synchronization procedure may be employed when an ASIC is "hot plugged" into the switch 100. Hot plugging refers to the process of adding one or more front-end or back-end ASICs to a device while the device is operating. Thus, the newly added ASICs may need to be synchronized.
In some embodiments, a front-end ASIC may be assigned as the master ASIC. The first synchronization stage may send a master synch from the master front-end ASIC; the second synchronization stage may send a slave sync from one or more back-end ASICs to one or more front-end ASICs; and the third synchronization stage may send a slave sync from one or more front-end ASICs to one or more back-end ASICs.
Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Derivation of Calculated Synchronization Advance Time (Csav) with a back-end ASIC as master.
The master back-end ASIC starts by downlinking the Master Sync (CM) to the slave front-end ASICs. The value received on the downlinks of each front-end ASIC (CFd_master) is found by subtracting the transport latency from the master front-end ASIC. Therefore,
C Fd
C Fd
Where Dd is the deterministic delay and Dn is the variable (i.e., nondetermisitic) delay. The downlink side of a front-end ASIC operates the farthest behind in the system. This is because the front-end downlink is at the end of the round-trip path where the front-end ASIC addresses the back-end ASICs via an uplink, and then a back-end ASIC returns the data on the downlink to a front-end ASIC. Since the front-end ASICs are getting their time reference via the downlink from the master back-end ASIC, this time is the farthest behind in the system. Therefore, in order to set a front-end ASIC's word counter, the worst case round-trip latency (Csav) must be added to the received downlink value (CFd
C SFu
C SFu
The slave front-end ASICs uplink their counters (CSFu) to the Slave back-end ASICs. Each slave back-end ASIC will set its counter from the latest (minimum) count received on the uplink from a slave front-end ASIC. This count is then sent down the downlink. Thus, the slave back-end ASICs' count value (CSBd) is the uplink count sent from the slave front-end ASIC (CSFu) with a transport delay subtracted.
C SBd
C SBd
In operation, each slave back-end ASIC will do port-to-port matching in order to set its counter value for downlink. To do this, it finds the latest port (the minimum) and delays the rest of the ports until they match the latest. However, we cannot assume the variable delay has been in every (or any) link at this point. Therefore, it is entirely possible that the latest value received by the slave front-end ASIC has no non-deterministic delay (Dn).
The slave front-end ASICs are now receiving the slave sync sequence sent from the slave back-end ASICs. This received sequence (CSFd) is the same as what was sent from the slave back-end with one transport latency subtracted from it.
C SFd
C SFd
The slave front-end ASICs are now getting Slave Sync from the first and last level of synchronization. In other words, the master back-end ASIC is the first chip to be in time. The front-end ASICs are the second to get in time. The slave back-end ASICs are the last to get time information. Each hop in synchronization inserts the possibility of variation from the source to destination. The front-end ASICs have the visibility of the worst possible delay (from a slave back-end ASIC) and the least possible delay (from the master ASIC). If we compare these two, we can find the Synchronization Advance Value. The latest (smallest) value is CFd
C M +C sav−3D d−3D n >=C M −D d (A10)
C sav>=2D d+3D n (A11)
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|Citing Patent
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|Mentor Graphics (Holdings) Ltd.
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|U.S. Classification
|370/350, 370/510, 398/129, 375/365, 398/53, 370/519, 375/371
|International Classification
|Cooperative Classification
|European Classification
|Mar 29, 2004
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Couple Gets Engaged at Machine Head Show as Robb Flynn Delivers Vulgar Vows
A happy couple of Machine Head fans are now engaged after Robb Flynn invited them up onstage at a show in Minot, N.D. to make it official.
A happy couple of Machine Head fans are now engaged after Robb Flynn invited them up onstage at a show in Minot, N.D. to make it official.
Machine Head and their former bassist Adam Duce have settled their legal differences out of court.
The past weekend marked yet another annual Record Store Day! The April 19 celebration brought vinyl lovers to record stores nationwide, where Machine Head's 'Killers & Kings' 10" was available for the first time. Now that Record Store Day has passed, Machine Head have shared the new demo for your digital listening pleasure.
Machine Head are inching closer to a new record, and we just got another indication of that as the band has booked an 11-date trek for this summer. In a new posting, the group states that the 'Killers & Kings Tour' will serve as a "primer" for a larger trek to follow.
Machine Head are seeking to end the legal mudslinging that has surrounded the band since former bassist Adam Duce brought a lawsuit against them. The suit made claims of copyright infringement, breach of partnership and mismanagement of funds, among other things.
The lineup for the sixth annual Scion Rock Fest has been unveiled. Among the 25 plus bands playing are headliners Machine Head and High on Fire along with Red Fang and Crowbar. The free event will be held at multiple venues in Pomona, Calif. on May 17.
Machine Head are making progress on their new record and would like to share some new music sooner than later. As such, they're giving fans a glimpse inside the studio in what will be a series of production blog videos and arranging for a special Record Store Day release.
Machine Head are making strides toward a new album, but as frontman Robb Flynn reveals in a new "General's Journals" posting, things are moving forward at a "slow and steady" pace. However, the progress is coming along well enough for Flynn to divulge the current titles of a few songs that may make the next disc.
On Feb. 11, 2013, Machine Head fired bassist Adam Duce after over 20 years of playing music together. Very little has been heard from Duce since, but news just broke that the former Machine Head bassist is suing the band, all three current members and the group's manager for alleged trademark infringement, breach of partnership agreement, defamation + more.
Machine Head frontman Robb Flynn and Spiralarms/Forbidden guitarist Craig Locicero have put together an all-star tribute band that will perform classic Black Sabbath songs at an upcoming benefit concert. The show will be Jan. 17 at the Oakland Metro Operahouse in Oakland, Calif.
Machine Head frontman Robb Flynn just typed up another post for his always entertaining 'The General Journals: Diary of a Frontman… And Other Ramblings' blog. This edition celebrates the 10th anniversary of the band's album 'Through the Ashes of Empires,' nearly becoming the singer of Drowning Pool and much, much more.
Avenged Sevenfold released their sixth studio album, 'Hail to the King,' on Aug. 23. Although the act's fans have been eating up the album, Avenged Sevenfold have been met by various detractors as well, including Machine Head frontman Robb Flynn. Avenged Sevenfold singer M. Shadows responded to Flynn's criticism a short while ago, and now, guitarist Zacky Vengeance has done the same.


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"You can't just do whatever"
The words stumbled out of you
Like a drunk leaving a bar looking for a fresh new last call
You were not a man of words
But did your best to offer advice
You offered me "You can't just do whatever"
And I know what you meant
You meant that whatever I choose to do, I must not be aimless
I must not simply spin this globe and go wherever I stick my finger
Because 71% of the time I will end up in the ocean
And if I do end up in the ocean I can't just do whatever,
Better learn to swim
"You can't just do whatever"
The conversation came after you asked me about heaven
Told me that you thought heaven would be specific to each person
And that each person would have their own version of it
Then asked me what mine would be
I was so scared to tell you,
"I don't have one"
But you nodded your head,
as if confirming a suspicion that school
had robbed me of a belief in some stories
You said "you don't have to beleive what I believe, its enough to be good.
Be good"
I will.
I will think about your heaven
Your heaven would be the same haircut, forever
It would be a stick a dog and some distance
A lawn that always needs mowing
A six-pack of pills in those short bottles and your real teeth back
Because your dentures could never master that bottle opening trick you loved to do
The first time you tried it with dentures I had nightmares for a month
Because I though your mouth had fallen off
Your heaven, would be Austria before the war
And Canada after you met grandma
It would be head cheese sandwiches and blood sausages
Other deli meats that would ensure you would never ever have to entertain dinner guests
And I would never be in danger of having my lunch stolen
Your heaven,
would be a stash of raisins
Problems that you could fix with your hands
I remember you tried to fix everything with your hands
I remember the difficult days
I remember the bandages
They looked like tiny blankets, as if your knuckles had all gone off to bed
Walls that looked like they'd said something to get under your skin
And where suddenly made to pay for it
I know you were an angry man
Finger tips like spent shotgun shells, bleeding smoke cocktails of gunpowder and singed plastic
You had what some people would call, "a temper"
But you loved a good joke,
even if it was on you
Something that would crack open the walls of your chest and let the wind tickle your heart
Just enough to let you know it was still there
You didn't always laugh, didn't always smile
You did keep a mental ledger of what you called your "send flowers list"
I remember thinking it was a thank you to those who got you good
But learned the truth after my grandmother added a thin layer of sand to your sandwiches
Because you refused to make your own lunch for work
You told me about it when you picked me up from school that day
You said "Grandma just made the send flowers list"
And I asked "Because you love her so much?"
And you said "Because I'm gonna kill her"
Of course you didn't
Your version of kill meant two months before winter,
Having a seamstress take in each of her coats a few inches
So on the first day she need one
She fumbled with the sudden tightness
And you stood there smiling then said "Honey, I love you no matter how big you get"
She did not laugh
And managed to staple your smile back into a straight face
When she told all of your friends at work that you had to move into the spare room
Because you couldn't stop farting at night
You often asked me "If I had a heaven, what would it be like?"
And I told you that for such a small word, if, is just too big to wrap my belief around
I would not bend to the hypothetical
But wish now that I would've
Even if it was just to ease your mind in the belief
That I could be headed to that other place you believed in
I would tell you now how my heaven is here
It was here, in the gentle warfare of your relationship with Grandma
Where volleys were traded back and forth
Like hockey cards between children who didn't care what the stats meant
My heaven would have been someone in grade five finally willing to trade me their fruit roll up
For my tin of sardines
My hell was wondering "why?" Why would you give me sardines for lunch
My heaven would make you laugh
Cause I get the feeling you didn't get to do that very much
Through my hell, through the night terrors and bloody noses
Through the eyes black, bruised back, sneak attack, nap sack and winter coat hijacks
You did your best to seal up the cracks in my armour and made my heaven here
I would have loved to have made you laugh more
To make your send flowers list just once
So I offer you now my if
If there is a heaven
Mine would have a post office
And I could send letters to yours
The first letter would read
"Hell's not so bad, they pretty much let you do whatever"
- The term 'heaven' is common. What does it mean to you?
- What do you think the poem is/was going to be about – based on the title?
- List the Shane Koyczan's poems you remember watching/reading so far. What do they have in common?
- How would you describe his writing style?
- Why might Shane write a poem about and to his grandfather?
- What would it be like, for you, if you had to go and live with your grandparents until your graduation from grade12?
- The video opens with a wide screen – with Shane Koyczan sitting on a park bench – tearing a page of writing from a book and making it into a paper airplane. The video then cuts to a drunk vomiting in the street. What are your thoughts on the opening visuals?
- Shane offers this simile "The words stumbled out of you
Like a drunk leaving a bar looking for a fresh new last call"
Explain the comparison – how could words stumble like a drunk?
- If heaven is a perfect place – Shane talks about his grandfather's version of heaven.
eg.Your heaven, would be Austria before the war
And Canada after you met grandma
It would be head cheese sandwiches and blood sausages
List the things that would be in Shane grandfather's heaven.(at least 5 items)
- What evidence is there that his grandfather had a temper?
- What evidence is there that his grandfather had a sense of humor?
- Explain his grandfather's 'send flowers list'?
- Discuss this line "My heaven would make you laugh
Cause I get the feeling you didn't get to do that very much"
- Shane Koyczan has noted that 'Heaven, or Whatever' is a thank you to his grandparents. Why is he so thankful to them?
Write a letter to one of your grandparents letting them know what you are thankful to them for. Think about their strengths, weaknesses and love they have/had for you. Think about the times you spent with them. Think about the experiences and places you shared.
Heaven, or Whatever


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- Bad lands
- Bad lands Bad" lands" Barren regions, especially in the western United States, where horizontal strata (Tertiary deposits) have been often eroded into fantastic forms, and much intersected by ca[~n]ons, and where lack of wood, water, and forage increases the difficulty of traversing the country, whence the name, first given by the Canadian French, Mauvaises Terres (bad lands). [1913 Webster]
The Collaborative International Dictionary of English. 2000.


text: Design of IOIM for VME bus based CPU using CPLD for nuclear power plantsS. Raveendran, P. Talwai, T. Khan, R. Balasubramanian, K. AgilandaeswariICWET2010In a nuclear reactor or process control systems it is required to continuously measure the signals from sensors and transmitters placed at various locations in the field. Accurate measurement of these signal parameters is essential to carry out the control operations effectively. The measured parameters have to be sent to the processor for necessary action.… (More)


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Disclaimer: I'm not in any way suggesting that Nokia is responsible for the comments listed below. They may have been made by an outside agency, well meaning loyal customer or even a competitor trying to sabotage them. This post is intended to present a collection of blog comments referencing the Nokia URL and discuss the issues involved.
Today I was moderating some comments on my mobile phone blog and spotted 3 comments from the same IP address of 188.8.131.52. All the comments were under different names but two had the same email address.
All three of them were promoting http://shop.nokia.co.uk and using the sort of language that kids use when they leave comments on YouTube.
A spam blog comment in my opinion is where a company enters a comment for the sole purpose of promoting a commercial service. When a company does this multiple times without disclosure and without using real full names one might assume they are trying to falsely represent themselves as consumers – something that is illegal under the UK Consumer Protection from Unfair Trading Regulations 2008 laws.
To be clear – as a blog owner I'm quite happy for companies to leave the occasional comment linking to their own products as long as they are upfront and honest about it. What bloggers don't like is companies leaving comments under false names pretending to be a consumer to disguise the fact they are promoting something. This is unethical and according to the OFT may be illegal too.
To see if any other blogs had received similar comments I did a quick search on Google and found the following. Click the images to see the live blog posts.
Symbian Guru
Esato, Daphne joined and made 2 posts. Both about Nokia.