text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 8, 1983
|Filing date
|Feb 23, 1981
|Priority date
|Feb 23, 1981
|Fee status
|Also published as
|Publication number
|Edward H. Greenwood
|Original Assignee
|Genrad, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (4), Referenced by (22), Classifications (11), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Field of the Invention
The invention relates to circuitry to testers for testing digital circuits and isolating faults therein.
2. Description of the Prior Art:
U.S. Pat. No. 4,194,113 describes in detail a system for testing digital circuits and isolating faults therein using a "guided probe" approach. As testers in which the described system is embodied have become increasingly popular, it has become desirable to implement lower cost versions of such testers, referred to herein as "field maintenance processors". A field maintenance processor includes a general purpose microcomputer which can implement the guided probe testing operations and can also be used for various other purposes. However, interfacing a general purpose microcomputer to a wide variety of digital systems which need to be "field tested" requires construction of suitable, "custom designed" circuits referred to as "device specific adaptors" to facilitate connection of the digital circuits under test to the field maintenance processor. A digital circuit under test may be a complex, computer-based product which can "take control" of an internal data bus and/or address bus of the field maintenance processor. The device specific adaptors need to have "pluggable connectors" which facilitate physical connection of device specific adaptors to the field maintenance processor.
If the device specific adaptor takes control of the "intenal field maintenance processor (FMP) bus", it is necessary that this be done in such a way as to avoid any loss of information stored in the dynamic memory of the field maintenance processor.
Accordingly, it is an object of the invention to provide a system and method for avoiding the effects of undetected loss of information in a field maintenance processor when a device specific adaptor connected thereto takes control of a bus in the field maintenance processor.
It is very important to the manufacturer of a field maintenance processor that it have extremely high operating reliability, so that users of the field maintenance processor will never have any reason to doubt the results of a particular test. However, buyers of field maintenance processors frequently will design their own device specific adaptors for interfacing between their products to be "field tested" and the field maintenance processor. It is expected that circuit designers who "custom design" their own device specific adaptors will occasionally ignore various timing specifications (which usually are quite conservative) of the field maintenance processor. In the event that a "customer designed" device specific adaptor asserts control over the FMP bus for too long a period of time, this may result in unexplained malfunctions resulting from loss of data stored in the dynamic memory of the field maintenance processor because of the inability of the field maintenance processor to quickly refresh dynamic memories while the device specific adaptor is in control of the internal FMP bus.
Therefore, it is another object of the invention to provide a system and method for preventing a device specific adaptor from taking control of an internal bus of the field maintenance processor for a time period that is so long that the integrity of data stored in dynamic random access memories contained in the field maintenance processor is jeopardized.
Briefly described, and in accordance with one embodiment thereof, the invention provides a system including a processor which automatically effects transparent refreshing operations on a dynamic random access memory during execution of program instructions and circuitry for generating a "wait" signal when a memory location having a slow excess time is accessed by the processor, and circuitry for generating a "wait enable" signal that is logically ANDed with the "wait" signal to produce an "enabled wait" signal applied to the "wait" input of the processor in order to ensure that the transparent refreshing operation does not fail to refresh any portion of the dynamic random access memory as a result of the "wait" signal having a duration which is too great. In the described embodiment of the invention, the circuitry includes a wait counter circuit having clear, load, and enable inputs and a carry output. A "wait enable" signal is produced in response to the carry output of the wait counter circuit. When the carry signal is "inactive", the "wait enable" signal is "active", enabling the "enabled wait" signal to be produced during accessing of the slow memory. This halts execution of an instruction by the microprocessor during accessing of the slow memory. Termination of the "wait" signal (when the accessing is complete) results in reloading an initial count in the wait counter. The wait counter does not begin counting until the "wait" signal again becomes active. If the carry output of the wait counter circuit becomes "active", the "enabled wait" signal becomes inactive, and an interrupt signal is generated that interrupts the microprocessor, causing it to execute an error routine which both causes refreshing of the entire dynamic random access memory and also alerts an operator by producing information indicating aborting (by the processor) of the instruction halted in response to the "wait" signal. During execution of the interrupt routine, the processor sends a signal to the "wait" counter circuit, thereby "clearing" it.
FIG. 1A is a perspective view illustrating the field maintenance processor of the present invention.
FIG. 1B is a block diagram useful in explaining operation of the field maintenance processor of FIG. 1A.
FIG. 1C is a block diagram illustrating a portion of the circuitry of the field maintenance processor of FIGS. 1A and 1B.
FIG. 2 is a schematic diagram illustrating buffer circuitry for a bus request conductor used in the system of FIGS. 1A and 1B.
FIG. 3 is a flow chart of an interrupt routine executed by the microprocessor of FIG. 1C in response to a wait signal generated by a device specific adaptor.
FIG. 4A is a timing diagram useful in explaining the operation of the microprocessor of the circuit of FIG. 1C.
FIG. 4B in another timing diagram useful in explaining the operation of the microprocessor of the circuit of FIG. 1C.
FIG. 4C is another timing diagram useful in explaining the operation of the microprocessor of the circuit of FIG. 1C.
Referring now to FIG. 1A, reference numeral 1 designates a field maintenance processor (FMP) which can be used to implement the guided probe fault isolation techniques referred to in U.S. Pat. No. 4,194,113, incorporated herein by reference, for field testing of complex digital electronic products.
As shown in FIG. 1A field maintenance processor 1 includes a cavity 2, referred to as a DSA (device specific adaptor) cavity into which up to four device specific adaptor (DSA) modules can be plugged in order to "interface" between a product under test (PUT) and field maintenance processor 1. A connector (not shown in FIG. 1A) referred to herein as a DSA connector is located in the deepest portion of DSA cavity 2 for receiving edge connectors of printed circuit cards of the above-mentioned device specific adaptors.
Referring to FIG. 1B, reference numeral 1 designates the above mentioned field maintenance processor, and reference numeral 2 designates the above-mentioned DSA cavity of field maintenance processor 1. Reference numeral 10 designates the above-mentioned DSA connector. DSA connector 10 is connected to edge connector "terminal strips" of as many as four device specific adaptors which can be plugged therein. The respective DSA connector terminal strips are also connected to corresponding conductors of a bus referred to as DSA bus 11-13'. DSA bus 11-13' is connected to corresponding terminals of bi-directional buffer circuit 29, which can be readily implemented by means of 74LS245 integrated circuit bus transceivers. The corresponding terminals of DSA buffers 29 are connected to corresponding terminals of an "internal" bus 11-13 occasionally referred to herein as the "Z80 bus". Internal bus 11-13 includes both bi-directional address bus lines and bi-directional data bus lines.
In FIG. 1B, reference numeral 16 designates a product under test (PUT) by field maintenance processor 1. Typically, product under test 16 may include circuits, such as a processor and direct memory address (DMA) circuit, both of which are capable of taking control of the Z80 bus. Product under test 16 is coupled to device specific adaptor 30' by means of a "user bus" 18 that conducts various signals between device specific adaptors 30' and product under test 16. A product interface module (PIM) may, if necessary, be connected between user bus 18 and product under test 16. (For example, it may be desirable for the user to design a particular device specific adaptor or group thereof to interface between field maintenance processor 1 and an entire "family" of related products, each of which is different, and requires somewhat different interfacing to the subject device specific adaptor. In this case, it is convenient to devise a number of different PIM's to interface between the user bus 18 and the various products of the product family.)
In use, field maintenance processor 1 enables a user to design a device specific adaptor (such as 30') that interfaces between user bus 18 and digital product under test (PUT) 16, which is to be tested using the guided probe or other suitable testing algorithm stored in the memory of field maintenance processor 1. For further details on an algorithm that can be stored and executed by field maintenance processor 1, see U.S. Pat. No. 4,194,191 issued Mar. 18, 1980 by Fulks et al. and U.S. Pat. No. 4,174,805 issued Nov. 20, 1979 by Fulks et al., both of the foregoing patents being incorporated herein by reference.
It can be seen that the function of device specific adaptor circuit 30' is to function as a "personality circuit" which performs the necessary operations on signals received from DSA bus 11-13' and transmitted to user bus 18, and vice-versa, to allow information to be transmitted back and forth between field maintenance processor 1 and product.
Referring now to FIG. 1C, field maintenance processor 1 includes a microprocessor 3, which may be implemented by means of a Z80 integrated circuit 8 bit microprocessor. The part number of a version of microprocessor 3 manufactured by Mostek, Inc. is the MK3380-4 N-Channel 8 bit microprocessor. Field maintenance processor 1 also includes a direct memory addressing (DMA) circuit 5, which may be implemented by means of Mostek MK3883-4 DMA integrated circuit. Field maintenance processor 1 also includes an approximately 128 kilobyte dynamic memory 7, which can be implemented by means of a plurality of Mostek MK4116 MOS dynamic RAM integrated circuits. Field maintenance processor 1 further includes a parallel input/output (PIO) circuit 9, which may be implemented by means of a Mostek MK3881-4 integrated PIO circuit.
A 16 line address bus 13 is connected to the address output ports of microprocessor 3, DMA circuit 5 and also to the address input ports of dynamic memory 7. Each conductor of bi-directional eight bit data bus 11 is is connected to respective corresponding ones of eight data terminals of microprocessor 3, DMA circuit 5, dynamic memory 7, and PIO circuit 9. An interrupt request line 15 is connected to the IRQ input of microprocessor 3 and the IRQ output of PIO circuit 9.
A "wait" conductor 19 is connected to the WAIT input terminals of microprocessor 3 and DMA circuit 5, respectively. The eight conductors of bi-directional data bus 11 are connected to corresponding terminals of bi-directional buffer circuits 29A, which can be implemented by means of 74LS245 Bus transceiver integrated circuits, manufactured by Texas Instruments and others. The individual bi-directional buffer circuits have terminals connected to corresponding lines of DSA data bus 11'. Similarly, the conductors of address bus 13 are coupled by means of bi-directional buffer circuits, collectively designated by reference numeral 29B, to corresponding conductors of DSA address bus 13'. It should be noted that all connections between field maintenance processor 1 and device specific adaptor 30 are made by means of the above-mentioned DSA connector, designated by reference numeral 10 in FIG. 1B, and also incorporated in blocks 29A-C of FIG. 1C. The letters "DSA" are added to the name of each conductor on the "device specific adaptor side" of the DSA buffers and connectors 29A, 29B and 29C.
Still referring to FIG. 1C, device specific adaptor 30 includes an address decoder 31. Address decoder 31 can be implemented easily by any suitable decode circuit, such as a PAL16L4 programmable array logic integrated circuit manufactured by Monolithic Memories, Inc. Block 31' of address decoder 31 contains a timer circuit (not shown, but easily implementable by those skilled in the art) for generating a DSA WAIT signal on conductor 28C. If the storage location being accessed by microprocessor 3 has an access time of more than 250 nanoseconds, timer circuit 31' must generate the DSA WAIT signal, which is inverted by inverter circuit 28B to produce a DSA WAIT signal on conductor 28A. A wide variety of suitable timer circuits can be easily used by one skilled in the art to sense the beginning of a fetch cycle (by detecting a transition of conductors of DSA address bus 13' and generating the DSA WAIT signal if the access time of the accessed storage location is greater than, for example, 250 nanoseconds), as required by the MK3380-4 microprocessor mentioned above.
In accordance with the invention, a wait counter 20 and associated circuitry are provided in field maintanence processor 1 to respond to any DSA WAIT signal that is received from device specific adaptor 30, by beginning timing of the duration of the DSA WAIT signal and generating a WAIT ENABLE signal on conductor 25. This WAIT ENABLE signal is utilized to generate the wait signals applied by means of conductor 19 to the WAIT inputs of microprocessor 3 and DMA circuit 5.
Wait counter 20 can be implemented by means of a 74LS161 loadable counter, which is manufactured by various semiconductor manufacturers. Wait counter 20 includes four "load" inputs labeled, A,B,C, and D. Load inputs C and D are connected to the positive supply to produce logical "ones" thereon, and load input B is connected to ground to produce a logical "zero" thereon. Load input A is connected to an "input/output request" conductor 20A, which conducts an I/O request signal generated by microprocessor 3.
As is known by those skilled in the art, the Z80 microprocessor addresses input/output ports separately from memory locations, and applies a low level to conductor 20A when a I/O request is being made and a high level when a memory request is being made. This causes either a "zero" or a "one" to be loaded into the least significant bit of wait counter 20, depending upon whether it is a memory cycle or an I/O cycle that is being executed. This information is needed (since the delay times are different for memory and I/O cycles) to preload corresponding starting counts into wait counter 20.
A "CLEAR" input of wait counter 20 is connected by means of conductor 21 and inverter 21A to a port bit A5 of PIO circuit 9; port bit 5A is programmed as an output.
A "LOAD" input of wait counter 20 is connected to conductor 23A, which is connected to the output of OR gate 23. A low level on conductor 23A causes the logic levels of inputs A, B, C and D to be loaded into wait counter 20 and inhibits counting as long as conductors 23A is low.
One input of OR gate 23 is connected to conductor 22, which is connected to the port bit A6 (which is programmed as an input) of PIO circuit 9. Conductor 22 is also connected to the "CARRY" output of wait counter 20, which generates a high logic level on conductor 22 when the logical state 1111 is attained by wait counter 20 (as it is incremented). Conductor 22 is connected to the input of inverter 24, the output of which is connected to conductor 25. The signal produced on conductor 25 is referred to as the "WAIT ENABLE" signal. Conductor 25 applies the WAIT ENABLE signal to the "ENABLE" input of wait counter 20 and also to one input of two input AND gate 26A.
A second input of OR gate 23 is connected to the output of an inverter contained in block 29D. The input of that inverter is connected to conductor 28A, which conducts the above-mentioned DSA WAIT signal produced by device specific adaptor 30 if an access is being made by field maintenance processor 1 to a slow memory 34 (such as a memory of a floppy disk controller).
The signal on conductor 23B is referred to as the "BUFFERED DSA WAIT" signal. That signal is applied to the other input of OR gate 23. The output of AND gate 26A is applied to one input of NOR gate 26B, the output of which is connected to WAIT conductor 19. WAIT conductor 19 is connected to the WAIT inputs of microprocessor 3 and DMA circuit 5. (The other input of NOR gate 26B is connected to circuitry, which is irrelevant to the wait enable counter 20 and circuitry associated therewith and therefore is not shown in FIG. 1C). The DSA WAIT signal on conductor 28A is inverted by one of inverters 29D and the result is ANDed with the WAIT ENABLE signal on conductor 25 by AND gate 26A and inverted by NOR gate 26B to produce an ENABLED WAIT signal on conductor 19.
Before describing the operation of the circuitry of FIG. 1C in detail, certain aspects of the operation of the Z80 microprocessor 3 should be understood.
The Z80 microprocessor executes instructions by stepping through a few basic operations including memory read or write, I/O device read or write, and interrupt acknowledge operations. All such instructions are merely a series of these basic operations. Each of the basic operations can take from there to six clock periods to complete or they can be lengthened to synchronize the microprocessor to the speed of external devices accessed by microprocessor 3. The basic clock periods are referred to as "T states" and the basic operations are referred to as "M (machine) cycles". A typical instruction will be merely a series of specific M and T cycles. For example, an instruction may consist of three machine cycles (M1, M2 and M3). The first machine cycle of any instruction is a fetch cycle which is four, five or six "T states" long (unless lengthened by the wait signal). The fetch cycle M1 is used to fetch the OP code of the next instruction to be executed. Subsequent machine cycles move data between the micrprocessor and memory or I/O devices and they may have anywhere from three to five T cycles. (Again they may be lengthened by wait states to synchronize the external devices to the microprocessor.)
FIG. 4A shows the timing during an M1 cycle (OP code fetch). The program counter contents are placed on the address bus at the beginning of the M1 cycle. One-half clock time later the MREQ signal goes active (i.e., low). At this time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories. The RD line also goes active to indicate that the memory read data should be enabled onto the data bus. The microprocessor samples the data from the memory on the data bus with the rising edge of the clock of state T3 and this same edge is used by the microprocessor to turn off the RD and MREQ signals. Thus, the data has already been sampled by the microprocessor before the RD signal becomes inactive.
Clock states T3 and T4 of a fetch cycle are used to refresh dynamic memories. The microprocessor uses this time to decode and execute the fetched instruction, so no other operation could be performed at this time anyway. During T3 and T4 the lower bits of the address bus contain a memory refresh address and the RFSH signal becomes active to indicate that a refresh read of all dynamic memories should be accomplished. Notice that a RD signal is not generated during refresh time to prevent data from different memory segments from being gated onto the data bus. The MREQ signal during refresh time should be used to perform a refresh read of all memory elements. The refresh signal can not be used by itself since the refresh address is only guaranteed to be stable during MREQ time.
Thus, it is seen that the Z80 generates "transparent" memory refresh signals during the T3 and T4 time slots of an M1 (op code fetch) cycle. Consequently, the Z80 microprocessor can be utilized in conjunction with dynamic memories without the requirement of providing additional hardware and software dedicated to keeping the dynamic memories refreshed. This reduces system complexity and cost.
FIG. 4B illustrates how the fetch cycle is delayed if the memory activates that WAIT line (by bringing it low). During T2 and every subsequent state Tw, the microprocessor samples the WAIT line with the falling edge of φ. If the WAIT line is active at this time, another wait state will be entered during the following cycle. Using this technique the read cycle can be lengthened to match the access time of any type of memory device.
It should be noted that when the wait signal is low on the Z80, the Z80 is incapable of responding to interrupts or "releasing" the bus for DMA control. The effect of the wait line being active during T2 is that the entire Z80 microprocessor is "frozen" until the next T period.
FIG. 4C illustrates the timing of memory read or write cycles other than an OP fetch (M1 cycle). The cycles are generally three clock periods long unless wait states are required by the memory via the WAIT signal. The MREQ signal and the RD signal are used the same as in the fetch cycle. In the case of a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is stable so that it can be used directly as a read/write pulse to virtually any type of semiconductor memory. The WR signal goes inactive of a half T state before the address and data bus contents are changed so that the overlap requirements for most semiconductor memory devices will be met.
Note that fetched data must be available on the Z80 microprocessor data bus by the T3 time frame of a memory read cycle. During time frames T3 and T4 the Z80 is simultaneously decoding the fetched op code and generating the refresh addresses and refresh signal. Note that if the fetched data will not be available on the data bus by T3, it is necessary for the memory to generate a WAIT cycle to lengthen the memory read cycle until the fetched data is available on the data bus.
FIG. 4C also illustrates how a WAIT request signal will lengthen any memory read or write operation. This lengthening is identical to that previously described for a fetch cycle. (Notice in this fiqure that a separate read and a separate write cycle are shown in the same figure, although read and write cycles can never occur simultaneously).
To summarize the foregoing, the Z80 microprocessor 3 has the capability of providing a "transparent refresh" operation for refreshing dynamic memory 7. If product under test 16 (FIG. 1B) has a memory which is sufficiently slow that, under worst case conditions, the transparent refresh capability of microprocessor 3 will fail to result in complete refreshing of dynamic memory 7 within a specified time, memory information stored in dynamic memory 7 will be lost. If microprocessor 3 executes a fetch cycle, it must receive the fetched data within a certain time. Otherwise, microprocessor 3 will not be able to properly accept the fetched data. For the MK3880-4, the fetched data must be available on Z80 bus 11-13 (FIG. 1B) within 250 nanoseconds after the beginning of the fetch cycle.
Since the information storage registers or other storage devices in device specific adaptor 30' or in product 16 frequency have access times which may be greater than 250 nanoseconds, it is necessary that device specific adaptor 30 automatically generate a "wait" signal to stop microprocessor 3 any time microprocessor 3 accesses a slow (greater than 250 nanoseconds) memory location of device specific adaptor 30. The DSA WAIT signal on conductor 28A of FIG. 1C is such a signal.
The above-mentioned "wait" signal then is used to temporarily "freeze" microprocessor 3 until the data being fetched from the slow memory appears on Z80 bus 11-13. Microprocessor 3 then continues execution of the current read or write cycle.
The operation of wait counter 20 (and its associated circuitry) in conjunction with slow memory 34 (FIG. 1C) in the system shown in FIG. 1C will now be described. For purposes of illustration, it will be assumed that microprocessor 3 accesses slow memory 34 of device specific adaptor 30, and that memory 34 is too slow to have the fetched data available on data bus 11 by T3 of the memory read cycle. Circuit 31' therefore generates a DSA WAIT signal on conductor 28A, causing it to go to a low level i.e., to become "active". This causes a BUFFERED DSA WAIT signal on conductor 23B to go to a high level. The output 23A of OR gate 23 then is forced to a high level.
This causes wait counter 20 to begin incrementing from the pre-load initial state specified by the A, B, C and D inputs until (a) wait counter 20 contains all "ones" (at which time the CARRY output goes to a high level), forcing a high level on conductor 22, or (b) the DSA WAIT signal on conductor 28A goes to a high level (i.e., becomes inactive). Wait counter 20 becomes "locked" into a non-counting mode as soon as its CARRY output goes high.
If the DSA WAIT signal on conductor 28A goes high before a CARRY signal is generated by wait counter 20, the BUFFERED DSA WAIT signal on conductor 23B goes low, and the LOAD signal on conductor 23A goes low, reloading the initial state specified by inputs A, B, C and D into wait counter 20. Wait counter 20 remains in this state until the LOAD signal on conductor 23A goes high again. The high DSA WAIT signal on conductor 28A also causes a low level to be produced on conductor 23D. This causes an ENABLED WAIT signal on conductor 19 to go from a low level (active) to a high level (inactive), enabling microprocessor 3 to continue executing the present cycle, which was temporarily halted when the ENABLED WAIT signal on conductor 19 went to a low (active) level.
If the CARRY signal on conductor 22 is forced high because wait counter 20 "times out" (i.e., contains all "ones"), then the LOAD signal on conductor 23A remains high, and the WAIT ENABLE signal on conductor 25 goes low, disabling wait counter 20 from further counting. The high CARRY signal on conductor 22 also produces a "one" at the A6 input of PIO circuit 9. PIO circuit 9 is programmed to responds to the "one" as the A6 input by producing a low signal on the IRQ conductor 15, thereby interrupting processor 3. The low WAIT ENABLE signal on conductor 25 also causes the ENABLED WAIT signal on conductor 19 to go from a low (active) level to a high (inactive) level, allowing microprocessor 3 to execute a "wait interrupt" routine in response to the above-mentioned interrupt signal on conductor 15.
In the case of executing the "wait interrupt" routine, microprocessor 3 transmits information to PIO circuit 9, causing it to produce a high level on its A5 terminal. This produces a low pulse on conductor 21, which clears wait counter 20. This causes the high CARRY level on conductor 22 to fall to a low level. The low level on conductor 22 is applied to an input of OR gate 23, causing a low level to be produced on conductor 23A. This loads the initial value presently specified by the A,B,C and D inputs of wait counter 20. Thus, wait counter 20 is in effect, "reset" and is now ready to respond in the manner described above to another DSA WAIT signal generated by device specific adaptor 30.
The effect of the above described operation is to cause an abort operation by microprocessor 3 if device specific adaptor 30 attempts to generate a DSA WAIT signal which is to long to allow refreshing of the entire dynamic memory 7 within a predetermined time under worst case conditions.
This will be understood after the wait interrupt routine executed by microprocessor 3 is described. It should be noted that in the course of executing the wait interrupt routine, enough memory cycles are executed by microprocessor 3 to cause generation of the 128 transparent refresh read cycles necessary to refresh the entire dynamic memory 3 in substantially less than the 2 millisecond specification of the dynamic random access memory chips of which dynamic memory 7 is composed.
The interrupt subroutine that is generated in response to a positive transition of the CARRY signal produced by wait counter 20 is shown in FIG. 3, and is entered via label 101. First, the program saves the contents of the various working registers and flag registers of the microprocessor 3 in dynamic memory 7. (This is an entirely conventional step which is always performed by a processor at the beginning of any interrupt routine. Therefore, the detailed steps of the "save" operation are not set forth in detail.)
Then the program enters decision block 103 and determines if the interrupt which generated the vector is a "wait" interrupt or some other type of interrupt. If it is some other type of interrupt, the program goes to block 104 and executes an interrupt routine corresponding to the "other" type of interrupt. (Note that decision block 103 is necessary only if the system has two different types of interrupts which generate the same interrupt vector.)
In block 105, the program causes microprocessor 3 to cause PIO circuit 9 to generate a "reset" signal on the A5 output of PIO circuit 9 in order to clear (i.e., reset) wait counter 20. This causes the CARRY output of the wait counter 20 to generate a "low" logic level which is inverted by inverter 24 to produce the WAIT ENABLE signal. This enables wait counter 20 to be "loaded" to the initial state (1100 or 1101) determined by I/O request line 20A and to begin counting as soon as a BUFFERED DSA WAIT signal is produced on conductor 23B in response to the DSA WAIT signal. Wait counter 20 then is incremented until the above-mentioned CARRY signal is produced.
Next, the program enters block 106 and causes an error (too long a DSA WAIT signal) to be "reported". This can include sending out an error message to a CRT display unit. In block 108, the program executes an abort operation, which essentially "freezes" the system and waits for human intervention.
Reporting the error, as indicated in block 106, includes loading an error routine which effects printing of an error message and printing of the machine state at which the error occurred, i.e., the address of the instruction being executed at that time. The operator can then try suitable remedial action, for example, removing the device specific adaptor with which the error occurred and substituting another identical one.
It should be noted that in order to allow either DMA circuit 5 or DMA circuit 32 of FIG. 1C to take control of the data bus 11 (and address bus 13), it is necessary for the DMA circuit (or any other circuit that desires to take control of the bus) to first monitor the status of a bus request line connected to a bus request terminal of the monitoring circuit. If the bus request line is low, this means that another circuit has control of the data bus and address bus, and it therefore is unavailable. No circuit in the system can assert control over the data and address buses when they are unavailable. However, if the bus request line is high, this means the data bus and address bus are presently available.
It should be noted that the bus request line connected to the Z80 DMA circuit 5 and Z80 microprocessor chip 3 is a bi-directional line. Unfortunately, there is no signal which indicates which direction information on the bus request line is going. This makes it very difficult to "buffer" the bus request line because it is not known whether to buffer the bus request line from the Z80 DMA chip as an output thereof or to buffer the request line to the Z80 DMA chip as an input thereof. Stated differently, buffering of the bus request line by connecting bi-directional buffer circuits in series with the bus request line is desirable for several reasons. First, the current driving capability of the bus request outputs of the DMA circuits 5 and 32 of FIGS. 1C and 2 is not great enough to drive a large bus request line capacitance at a suitable rise time rate.
Second, in the system shown in FIG. 1C, the bus request line 51' of field maintenance processor 1 is coupled directly to the bus request terminals of both microprocessor 3 and DMA circuit 5. It would not be desirable to connect the BUS REQ terminals of microprocessor 3 and DMA circuit 5 directly to the DSA connector 10 (FIG. 1B), since device specific adaptor 30 is also plugged directly into DSA connector 10, since it is possible that static electric charge present on the bus request conductor of device specific adaptor 30 is great enough to destroy the sensitive MOS input circuitry of microprocessor 3 and DMA circuit 5.
Provision of suitable buffering circuitry in series with the BUS REQ conductors between the DSA connector 10 and the bus request terminals of microprocessor 3 and DMA chip 5 could solve both of the above problems, if there were available control signals indicating whether the DMA chips 5 and 32 and other circuits wishing to assert control over the data bus are monitoring or driving the bus request line.
Buffer circuit 50' in FIG. 1C performs the function of buffering the BUS REQ input of DMA circuit 5 and conductor 51' from conductor 51", which is connected by means of a buffer circuit contained in circuit 29C and part of the above mentioned DSA connector also contained in circuit 29C to conductor 51. Buffer circuit 50 is substantially similar to buffer circuit 51'. Buffer circuit 50 is shown in detail in FIG. 2.
In accordance with the present invention, the circuit of FIG. 2 includes a flip-flop which "examines" the bus request line, determines whether or not it is being asserted by any circuit capable of doing so, and stores a corresponding level indicating whether the DMA chip is monitoring or driving the bus request line. The contents of this flip-flop can then be used to control the direction of the buffer circuitry for the bus request line.
Referring still to FIG. 2, a DSA bus request conductor 51 is connected to or coupled by means of suitable buffers to the bus request inputs of all devices in the system which are capable of asserting control over the address bus 13, 11 including, microprocessor 3, DMA circuit 5 and DMA circuit 32.
DSA bus request conductor 51 is connected to a pullup resistor 52, which is connected to a positive 5 volt power supply voltage, and is also connected to the input of a three-state buffer 53.
The output of three-state buffer 53 is connected by means of conductor 55 to the input of an inverter 56 and to one input of two input AND gate 66. The output of inverter 56 is connected to one input of two input AND gate 60, the output of which is connected to the K input of J-K flip-flop 62. The other input of two input AND gate 60 is connected by means of conductor 59 to a pull-up resistor 58 and to the bus request terminal of DMA circuit 32. The signal on conductor 59 is referred to as DMA BUS REQUEST.
Conductor 59 is also connected to the J input of J-K flip-flop 62. The Q output of flip-flop 62 is connected by means of conductor 63 to an enable input of three-state buffer 70. The input of three-state buffer 70 is connected to a ground level supply voltage conductor, and the output thereof is connected to conductor 51, on which the internal DSA BUS REQUEST signal is conducted. The Q output of flip-flop 62 is connected by means of conductor 64 to the other input of two input AND gate 66. The output of AND gate 66 is connected by means of conductor 67 to the enable input of three-state buffer 68. The input of three-state buffer 68 is connected to a ground level voltage conductor and its output is connected to conductor 59.
The operation of the circiut of FIG. 2 is as follows:
First, assume that DMA chip 32, which is part of the DSA circuit 30 is monitoring the status of the DSA BUS REQUEST conductor 51, which is connected to the Z80 microprocessor 3 of the FMP 1. Also, assume that the flip-flop 62 is initially set. (The reason for this assumption will be clear later.) When flip-flop 62 is set, this means that DMA circuit 32 is monitoring the DMA BUS REQUEST conductor 59, as can be seen by assuming that a logical "one" is applied to DSA BUS REQUEST conductor 51 to indicate that no other device in the system is exerting control over the data bus. This logical "one" is produced on conductor 51 by pull-up resistor 52, since no other device is pulling conductor 51 low because no other device is asserting control over busses 11 and 15. The fact that flip-flop 62 is initially set causes a "one" to be applied via conductor 64 to the control input of three-state inverter 70, disabling three-state inverter 70, and thereby allowing pull-up resistor 52 to pull conductor 51 to a "one" level. Then conductor 55 will be at a logical one, and conductor 57 will be at a logical "zero".
Since flip-flop 62 is in a "set" state, the Q output conductor 64 will be at a logical "zero". Thus, one input of gate 66 is at a logical "zero" and the other input is at a logical "one". The output of gate 66 therefore is at a logical "one" causing three-state buffer 68 to be off. This means it presents a very high output impedance. The voltage on DMA BUS REQUEST conductor 59 is therefore a logical "one" due to the action of pull-up resistor 58. Since at least one input of gate 60 is at a logical "one", its output, conductor 61, is at a logical "one". Thus, flip-flop 62 remains set (since K must be a "zero" to reset flip-flop 62).
It should be noted that the truth table for logic gates 60 and 66 is as follows:
Next, assume that an external device, such as DMA circuit 5 (FIG. 1) "takes control" of the address bus and data bus. DAM circuit 5 is then required to apply a logical "zero" on DSA BUS REQUEST conductor 51. This results in a logical "zero" on conductor 55 and a logical "one" on conductor 57. Conductor 61 remains at a logical "one", so the output of gate 60 remains a logical "one", and therefore the state of flip flop 62 is not changed. Thus, both inputs of gate 66 are logical "zeros". As can be seen from the above truth table, conductor 67 assumes a logical "zero", turning on three-state buffer 68 to produce a logical "zero" on DMA BUS REQUEST conductor 59. It will readily be apparent that this (the "zero" on conductor 59) produces no change on the K input of flip-flop 62, which thus remains "set".
Thus, we see that for either a logical "one" or a logical "zero" applied to DSA BUS REQUEST conductor 51, that state will be reproduced on DMA BUS REQUEST conductor 59 when DMA circuit 69 is in its "monitoring" mode, which occurs when flip-flop 62 is in its "set" state.
Next, it is helpful to consider the operation of the circuit of FIG. 2 when DMA circuit 32 itself applies a logical "zero" to DMA BUS REQUEST conductor 59 in order to exert control over the data bus (after having determined that the data bus is indeed available).
In this event, DSA BUS REQUEST conductor 51 is initially at a logical "one". Conductor 57 is at a logical "zero" and conductor 55 is at a logical "one". Since both conductors 57 and 59 are now at logical "zeros", the above truth table indicates that gate 60 produces a logical "zero" on conductor 61, the K input to flip-flop 62. This causes flip-flop 62 to "reset". This cause Q conductor 63 to go from a logical "one" to a logical "zero", turning three state non-inverting buffer 70 on, and forcing DSA BUS REQUEST conductor 51 to a logical "zero" to "request the bus" and inform the rest of the system that the address and data buses are not available.
This causes conductor 55 to go to a logical "zero" and in turn causes conductor 57 to go from a logical "zero" to a logical "one". This causes conductor 61 to go from a logical "zero" to a logical "one", thereby preventing further resetting of flip-flop 62. Meanwhile, Q output conductor 64 of flip-flop 62 has gone from a logical "zero" to a logical "one". The output of gate 66 causes conductor 67 to remain at a logical "one", maintaining three state non-inverting buffer 68 off.
Thus, it is seen that when DMA circuit 32 exerts a logical "zero" on DMA BUS REQUEST conductor 59 in order to assert control over the bus, the same logic "zero" level is forced onto DSA BUS REQUEST conductor 51, "requesting the bus" and informaing the rest of the system that the bus is now unavailable.
Next, it is instructive to explain the operation of the circuit of FIG. 2 when DMA circuit 32 released control of the data bus by allowing DMA BUS REQUEST conductor 59 to return from the logical "zero" to a logical "one" under the influence of pull-up resistor 58. It will be recalled that at the beginning of this process, conductor 57 is at a logical "one", since DSA BUS REQUEST conductor 51 had been held low (as previously explained), while DMA circuit 32 was exerting control over the data and address buses. With conductor 59 and conductor 57 both at logical "ones", the output of gate 60 remains at a logical "one". The logical "one" on conductor 59, applied to the J input of flip-flop 62, now causes flip-flop 62 to be "set", so that Q conductor 63 goes from a logical "zero" to a logical "one", turning off three-state non-inverting buffer 70. This allows pull-up resistor 52 to pull DSA BUS REQUEST conductor 51 to go from a logical "zero" to a logical "one", indicating to the rest of the system that the data bus and address are now available. Q conductor 64 goes from a logical "one" to a logical "zero", and the other input (conductor 55) goes from a logical "zero" to a logical "one". The output of gate 66 remains at a logical "one" and three-state non-inverting buffer 68 remains off, so that DMA BUS REQUEST conductor 59 remains at a logical "one" due to the action of pull-up resistor 58.
While the invention has been described with reference to a particular embodiment thereof, those skilled in the art will be able to make various modifications to the disclosed embodiment without departing from the true spirit and scope of the invention.
|Cited Patent
|Filing date
|Publication date
|Dec 10, 1976
|Jul 4, 1978
|Honeywell Information Systems Inc.
|Interrupt apparatus for enabling interrupt service in response to time out conditions
|Oct 19, 1976
|Feb 27, 1979
|Tokyo Shibaura Electric Co., Ltd.
|Refreshing system for dynamic memory
|Mar 23, 1976
|Jun 26, 1979
|Texas Instruments Incorporated
|Input/output controller having selectable timing and maskable interrupt generation
|Sep 17, 1979
|Dec 29, 1981
|Honeywell Information Systems Inc.
|Microprocessor based maintenance system
|Citing Patent
|Filing date
|Publication date
|Oct 31, 1983
|Dec 23, 1986
|Ncr Corporation
|Dynamic random access memory refresh control system
|Oct 4, 1984
|May 5, 1987
|Nec Corporation
|Control system for tightly-coupled multiprocessing units
|Dec 23, 1983
|Sep 8, 1987
|American Telephone And Telegraph Company, At&T Bell Laboratories
|Microprocessor peripheral access control circuit
|Nov 12, 1985
|Oct 4, 1988
|Westinghouse Electric Corp.
|Electronic key check for ensuring proper cradles insertion by respective processing board
|Dec 12, 1988
|Sep 11, 1990
|Canon Kabushiki Kaisha
|Data processing system with memories access time counting and information processor wait signal generating circuitries
|Jul 24, 1987
|Dec 3, 1991
|Hitachi, Ltd.
|Apr 11, 1990
|Jun 22, 1993
|Kabushiki Kaisha Toshiba
|Data processing system having a resume function and an operating method thereof
|May 19, 1989
|Sep 21, 1993
|Compaq Computer Corporation
|Minimum reset time hold circuit for delaying the completion of a second and complementary operation
|Jan 29, 1991
|Oct 12, 1993
|Nec Corporation
|Direct memory access (DMA) request controlling arrangement including sample and hold circuits and capable of handling immediately successive DMA requests
|Oct 15, 1990
|Apr 19, 1994
|Chips And Technologies, Inc.
|Bus controller with different microprocessor and bus clocks and emulation of different microprocessor command sequences
|Mar 22, 1993
|May 17, 1994
|Zilog, Inc.
|Programmable wait states generator for a microprocessor and computer system utilizing it
|Apr 13, 1993
|Jun 28, 1994
|International Business Machines Corporation
|Method and apparatus for extending a computer bus
|Jul 6, 1993
|Sep 5, 1995
|Intel Corporation
|Transparently inserting wait states into memory accesses when microprocessor in performing in-circuit emulation
|Mar 28, 1994
|Dec 12, 1995
|Kabushiki Kaisha Toshiba
|Computer with password processing function and password processing method of computer
|Jul 13, 1994
|Aug 6, 1996
|Kabushiki Kaisha Toshiba
|Password management method and apparatus
|Dec 5, 1994
|Aug 20, 1996
|Motorola, Inc.
|Data processor and method for providing show cycles on a fast multiplexed bus
|Jul 1, 1994
|Nov 5, 1996
|Canon Kabushiki Kaisha
|Electronic equipment having controllable access times for detachable cartridges
|Nov 17, 1993
|Jun 16, 1998
|Adaptec, Inc.
|Intelligent hardware for automatically reading and writing multiple sectors of data between a computer bus and a disk drive
|Jun 28, 1996
|Dec 1, 1998
|Nec Corporation
|System for accessing dynamic random access memory where the logic/control circuit temporarily stops upon word line switching
|Feb 2, 2005
|Jun 9, 2009
|Seiko Epson Corporation
|Display controller, display system, and display control method
|Feb 2, 2005
|Aug 11, 2005
|Kiyohide Tomohara
|Display controller, display system, and display control method
|Aug 5, 1992
|Feb 18, 1993
|Adaptec, Incorporated
|Intelligent hardware for automatically reading and writing multiple sectors of data between a computer bus and a disk drive
|U.S. Classification
|714/754, 710/260
|International Classification
|Cooperative Classification
|European Classification
|Feb 23, 1981
Owner name: GEN RAD, INC., 300 BAKER AVENUE, CONCORD, MASS. 01
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GREENWOOD, EDWARD H.;REEL/FRAME:003910/0442
Effective date: 19810217
Owner name: GEN RAD, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GREENWOOD, EDWARD H.;REEL/FRAME:003910/0442
Effective date: 19810217
|Mar 27, 1986
Owner name: BANK OF NEW ENGLAND, N.A., 28 STATE STREET, BOSTON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GENRAD, INC., A CORP OF MA.;REEL/FRAME:004536/0565
Effective date: 19860318
|Mar 16, 1987
|Fee payment
Year of fee payment: 4
|Mar 29, 1991
Owner name: GENRAD, INC., A MA CORP.
Free format text: SECURITY INTEREST;ASSIGNOR:NEW BANK OF NEW ENGLAND, N.A.;REEL/FRAME:005674/0103
Effective date: 19910329
|Jun 12, 1991
|Maintenance fee reminder mailed
|Nov 10, 1991
|Lapse for failure to pay maintenance fees
|Jan 21, 1992
|Expired due to failure to pay maintenance fee
Effective date: 19911110


text:
Billy Vaughn
- Overview
- Biography
- Songs
- Browse by Format
- Browse by Genres
- Similar Artists
|Easy Listening Holiday & Seasonal Jazz Pop / Rock
|instrumental orchestra easy listening swing 50s billy vaughn 60s
|1950s 1960s 1970s 1980s 1990s 2000s
|discogs lyrics purchase for download VIAF wikidata wikipedia
Richard Vaughn, 12 April 1919, Glasgow, Kentucky, USA, d. 26 September 1991, Escondido, California, USA. An extremely successful orchestra leader, arranger and musical director during the 50s and early 60s. In 1952, singing baritone and playing piano, he formed the Hilltoppers vocal quartet, with Jimmy Sacca, Seymour Speigelman and Don McGuire. They had a string of US hits through to 1957, commencing in August 1952 with Vaughns composition Trying, and in the following year with the million-selling P.S. I Love You. When Vaughn left the group in 1955 to become musical director for Dot Records, the other three members continued together until the early 60s, when they too accepted jobs with Dot.
Throughout the 50s, Vaughn contributed significantly to Dots chart success, particularly with his arrangements for the somewhat antiseptic cover-versions of rock n roll and R&B hits,...
- MatchBilly Vaughn
- 100%Ray Coniff
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- 78%Roger Williams
- 68%Paul Mauriat
- 64%Bert Kaempfert
- 60%Franck Pourcel
- 55%Percy Faith And His Orchestra
- 48%Caravelli
- 47%Lawrence Welk
- 46%Mantovani

subset: commoncrawl


text:
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text:
Vinson Massif, the highest mountain in Antarctica
Member of True Patriot Love Scotiabank Expedition: Antarctica climb
That was how Heather Moyse began her last Facebook post before starting an attempt to climb the summit of Vinson Massif, the highest mountain in Antarctica, in -40 degree temperatures.
"I will be offline/unplugged in the middle of a white ice desert. It will be way outside of my comfort zone," wrote the 37-year-old two-time Olympic gold medalist and Summerside native.
The True Patriot Love Scotiabank Expedition: Antarctica climb, aimed at raising awareness and funds to address the challenges of Canadian Armed Forces as they transition back to civilian life, began on Jan. 9.
In her post, Moyse shared a note written by one of her teammates, Brian Carney.
"As of right now my somewhere is with seven Canadian Armed Forces veterans, two specialists, 15 other civilians and six hopefully very experienced guides on the True Patriot Love Antarctica Expedition," wrote Carney. "After a brief pit stop in Punta Arenas, Chile, our team will attempt to summit Vinson Massif, the highest peak in Antarctica and one of the world's Seven Summits."
Moyse has spent the past few months fundraising and training for the expedition, posting on her various social media updates on her progress, including a photo of her on a treadmill, a 75-pound backpack on her back, walking a 12 per cent incline.
In an email to the Journal Pioneer before departing, Moyse indicated she would not have access to email during her adventure.
She is expected to be gone until Jan. 28.
"This is truly going to be an introspective journey," she wrote in her last Facebook post. "I can't wait to tell you all about it when I get back!"
For more information or to donate, visit Moyse's website — heathermoyse.com.


text:
Hey folks! I was up visiting my family again this weekend, and since I hadn't seen any posts on the merits (or lack of merits) of Fuji San, I figured I'd go give them a try. I got there at 6:30 on Friday evening, was seated immediately at the sushi bar. The place is well lit, clean, and I thought nicely decorated.
I ordered the gyoza soup, which I expected would be just a standard won ton. It was so much more! The broth was EXTREMELY hot - so be careful when you order it... how to describe it. The broth was like a clear soup/won ton but more peppery. the gyoza were delicate and flavorful. AND - there were veggies in the soup. If I had to guess, they put in the gyoza, then raw onion, cabbage, carrots and mushrooms, the this very hot broth to quickly cook the veggies. It was so very tasty. I recommend it.
I ordered several pieces of sushi - the rainbow roll, and several basic nigri - not remembering exactly now because I'm tired, but I'm sure salmon and hamachi were in there. Everything was very nicely put together, and very tasty. There were 2 sushi chefs, one made the nigri, the other made the rolls. Presentation was not fancy, but was nice.
we will definately be going to fuji san again in our visits to the Binghamton area - I liked it very much.
BTW, the staff was very attentive, kept my water glass filled, asked if I needed anything else, etc.


text:
Craig Rivet News Archive
News -- July 2016 (1)
- 7/20 Sabre Noise: Buffalo Sabres Past Provides Blueprint For Future: As the Buffalo Sabres continue to build out their roster, we take a look back at the historic 2006-07 season, at Daniel Briere...
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text:
At their January 9, 2017 meeting the Board of Education directed district administration to look for ways to create a facilities solution that addressed the district's identified needs in a way that explores potential partnerships, creates definitive answers to potential issues with City of Milton utility infrastructure in an around a potential new high school, includes a clear and definitive plan for the current middle school, and is as affordable as possible to taxpayers for a potential referendum within the next six months.
Updates to our community on that directed work are found in the links to the documents below.
1/23/2017 Board Meeting Referendum Update
2/13/2017 Board Meeting Referendum Update
2/27/2017 Board Meeting Referendum Update
5/8/2017 MHS Programming Needs And Concepts Presentation To School Board
5/22/2017 Baird Financial Presentation To School Board
7/10/2017 JP Cullen Board Presentation Information
Tweets by @SchDistofMilton


text:
Data Entry image to word
Budget $2-8 USD / heure
I have some images and PDFs to be 'hand type' in Microsoft office. Around 120 pages of image and 48 PDF files. Give me your best quotes!
135 freelances ont fait une offre moyenne de 4 $ /heure pour ce travail
Dear Sir / Madam , We Provide Complete Data Processing and Data Management Services. Our Key Services: • Online / Off Line data Entry • Web Research & Web Scrapping • Data Mining & Data Base Management • ecom Plus
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text:
Pan-Seared Scallops With Spinach
Recipe by loof751
From Country Home Magazine - what a lovely seafood dish!
Top Review by KateL
Better than restaurant quality, I had to promise DH to make this once a month. I used never frozen "large" sea scallops, but not "colossal" size. The searing times were perfect; I had purchased 1 1/2 pounds of sea scallops, and only 1 pound fit my 12" deep dish frying pan at one time. I kept the first batch warm in the oven at its lowest setting, and had to add more bacon grease to the pan. I used 5 ounces of fresh spinach, because it looked like enough for just 2 of us, and it was expensive. Even so, the spinach appeared to fill the 2-3" tall frying pan, so I would use my tall-sided Le Creuset pot if I were making more spinach (and that pot would probably accept 1 1/2 pounds of scallops at one time). I used Tony Chacere's Creole seasoning, and I liked its subtle presence in this dish. The only improvement I might suggest would be to chill the dredged scallops for 30 minutes to 1 hour prior to searing. As always, the secret to searing is to make sure the pan and the fat are hot enough to sear, and it is important not to turn the scallops until they are ready; some say that if the "meat" sticks, and does not release, you need to wait until it does. The spinach was not so pretty on the plate, so I would be tempted to steam it separately; DH wouldn't change a thing. At the end, I had leftover bacon bits even though I sprinkled them liberally. Served with a sourdough roll. Made for Please Review My Recipe tag game.
Ingredients Nutrition
- 3 slice lean bacon
- 453.59 g sea scallops
- 29.58 ml flour
- 9.85 ml cajun seasoning
- 283.49 g fresh spinach
- 14.79 ml dry white wine
- 29.58 ml balsamic vinegar
Directions See How It's Made
- In a large skillet cook bacon until crisp. Remove from pan and drain well on paper towels. Remove all but 1 tablespoon drippings from skillet.
- Rinse scallops and pat dry. Combine flour and cajun seasoning; add scallops and toss to coat.
- Cook scallops in hot drippings in skillet about 6 minutes or until browned, turning once.
- Remove scallops from skillet. Deglaze skillet with white wine.
- Add spinach to liquid in skillet. Cover and cook over medium-high heat for 2 minutes or until spinach is wilted. Add vinegar and toss to coat evenly.
- Return scallops to skillet and heat through. Crumble bacon and sprinkle over scallops.


text: So, in VB3.8 if I wanted to give an individual user a custom icon under their username I would add their id number to a conditional I had going to the appropriate template. I think I can just use the XF userbanner in my case, is using a template conditional still the best way or is there a better way that I haven't discovered yet such as an add-on or etc.?


text:
Our Volcano, Hawaii Restaurant Serves Breakfast, Lunch & Dinner
For reservations at our Volcano Village, Hawaii restaurant call 808-967-7366 or click here to reserve a dinner table online
Hours at Our Volcano, Hawaii Restaurant
Breakfast Daily – 7:30am to 10am (view menu)
Lunch Daily – 10am to 2pm (view menu)
Dinner Nightly starting at 5pm (view menu)
Sunday Brunch – 10am to 2pm (view menu)
Kilauea Lodge Restaurant is located on property at Kilauea Lodge in the town of Volcano Village, on the Island Hawai'i (also known as The Big Island") and close to Hawai'i Volcanoes National Park. We are open for breakfast and lunch daily and dinner nightly. We also offer a Sunday Brunch. Kilauea Lodge Restaurant serves up some of the finest dining in Hawaii.
Explore the Dining Experience of Our Volcano, Hawaii Restaurant
Kilauea Lodge Breakfast
Breakfast includes Pancakes, French Toast, Omelets and more. Lodging guests enjoy complimentary breakfast each morning with their stay.
Kilauea Lodge Lunch
A Kilauea Lodge lunch includes salads such as Caesar, Curried Chicken, Nicoise, NY Steak and Cobb; Mini Burgers combo (antelope, buffalo and beef); German Sausage plate with house made sauerkraut; Sandwiches such as Reuben, Club, Vegetarian, Portobello, fresh fish and others.
Kilauea Lodge Dinners
Kilauea Lodge dinners are well known for owner-chef Albert Jeyte's continental cuisine with a touch of local flavors. His specialties include European favorites; hasenpfeffer, antelope, and duck, and there's always fresh fish from deep Big Island waters. All entrees include soup or salad. A thoughtful wine list and helpful staff make Kilauea Lodge a memorable experience.
Kilauea Lodge Sunday Brunch
The Kilauea Lodge Sunday Brunch includes savory dishes such as Smoked Salmon Benedict, homemade Corned Beef Hash and Eggs, Volcano Loco Moco, and the Chief Ranger. Sunday Brunch has become a favorite tradition with local residents.
Kilauea Lodge International Fireplace of Friendship
In October 1938, four hundred people from around the Territory of Hawaii gathered at Camp Hale O Aloha in Volcano Village for the dedication of a unique fireplace. The International Fireplace of Friendship with its stones and coins from all over the world was the inspiration of Harold Lucas, the Y.M.C.A. camp director in charge of construction at Camp Hale O Aloha. Lucas' dream was to create a hearth of world brotherhood using stones from 32 countries around the world.
After a fabulous day of hiking National Park trails, nothing beats a good dinner at Kilauea Lodge Restaurant. A relaxing interior of hardwood floors, koa tables, fresh flowers, original art and, at the center of it all, the historic Fireplace of Friendship with its precious collection of artifacts, provide the setting for fabulous dinners served nightly.
Also View: Breakfast | Lunch | Dinner | Sunday Brunch


text:
"Picture of fashion- the new line of the casual - lowered waistline and a bodice that follows your figure. Bouffant skirt is gathered 'neath the button-front bodice."
Links to reviews/blog posts Edit
Sources/Vendors Edit
Gallery Edit
[insert your photos of this pattern made up]
Wishlist Edit
[insert your username, and make sure your preferences allow for people to contact you via e-mail. Do not list your email address here!]


text:
As our patient you will receive the best of care. You can freely select an independent examining doctor from a network of 2'000 doctors.
Our partners are all highly qualified specialists offering you the highest level of care.
The Klinik Belair is situated on a hill above the old town of Schaffhausen in a quiet location in the "Breite" residential area. The park-like surroundings with its old trees and peaceful seating areas offer you and your visitors restful moments.
The bus lines 3 (Sommerwies), 4 (Birch) and 6 (Neuhausen SBB) from the Schaffhausen train station, departing from the train station side, all bring you to the clinic. The clinic is situated 100 metres from the Schützenhaus bus stop. We would be happy to organise transport for you to the clinic should you wish.
The public transport timetable can be found at www.sbb.ch.
Free parking spaces for visitors are available within the clinic grounds. These can be only be accessed from Rietstrasse.


text:
Congresswoman Maxine Waters (D-Calif.) issued the following statement today after a student allegedly brought a gun to Gardena High School and shot two students when the backpack concealing the weapon was dropped:
"I am just devastated to learn of the events today at Gardena High School. I am very thankful that the two students who were injured survived the initial shooting, and with limited information at this time I can only be hopeful they will make a full recovery, despite the brave young girl who remains in grave condition at the hospital tonight. I also want to thank the first responders and the faculty, staff, and students at Gardena for their quick response in isolating this incident and bringing it to a close.
"Weighing heavy on my heart is a recent wave of violence throughout my district in South Los Angeles that has claimed the lives of many of my constituents like: five-year-old Aaron Shannon Jr., hit by a bullet in his own backyard while showing off his Spiderman Halloween costume to his family; Kashmier James, a young woman killed while visiting friends on Christmas day; 14-year-old Taburi Watson, shot while riding his bike a few days before New Year's; and Mr. Lewis Smith, who sadly was removed from life support last week after surviving the initial shooting, in some sad and tragic twist of fate, in a plaza named for Dr. Martin Luther King. Jr.
"The debate over gun control has been brewing since the tragedy in Arizona almost two weeks ago that killed 6 people and left 14 injured, including my colleague, Congresswoman Gabby Giffords. One of the Congress' fiercest gun control advocates, Congresswoman Carolyn McCarthy, introduced simple and sensible legislation to ban the kind of magazine used in the shooting. I am proud to be a cosponsor of her legislation, even as I and my colleagues are being told by people both on and off the Hill that the legislation will go nowhere.
"Let's all be clear about one thing though: guns don't belong in the hands of students. And they don't belong on any school property. Period.
"I am eager to learn what steps LAUSD, the Cities of Gardena and Los Angeles, LAPD, the community, and all Los Angelinos will take to ensure that we remain united in our efforts to confront violence, keep our streets and our schools safe, and create economic and educational opportunities for all people.
"I ask all Americans to keep these young students in their thoughts and prayers during the critical hours and days ahead."
Source: http://waters.house.gov/News/DocumentSingle.aspx?DocumentID=220436


text:
AF promo 3 by DFer32Watch
©2012-2017 DFer32
Another work for an anime con promo. This is the last one by now, i can go back to work on commissions again e-e
Done in SAI.
Done in SAI.
I love it! ♥
I've been away for about 2 months. Oh, how I've missed the Eye Candy, that is your art.
SHe looks adorable!!!
Tu acabas de hacer una muy buena gatubela mejor que la de las películas esta chida
Uuu very nice
Kinda reminds me of Catwoman
Cute and sexy kitty.
Genial, como siempre
..Amazing D:
You always blow me away with the sheer amount of details ~
You always blow me away with the sheer amount of details ~
Otra animu friends, nunca me entero cuando son XD
cute and sexy!!! She has a nice face
En SAI!! increible loq eu se puede hacer... cuando se sabe usar un programa!!
Asi es, es solo cuestion de aprender ^^
Ehh ta re bueno pibe
Bellisimo trabajo, como siempre.
i really like this drawing, but the left leg seems a bit off to me. it almost seems proportionately like it should be a little closer to the viewer rather than on the same line with the other leg, unless that was your intention in the design. regardless its a great piece!
kinda reminds me of pogojo's work
wow OwO nicely done, I say, lookin' good in dem pants


text:
- Description
Individually Placed NailheadsIncludes
Accent Pillows Included
Plush Rolled Arms
Reversible Pocket Coil Cone Seating
Kiln Dried Hardwood Frame
Cushions: Seat: Reversible Back: Reversible
Wood Frame: Sturdy Construction For Stability And Heavy Use
Sinuous Spring Base: Spring Base Allows For Sleek And Sturdy Construction
Accent Pillows Included: 2 Pillows For Sofa
1 Sofa and 1 Love SeatDimensions
Sofa, 86.50"W x 35.50"D x 31.50"H x 29.00"SD x 21.00"SH
Love Seat, 63.50"W x 35.50"D x 31.50"H x 29.00"SD x 21.00"SH
- Additional Information
Additional Information
SKU 12694659 GTIN No Collection No Assemble Length No Assemble Width No Assemble Height No Assembly Required Yes Material Linen Color Charcoal Styles Contemporary Shipping Time 1-2 Weeks Free Shipping No
- Reviews
Disclaimer: Pictures displayed may include optional products not included in the price. Computer monitors often display color variations. Color swatches are shown if alternative colors are available. Please call us or email us if you have any questions!


text:
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text:
The six candidates vying to be the next superintendent of the Jefferson Parish Public School System got a chance Thursday to publicly lay out their vision and qualifications for the job and field questions about issues they'd face if they get it.
The interviews, hosted by the Jefferson Parish School Board, were designed to give the public a sense of the views of the two men and four women seeking to replace Superintendent James Meza, who stepped down in late January.
The interviews will air at 5:30 p.m. Monday on JPS-TV, carried on Cox Channel 8 and Channel 99 through AT&T U-Verse. They were designed to allow the public to hear from the candidates in advance of the board's decision, which is expected Wednesday. The board also has a series of video profiles available on its website.
The candidates were asked the same set of questions, such as how they would approach bargaining with teachers unions, how they would guide the system out from under a state corrective action plan related to special-needs students, how they would better serve students who don't speak English as a primary language and what their plans would be for the first 100 days and first six months of their administration.
Among their responses:
Sharon Wegner, of Gretna, director of Jefferson Parish government's Workforce Connection and a former teacher and longtime administrator, said the system should strive to make sure that students are taught to be problem-solvers and thinkers. She said the curriculum should mix academics with occupational skills to accommodate students who plan to enter the workforce right after high school.
In her work with the parish, Wegner said, she sees young people looking for work who don't have any of the necessary skills to qualify for many jobs.
"They don't have the luxury of going to training," she said. "They need a job."
Wegner said she can motivate groups toward a common goal, shown by the fact that she turned the parish's workforce department around from failing in six of nine performance indicators to passing all of them.
Isaac Joseph, of Harvey, the school system's executive director of grants and federal programs, said academics would be his first priority, followed by fiscal responsibility. He said the system needs to develop a public relations campaign to help sell public education and dispel myths about the system.
He also said the system needs to have a difficult conversation about why black and Hispanic students do not succeed academically as often as their white and Asian counterparts. "As professionals and educators, we are going to have to address that head-on," he said.
He said the key to student discipline is applying corrective action consistently.
Overall, Joseph said, he feels that climate and culture trump strategy, and that he would work to foster the former from the ground up to help the system excel.
Michelle Blouin-Williams, of Gretna, a former teacher, deputy superintendent and now interim superintendent, said she would make it a point to listen to all parties — students, parents, board members and administrators.
Blouin-Williams, who was named publicly by Meza as his choice to replace him, said schools should be given the tools they need to succeed and there should be more room for different approaches to academic success.
As for negotiations with the teachers union, she said she would encourage all sides to listen to one another but that, as superintendent, she would ultimately respect any decision made by the board.
The students, Blouin-Williams said, "are always first in my heart and will always be first in every decision that is made under my leadership."
Charles Michel, who has lived in Metairie for the last nine years and is now special education director for the Lafourche Parish school system, said he thinks the Jefferson system would benefit from having a superintendent come in from the outside.
He said that despite its successes, the system still has 10 D-rated schools and three F-rated schools, and that support teams should be created to make recommendations on how to improve them.
Michel said he would meet with all stakeholders and work to repair broken relationships and rebuild trust.
He said discipline issues and academic achievement are more closely connected than people realize. Many students who are "acting out" are doing so because of an underlying academic problem, and they would rather be seen as bad than stupid, he said.
Germain Gilson, of Gretna, a chief student support officer for K-12 students in the system, said schools can succeed if they are given the proper support.
"The standards don't scare us as educators," she said. "We have been dealing with standards for a long time. … What scares us is if we don't have what we need to teach the kids (to) the standard."
Gilson said the test results of students who don't speak English as their primary language are incorporated into the overall results much earlier than they should be. "It takes more than one year for those students to be able to be tested like their peers who have … lived here all their lives," she said.
On negotiations with teachers unions, Gilson said she has been a union representative and that any agreement should be a compromise among professionals that deals with work-related issues, not one that restricts teachers from helping their students succeed.
Carolyn Van Norman, of River Ridge, the Jefferson school system's executive director of performance management, said the system should allow principals and schools to take an individualized approach to instruction to fit the needs of their students.
She said students who are falling behind should be identified early and given additional instruction.
Van Normand said the superintendent should work closely with the state Board of Secondary and Elementary Education to make sure state policymakers understand the needs and challenges of educators at the local level.
She said the system should embrace the influx of non-native students but bolster resources to bring them up to the level of their English-speaking peers. She said it takes longer to do so than current standards recognize.
Follow Chad Calder on Twitter, @Chad_Calder.


text:
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Running Time: 74 minutes
Studio Name: COSMOS Produktion
Series: Non Stop Sex
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text:
Attendance Policy
Dear Parents and Guardians,
All students at Dominguez High School are required to maintain good attendance because academic achievement and school attendance are directly correlated. Students are required to attend class regularly and to arrive promptly. Only by attending regularly can they take the best advantage of their classes. By arriving promptly, they make the best possible use of class time and cause the least possible disturbance to those students ready to begin their work.
When a student is tardy
When a student is tardy to school for any reason, that student must bring a note from home to present to the teacher. Periodically, Dominguez will have tardy sweeps. During the tardy sweep students will report to the Gymnasium and will be issued a pass to class. If students are late after a sweep they must report to Room F-1 for a pass.
When a student is absent
When a student has missed a class or classes, that student must take a note from the parent/guardian to the Attendance Office. The note should have the following information:
- Date of absence
- Reason for absence
- First and Last Name, birthday and grade of student
- Signature of parent or guardian
The readmit slip which the student receives must be presented to the teacher of each class period at the beginning of class. The attendance office is open at 7:30 a.m.daily. The attendance office issues re admits from 7:30 a.m.until 7:55 a.m.After five days, each absence that has not been cleared with a note from home will be changed to truant. Re-admits are also issued between class periods and during lunch. Re-admits are not issued after lunch break.
Early dismissal
A student who must leave campus for an appointment before the end of the school day must bring a note from the parent/guardian explaining the reason BEFORE classes begin at 7:30 a.m. A student will receive a permit to leave grounds from the attendance office only after verification of the request. All requests are verified by phone call. The permit to leave grounds must be signed by parents/guardian or doctor and used by the student as a readmit the following day. Phone calls from parents are not accepted to release students.
If a parent/guardian comes to the Attendance Office with a request for a student to leave early, you must be on the student's emergency information card and you will be required to produce a valid picture identification card. A student cannot and will not be released by a telephone request.
We thank you in advance for your cooperation this school year. If there are any questions or concerns you may contact the Attendance office at (562) 630-0142.


text:
4mth old spitting up
Hi I'm new here my baby is 4mths and has acid reflux and allergy to cows milk n is on lactose free formula. Also on acid reflux meds twice a day. She spits up at every feed....
Started by Erica on 11/07/2016 in July 2016 Babies
Last update on 11/29/2016 by Kirsten


text:
House of the Dead (2003)
In House of the Dead (2003), some partying young people go to an island for a big rave and discover the place is overrun by vacant-eyed, drooling maniacs—oh, and there are also some zombies on the loose. This adaptation of the hit video game is a pretty amazing concoction and deserves plenty of credit for finding a feasible reason why the female victims would be dressed in incredibly hot clothing. Erica Durance, Sonya Salomaa, Mashiah Vaughn-Hulbert, and Penny Phang are all cheerfully...Join Mr. Skin for the full review >>


text:
Mushroom World is the planet that the Super Mario and the Donkey Kong series takes place on. The only time we have seen an official picture of the planet is in Super Mario Galaxy. The dominant species` of the planet are Toads, Beanish, Hoohooligan and Koopas.
Lands and KingdomEdit
- Mushroom Kingdom
- Jewelry Land
- Dinosaur Land
- Beanbean Kingdom
- Sarasaland
- Muda Kingdom
- Easton Kingdom
- Birabuto Kingdom
- Chai Kingdom


text:
News By Tag
Industry News
Industry News
Toyota Reports Hydrogen Fuel Cell Vehicles Planned for 2016 | Ourisman Chantilly Toyota
Though details like pricing on the first hydrogen fuel cell vehicles from Toyota are a long ways off, it has been speculated that the first vehicles would cost about 8 million yen, which is the equivalent of about $78,000.
Hydrogen fuel cell vehicles work by mixing hydrogen with oxygen in order to power an electric motor. They offer a driving range of about 300 miles, providing drivers with incredible efficiency.
Drivers who are interested in finding out more about Toyota's hydrogen fuel cell vehicle plans for the future can visit Ourisman Chantilly Toyota today!
Ourisman Chantilly Toyota is your source for new and pre-owned Toyota vehicles in Chantilly, Virginia, and features a friendly and knowledgeable staff that puts customer satisfaction above all else. The showroom is located at 4135 Auto Park Circle, Chantilly, Virginia 20151. To browse the selection of new and used vehicles available at Ourisman Chantilly Toyota, stop by the dealership or visit http://www.ourismanchantillytoyota.com today.
Kate Farley
(678) 208-0667
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text:
Power spectrum analysis is often used to determine whether population time series are dominated by particular frequencies. Results for chaotic time series are often reported in terms of the colour of the spectra whereby red spectra indicate a dominance of low frequency (long-term) fluctuations, white spectra indicate that all frequencies are equally dominant and blue spectra indicate a dominance of high frequency (short-term) fluctuations. Several studies have employed such analysis and much discussion has been provoked by an apparent conflict between the fact that the time series of natural populations produce reddened power spectra whereas chaotic, single species ecological models can produce blue, white or red spectra. Here, we resolve the question of which parameter values give rise to particular colour spectra by analysing simple models in terms of `universal' parameters allowing direct comparisons between models to be drawn. This suggests that some models are not capable of producing reddened spectra, which would question their usefulness in describing ecological systems. The population behaviour associated with each colour spectrum is described and compared with models that incorporate simple modifications to represent delayed density dependence, spatial structure and environmental effects.
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text:
When chunky is good.
Not long ago, the ESI Chunky Mountain Bike Grips were a well-kept secret of elite endurance racers. But, the secret is out, and you're now able to experience the smooth ride and all-conditions control that these silicone wonder-grips have become so well known for.
ESI's grips are built from silicone for a host of reasons. Chief among them is the vibration damping that silicone provides. Basically, these are much more effective than a standard grip at canceling out high frequency vibrations, which ultimately leads to numbness and pain in the hands. It's especially noticeable during long rides, but the benefits will be apparent every time that you hop on your bike. Silicone is grippy stuff, which is good news, because that grip works in both directions. As a result, the grips are secured not only to your hands, but to your handlebars as well. In fact, when installed per the instructions, these grips stick firmly to handlebars, even in the rain. And naturally, they provide a solid hold for your hands, regardless of sweat or dirt. Better yet, because silicone has memory, these grips will break in to the shape of your hand, providing a custom-fit that gets better the more that you ride them.
These grips are offset, which means that they're slightly thicker on one side than the other. So, when installing them, make sure that you have the thicker end facing your palms, and the thinner end underneath your fingers. This will ensure maximum vibration damping, while still providing a direct steering feel. The Chunky grips have a medium thickness that works well for most riders. Riders with smaller hands, or those who prefer thinner grips, will be better served by the ESI Racer's Edge grip.
The ESI Chunky Grips are available in one size and in the colors Black, Blue, Green, Red, and White. Please note that we advise referring to the included instructions for correct installation.
- Made with silicone
- Optimal vibration damping
- Custom fit
Tech Specs
View more Grips
Reviews & Community
I Can't Feel Anything Anymore
- Familiarity: I've used it several times
I got these mainly for the vibration dampening, and man do they do that well. I'm wearing some gloves with just a bit of padding, and I can't feel any of those little vibrations that I used to dread. I used to be ready to quite riding after a few miles just because of hand fatigue, but I can ride WAY longer now almost without having to worry about that at all. The price is pretty great too. I would definitely recommend getting a pair of these!
No Reason to Use Anything Else
- Familiarity: I've put it through the wringer
These things are great. I would say that they are the most comfortable grips out there, and these Chunky ones give you that little bit extra to hold on to and a little more cushion compared to the Racer's Edge version. Pretty straight forward to install as well. I will never use anything other than ESI grips on my bikes.
ESI Grips Chunky Mountain Bike Grip
- Familiarity: I've put it through the wringer
Review #2... since got a pair for my fiance.. ESI grips are the standard! They are the best lightweight grip on the market. While the durability from a cut/tear standpoint can be a challenge as they are so light, they are super durable from a normal wear and tear perspective. I have and will continue to use them for years!
To me these are the standard
- Familiarity: I've put it through the wringer
I dont know why you would ride any other grip. Cheap, durable and feel great. What else do you need?
Every MTB i've owned have had these since I first found them. Do yourself a favor and buy the grips you will use from now on.
- Familiarity: I've put it through the wringer
These grips are super comfy, hands feel fine on rides over 25 miles. If I could change anything I would just give some bar end options.
Best grips on the market!
- Familiarity: I've put it through the wringer
I've used ESI grips for years, and I can attest that they're the best grips on the market. The silicone foam absorbs shock better than hard rubber compounds, which allows me to runner somewhat stiffer suspension without my hands hurting. The chunky ones are perfect for people with medium-large hands and provide a good amount of surface area to grip the bars with. Also, the silicone compound doesn't get slippery when it's wet. It's still super sticky and perfect in wet conditions. Another benefit of the silicone foam is that you don't really need to wear gloves because it's soft enough that it won't tear up your hands! Perfect for grip shifters too because they're easy to trim to the right length and are the perfect thickness with the grip shifter.
ESI Chunky Mountain Bike Grip
good ones
- Familiarity: I've put it through the wringer
The ESI grips are simple and comfy. The grip is tactile and even works well in wet conditions. Use alcohol to install and they will stay nice and secure.
Go to grips
- Familiarity: I've put it through the wringer
I've been running these grips on my past 4 bikes. They don't last a full season, but they are comfy!
Love Them, just wish they were more dura
I've written a couple reviews and these are my go to grips. Just wish they were a little more durable as they tend to rip easily after a minor crash. Still would highly recommend as the light weight and grip are amazing.
Get a grip
- Familiarity: I've used it several times
These are great! Love the cushy and soft feel of the grip. They definitely tear easily if you crash or lay the bike over. But other than that I am super happy with them.
Probably the best.
- Familiarity: I've put it through the wringer
Finally, all my bikes have EIS grips.. replaced a pair of specialized contour grips and no going back... These are by far the most comfortable grips i have tried. My only beef is bar end plugs, looks super cheap.
Best MTB grips!
- Familiarity: I've put it through the wringer
These are the best mtb grips out there! Buy them now, you will not be disappointed. Light, comfortable, stylish. What more could you want from a mtb grip??
Comfortable and Absorb vibration
Have these on all my bikes. They are slick in the rain with finger-less gloves. Doesn't rain much in Phoenix!
review flagged as Inaccurate, 29ers are gay. Click here to view.
The Obvious Choice
- Familiarity: I've put it through the wringer
These grips are hands down, my favorite! They are not only grippy, comfortable, and shock absorbing, they are insanely light! Also a very good price!!!
Love these
- Familiarity: I've put it through the wringer
These are great grips for those who want a comfortable ride. They provide ample padding and the grip only gets better with the gloves as you sweat. The only downfall to these is they can get torn up pretty quickly in rough terrain or overgrown trails.
A little hard to get on
but they are well worth it. Super cheap, good quality and simple.
super cool grips
The ESI chunky grips are super cool. My first time running a pair and I think I may never go back to running rubber grips. I love the texture and cushion.
Go to Grip
- Familiarity: I've put it through the wringer
These grips seem to make it on all of my bikes. I regular try others (love Ergons) but these make it on all of my flat bar bikes. I have some nerve issues in my hands, so grips and gloves are important to me. The ESI Chunkies do their job well.


text:
Guitarist Dan Baraszu and Organist Dave Ellington team up with this latest Blue Canoe release titled, "Organ Trio". This CD has an amazing array of original tunes (with the exception of a Quincy Jones cover) that will inspire the traditional jazz fan and novice alike. Read the Official Blue Canoe Press Release. For all personnel, view on AllMusic.com
Blue Canoe Records
Blue Canoe Records
© 2003-2017 Blue Canoe Records and Blue Canoe Digital LLC. All Rights Reserved


text: Adelaide: A century by deposed Test opener Greg Blewett drove South Australia into a comfortable position on the opening day of their Sheffield Shield cricket match against Victoria at Adelaide Oval on Monday. At the close, South Australia was 261 for four with Jeff Vaughan unbeaten on 15 and Chris Davies not out 21.With the searing heat, the SA batsmen toiled hard against a disciplined Victorian attack with Blewett battling for four hours on his way to 117 from 228 deliveries, including 15 fours. In Brisbane, Ashes tour hopeful Simon Katich did his usual hatchet job on Queensland but he wasn't able to save Western Australia from a probable slide to defeat at the Gabba.Katich propped up WA with a fine century but his innings - and the hopes of the visitors - were battered when Andrew Symonds took a freakish catch to thwart the revival.vWA went to stumps on the second day at 253 for seven in their second innings - leading Queensland by 113 runs - after a handy unbeaten stand of 51 between Mark Walsh (28) and Matthew Nicholson (27). The score line would have been worse if not for Katich (101), who began his rescue mission when WA were wallowing at 12 for two, unhappy that opener Mike Hussey had been given out caught behind from the first ball of the innings.But Katich took charge with a series of punishing square boundaries and cracking drives to reach his fourth century against Queensland, enhancing his glowing reputation in Australian cricket circles.Copyright AFP 2000