text:
I am working with a client right now that has a very small living area. We are searching for a coffee table that won't further dwarf the space. How do you make a small space live large? Fool the eye by creating the illusion of more space. The obvious solution is to pare down the size and keep the design monochromatic.
via french gray
Are you a color and pattern person? Designer Sig Bergamin's apartment is awash with color and pattern. Because the coffee table is kept to a minimum size it works
Clear materials have less visual weight
Try combining two small side tables. The two together have more negative space than a large coffee table.
Michael Hampton D.C Design House
Trad Home Napa Valley Showhouse
Nate Berkus
They don't have to be the same size. Mix them up for interest as we did in my client's former home.
Anything with an open base creates the illusion of space.
via Briggs Edward Soloman
Anything glass or mirrored requires less visual space
via amy howard/cote de texas
via wisteria.com
via decoist.com
Use these helpful tips when shopping for a coffee table
For more design tips and tricks click on my Pinterest Board on the Upper Right Hand Corner.


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Institute for Tribal Environmental Professionals (ITEP)
The Institute for Tribal Environmental Professionals (ITEP) was created in 1992 to act as a catalyst among tribal governments, research and technical resources at Northern Arizona University (NAU), in support of environmental protection of Native American natural resources.
Their Mission: "ITEP serves tribes through outstanding, culturally-relevant education and training that increase environmental capacity and strengthen sovereignty."
Tribes & Climate Change (ITEP Program)
On the Tribes & Climate change website they provide information and resources tailored to helping Native people gain a better understanding of climate change and its impacts on their communities. Here you'll find basic climate-change information; profiles of tribes in diverse regions of the U.S., including Alaska, who are coping with climate change impacts; audio files of elders discussing the issue from traditional perspectives; and resources and contacts you can use to develop climate change mitigation and adaptation strategies. Soon they plan to provide an open forum where you can share your ideas and views on climate change with others.
Tribal Climate Change Project
The Tribal Climate Change Project is a collaborative project between the University of Oregon Environmental Studies Program and the USDA Forest Service Pacific Northwest Research Station. The project focuses on understanding needs and opportunities for tribes in addressing climate change, examining the government-to-government relationship in a climate context and exploring the role of traditional knowledge in climate change studies, assessments and plans.
Native Communities & Climate Change
Native Communities and Climate Change is a project of the University of Colorado Law School and Cooperative Institute for Research in Environmental Studies (CIRES). The Project received seed funding from the Renewable and Sustainable Energy Institute—a joint institute between the University of Colorado and the National Renewable Energy Laboratory. It is currently funded by the Western Water Assessment (WWA)—a Regional Integrated Sciences and Assessments (RISA) program, one of eleven nation-wide funded by NOAA's Climate Program Office—and the National Integrated Drought Information System (NIDIS). The Native Communities and Climate Change project seeks to provide resources for climate change adaptation and natural resource planning by American Indian tribes as well as to provide useful information to organizations and agencies working with Indian tribes on these issues.

subset: commoncrawl


text:
Cadmium Content of Wheat Grain from a Long-Term Field Experiment with Sewage Sludge
- Amar M. Chaudri *a,
- Céline M.G. Allaina,
- S.H. Badawyab,
- Martin L. Adamsa,
- Steve P. McGratha and
- Brian J. Chambersc
Grain Cd concentrations were determined in the wheat (Triticum aestivum L.) cultivars Soissons, Brigadier, and Hereward grown in 1994, 1996, and 1999, respectively, in soils of a long-term field experiment to which sewage sludges contaminated with Zn, Cu, Ni, or Cr had previously been added. Soil pore water soluble Cd and free Cd2+ increased linearly with increasing total soil Cd (R 2 = 0.82 and 0.84, respectively; P < 0.001). Similarly, soil pore water free Cd2+ increased linearly with increasing soil pore water soluble Cd (R 2 = 0.98; P < 0.001). There was no evidence of a plateau in soil pore water Cd concentrations with increasing soil Cd concentrations. Grain Cd concentrations were significantly correlated with total soil Cd (P < 0.001), soil pore water Cd (P < 0.001), and free Cd2+ (P < 0.001). A slight curvilinear relationship between grain Cd and soil Cd was apparent, but there was no plateau, even at the maximum soil Cd concentration of about 2.7 mg kg−1 The relationship between soil pore water Cd and grain Cd was linear for all three cultivars. The slopes were in the order 1994 > 1996 > 1999, with more Cd being taken up into the grain by Soissons grown in 1994, and least by Hereward grown in 1999. For Soissons, Cd concentration in the grain greater than the EU limit (0.24 mg kg−1 dry wt.) occurred at soil Cd less than the current UK limit of 3 mg kg−1 for soils receiving sewage sludge. In contrast, for Brigadier and Hereward, grain Cd concentrations were near to and less than the EU limit, respectively, at soil Cd concentrations of 3 mg kg−1Please view the pdf by using the Full Text (PDF) link under 'View' to the left.
Copyright © 2001.


text: 1st, I would just like to say that I'm doing this for no other reason than I have nothing better to do while getting paid at work. This isnt to bash the picks we did make. Ok so, I remember Jerry saying that they had legitimate trade back offers on the table, but decided Martin was the better value. This is my draft assuming the Saints called us 1st to move up for Cooks. And I won't be greedy, we take the same deal the cardinals got. 27 and 91for 16. 27- Demarcus Lawrence- obvious pick here, BPA=best passrusher available 47- Timmy Jernigan- as long as the drug test thing didn't scare us away I feel like this is also a pretty obvious pick. We showed a ton of interest and it was an obvious need. Fits perfectly as the 1 tech next to Melton 78- Donte Moncreif- This is where it gets interesting...my gut tells me to go with Brooks, but I don't think the war room was ever thinking FS in this draft. With D line already addressed I think this pick would come down to Moncreif, Huff, or Phillip Gaines. I went with the best athlete. 91- Trai Turner- Again, obvious pick in my opinion. There were rumors talking about us trading up for him even after drafting Martin. I think it would be a dream come true if he was still on the board with the extra pick acquired. Just a fun exercise, I'm sure there are dozens of different combinations so post what you would have done.


text: Looking for a Corvette, but want to be different? Here is the one for you! This awesome low mileage, great running, driving, and looking Corvette is "bronze!" With a black canvas convertible top! You just don't see many with this color combo. And it does run and drive great! The a/c is ice cold and everything works! Detail this one and you are ready to cruise and show! Don't let this one get away! Soon you'll be Corvette cruising in style!


text:
Screen recorder tools are an essential part of creating e-learning course content. There's no better way to demonstrate software or processes than by recording the contents of your screen and making that recording available to your students.
Most screen recorder software allow you to capture your screen contents and add voice narration to your video. But what can you do to make the experience more engaging for your viewers?
That's where Panopto can help. With a couple of clicks in the Panopto recorder, you can add a webcam to capture video of yourself as you deliver a screencast. Your two capture sources — your screen recording and your webcam — are automatically synchronized and combined into a single Panopto video, which your viewers can access on any device. Your audience will be able to see both you and the material you're presenting, which helps your learners — especially ones that might be new to e-learning — feel more comfortable with the medium.
Once viewers have access to your recording, you can help them find precisely what they're looking for using our Smart Search technology. Optical character recognition captures every word that appears on-screen in your videos, including any text in your screencasts. Additionally, our speech recognition technology indexes every word spoken during your presentation. Smart Search enables your viewers to search for a word or phrase that you've either said or appeared on your screen and automatically fast-forward to that particular part of your presentation.
To learn more about Panopto's screen recording features, watch our video below.
With Panopto, you can be sure that your viewers are getting the most out of what you have to teach them. If you'd like to learn more about delivering e-learning courses using the Panopto video platform, contact us for a demo or sign up for a free trial today.


text:
Company Profile
Observer Electronic Technology Co., Ltd. was established in 2007 and located in DaLang town, DongGuan city, GuangDong province, China, which is a high-tech enterprise with developing and producing the electric wheelchair of independent intellectual property. Observer insists on the management concept "quality first, credit paramountcy, and innovation", and adheres to the service concept "customer demand and customer satisfaction for the purpose". The unlimited electric wheelchair will provide more convenient of activity to senior citizen and handicapped. Welcome any enquiry from domestic and oversea customers and dealer; we sincerely invite you to our company for visiting.Our unlimited electric wheelchair's patent:China:03104941.9 Holand:1025497 U.S.A:10/789.150France: 0401294 Italy :MI 2004A00238 Taiwan:256353HISTORY Observer Electronic Technology Co., Ltd. (Original Observer Optical Instrument Ent.Co., Ltd.) was established at in 1982. From 1982 to 1990, we are a Professional manufacturer of designing and machining model. In this period, we have designed and manufactured a lot of high quality products and get high affirmation from every walk of life. In 1991, we added the productive department of hardware and plastic accessory. Because of our good management and reliable quality, we have achieved the trust of customers from and abroad.In 1995, we decided to product and sell finished products after seriously discussion. Till now hundreds of products were sold throughout the world and moved to China mainland.In 2007, we established Observer Electronics Technology Co.,Ltd to meet our changes that we want to extend our products. Thanks all the supporting!!
- conquer mountain snowdon for charity[2017-07-20]
- CMEF in 2015[2015-04-01]
- Observer's Chinese web site has been opened[2014-07-04]
- Best Design of Mobility Product Award 2014[2014-05-29]
- Best Design of Mobility Product Award 2014[2014-05-29]
- Best Design of Mobility Product Award 2014[2014-05-29]
- The 71st China International Medical Equipment Fair[2014-04-04]
- Rehacare&Orthopedic China 2014 ended successfully[2014-04-03]
- SoChi 2014 Paralympics Winter Games[2014-03-04]
- Rehacare&Orthopedic China 2014[2013-11-08]
Contact Person
- William Chen
- Tel:
- 0086-769-81129280
- 0086-769-81129281
- Address:
- No.8 ShunXing Road One,
Dajingtou No.2 Industrial Park,
DaLang Town,DongGuan City,


text:
20% off Posters, Art Prints, and Art Boards. Use HAPPYWALLS20
Statues on display at the Annual Sculpture in Context at the Botanic Gardens ,Dublin, Ireland.©MCN:C9EXF-2U8W3-9RE46
onward motion statues figures birds bird curlew botanic gardens textures sculpture waterfowl
Goodness, you really did a top rate job on this Martina,,, I love the edit and the thought
amazing capture!
So adorable!
beautiful work
Delightful shot, Tina !!
Great editing, very attractive subject!
wonderful capture Tina
one of the best …
They look like Ballerinas….very nice….Cris
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text: Icarus Frames Kualis Cycles Kish Fab Carrboro / North Carolina / United States Located in Carrboro, North Carolina, Kish Fabrication has been building some of the finest titanium road, mountain and cross/gravel bicycles since 1992. Founder and owner Jim Kish is well known in the bicycle industry as an expert in titanium, and shares his skills through teaching at United Bicycle Institute, Cal Poly-SLO and at the Kish Fabrication shop in North Carolina. Jim is still involved in the design, machining, welding, and customer communication during the construction of each Kish frame. Kish Fab 9220 Bracken Lane Chapel Hill, North Carolina 27516 Follow Kish Fab FacebookTwitterInstagramWebsite Share this: Share on Facebook Share on Twitter Email Link Instagram FeedPreferred Products Road Bar Full carbon fiber road handlebar with thoughtful ergonomics and geometry


text:
Call If You Need Me
04.02.17 – 05.06.17
Devening Projects is pleased to present Melissa Pokorny's most recent installation of sculpture and wall works. This is Melissa's second project with the gallery; in 2011 she participated in a "Kabinett" exhibition with Andreas Fischer. The exhibition opens on April 2 and will continue until May 6, 2017.
Melissa Pokorny's new work explores literal and metaphorical attachments, in a sort of call-and-response between people, places and things. In these imagined spaces, where collections of diverse elements meet, "stuff happens" through an expanded sense of connectedness.
Things that are meant to prop, hold, attach, or support are rendered useless (or made useful) through uncertain applications within these relational geographies. A sense of absence prevails throughout, emphasized by situations that elicit a sense of loss—of losing one's way, the loss of memory to time and distance, of losing one's mind, or the loss of self. People go missing, and things get left behind.
Melissa Pokorny lives and works in Urbana-Champaign, Illinois, where she is an Associate Professor in Painting and Sculpture at the University of Illinois. Shows at Platform Gallery in Seattle and Front Room Gallery in New York augment a long career of solo exhibitions. Select group exhibitions include New Langton Arts, Southern Exposure, Victoria Room and Yerba Buena Gardens in San Francisco; Foodhouse Gallery in Los Angeles; Columbia College, devening projects + editions, Gallery 400 and The James Hotel in Chicago; and The Richard Peeler Art Center at Depauw University in Greencastle, Indiana. Her work is held in collections on the west coast at the Berkeley Art Museum and Pacific Film Archive, the Richard L. Nelson Museum at UC Davis, Orange County Museum of Art and San Francisco Museum of Modern Art, as well as at the Richard Peeler Art Center at Depauw University.
Apport (2017)
inkjet on aluminum and foam, silicone, vinyl, ceramic, polyurethane,
Contorta Portal (2017)
printed polyester, vinyl, ironing board fabric, ceramic, trashcan,
Medium (Betula) (2017)
printed polyester, reflective fabric, vinyl, polystyrene, leather, epoxy, utility hook,
Prick (2017)
inkjet prints on aluminum, aluminum, epoxy, leather, ironing board fabric, vinyl,
Rule of Three (2017)
inkjet print on aluminum and foam, aluminum, epoxy, ceramic, nylon, vinyl, ironing board fabric,
Call if you need me (2017)
inkjet prints on aluminum and foam, aluminum, wood, epoxy, felt, vinyl, silicone,
Thing (2017)
printed polyester, ironing board fabric, ceramic, vinyl, utility hook, polyurethane,
Nedri Stafur (2017)
printed satin, aluminum, epoxy, ironing board fabric,
North (2017)
inkjet on aluminum, ceramic, cord, epoxy, vinyl, aluminum,
Olympia (2017)
inkjet print on aluminum, ceramic, vinyl, rubber band,
Skálanes (2017)
ceramic, inkjet on aluminum, vinyl,


text:
This hotel is in a pretty good location, short walk to the metro train or buses and then only two train stops to Metro Center - you could even walk there or to attractions if you wanted to. Quite decent neighbourhood with lots of eating places nearby (not just fast food) - the embassies and a few high-end hotels nearby indicate it's pretty good. It's an older building, a bit creaky, but it's quite nice and seems to have been refurbished quite recently.
The room was a reasonable size given it's an older building in DC and nice enough feeling to it; it has a bit of pokey bathroom, but it was functional. Shower was OK, but hot water takes ages to come through - it's worth turning it on about three minutes before you actually want to shower. Ceiling fan is very noisy, but towels are quite nice. The room had the appearance of being recently renovated, furnishings had a new 'period' look but were fairly lightweight, and not a lot of amenities were provided - a desk and chair but no armchair or second chair of any kind, no bedside lamp, etc. The TV was a cheap but newish LCD model, but channel selection was very poor and reception had a tendency to cut out. WiFi was okay once you got connected. The bed wasn't terrible, but a little lumpy, and pillows are sparse and low range. The Venetian blinds on the windows didn't seem that old, but were a little faulty, including one not going all the way down, and certainly didn't blackout the room, especially once day broke. Breakfast cost an extra $5 - I can't comment on it any further as I ate elsewhere. There's no in room coffee making facilities; there is a jug down at reception, but the coffee was undrinkable.
The two counter staff I dealt with didn't seem particularly friendly or helpful. They were however good enough to store my bag when I got there early, but it was just put under the staircase along with several others with free access to anyone passing by, and they never even checked my tag when I came back to check in. The elevator didn't seem to work, meaning you had to lug your luggage up the steep and narrow staircase.
Security is a concern. I was allocated a room, and when I opened the door I found the TV on, the bed had been used, and an open suitcase was sitting on the rack - obviously the room was still occupied. Went back and told reception; she didn't seem too fussed about this and just allocated me a different room, but needless to say I didn't leave any valuables in my room and deadlocked it when I was there. The hotel also shares its entrance with the associated bar with nothing really stopping bar patrons from going up the stairs, accessing the checked bags, etc.
The place is also noisy, from a front room on the third floor (this gave a bit of a view, but also plenty of noise). There's not much sound insulation, with any street noise coming straight in and floors above creaking a bit it the people above are moving around much. The first night, even after the noisy bar patrons left, still had some car parked over the road with extremely loud hip-hop music playing, along with associated noisy hoodlums, until after 3am. The second night noisy bar patrons downstairs and on the street till very late, 2am and after. The third night saw a chap downstairs having an extended, extraordinarily loud, expletive laden late night cell phone conversation, but at least the bar patrons were fewer and cleared earlier being a Sunday. Passing through the second floor on the way to my room there seemed to be a lot of noise coming through from the bar downstairs. Maybe higher level, back rooms would be quieter.
OK, so this place isn't cheap, but anywhere in central Washington is expensive, and compared to what else I could find the price isn't too bad. With some of the issue I've mentioned addressed it would be quite good, but at the moment I probably couldn't overly recommend it. On the other hand I wouldn't condemn it either. Weigh up the pros and cons I've given with the price and see what else you can come up with to match.
- Reservation Options:
- TripAdvisor is proud to partner with Expedia, Booking.com, Orbitz, Hotels.com, Travelocity, Cheap Tickets, Hotwire and TripOnline SA so you can book your The Baron Hotel reservations with confidence. We help millions of travelers each month to find the perfect hotel for both vacation and business trips, always with the best discounts and special offers.


text:
|Publication number
|Publication type
|Application number
|Publication date
|Mar 6, 2012
|Filing date
|Oct 8, 2008
|Priority date
|May 17, 2005
|Fee status
|Also published as
|Publication number
|Arup Bhattacharyya
|Original Assignee
|Micron Technology, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (20), Non-Patent Citations (10), Referenced by (2), Classifications (18), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
This Application is a Divisional of U.S. application Ser. No. 11/131,006, titled "NOVEL LOW POWER NON-VOLATILE MEMORY AND GATE STACK," filed May 17, 2005 now U.S. Pat. No. 7,612,403, (Allowed) which is commonly assigned and incorporated herein by reference.
The present invention relates generally to integrated circuits and in particular the present invention relates to non-volatile memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM functions as a read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM, such as dynamic RAM (DRAM), static RAM (SRAM) and synchronous DRAM (SDRAM), is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a memory array which includes a large number of memory cells having electrically isolated gates. Data is stored in the memory cells in the form of charge on the floating gates or floating nodes associated with the gates. Each of the cells within an EEPROM memory array can be electrically programmed in a random basis by charging the floating node. The charge can also be randomly removed from the floating node by an erase operation. Charge is transported to or removed from the individual floating nodes by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of a single bit or one byte (8 or 9 bits) at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor (FET) capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate/charge trapping layer. The cells are usually grouped into sections called "erase blocks." Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
The memory cells of both an EEPROM memory array and a Flash memory array are typically arranged into either a "NOR" architecture (each cell directly coupled to a bit line) or a "NAND" architecture (cells coupled into "strings" of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).
Floating gate memory cells are typically programmed by injecting electrons to the floating gate by channel hot carrier injection (CHE), placing the cell in a high threshold voltage state, and can be erased by hot hole injection from the substrate. Alternatively, floating gate memory cells can be programmed and erased by electron tunneling from and to the substrate by Fowler-Nordheim tunneling to put the cell in a programmed or erased threshold state. Both mechanisms require significant amounts of power and the generation of high positive and negative voltages in the memory device which can place high fields across the gate insulation layers with resulting adverse effects in device characteristics and reliability.
A problem with CHE, hot hole injection and Fowler-Nordheim tunneling is that the high energy required for their operation damages the device materials, reducing memory cell lifetimes and endurance. They can also consume large amounts of power, which is a problem in portable devices. In addition, the high voltages and fields limit the device feature scalability of the array and its support circuitry and significantly slow the write, read and erase speed of the resulting device. In particular, with Flash memory device types, CHE electron injection can generate interface states, degrade device transconductance, and enhance back-tunneling that affects charge retention and read-disturb. Fowler-Nordheim tunneling and hot hole injection can generate fixed charge centers in the tunneling insulators and shallow traps and defects in the trapping layer, thus breaking stable bonds and eventually degrading the insulator/dielectric properties of the device (limiting device endurance to a typical lifetime of less than 106 program/erase cycles). Such high power, high voltage, slow access speed, limited endurance and scaling difficulties are a typical characteristic of most commonly utilized non-volatile memory devices.
An ideal or universal memory would combine the high speed, low power and effectively infinite (1012 to 1015 program/erase cycles) write and erase endurance of RAM with the non-volatile long term data retention of a non-volatile memory. Such a memory device could be utilized by system designers to supplement or even entirely replace both RAM and ROM/Flash/non-volatile memory in computer systems and in portable devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for methods and apparatus for a non-volatile memory cell that allows for a non-volatile memory with high speed write/read/erase access, low voltage program and erase, low power usage, device feature scalability and effectively infinite endurance.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The terms wafer and substrate used previously and in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims and equivalents thereof.
Non-volatile memory devices and arrays, in accordance with embodiments of the present invention, facilitate the utilization of band-gap engineered gate stacks with asymmetric tunnel barriers in floating node memory cells. These asymmetric tunnel barrier floating node memory cells allow for low voltage direct tunneling programming and erase in NOR or NAND architecture memories. The asymmetric band-gap gate memory cell stack also contains high charge blocking barriers and deep carrier trapping sites for good charge retention. This allows memory device embodiments of the present invention to operate with the characteristics of an ideal or universal memory device. The low voltage direct tunnel program and erase capability also reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan allowing effective infinite endurance (1012 to 1015 program/erase cycles). The low voltage program and erase of embodiments of the present invention also allow for low voltage memory array design and a smaller effective oxide thickness (EOT) of the memory cell gate-stacks, allowing low power, voltage scaling, and for an overall memory array die area reduction and enabling further scaling of device features as process technology improves. Reverse and normal mode memory cell embodiments of the present invention are detailed. Other memory cell embodiments of the present invention allow multiple levels of bit storage in a single memory cell. Embodiments of the present invention arranged in NOR or NAND memory architectures are provided.
For a non-volatile memory to fulfill the role of both RAM and ROM in a system as a universal memory device, it should overcome the current limitations of non-volatile memory of limited write/erase endurance, high operating voltages, high power requirements, and limited access speeds. To do this the non-volatile memory should generally fulfill the following requirements: no more than 2� to 3� supply/logic operating voltage for conducting its read, write, or erase operations; have an effectively infinite endurance (1012 to 1015 program/erase cycles); have a limited power draw, such that it can be powered off batteries in portable devices; have a high access speed (in the range of nanoseconds to be similar to RAM access) for read and write operations; and retain stored data for 10 or more years (as currently is the standard for non-volatile memory devices). It is noted that such an ideal non-volatile memory would also benefit from lower internal operating voltages, currently and in the future, by not being limited in device feature scaling and overall design architecture due to high voltage considerations. In addition, it is noted that if a non-volatile memory, such as an embodiment of the present invention, comes close to these requirements for a universal memory device for speed of access, system architecture and design in many cases can be modified to still allow it to be used as a universal memory. Such architecture and design changes will be apparent to those skilled in the art with the benefit of the present disclosure and include, but are not limited to, multi-level memory architectures, memory system read and write caching, on-chip write caching, and memory interleaving.
As stated above, current non-volatile memory devices, due to their operating characteristics, generally cannot act as a universal memory and fulfill the role of both RAM and ROM in a computer system or portable device. Most current non-volatile memory devices require that a 10V to 20V of voltage be supplied or internally generated for programming and/or erase operations, which typically occur utilizing CHE, hot hole, or Fowler-Nordheim tunneling. Because of this high voltage requirement (5� to 10� or more of the currently common supply voltages/logic levels of 1.8V to 2.5V) the power requirements of the devices is quite high during a programming or erase operation. In addition, if high voltage is not externally supplied, the internal generation of high voltages (via internal supply circuits such as charge pumps) is itself inefficient and power consuming.
The high programming and erase voltages required by the current generation of non-volatile memory devices also dictates that channel widths and the effective oxide thickness of the individual memory cells be relatively large in order to be able to withstand the high fields generated by these voltages. This increases the size of the resulting memory array and limits the amount of scaling that can be done due to integrated circuit processing improvement. In addition, the support circuitry of the non-volatile memory device must also be designed to accommodate the elevated voltages. The increased oxide thicknesses, device separation requirements, scaling limitations, isolation wells, high voltage circuit designs and other circuit accommodations due to high voltage use typically increases the size of the resulting memory device layout by as much as 40% to 50% in current non-volatile memory devices. Furthermore, due to the large EOT of the memory cells, internal voltage generation, high voltage support circuitry designs and other characteristics of the current generation of non-volatile memory devices, access speeds are generally quite slow compared to RAM devices. In particular, write and erase operations are typically executed in milliseconds to microseconds, instead of the nanosecond execution of a write operation in a DRAM. As also detailed above, the high amount of leakage current generated by and materials damage done to the memory cells and other devices of the current generation of non-volatile memory devices by the required high voltages, fields, and high energy carriers also generally limits the endurance of the overall non-volatile memory device and its expected useful lifetime (typically 106 program/erase cycles in current non-volatile memory devices).
As stated above, conventional floating gate memory cells of the prior art are typically Field Effect Transistor (FET) devices. These devices are typically formed as three terminal devices having a source, drain and control gate connections. In a typical floating gate memory cell, source and drain regions of an opposite impurity doping are formed in an impurity doped silicon substrate and are separated by a channel region (a typical NFET transistor would have N+ doped source/drain regions in a P doped substrate, a PFET transistor would have P+ source/drains in a N doped substrate). The gate stack of the floating gate or floating node memory cell is typically formed over the channel region and/or portions of the source and drain regions and typically comprises successive layers of tunnel insulation, a floating gate or floating node, a charge blocking insulation layer and the control gate. The gate stack allows the formation of minority carriers in the channel and control of the carrier flow from the source to the drain through the channel via the voltage applied to the control gate. The floating gate or floating node is typically formed of a conductive material (such as polysilicon as a floating gate) or a non-conductive charge trapping layer (such as nitride as a floating node) and is electrically isolated between tunnel and charge blocking insulation layers. The control gate is typically formed of aluminum, tungsten, iridium, polysilicon, or other conductive material. A conductive underlayer may optionally be applied before depositing the control gate, which acts as a chemical passivation layer. This passivation layer typically consists of a thin film of TaN, TiN, HfN, or IrO2.
The electrical structure of a FET is that of a capacitor if viewed from between the channel and the control gate. If sufficient voltage is applied across the control gate and the channel will form a channel of carriers and the FET will conduct current from its source to drain region. In a floating gate memory cell FET, the electrical structure formed between the channel, floating gate and control gate is equivalent to that of two series coupled capacitors. Because of this, charge placed/trapped on the floating gate by moving carriers through the insulation layers (via charge injection or tunneling) alters the effective threshold voltage (Vth) of the floating gate memory cell FET (the voltage applied across the control gate and the channel at which a channel of carriers is formed in the channel region and the FET begins to conduct current from its source to drain region). This ability to alter the threshold voltage by trapping or removing charge from the floating gate allows data values to be stored in the floating gate memory cell and read by sensing the differing current flows through the memory cell FET from its source to drain in its programmed and unprogrammed states. The floating node memory cell FET operates similar to the floating gate memory cell FET, except that the charges are stored in a non-conductive trapping layer replacing the floating gate. It is noted that some floating node memory cells with non-conductive trapping layer, such as NROM, allow the storage of more than one bit of data in a memory cell by trapping carriers locally near and/or above each source/drain region, allowing the differing bits of data to be read by switching which source/drain region is electrically used as the source or drain.
The insulation layers of conventional floating gate memory cell FETs must have sufficient charge blocking ability for the memory cell to allow for required charge retention period (typically set at a 50% to 75% amount of the originally stored charge retained after a 10 year time period). In conventional floating gate memory cells, this is accomplished by forming the insulator layers (also known as oxide layers due to the most common forms of insulator materials utilized) of materials with sufficient thickness and high enough conduction bands to be effective tunnel barriers, preventing leakage and back-tunneling of the trapped charge. Conventional flash memory cell devices typically utilize a relatively thick SiO2 tunnel insulator layer oxide and a stack of oxide-nitride-oxide (ONO) as a charge blocking layer medium between the control gate and the floating gate. The typical effective oxide thickness (EOT) of the entire gate-stack (which affects the capacitive characteristics of the floating gate/node FET) for these conventional flash memory cells generally range from 150 nm to 200 nm in thickness. If these insulation layers of a floating gate memory cell are too thin or are formed of materials that do not have a sufficiently high conduction band, the trapped charge will leak out of the device from the floating gate or floating node through leakage current or via direct tunneling. As this leakage current increases, the floating gate device acts less and less as a non-volatile memory and more like a volatile memory device (such as DRAM) in that it must be periodically refreshed or its stored charge data contents will dissipate and be lost.
Because of these high insulator thicknesses and tunnel barriers, the effective oxide thickness (EOT) of the FET from the control gate to the channel is relatively high and therefore the voltages that must be utilized in programming and/or erasing conventional floating gate memory cells (12V to 20V for the current 90-100 nm feature size of integrated circuit process technology) are typically significantly higher than the supply voltages of the device (1.2V to 5V). As a result, such high voltage must therefore be internally generated with charge pump circuits or separately supplied from a special external source. This use of such relatively high voltage requires specialized design and layout, which, as stated above, can increase the size of the resulting memory by as much as 40% to 50% and can significantly impact the memory device's cost of fabrication. Furthermore, this use of high voltage can increase the energy utilized in erase and program significantly, and therefore increases the power requirements of the memory device. The high voltage requirements, as also detailed above, can also increase damage to the material of the insulator layers, leading to increased charge leakage and a shorter useful life (a smaller number of overall program/erase cycles) for the memory device. In addition, the relatively high fields generated by these high programming and erase voltage places limits on any future feature reductions for the part as manufacturing processes improve.
As stated above, another type of non-volatile memory cell consists of a floating node field effect transistor (FET), whereby charge is stored in local defect sites called traps characteristic of the material properties of a thin layer of dielectric that is incorporated as a part of the gate-insulator stack of the FET. These types of devices are classified as embedded trap devices, in contrast to the floating or embedded gate devices mentioned earlier. Embedded trap devices, in general, require lower programming voltages and exhibit somewhat higher programming speed and endurance due to the lower effective oxide thickness (EOT) of the gate insulator stack employed and the differing materials utilized in their construction.
A first common type of embedded trap device, which is widely utilized in many current memory devices, uses a trapping insulator where the charges are stored both at the interface and in the bulk of the trapping insulator. This kind of device usually employs a silicon (substrate)-oxide-nitride-oxide-silicon (gate) or "SONOS" gate-stack, wherein the nitride is the trapping insulator. A more recently developed second type of embedded trap device is known as a "nano-crystal" or "nano-dot" embedded trap device. In this type, silicon, germanium, or metal crystals or dots are embedded in the insulator layer (such as SiO2 or other dielectric), replacing the nitride. Defects or traps associated with the nano-crystals become centers of charge storage in these types of devices.
In both of the above described embedded trap devices, the effective oxide thickness (EOT) of the gate insulator stack can be reduced to nearly half that of the minimum EOT of a conventional floating gate type of device. Consequently, the programming voltages of embedded trap device can be reduced by nearly a factor of two (2�) compared to that of a conventional floating gate memory cell. As a result of this, embedded trap devices are generally considered to be more scalable with the development of improved integrated processing techniques. This improvement is true irrespective of the charge injection mechanism being utilized, CHE or Fowler-Nordheim tunneling. However, the high carrier energy associated with the above charge injection mechanisms still limit the reliability and endurance of such devices in a similar manner (although at a reduced level) to that of a conventional floating gate memory cell device.
The conventional floating gate and embedded trap memory cells and devices discussed above involve high energy ("hot") charge transport between the substrate and the floating gate for programming and erasure, known as channel hot electron (CHE) or hot hole injection. In CHE/hot hole programming and erasure, the field placed across the control gate and the channel is high enough to inject carriers (holes/electrons) to or from the channel to the floating gate or trapping layer across the tunnel insulator layer. Part of the energy of the hot carriers is transferred to the interface lattice between the silicon substrate and the gate oxide. As a result, interface bonds break and interface characteristics get degraded after multiple write-erase cycles. Consequently, the hot charge transport generates surface states at the silicon-oxide interface and creates local weak spots in the gate oxide that negatively affects the device by degrading the FET transconductance (Gm), enhancing the stored charge loss from the floating gate (i.e. retention loss), and reducing the endurance (i.e. operable write-erase cycles) of the device.
Programming and erasure by Fowler-Nordheim tunneling operates by field enhanced quantum mechanical tunneling of the carriers through the conduction barriers of the insulator layers to place or remove the carriers to or from the floating gate/trapping layer of the memory cell. As a result, Fowler-Nordheim tunneling takes place at reduced fields and voltages than CHE or hot hole injection. However, as an elevated voltage is required to boost the electrical field to the levels needed to induce tunneling, the energy acquired by the carriers is still high and can induce damage of the device materials, reducing memory cell endurance and the effective device lifetimes. In particular, Fowler-Nordheim tunneling can generate fixed charge centers in the tunneling insulators and shallow traps and defects in the trapping layer, thus breaking stable bonds and eventually degrading the dielectric properties of the insulators of the device. Due to the high voltages and currents required, power consumption during programming and erasure is also still significant factor in Fowler-Nordheim tunneling devices.
As stated above, both the high voltage requirements and higher leakage currents associated with the current generation of flash technology have begun to adversely affect endurance, reliability, power and speed of operation of the resulting devices. The high programming and erase voltages create high fields across the gate insulator stack resulting in gate insulator oxide degradation. This gate insulator oxide degradation impacts device non-volatility (retention) reliability and limits the overall device endurance. The high fields also severely limit the amount the device feature geometry can shrink beyond the current generation. The high programming voltages are also known to induce a strong capacitive cross-coupling between a selected bit and adjacent unselected bits with the same wordline (or bitline) or between adjacent wordlines or bitlines. This cross-coupling has become a critical issue in the overall memory device speed and scaling. Cross-coupling issues typically increase as voltage levels are increased or the memory device features are scaled smaller without a commensurate reduction in voltage levels.
In conventional SONOS type Flash memory cell devices or for Flash memory cell devices using nano-crystal traps, the tunnel oxide thickness can generally be reduced to around 4 nm and EOT of the charge blocking oxide/NO layer to around 5-6 nm while still ensuring approximately 10 years of charge retention at 85� C. (assuming sufficient fraction of original trapped charge, typically 50% to 75%, retained at the end-of-life such that the logic level may be appropriately sensed). This sets an overall minimum gate stack EOT of approximately 10 nm and, consequently, a programming voltage level of approximately 10 volts at the low end for such devices, assuming a reasonable programming speed in the range of 100 μsec to 1 msec. For the above tunnel oxide thickness, electron transport during the programming typically takes place via Fowler-Nordheim tunneling. However, to meet the programming speed, the initial electron current density typically must exceed 1 E-3 A/cm2, requiring a field across the tunnel oxide exceeding 10E6 V/cm, limiting the amount of programming voltage reduction realistically possible. The above oxide thicknesses typically will also allow reverse leakage current for the stored electrons of <1E-12 A/cm2, which allows the resulting devices to meet the requirement of 10 years of charge retention at 85� C.
If the tunnel oxide thickness in a conventional floating gate or floating node memory cell is scaled below 3.2 nm, transport takes place via direct tunneling. Unlike transport by Fowler-Nordheim tunneling, wherein electrons need to acquire sufficient energy to exceed the energy barrier (typically 3.2 eV for SONOS devices), direct tunneling is exponentially dependent on the tunneling distance and takes place at significantly lower electron energy. Therefore, electron current density can be many orders of magnitude higher while at low voltages when the tunnel oxide is very thin (e.g., 1 nm-1.5 nm). Consequently, both programming speed could be enhanced as well as programming power significantly reduced if electron transport could take place by direct tunneling. However, as stated above, for very thin tunnel oxide the reverse leakage is also very high as the likelihood of back-tunneling is also typically increased by the thin oxides. As such, the retention of such pure direct tunneling devices fails to meet non-volatility requirements of holding the stored charge for any significant time duration, meaning that the device has failed and may not be considered an operative non-volatile memory device (without employing frequent refreshing of the memory states).
Because of the above stated reasons, oxide-based non-volatile memory cell devices, such as traditional Flash, SONOS, or Nano-crystal memory cells are limited in voltage, power and speed scalability. Additionally, because of the high fields required across the oxide insulation layers, such oxide-based devices are also limited in reliability and endurance.
Generally, to meet universal memory device operating characteristics, non-volatile memory cells devices must program and erase at a fast access speed at acceptably low voltage and power, while concurrently exhibiting long retention, enhanced endurance and reliability. In order to do this they typically must satisfy the following requirements:
To meet these requirements, embodiments of the present invention utilize band-gap engineered gate-stacks that allow low voltage program and erase of the memory cells via the direct tunneling of carriers to or from the trapping layer. The band-gap engineered gate stack of the present invention incorporate asymmetric tunnel barriers having multiple layers of direct tunnel layers of increasing conduction band offset and increasing values of K (dielectric constant) to provide very high electron current density during programming at reduced voltage drop across the direct tunnel layers, fulfilling requirements 2) and 3) stated above. The combination of deep charge trapping centers and asymmetric tunnel barriers of increasing band offset provides large reverse tunneling barrier to promote the required charge retention, thereby fulfilling requirement 4) above. Appropriate selections of charge trapping material and embedded nanocrystals enable fulfillment of requirement 5) while the dielectric constant values of the entire gate stack layers help fulfill requirement 1).
As stated above, in direct tunneling of carriers, the carriers are quantum mechanically tunneled into the floating gate/trapping layer under low energy conditions. To overcome limitations of reverse direct tunneling operation, the gate-stack of the embodiments of the present invention utilizes multiple layers of material that are band-gap engineered with increasing band-gap offsets and high K values to form an asymmetric band-gap tunnel insulator layer. This asymmetric band-gap tunnel insulator layer is very efficient in charge transport in one direction and yet becomes very retarded in the reverse transport direction, presenting a large barrier. The asymmetric band-gap tunnel insulator layer allows for a low voltage direct tunneling to the trapping layer of the device when a programming field is applied across it utilizing the stepped internal fields of the band-gaps of the asymmetric band-gap tunnel insulator layers, while the same stepped band-gap offsets and high K dielectrics present a large band-gap and consequently large energy barrier to the charges so trapped to prevent back-tunneling and maintain the required long term charge retention.
Because of this direct tunneling programming and erasure, embodiments of the present invention provide a non-volatile memory cell having an insulator stack with a low overall EOT, allowing them to be operated at very low power and at low programming voltage. The low voltage program and/or erase operations of embodiments of the present invention also reduce damage in the material of the device due to the tunneling/injection of carriers through the insulator layers (the injected carriers are "cool" and never gain enough energy to affect the lattice or material bonds). In addition, embodiments of the present invention allow for improved scaling by allowing the memory to employ smaller effective oxide thicknesses (EOT) and low voltage layout and design in the array and support circuitry of the resulting memory device.
The band-gap engineered tunneling medium of embodiments of the present invention consists of multiple layers of direct tunnel layers of increasing conduction band offset (each following tunnel layer has a higher conduction band energy level than the previous layer) and increasing values of K (dielectric constant) to provide very high electron current density during programming at reduced voltage drop across the direct tunnel layers, allowing for high speed, low power programming.
For a conventionally structured normal mode memory cell (a normal gate-insulator stack or NGIS) the charge blocking layer and tunnel layer placement are positioned in the gate-insulator stack, such that the charge blocking layer is between the control gate and the floating node and the tunnel insulator is between the channel and the floating node. In this arrangement, charge transport takes place primarily between the channel and the trapping layer (floating node) during programming and erasure. In operation, the stepped band-gap arrangement facilitates direct tunneling of electrons layer to layer from the channel to the trapping layer with a low applied field. After tunneling to the trapping layer, the combined asymmetric stepped energy barriers, long back tunnel distance, and optional deep level charge traps act to reduce charge leakage to the substrate and provide adequate charge retention for non-volatile usage. A high K charge blocking layer and passivation layer are also integrated in the gate-stack for such embodiment of the present invention to maintain low charge leakage to the control gate from the trapping layer.
In another embodiment of the present invention, nano-crystals are embedded in a trapping layer which contains deep high density traps to provide a large trapped charge density, enhancing logic level separation and increasing stored charge, while minimizing the adverse effects of coulomb blockade and quantum confinement. The use of deep traps and/or nano-crystals further increase charge retention by providing deep quantum wells at the trapping layer, further increasing the potential barrier that the trapped charges must overcome to escape from the trapping layer or back-tunnel through.
Programming the above normal mode memory cell embodiments of the present invention is accomplished by providing a voltage across the channel and the control gate to apply a field across the multiple tunnel layers and induce direct tunneling of electrons from the channel to the trapping layer. In multi-bit storage, the voltage is applied between a selected source/drain region (with memory cell FET operating with the selected source/drain region acting as a source and the second source/drain region acting as the drain) and the control gate, tunneling electrons to the trapping layer directly adjacent to the selected source/drain region. The memory cell is then read by reversing the operational function of the first and second source/drain regions (the selected source/drain region acting as the drain and the second source/drain region acting as the source).
Erasure in the above normal mode embodiments of the present invention is also accomplished by direct tunneling. Although the erase operation is also by direct tunneling, the energy barriers are successively higher due to the asymmetric stepped barriers present in the tunnel layers, resulting in a relatively slower erase speed when compared to the write operation. An elevated negative voltage is applied across the channel and the control gate, applying a field across the multiple tunnel layer and inducing direct tunneling of electrons from the trapping layer to the channel to erase the memory cell. As stated above, it is noted that this direct tunneling erase is typically slower in operation than the direct tunnel program operation due to having to tunnel through the entire combined thickness and barrier of the asymmetric band-gap tunnel insulator. Higher voltages can also be applied to speed the erase operation, however, this will have the effect of increasing device structure damage. At the same time, the asymmetric barrier significantly improves the charge retention, since trapped electrons cannot assume enough energy to get into the conduction band when the memory cell is in the standby state. The relatively slower erase, however, can be offset by utilization of a block erase operation, where a large block of bits is erased in parallel.
Although the low voltage direct tunneling erase is in a relatively slower speed than the direct tunnel programming due to the asymmetric band-gap tunnel insulator, it is noted that non-volatile device erasure is typically infrequent and, in block erase based devices, can be done on a parallel basis, as stated above. It is also noted that memory cell erasure of embodiments of the present invention can also be accomplished by conventional hot-hole injection, Fowler-Nordheim tunneling, or by enhanced tunneling of holes from the control gate.
It is also noted that the appropriate selection of gate passivation layers as well as band engineered tunnel layers can be utilized to enhance erase speed through simultaneous hole injection from the control gate during erase operation. In this form of erasure, a band-gap engineered charge blocking insulation layer is formed between the control gate and the trapping layer, which allows for efficient and enhanced tunneling of holes from the control gate to the trapping layer at an appropriate control gate voltage level. At the above voltage level, an effective field is established across the charge blocking layer, between the electrons trapped in the charged trapping layer to the control gate, such that holes (which have a higher effective mass than electrons) are efficiently tunneled across the charge blocking layer. As more and more trapped electrons are compensated from the trapping layer by hole tunneling and trapping, the effective field between the control gate and the trapping layer across the charge blocking layer diminishes until the trapping layer is discharged or compensated (at this point, a balanced steady state of hole tunneling from the control gate and electron tunneling from the channel to the trapping layer is established). As a result of this balanced steady state, memory cell erasure is self-limiting and the possibility of memory cell overerasure diminished. Such method of memory cell erasure through hole injection is detailed in U.S. Pat. No. 7,279,740, titled "BAND-ENGINEERED MULTI-GATED NON-VOLATILE MEMORY DEVICE WITH ENHANCED ATTRIBUTES," issued Oct. 9, 2007 and U.S. Pat. No. 6,784,480, titled "ASYMMETRIC BAND-GAP ENGINEERED NONVOLATILE MEMORY DEVICE," issued Aug. 31, 2004, both of which are commonly assigned.
For the reverse mode memory cell (a reverse gate-insulator stack or RGIS) the charge blocking layer and tunnel layer placement are reversed in the gate-insulator stack, such that the charge blocking layer is now between the channel and the floating node and the tunnel insulator is between the control gate and the floating node. In this arrangement, charge transport takes place primarily between the control gate and the trapping layer (floating node) during programming and erasure. Programming such a reverse mode memory cell is accomplished by providing a voltage to the substrate while the control gate of the cell to be programmed is held to a low or ground potential. Enhanced electron injection from the control gate, increased transport through the direct tunnel layers due to increasing conduction band offset and increasing K values, and subsequent trapping in the deep trapping centers in the trapping layer fulfills the programming requirements. As a result, the threshold of the programmed cell is raised and data is stored. Reading is accomplished in a similar manner as a normal mode memory cell.
For the reverse mode memory cell, erasure is accomplished by imposing an appropriate positive potential at the control gate while the substrate is held at a low (even to a slightly negative) or ground potential. During erasure, the electrons from the trapping layer returns to the control gate by direct tunneling. Block erasure offsets somewhat reduced erase speed similar to the normal mode memory cell device. Reading of the erased state is accomplished in a similar manner as carried out in the normal mode device.
Reverse mode memory cells have an advantage over normal mode memory cells in that both the program and erase operations can be accomplished with positive voltages only, thereby simplifying support circuitry. In addition, appropriate selection of channel passivation layers (such as SiO2 and oxygen-rich SiON of refractive index γ=1.5 which can be utilized to saturate the dangling bonds of the silicon substrate) between the channel and the charge blocking layer as well as band engineered charge blocking layers can be utilized to enhance erase speed through simultaneous hole injection from the channel during erase operation.
Although much of the focus of the embodiment is primarily on the normal mode memory cell, it should be noted that the reverse mode memory cell equally embraces the underlying concepts of the invention towards providing a universal memory device. Furthermore, in actual implementation, the reverse mode memory cell may exhibit certain advantages in speed-power-density tradeoffs over normal mode memory cells.
This programming and erasure by the transport of electrons by direct tunneling allows embodiments of the present invention to consume orders of magnitude lower power compared to conventional flash memory cells and devices. Writing speed is significantly enhanced as electrons tunnel directly from one direct tunnel layer into the next through successive layers of low barrier energy.
As stated above, the tunnel insulation layer region of embodiments of the present invention consists of two or more layers of dielectric material with increasing conduction band offsets and/or increasing dielectric K values, allowing directionally asymmetric direct tunneling efficiency of carriers through the tunnel layer. The layers of dielectric material can be selected from any commonly utilized insulator materials (oxides, mixed oxides, nitrides, oxynitrides, mixed oxynitrides, or silicates) so long as they are arranged in increasing band-gap offsets and, preferably, higher K dielectric materials to help reduce the EOT of the resulting memory cell. Examples of these insulator materials include, but are not limited to, silicon dioxide (SiO2), titanium dioxide (TiO2), hafnium oxide (HfO2), zirconium oxide, Praseodymium Oxide (Pr2O3), alumina (Al2O3), mixed oxide hafnium and aluminum, mixed oxide of hafnium and titanium, mixed oxide of hafnium and silicon, silicon oxynitride (SiON), SiN, AlN, HfN, mixed oxynitrides of hafnium and silicon, etc. These layers of increasing band-gap offset dielectric material are typically deposited over the channel region of the memory cell during manufacturing processing utilizing atomic layer deposition (ALD) or other appropriate deposition processes.
For example, the tunnel region may be a composite of one or more mono layers of SiO2(band gap 9 eV, K=3.9), ALD grown on silicon substrate, followed by a one or more mono-layers of silicon nitride (SiN, band offset 1.03 eV, K=7) or alumina (Al2O3, band offset: 4.5 eV, K=10) to be followed by a one or more mono-layers of HfO2 (band offset: 1.65 eV, K=24) or Pr2O3 (band offset: 1.9 eV; band gap 3.9 eV; K=30) or TiO2 (band offset 3.15 eV; K=60) for a three layer tunnel layer structure. A two-layer tunnel structure can consist of SiO2/Pr2O3 or SiO2/TiO2, SiO2/HfO2, etc. It is noted that other two, three, or more layer asymmetric band-gap tunnel regions of embodiments of the present invention are also possible and will be apparent to those skilled in the art with the benefit of the present disclosure, and as such the above examples should not be considered as limiting.
It is also noted that, in one embodiment of the present invention, the successive layers of the asymmetric band-gap tunnel layer not only have increasing band offsets, but also have material of higher K values and increased direct tunnel thickness to minimize the effective EOT of the tunnel layer composite and optimize voltage drop across the each of the tunnel layers. In embodiments of the present invention, the physical thickness of the composite tunnel layer can be preferably designed to be around 3 nm or less and the EOT around 1.5 nm or less for low voltage operation. For example, a typical tunnel layer may consist of 0.8 nm of SiO2+1 nm of SiN+1 nm of HfO2 (EOT=1.6 nm) or 0.8 nm of SiO2+1 nm of HfO2+1.5 nm of Pr2O3 (EOT=1.3 nm) or 0.8 nm of SiO2+1 nm of HfO2+2 nm of TiO2 (EOT˜=1.2 nm).
In order to improve retention and charge density, metal nano-crystal memory devices have been utilized that contain certain metal or semiconductor nano-dots or nano-crystals including, but not limited to, tungsten, silicon, germanium, cobalt, platinum, gold, iridium, and palladium to provide deep energy trapping sites at the metal-insulator interface due to large work function difference. However, such devices require optimum dot size and dot separation to facilitate effective retention of trapped charges due to quantum confinement effect (to prevent electrons from tunneling between adjacent trapping sites within the trapping layer or tunneling back to silicon). In addition, coulomb blockade (where like charges repel each other) could further degrade charge retention, necessitating that multiple charge trapping per nano-dot should be avoided.
If coulomb blockade is minimized such that effectively a single electron is captured for every available nano-dot trapping site and the nano-dot size and separation are optimized to reduce the adverse effects of quantum confinement, the effective charge trapping density of nano-dot trapping layer is limited to around 1E12/cm2 to 2E12/cm2 regardless of the actual density of nano-dots. Consequently, the effective charge trapping density for conventional nano-dot or nano-crystal devices is limited. This effective charge trapping density limitation can be overcome if an optimum geometry and distribution of nano-crystals were embedded in insulating trapping layers that also contained a high density of naturally occurring deep traps, such as SiN, AlN, Ta2O5, TiO2, or SiON. If this trapping layer is also formed of high K material, the EOT of the entire stack would also be reduced.
The above concept is utilized for the trapping medium in one embodiment of the invention. In this approach, the trapping medium may consist of an appropriate thickness of an insulator having a large number of naturally occurring trap sites, such as silicon oxynitride (SiON, trap depth: Et>1.2 eV, refractive index 1.8, K=7) or HfO2 (trap depth: Et=1.5 eV, K=24), silicon nitride (Si3N4, trap depth: Et=1.0 eV, refractive index=2.0, K=7), silicon-rich silicon nitride, tantalum oxide, (Ta2O5, Et=2.7 eV, K=26) aluminum nitride (AlN, trap depth >1.0 eV, K=10) or TiO2 (trap depth: Et=0.9 eV; K=60). The trapping medium is then embedded with nano-crystals/nano-dots that can include, but are not limited to tungsten, silicon, germanium, cobalt, platinum, iridium, gold, or palladium in sizes ranging from 1.5 nm to 4 nm with a separation of 3.5 nm to 5 nm to further increase the number of trapping sites.
As stated above, the silicon oxy-nitride (SiON) utilized in the above example provides additional charge trapping sites. The nitrogen-rich SiON has an atomic silicon concentration of approximately 38%-40%, an atomic oxygen concentration of approximately 20%, and an atomic nitrogen concentration of approximately 40%, resulting in a trapping layer with a dielectric constant of approximately 7, refractive index of approximately γ=1.8 and a charge trap density of 8E12-E13/cm2. In the above SiON, deep energy traps are associated with larger concentrations of Si—O—N bond "defects" in the silicon oxy-nitrides. Such a trapping layer of an embodiment of the present invention would provide an effective charge density in the desired range of 5E12/cm2 to 1E13/cm2 without the adverse effects on retention due to coulomb blockade or quantum confinement. It is noted that other charge trapping insulator materials may also be utilized in embodiments of the present invention as the charge trapping layer.
For one embodiment of the present invention, the charge blocking layers are preferably comprised of a single or composite layer of large K dielectric material layers such as Al2O3 (K=10) or Pr2O3 (K=30) or TiO2 (K=60) of thickness greater than 6 nm, to provide a large electron energy barrier and prevent direct tunneling of trapped charges to the control gate while helping minimize the overall EOT of the gate-stacks. As stated above, charge blocking layers have been disclosed that allow for erasure of the data stored in the trapped charge on the trapping layer or floating gate of the memory cell by allowing the tunneling or injection of hole or electron carriers through the charge blocking layer from the control gate. It is noted, however, that multiple insulators can be utilized in charge blocking layers of embodiments of the present invention, including, but not limited to insulators from the oxide, mixed oxide, nitride, oxynitrides, mixed oxynitrides, and silicate families.
For the reverse mode device, similar concepts apply for the charge blocking layer which is deposited on top of the silicon substrate. To passivate the silicon-gate insulator interface, one to three mono-layers of SiO2 or SiON may be employed before a high K charge blocking layer (e.g., Al2O3 or Pr2O3) is deposited. Such interface has the added advantage of providing a fixed negative charge to reduce electron injection from the substrate during programming and erase.
The control gate of embodiments of the present invention typically consist of a thin passivating conductive underlayer of HfN, TiN, IrO2 or TaN (for process integration) with either a polysilicon gate or any other appropriate metal gate (such as aluminum, iridium, or tungsten) formed over it.
The total EOT for a gate stack of an embodiment of the present invention made with the above materials and specifications will typically range from EOT=2.5 nm to EOT=6.5 nm with physical thickness ranging (excluding gate electrode thickness) from 10 nm and upward, have a programming voltage as low as 1.5V, and an average field as low as 1.0E6V/cm2. This allows memory cells and devices of embodiments of the present invention to provide voltage scalability and low power consumption levels not available in other current memory devices.
For the normal mode device,
Specifically, in one embodiment, the tunnel insulator layer 112 contains three layers of material, a first layer of 0.5 nm of SiO2 (K=4), having a band-gap of approximately 9 eV formed over the channel region 108 and silicon substrate 102, which has a band-gap of 1.1 eV. A second layer of 1 nm of SiN (band offset 1.03 eV, K=7) or Al2O3, (band gap: 8.8 eV, K=10) is formed over the first layer of SiO2. And a third layer of 1 nm of HfO2 (band-gap: 4.5 eV, K=24) is formed over the second layer.
The trapping layer 114 is formed of a layer of 5-7 nm of TiO2 (band-gap of approximately 3.15 eV, K=60) with 3.5-4.0 nm of embedded Cobalt nano-dots, having a resulting EOT of nearly 0.3 nm. Alternatively, the trapping layer could be a single layer of aluminum nitride (AlN, K=15) or nitrogen-rich SiON (of refractive index of approximately γ=1.8 and K=7) of appropriate thickness containing deep traps (Et>1.0 eV). The charge blocking layer 116 is formed of 10 nm of Al2O3, (band gap: 8.8 eV, K=10), Pr2O3 (band gap: 3.9 eV, K=30), TiO2 (band gap: 3.15 eV, K=60) with an EOT as low as 0.67 nm. The control gate 118 is then typically formed of polysilicon, tungsten, iridium, or aluminum and may include an initial passivation layer 117, such as a thin layer of HfN, TaN, IrO2 or TiN, formed over the charge blocking layer 116.
In another embodiment, the tunnel insulator layer 112 also contains three layers of material, a first layer of 0.5 nm of SiO2 (K=4), having a band-gap of approximately 9 eV formed over the channel region 108 and silicon substrate 102, which has a band-gap of 1.1 eV. A second layer of 1 nm of SiN (band offset 1.03 eV, K=7) or oxygen-rich silicon oxy-nitride, SiON, (refractive index of approximately γ=1.55, band-gap 7.3 eV, and K=5) or Al2O3, (band gap: 8.8 eV, K=10) formed over the first layer of SiO2. And a third layer of 1.5 nm of HfO2 (band-gap: 4.5 eV, K=24) formed over the second layer. The effective oxide thickness (EOT) of these three layers could be as low as 1.32 nm. The oxygen-rich silicon oxy-nitride (SiON, with refractive index of approximately γ=1.55) has an atomic oxygen concentration of >=46%, while its atomic silicon concentration is <=33%. The corresponding nitrogen-rich silicon oxy-nitride (SiON, with a refractive index of approximately γ=1.8) has an atomic oxygen concentration of <=25%, while the atomic nitrogen concentration is approximately 40%.
The trapping layer 114 is formed of a layer of 6 nm of HfO2 with 3.5-4.0 nm of embedded Cobalt nano-dots, having a resulting EOT of 0.3 nm. The charge blocking layer 116 is formed of 10 nm of TiO2 (K=60) with an EOT of 0.67 nm. And the gate electrode 118 formed of 10 nm of TiN as a passivation layer 117 and doped polysilicon.
Total combined EOT of the gate-stack 110 for the above example can be as low as 2.3 nm and the total physical insulator thickness is 19 nm. Such a device would yield the following characteristics: programming voltage+/−1.5V; voltage coupling to tunnel layer: 0.86V (coupling coefficient: 0.574); trap density: >5E12/cm2; Logic Separation: >0.5V (100 electron trapping/storage) per device. Average programming/erase electric field: <1E6V/cm2.
It is noted, as detailed above, that multiple insulators can be utilized in tunnel layers of embodiments of the present invention, including, but not limited to insulators from the oxide, mixed oxide, nitride, oxynitride, mixed oxynitride, and silicate families.
For the reverse mode device,
On a read access the row address is latched and decoded by row decode circuit 220, which selects and activates a row/page (not shown) of memory cells across a selected memory bank. The bit values encoded in the output of the selected row of memory cells are coupled to a local bit line (not shown) and a global bit line (not shown) and are detected by sense amplifiers 222 associated with the memory bank. The column address of the access is latched and decoded by the column decode circuit 224. The output of the column decode circuit 224 selects the desired column data from the internal data bus (not shown) that is coupled to the outputs of the individual read sense amplifiers 222 and couples them to an I/O buffer 226 for transfer from the memory device 200 through the data interface 208.
On a write access the row decode circuit 220 selects the row page and column decode circuit 224 selects write sense amplifiers 222. Data values to be written are coupled from the I/O buffer 226 via the internal data bus to the write sense amplifiers 222 selected by the column decode circuit 224 and written to the selected non-volatile memory cells (not shown) of the memory array 212. The written cells are then reselected by the row and column decode circuits 220, 224 and sense amplifiers 222 so that they can be read to verify that the correct values have been programmed into the selected memory cells.
As previously stated, the two common types of EEPROM and Flash memory array architectures are the "NAND" and "NOR" architectures, so called for the similarity each basic memory cell configuration has to the corresponding logic gate design. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix similar to RAM or ROM. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines (word lines) and their drains are coupled to column bit lines. The source of each floating gate memory cell is typically coupled to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line coupled to their gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current from the coupled source line to the coupled column bit lines depending on their programmed states. A column page of bit lines is selected and sensed, and individual data words are selected from the sensed data words from the column page and communicated from the memory.
An EEPROM or Flash NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word lines. However each memory cell is not directly coupled to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. This allows a NAND array architecture to have a higher memory cell density than a comparable NOR array, but with the cost of a generally slower access rate and programming complexity.
A NAND architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each floating gate memory cell of the series coupled string, restricted only by the memory cells of each string that are selected to be read. This places the current encoded stored data values of the row of selected memory cells on the column bit lines. A column page of bit lines is selected and sensed, and then individual data words are selected from the sensed data words from the column page and communicated from the memory device.
It is also noted that other memory cells, memory strings, arrays, and memory devices in accordance with embodiments of the present invention are possible and should be apparent to those skilled in the art with benefit of the present disclosure.
Non-volatile memory devices and arrays have been described that utilize asymmetric band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. The low voltage program and erase also allow for low voltage memory array design and a smaller effective oxide thickness (EOT) of the memory cell gate-stacks, allowing for an overall memory array die area reduction and enabling further scaling of device features as process technology improves. Reverse and normal mode memory cell embodiments of the present invention are detailed. Memory cell embodiments of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. These characteristics allow memory device embodiments of the present invention to operate within the definition of an ideal or universal memory device, capable of replacing both DRAM and ROM in a system.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
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|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Aug 19, 2015
|Fee payment
Year of fee payment: 4
|May 12, 2016
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August 27, 2014
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North suburbs
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Imported from Italy and made from seasoned Beech wood, this robust 26 lb studio easel can adjust sizes and heights to take canvases as large as 70" high. The additional canvas height is achieved by the use of an extension to the central support which can be fitted or removed as required. To paint the edges of your canvas, the Bettina features removable metal screws on spacers. These spacers offset the canvas and eliminate the problem of finishing the painting at the edge. Locking castors keep this sturdy and durable easel from moving while you paint!
|Key Features:
Made from seasoned Beech wood Castors for mobility Locking casters to keep sturdy Adjustable height to fit larger canvases as 70" high
|Perfect For:
Creating and displaying large works of art Working seated or standing up Artists of all skill levels
Dimensions: 27"x21", Height 75"/118", Weight 26 lbs