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MIPS IV Instruction Set. Revision 3.2 By Charles Price September, 1995
- Reynold Morton
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1 MIPS IV Instruction Set Revision 3.2 By Charles Price September, 1995
2 Copyright 1995 MIPS Technologies, Inc. ALL RIGHTS RESERVED U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS and/or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor/manufacturer is MIPS Technologies, Inc., 211 N. Shoreline Blvd., Mountain View, CA R2, R3, R6, R4, R44, R42, R8, R43 and R1 are trademarks of MIPS Technologies, Inc. MIPS and R3 are registered trademarks of MIPS Technologies, Inc. The information in this document is preliminary and subject to change without notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of the product described herein to improve function or design. MTI does not assume liability arising out of the application or use of any product or circuit described herein. Information on MIPS products is available electronically: (a) Through the World Wide Web. Point your WWW client to: (b) Through ftp from the internet site sgigate.sgi.com. Login as ftp or anonymous and then cd to the directory pub/doc. (c) Through an automated FAX service: Inside the USA toll free: (8) (8-IGO-MIPS) Outside the USA: (415) (call from a FAX machine) MIPS IV Instruction Set ii
3 MIPS Technologies, Inc. 211 North Shoreline Mountain View, California MIPS IV Instruction Set iii
4 MIPS IV Instruction Set iv
5 MIPS IV Instruction Set v
6 vi MIPS IV Instruction Set
7 Revision History 2. (Jan 94): First General Release This version contained incorrect definitions for MSUB and NMSUB. It did not contain the RECIP and RSQRT instructions. It contained incomplete or erroneous information for LL, LLD, SC, SCD, SYNC, PREF, and PREFX. All copies of this version of the document should be destroyed 2.2 (Jul 94): Mandatory Replacement of Rev 2. This version should probably have been 3. since it is a major content change. 3. (Oct 94): This version is issued with no known errors. It includes the late changes to the MIPS IV definition including the reintroduction of RECIP and RSQRT and the definition of the multiply-accumulate instructions as unfused (rounded) operations. Add itemized instruction lists in the discussion of instruction functional groups. Add a more complete description of FPU operation Correct problems discovered with Revision (Jan 95): Correct minor problems discovered with Revision (Sep 95): Revise the opcode encoding tables significantly. Correct minor problems discovered with Revision 3.1. CPU Instruction Set MIPS IV Instruction Set. Rev 3.2
8 Changes From Previous Revision Changes are generally marked by change bars in the outer margin of the page -- just like the bar to the side of this line (sorry; not visible in HTML). Minor corrections to punctuation and spelling are neither marked with change bars nor noted in this list. Some changes in figures are not marked by change bars due to limitations of the publishing tools. CVT.D.fmt Instruction Change the architecture level for the CVT.D.L version of the instruction from: to: MIPS III CVT.S.fmt Instruction Change the architecture level for the CVT.S.L version of the instruction from: to: MIPS III LWL Instruction In the example in Fig. A-4 the sign extension After executing LWL $24,2($) should be changed from: no cng or sign ext to: sign bit (31) extend. The information in the tables later in the instruction description is correct. MOVF Instruction Change the name of the constant value in the function field from: MOVC to: MOVCI There is a corresponding change in the FPU opcode encoding table in section B.12 with opcode=special and function=movc, changing the value to MOVCI. MOVF.fmt Instruction Change the name of the constant value in the function field from: MOVC to: MOVCF There is a corresponding change in the FPU opcode encoding table in section B.12 with opcode=cop1, fmt = S or D, and function=movc, changing the value to MOVCI. MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
9 MOVF Instruction Change the name of the constant value in the function field from: MOVC to: MOVCI There is a corresponding change in the FPU opcode encoding table in section B.12 with opcode=special and function=movc, changing the value to MOVCI. MOVT.fmt Instruction Change the name of the constant value in the function field from: MOVC to: MOVCF There is a corresponding change in the FPU opcode encoding table in section B.12 with opcode=cop1, fmt = S or D, and function=movc, changing the value to MOVCI. CPU Instruction Encoding tables Revise the presentation of the opcode encoding in section A 8 for greater clarity when considering different architecture levels or operating a MIPS III or MIPS IV processor in the MIPS II or MIPS III instruction subset modes. There is a separate encoding table for each architecture level. There is a table of the MIPS IV encodings showing the architecture level at which each opcode was first defined and subsequently modified or extended. There is a separate table for each architecture revision Ι II, II III, and III IV showing the changes made in that revision. FPU Instruction Encoding tables Revise the presentation of the opcode encoding in section B.12 for greater clarity when considering different architecture levels or operating a MIPS III or MIPS IV processor in the MIPS II or MIPS III instruction subset modes. There is a separate encoding table for each architecture level. There is a table of the MIPS IV encodings showing the architecture level at which each opcode was first defined and subsequently modified or extended. There is a separate table for each architecture revision Ι II, II III, and III IV showing the changes made in that revision. CPU Instruction Set MIPS IV Instruction Set. Rev 3.2
10 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
11 A CPU Instruction Set A. 1 Introduction This appendix describes the instruction set architecture (ISA) for the central processing unit (CPU) in the MIPS IV architecture. The CPU architecture defines the non-privileged instructions that execute in user mode. It does not define privileged instructions providing processor control executed by the implementation-specific System Control Processor. Instructions for the floatingpoint unit are described in Appendix B. The original MIPS I CPU ISA has been extended in a backward-compatible fashion three times. The ISA extensions are inclusive as the diagram illustrates; each new architecture level (or version) includes the former levels. The description of an architectural feature includes the architecture level in which the feature is (first) defined or extended. The feature is also available in all later (higher) levels of the architecture. MIPS I MIPS II MIPS III MIPS IV MIPS Architecture Extensions CPU Instruction Set MIPS IV Instruction Set. Rev 3.2-1
12 The practical result is that a processor implementing MIPS IV is also able to run MIPS I, MIPS II, or MIPS III binary programs without change. The CPU instruction set is first summarized by functional group then each instruction is described separately in alphabetical order. The appendix describes the organization of the individual instruction descriptions and the notation used in them (including FPU instructions). It concludes with the CPU instruction formats and opcode encoding tables. A. 2 Functional Instruction Groups CPU instructions are divided into the following functional groups: Load and Store ALU Jump and Branch Miscellaneous Coprocessor A. 2.1 Load and Store Instructions Load and store instructions transfer data between the memory system and the general register sets in the CPU and the coprocessors. There are separate instructions for different purposes: transferring various sized fields, treating loaded data as signed or unsigned integers, accessing unaligned fields, selecting the addressing mode, and providing atomic memory update (read-modify-write). Regardless of byte ordering (big- or little-endian), the address of a halfword, word, or doubleword is the smallest byte address among the bytes forming the object. For big-endian ordering this is the most-significant byte; for a little-endian ordering this is the least-significant byte. Except for the few specialized instructions listed in Table A-4, loads and stores must access naturally aligned objects. An attempt to load or store an object at an address that is not an even multiple of the size of the object will cause an Address Error exception. Load and store operations have been added in each revision of the architecture: MIPS II 64-bit coprocessor transfers atomic update MIPS III 64-bit CPU transfers unsigned word load for CPU MIPS IV register + register addressing mode for FPU -2 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
13 Tables A-1 and A-2 tabulate the supported load and store operations and indicate the MIPS architecture level at which each operation was first supported. The instructions themselves are listed in the following sections. Table A-1 Load/Store Operations Using Register + Offset Addressing Mode. Data Size Load Signed CPU coprocessor (except ) Load Unsigned Store Load Store byte I I I halfword I I I word I III I I I doubleword III III II II unaligned word I I unaligned doubleword III III linked word II II (atomic modify) linked doubleword (atomic modify) III III Table A-2 Load/Store Operations Using Register + Register Addressing Mode. floating-point coprocessor only Data Size Load Store word IV IV doubleword IV IV A Delayed Loads The MIPS I architecture defines delayed loads; an instruction scheduling restriction requires that an instruction immediately following a load into register Rn cannot use Rn as a source register. The time between the load instruction and the time the data is available is the load delay slot. If no useful instruction can be put into the load delay slot, then a null operation (assembler mnemonic NOP) must be inserted. In MIPS II, this instruction scheduling restriction is removed. Programs will execute correctly when the loaded data is used by the instruction following the load, but this may require extra real cycles. Most processors cannot actually load data quickly enough for immediate use and the processor will be forced to wait until the data is available. Scheduling load delay slots is desirable for performance reasons even when it is not necessary for correctness. CPU Instruction Set MIPS IV Instruction Set. Rev 3.2-3
14 A CPU Loads and Stores There are instructions to transfer different amounts of data: bytes, halfwords, words, and doublewords. Signed and unsigned integers of different sizes are supported by loads that either sign-extend or zero-extend the data loaded into the register. Table A-3 Normal CPU Load/Store Instructions Mnemonic Description Defined in LB Load Byte MIPS I LBU Load Byte Unsigned I SB Store Byte I LH Load Halfword I LHU Load Halfword Unsigned I SH Store Halfword I LW Load Word I LWU Load Word Unsigned III SW Store Word I LD Load Doubleword III SD Store Doubleword III Unaligned words and doublewords can be loaded or stored in only two instructions by using a pair of special instructions. The load instructions read the left-side or right-side bytes (left or right side of register) from an aligned word and merge them into the correct bytes of the destination register. MIPS I, though it prohibits other use of loaded data in the load delay slot, permits LWL and LWR instructions targeting the same destination register to be executed sequentially. Store instructions select the correct bytes from a source register and update only those bytes in an aligned memory word (or doubleword). Table A-4 Unaligned CPU Load/Store Instructions Mnemonic Description Defined in LWL Load Word Left MIPS I LWR Load Word Right I SWL Store Word Left I SWR Store Word Right I LDL Load Doubleword Left III LDR Load Doubleword Right III SDL Store Doubleword Left III SDR Store Doubleword Right III -4 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
15 A Atomic Update Loads and Stores There are paired instructions, Load Linked and Store Conditional, that can be used to perform atomic read-modify-write of word and doubleword cached memory locations. These instructions are used in carefully coded sequences to provide one of several synchronization primitives, including test-and-set, bit-level locks, semaphores, and sequencers/event counts. The individual instruction descriptions describe how to use them. Table A-5 Atomic Update CPU Load/Store Instructions Mnemonic Description Defined in LL Load Linked Word MIPS II SC Store Conditional Word II LLD Load Linked Doubleword III SCD Store Conditional Doubleword III A Coprocessor Loads and Stores These loads and stores are coprocessor instructions, however it seems more useful to summarize all load and store instructions in one place instead of listing them in the coprocessor instructions functional group. If a particular coprocessor is not enabled, loads and stores to that processor cannot execute and will cause a Coprocessor Unusable exception. Enabling a coprocessor is a privileged operation provided by the System Control Coprocessor. Table A-6 Coprocessor Load/Store Instructions Mnemonic Description Defined in LWCz Load Word to Coprocessor-z MIPS I SWCz Store Word from Coprocessor-z I LDCz Load Doubleword to Coprocessor-z II SDCz Store Doubleword from Coprocessor-z II Table A-7 FPU Load/Store Instructions Using Register + Register Addressing Mnemonic Description Defined in LWXC1 Load Word Indexed to Floating Point MIPS IV SWXC1 Store Word Indexed from Floating Point IV LDXC1 Load Doubleword Indexed to Floating Point IV SDXC1 Store Doubleword Indexed from Floating Point IV CPU Instruction Set MIPS IV Instruction Set. Rev 3.2-5
16 A. 2.2 Computational Instructions Two s complement arithmetic is performed on integers represented in two s complement notation. There are signed versions of add, subtract, multiply, and divide. There are add and subtract operations, called unsigned, that are actually modulo arithmetic without overflow detection. There are unsigned versions of multiply and divide. There is a full complement of shift and logical operations. MIPS I provides 32-bit integers and 32-bit arithmetic. MIPS III adds 64-bit integers and provides separate arithmetic and shift instructions for 64-bit operands. Logical operations are not sensitive to the width of the register. A ALU Some arithmetic and logical instructions operate on one operand from a register and the other from a 16-bit immediate value in the instruction word. The immediate operand is treated as signed for the arithmetic and compare instructions, and treated as logical (zero-extended to register length) for the logical instructions. Table A-8 ALU Instructions With an Immediate Operand Mnemonic Description Defined in ADDI Add Immediate Word MIPS I ADDIU Add Immediate Unsigned Word I SLTI Set on Less Than Immediate I SLTIU Set on Less Than Immediate Unsigned I ANDI And Immediate I ORI Or Immediate I XORI Exclusive Or Immediate I LUI Load Upper Immediate I DADDI Doubleword Add Immediate III DADDIU Doubleword Add Immediate Unsigned III -6 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
17 Table A-9 3-Operand ALU Instructions Mnemonic Description Defined in ADD Add Word MIPS I ADDU Add Unsigned Word I SUB Subtract Word I SUBU Subtract Unsigned Word I DADD Doubleword Add III DADDU Doubleword Add Unsigned III DSUB Doubleword Subtract III DSUBU Doubleword Subtract Unsigned III SLT Set on Less Than I SLTU Set on Less Than Unsigned I AND And I OR Or I XOR Exclusive Or I NOR Nor I A Shifts There are shift instructions that take the shift amount from a 5-bit field in the instruction word and shift instructions that take a shift amount from the low-order bits of a general register. The instructions with a fixed shift amount are limited to a 5-bit shift count, so there are separate instructions for doubleword shifts of -31 bits and bits. Table A-1 Shift Instructions Mnemonic Description Defined in SLL Shift Word Left Logical MIPS I SRL Shift Word Right Logical I SRA Shift Word Right Arithmetic I SLLV Shift Word Left Logical Variable I SRLV Shift Word Right Logical Variable I SRAV Shift Word Right Arithmetic Variable I DSLL Doubleword Shift Left Logical III DSRL Doubleword Shift Right Logical III DSRA Doubleword Shift Right Arithmetic III DSLL32 Doubleword Shift Left Logical + 32 III DSRL32 Doubleword Shift Right Logical + 32 III DSRA32 Doubleword Shift Right Arithmetic + 32 III DSLLV Doubleword Shift Left Logical Variable III DSRLV Doubleword Shift Right Logical Variable III DSRAV Doubleword Shift Right Arithmetic Variable III CPU Instruction Set MIPS IV Instruction Set. Rev 3.2-7
18 A Multiply and Divide The multiply and divide instructions produce twice as many result bits as is typical with other processors and they deliver their results into the HI and LO special registers. Multiply produces a full-width product twice the width of the input operands; the low half is put in LO and the high half is put in HI. Divide produces both a quotient in LO and a remainder in HI. The results are accessed by instructions that transfer data between HI/LO and the general registers. Table A-11 Multiply/Divide Instructions Mnemonic Description Defined in MULT Multiply Word MIPS I MULTU Multiply Unsigned Word I DIV Divide Word I DIVU Divide Unsigned Word I DMULT Doubleword Multiply III DMULTU Doubleword Multiply Unsigned III DDIV Doubleword Divide III DDIVU Doubleword Divide Unsigned III MFHI Move From HI I MTHI Move To HI I MFLO Move From LO I MTLO Move To LO I A. 2.3 Jump and Branch Instructions The architecture defines PC-relative conditional branches, a PC-region unconditional jump, an absolute (register) unconditional jump, and a similar set of procedure calls that record a return link address in a general register. For convenience this discussion refers to them all as branches. All branches have an architectural delay of one instruction. When a branch is taken, the instruction immediately following the branch instruction, in the branch delay slot, is executed before the branch to the target instruction takes place. Conditional branches come in two versions that treat the instruction in the delay slot differently when the branch is not taken and execution falls through. The branch instructions execute the instruction in the delay slot, but the branch likely instructions do not (they are said to nullify it). By convention, if an exception or interrupt prevents the completion of an instruction occupying a branch delay slot, the instruction stream is continued by re-executing the branch instruction. To permit this, branches must be restartable; procedure calls may not use the register in which the return link is stored (usually register 31) to determine the branch target address. -8 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
19 Table A-12 Jump Instructions Jumping Within a 256 Megabyte Region Mnemonic Description Defined in J Jump MIPS I JAL Jump and Link I Table A-13 Jump Instructions to Absolute Address Mnemonic Description Defined in JR Jump Register MIPS I JALR Jump and Link Register I Table A-14 PC-Relative Conditional Branch Instructions Comparing 2 Registers Mnemonic Description Defined in BEQ Branch on Equal MIPS I BNE Branch on Not Equal I BLEZ Branch on Less Than or Equal to Zero I BGTZ Branch on Greater Than Zero I BEQL Branch on Equal Likely II BNEL Branch on Not Equal Likely II BLEZL Branch on Less Than or Equal to Zero Likely II BGTZL Branch on Greater Than Zero Likely II Table A-15 PC-Relative Conditional Branch Instructions Comparing Against Zero Mnemonic Description Defined in BLTZ Branch on Less Than Zero MIPS I BGEZ Branch on Greater Than or Equal to Zero I BLTZAL Branch on Less Than Zero and Link I BGEZAL Branch on Greater Than or Equal to Zero and Link I BLTZL Branch on Less Than Zero Likely II BGEZL Branch on Greater Than or Equal to Zero Likely II BLTZALL Branch on Less Than Zero and Link Likely II BGEZALL Branch on Greater Than or Equal to Zero and Link Likely II A. 2.4 Miscellaneous Instructions A Exception Instructions Exception instructions have as their sole purpose causing an exception that will transfer control to a software exception handler in the kernel. System call and breakpoint instructions cause exceptions unconditionally. The trap instructions cause exceptions conditionally based upon the result of a comparison. Table A-16 System Call and Breakpoint Instructions Mnemonic Description Defined in SYSCALL System Call MIPS I BREAK Breakpoint I CPU Instruction Set MIPS IV Instruction Set. Rev 3.2-9
20 Table A-17 Trap-on-Condition Instructions Comparing Two Registers Mnemonic Description Defined in TGE Trap if Greater Than or Equal MIPS II TGEU Trap if Greater Than or Equal Unsigned II TLT Trap if Less Than II TLTU Trap if Less Than Unsigned II TEQ Trap if Equal II TNE Trap if Not Equal II Table A-18 Trap-on-Condition Instructions Comparing an Immediate Mnemonic Description Defined in TGEI Trap if Greater Than or Equal Immediate MIPS II TGEIU Trap if Greater Than or Equal Unsigned Immediate II TLTI Trap if Less Than Immediate II TLTIU Trap if Less Than Unsigned Immediate II TEQI Trap if Equal Immediate II TNEI Trap if Not Equal Immediate II A Serialization Instructions The order in which memory accesses from load and store instruction appear outside the processor executing them, in a multiprocessor system for example, is not specified by the architecture. The SYNC instruction creates a point in the executing instruction stream at which the relative order of some loads and stores is known. Loads and stores executed before the SYNC are completed before loads and stores after the SYNC can start. Table A-19 Serialization Instructions Mnemonic Description Defined in SYNC Synchronize Shared Memory MIPS II A Conditional Move Instructions Instructions were added in MIPS IV to conditionally move one CPU general register to another based on the value in a third general register. Table A-2 CPU Conditional Move Instructions Mnemonic Description Defined in MOVN Move Conditional on Not Zero MIPS IV MOVZ Move Conditional on Zero IV A Prefetch There are two prefetch advisory instructions; one with register+offset addressing and the other with register+register addressing. These instructions advise that memory is likely to be used in a particular way in the near future and should be -1 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
21 prefetched into the cache. The PREFX instruction using register+register addressing mode is coded in the FPU opcode space along with the other operations using register+register addressing. Table A-21 Prefetch Using Register + Offset Address Mode Mnemonic Description Defined in PREF Prefetch Indexed MIPS IV Table A-22 Prefetch Using Register + Register Address Mode Mnemonic Description Defined in PREFX Prefetch Indexed MIPS IV A. 2.5 Coprocessor Instructions Coprocessors are alternate execution units, with register files separate from the CPU. The MIPS architecture provides an abstraction for up to 4 coprocessor units, numbered to 3. Each architecture level defines some of these coprocessors as shown in Table A-23. Coprocessor is always used for system control and coprocessor 1 is used for the floating-point unit. Other coprocessors are architecturally valid, but do not have a reserved use. Some coprocessors are not defined and their opcodes are either reserved or used for other purposes. Table A-23 Coprocessor Definition and Use in the MIPS Architecture MIPS architecture level coprocessor I II III IV Sys Control Sys Control Sys Control Sys Control 1 FPU FPU FPU FPU 2 unused unused unused unused 3 unused unused not defined FPU (COP 1X) The coprocessors may have two register sets, coprocessor general registers and coprocessor control registers, each set containing up to thirty two registers. Coprocessor computational instructions may alter registers in either set. System control for all MIPS processors is implemented as coprocessor (CP), the System Control Coprocessor. It provides the processor control, memory management, and exception handling functions. The CP instructions are specific to each CPU and are documented with the CPU-specific information. If a system includes a floating-point unit, it is implemented as coprocessor 1 (CP1). In MIPS IV, the FPU also uses the computation opcode space for coprocessor unit 3, renamed COP1X. The FPU instructions are documented in Appendix B. CPU Instruction Set MIPS IV Instruction Set. Rev
22 The coprocessor instructions are divided into two main groups: Load and store instructions that are reserved in the main opcode space. Coprocessor-specific operations that are defined entirely by the coprocessor. A Coprocessor Load and Store Load and store instructions are not defined for CP; the move to/from coprocessor instructions are the only way to write and read the CP registers. The loads and stores for coprocessors are summarized in Load and Store Instructions on page A-2. A Coprocessor Operations There are up to four coprocessors and the instructions are shown generically for coprocessor-z. Within the operation main opcode, the coprocessor has further coprocessor-specific instructions encoded. Table A-24 Coprocessor Operation Instructions Mnemonic Description Defined in COPz Coprocessor-z Operation MIPS I A. 3 Memory Access Types MIPS systems provide a few memory access types that are characteristic ways to use physical memory and caches to perform a memory access. The memory access type is specified as a cache coherence algorithm (CCA) in the TLB entry for a mapped virtual page. The access type used for a location is associated with the virtual address, not the physical address or the instruction making the reference. Implementations without multiprocessor (MP) support provide uncached and cached accesses. Implementations with MP support provide uncached, cached noncoherent and cached coherent accesses. The memory access types use the memory hierarchy as follows: Uncached Physical memory is used to resolve the access. Each reference causes a read or write to physical memory. Caches are neither examined nor modified. Cached Noncoherent Physical memory and the caches of the processor performing the access are used to resolve the access. Other caches are neither examined nor modified. -12 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
23 Cached Coherent Physical memory and all caches in the system containing a coherent copy of the physical location are used to resolve the access. A copy of a location is coherent (noncoherent) if the copy was placed in the cache by a cached coherent (cached noncoherent) access. Caches containing a coherent copy of the location are examined and/or modified to keep the contents of the location coherent. It is unpredictable whether caches holding a noncoherent copy of the location are examined and/or modified during a cached coherent access. Cached For early 32-bit processors without MP support, cached is equivalent to cached noncoherent. If an instruction description mentions the cached noncoherent access type, the comment applies equally to the cached access type in a processor that has the cached access type. For processors with MP support, cached is a collective term, e.g. cached memory or cached access, that includes both cached noncoherent and cached coherent. Such a collective use does not imply that cached is an access type, it means that the statement applies equally to cached noncoherent and cached coherent access types. A. 3.1 Mixing References with Different Access Types It is possible to have more than one virtual location simultaneously mapped to the same physical location. The memory access type used for the virtual mappings may be different, but it is not generally possible to use mappings with different access types at the same time. A processor executing load and store instructions must observe the effect of the load and store instructions to a physical location in the order that they occur in the instruction stream (i.e. program order) for all accesses to virtual locations with the same memory access type. If a processor executes a load or store using one access type to a physical location, the behavior of a subsequent load or store to the same location using a different memory access type is undefined unless a privileged instruction sequence is executed between the two accesses. Each implementation has a privileged implementation-specific mechanism that must be used to change the access type being used to access a location. The memory access type of a location affects the behavior of I-fetch, load, store, and prefetch operations to the location. In addition, memory access types affect some instruction descriptions. Load linked (LL, LLD) and store conditional (SC, SCD) have defined operation only for locations with cached memory access type. SYNC affects only load and stores made to locations with uncached or cached coherent memory access types. CPU Instruction Set MIPS IV Instruction Set. Rev
24 A. 3.2 Cache Coherence Algorithms and Access Types The memory access types are specified by implementation-specific cache coherence algorithms (CCAs) in TLB entries. Slightly different cache coherence algorithms such as cached coherent, update on write and cached coherent, exclusive on write can map to the same memory access type, in this case they both map to cached coherent. In order to map to the same access type the fundamental mechanism of both CCAs must be the same. When it affects the operation of the instruction, the instructions are described in terms of the memory access types. The load and store operations in a processor proceeds according to the specific CCA of the reference, however, and the pseudocode for load and store common functions in the section Load and Store Memory Functions on page A-21 use the CCA value rather than the corresponding memory access type. A. 3.3 Implementation-Specific Access Types An implementation may provide memory access types other than uncached, cached noncoherent, or cached coherent. Implementation-specific documentation will define the properties of the new access types and their effect on all memoryrelated operations. -14 MIPS IV Instruction Set. Rev 3.2 CPU Instruction Set
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text:
Sometimes It Just Works Out Right!
I took some samples around to businesses today and came back to the shop where I spent the whole day just cleaning. I organized the storage area. I straightened up the supply of disposable plates, forks, and and napkins that had gotten all jumbled. I organized and stacked all of my rubbermaid containers of catering equipment. I moved kitchen equipment out from the wall and mopped behind it. I moved tables. I got down on my hands and knees and scraped stuff off of the floor. I took that big pile of tablecloths (that had been laying in the corner for a few days) out to the van so I could wash them. The sinks were shiny, the floors were sparkling, the counters were empty.
And then .......
My health inspector came by this afternoon.
Yeah, sometimes things work out JUST fine!
How sweet it is!
Whoa~~what are the chances??
I haven't lived long enough yet (for that to happen to me)
Way way cool.
Geez, quick buy a lottery number!!!
that is so perfect!!
Wow, perfect timing! Bet the inspector was super impressed. Is it normal for them to do surprise visits?
Wow........can you say LUCKY dog??
Wow, perfect timing! Bet the inspector was super impressed. Is it normal for them to do surprise visits?
Always--except never on weekends.
<insert halo wearing smilie face>
Wow, perfect timing! Bet the inspector was super impressed. Is it normal for them to do surprise visits?
Always--except never on weekends.
<insert halo wearing smilie face>
Yup ... always surprise visits. My guy is SO cool though. I just luv him and I actually like it when he visits. He said to me once, "You make my job SO easy!" (yeah...big cheesy grin just JUMPED onto my face at that one!).
Yea! Don't you love it when good things happen to nice people !!
Deb, you are always so helpful to everyone here online...this is that good karma coming back to you !
Here, the health inspectors call and schedule an appointment to come see you. Isn't that the dumbest thing you ever heard of? The scary part is that they still find violations.
Definitely good karma!
couldn't have said it better myself Elserj! good karma is rewarded! glad you had a nice day Indydebi!! ((hugs)))
WOW! Thats so crazy. Happy for you.
Hey indydeb you know what they say..............."good things happen to good people."
psssssst.............do you think susiecreamcheese sent him?
that happened to me once about 5 years ago...he came after i got done cleaning and scrubbing the baseboards....it was great!
the last time however not so much....after he left i had to have 500.00 bucks worth of repairs done...THEN
after i did em...cleaned like a mad hatter, i called him to see if he was gonna come back...no he didn't think he would have time...i guess they figger if you really WANT them to come...your place must be A OK.
Wow! I bet you were relieved!
Quote by @%username% on %date%

subset: commoncrawl


text:
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text:
I had a co-worker who would constantly use the the phrase, "bad juju" to describe a bad situation. I'd be all, "Dude, why are you late?" He'd be all, "Dude, I missed my bus. Bad juju!"
I would call him an anti-semitic, stuttering bastard. Then, we'd laugh and laugh and laugh... because, we were douchebags!
Posted on April 4, 2011
Category : Bad Juju, Douchebags, Ramblings, Stupid Mofos


text:
- For other uses of King's Highway, see King's Highway
Work on the King's Highway was begun in 1629OT, the road travelling from Djiretta via the capital to Kelther to unify the kingdom.[1]
But due to frequent wars and the sheer scale of the project work took many years, although merchants made use of those parts that were finished along the way. Thus even the unfinished highway brought much prosperity.
The highway was built from either end toward a middle point. Because Shakista already had a decent road leading merchant routes to the capital the need for the highway there was least and left to the last. In 1702OT, 12th Nature's Curling (9th Hiding), work finally began on the King's Highway,[2] in Balaran, then a small town near the capital which was renamed Ximoran after the Great War against Chaos. This marked the last building phase of the highway and at the end of 1703OT it was finished.
Trade multiplied further due to this great road with merchants and other travellers making their way from the Shantak River in the north to Zagoula in the south. In some places little more than a dirt track these days, this still great road can be followed south as far as the port of Kelther at the mouth of the River Swordflow. To the north it makes a wide sweep east, away from Scorpion Swamp,[3] before heading north to the ancient city of Djiretta, on the Coast of Sharks.
See AlsoEdit
- ↑ Titan - The Fighting Fantasy World - p.??/??
- ↑ The Fighting Fantasy 10th Anniversary Yearbook - p.183
- ↑ Scorpion Swamp - ???


text:
New Orleans Magazine's Hobnobber Event at Pete's
Renaissance Publishing LLC
Thursday, July 31, 2014 from 5:00 PM to 7:00 PM (CDT)
Who's Going
San Francisco, California
London, United Kingdom
Florence, Italy
Event Details
Sip and Socialize at the New Orleans Magazine's Hobnobber event at Pete's.
Thursday, July 31, 2014
5-7 pm
at the InterContinental New Orleans
444 St. Charles Avenue, New Orleans
Drink Specials * Door Prizes
For more information, contact Sara Kelemencky at 504.830.7231
When & Where
InterContinental New Orleans
444 St. Charles Avenue
New Orleans,
Thursday, July 31, 2014 from 5:00 PM to 7:00 PM (CDT)
Add to my calendar
Renaissance Publishing LLC
Renaissance Publishing LLC. is locally owned by Todd Matherne, Errol Laborde and Alan Campell. Renaissance Publishing is a leader in the four-color glossy publishing industry. We offer many different product niches to specifically target readers in an inviting lifestyle reading experience. Renaissance Publishing publishes New Orleans Magazine, New Orleans Homes & Lifestyles, Biz New Orleans, St. Charles Avenue, Louisiana Life, OnStage, New Orleans Bride, and Acadiana Profile. In addition to print magazines and custom publishing, Renaissance Publishing offers digital media, websites, email newsletters, a mobile app and digital editions.
Cheryl Lemoine is the Director of Marketing Events and can be reached at
email@example.com or (504) 830-7232.


text:
It is difficult to convey a personality without any kind of exchange in person, I think. Here is my try: I am an altruistic, logical, somewhat introverted, but still pretty outgoing, average dude. I have excellent communication skills, know how to look nice when it is called for, be polite when it is appropriate, and keep a cool head in stressful situations. Some other stuff that's neat, I don't know, see more below.
Animals are awesome; I've spent far more time with cats than dogs, but I am good with pretty much any animal. I have experience with rodents, reptiles, and birds, as well. Insects and arachnids...not so much, but I have friends who keep them and I plan on holding a tarantula once I get over myself.
Books: Gaiman, King, Vonnegut, Orwell, Eddings, G.R.R.Martin, etc. I have a big list of stuff I still need to read. The last few books I read were Do Androids Dream of Electric Sheep? by Phillip K. Dick, The Plague by Albert Camus, Brave New World by Aldous Huxley, Catch 22 by Joseph Heller, Mary Shelley's Frankenstein, The Lord of the Rings, The Picture of Dorian Gray, The Wonderful Wizard of Oz. I just read the Sprawl trilogy by William Gibson, the bible of cyberpunk, and I thought it was excellent.
Music: Pink Floyd, Brand New, Protest the Hero, The Mars Volta, Silversun Pickups, Decemberists, Mumford & Sons, City & Colour, Thrice, and many more.
I have never been much of a TV person(except for anime(don't hate)), but now that I have this nifty netflix setup I've been enjoying stuff like The Walking Dead, Archer, Bob's Burgers, Breaking Bad, Sherlock, House of Cards, and once again there is always more to discover. As for anime I like: Trigun, Bebop, Spirited Away(I haven't seen all of the Ghibli films yet but the ones I have seen are amazing), Death Note, Fullmetal Alchemist, Attack on Titan, Outlaw Star, Psycho-Pass and so on.
I have a soft spot for Italian food, and otherwise I'm not too picky.
In the spirit of transparency, I will admit that I play a lot of video games. Overwatch, League of Legends, Diablo III, Hearthstone, Skyrim, FTL: Faster Than Light to name the most common. I'm working my way through Dishonored and Fallout 4.
Sounds like everyone else.


text:
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DOY Previews the Sabres
I know things around here haven't been very active in the last month. However, I couldn't pass up an opportunity to get some good old fashioned trolling in from our friends at Days of Y'orr, who happen to be master haters of the Buffalo Sabres. Enjoy and follow Greg at @PezDOY!
I feel honored being able to write for Blackhawks Down Low, if only for today. So I've been given quite a large task, although I think I can pull it off. Andrew has asked me to inform the Blackhawks fan base the reasons to hate the Buffalo Sabres. Well I hope you have a good pint of ale, a comfy place to rest your ass and some time because this may take a little while. The reason being is that it's so easy to hate the Buffalo Sabres. My brain is running at 6000 RPM's right now just trying to figure out where to start, but I guess if you're going to start anywhere, you start with the "face of the franchise".
Reason #1 To Hate The Buffalo Sabres: Ryan Miller
I've never seen such a fall from grace happen in the short span of two years. In 2010, Ryan Miller led the Americans to the gold medal game in the 2010 Olympics. Everyone in the United States loved Ryan Miller. He was like apple pie, fire works, liberty, freedom, small puppies and Hulk Hogan all rolled into one. The last America was this proud of someone, George Washington had his foot atop a boat heading down a river. He was the bee's knees and although the Americans lost in overtime, it was okay. It wasn't Ryan Miller's fault that Sidney Crosby is a pretty good hockey player.
Lets jump to the 2010-2011 season. Ryan Miller is still considered to be a great goaltender, although the stats aren't beginning to support his claim. Out of 87 goalies who could register a GAA, Miller was 37th overall with a GAA of 2.59. His save percentage was a little better, registering at 32nd overall at .916. Where did the Sabres end up at the end of the year in 2010-2011? They lost in 7 games to Philadelphia and hit up the buffalo wings place by Sunday. The series was pretty good though, so many thought that Miller and the Sabres were about to turn it around and become a formidable opponent in the Eastern Conference, let a lone the Northeast Division.
Then "the hit" happened.
I would like to apologize ahead of time that you have to listen to Rick Jeanneret, who makes Jack Edwards sound like a master at his craft.
Oh God, the hit. Okay, so Milan Lucic blatantly runs over Ryan Miller. I'm not going to deny it and I didn't deny it when it first happened. He plowed into him. He ran him over. Miller tries to take a huge swipe at Lucic's legs and misses, then he lays on the ice like he's been shot. Then he plays another period and a half. Then he leaves with a "concussion". No quiet room, no eye checks, no little flashlight in the face, nothing. After the incident, the concussed superstar goalie had this to say:
Hey, that's fine by me. I'd be pissed too if some dude ran me down like I was the frog from Frogger. Here's the issue with the whole thing. Miller supposedly had a concussion without proper protocol being done. Like I mentioned, none of that quiet room bullshit. Then, after Milan Lucic hangs out with Brendan Shanahan for a little bit and doesn't get suspended, Miller changes his mind on his concussion.
"I feel good symptom-wise," Miller said after practice, according to The Buffalo News. "It was more neck and something where I aggravated a disc in my neck pretty good and we had an MRI and CT scan showing that which kind of backed that up and was the source of a lot of the tension and a lot of the discomfort. It definitely was limiting my range of motion. "I don't know for certain what it was," Miller added. "It definitely felt ... I took a good impact and definitely felt that way [that it was a concussion] but I also had some symptoms in my neck and that was proven through some tests."
Yup, that just happened. Want even more reason to hate Ryan Miller?
After allowing 5 goals in two periods against the Detroit Red Wings, Miller has the audacity to start chirping about his own team.
"That's not my decision. If it's going to happen, it's going to happen in the locker room. If you guys really think there's going to be any kind of trade made anywhere that's going to affect this team any more than we can affect it in this locker room, you guys are just … I don't know what to think, because there's no such trade. "There's not ever going to be a trade in the history of the NHL that's going to affect anything like that. There's no chance anybody comes into this team and just shakes it up or we can even move multiple players and get any kind of return … If you want to just destroy a team and just go out and be reckless and do something, yeah. "But then there's going to be new guys in here, but other than that, this locker room's going to be pretty much the same, if not completely the same, and we've got to find it from in here. [Points to chest] We can't sit and wait for somebody else to f--king do it."
In his own words: "What a piece of shit".
Reason #2 To Hate The Buffalo Sabres: Patrick Kaleta
Kaleta is Buffalo's version of the "goon" player, but he does a shitty job at it. To Kaleta's credit, he's a shit disturber. He'll pick his spots to start things, but he never backs them up. He chirps when the refs are in between people. He takes cheap and dirty shots. He headbutts people. When Kaleta does try to be a tough guy, he is shown why he's a piece of shit.
Reason #3 To Hate The Buffalo Sabres: Lindy Ruff
I fucking hate Lindy Ruff. Lets start with the aforementioned Ryan Miller hit. Here's what he had to say on it.
"I turn on TSN this morning and the goalies getting bumped almost falls in that open season category," Ruff said, referring to the phrase he used when Ryan Miller got drilled by Milan Lucic. "… We're in dangerous territory with some of that stuff."
What Ruff doesn't say is that he declared it "open season" on goalies in 2007. His comments after the game?
"I'm not going to comment what I had on my mind." After pausing, Ruff added: "Go out and run 'em."
That's just the tip of the iceberg with Ruff. When the Sabres played the Bruins in the 2009-2010 playoffs, Ruff complained about the referees after every game. In fact, it seems that all he does is cry and whine about something. I mean, he does it so much that we at Days of Y'Orr constantly make photoshops of him crying. Constantly. It's maddening to think that a coach who is the NHL's longest tenured coach can do so without actually winning anything. Then again, it's also Buffalo so anything is possible.
There's three good reasons why you should hate the Buffalo Sabres. In all honesty, I could go into how pathetic and entitled the fan base is. I could go into how shitty the actual city is. What's the point? These things are already known. Shawn Thornton was asked if he liked playing in the city of Buffalo and what he thought of it. He waited a moment and said "Well it's not the prettiest city out there" and he's right. It's an ugly mess. It's such a mess that their own football team that's been there for decades would rather move to Canada.
I hope I did this some justice and I've given you enough reason to hate the Sabres, or at least dislike them a lot. If not, I'm sure you can search LiveJournal for Ryan Miller's diary and see the true piece of shit he is.
This is really awesome!!Thanks for the video...
Latest blog post: Staying Healthy Whilst Using A Hot Tub
Most excellent, Greg!! Also... http://www.buffalonews.com/city/article507007.ece


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House Sitter in New Monmouth
Hey there! I'm a 32 year old female who enjoys looking after people's homes/animals while they're out of town. After doing this many times to help out friends and family I figured I would see what other opportunities were out there. I work as a manicurist/ esthetician at a salon in red bank, even though I'm working half a day on Tuesdays and full days the rest of the week my job is pretty flexible if I needed to block myself out to go to the location to care for an animal I would be able to. I'm moved back in with my parents for a while since my boyfriend and I are saving to get our own place together eventually. In the meantime it's always a plus for me to stay at other peoples homes and take care of responsibilities while the homeowners are away. I love animals, I keep things neat and make sure whatever is requested to be done will get done. I miss having my own space, so in the meantime I figured this would be the best thing for me to enjoy alone time while making some extra money. I look forward to hearing from anybody who is willing to give me a chance. I have many references, clean background check, and am trustworthy and responsible.
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PNS Hector Van Dragen was a superdreadnought of the State Security Naval Forces.
History Edit
Commanded by Captain (SSNF) Jillian Gallanti, Hector Van Dragen was one of the ships assigned to monitor the People's Navy vessels in the La Martine Sector picket.
Seven of its officers and twenty-three crewmembers were arrested in the first week of Special Investigator for the Director Victor Cachat's investigation. Six officers were shot almost immeditely by Cachat during his investigation. After Captain Gallanti was killed, when she didn't obey Cachat's orders, the ship was succesfully subordinated to the navy. (HHA4.5: F)
Technical specifications Edit
- Tonnage: 7,000,000 tons
Known crewmembers Edit
SSNF Officers Edit
- Captain Jillian Gallanti – Commanding Officer (†)
- Commander Wright – acting Commanding Officer, brevet promotion within the PN / RHN on Captain grade
- Commander Kit Carson – Executive Officer
- Commander Edouard Ballon – Tactical Officer (†)
- Commander Tarack – acting Tactical Officer
- Lieutenant Commander Saunders – Chief Engineering Officer
SSNF Enlisted Edit
- Rita Enquien – Communications Technician First Class
- Bob Gottlieb – Impeller Technician
- Henri Alouette – Gravitic Array Technician
Marine complement Edit
The original SSGF complement was mixed with People's Marines by Special Investigator Cachat's order.
- Major Diana Citizen, SSGF
- Sergeant Jaime Rolla, SSGF
- Major Khedi LaFitte, PM – Commanding Officer, Marine squad from PNS Veracity
- Sergeant Ned Pierce, PM – member of the Marine squad from PNS Veracity
- two other unnamed PM Sergeants from PNS Veracity


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Nielsens: 'America's Got Talent' is tops
•Got ratings. The first elimination-round episode of NBC's America's Got Talent (15.8 million viewers Tuesday) topped the week and grabbed the series' third-biggest audience.
•Kidnap tale. Diane Sawyer's Sunday Primetime interview with kidnap victim Jaycee Dugard drew a big 15.1 million viewers, a summer best for a newsmagazine since 2004.
•Watching. The 13th season premiere of CBS' Big Brother claimed 7.9 million viewers, up half a million from last year.
•Not curbed. The eighth season opener of HBO's Curb Your Enthusiasm took in 1.7 million viewers, its biggest audience since 2004, helped by lead-in True Blood (5 million).
RESULTS: Nielsen charts
•Cable corner: MTV's Teen Mom returned with 3.7 million viewers Tuesday, its biggest opener yet; Nickelodeon's Fairly Odd Movie was the week's top cable draw with 5.8 million Saturday; TNT's Men of a Certain Age wrapped its second season with 1.8 million Wednesday; and Starz's Torchwood premiered with 819,000 Friday.
Posted | Updated


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Lyrics for Roller Coaster by Blink-182 from the hit album Take Off Your Pants and Jacket released in June 2001. Enjoy (:
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Music video by blink-182 performing Adam's Song. (C) 1999 Geffen Records.
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Music video by blink-182 performing Stay Together For The Kids. (C) 2001 Geffen Records.
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Get an overview of this hotel4-star hotel with 2 restaurants and outdoor pool
Popular property highlights
Situated near the beach, this hotel is 1.1 mi (1.7 km) from National Museum of Ras al Khaimah and within 3 mi (5 km) of Khuzam Family Park and Tower Links Golf Club. Iceland Water Park is 9.9 mi (15.9 km) away.
Hotel Features
This hotel features 2 restaurants, an outdoor pool, and a health club. Free WiFi in public areas, free self parking, and a free beach shuttle are also provided. Additionally, a poolside bar, a coffee shop/café, and a 24-hour business center are onsite.
Room Amenities
All 186 rooms boast deep soaking tubs and offer free WiFi and TVs. Minibars, coffee makers, and free bottled water are among the other amenities available to guests.Information missing or incorrect? Tell us!Opens in a new window
Mangrove by Bin Majid
Hotel Amenities
Hotel Amenities
Mangrove by Bin Majid features an outdoor pool and a health club. Dining is available at one of the hotel's 2 restaurants and guests can grab coffee at the coffee shop/café. A poolside bar is on site where guests can unwind with a drink. Wireless Internet access is complimentary.
Business-related amenities at this 4-star property consist of a 24-hour business center and meeting rooms. This business-friendly hotel also offers tour/ticket assistance, multilingual staff, and concierge services. For a surcharge, a roundtrip airport shuttle (available 24 hours) is offered to guests. Complimentary self parking is available on site.
- 24-hour front desk
- Airport transportation (surcharge)
- Total number of rooms - 186
- Breakfast available (surcharge)
- Coffee shop or café
- Free newspapers in lobby
- Concierge services
- Dry cleaning/laundry service
- Express check-in
- Express check-out
- Free beach shuttle
- Health club
- Tours/ticket assistance
- Free WiFi
- Laundry facilities
- Meeting rooms 2
- Multilingual staff
- Valet parking (surcharge)
- Poolside bar
- Luggage storage
- Free self parking
- Number of restaurants - 2
- 24-hour business center
- Outdoor pool
Family Friendly Amenities
- Family Hotel
- Outdoor pool
- Free Wi-Fi
- Laundry facilities
Available in all rooms: Free WiFi
Available in some public areas: Free WiFi
Free self parking, Valet parking (surcharge)
Room Amenities
- Air conditioning
- Free bottled water
- Minibar
- Coffee/tea maker
- Private bathroom
- Free toiletries
- Deep soaking bathtub
- Shower/tub combination
- In-room safe
- Television
- Satellite TV service
- Free WiFi
Where to Eat
Buffet breakfasts are available for a surcharge and are served each morning.
Mangrove by Bin Majid has 2 restaurants on site.
Nearby Things to Do
Recreational amenities at the hotel include an outdoor pool and a health club.
If you have requests for specific accessibility needs, please note them at check-out when you book your room.
- Accessible bathroom
- In-room accessibility
Hotel Policies
Check-in time starts at 2 PM
Special check-in instructions:
Check-out time is 12:30 PM
Payment types
Children and extra beds
- Children are welcome.
- Kids stay free! One child 4 years old or younger stays free when using existing bedding.
- Rollaway/extra beds are not available.
- Cribs (infant beds) are not available.
- No pets or service animals allowed
You need to know
Extra-person charges may apply and vary depending on property policy.
Government-issued photo identification and a credit card or cash deposit are required at check-in for incidental charges.
Special requests are subject to availability upon check-in and may incur additional charges. Special requests cannot be guaranteed.
- The name on the credit card used at check-in to pay for incidentals must be the primary name on the guestroom reservation.
No rollaway/extra beds available
No cribs (infant beds) available
No pets or service animals allowed
The credit card used to book the reservation must be presented at the time of check-in. For more details, please contact the office using the information on the reservation confirmation received after booking.
Local guests are required to provide a valid Emirates identification card; tourists must provide a passport at check-in. For more details, please contact the office using the information on the reservation confirmation received after booking.
- New Year's Eve (31 December) Gala Dinner per adult: AED 350.00
- New Year's Eve (31 December) Gala Dinner per child: AED 175.00 (from 4 to 12 years old)
- Tourism fee: AED 15 per accommodation, per night
Optional extras
- Fee for buffet breakfast: AED 75 per person (approximately)
- Airport shuttle fee: AED 250 per vehicle (one way)
- Valet parking fee: AED 10 per stay
Hotel Name
- Hotel Mangrove
- Mangrove Bin Majid Hotel Ras Al Khaimah
- Mangrove Hotel Ras Al Khaimah
- Mangrove Ras Al Khaimah
- Mangrove Hotel Bin Majid Hotels Resorts Ras Al Khaimah
- Mangrove Hotel Bin Majid Hotels Resorts
- Mangrove Bin Majid Hotels Resorts Ras Al Khaimah
- Mangrove Bin Majid Hotels Resorts
- Mangrove Bin Majid Hotel
- Mangrove Bin Majid Ras Al Khaimah
- Mangrove Bin Majid
- Mangrove Hotel by Bin Majid Hotels Resorts
We should mention
One child 4 years old or younger stays free when occupying the parent or guardian's room, using existing bedding. Only registered guests are allowed in the guestrooms. No pets and no service animals are allowed at this property.


text:
Chris Brown gets candid on...Read More
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After more than a year of delays, Chris Brown''s sixth studio album X was released on Tuesday. So what has Brown been up to in the two years since his last album hit shelves? Well, in between court dates and co-writing...Read More
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As Arnold Schwarzenegger has now successfully made the transition from Hollywood to politics back to Hollywood, he told ET at the premiere of his new action film The Expendables 2 that there was no better film with which to segue back...Read More


text: Unpretty Rapstar runner-up Jessi has recently been promoting her latest solo release, "SSENUNNI"! She has had some energetic stages on a variety of weekly music programs including Inkigayo. For a recent Inkigayo performance, Jessi could be seen wearing an Off-White Camouflage Print Jacket ($1200). This item was worn over a red crop top and American Apparel Acid Wash Easy Jean Shorts ($54). The look is similar to one seen in the fierce unni's MV, which featured a camo jacket worn over a red dress.


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Built in 2008, this hotel comprises a total of 74 guest rooms and suites. Fully air-conditioned, this establishment welcomes its guests into a lobby with a 24-hour reception and check-out service. Facilities on offer at this hotel include lift access, an on-site caf�, bar and restaurant and a laundry service is available for a fee. Guests staying at this establishment can also enjoy complimentary parking in the car park or garage.
This city hotel is situated at the heart of the famous Lido resort, close to the centre of town (about a 30-minute walk away) and about 100 m from the nearest bus stop. Guests will find a number of restaurants, bars, coffee shops and shopping centres in the vicinity. Funchal Airport is some 3 km from the accommodation.
The bedrooms are modern and well-equipped and come with standard facilities like a hairdryer, a direct dial telephone, cable TV, tea and coffee making facilities, air conditioning and a safety deposit box (available for hire). The en suite bathrooms come with a bathtub/shower and balconies/terraces also feature.
The hotel has a heated outdoor swimming pool with sun loungers and parasols laid out on the sun terrace and poolside. Guests looking to keep in shape can visit the small gym for a work-out.
This hotel offers bed and breakfast and half-board stays. A buffet breakfast is served daily and evening meals can be selected from the � la carte menu or enjoyed buffet style.
The hotel accepts the following credit cards: American Express, MasterCard and VISA.
From the airport: Take the motorway heading to Funchal, then the exit to the hospital and follow the Estrada Monumental until reaching the Lido area. Public transport goes as far as Funchal, where several buses can be found which head to the lido area.
Room Facilities:
Direct dial telephone
Satellite cable TV
Tea Coffee
Central airconditioned
Individual airconditioned
Wheelchair accessible