text:
|Publication number
|Publication type
|Application number
|Publication date
|Feb 1, 1994
|Filing date
|Oct 4, 1991
|Priority date
|Oct 4, 1991
|Fee status
|Also published as
|Publication number
|Thomas F. Joyce, James W. Keeley
|Original Assignee
|Bull Hn Information Systems Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (11), Referenced by (36), Classifications (8), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
1. The patent application of James W. Keeley and Thomas F. Joyce entitled, "High Performance Tightly Coupled Multiple Synchronous State Machine Based Processing Unit," filed on Oct. 4, 1991 bearing Ser. No. 07/771,289, which is assigned to the same assignee as this patent application.
2. The patent application of James W. Keeley entitled, "Bus Interface State Machines," filed on Oct. 4, 1991, bearing Ser. No. 07/771,712, which is assigned to the same assignee as this patent application.
3. The patent application of Thomas F. Joyce and James W. Keeley and Richard A. Lemay entitled, "Programmable Bus State Machine," filed on Oct. 4, 1991, bearing Ser. No. 07/771,297, which is assigned to the same assignee as this patent application.
1. Field of Use
The present invention relates generally to multiprocessor systems and, more particularly, to deadlock detection apparatus for avoiding deadly embrace situations between the processing units within a multiprocessing system.
2. Prior Art
In computer systems, it is important that resources be allocated in a way that deadlock does not occur. A deadlock occurs when processes holding some resources request access to resources held by other processes in the same set. Unless the deadlock is resolved, all the processes involved are blocked indefinitely. Therefore, a deadlock requires the attention of a process outside those involved in the deadlock for its detection and resolution.
Generally, a deadlock can be resolved by aborting one or more processes involved in the deadlock and granting the released resources to other processes involved in the deadlock. A process is aborted by withdrawing all its resource requests, restoring its state to an appropriate previous state, relinquishing all the resources it acquired after that state, and restoring all the relinquished resources to their original states.
U.S. Pat. No. 4,318,182 discloses a system in which a deadlock detection mechanism detects situations where two or more processes are waiting for related events which cannot happen, preventing a requesting process from waiting for the availability of a resource or resources which are already held by a second process which is waiting directly or indirectly upon the first process. This requires that the system have access to all of the resources within the system to ensure that a requested resource is not currently assigned to a second process which is already waiting directly or indirectly for a second resource currently assigned to a first process.
In tightly coupled multiprocessor systems, the different processors are required to share data within a common or global main memory system. To preclude race conditions and the occurrence of the deadlock or deadly embrace situation, it is well known to have each processor use test and set lock instructions. That is, each processor obtains or tests the lock for a shared data structure or section of main memory. If it is unlocked, the processor gets the lock and accesses the segment. However, if the segment is locked, the processor spins in a loop, periodically testing until the lock becomes available.
While the above type of mutually exclusive protocol has been effective in eliminating the above problems, this approach may not be effective in certain types of situations which may not be easily detected. For example, this type of situation may go undetected in a multiprocessor system which includes processors with local memories where the local memories of such processors are required to be shared by other processors of the system.
Accordingly, it is a primary object of the present invention to provide a multiprocessor lock mechanism which reliably protects against deadlocks.
It is a more specific object of the present invention to provide a multiprocessor lock protocol which permits reliable accesses to all processor shared memories within a tightly coupled multiprocessor system.
The above and other objects of the present invention are achieved in a multiprocessor system which includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each on-board memory processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol.
Each processor has a system interface which includes circuits for implementing the memory lock protocol for accessing system memory. According to the present invention, each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.
In the first case, when a processor issues a memory lock command on the system bus to a local memory of the on-board memory processor, the lock mechanism included as part of the system bus interface circuits effectively locks the on-board or local memory and prevents the microprocessor from accessing the local bus through the use of its local bus standard hold acknowledge mechanism. This allows the local memory to read out and transfer requested data to the system bus. The local memory maintains control of the microprocessor local bus until the entire memory lock protocol sequence is deemed completed. That is, until the data is delivered to the requesting processor and it receives a next memory write clear command from the system bus. At that time, the lock mechanism unlocks the on-board memory, transfers the write command to the local memory for writing the data into the specified location, completing the sequence.
All further memory lock commands received from the system bus are refused by the on-board processor during the time the local memory is locked thereby ensuring proper operation. Also, this enables the use of different types of system bus protocols, such as a split bus cycle protocol.
In the second case, when the on-board processor's microprocessor issues a memory read lock command to an off-board memory (i.e., to another on-board processor's local memory or to system memory), the system interface circuits convert the command into the appropriate memory read lock command sequence which it applies to the system bus. All subsequent read requests to the off-board memory are converted into normal system bus request cycles. The first write command issued by the on-board processor to the off-board memory during the memory lock protocol sequence is assumed to be directed to the same memory lock region (i.e., word or double word) and is converted to a write clear system bus cycle. As discussed, when the command is accepted by the off-board memory, both lock mechanisms are cleared (i.e., the lock mechanism of the addressed memory lock region and the lock mechanism of the on-board memory). All subsequent memory read commands issued by the microprocessor to the off-board memory during the memory lock sequence are converted to normal system bus read cycles.
The system of the present invention through the use of such lock mechanisms is able to avoid the possibility of a deadlock situation. If a memory region is already locked, the microprocessor's wait state generator circuits can insert "waits" while the bus interface retry the operation until the memory region is unlocked. By maximizing the use of existing capabilities, the system is able to provide lock functionality with little additional circuits. Further, the system of the present invention enables tasks to be properly synchronized between processors relative to accessing memory resources, notwithstanding differences in the types of locking mechanisms utilized by such processors.
The above objects and advantages of the present invention will be better understood from the following description when taken in connection with the accompanying drawings.
FIG. 1 is a block diagram of a multiprocessor system which incorporates the locking mechanism of the present invention.
FIG. 2 shows in greater detail, one of the processors of FIG. 1 which incorporates the locking mechanism of the present invention.
FIG. 3 shows in greater detail, the locking mechanism of FIG. 2.
FIG. 4 shows in greater detail, the microprocessor of FIG. 2.
FIG. 1 shows a multiprocessor system 10 which includes a plurality of central processing units 10-2 through 10-6 and peer processors 12-2 and 12-4 which tightly couple in common to a system bus 16 and to a main memory or system memory 14. Each processor, as shown, includes a bus interface area which enables the unit to transmit or receive requests in the form of commands, interrupts, data or responses/status to another unit on system bus 16. In the preferred embodiment, the system bus 16 operates asynchronously and uses a split bus cycle protocol which provides higher performance by granting other units bus cycles during the period of time a unit is waiting for main memory to furnish data in response to an earlier request made by that unit. For further information regarding this type of bus interface and operation, reference may be made to U.S. Pat. No. 3,997,896.
Referring to FIG. 1, it is seen that each peer processor 12-2 and 12-4 includes a microprocessor 12-20, a local memory 12-30 and interface buses which couple to the bus interface circuits of block 12-40 as shown. The microprocessor 12-20 and local memory 12-30 are tightly coupled through a local processor bus 12-25. The microprocessor 12-20 is a high performance 32-bit processor which operates at clock speeds of up to 33 MHz and in the preferred embodiment corresponds to an Intel 80486 chip. The Intel 80486 chip includes a microprocessor, a floating point math coprocessor, a memory cache controller and an 8K RAM cache unit. The principal processing function is performed by the microprocessor while complex processing functions, such as floating operations, are performed by the math coprocessor. The internal cache unit provides fast access to the data required for processing. In the preferred embodiment, peer processors 12-2 and 12-4 operate under the control of a UNIX operating system.
In FIG. 1, the processors 10-2 through 10-6 function as host processors. In the preferred embodiment, each processor takes the form of a Bull DPS6000 system which operates under the control of the Bull HVS proprietary operating system. In the system of FIG. 1, each of the processors are organized to operate in an independent manner and have access to the full complement of system resources, such as input/output units, main memory and the like.
FIG. 2 shows in greater detail, the on-board processor 12-2 of FIG. 1. In the preferred embodiment, the microprocessor 12-20 and local memory 12-30, along with associated control circuits, in addition to clock generation circuits of block 12-22, are contained on a single daughter board as shown. The clock generator circuits of block 12-22 generate a single frequency clock signal CLKREF of 33 MHz which provides the fundamental timing and internal operating frequency for microprocessor 12-20, in addition to all of the other circuits which make up processor 12-2. The bus interface circuits, sets of command, address and data registers and state control circuits are contained on the mother board. These two boards make up the entire processor.
In greater detail, the microprocessor 12-20 and local memory 12-30 are tightly coupled to the address, data and command control processor bus lines as shown. The circuits of block 12-24 are used to control the microprocessor's access to processor bus by the generation of a bus hold signal DBHOLD as a function of control signals generated by an external state machine (XSM) 12-66 included as part of the mother board. As explained herein, such control is used to implement lock functionality relative to accessing local memory 12-30 in response to external requests according to the teachings of the present invention.
When processor 12-2 does not have an external memory lock operation in process (i.e., signal PTLOKFF is off), each external request received from system bus 16 to access local memory 12-30 which has been acknowledged by the system bus response logic circuits of block 12-90 is loaded into the corresponding receive data, address and command registers 12-42 through 12-46 in response to an enable signal CYCREQ generated by clock logic circuits, not shown. The address and command signals are converted into the appropriate form by address and command converter circuits of blocks 12-52 and 12-54 and stored in available registers of the two sets of queue registers of blocks 12-62 and 12-64, in response to signal CYFIFO. Thereafter, the stored address and command signals are applied to the processor bus via the driver circuits of blocks 12-72 and 12-74, in response to an enabling signal EADQTP. Additionally, the bus command signals are applied to the system bus response logic circuits of block 12-90. According to the present invention, these circuits include a lock flip-flop which stores an indication of having received a memory lock request from system bus 16 to access local memory 12-30.
Any data associated with a request loaded into register 12-42 is reordered as required by the programmable array logic (PALs) of block 12-50 and stored into the appropriate one of the register of block 12-60. The different bytes of the data words are swapped from the so-called big endian format of the system bus to the little endian format utilized by microprocessor 12-20. This is accomplished by the byte swap circuits of block 12-70 which is implemented by the proper reordering of connector pin connections.
The XSM state machine 12-66 generates the required control signals for executing external memory read and write requests. In response to an input signal RXHAVE, which indicates the receipt of a memory request, the XSM state machine 12-66 loads the request into one of the sets of registers of the two level queue. It also properly conditions the microprocessor control bus circuits of block 12-24 for enabling transfer of the memory request via signal EADQTP to local memory 12-30 via the local bus in the same form as those memory requests made by microprocessor 12-20. Also, the XSM state machine 12-66 generates the required signals for transferring local memory data to system bus 16 via data swap circuits 12-56 and a set of registers of an array 12-58.
A processor state machine control block 12-80 controls the processing of transactions or requests initiated by microprocessor 12-20. As shown, commands generated by microprocessor 12-20 are applied to a microprocessor to bus command generator of block 12-82 which, in turn, generates the appropriate system bus command. The bus command is loaded into a processor command register 12-84, along with the appropriate address and data. The address and data are loaded into registers 12-86 and 12-88, respectively. This is all done in response to an enabling load signal PTDTLD generated by state machine 12-80 as a function of the state of processor lock control signal PTLOKFF which is applied as an input to generator 12-82 and to the system bus response circuits of block 12-90.
FIG. 3 shows in greater detail, the system bus response logic circuits constructed, according to the present invention. As shown, the block 12-90 includes a memory lock flip-flop 12-901 which couples to system bus 16 and is set and cleared, in response to bus signals BSMREF, BSLOCK, BSMCLR and BSSHBC. Signal MMLKCK is used to clock the switching of flip-flop 12-901. The lock output signal LOCKFF is applied to a PAL circuit 12-902 together with bus signals BSMREF, BSLOCK and BSSHBC, in addition to processor lock signal PTLOKFF from system lock circuits 12-48. The PAL circuits 12-902 generate the required system bus response signals MMACKR through MMWAIT loaded into register 12-904 which are applied to system bus 16. Also, circuits 12-902 generate second half bus cycle acknowledgement signal CPSHBA which is inverted by circuit 12-906 and used for storing data received via system bus 16 from an off-board memory, during a system second half bus cycle. It also generates the signal MMLOCK which is used to generate clock signal MMLKCK.
FIG. 4 shows in greater detail, the microprocessor 12-20 and the different interface signals. The interfaces are divided into sections which denote the different functions which do not necessarily correspond with the physical layout of the Intel 80486 chip. The address bus and bus control lines comprise the majority of the lines. The address lines are bidirectional for accommodating the cache bus snooping capability.
The cache control section includes six pins for controlling the microprocessor's internal cache. The cache enable (KEN) input is most frequently used to disable areas of memory that cannot be cached. The address hold (AHOLD) and external address strobe (EADS) inputs allow an external device to present the microprocessor 12-20 with an address. If the address matches an address in the microprocessor's internal cache, the associated data is flagged as invalid. The flush (FLUSH) cache input is used to inform the microprocessor that the entire contents of its cache are invalid. The page write-through (PWT) and page cache-disable (PCD) output pins reflect the states of the page attribute bit settings in internal page table entry or page directory entry registers. They indicate caching control that software has exerted over logical memory pages.
The bus control section includes thirteen pins for controlling the processor's bus. The bus request (BREQ) output signal indicates that the microprocessor needs the address/data bus. The backoff input (BOFF) enables an external device to take control of the entire address/data bus even within an active, yet incomplete cycle. The pseudo lock output signal (PLOCK) is used by the microprocessor to indicate that the transaction it is performing requires more than one bus cycle to complete. By contrast, the bus lock signal (LOCK) is used to signal a critical read-modify-write operation in which no other system element can examine the item being modified until the current operation is complete. The microprocessor will not allow a bus hold request (HOLD) to take place wherein another bus master can complete control of the bus. That is, the microprocessor will not generate a hold acknowledge signal (HLDA) in response to a bus hold request.
The memory/input-output (M/IO), data/control (D/C), and write/read (W/R) signals are used to define the type of bus cycle being initiated. The address status output signal (ADS) indicates when these bus cycle definition signals and address signals are valid. The non-burst ready input signal (RDY) indicates that the current bus cycle is complete. The burst ready input signal (BRDY) and the burst last signal (BLAST) are used to carry out burst transfer operations.
The burst ready signal indicates that the current cycle is complete and the system will continue data transfer in the next clock cycle, unless the signal BLAST is presented. The BLAST signal signifies that the burst transfer is complete. For further information regarding the use of these signals, reference may be made to the Intel publication entitled, "i486 MICROPROCESSOR," dated November, 1989, Order Number: 240440-002.
With reference to FIGS. 1 through 4, the operation of the preferred embodiment of the present invention will now be described. It will be appreciated that semaphores or shared data structures can reside in system memory 14 or in the local memory 12-30 of processor 12-2 or 12-4. The semaphore ensures that a shared resource such as an area of memory is properly accessed by the different processors of the system. In the system of the present invention, locking mechanisms are in place which provides for any combination of semaphores notwithstanding the different types of locking protocols being employed.
It will be assumed that the microprocessor 12-2 issues a memory read lock command to perform a read-modify-write operation using the semaphore mechanism in system memory 14 represented by the shaded block in FIG. 1. This results in microprocessor 12-2 of FIG. 4 generating lock signal DBLOCK. This signal is applied to microprocessor generator 12-82. The generator 12-82 produces a system bus command as a function of signal PTLOKFF generated by system lock circuits 12-48. These circuits determine if processor 12-2 sent out a memory lock command which was acknowledged by any memory unit, including its own as explained herein. If such a command was received and acknowledged, then the processor lock command would not be issued to the system bus 16.
Assuming that no such command was received, the system lock circuits 12-48 do not generate signal PTLOKFF. This enables state machine 12-80 to generate load signal PTDTLD which loads the command into register 12-84 along with the address into register 12-86. This causes a test and set lock bus cycle to be issued to system memory 14. More specifically, read, test and set lock commands are signalled by setting signal BSLOCK to a binary ONE state while signal BSSHBC is set to a binary ZERO state.
The system bus command is processed in a conventional manner employing the standard memory lock protocol sequences. If the lock associated with the address bits OA through 22 is already set, the system memory will respond by forcing signal BSNAKR to a binary ONE. If processor 12-2 receives a WAIT or NAK response to the command, it will retry the operation. If the lock associated with address bits OA through 22 is not already set and the memory is not busy, the system memory will accept the command by forcing signal BSACKR to a binary ONE and then set the lock. Assuming that the system memory 14 acknowledges the command signaling its acceptance, the memory area is then locked.
Also, in response to the microprocessor memory lock command, the generator (PAL) 12-82 forces signal CPLOCK to a binary ONE state. This causes the setting of system lock circuits 12-48 via the system bus 16 to record the occurrence of the lock command. This enables the microprocessor 12-20 to continue operating as it does normally. That is, it still can issue another read lock operation immediately and even to the same memory structure. However, the command generator 12-82 converts the read to a generic read operation to preclude the occurrence of a deadlock condition.
The processor 12-2 continues its completion of the lock operation. During that time interval, any system lock command received by processor 12-2 from system bus 12 even through unrelated to the first command will be automatically ignored. That is, signal PTLOKFF from the system lock circuits 12-48 cause the PAL generator circuit 12-902 of FIG. 3 to generate a negative acknowledgement (NAK) signal on system bus 16. When microprocessor 12-20 issues a first write request, the microprocessor t bus command generator 12-82 converts this request into a write-clear command. That is, a write and clear lock command is generated by forcing signals BSLOCK and BSSHBC to binary ONES. The command is loaded into the register 12-84 along with the associated address and data into registers 12-86 and 12-88 in response to load signal PTDTLD.
When the write and clear lock command applied to system bus 16 is received and the system memory is not busy, it accepts the write and clear lock command by forcing signal BSACKR to a binary ONE and clears its memory lock for the addressed lock region. The write and clear lock command also resets the microprocessor's system lock circuits 12-48, forcing signals PTLOKFF to a binary ZERO state.
By assuming that the microprocessor's first write request will be directed to same lock-region of memory (i.e., 16 word block), this ensures that no deadlock condition will arise. All subsequently issued microprocessor write requests during the lock operation are converted into normal system write bus cycles.
The present invention enables access to the microprocessor's local memory 12-30 by system bus requests issued by any one of the processors of FIG. 1. It is assumed that one of the processors (e.g. processor 10-6) issues a memory read lock command to processor 12-2 to perform a read-modify-write operation using the semaphore mechanism in local memory 12-30 represented by the shaded block in FIG. 1. This results in processor 10-6 issuing a memory read lock request to system bus 16. The command, address, and data signals of the memory request are loaded into registers 12-42 through 12-46 in response to signal CYCREQ. As previously discussed, this results in the on-board memory lock flip-flop 12-901 being switched on which forces signal LOCKFF to a binary ONE.
The bus command signals are converted into the corresponding microprocessor bus lock command by the circuits of block 12-54 and loaded into one of the queue registers 12-64. Also, the bus lock signal RXLOCK stored in the queue command register is applied as input signal XBLOCK to the XSM state machine 12-66, along with certain subcommand control signals derived from decoding the converted command signals stored in queue register 12-64.
The XSM state machine 12-66 generates lock hold signal LOCKHOLD which is applied to microprocessor control bus circuits of block 12-24. This forces signal DBHOLD to a predetermined state which prevents microprocessor 12-20 from accessing the microprocessor bus until the read-modify-write operation is completed. That is, signal DBHOLD allows the local memory 12-30 to read out the contents of the addressed location, send the data contents back to the system bus interface circuits and wait for the data to be delivered to processor 10-6. Upon receiving the local memory data, processor 10-6 completes the sequence by issuing a memory write and clear lock command.
Upon the receipt of the memory write and clear lock command, the interface circuits load the address, data, and command into registers 12-42 through 12-46. The write command is converted into the appropriate microprocessor bus write command for writing the associated data contained in XTRDATA register of block 12-60 into local memory 12-30, completing the operation. Also, in response to the write command, the system lock circuits reset the memory lock flip-flop 12-901 which unlocks local memory 12-30 for allowing acceptance of another locking operation.
It will be appreciated by those skilled in the art that many changes may be made without departing from the teachings of the present invention. For example, the invention may be used in conjunction with different types of protocols and commands. Also, while the preferred embodiment utilizes different PAL circuits to perform certain functions that such functions can be combined in certain instances and performed within a single circuit. Also, the invention is not limited to any specific type of circuit.
While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the spirit of the invention as set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.
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|Dec 16, 1991
Owner name: BULL HN INFORMATION SYSTEMS INC. A CORPORATION
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:JOYCE, THOMAS F.;KEELEY, JAMES W.;REEL/FRAME:005945/0964
Effective date: 19911122
|Sep 2, 1997
|Surcharge for late payment
|Sep 2, 1997
|Fee payment
Year of fee payment: 4
|Sep 9, 1997
|Maintenance fee reminder mailed
|Jul 31, 2001
|Fee payment
Year of fee payment: 8
|Jul 26, 2005
|Fee payment
Year of fee payment: 12


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There's a range of other rural and remote scholarships available to medical students. You will find details of those that we think might be useful for you below.
The Rural Australia Medical Undergraduate Scholarship Scheme (RAMUS) is one of a number of Commonwealth Government initiatives to increase the number of students with a rural background who enter and complete their study of medicine. These scholarships provide rural students with financial assistance to meet the costs associated with moving away from their home to undertake their studies. The National Rural Health Alliance administers the RAMUS Scheme on behalf of the Commonwealth Government.
You can search the site for scholarships which may help you get into university or make it easier for you to stay there. When it comes time to get some practical experience and you want to go bush, you will be able to search for grants to help you do so.
If you are planning to study at a university in NSW or the ACT (or are already there), then browse through the data from various universities, organisations and government departments that promote rural health. There are links to all universities offering health courses and to the agencies administering scholarships.
The Puggy Hunter Memorial Scholarship scheme is funded by Australian Government Department of Health. The Scheme was established in recognition of Dr Arnold 'Puggy' Hunter's significant contribution to Aboriginal and Torres Strait Islander health and his role as Chair of the National Aboriginal Community Controlled Health Organisation (NACCHO).
The aim of the scheme is to encourage and assist Aboriginal and Torres Strait Islander undergraduate students in health-related disciplines to complete their studies and join the health workforce.
Applicants for this scholarship must be Aboriginal or Torres Strait Islander. For the purposes of this scholarship, an Aboriginal or Torres Strait Islander is someone who is of Australian Aboriginal or Torres Strait Islander descent, or who identifies as an Australian Aboriginal or Torres Strait Islander and is accepted as such by the community in which he or she lives or has lived. Applicants will be asked to provide a letter from an Aboriginal or Torres Strait Islander community organisation supporting their claim. Please note that it is the responsibility of applicants to seek advice from Centrelink on how the scholarship payment may affect ABSTUDY or any other government payment.
For a further list of scholarships available to health students, visit the National Rural Health Students Network (NRHSN) website scholarships page.


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This city hotel comprises a total of 50 rooms of which 29 are doubles. Facilities within the building include a lobby with a 24-hour reception desk and a hotel safe. Guests may like to make use of the restaurant, the conference facilities and WLAN Internet access (charges apply). Those arriving by car may take advantage of the hotel's private car park free of charge. A bicycle hire service as well as room and laundry services complete the range of services offered at this establishment. The hotel offers a free airport shuttle to the terminal.
This hotel is located around 100 m from Berlin Sch�nefeld Airport and some 500 m from links to the public transport. The city centre and various lakes lie within 20 km of the airport and a park within 10 km.
The comfortably fitted rooms come with an en suite bathroom with hairdryer, a direct dial telephone, satellite/cable TV, Pay TV, a fax machine and a radio. other in-room amenities include a minibar/fridge, a double bed, Internet access and underfloor heating.
Guests may make use of the sun terrace and, for an additional fee, the sauna and the massage service.
Guests may select their breakfast from a buffet. Lunch and dinner may be selected from the � la carte menu or alternatively chosen from the set menu. A bottle of water from the minibar is offered free of charge.
American Express, Diners Club, MasterCard and VISA are accepted as methods of payment.
Room Facilities:
Direct dial telephone
Satellite cable TV
Internet access
Double bed
Central heating


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text: Update: Carib Sports player receives $2,000 payment By SBR Monday, June 6, 2016 Share with: A Carib Sports (SBR rating B-) player has reported receiving payment. The player originally complained to SBR that he had requested a withdrawal dated April 27 that had not yet been fulfilled. Sportsbook Review reported on May 10 that Carib Sports' eWallet availability was a hot topic at SBR Forum as gamblers expressed frustration at the lack of cashier options. The player was one of many who felt that Carib Sports should at least offer a different solution at the same cost to receive payment pending the return of eWallet. The player has now confirmed that he received a $2,000 payout through an alternate method which was the max that he could be paid in a calendar week. He plans to take out a further $1,000 using this workaround solution. The complaint is considered closed for the time being. Carib Sports players with feedback are encouraged to write to firstname.lastname@example.com. Alternatively, Carib Sports players in need of assistance are asked to submit a sportsbook complaint form.


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All your housekeeping needs, move in/ move out specials. Over 15 years experience. Weekly, biweekly, monthly rates available. References. 10% senior discount. I also provide Office and Commercial work. I am a hard worker not only do I clean I disenfect as well. I take pride in what I do to assure customer satisfaction.
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At my company I got a restriction for using SpiceWorks with scanning functionality, so I implemented standalone agents using 443 port. Anyone knows How Can I do for extracting information from Microsoft exchange and AD using standalone way.
This topic was created during version 5.1.
The latest version is 7.5.00101.
2 Replies
Jun 18, 2011 at 12:10 UTC
IT Journey, LLC is an IT service provider.
You can install Spiceworks directly on each of those servers and set them up as remote collectors. Then they will report back to the main spiceworks install for central viewing.
This is typically only used for remote office, but it should work just fine for what you are wanting to do.
Do you know why they are restricting the scanning?
Jun 18, 2011 at 7:52 UTC
Thanks for your help. They are restricting it because you have to enter a user and password. This environment is used for serveral system administrators, so using this saved user and password you could kill process on servers. In addition the company i work for has a strong policy about management users and passwords and spiceworks doesn't have a security module. For examples they want some features like user expiration, blocking user after tries, and other things.
This discussion has been inactive for over a year.
You may get a better answer to your question by starting a new discussion.


text:
Previous - Find Allies in the Government (CYOAH)
Himmler decides that the most important thing to be done is build the military. Mandatory conscription is reinstated, and the military is vastly increased. This is an obvious violation of the Treaty of Versailles, which angers the former Entente Powers. However, nothing is done at the time to stop it, other than a few harsh words.
Himmler, however, knew that the large army was useless if it had nowhere to go. He looked through his choices: Poland, Czechoslovakia, and France. All of them possessed territories that Germany wanted. This would have to be decided carefully.
Doctor Evulz (talk) 02:21, December 18, 2012 (UTC)


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Vintage Collectible Griswold Black Cast Iron Skillet
- Sold for: Start Free Trial or Sign In to see what it's worth.
- Item Category: Furniture & Furnishings
- Source: eBay
- Sold Date: Nov 03, 2007
- Channel: Auction House Sell similar item on eBay
This vintage cast iron skillet measures about 7 1/2". It is marked on the bottom "Cast Iron Skillet", 8, Griswold (in logo of 2 circles with Griswold on the crossbar of an embossed cross), Erie, PA U.S.A. and at the very bottom, 699 A".This skillet was purchased with the Griswold griddle which is also up for auction.


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Kopal Institute of Science & Technology
Madhya Pradesh
Total Students
Fees Range
How to reach
Kopal Institute of Science & Technology is situated at Near Neelbad Square, Kalkheda, Bhopal, Madhya Pradesh in Bhopal.
Courses Offered
- 4 Years
- Bachelor of Engineering-B.E.
- Engineering
- 4 Years
- Bachelor of Engineering-B.E.
- Engineering
- 4 Years
- Bachelor of Engineering-B.E.
- Engineering
- 4 Years
- Bachelor of Engineering-B.E.
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- 4 Years
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- Engineering
- 2 Years
- Master in Technology-M.Tech
- Engineering
- 2 Years
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- Engineering
- 3 Years
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- 3 Years
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Kopal Institute of Science & Technology - KIST
The history of imparting formal technical education in India can be traced back to mid 19th century , although it got momentum in 20th century with the set up of Constitution of Technical Education Committee of the central University Board of Education (CABE) in 1943 Preparation of Sergeant Report in 1944 and Formation of All India Council of Technical Education (AICTE) in 1945.With the country gaining independence in 1947,the development of technical education had become a major concern for the government of India to face the new challenge and move the country forward. Technical Education plays a vital role in human resource development of the country by creating skilled manpower, enhancing industrial productivity and improving the quality of life .Technical Education covers courses and programmes in engineering technology, management ,architecture, town planning, pharmacy and applied arts & crafts, hotel management and careering technology . One of the main triggers for growth in Indian economy is the explosion in the IT sector. In order to sustain the current growth rates in the new knowledge economy sectors, the pool of technical talent needs to continue to grow, which is attracting private players in the sector. With the increasing role of private institutions in technical education ,quality assurance becomes mere accreditation agencies is an official endorsement, the perception of students with respect to the quality of the programmes offered by these technical institutions plays an important role in their success .There are many factors that contribute to these perceptions as well the delivery of high quality education. The basic academic philosophy of Kopal Shiksha Evam Jan Vikas Samiti,Bhopal has been to provide sound higher technical professional education to prepare their product to meet the challenge in the 21st Century .The students should be equipped with theoretical knowledge, clear in their concepts and refined through the laboratory work, assignments and projects that will make them independently tackle problems in the field. The students should make full use of the computational facilities, library in achieving these tasks. Equal importance is to be given on practical training and internship with the industry, during summer vacations. Such training will be arranged for the students to give them a distinct competitive edge.
Nearby Hangout
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The College has Excellent infrastructure Facilities.
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Our library is well stocked with good number of books ralated to the curriculum. The college library has vest number of volumes. Apart from these we also have a comprehensive and in-exhaustible collection of reference material , magazines and journals, library also subscriptionod Del Net for the online access of scientific and engineering journals. All leading national and local news papers and news magazines are also available in the library. There is a provision of books for all students under the book bank. Reprographic facility is aslo available.
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|Specific References
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|Recombinant Human Carbonic Anhydrase II protein (Catalog#10478-H08E)
|Rabbit IgG
|0.2 μm filtered solution in PBS with 5% trehalose
|This antibody was obtained from a rabbit immunized with purified, recombinant Human Carbonic Anhydrase II (rh Carbonic Anhydrase II; Catalog#10478-H08E; NP_000058.1; Met1-Lys260).
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No cross-reactivity in ELISA with
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ELISA: 0.1-0.2 μg/mL
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text:
August 12, 2016
Solo claims Sweden was 'cowards' after USA elimination
By Michael Lewis
BigAppleSoccer.com Editor
Well, Hope Solo was at it again Friday afternoon.
No, she wasn't making any saves to save the U.S. women's bacon in their Olympic quarter final elimination to Sweden in Brasilia, Brazil.
It was her reaction to the defeat after the Swedes handed the Americans their earliest elimination from a tournament -- Women's World Cup or Olympics.
Solo called Sweden "a bunch of cowards" after the Americans were shown the door at the Rio Olympics as they lost in a shootout, 4-3, following a 1-1 draw over 120 minutes of regulation and extratime.
"I'm very proud of this team," Solo told reporters. "But I also think we played a bunch of cowards.
"The best team did not win today. I strongly believe that. I think you saw American heart. You saw us give everything we had today," she told SI.com's Grant Wahl.
Asked why she called the Swedes cowards, Solo replied that she wasn't impressed with their tactics.
"They dropped into a 50," she said. "They didn't try and press. They didn't want to open the game. And they tried to counter with longballs. We had that style of play when Pia was our coach. I don't think they're going to make it far in the tournament. I think it was very cowardly. But they won. They're moving on, and we're going home."
Pia is Pia Sundhage, the Swedish coach. Sundhage directed the USA to a pair of gold medal victories in 2008 and 2012 and to the finals of the 2011 Women's World Cup, where the USA lost in a shootout to Japan.
Sundhage's reply to Solo's comments?
"I don't give a crap," she said. "I'm going to Rio, she's going home."
Sweden will play the winner of the Brazil-Australia Friday night, in Rio de Janeiro on Tuesday.


text:
posted by John Christian .
What are irrational, rational, and natural numbers?
A rational number is a number that can be written as a ratio. That means it can be written as a fraction, in which both the numerator (the number on top) and the denominator (the number on the bottom) are whole numbers.Every whole number is a rational number, because any whole number can be written as a fraction. For example, 4 can be written as 4/1, 65 can be written as 65/1, and 3,867 can be written as 3,867/1.
All numbers that are not rational are considered irrational. An irrational number can be written as a decimal, but not as a fraction.
An irrational number has endless non-repeating digits to the right of the decimal point.
Although irrational numbers are not often used in daily life, they do exist on the number line. In fact, between 0 and 1 on the number line, there are an infinite number of irrational numbers!
this is not a question


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I really don't have any plans whatsoever to play WoW again. Although they always seem to get me when I'm on my Winter vacation with that 10 free days thing... I always end up hitting the cap and PvPing, which gets old after a while.
Anyway I'm hoping that SE fills the December update with more stuff so I can stick around.
Generally, and as others have already answered FFXIV is niche and it will always be, regardless if it had a perfect launch or not. There might be a few leaving to WoW or checking it out, but either they're here or they aren't and I hope FFXIV ends up with a strong community regardless.


text:
Although the book is vague on the details of how the world came to its current state, one is able to extract this information:
At the end of 20th century, national governments of the world collapse because of so-called unlimited democracies. These "unlimited democracies" are the fraudulent Marxian definition of value from which "Communism derives" and civil unrest due to a "pre-scientific pseudo-professional class" who called themselves Social Workers and Child Psychologists banning Corporal Punishment.
In 1987 there is war between the Russo - Anglo - American Alliance and the Chinese Hegemony. Shortly before the war's end, a group of intellectuals perform a coup d'état in an attempt at creating a utopia. This incident later came to be known as the Revolt of the Scientists. . At the end of the war the Treaty of New Delhi was signed. This treaty freed prisoners captured by the Russo-Anglo-American Alliance. However left approximately 65,000 civilians (Japanese, Filipino and Russian) and 2 divisions of British Paratroopers in Chinese incarceration to be sentenced for political crimes, forcing the abandoned prisoners to escape to gain freedom.
It should also be noted that at the end of the 20th century, the North American Republic was brought down by raging illegal activity which took place all around the world, including Russia and the United Kingdom. Crime was at its peak for most of the second half of the 20th century, lasting up to the war between the Russo - Anglo - American Alliance and the Chinese Hegemony.
After the collapse of national governments, a group of veterans in Aberdeen, Scotland formed a vigilante group to stop rioting and looting. They hanged a few people (including 2 veterans) and decide to only allow veterans to join their committee due to a mistrust of politicians. This contingency plan became routine after a couple of generations, and this group of vigilantes was the start of the Terran Federation.


text:
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This is page 1 of 1 (This thread has 19 messages.)
Free Schools in East Suffolk ...why(19 Posts)
... did they allow them to open in areas where there are 38% and 28% suplus school places currently, rising to 45% and 31.5% in 2015 (and that is calculated without the Free Schools)?
The Dept of Education have finally released the impact assessments for Beccles and Saxmundham Free Schools. See https://www.gov.uk/government/uploads/system/uploads/attachment_data/file/251353/Beccles_Free_School-_Impact_Assessment_2012.pdf and https://www.gov.uk/government/uploads/system/uploads/attachment_data/file/251405/Saxmundham_Free_School-Impact_Assessment_2012.pdf
The reports admits that the Free Schools will undermine the viability of the closest alternative Academies, leading to instability and possible redundancies. For the next few years, these other schools, are given significantly lower per capita funding than the Free Schools, so cannot offer the pupil inducements that the Free Schools can. It will make planning difficult.
Meanwhile, seventeen miles away in East Ipswich there is a significant shortage of school places. To my mind this is absolutely bonkers!
But who says any government is sensible when planning school places??? Planning schools has, effectively, been taken away from locally elected authorities in the name of 'choice'. Many authorities are now struggling to provide enough school places and why bother if there is a Gove free school likely to pop up and disrupt everything? It is such a waste of money to have these 'vanity' school projects where they are not needed but unfortunately Gove is going to trample on everyone to get his way and support a tiny minority rather than do the best for the majority.
The clue is in the paragraph that says educational standards in Suffolk are below the national average and have been for some time. The government presumably believes that introducing new schools with a strong academic focus will help to resolve this issue. The question is whether we only allow new schools where there is a shortage of places or whether we also allow them where existing provision is poor.
Free schools have to find most (and in many cases all) of their startup costs themselves. Allowing free schools to open where there is no shortage of places does not necessarily mean that they cannot also open where there is a shortage.
By the way, free schools receive the same per capita funding as academies. This is a little higher than community schools to cover the services they do not receive from the LA and therefore have to fund themselves.
'Free schools have to find most (and in many cases all) of their startup costs themselves'
I've never heard that before. Start-up expenses up to and including the first year paid by the state are here.
IES Breckland = £720,036
Beccles Free School = £2,093,628
Stour Valley = £1,048,167
You're wrong about the quality of surrounding schools here too, prh. There are two schools near free schools in Beccles and Sudbury rated 'Good' but their viability is threatened in a low population density area if free schools open next door and their ability to offer the full curriculum is in doubt. There a Radio 4 programme you can download as a podcast that has an interview with the head of one of these neighbouring schools.
In Suffolk because there was a reorganisation that involved closing middle schools, sponsors including a private school foundation and a for-profit provider too advantage of available sites. But they did not do this out of a sense of altruism in lifting the standards of the sector as a whole.
straggle - I am not making any comment on the quality of surrounding schools, simply noting that the impact report states that educational standards in Suffolk are generally below the national average and have been for some time. Figures on the DfE website confirm that Suffolk is indeed below the national average and has been since at least 2009 with the gap widening every year.
The spreadsheet to which you link is measuring something a little different. I was talking purely about startup funding. I got my information from the government's response to an FoI request which can be found here. You have in any case highlighted some of the higher figures. The spreadsheet to which you link shows 1 open school with zero pre-opening expenditure and 5 with £25,000 or less. Even if we include post-opening expenditure there are still 6 schools with £50,000 or less, all but one of them below £25,000.
Just to quantify the gap between Suffolk and the rest of England, in 2012 50.5% of students in Suffolk achieved 5+ GCSEs at grades A*-C or equivalent including English and maths. The figure for England as a whole was 59.4%.
Sorry - "below £25,000" should be "£25,000 or less".
The gap between Suffolk/Norfolk and rest of England has always been so, even 15 years ago when my dc were there.
Many of the children in the small village schools came from farming communities and weren't very ambitious when it came to education. The parents seeking a better education/more robust sent them further a field.
I am not being mean because it takes all sorts and my dc enjoyed there time at there little school.
Their usual chant included:
We can't read and we can't write, it doesn't seem to matter.
We are Norwich City fans, and we can drive a tractor.
prh that FOI data was incomplete and concealed other costs invoiced later. My spreadsheet was published by DfE too
I am aware of that. It is measuring something slightly different. The FoI reply, for example, was only about startup costs and did not include post-opening costs. My point remains that many free schools have to fund a significant proportion of their startup costs themselves.
You don't improve education in a county as a whole by building a free school in the catchment of two already good schools - you site one where schools are poor. So why doesn't Newmarket have a free school?
Sorry, but to my mind it feels as if the Beccles Free School has been set up because there are easy academic pickings to be had where it is so it can look good without much effort. If there had been any other intent, the school would have set up where it was truly needed, in an area where schools genuinely needed competition in order to raise standards.
prh47bridge Your comments are interesting but I think the priority should be to ensure school places for all in areas of school place shortages, rather than some kind of competition in areas of over supply (particularly given there was hugh opposition to the Free School in Beccles, even from the Tory MP.)
With regard to per capita funding, I was advised that for the first few years, free schools are funded as if they were full to capacity (which last year neither Beccles nor Saxmundham were). The exisiting Academies are only paid for the students they actually had on roll. Given that there is such oversupply of school places in that part of East Suffolk, that difference gives the Free Schools an unfair financial advantage. A local blog (talking about another Free School in West Suffolk ) explains it blog.hargrave.org.uk/search?q=clare
When considering Suffolk's education performance, it is worth remembering it is a huge county with very different performance depending on area. The report does not make that clear. If you wanted to raise performance in areas which required it, then there are better places in Suffolk to place a free school (such as West Ipswich).
I have no problem with choice and competition - the location may not address school places but I suspect if the local community get behind it and get involved, these schools will thrive. Its a sign of the times when Hackney is mentoring Suffolk (a failing county) on educational progress.
Isn't Saxmundham having another development at the top of Rendham Road anyhow that will boost numbers?
Setting a Free school up in Newmarket is seen by many to be divisive. A Free School application in Newmarket has been turned down as would impact negatively on school nearby.
EmeraldJeanie there was a lot of opposition to the Beccles Free Scholl too, and that was pushed through - which makes me pretty damn suspicious.
I'm opposed to Free Schools in any case - I always was, and the Al Madinah affair has hardened that for me. The only exception I can see is Free Schools catering specifically for SEN, since the state sector is so bad at SEN provision (and that lies at the door of both the current and previous governments).
In every other case I feel that my taxes would be far better spent on improving what we have - and that includes buildings, DD1's school was on the BSF programme but is not on the new programme for better buildings and it is a disgrace - rather than on the vanity projects of a few people. I'm all for new schools where new schools are needed, and I definitely think local parents should be consulted, but the Free Schools programme as it stands is a disaster.
Just checked the census (taken January 2013 so last school year) and there were the following numbers in year 7:
Beccles Free School: 27 (admission number 108)
Saxmundham Free School: 26 (admission number 108)
Both are operated by a private school foundation (120 pupils per year) and received £2 million in revenue up to and including their first year, not including capital costs. That's a complete waste of money but I don't even see how a mixed ability secondary school can be effective with 108 children.
Saxmundham Free School: The year 7 to start in September is already over subscribed (the school has re-organised to be able to take in more pupils than their previous maximum). They've just been OFSTED inspected and rumour has it it was an excellent one. If it's an Outstanding or Good when published, that will attract more parents and children. Does that change opinions at all I wonder?
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Why You Should Try Yum Cha (+Oolong)
Translated literally as "drink tea," Yum Cha is a Chinese-style brunch tea that originated to China and has spread as far as Australia and the U.S. and Canada, where it's known as Dim Sum (in Cantonese, Dim Sum refers to the small plates of food that are served, while Yum Cha refers to the whole experience).
The Tea Ritual
Yum Cha is a communal experience: Groups of friends, family, or co-workers often go out for Yum Cha, where tea and food are shared among the members of the table. Serve tea to others at the table first, then yourself. If someone else serves you tea, show thanks by tapping your pointer and middle finger on the table. Out of tea? Turn the lid over, and it'll soon be refilled. Tea is a traditional drink of choice at Yum Cha for its use in aiding digestion. We think LiShan Oolong or Wenshan Baochung Oolong would be perfect at Yum Cha.
The Food
At Yum Cha, you won't order from a menu – instead, you'll be offered small servings of food from carts roving the dining room. Steamed dishes (read: dumplings) abound, but there's also braised meats, noodles, and other goodies to be had. Some of our favorites are the classic chai siu bao, tender pork-stuffed steamed buns, and cheong fun (rice noodles with prawns, beef, or pork). For dessert, there are often egg tarts and mango pudding.
Do I have to use chopsticks? No – but you should try! For items that are notoriously difficult to pick up, such as button mushrooms, it's acceptable to spear your food with a toothpick.
The bottom line: For its good food, good tea, and good company, Yum Cha is a tradition that has spread worldwide.


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Cipha Sounds fucked up.
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Get Rich or Die Tryin' Appreciation Thread
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Cipha Sounds fucked up.
raw tomatoe eating faggots, who cares about haiti, cipha sounds needs to finish what god started wit the earthquakes b2 Weeks ago in Off Topic
Gran Turismo 5 Official Discussion Thread
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Splinter Cell HD Trilogy Collection Official Discussion Thread
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Great set for fans!
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Nikhil Parekh
Fountain Pen - Poem by Nikhil Parekh
I scribbled innumerable lines of literature with it,
it was still ready to execute a umpteenth phrases more,
being as strong as an ox when it came to decoding thoughts into verse,
even when tested at bizarre limits of endurance.
i sketched glowing peaks of mountain basking in the golden Sun,
weaving articulate outlines of the encroaching shadows,
it yielded to the faintest of my caress; unleashing dark forms with fountain ink,
a true stalwart engulfing me in the times of difficulty.
i even used it for scraping minute blotches of dirt from my ear,
delicately tickling the inner soft skin with insipid strokes,
it obliged pathetically to whatever i did,
didn't shed a tear from its eye; nor developed a retaliatory hole in its heart.
i filled it with surplus amounts of colored ink,
sprinkling the same with lots of glee on the faces of my counterpart mates,
transforming them into jocular clowns,
with an awe-inspiring caricature of white skin with opalescent paint.
i kept it well stuffed within the interiors of my waistcoat pocket,
lived with it for all night and Sunlit day,
it had fulfilled my insatiable desire to explore the world,
assisted me create the animate; and already burried,
i hardly skipped exiting my place of dwelling,
without the reassuring comfort of my chrome tipped fountain pen.
Topic(s) of this poem: poetry
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2010 Alpamanta Estate Malbec
Retail: $32.49
$24.98per bottle
Product Description:
"Bright medium ruby. Dark fruits, smoked meat, nutty oak, coffee and a whiff of truffle on the slightly portly nose. Fat and sweet, with flavors of coffee, truffle and game lifted by sound acidity. The sweet, pliant fruit lingers nicely on the back end, where the tannins are supple and ripe.
All Alpamanta wines are made out of organic grapes and manipulation of the vinification processes from harvest to bottleing is kept to a minimum -low amount of sulfites, native yeasts, simple packaging, etc.- by using state of the art technology and focusing on producing excellent wines.
These wines are made with the best grapes from our vineyard, where maceration started at cold temperature previous to fermentation. Once alcoholic fermentation was completed at 26ºC, a postfermenting maceration took place over the next 7 days, making a total of 28 tank days and then aged 10 months in French oak barrels." - Winery


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Excellent 1665 SF retail space on the busy stop light corner of 171st and 80th. Anchor tenants include Jimmy Johns, Dunkin Donuts, Bo Rics, Dollar Store and Plush Horse Ice Cream. Traffic counts at 40,000 cars per day. Newer parking lot with ample parking. Perfect for any office/retail use. Immediate Occupancy. Bring your ideas.
The listing information set forth on this site is based upon information which we consider reliable, but because it has been supplied by third parties to our franchisees (who in turn supplied it to us) , we cannot represent that it is accurate or complete, and it should not be relied upon as such. The offerings are subject to errors, omissions, changes, including price, or withdrawal without notice. All dimensions are approximate and have not been verified by the selling party and cannot be verified by Sotheby's International Realty Affiliates LLC. It is recommended that you hire a professional in the business of determining dimensions, such as an appraiser, architect or civil engineer, to determine such information.


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In the summer of 1997, at the Gordon Research Conference on the Origin of Life, Harvard Univ. paleontologist Andy Knoll and I got into a conversation about how standard analytical techniques of mineralogy might be applied to the study of fossils. That conversation led to a series of collaborations with Knoll students. My first efforts were simply to map fossil carbon in plant fossils, such as ancient wood and a variety of species from the famed Rhynie Chert of Scotland (Boyce et al., 2001; 2003; 2007). Kevin Boyce worked at the Geophysical Lab with Marilyn Fogel on isotopes and with George Cody on x-ray microscopy as well.
I've subsequently worked with Prof. Nora Noffke (Old Dominion University) on a variety of Archean samples with evidence of ancient microbial mats (Noffke et al. 2003; 2006a; 2006b; 2007).
Boyce, C.K., R.M.Hazen and A.H.Knoll (2001) Nondestructive, in situ, cellular-scale mapping of elemental abundances including organic carbon in permineralized fossils. Proceedings of the National Academy of Sciences (US), 98: 5970-5974.
Noffke, N., N. Nhleko and R. M. Hazen (2003) Earth's earliest microbial mats in a siliciclastic marine environment (2.9 Ga Mozaan Group, South Africa). Geology 31, 673-677.
Hazen, R.M., A. Steele, G. D. Cody, M. L. Fogel and W. T. Huntress, Jr. (2003) Biosignatures and abiosignatures. Astrobiology 2, 512-513.
Boyce, C.K., G.D.Cody, M.L.Fogel, R.M.Hazen, C. M. O'D. Alexander and A. H. Knoll (2003) Chemical evidence for cell wall lignifications and the evolution of tracheids in early Devonian plants. International Journal of Plant Science 164, 691-702.
Noffke, N., N. Beukes, J. Gutzmer and R. M. Hazen (2006a) Spatial and temporal distribution of microbially induced sedimentary structures: a case study from siliciclastic storm deposits of the 2.9 Ga Witwatersrand Supergroup, South Africa, Precambrian Research 146, 35-44.
Noffke, N., K. A. Eriksson, R. M. Hazen and E. L. Simpson (2006b) A new window into Early Archean life:microbial mats in Earth's oldest siliciclastic tidal deposits (3.2 Ga Moodies Group, South Africa). Geology 34, 253-256.
Noffke, N., N. Beukes, R. M. Hazen and D. Swift (2007) Exceptionally preserved microbial mats of Meso-Archean age: the Sinqueni Formation, Pongolo Supergroup, South Africa. Geobiology, in press.
Boyce, C. K., C. L. Hotton, M. L. Fogel, G. D. Cody, R. M. Hazen and A. H. Knoll (2007) Devonian landscape heterogeneity recorded by a giant fungus. Geology 35, 399-402.
I. Research with Prof. Kevin Boyce (Univ. Chicago):
1. Early wood fossils that show cellular structures: These were our first tests of electron microprobe analysis of carbon in ancient fossils.In these maps red indicates the highest concentration of carbon.
2. Work on the Rhynie chert: described in the abstract from Boyce et al. (2003): "Anatomically preserved land plant fossils from the Lower Devonian Rhynie Chert contain conducting tissues with cells that range from dark colored, elongated cells without secondary wall thickenings to tracheids similar to those of extant tracheophytes. A suite of tissue-specific microanalytical techniques was used to assess lignification in fossils of Aglaophyton, Rhynia, and Asteroxylon. Isotope ratio mass spectrometry provides millimeter-scale resolution of carbon isotopic abundances, whereas soft X-ray carbon (1s) spectromicroscopy provides micron-scale resolution of the preservation of organic molecular functionality. The isotopic and organic chemistry of Rhynie Chert plants suggests that the earliest vascular thickenings were probably unlignified and that cell wall lignification may have first appeared in the outer cortex. Only later, it seems, was lignin deposited in conducting cells to produce the true tracheids seen today in vascular plants."
3. Work on Prototaxites: From the abstract by Boyce et al. (2007): "The enigmatic Devonian fossilPrototaxites Dawson 1859 consists of tree-like trunks up to a meter in diameter and eight meters long built of interwoven tubes 5 to 50 microns in diameter. Carbon isotopic abundances of Prototaxites specimens from five localities differ from those of contemporaneous vascular plants, exhibiting a range of δ13C values, within and between localities, of up to 13‰. Pyrolysis-gas chromatography/mass spectrometry (GCMS) highlights compositional differences between Prototaxites and co-occurring plant fossils and supports interpretation of isotopic distinctions as biological rather than diagenetic in origin. Such a large isotopic range is difficult to reconcile with autotrophic metabolism, suggesting instead that, consistent with anatomy-based interpretation as a fungus, Prototaxites was a heterotroph that lived on isotopically heterogeneous substrates. Light isotopic values found in Prototaxites approximate those of vascular plants from the same localities; in contrast, heavy extremes appear to reflect consumption of primary producers with carbon-concentrating mechanisms, such as cryptobiotic soil crusts or, possibly, bryophytes. Prototaxites biogeochemistry, thus, suggests that a biologically heterogeneous mosaic of primary producers characterized land surfaces well into the vascular plant era."
II. Research with Prof. Nora Noffke (Old Dominion University) on ancient microbial mats: Noffke has pioneered the study of Archean microbially induced sedimentary structures (MISS), such as wrinkle textrures, roll-up features, filamentous mat-like structures, and distinctive binding and trapping of sedimentary grains.
III. Research on Doushanto, China, phosphatic microfossils with Prof. Shuihai Xiao (Virginia Tech): Summer intern David Olesh from Harvard University also did research on these specimens.
IV. Eozoons????: OK, so here's an enigma. Does anybody have any information on so-called "eozoons" from the Precambrian Belt Formation? Here's a description of a recent find of enigmatic carbonate rocks from the Langel Ranch, Manhattan, Montana. On August 13, 2007, I had the opportunity to examine briefly a carbonate outcrop near the banks of the Gallatin River, located just below the home of Tom and DeeAnn Langel on their ranch in Manhattan, Montana. The outcrop represents approximately 8 meters in vertical section, and perhaps 10 meters in lateral extent. Outcrop and hand specimens feature two interleaved lithologies – a blue-grey limestone and a buff chert – that form a variety of unusual patterns, as illustrated below. By the way, my hunch is that these rocks represent some kind of physical separation of immiscible fluids – one aqueous and carbonated, the other siliceous and oil-rich. But if anyone knows, please let me know!
Calvert County Fossil Collecting
Since 1993 Margee and I have actively collected fossils along the Miocene cliffs of the western shore of the Chesapeake Bay. Most specimens, including molluscs and vertebrate remains, have been found in the float. We donate most of these specimens to middle school science teachers for use in classrooms. However, we have also found a few important mammal specimens, including whale, dolphin, and seal material. These specimens are donated to the Calvert marine Museum.


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