text:
|Publication number
|Publication type
|Application number
|Publication date
|Sep 5, 2006
|Filing date
|Jun 30, 2000
|Priority date
|Jun 30, 2000
|Fee status
|Publication number
|Ben Speiser, Ronald P. Bianchini, Jr., Jeff Schulz
|Original Assignee
|Marconi Intellectual Property (Ringfence), Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (10), Referenced by (50), Classifications (19), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention is related to transferring fragments between port cards and fabrics. More specifically, the present invention is related to transferring fragments between port cards and fabrics with gigabit transceivers.
The switch originally was designed to have high-speed HSTL point-to-point connections between port cards and fabrics running at 250 MHz. This was proven to be too fast and signal integrity could not be guaranteed due to the long trace length that exist. A more robust method had to be devised. The new method uses a network of gigabit transceivers between port cards and fabrics. The gigabit network is comprised of gigabit transmitters and receivers that communicate with each other at up to 1.3 GHz. The interfaces to each transceiver are an 8-bit data bus running at 125 MHz. Since the frequency of operation was reduced by half, the bus widths had to be multiplied by two. This new method provides to be more robust and has better noise rejection since the gigabit transceivers use differential pairs to communicate with each other. Since these gigabit transceivers are replacing point-to-point buses and some buses are larger than 8 bits wide, multiple gigabit transceivers need to be used to make up these buses. The initial total number of gigabit transceivers required was as follows: 22 transmitters per Striper, 40 receivers per Aggregator, 52 transmitters per Separator and 28 receivers per Unstriper. For a 480 G switch, this would total to about (48 port cards)(4Stripers)(22)+(13 fabrics)(9 Aggregators)(40)+(13 fabrics)(9 Separators)(52)+(48 port cards)(4 Unstripers)(28)=4224+4680+6084+376=20364. This large number of gigabit transceivers proved to consume too much power and take up too much boards space. At an average of 0.29 Watts of power dissipation per transceiver, the total power dissipation would have been 5,905 Watts (20364)(0.029).
The present invention using the gigabit transceivers solves the following problems:
This optimization solves all the above problems by intelligently allocating gigabit transceivers to be re-used in modes where they can be re-used. This technique allows changes in the configuration of the switch (40 G, 80 G, 120 G, etc.) To alter the gigabit transmitter and receiver assignment to be un-synchronized as long as the switch configuration is changed up or down by one step in the configuration.
A switch which stripes data onto multiple fabrics and sends parity data to another fabric has been described in U.S. patent application Ser. No. 09/333,450, incorporated by reference herein. See also U.S. patent application Ser. No. 09/293,563 which describes a wide memory TDM switching system, incorporated by reference herein.
The present invention pertains to a switch. The switch comprises a plurality of port cards. The switch comprises a network connected to the port cards. Preferably, the network is a gigabit network. The gigabit network has transmitters and receivers that communicate with each other and have assignments between each other. Preferably, the transmitters and receivers are gigabit transmitters and gigabit receivers. The switch comprises a plurality of fabrics. Each fabric is connected to each port card through the gigabit network to send and receive fragments of packets to or from the port cards, the port cards, fabrics and network having a plurality of modes of operation. The switch comprises a control mechanism connected to the gigabit transmitters and gigabit receivers which changes the assignments according to the mode. The control mechanism changes the mode and reuses the gigabit transmitters and gigabit receivers where they can be reused.
The present invention pertains to a method for switching fragments of packets. The method comprises the steps of assigning assignments between transmitters and receivers of a network. Preferably, the network is a gigabit network. Preferably, the transmitters and receivers are gigabit transmitters and gigabit receivers. Next there is the step of changing a mode of the fabrics, port cards and networks. Then there is the step of changing the assignments of the transmitters and receivers according to the mode and reusing the gigabit transmitters and gigabit receivers where they can be reused. Then there is the step of transferring the fragments of packets between fabrics and port cards with the gigabit transmitters and gigabit receivers of the gigabit network.
In the accompanying drawings, the preferred embodiment of the invention and preferred methods of practicing the invention are illustrated in which:
Referring now to the drawings wherein like reference numerals refer to similar or identical parts throughout the several views, and more specifically to
Preferably, the network 14 includes a mux structure 24 that makes the assignments between transmitters 16 and receivers 18. The modes preferably are 40 G, 80 G, 120 G, 240 G slow, 240 G fast or 480 G. Preferably, the network 14 can support two modes simultaneously as combined modes. The combined modes preferably are 40 G/80 G, 80 G/120 G, 120 G/160 G, 160 G/240 G fast, 240 G fast/240 G slow, or 240 G slow/480 G.
Preferably, each port card 12 includes a striper 26 and an unstriper 28. Each fabric 20 preferably includes a separator 30 and an aggregator 32. Preferably, the assignments between transmitters 16 and receivers 18 communicate with each other at up to 1.3 GHz. Each transmitter 16 preferably takes in 8 bits of data and 2 bits of control and serially transmits the bits of data and control to the associated receiver. Preferably, each receiver recovers clock and data it receives by using an 8B/10B decoding protocol and provides 8 bits of data and 3 bits of control.
The present invention pertains to a method for switching fragments of packets. The method comprises the steps of assigning assignments between transmitters 16 and receivers 18 of a network 14. Preferably, the network is a gigabit network. Preferably, the transmitters and receivers are gigabit transmitters and gigabit receivers. Next there is the step of changing a mode of the fabrics 20, port cards 12 and networks 14. Then there is the step of changing the assignments of the transmitters 16 and receivers 18 according to the mode and reusing the gigabit transmitters 16 and gigabit receivers 18 where they can be reused. Then there is the step of transferring the fragments of packets between fabrics 20 and port cards 12 with the gigabit transmitters 16 and gigabit receivers 18 of the gigabit network 14.
Preferably, the changing of the assignments step includes the step of rearranging the mux structure 24 of the network 14 that makes the assignments between the receivers 18 and transmitters 16. The changing the mode step preferably includes the step of changing the mode between 40 G and 80 G, or 80 G and 120 G, or 120 G and 160 G or 160 G and 240 G slow or 240 G slow and 240 G fast. Preferably, the assigning step includes the step of assigning assignments between the receivers 18 and transmitters 16 to support two modes simultaneously as combined modes. The transferring step preferably includes the step of transferring with the transmitter 8 bits of data and 2 bits of control serially through a mux structure 24 to the receiver assigned to the transmitter.
In the operation of the invention, the switch uses a network 14 of gigabit transceivers that make the connections from port cards 12 to fabrics 20 across the backplane. The gigabit network 14 is comprised of gigabit transmitters 16 and receivers 18 that communicate with each other at up to 1.3 GHz by using differential pairs. Each gigabit transmitter 16 takes in 8 bits of data and 2 bits of control and serially transmits this data to a gigabit receiver that recovers clock and data and by using an 8B/10B decoding protocol, provides 8 bits of data and 3 bits of gigabit receiver that recovers clock and data and by using an 8B/10B decoding protocol, provides 8 bits of data and 3 bits of control. Between the transmitters 16 and receivers 18 exists a mux structure 24 that makes the assignment of transmitters 16 to receivers 18. The mux structure 24 can be configured by software control to re-assign transceivers based on the mode of the switch 10. The mux structure 24 utilizes built-in 2-to-1 muxes in each transceiver. The mux structure 24 could not be built entirely with 2-to-1 muxes since in some cases 3-to-1 muxes were required. Therefore, some additional external 2-to-1 muxes are required. The seven possible configurations are as follows 40 G, 80 G, 120 G, 160 G, 240 G slow, 240 G fast, 480 G. Since updates to the gigabit network 14 cannot be synchronized across the whole switch 10, it was decided to combine the switch 10 configurations in pairs so that at any particular time, the gigabit network 14 would support two configurations simultaneously. This can be done because pairs of configuration modes have transceivers that are common to both and can be shared. However, the switch 10 configuration is restricted to move up or down in capacity by one mode at a time. The combined modes that are supported as follows: 40 G/80 G, 80 G/120 G, 120 G/160 G, 160 G/240 G fast, 240 G fast/240 G slow, 240 G slow/480 G. 240 G fast and slow modes are described later.
The minimum requirement on the number of gigabit transceivers can be obtained by looking at the minimum number of independent channels that need to be supported by each ASIC. For the Striper 26 and Unstriper 28, 13 independent sources and destinations exist respectively, that need their own clock source in 480 G mode. The Striper 26 needs to source 2 routeward bits, 2 data bits and a back-pressure bit for a total of 5 bits per transmitter used. The Separator 30 needs to source 4 routeword bits and 4 data bits for a combined total of 8 bits per transmitter. Each transceiver can handle 8 bits of data so one transceiver per channel in 480 G mode is sufficient. This limits the reduction of gigabit transceivers to at least 13 per striper and unstriper since each gigabit transceiver provides only one clock source. A similar requirement holds true for the Aggregator 32 and Separator 30. The Aggregator 32 and Separator 30 require 24 independent channels in 480 G mode and therefore require a minimum of 24 gigabit transceivers each. After some analysis, it was shown that the original speedup of 2 on the egress of the switch was compromised in some modes. The speedup for 240 G mode was reduced to 1 and was not acceptable. To have a speedup of 2 in 240 G mode, one additional transceiver was required for the Unstriper 28. To make things symmetrical, an additional transmitter 16 was added to the Striper 26. 240 G mode was split into two modes. 240 G fast mode has a speedup of 2 and 240 G slow mode has a speedup of 1. 240 G slow mode needs to also be used since no common mapping of transceivers could be found from 240 G fast mode to 480 G mode. This is true since both modes use all 14 transceivers but have completely different mappings. This can be seen in the Appendix "BFS Backplane Optimization Worksheet". This shows how the gigabit transceiver assignments were derived. The original map was done for the Unstriper 28 and from this, it can be seen that in 240 G fast mode, all 14 transceivers were required. All other modes were assigned based on the 240 G fast mode and unused transceivers were re-used in modes that required them. The Striper 26 map is a subset of the Unstriper 28 map and both Aggregator 32 maps and the Separator 30 5-8 map are derived from the Separator 30 1-4 map. In the Appendix, the "BFS ASIC Backplane Connection Map" shows the final gigabit transceiver assignments. This is a summary of the mappings derived earlier. The document in the Appendix "Gigabit Signals", shows how the number of data bits per bus for each mode affect the number of gigabit transceivers used.
After this optimization, the total gigabit transceiver requirement is as follows: 14 transmitters per Striper, 24 receivers 18 per Aggregator, 24 transmitters per Separator and 14 receivers per Unstriper 28. For a 480 G switch, this would total to about (48 port cards)(4 Stripers)(14)+(13 fabrics)(9 Aggregators)(24)+(13 fabrics)(9 Separators)(24)+(48 port cards)(4 Unstripers)(14)=2688+2808+2808+2688=10992. This is a 46% reduction in the number of transceivers required. At an average of 0.29 Watts of power dissipation per transceiver, the total power dissipation will be 3,187 Watts (10992)(0.29).
The switch uses RAID techniques to increase overall switch bandwidth while minimizing individual fabric bandwidth. In the switch architecture, all data is distributed evenly across all fabrics so the switch adds bandwidth by adding fabrics and the fabric need not increase its bandwidth capacity as the switch increases bandwidth capacity.
Each fabric provides 40 G of switching bandwidth and the system supports 1, 2, 3, 4, 6, or 12 fabrics, exclusive of the redundant/spare fabric. In other words, the switch can be a 40 G, 80 G, 120 G, 160 G, 240 G, or 480 G switch depending on how many fabrics are installed.
A portcard provides 10 G of port bandwidth. For every 4 portcards, there needs to be 1 fabric. The switch architecture does not support arbitrary installations of portcards and fabrics.
The fabric ASICs support both cells and packets. As a whole, the switch takes a "receiver make right" approach where the egress path on ATM blades must segment frames to cells and the egress path on frame blades must perform reassembly of cells into packets.
There are currently eight switch ASICs that are used in the switch:
There are 3 different views one can take of the connections between the fabric: physical, logical, and "active." Physically, the connections between the portcards and the fabrics are all gigabit speed differential pair serial links. This is strictly an implementation issue to reduce the number of signals going over the backplane. The "active" perspective looks at a single switch configuration, or it may be thought of as a snapshot of how data is being processed at a given moment. The interface between the fabric ASIC on the portcards and the fabrics is effectively 12 bits wide. Those 12 bits are evenly distributed ("striped") across 1, 2, 3, 4, 6, or 12 fabrics based on how the fabric ASICs are configured. The "active" perspective refers to the number of bits being processed by each fabric in the current configuration which is exactly 12 divided by the number of fabrics.
The logical perspective can be viewed as the union or max function of all the possible active configurations. Fabric slot #1 can, depending on configuration, be processing 12, 6, 4, 3, 2, or 1 bits of the data from a single Striper and is therefore drawn with a 12 bit bus. In contrast, fabric slot #3 can only be used to process 4, 3, 2, or 1 bits from a single Striper and is therefore drawn with a 4 bit bus.
Unlike previous switches, the switch really doesn't have a concept of a software controllable fabric redundancy mode. The fabric ASICs implement N+1 redundancy without any intervention as long as the spare fabric is installed.
As far as what does it provide; N+1 redundancy means that the hardware will automatically detect and correct a single failure without the loss of any data.
The way the redundancy works is fairly simple, but to make it even simpler to understand a specific case of a 120 G switch is used which has 3 fabrics (A, B, and C) plus a spare (S). The Striper takes the 12 bit bus and first generates a checkword which gets appended to the data unit (cell or frame). The data unit and checkword are then split into a 4-bit-per-clock-cycle data stripe for each of the A, B, and C fabrics (A3A2A1A0, B3B2B1B0, and C3C2C1C0). These stripes are then used to produce the stripe for the spare fabric S3S2S1S0 where Sn=An XOR Bn XOR Cn and these 4 stripes are sent to their corresponding fabrics. On the other side of the fabrics, the Unstriper receives 4 4-bit stripes from A, B, C, and S. All possible combinations of 3 fabrics (ABC, ABS, ASC, and SBC) are then used to reconstruct a "tentative" 12-bit data stream. A checkword is then calculated for each of the 4 tentative streams and the calculated checkword compared to the checkword at the end of the data unit. If no error occurred in transit, then all 4 streams will have checkword matches and the ABC stream will be forwarded to the Unstriper output. If a (single) error occurred, only one checkword match will exist and the stream with the match will be forwarded off chip and the Unstriper will identify the faulty fabric stripe.
For different switch configurations, i.e. 1, 2, 4, 6, or 12 fabrics, the algorithm is the same but the stripe width changes.
If 2 fabrics fail, all data running through the switch will almost certainly be corrupted.
The fabric slots are numbered and must be populated in ascending order. Also, the spare fabric is a specific slot so populating fabric slots 1, 2, 3, and 4 is different than populating fabric slots 1, 2, 3, and the spare. The former is a 160 G switch without redundancy and the latter is 120 G with redundancy.
Firstly, the ASICs are constructed and the backplane connected such that the use of a certain portcard slots requires there to be at least a certain minimum number of fabrics installed, not including the spare. This relationship is shown in Table 0.
In addition, the APS redundancy within the switch is limited to specifically paired portcards. Portcards 1 and 2 are paired, 3 and 4 are paired, and so on through portcards 47 and 48. This means that if APS redundancy is required, the paired slots must be populated together.
To give a simple example, take a configuration with 2 portcards and only 1 fabric. If the user does not want to use APS redundancy, then the 2 portcards can be installed in any two of portcard slots 1 through 4. If APS redundancy is desired, then the two portcards must be installed either in slots 1 and 2 or slots 3 and 4.
Fabric Requirements for Portcard Slot Usage
# of
To add capacity, add the new fabric(s), wait for the switch to recognize the change and reconfigure the system to stripe across the new number of fabrics. Install the new portcards.
Note that it is not technically necessary to have the full 4 portcards per fabric. The switch will work properly with 3 fabrics installed and a single portcard in slot 12. This isn't cost efficient but it will work.
To remove capacity, reverse the adding capacity procedure.
If the switch is oversubscribed, i.e. install 8 portcards and only one fabric.
It should only come about as the result of improperly upgrading the switch or a system failure of some sort. The reality is that one of two things will occur, depending on how this situation arises. If the switch is configured as a 40 G switch and the portcards are added before the fabric, then the 5th through 8th portcards will be dead. If the switch is configured as 80 G non-redundant switch and the second fabric fails or is removed then all data through the switch will be corrupted (assuming the spare fabric is not installed). And just to be complete, if 8 portcards were installed in an 80 G redundant switch and the second fabric failed or was removed, then the switch would continue to operate normally with the spare covering for the failed/removed fabric.
The chipset supports ATM and POS port cards in both OC48 and OC192c configurations. OC48 port cards interface to the switching fabrics with four separate OC48 flows. OC192 port cards logically combine the 4 channels into a 10 G stream. The ingress side of a port card does not perform traffic conversions for traffic changing between ATM cells and packets. Whichever form of traffic is received is sent to the switch fabrics. The switch fabrics will mix packets and cells and then dequeue a mix of packets and cells to the egress side of a port card.
The egress side of the port is responsible for converting the traffic to the appropriate format for the output port. This convention is referred to in the context of the switch as "receiver makes right". A cell blade is responsible for segmentation of packets and a cell blade is responsible for reassembly of cells into packets. To support fabric speed-up, the egress side of the port card supports a link bandwidth equal to twice the inbound side of the port card.
The block diagram for a Poseidon-based ATM port card is shown as in
At the inbound side, OC-48c or 4 OC-12c interfaces are aggregated. Each vortex sends a 2.5 G cell stream into a dedicated striper ASIC (using the BIB bus, as described below). The striper converts the supplied routeword into two pieces. A portion of the routeword is passed to the fabric to determine the output port(s) for the cell. The entire routeword is also passed on the data portion of the bus as a routeword for use by the outbound memory controller. The first routeword is termed the "fabric routeword". The routeword for the outbound memory controller is the "egress routeword".
At the outbound side, the unstriper ASIC in each channel takes traffic from each of the port cards, error checks and correct the data and then sends correct packets out on its output bus. The unstriper uses the data from the spare fabric and the checksum inserted by the striper to detect and correct data corruption.
The OC192 port card supports a single 10 G stream to the fabric and between a 10 G and 20 G egress stream. This board also uses 4 stripers and 4 unstriper, but the 4 chips operate in parallel on a wider data bus. The data sent to each fabric is identical for both OC48 and OC192 ports so data can flow between the port types without needing special conversion functions.
Each 40 G switch fabric enqueues up to 40 Gbps cells/frames and dequeue them at 80 Gbps. This 2� speed-up reduces the amount of traffic buffered at the fabric and lets the outbound ASIC digest bursts of traffic well above line rate. A switch fabric consists of three kinds of ASICs: aggregators, memory controllers, and separators. Nine aggregator ASICs receive 40 Gbps of traffic from up to 48 network blades and the control port. The aggregator ASICs combine the fabric route word and payload into a single data stream and TDM between its sources and places the resulting data on a wide output bus. An additional control bus (destid) is used to control how the memory controllers enqueue the data. The data stream from each aggregator ASIC then bit sliced into 12 memory controllers.
The memory controller receives up to 16 cells/frames every clock cycle. Each of 12 ASICs stores 1/12 of the aggregated data streams. It then stores the incoming data based on control information received on the destid bus. Storage of data is simplified in the memory controller to be relatively unaware of packet boundaries (cache line concept). All 12 ASICs dequeue the stored cells simultaneously at aggregated speed of 80 Gbps.
Nine separator ASICs perform the reverse function of the aggregator ASICs. Each separator receives data from all 12 memory controllers and decodes the routewords embedded in the data streams by the aggregator to find packet boundaries. Each separator ASIC then sends the data to up to 24 different unstripers depending on the exact destination indicated by the memory controller as data was being passed to the separator.
The dequeue process is back-pressure driven. If back-pressure is applied to the unstriper, that back-pressure is communicated back to the separator. The separator and memory controllers also have a back-pressure mechanism which controls when a memory controller can dequeue traffic to an output port.
In order to support OC48 and OC192 efficiently in the chipset, the 4 OC48 ports from one port card are always routed to the same aggregator and from the same separator (the port connections for the aggregator & Sep are always symmetric.). The table below shows the port connections for the aggregator & sep on each fabric for the switch configurations. Since each aggregator is accepting traffic from 10 G of ports, the addition of 40 G of switch capacity only adds ports to 4 aggregators. This leads to a differing port connection pattern for the first four aggregators from the second 4 (and also the corresponding separators).
Agg/Sep port connections
Switch Size
Agg 1
Agg 2
Agg 3
Agg 4
Agg 5
Agg 6
Agg 7
Agg 8
1, 2, 3, 4
5, 6, 7, 8
9, 10, 11, 12
13, 14, 15, 16
1, 2, 3, 4
5, 6, 7, 8
9, 10, 11, 12
13, 14, 15, 16
17, 18, 19, 20
21, 22, 23, 24
25, 26, 27, 28
29, 30, 31, 32
1, 2, 3, 4
5, 6, 7, 8
9, 10, 11, 12,
13, 14, 15, 16,
17, 18, 19, 20
21, 22, 23, 24
25, 26, 27, 28
29, 30, 31, 32
33, 34, 35, 36
37, 38, 39, 40
41, 42, 43, 44
45, 46, 47, 48
1, 2, 3, 4
5, 6, 7, 8
9, 10, 11, 12,
13, 14, 15, 16,
17, 18, 19, 20,
21, 22, 23, 24,
25, 26, 27, 28,
29, 30, 31, 32,
33, 34, 35, 36
37, 38, 39, 40
41, 42, 43, 44
45, 46, 47, 48
49, 50, 51, 52
53, 54, 55, 56
57, 58, 59, 60
61, 62, 63, 64
The external interfaces of the switches are the Input Bus (BIB) between the striper ASIC and the ingress blade ASIC such as Vortex and the Output Bus (BOB) between the unstriper ASIC and the egress blade ASIC such as Trident.
The unstriper ASIC sends data to the egress port via Output Bus (BOB) (also known as DOUT_UN_bl_ch bus), which is a 64 (or 256) bit data bus that can support either cell or packet. It consists of the following signals:
This bus can either operate as 4 separate 32 bit output buses (4�OC48c) or a single 128 bit wide data bus with a common set of control lines from all Unstripers. This bus supports either cells or packets based on software configuration of the unstriper chip.
The Synchronizer has two main purposes. The first purpose is to maintain logical cell/packet or datagram ordering across all fabrics. On the fabric ingress interface, datagrams arriving at more than one fabric from one port cards's channels need to be processed in the same order across all fabrics. The Synchronizer's second purpose is to have a port cards's egress channel re-assemble all segments or stripes of a datagram that belong together even though the datagram segments are being sent from more than one fabric and can arrive at the blade's egress inputs at different times. This mechanism needs to be maintained in a system that will have different net delays and varying amounts of clock drift between blades and fabrics.
The switch uses a system of a synchronized windows where start information is transmit around the system. Each transmitter and receiver can look at relative clock counts from the last resynch indication to synchronize data from multiple sources. The receiver will delay the receipt of data which is the first clock cycle of data in a synch period until a programmable delay after it receives the global synch indication. At this point, all data is considered to have been received simultaneously and fixed ordering is applied. Even though the delays for packet 0 and cell 0 caused them to be seen at the receivers in different orders due to delays through the box, the resulting ordering of both streams at receive time=1 is the same, Packet 0, Cell 0 based on the physical bus from which they were received.
Multiple cells or packets can be sent in one counter tick. All destinations will order all cells from the first interface before moving onto the second interface and so on. This cell synchronization technique is used on all cell interfaces. Differing resolutions are required on some interfaces.
The Synchronizer consists of two main blocks, mainly, the transmitter and receiver. The transmitter block will reside in the Striper and Separator ASICs and the receiver block will reside in the Aggregator and Unstriper ASICs. The receiver in the Aggregator will handle up to 24(6 port cards�4 channels) input lanes. The receiver in the Unstriper will handle up to 13(12 fabrics+1 parity fabric) input lanes.
When a sync pulse is received, the transmitter first calculates the number of clock cycles it is fast (denoted as N clocks).
The transmit synchronizer will interrupt the output stream and transmit N K characters indicating it is locking down. At the end of the lockdown sequence, the transmitter transmits a K character indicating that valid data will start on the next clock cycle. This next cycle valid indication is used by the receivers to synchronize traffic from all sources.
At the next end of transfer, the transmitter will then insert at least one idle on the interface. These idles allow the 10 bit decoders to correctly resynchronize to the 10 bit serial code window if they fall out of synch.
The receive synchronizer receives the global synch pulse and delays the synch pulse by a programmed number (which is programmed based on the maximum amount of transport delay a physical box can have). After delaying the synch pulse, the receiver will then consider the clock cycle immediately after the synch character to be eligible to be received. Data is then received every clock cycle until the next synch character is seen on the input stream. This data is not considered to be eligible for receipt until the delayed global synch pulse is seen.
Since transmitters and receivers will be on different physical boards and clocked by different oscillators, clock speed differences will exist between them. To bound the number of clock cycles between different transmitters and receivers, a global sync pulse is used at the system level to resynchronize all sequence counters. Each chip is programmed to ensure that under all valid clock skews, each transmitter and receiver will think that it is fast by at least one clock cycle. Each chip then waits for the appropriate number of clock cycles they are into their current sync_pulse_window. This ensure that all sources run N* sync_pulse_window valid clock cycles between synch pulses.
As an example, the synch pulse window could be programmed to 100 clocks, and the synch pulses sent out at a nominal rate of a synch pulse every 10,000 clocks. Based on a worst case drifts for both the synch pulse transmitter clocks and the synch pulse receiver clocks, there may actually be 9,995 to 10,005 clocks at the receiver for 10,000 clocks on the synch pulse transmitter. In this case, the synch pulse transmitter would be programmed to send out synch pulses every 10,006 clock cycles. The 10,006 clocks guarantees that all receivers must be in their next window. A receiver with a fast clock may have actually seen 10,012 clocks if the synch pulse transmitter has a slow clock. Since the synch pulse was received 12 clock cycles into the synch pulse window, the chip would delay for 12 clock cycles. Another receiver could seen 10,006 clocks and lock down for 6 clock cycles at the end of the synch pulse window. In both cases, each source ran 10,100 clock cycles.
When a port card or fabric is not present or has just been inserted and either of them is supposed to be driving the inputs of a receive synchronizer, the writing of data to the particular input FIFO will be inhibited since the input clock will not be present or unstable and the status of the data lines will be unknown. When the port card or fabric is inserted, software must come in and enable the input to the byte lane to allow data from that source to be enabled. Writes to the input FIFO will be enabled. It is assumed that, the enable signal will be asserted after the data, routeword and clock from the port card or fabric are stable.
At a system level, there will be a primary and secondary sync pulse transmitter residing on two separate fabrics. There will also be a sync pulse receiver on each fabric and blade. This can be seen in
If the sync pulse receiver determines that the primary sync pulse transmitter is out of sync, it will switch over to the secondary sync pulse transmitter source. The secondary sync pulse transmitter will also determine that the primary sync pulse transmitter is out of sync and will start generating its own sync pulse independently of the primary sync pulse transmitter. This is the secondary sync pulse transmitter's primary mode of operation. If the sync pulse receiver determines that the primary sync pulse transmitter has become in sync once again, it will switch to the primary side. The secondary sync pulse transmitter will also determine that the primary sync pulse transmitter has become in sync once again and will switch back to a secondary mode. In the secondary mode, it will sync up its own sync pulse to the primary sync pulse. The sync pulse receiver will have less tolerance in its sync pulse filtering mechanism than the secondary sync pulse transmitter. The sync pulse receiver will switch over more quickly than the secondary sync pulse transmitter. This is done to ensure that all receiver synchronizers will have switched over to using the secondary sync pulse transmitter source before the secondary sync pulse transmitter switches over to a primary mode.
In order to lockdown the backplane transmission from a fabric by the number of clock cycles indicated in the sync calculation, the entire fabric must effectively freeze for that many clock cycles to ensure that the same enqueuing and dequeueing decisions stay in sync. This requires support in each of the fabric ASICs. Lockdown stops all functionality, including special functions like queue resynch.
The sync signal from the synch pulse receiver is distributed to all ASICs. Each fabric ASIC contains a counter in the core clock domain that counts clock cycles between global sync pulses. After the sync pulse if received, each ASIC calculates the number of clock cycles it is fast. (δ). Because the global sync is not transferred with its own clock, the calculated lockdown cycle value may not be the same for all ASICs on the same fabric. This difference is accounted for by keeping all interface FIFOs at a depth where they can tolerate the maximum skew of lockdown counts.
Lockdown cycles on all chips are always inserted at the same logical point relative to the beginning of the last sequence of "useful" (non-lockdown) cycles. That is, every chip will always execute the same number of "useful" cycles between lockdown events, even though the number of lockdown cycles varies.
Lockdown may occur at different times on different chips. All fabric input FIFOs are initially set up such that lockdown can occur on either side of the FIFO first without the FIFO running dry or overflowing. On each chip-chip interface, there is a sync FIFO to account for lockdown cycles (as well as board trace lengths and clock skews). The transmitter signals lockdown while it is locked down. The receiver does not push during indicated cycles, and does not pop during its own lockdown. The FIFO depth will vary depending on which chip locks down first, but the variation is bounded by the maximum number of lockdown cycles. The number of lockdown cycles a particular chip sees during one global sync period may vary, but they will all have the same number of useful cycles. The total number of lockdown cycles each chip on a particular fabric sees will be the same, within a bounded tolerance.
The Aggregator core clock domain completely stops for the lockdown duration—all flops and memory hold their state. Input FIFOs are allowed to build up. Lockdown bus cycles are inserted in the output queues. Exactly when the core lockdown is executed is dictated by when DOUT_AG bus protocol allows lockdown cycles to be inserted. DOUT_AG lockdown cycles are indicated on the DestID bus.
The memory controller must lockdown all flops for the appropriate number of cycles. To reduce impact to the silicon area in the memory controller, a technique called propagated lockdown is used.
The on-fabric chip-to-chip synchronization is executed at every sync pulse. While some sync error detecting capability may exist in some of the ASICs, it is the Unstriper's job to detect fabric synchronization errors and to remove the offending fabric. The chip-to-chip synchronization is a cascaded function that is done before any packet flow is enabled on the fabric. The synchronization flows from the Aggregator to the Memory Controller, to the Separator, and back to the Memory Controller. After the system reset, the Aggregators wait for the first global sync signal. When received, each Aggregator transmits a local sync command (value 0x2) on the DestID bus to each Memory Controller.
The striping function assigns bits from incoming data streams to individual fabrics. Two items were optimized in deriving the striping assignment:
These were traded off against additional muxing legs for the striper and unstriper ASICs. Irregardless of the optimization, the switch must have the same data format in the memory controller for both OC48 and OC192.
Backplane efficiency requires that minimal padding be added when forming the backplane busses. Given the 12 bit backplane bus for OC48 and the 48 bit backplane bus for OC192, an optimal assignment requires that the number of unused bits for a transfer to be equal to (number_of_bytes*8)/bus_width where "/" is integer division. For OC48, the bus can have 0, 4 or 8 unutilized bits. For OC192 the bus can have 0, 8, 16, 24, 32, or 40 unutilized bits.
This means that no bit can shift between 12 bit boundaries or else OC48 padding will not be optimal for certain packet lengths.
For OC192c, maximum bandwidth utilization means that each striper must receive the same number of bits (which implies bit interleaving into the stripers). When combined with the same backplane interconnection, this implies that in OC192c, each stripe must have exactly the correct number of bits come from each striper which has � of the bits.
For the purpose of assigning data bits to fabrics, a 48 bit frame is used. Inside the striper is a FIFO which is written 32 bits wide at 80–100 MHz and read 24 bits wide at 125 MHz. Three 32 bit words will yield four 24 bit words. Each pair of 24 bit words is treated as a 48 bit frame. The assignments between bits and fabrics depends on the number of fabrics.
Bit striping function
Fab 0
Fab 1
Fab 2
Fab 3
Fab 4
Fab 5
Fab 6
Fab 7
Fab 8
Fab 9
Fab 10
Fab 11
1 fab
2 fab
0, 2, 5,
1, 3, 4,
7, 8, 10
6, 9, 11
13, 15,
12, 14,
16, 18,
17, 19,
20, 22
+24 to
+24 to
+24 to
+24 to
3 fab
0, 3, 5, 10
2, 4, 7, 9
1, 6, 8, 11
15, 17,
14, 16,
13, 18,
22, 13
19, 21
20, 23
+24 to
+24 to
+24 to
+24 to
+24 to
+24 to
4 fab
0, 5, 10
3, 4, 9
2, 7, 8
1, 6, 11
15, 16,
14, 19,
13, 18,
12, 17,
26, 31,
25, 30,
24, 29,
27, 28,
37, 42,
36, 41,
39, 40,
38, 43,
6 fab
0, 11
1, 4
5, 8
2, 9
3, 6
7, 10
14, 21
15, 18
19, 22
12, 23
13, 16
17, 20
+24 to
+24 to
12 fab
The following tables give the byte lanes which are read first in the aggregator and written to first in the separator. The four channels are notated A,B,C,D. The different fabrics have different read/write order of the channels to allow for all busses to be fully utilized.
One Fabric—40 G
The next table gives the interface read order for the aggregator.
Two fabric-80 G
Three fabric-160 G
Siz fabric-240 G
Twelve Fabric-480 G
0, 1, 2
3, 4, 5
6, 7, 8
9, 10, 11
Interfaces to the gigabit transceivers will utilize the transceiver bus as a split bus with two separate routeword and data busses. The routeword bus will be a fixed size (2 bits for OC48 ingress, 4 bits for OC48 egress, 8 bits for OC192 ingress and 16 bits for OC192 egress), the data bus is a variable sized bus. The transmit order will always have routeword bits at fixed locations. Every striping configuration has one transceiver that it used to talk to a destination in all valid configurations. That transceiver will be used to send both routeword busses and to start sending the data.
The backplane interface is physically implemented using interfaces to the backplane transceivers. The bus for both ingress and egress is viewed as being composed of two halves, each with routeword data. The two bus halves may have information on separate packets if the first bus half ends a packet.
For example, an OC48 interface going to the fabrics locally speaking has 24 data bits and 2 routeword bits. This bus will be utilized acting as if it has 2�(12 bit data bus+1 bit routeword bus). The two bus halves are referred to as A and B. Bus A is the first data, followed by bus B. A packet can start on either bus A or B and end on either bus A or B.
In mapping data bits and routeword bits to transceiver bits, the bus bits are interleaved. This ensures that all transceivers should have the same valid/invalid status, even if the striping amount changes. Routewords should be interpreted with bus A appearing before bus B.
The bus A/Bus B concept closely corresponds to having interfaces between chips.
All backplane busses support fragmentation of data. The protocol used marks the last transfer (via the final segment bit in the routeword). All transfers which are not final segment need to utilize the entire bus width, even if that is not an even number of bytes. Any given packet must be striped to the same number of fabrics for all transfers of that packet. If the striping amount is updated in the striper during transmission of a packet, it will only update the striping at the beginning of the next packet.
Each transmitter on the ASICs will have the following I/O for each channel:
8 bit data bus, 1 bit clock, 1 bit control.
On the receive side, for channel the ASIC receives
a receive clock, 8 bit data bus, 3 bit status bus.
The switch optimizes the transceivers by mapping a transmitter to between 1 and 3 backplane pairs and each receiver with between 1 and 3 backplane pairs. This allows only enough transmitters to support traffic needed in a configuration to be populated on the board while maintaining a complete set of backplane nets. The motivation for this optimization was to reduce the number of transceivers needed.
The optimization was done while still requiring that at any time, two different striping amounts must be supported in the gigabit transceivers. This allows traffic to be enqueued from a striping data to one fabric and a striper striping data to two fabrics at the same time.
Depending on the bus configuration, multiple channels may need to be concatenated together to form one larger bandwidth pipe (any time there is more than one transceiver in a logical connection. Although quad gbit transceivers can tie 4 channels together, this functionality is not used. Instead the receiving ASIC is responsible for synchronizing between the channels from one source. This is done in the same context as the generic synchronization algorithm.
The 8b/10b encoding/decoding in the gigabit transceivers allow a number of control events to be sent over the channel. The notation for these control events are K characters and they are numbered based on the encoded 10 bit value. Several of these K characters are used in the chipset. The K characters used and their functions are given in the table below.
K Character usage
Sync indication
Transmitted after lockdown cycles, treated as
the prime synchronization event at the
Transmitted during lockdown cycles on the
Packet Abort
Transmitted to indicate the card is unable to
finish the current packet. Current use is
limited to a port card being pulled while
transmitting traffic
Transmitted by the striper at the start of a
synch window if a resynch will be contained
in the current sync window
BP set
Transmitted by the striper if the bus is
currently idle and the value of the bp bit
must be set.
Indicates idle condition
BP clr
Transmitted by the striper if the bus is
currently idle and the bp bit must be cleared.
The switch has a variable number of data bits supported to each backplane channel depending on the striping configuration for a packet. Within a set of transceivers, data is filled in the following order:
F[fabric]_[oc192 port number][oc48 port designation (a,b,c,d)][transceiver_number]
The chipset implements certain functions which are described here. Most of the functions mentioned here have support in multiple ASICs, so documenting them on an ASIC by ASIC basis does not give a clear understanding of the full scope of the functions required.
The switch chipset is architected to work with packets up to 64 K+6 bytes long. On the ingress side of the switch, there are busses which are shared between multiple ports. For most packets, they are transmitted without any break from the start of packet to end of packet. However, this approach can lead to large delay variations for delay sensitive traffic. To allow delay sensitive traffic and long traffic to coexist on the same switch fabric, the concept of long packets is introduced. Basically long packets allow chunks of data to be sent to the queueing location, built up at the queueing location on a source basis and then added into the queue all at once when the end of the long packet is transferred. The definition of a long packet is based on the number of bits on each fabric.
If the switch is running in an environment where Ethernet MTU is maintained throughout the network, long packets will not be seen in a switch greater than 40 G in size.
A wide cache-line shared memory technique is used to store cells/packets in the port/priority queues. The shared memory stores cells/packets continuously so that there is virtually no fragmentation and bandwidth waste in the shared memory.
There exists up to 200 multiple queues in the shared memory. They are per-destination and priority based. All cells/packets which have the same output priority and blade/channel ID are stored in the same queue. Cells are always dequeued from the head of the list and enqueued into the tail of the queue. Each cell/packet consists of a portion of the egress route word, a packet length, and variable-length packet data. Cell and packets are stored continuously, i.e., the memory controller itself does not recognize the boundaries of cells/packets for the unicast connections. The packet length is stored for MC packets.
The multicast port mask memory 64 K�16-bit is used to store the destination port mask for the multicast connections, one entry (or multiple entries) per multicast VC. The port masks of the head multicast connections indicated by the multicast DestID FIFOs are stored internally for the scheduling reference. The port mask memory is retrieved when the port mask of head connection is cleaned and a new head connection is provided.
APS stands for a Automatic Protection Switching, which is a SONET redundancy standard. To support APS feature in the switch, two output ports on two different port cards send roughly the same traffic. The memory controllers maintain one set of queues for an APS port and send duplicate data to both output ports.
To support data duplication in the memory controller ASIC, each one of multiple unicast queues has a programmable APS bit. If the APS bit is set to one, a packet is dequeued to both output ports. If the APS bit is set to zero for a port, the unicast queue operates at the normal mode. If a port is configured as an APS slave, then it will read from the queues of the APS master port. For OC48 ports, the APS port is always on the same OC48 port on the adjacent port card.
The shared memory queues in the memory controllers among the fabrics might be out of sync (i.e., same queues among different memory controller ASICs have different depths) due to clock drifts or a newly inserted fabric. It is important to bring the fabric queues to the valid and sync states from any arbitrary states. It is also desirable not to drop cells for any recovery mechanism.
A resync cell is broadcast to all fabrics (new and existing) to enter the resync state. Fabrics will attempt to drain all of the traffic received before the resynch cell before queue resynch ends, but no traffic received after the resynch cell is drained until queue resynch ends. A queue resynch ends when one of two events happens:
1. A timer expires.
2. The amount of new traffic (traffic received after the resynch cell) exceeds a threshold.
At the end of queue resynch, all memory controllers will flush any left-over old traffic (traffic received before the queue resynch cell). The freeing operation is fast enough to guarantee that all memory controllers can fill all of memory no matter when the resynch state was entered.
Queue resynch impacts all 3 fabric ASICs. The aggregators must ensure that the FIFOs drain identically after a queue resynch cell. The memory controllers implement the queueing and dropping. The separators need to handle memory controllers dropping traffic and resetting the length parsing state machines when this happens. For details on support of queue resynch in individual ASICs, refer to the chip ADSs.
For the dequeue side, multicast connections have independent 32 tokens per port, each worth up 50-bit data or a complete packet. The head connection and its port mask of a higher priority queue is read out from the connection FIFO and the port mask memory every cycle. A complete packet is isolated from the multicast cache line based on the length field of the head connection. The head packet is sent to all its destination ports. The 8 queue drainers transmit the packet to the separators when there are non-zero multicast tokens are available for the ports. Next head connection will be processed only when the current head packet is sent out to all its ports.
Queue structure can be changed on fly through the fabric resync cell where the number of priority per port field is used to indicate how many priority queues each port has.
The following words have reasonably specific meanings in the vocabulary of the switch. Many are mentioned elsewhere, but this is an attempt to bring them together in one place with definitions.
Automatic Protection Switching. A sonet/sdh standard
for implementing redundancy on physical links.
For the switch, APS is used to also recover from any
detected port card failures.
A generic term referring either to the general process the
the switch boards use to account for varying transport
delays between boards and clock drift or to the logic
which implements the TX/RX functionality required for
the the switch ASICs to account for varying transport
delays and clock drifts.
The switch input bus. The bus which is used to pass data to
the striper(s). See also BOB
Another term used for a port card. References to blades
should have been eliminated from this document, but
some may persist.
The switch output bus. The output bus from the striper
which connects to the egress memory controller. See
also BIB.
This is the routeword which is supplied to the chip after the
unstriper. From an internal chipset perspective,
the egress routeword is treated as data.
See also fabric routeword.
Routeword used by the fabric to determine the output
queue. This routeword is not passed outside the unstriper.
A significant portion of this routeword is blown away in
the fabrics.
Having logic maintain its values during lock-down cycles.
Period of time where the fabric effectively stops performing
any work to compensate for clock drift. If the backplane
synchronization logic determines that a fabric is 8 clock
cycles fast, the fabric will lock down for 8 clocks.
A queue resynch is a series of steps executed to ensure
that the logical state of all fabric queues for all ports is
identical at one logical point in time. Queue resynch is
not tied to backplane resynch (including lock-down)
in any fashion, except that a lock-down can occur
during a queue resynch.
Striped input bus. A largely obsolete term used to describe
the output bus from the striper and input bus to the
One of two meanings. The first is striped output bus, which
is the output bus of the fabric and the input bus
of the agg. See also SIB. The second meaning is a generic
term used to describe engineers who left Marconi
to form/work for a start-up after starting the switch design.
Depends heavily on context. Related terms are queue
resynch, lock-down, freeze, and backplane sync.
The implicit bit steering which occurs in the OC192 ingress
stage since data is bit interleaved among stripers.
This bit steering is reversed by the aggregators.
Although the invention has been described in detail in the foregoing embodiments for the purpose of illustration, it is to be understood that such detail is solely for that purpose and that variations can be made therein by those skilled in the art without departing from the spirit and scope of the invention except as it may be described by the following claims.
|Cited Patent
|Filing date
|Publication date
|Jan 3, 1991
|Jun 23, 1992
|Bell Communications Research, Inc.
|Grouping network based non-buffer statistical multiplexor
|Feb 6, 1992
|May 10, 1994
|International Business Machines Corporation
|Configurable gigabits switch adapter
|Jul 8, 1991
|Aug 8, 1995
|Seiko Epson Corporation
|Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
|Jan 16, 1996
|Nov 18, 1997
|Lucent Technologies Inc.
|Buffering of multicast cells in switching networks
|Sep 8, 1995
|Jun 9, 1998
|Cisco Systems, Inc.
|Early and integrated tail packet discard system
|Jan 20, 1995
|Oct 6, 1998
|Newbridge Networks Corporation
|Transparent interconnector of LANs by an ATM network
|Oct 15, 1997
|Jul 27, 1999
|Teledesic Llc
|Non-blocking dynamic fast packet switch for satellite communication system
|Oct 23, 1996
|Feb 22, 2000
|Com21, Inc.
|Prioritized virtual connection transmissions in a packet to ATM cell cable network
|Apr 29, 1999
|Nov 11, 2003
|Pmc-Sierra, Inc.
|Packet-switch system
|Dec 2, 1999
|Jan 27, 2004
|Worldcom, Inc.
|Method and system for implementing an improved DSO switching capability in a data switch
|Citing Patent
|Filing date
|Publication date
|Jul 26, 2002
|Oct 23, 2007
|Extreme Networks
|Method and apparatus for providing quality of service across a switched backplane for multicast packets
|Jul 2, 2002
|Aug 5, 2008
|Extreme Networks
|Method and apparatus for providing quality of service across a switched backplane between egress queue managers
|Nov 16, 2001
|Sep 29, 2009
|Foundry Networks, Inc.
|Backplane interface adapter with error control and redundant fabric
|Aug 5, 2002
|Oct 6, 2009
|Extreme Networks
|Method and apparatus for providing quality of service across a switched backplane between egress and ingress queue managers
|May 6, 2002
|Jan 19, 2010
|Foundry Networks, Inc.
|Network routing system for enhanced efficiency and monitoring capability
|Apr 28, 2005
|Feb 2, 2010
|Foundry Networks, Inc.
|Double density content addressable memory (CAM) lookup scheme
|Jul 25, 2007
|Jun 15, 2010
|Foundry Networks, Inc.
|System architecture for very fast ethernet blade
|Jan 8, 2007
|Oct 12, 2010
|Foundry Networks, Inc.
|Pipeline method and system for switching packets
|Mar 26, 2004
|Oct 19, 2010
|Foundry Networks, Llc
|Method and apparatus for aggregating input data streams
|Sep 12, 2007
|Nov 9, 2010
|Foundry Networks, Llc
|Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability
|Dec 22, 2006
|Mar 8, 2011
|Foundry Networks, Llc
|System and method for ECMP load sharing
|Mar 9, 2009
|May 24, 2011
|Foundry Networks, Llc
|Backplane interface adapter with error control and redundant fabric
|Dec 16, 2009
|May 31, 2011
|Foundry Networks, Llc
|Double density content addressable memory (CAM) lookup scheme
|Dec 16, 2009
|May 31, 2011
|Foundry Networks, Llc
|Double density content addressable memory (CAM) lookup scheme
|Dec 10, 2007
|Jul 12, 2011
|Foundry Network, LLC
|Techniques for detecting non-receipt of fault detection protocol packets
|Feb 17, 2009
|Jul 12, 2011
|Foundry Networks, Llc
|Backplane interface adapter
|Mar 9, 2009
|Aug 9, 2011
|Foundry Networks, Inc.
|Backplane interface adapter with error control and redundant fabric
|Jul 18, 2007
|Oct 11, 2011
|Foundry Networks, Llc
|Techniques for segmented CRC design in high speed networks
|May 14, 2009
|Jan 3, 2012
|Brocade Communications Systems, Inc.
|TCAM management approach that minimize movements
|Aug 26, 2008
|Apr 3, 2012
|Foundry Networks, Llc
|Selection of trunk ports and paths using rotation
|Dec 10, 2007
|Apr 10, 2012
|Foundry Networks, Llc
|Techniques for using dual memory structures for processing failure detection protocol packets
|Jun 7, 2010
|May 1, 2012
|Foundry Networks, Llc
|Pipeline method and system for switching packets
|Jan 29, 2007
|Jun 5, 2012
|Foundry Networks, Llc
|Flexible method for processing data packets in a network routing system for enhanced efficiency and monitoring capability
|Dec 24, 2008
|Jul 17, 2012
|Infinera Corporation
|Programmable time division multiplexed switching
|Jul 31, 2007
|Aug 7, 2012
|Foundry Networks, Llc
|Recovering from failures without impact on data traffic in a shared bus architecture
|Jul 18, 2007
|Sep 18, 2012
|Foundry Networks Llc
|Segmented CRC design in high speed networks
|Sep 30, 2007
|Sep 25, 2012
|Extreme Networks, Inc.
|Method and apparatus for providing quality of service across a switched backplane for multicast packets
|Dec 10, 2007
|Mar 12, 2013
|Foundry Networks, Llc
|Techniques for processing incoming failure detection protocol packets
|Dec 27, 2006
|May 21, 2013
|Foundry Networks, Llc
|Hitless software upgrades
|Sep 13, 2010
|Jul 23, 2013
|Foundry Networks, Llc
|Method and apparatus for aggregating input data streams
|Aug 26, 2008
|Aug 13, 2013
|Foundry Networks, Llc
|Techniques for selecting paths and/or trunk ports for forwarding traffic flows
|Jun 4, 2012
|Aug 20, 2013
|Foundry Networks, Llc
|Backplane interface adapter with error control and redundant fabric
|Jan 7, 2010
|Dec 3, 2013
|Brocade Communications Systems, Inc.
|Provisioning single or multistage networks using ethernet service instances (ESIs)
|Apr 8, 2011
|Dec 31, 2013
|Foundry Networks, Llc
|Backplane interface adapter with error control and redundant fabric
|May 7, 2007
|Mar 11, 2014
|Foundry Networks, Llc
|Method and apparatus for efficiently processing data packets in a computer network
|Oct 29, 2009
|May 6, 2014
|Foundry Networks, Llc
|System and method for high speed packet transmission
|Apr 26, 2004
|May 20, 2014
|Foundry Networks, Llc
|System and method for optimizing router lookup
|Oct 29, 2009
|Aug 19, 2014
|Foundry Networks, Llc
|System and method for high speed packet transmission
|Nov 8, 2013
|Feb 24, 2015
|Foundry Networks, Llc
|Backplane interface adapter with error control and redundant fabric
|Feb 16, 2012
|Mar 24, 2015
|Foundry Networks, Llc
|Pipeline method and system for switching packets
|Jul 11, 2013
|May 12, 2015
|Foundry Networks, Llc
|Backplane interface adapter with error control and redundant fabric
|Jul 12, 2012
|May 12, 2015
|Foundry Networks, Llc
|Recovering from failures without impact on data traffic in a shared bus architecture
|Feb 13, 2013
|Aug 18, 2015
|Foundry Networks, Llc
|Techniques for processing incoming failure detection protocol packets
|Nov 18, 2013
|Oct 20, 2015
|Brocade Communications Systems, Inc.
|Provisioning single or multistage networks using ethernet service instances (ESIs)
|Jun 24, 2013
|May 10, 2016
|Foundry Networks, Llc
|Method and apparatus for aggregating input data streams
|Apr 12, 2013
|Jun 28, 2016
|Foundry Networks, Llc
|Hitless software upgrades
|Jul 9, 2014
|Oct 4, 2016
|Foundry Networks, Llc
|System and method for high speed packet transmission
|Jul 13, 2004
|Jan 19, 2006
|International Business Machines Corporation
|System, apparatus and method of improving network data traffic between interconnected high-speed switches
|May 21, 2007
|Nov 1, 2007
|Andrew Chang
|Backplane interface adapter
|Dec 24, 2008
|Oct 1, 2009
|Infinera Corporation
|Programmable time division multiplexed switching
|U.S. Classification
|370/389, 370/476, 370/907, 370/360, 398/43
|International Classification
|Cooperative Classification
|European Classification
|Nov 27, 2000
Owner name: FORE SYSTEMS, INC., PENNSYLVANIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SPEISER, BEN;BIANCHINI, RONALD P., JR.;SCHULZ, JEFF;REEL/FRAME:011352/0901;SIGNING DATES FROM 20000918 TO 20001111
|Jul 11, 2001
Owner name: MARCONI COMMUNICATIONS, INC., PENNSYLVANIA
Free format text: CHANGE OF NAME;ASSIGNOR:FORE SYSTEMS, INC.;REEL/FRAME:011969/0390
Effective date: 20010328
|Nov 5, 2003
Owner name: MARCONI INTELLECTUAL PROPERTY ( RINGFENCE) INC., P
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARCONI COMMUNICATIONS, INC.;REEL/FRAME:014675/0855
Effective date: 20031028
|Jun 14, 2006
Owner name: ERICSSON AB, SWEDEN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARCONI INTELLECTUAL PROPERTY (RINGFENCE) INC.;REEL/FRAME:018047/0028
Effective date: 20060101
Owner name: ERICSSON AB,SWEDEN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARCONI INTELLECTUAL PROPERTY (RINGFENCE) INC.;REEL/FRAME:018047/0028
Effective date: 20060101
|Jan 26, 2010
|Certificate of correction
|Mar 5, 2010
|Fee payment
Year of fee payment: 4
|Mar 5, 2014
|Fee payment
Year of fee payment: 8


text:
No approved endorsements
About Mr. Vincent Descubes
I am Vincent Descubes, a french Software Engineer born in Paris, France. I live in Montreal and I am 32 years old. I work as Senior Game Developer at Ubisoft Montreal.
I speak french, english, german and C++ ;-)
I am passionate about video games and graphical arts since my childhood.
I have done several projects on PS2, PSP and DS.
I have worked on Hot Pixel for PSP, CodeLyoko and ThrillVille for DS, and more recently on Shaun White Snowboarding for DS.
If you notice offensive or incorrect information, please contact us.

subset: commoncrawl


text:
More color! I kind of remembered to take a picture of the hedgehog before I started adding color. This is almost the base state–I added a bit of fox red and some yellow highlights. Then I got started with more of the purple and blues.
Tag Archives: fox
Experimenting with Color
As I mentioned here, a while back I stumbled across the work of Kimika Hara. Her work has me thinking about how I approach color. My approach to animals has mostly been what I would call more naturalistic, tending toward the specific colors one might actually find on said animal. But–why not play with other colors?
So here goes. I started with a base of two strands of floss in fairly tame, natural colors (except on the animals' faces, where I used a single strand):


text:
It only takes a minute to get started. Fill out our simple sign up form and login to the site.
This step is optional but will drastically enhance your chances of people actually reading your profile and contacting you. Write a little something about yourself, your hobbies and atach your nicest photo of yourself.
Use our website's sophisticated search to uncover over 60s members who match your desired requirements. Or just leaf through listings and uncover folks that interest you.
Identified someone who interests you? Send a letter to them or just a wink and see how you get along. With a little luck you'll be on your way to a once in a lifetime experience.
You won't regret it


text:
Sauteed string beans with Pork and Shrimp.
Ingredients Edit
- 2 tbit/s. vegetable oil
- 2-3 cloves mashed garlic
- 1 sliced Onion
- 1 tsp. bagoong alamang (Shrimp paste) to taste
- 1/2 cup cubed Pork
- 1/2 cup peeled and deveined Shrimp
- 1 bundle of sitaw (string beans) cut in 3-inch length
- 1/4 cup water if needed
Directions Edit
Saute garlic and Onion in hot vegetable oil as usual. Add bagoong and stir. Add the Pork and stir until slightly brown. Add the sitaw and keep stirring until coated with oil. Add the shrimps (if overcooked, shrimps tend to be tough). Cover pot so let cook for a couple of minutes. Check if gets too dry and keep stirring. Add 1/4 cup water if it dries up to prevent burning. Cook until string beans are tender but still crisp Serve with hot steamed jasmine rice.


text:
Job Title: Chief Security Officer
Qualification and Experience
- A honours degree or HND with specialized training in the police/armed forces and other related services with Twelve (12) years cognate experience.
- A certificate in specialized security training and or a possession of a Master's Degree is an added advantage.
- Superintendent of Police or equivalent ranks in the Armed Forces with Eighteen (18) year's experience.
- The candidate should not be more than Fifty-four (54) years of age on assumption of duty.
- He /She should be able to conduct drills and should show evidence of good communication skills and crisis management.
- The salary and conditions of service of the University Chief Security Officer shall be as obtainable in Federal Universities and as determined from time to time by the Federal Government of Nigeria.
Closing Date
21st December, 2016.
Method of Application
1) Interested and qualified candidates are requested to submit Fifteen type-written copies of their application letters and Curriculum Vitae in an envelope addressed to the:
Vice-Chancellor,2) The post applied for must be clearly written at the top right hand corner of the envelope.
Federal University Otuoke,
Bayelsa State.
3) The application must include academic and professional qualifications, Birth Certificate or Statutory Declaration of Age, list of publications, where applicable, verifiable evidence of work experience and Curriculum Vitae that includes the following information:
4) Candidates should request their referees to send, under confidential cover, their independent reports to the Vice-Chancellor with full details of the applicant and the post applied for not later than the closing date stated above.
- Full Name
- Post Desired
- Date of Birth
- Place of Birth
- State of Origin
- Nationality
- Permanent Home Address
- Current Postal Address
- E-mail Address
- Telephone Number
- Marital Status
- Institutions Attended (with dates)
- Academic Qualifications (with dates)
- Professional Qualifications (with dates)
- Work Experience, General and Specific Experiences (with dates)
- Extra-Curricular Activities
- Reference Letters
5) The reference letter should be marked "Confidential" on the right hand corner of the envelope.
Note: Only candidates who are short-listed will be invited for interview.


text:
Photo Gallery »
The Strand Video Center
We invite you to take an interactive tour of our property and Myrtle Beach, South Carolina. Learn all about our amenities and accommodations, enjoy highlighted clips of favorite area golf courses and check out what is fun to do in town. With these short video clips, you'll have a firsthand look at all you can enjoy during your next stay at The Strand, a boutique resort.
Willbrook Plantation Golf Club
Carved from the site of two Carolina plantations, Willbrook Plantation Golf Club is a course that noted architect Dan Maples has often called "One of my best!"
Other Videos
There were no videos found matching your filter, please try your request again.


text:
Used In
Go to Play Vocabulary
Go to Word Detail
joys, Wanton in fulness, seek to hide themselves In drops of sorrow.
There are no more uses of "plenitude" in the play.
Show samples from other sources
There was simply combined with the thought of Leslie's imminent appearance a stirring awareness—I confess without shame—of this
of money.
William Styron --
Sophie's Choice
Back at the Barbours', amidst the clamor and
of a family that wasn't mine, I now felt even more alone than usual—especially since, as the end of the school year neared, it wasn't clear to me (or Andy either, for that matter) if I would be accompanying them to their summer house in Maine.
Donna Tartt --
The Goldfinch
Go to more samples
Go to Play Vocabulary
. . . enhancing vocabulary while reading


text:
A Way To Record Lectures, Interviews and Stuff To Your PC
I have long been looking for a way to record interviews and whatnot to my computer. Here's a program that might help: LectureRecorder, from Cyprus-based XemiComputers.
LectureRecorder "allows you to record lectures and write summaries for them. To make a lecture summary the program provides several rich-text fields: course, subject, date, lecturer, digest and notes. There is also an option to print the summary. "
The built-in audio recorder uses real-time OGG audio compression, includes an editor and records in 8-bit, mono, with sampling rates of 44KHz down to 11KHz. The files can be converted to standard sound files.
The program costs $20. They also do some interesting other, but roughly similar software, such as Minutes of Meeting Recorder. What's not quite clear in either is whether you can alter playback speed — a must for transcribing — and assign function keys for easily pausing the recording (a great feature of the software that comes with Olympus voice recorders.)
Comments (2)
This from the manufacturers: Regarding your comment about transcribing, the program already has options for altering playback speed and numerous keyboard shortcuts to control it.
When the program is in playback mode click on the double left arrow (< <) to get slower playback. There are four levels of slow playback. Likewise, clicking on double right arrow (>>) will speed the playback up.
To see the list of available keyboard shortcuts go to Help menu and choose Available Shortcuts option. For transcribing you should enable so called "off-focus" shortcuts that give you control over the program when working in other programs.
Hi there.
What sort of mic should I use!!???I tried one (Sony ECM-MS907) but it's not sesitive enough! I'm pluggin in to an iMic (Griffin) then directly into my PowerBook and recording using QuickTime. I know it's not to do with the software here, but the mic is really important!!!
Please help!!!


text:
Accessorize. Beautify. UMT aids make all of it so easy. Add your very own boat title or firm brand for your custom crafted aluminum gangway. Include LED lights to get a unique and distinctive touch.Much like the European or contemporary aluminum gangway trend? UMT might support. Aluminum gangways certainly are a UMT specialty. Their durability and resilience are famous and ideally produced towards quite possibly the most exacting requirements of perfection ClearlyObviouslyNaturally, otherwise about the shoe-string investing budgetcost rangefinances, awesomeawesomegreatneat presentsproductsitems could integrate foodsmealsfoods hinders, containers linked withregardingincluding candiestreats, torches, umbrellas, wine drinkswinewine bottles or possibly moregreater state-of-the-art productspartsbits for adornment reasonsreasonsfunctionsuses. There's noThere isn't anyThere is noThere's basically no maximummaximum that absolutely sure canthat you couldyou could invest in marketing and promoting giftsmarketing productsmarketing objects which make sure youyou need to have tomake particular to. It just requires a smallsmallminor creativenesscreativityideas along with aalong with ain addition to a pat linked withregardingincluding senseseem judgmentsmart practice to choosechooseto select presentsproductsitems which can be relevant, affordableaffordable and consequently are apt to bemost probable beprone to finish up valuedappreciatedloved through the readersvisitorspeoplepeople.mcm bag small
Particularly firstfirst, very good top quality is really pretty subjective, howevernonetheless there have to be a couple ofseveralnumerous typical knowingknowingcomprehension how all of us identify if yourjust in problem awhen the gown presents high-quality or otherwise. Top quality is genuinely afrequently a obscure technique to numerous peoplefolksmales and girls but could finish up beingbecomecontinually be indicatedcharacterisedrecognizedindicated in to two components. The incredibly very first ismight be elements, and nonetheless an additional the 1st ismight be stitching. You could uncover someYou will find out severalYou will learn a couple ofYou will obtain a great deal of fundamentalfundamentalsimplestandard recommendationsrecommendationssuggestionstips the way in which you'll be able to obtain a appreciably betterenhanceda bigger gown in conjunction with yourtogether with yourmaking utilization of your restrictedrestrictedminimal investing budgetcost rangefinances. You have to considerconsidercontemplate four primarysignificantkey issuesproducts purchasingwhen buyingwhen selectingwhen picking gown: top quality, style (type and design, pattern), ease of accesssupplyaccess (modification, personalizedcustomizedcustomized purchase), and lastlyand finallyfinallylastly costcostvaluecost. Replica Clothes: ?Affordability. High top quality, comfort and style doesn need to be highly-priced. The very best point about Eros Veneziani garments may be the proven fact that it is actually possible to appreciate them with no possessing busting your budget by ordering them at DealByEthan.com, during which you acquire them at discounted costs. The further garments you purchase, the larger your very low price.
secondNextSubsequent, the actual design/style or evenpossiblyin addition to pattern within the gown is certainly an veryis undoubtedly ais unquestionably a crucial element for prime fantastic high quality attire. Type may well be thewould be themay be the distinctive form with the gown and it truly is style. The kind could bemight bemay be lengthyextendedextendedprolonged, quick, basketballbasketballfootball dresswedding gown, also astogether with golf teefirst tee duration. The authentic attire colour could bemight bemay be strongseemreliable, combinedcombinedcome up with, or evenpossiblyin addition to printing. Pattern may be thewould be themay be the feeling likewise astogether with colour inside the recent period. A number of peopleLots of peopleSome peopleMany individuals simplybasicallyonly adhere tostay withadhere to developmentshabitsstyles no matterregardless ofregardless ofregardless of it definitely is type and style. DevelopmentsHabitsStyles are producedare producedare produced by means of the the majority of importanteffectivesignificant best inventive designersdesignersmakers in the gown community.mcm backpack red
One of one's most famous perfumes, Chanel No 5, was released by Chanel in 1921. The perfume was revolutionary in scent and presentation. The bottle was a very simple layout. The perfume was intended to make the masculine planet available to women. adar Arches accommodate halogen lights, antennas and in addition a wide selection of other products. What ever the mount, UMT Worldwide delivers. Just ask us. The true Casio wrist watcheswatcheswrist watches the truth isthe basic reality isthe reality may be the fact that nowadaysnowadaysat this time are already notaren'tjust weren't beganstartedbegan outcommenced which features a see or possiblyin addition to add-onsadd-onscomponentsequipment enterprise that'swhich could effectively bethat's trulyreallyreally incredibleamazingwonderful for yourfor thetowards the premium good quality likewise astogether with cutting-edge styles oftypes oftypes of Casio likeslikeslovesanticipates the truth isthe very basic reality isthe actuality could be the proven fact that nowadaysnowadaysat this time. Within 1946, Casio was producedcame fromis produced with each other withalong withusing Tadio Kashio since the mindchiefboss of one's hands onon the jobdiligent corporation. During this time aroundThroughout this eraThroughout this time about periodDo your exceptionally ideal, Asia was from the middle ofgreatest marketplace ofthe midst of Planet FightConflictWarfare two, the authentic problem financially linked withregardingincluding Asia such as a lot more nationsNations in europeThe euEurope had beenwound up being considerable. At that timeThroughout timeIn in recent times when Mister. Kashio beganstartedbegan outcommenced their organization, she or he was at about staying effectivesucceedingwhich aids make it which heand also the guyand hubby do specifically that applying the development and improvement ofongoing advancement and development from the real yubiwa water pipe.
longchamp planetes tote bag
Paint Camila Alves went just soon after an occupation like a style and design layout from 1920Twenty. Aside fromAdditionally toApart from optionsoptionsoptionschoices within, the ladyladythe lady likeswantsloves chanceearnings chancehome based modest enterprise chancework from dwelling organization. The ladyladyThe lady likewise astogether utilizing the woman's mothermothermothermother gonna create developing handbagshandbagshandbags and pursesbags soon after that setup their very personal handbag corporation, Muxo.Prev page:longchamp bags outlet


text:
|Message view
|« Date » · « Thread »
|« Date » · « Thread »
|"email@example.com" <seba.wag...@gmail.com>
|Re: issue with keystore path in red5-core.xml while using RTMPS
|Fri, 01 Feb 2013 03:57:20 GMT
Thanks for sharing Bart, if you want to contribute you can also easily make this documentation permanent by adding it to: https://cwiki.apache.org/confluence/display/OPENMEETINGS/Index Just make sure to ping the mailing list so people can give you feedback on your docs and eventually a dev has time to merge this into the main website. Sebastian 2013/1/31 Bart Coninckx <email@example.com> > Hi, > > I'm just mentionning this for people encountering this in the future. I > understand from previous posts it should not be necessary to do, but it > helps in my case. > > So what happened: I left a working installation yesterday and when trying > to log in to it again today, I could not, observing "try1, try2, try3, > NetConnection.Connect.Failed". > The logging showed: > > Exception caught Keystore or password are null > > by editing red5-core.xml and replacing this: > > <property name="keystoreFile" value="conf/keystore" /> > > with this: > > <property name="keystoreFile" value="/data/openmeetingsd/**conf/keystore" > /> > > and restarting OM, things work again. > I can reproduce this at infinitum. I don't know if it is an effect of me > using a different install directory, but it is what it is. > > Might help someone out there. > > BC > -- Sebastian Wagner https://twitter.com/#!/dead_lock http://www.webbase-design.de http://www.wagner-sebastian.com firstname.lastname@example.com
|View raw message


text:
Your home might not be the Gordon House, but that doesn't mean it isn't as special. A new paint job from the industrious students at College Pro Salem can be the first step in making your house look as important as it is to your family. Our student entrepreneurs care about the people of Salem just as much as you do, and they'll prove it with their hard work and meticulous attention to detail. You'll love the results and the feeling of giving hard-working local students an opportunity to get a valuable education outside the classroom.
It's common knowledge that one of the fastest, easiest, and least expensive ways to transform your home is a fresh coat of paint. It can turn even the dullest and most run-down house into a sparkling beacon of beauty. One of the fastest, easiest and least expensive ways to obtain that coat is through College Pro Salem. In addition to investing in the present beauty of your home, you'll be investing in the future of your community. College Pro employs only the most industrious, hard-working Salem students. Our student painters are trained in everything from house painting to business management. They gain real-world experience while adding real value for your house.
With competitive pricing and amazing customer service, College Pro Salem house painting has everything you need to spruce up your home. Our services include a two-year warranty, and we don't collect final payment until the job is finished and you're thrilled with your rejuvenated house. You'll be amazed by the skill, speed, and professionalism of our student employees and entrepreneurs. Give back to your community while giving your house a much-needed facelift with College Pro Salem. It's the perfect solution for you, your beloved home, and the great city of Salem! We have locally owned franchises all over North American and over 40 years of experience, but College Pro is still dedicated to helping local communities. Get started on the gorgeous house you've always wanted with College Pro Salem.
Learn more about College Pro Salem


text:
Here is PCWorld's live coverage of Samsung's London Mobile Unpacked press conference. The live blog is brought to PCWorld courtesy of the UK-based PC Advisor, a PCWorld sibling publication.
See the updated news: Samsung Launches Galaxy S III Smartphone
This story, "Live Now: Samsung Galaxy S3 Is Officially Here" was originally published by PC Advisor (UK).


text:
Benge Photography Photographer
PersadieModel Male Oklahoma City, Oklahoma, US
My MM URL: http://www.modelmayhem.com/persadiejames
Mayhem # 2353827
About MeHello and welcome, my name is james. I've been modeling for a little while now...still very new to this, but I'm loving every minute of it. I've been out the loop for sometime, however, I'm looking to try and get back into it. Take a look at my pics...Most are kinda old but my image haven't change much...just put on a little more muscle mass. If you have any ideas on a shoot please message me and fill me in...I would love to hear them.
Have you worked with Persadie? Add Credits for Persadie! >>
Credit Noteshttp://www.b-adore.com/lifestyle/tag/james-persadie/
Benge Photography Photographer
studio1409 Artist/Painter
Ciarra A Model
Leland Images Photographer
ashley_nic... Model
Monique Prestridge Model
Loading Content


text: 12/02/10 12/01/10 POPSUGAR Celebrity Angelina Jolie Pictures of Angelina and Knox December 1, 2010 by katie henry 0 Shares Chat with us on Facebook Messenger. Learn what's trending across POPSUGAR. View on One Page Photo 0 of 20 Start Slideshow ADVERTISEMENT () Share This Link Copy ← Use Arrows Keys → 0 Pictures of Angelina and Knox Previous Next Angelina Jolie


text:
Mt Elgon rankings
Difficulty ranking world: 2077 (all)
Ranking Kenya: 1 (all)
Difficulty score: 89.78 what?
Mt Elgon ratings
(rate it)
The Mt Elgon is situated in Western (KE).
Starting from Kitale,
the Mt Elgon ascent is 16.88 km long. Over this distance, you climb 870 heightmeters.
The average percentage thus is 5.1 %.
Look for other sides to climb the Mt Elgon.
Click here to open big profile.
Click here to open detailed route.
Find climbs close to the Mt Elgon: within 10 km - within 20 km - within 50 km
Find all climbs and cols in Western (KE) on a map.
No stories submitted yet. Did you climb this mountain?
Did you climb the Mt Elgon? Please send your cycling story, description or comments. You can also send us video's or send us pictures on the Mt Elgon.
© climbbybike™ All rights reserved 2005 -


text:
Forensic Medicine: Clinical and Pathological Aspects
This edited, multi-author, multi-national book is intended to provide state-of-the-art information about the forensic aspects of medicine and related fields for those involved in the clinical and pathological forensic aspects of the care, assessment, investigation and diagnosis of victims, perpetrators and assailants and others involved in police or judicial systems. Each chapter is written by an acknowledged specialist and established authority within the particular field and this book is intended to become the standard reference work on the forensic aspects of forensic medicine and healthcare. Each chapter, when appropriate, will suggest clear guidelines for the practical applications of issues discussed and will be fully referenced with the most up-to-date or most authoritative references and clear illustrations, tables and algorithms for practical guidance. The book will be divided into a number of sections, concerned with the different aspects of forensic medicine, for ease of reference.
Please visit Help Page for Questions
regarding ISBN / ISBN-10 / ISBN10, ISBN-13 / ISBN13, EAN / EAN-13, and Amazon
Home | ISBN Directory | Affiliate
Program | Contact
Copyright © 2003-2014 AllDiscountBooks.net All rights reserved.


text:
As Destiny's crew continues to battle Lucian Alliance soldiers over control of the ship, T.J. finds herself and her baby transported to a safe place.
"Intervention" Facts:
"Intervention" on GateWorld:
Download "Intervention" now from Amazon or iTunes!
Rewatch "Intervention" this week! Then post your comments below, or head over to the "Intervention" discussion forum and see what people were saying back in the day. What are your favorite moments?
Each week we're highlighting a favorite episode from Stargate's 17 seasons. Watch the episode with us this week and join in the fun!
Nothing about the introduction of Ginn? She's in the selected thumbnail and everything.
Thanks for getting this piece up, as always. Better late than never. :)
If you are volunteering to write these things every week, send me an e-mail and we'll talk! ;)
Remember Me
Will you watch the new Devlin/Emmerich Stargate movie?
View Results


text:
Triamterene combined with hydrochlorothiazide is a diuretic used to reduce excess water and salt in the body, according to MedlinePlus. The medication is administered orally in a pill form as a tablet or capsule. Common ailments treated by triamterene and hydrochlorothiazide include high blood pressure and edema.Continue Reading
Triamterene and hydrochlorothiazide have a direct effect on the kidneys by controlling how much water and sodium are reabsorbed by the body, as explained by MedicineNet. The kidneys naturally try to compensate for the loss of sodium by replacing it with potassium, thus decreasing potassium levels in the exchange. Hydrochlorothiazide reduces water retention by increasing urine production, while triamterene works to regulate potassium levels.Learn more about Medications & Vitamins


text:
This week we discuss UFC 203 – including the heavyweight title fight and the CM Punk debacle–as well as Gennady Golovkin vs Kell Brook. We answer questions on Minoru Suzuki, the UFC flyweight division, and great fights for noobs.
07/09/2016 FGB # 6 + Reading Lists
In this week's Fights Gone By podcast we discuss Josh Barnett's Sakuraba-esque victory over Andrei Arlovski, Ryan Bader helps us reminisce about Joachim Hansen's intercepting knees, and we cover UFC 203.
I also clipped off a couple of highlights from previous episodes including a boxing reading list and a grappling reading list.
17/08/2016 FGB #3: Steven Seagal + UFC 202
Episode three of the Fights Gone By Podcast is now up, covering the remaining fights on the UFC 202 card, complete with a rant about Steven Seagal.
Also available on iTunes and Direct Download can be found here.
Hey guys, I managed to get the MP3 version of the podcast up for those who want to listen to it on the go (or while they're supposed to be working).
Here's the direct download link.
Thank you all for all the positive feedback already! Hopefully I'll have these coming out every week or two and we'll be on iTunes soon.
03/08/2016 FGB Podcast #1
After promising to put out more videos I finally decided to give podcasting a go! An experimental episode of 'Jack's Unnamed Podcast' is up on Youtube now for folks to enjoy. In it we talk the ins and outs of McGregor vs Diaz II and I answer some reader questions.
Please let me know how you find it and what I should do for next time in the Youtube comments. I'm looking into iTunes and SoundCloud at the moment for future episodes. I'm not sure how often I'll do them but I'll try to respond to whatever demand there is.
21/06/2016 The State of Ringcraft etc.
Lots going on at the moment. I'm playing with my new microphone and throwing out the occasional video on my Youtube channel (make sure to subscribe to that I suppose). I recently published videos entitled: Some Quick Thoughts on Stephen Thompson, Pressure Point Techniques That Could Save Your Life, and A Little Bit of Buddy McGirt. Really I'm just twiddling my thumbs on the video front until Vice decide to release Ringcraft IV, which has been ready since January. If they decide Fightland is done with videos I'll get a new channel and a Patreon page and decide how to proceed from there. I would love to team up with an animator and do some history stuff or make something similar to Luke Thomas' excellent Monday Morning Analyst.
At any rate I'm having a lot more fun doing voice overs and scripts nowadays. It still takes me far too long to record something I actually like but I'm getting there. I even started doing some research to have a bash at writing a screenplay combining my love of fight history and titillating, violent schlock.
Something which caught my eye this week was BJJ Scout's return to business. He is putting together a multi-part series on the guard passing of Demian Maia and it is well worth your time.
What else happened since my last blog? Well Muhammad Ali and Kimbo Slice died, which was quite upsetting. And then Michael Bisping became UFC middleweight champion on short notice which–whether you like him or not–is pretty inspiring. Oh and Brock Lesnar is coming back for a one off fight to save UFC 200 which was pretty much unthinkable until the moment it was announced.
We've got three huge events coming up back-to-back-to-back, so the next few weeks will be fairly hectic. Apologies that I don't have any big updates regarding books or Ringcraft right now, but thanks for all your support and patience.
24/02/2016 Updating Blog
Apologies for the extremely long time between updates. The last time I wrote an entry on here was November of 2014! A lot has happened between then and now. Hundreds of articles, a couple of injuries, and a nomination for MMA Journalist of the Year. Overall I can't complain.
Also, Fightland got my webseries off the ground! You can go and watch that in the Videos tab up the top there. We are three episodes in at the time of writing, with a fourth on the horizon. The original plan was for 'How to Enjoy a Fight' but we ended up going with Jack Slack's Ringcraft. Ringcraft just sounded much snappier.
At any rate, I'm doing a bit of a spring clean of Fights Gone By. With all the writing I do for Fightland I struggle to post my own articles here as well. I wanted to do that for a while but it just never happened. Instead I have decided to use the Articles and Analysis section to compile the features which I have been truly proud of writing.
Most of the gifs and videos in the Techniques and Principles section from the first incarnation of Fights Gone By have expired, so I have replaced that section of the site with a Resources section which I will add notable analysts, writers and podcasters to as we go along.
Books is still books, where you can pick up the old technical studies I wrote a few years back. If you want to check out my new ebook, Finding the Art, you can pick it up on Amazon.
Hopefully over the coming weeks I can start to update this site and share some of the wonderful work and ideas I have encountered in the martial arts world.