text:
Testing SATA Express And Why We Need Faster SSDsby Kristian Vättö on 3/13/2014 7:00 AM EST
- Posted in
- Storage
- SSDs
- Asus
- SATA Express
130 Comments
Back to Article
R0H1T - Thursday, March 13, 2014 - link"This is actually the same motherboard as our 2014 SSD testbed but with added SATAe functionality."
Does this mean you're going to test next gen SSD's with this(SATAe) & if so perhaps anytime during the current 2014 calendar year? Reply
ddriver - Thursday, March 13, 2014 - linkSo why not use 2 lane PCIE for the SSD instead - it does look like it uses less power and has higher bandwidth than SATAE? Reply
DanNeely - Thursday, March 13, 2014 - linkMini ITX with a discrete GPU (or any other card) or mATX with dual GPU setups either don't have anywhere to put a PCIe SSD or don't have anywhere good to put one. Reply
SirKnobsworth - Saturday, March 15, 2014 - linkThat's what M.2 is for. Reply
Bigman397 - Friday, April 04, 2014 - linkWhich is a much better solution than retrofitting controllers and protocols meant for rotational media. Reply
Kristian Vättö - Thursday, March 13, 2014 - linkThe motherboard in our 2014 testbed is the normal Z87 Deluxe without SATAe. There aren't any official SATAe products yet so we're not sure how we'll test those but the ASUS board is certainly an option. Reply
MrPoletski - Thursday, March 13, 2014 - linkI wonder what ridiculous speed SSD's we are going to start seeing with this tech. Quite exciting really. Reply
nathanddrews - Friday, March 14, 2014 - linkThe Future!
http://www.tomsitpro.com/articles/intel-silicon-ph... Reply
thevoiceofreason - Thursday, March 13, 2014 - link"because after all we are using cabling that should add latency"
Why would you assume that? Reply
DiHydro - Thursday, March 13, 2014 - linkWhen talking about one nanosecond signals, a charge will travel approximately 30 cm or 1 foot. If you add length onto a signal path, it will delay your transmission speed. Reply
frenchy_2001 - Friday, March 14, 2014 - linkno, it does not. It adds latency, which is the delay before any command is received. Speed stays the same and unless your transmission depends on hand shake and verification and can block, latency is irrelevant.
See internet as a great example. Satellite gives you fast bandwidth (it can send a lot of data at a time), but awful latency (it takes seconds to send the data).
As one point of those new technology is to add a lot of queuing, latency becomes irrelevant, as there is always some data to send... Reply
nutjob2 - Saturday, March 15, 2014 - linkYou're entirely incorrect. Speed is a combination of both latency and bandwidth and both are important, depending on how the data is being used.
Your dismissal of latency because "there is always data to send" is delusional. That's just saying that if you're maxing out the bandwidth of your link then latency doesn't matter. Obviously. But in the real world disk requests are small and intermittent and not large enough to fill the link, unless you're running something like a database server doing batch processing. As the link speed gets faster (exactly what we're talking about here) and typical data request sizes stay roughly the same then latency becomes a larger part of the time it takes to process a request.
Perceived and actual performance on most computers are very sensitive to disk latency since the disk link is the slowest link in the processing chain. Reply
MrPoletski - Thursday, March 13, 2014 - linkwait:
by Kristian Vättö on March 13, 2014 7:00 AM EST
It's currently March 13, 2014 6:38 AM EST - You got a time machine over at Anandtech? Reply
Ian Cutress - Thursday, March 13, 2014 - linkI think the webpage is in EDT now, but still says EST. Reply
Bobs_Your_Uncle - Saturday, March 15, 2014 - linkPRECISELY the point of Kristian's post. It's NOT a time machine in play, but rather the dramatic effects of reduced latency. (The other thing that happens is the battery in your laptop actually GAINS charge in such instances.) Reply
mwarner1 - Thursday, March 13, 2014 - linkThe cable design, and especially its lack of power transmission, is even more short sighted & hideous than that of the Micro-B USB3.0 cable. Reply
3DoubleD - Thursday, March 13, 2014 - linkAgreed, what a terrible design. Not only is this cable a monster, but I can already foresee the slow and painful rollout of PCIe2.0 SATAe when we should be skipping directly to PCIe3.0 at this point.
Also, the reasons given for needing faster SATA SSDs are sorely lacking. Why do we need this hideous connector when we already have PCIe SSDs? Plenty of laptop vendors are having no issue with this SATA bottleneck. I also debate whether a faster, more power hungry interface is actually better on battery life. The SSD doesn't always run at full speed when being accessed, so the battery life saved will be less than the 10 min calculated in the example... if not worse that the reference SATA3 case! And the very small number of people who edit 4k videos can get PCIe SSDs already. Reply
DanNeely - Thursday, March 13, 2014 - linkBlame Intel and AMD for only putting pcie 2.0 on the southbridge chips that everything not called a GPU are connected to in consumer/enthusiast systems. Reply
Kristian Vättö - Thursday, March 13, 2014 - linkA faster SSD does not mean higher power consumption. The current designs could easily go above 550MB/s if SATA 6Gbps wasn't bottlenecking, so a higher power controller is not necessary in order to increase performance. Reply
fokka - Thursday, March 13, 2014 - linki think what he meant is that while the actual workload may be processed faster and an idle state is reached sooner on a faster interface, the faster interface itself uses more power than sata 6g. so the question now is in what region the savings of the faster ssd are and in what region the additional power consumption of the faster interface. Reply
mkozakewich - Friday, March 14, 2014 - linkOoh, or what if we had actual M.2 slots on desktop motherboards that could take a ribbon to attach 2.5" PCIe SSDs? Reply
phoenix_rizzen - Thursday, March 13, 2014 - linkYeah. Seems strange that they wouldn't re-use the M.2 or mSATA connector for this. Why take up 2 complete SATA slots, and add an extra connector? What are they doing with the SATA connectors when running in SATAe mode?
It amost would have made sense to make a cable that plugged into <whatever> at the drive end, and just slotted into a PCIe x1 or x2 or x4 slot on the mobo. Skipped the dedicated slot entirely. Then they wouldn't need that hokey power dongle off the drive connector. Reply
frenchy_2001 - Friday, March 14, 2014 - linkThey were looking for backward compatibility with current storage and in that context, the decision makes sense. No need to think about how to plug it, it just slots right where the rest of the storage goes and can even accept its predecessor.
It's a desktop/server/storage centric product, not really meant for laptop/portable.
But I agree its place is becoming squished between full PCIe (used already in data centers) and miniPCIe/M2 used in portables. As the requirement is already 2x PCIe lanes (like the others), it will be hard to use for lots of storage and if you cannot fit 24 of those in a rack (which is how most server use SATA/SAS), as few servers have 48 lanes of PCIe hanging around unused then it seems only reserved to desktop/workstation and those can easily use PCIe storage... Reply
phoenix_rizzen - Friday, March 14, 2014 - linkYeah, until you try to connect more than 2 of those to a motherboard. And good luck getting that to work on a mini-ATX/micro-ATX board. Why use up two whole SATA ports, and still use an extra port for PCIe side of it?
How are you going to make add-in controller cards for 4+ drives? There's no room for 4 of those connectors anywhere. And trying to do a multi-lane setup like SFF-8087 for this will be rediculous.
The connector is dumb, no matter how you look at it. Especially since it doesn't support power. Reply
jasonelmore - Saturday, March 15, 2014 - linkit looks like the only reason to be excited about this connector is for using older Hard Drives 2.5 or 3.5 form factor, and putting them on a faster bus.
Other than that, other solutions exist and they do it quicker and with less power. its just a solution to let people use old hardware longer. Reply
phobos512 - Thursday, March 13, 2014 - linkIt's not an assumption. The cabling adds distance to the signal path, which increases latency. Electrons don't travel at infinite speed; merely the speed of light (in a vacuum; in a cable it is of course reduced). Reply
ddriver - Thursday, March 13, 2014 - linkYou might be surprised now negligible the effect of the speed of electrons is for the total overall latency. Reply
Khenglish - Thursday, March 13, 2014 - linkIt's negligible.
The worst cables carry a signal at 66% of the speed of light, with the best over 90%. If we take the worst case scenario of 66% we get this:
speed of light = 3*10^8 m/s
1m / (.66 * 3*10^8 m/s) = 5ns per meter
If we have a really long 5m cable that's 25ns. Kristian says it takes 115us to read a page. You never read less than 1 page at a time.
25ns/115us = .0217% for a long 5m cable. Completely insignificant latency impact. Reply
willis936 - Thursday, March 13, 2014 - linkThe real latency number to look at is the one cited on the nvme page: 2.8us. It's not so negligible then. It does affect control overhead a good deal.
Also I have a practical concern of channel loss. You can't just slap a pcie lane onto a 1m cable. Pcie is designed to ride a vein of traces straight to a socket, straight to a card. You're now increasing the length of those traces, still putting it through a socket, and now putting it through a long, low cost cable. Asking more than 1.5GB/s might not work as planned going forward. Reply
DanNeely - Thursday, March 13, 2014 - linkActually you can. Pcie cabling has been part of the spec since 2007; and while there isn't an explicit max length in the spec, at least one vendor is selling pcie2.0 cables that are up to 7m long for passive versions and 25m for active copper cables. Fiberoptic 3.0 cables are available to 300m. Reply
Khenglish - Thursday, March 13, 2014 - linkThat 2.8 uS you found is driver interface overhead from an interface that doesn't even exist yet. You need to add this to the access latency of the drive itself to get the real latency.
Real world SSD read latency for tiny 4K data blocks is roughly 900us on the fastest drives.
It would take an 18000 meter cable to add even 10% to that. Reply
willis936 - Thursday, March 13, 2014 - linkShow me a consumer phy that can transmit 8Gbps over 100m on cheap copper and I'll eat my hat. Reply
Khenglish - Thursday, March 13, 2014 - linkThe problem is long cables is attenuation, not latency. Cables can only be around 50M long before you need a repeater. Reply
mutercim - Friday, March 14, 2014 - linkElectrons have mass, they can't ever travel at the speed of light, no matter the medium. The signal itself would move at the speed of light (in vacuum), but that's a different thing.
/pedantry Reply
Visual - Friday, March 14, 2014 - linkIt's a common misconception, but electrons don't actually need to travel the length of the cable for a signal to travel through it.
In layman's terms, you don't need to send an electron all the way to the other end of the cable, you just need to make the electrons that are already there react in a certain way as to register a required voltage or current.
So a signal is a change in voltage, or a change in the electromagnetic fields, and that travels at the speed of light (no, not in vacuum, in that medium). Reply
AnnihilatorX - Friday, March 14, 2014 - linkJust to clarify, it is like pushing a tube full of tennis balls from one end. Assuming the tennis balls are all rigid so deformation is negligible, the 'cause and effect' making the tennis ball on the other end move will travel at speed of light. Reply
R3MF - Thursday, March 13, 2014 - linkhaving 24x PCIe 3.0 lanes on AMD's Kaveri looks pretty far-sighted right now. Reply
jimjamjamie - Thursday, March 13, 2014 - linkif they got their finger out with a good x86 core the APUs would be such an easy sell Reply
MrSpadge - Thursday, March 13, 2014 - linkRe: "Why Do We Need Faster SSDs"
You power consumption argument ignores one fact: if you use the same controller, NAND and firmware it costs you x Wh to perform a read or write operation. If you simply increase the interface speed and hence perform more of these operations per time, you also increase the energy required per time, i.e. power consumption. I your example the faster SSD wouldn't continue to draw 3 W with the faster interface: assuming a 30% throughput increase expecting a power draw of 4 W would be reasonable.
Obviously there are also system components actively waiting for that data. So if the data arrives faster (due to lower latency & higher throughput) they can finish the task quicker and race to sleep. This counterbalances some of the actual NAND power draw increases, but won't negate it completely. Reply
Kristian Vättö - Thursday, March 13, 2014 - link"If you simply increase the interface speed and hence perform more of these operations per time, you also increase the energy required per time, i.e. power consumption."
The number of IO operations is a constant here. A faster SSD does not mean that the overall number of operations will increase because ultimately that's up to the workload. Assuming that is the same in both cases, the faster SSD will complete the IO operations faster and will hence spend more time idling, resulting in less power drawn in total.
Furthermore, a faster SSD does not necessarily mean higher power draw. As the graph on page one shows, PCIe 2.0 increases baseline power consumption by only 2% compared to SATA 6Gbps. Given that SATA 6Gbps is a bottleneck in current SSDs, more processing power (and hence more power) is not required to make a faster SSD. You are right that it may result in higher NAND power draw, though, because the controller will be able to take better advantage of parallelism (more NAND in use = more power consumed).
I understand the example is not perfect as in real world the number of variables is through the roof. However, the idea was to debunk the claim that PCIe SSDs are just a marketing trick -- they are that too but ultimately there are gains that will reach the average user as well. Reply
MrSpadge - Friday, March 14, 2014 - linkYou're right, the increased interface power consumption won't matter much and will be counterbalanced by the quicker execution time. But as far as I understand the bulk of SSD power draw under load, especially for writes, comes from the actual NAND power draw (unless the controller would be really inefficient). If this is true higher performance automatically equates higher SSD power draw under load. Reply
willis936 - Thursday, March 13, 2014 - linkI love SATAe and NVMe but whenever SAS is mentioned as a comparison it would be nice to use 12G numbers. I noticed a Microsoft graph showed the 6G but didn't even label it. A doubling of bandwidth is nothing to sneeze at. That said SAS is expensive and is for a very different market. Reply
Flunk - Thursday, March 13, 2014 - linkI think they're really making a mistake trying to keep the same connector as SATA. Tacking on a new cable that looks so unwieldy just seems silly. And why not just use M.2 slots? Especially if this is for notebooks (and based on the power usage comparisons it seems like it is, otherwise why would it matter?).
I suspect this will go nowhere. Reminds me of ISA 2.0. Reply
Rajinder Gill - Thursday, March 13, 2014 - linkBackwards compatibility with existing SATA devices was the primary reason for keeping the connector as part of the interface. :) Reply
Flunk - Thursday, March 13, 2014 - linkI understand that, but there isn't much reason not to have 2 sets of ports with the legacy ones slowly disappearing on a desktop. The ports are not large and there is plenty of space. This way we're stuck with a future of badly-designed ports far past the end of SATA's lifetime. Reply
Kristian Vättö - Thursday, March 13, 2014 - linkSATA Express is mainly for desktops -- in mobile M.2 will be the dominant form factor (though SATAe might have some place there too as I mentioned in the article).
As for power consumption and battery life, that was about PCIe in general. Reply
phoenix_rizzen - Thursday, March 13, 2014 - linkSo why not add M.2 slots to the desktop, in a vertical orientation, and just make M.2->M.2 cables? Then add the M.2 connector to desktop drives? Reply
TheinsanegamerN - Monday, March 24, 2014 - linkbecause, silly, that would mean being progressive and eliminating all backwards compatibility, and we CANT do that! /s
in all seriousness, that would be much nicer. manufacturers would probably throw a temper tantrum, but aside from that, it would be a great solution. Reply
grahaman27 - Thursday, March 13, 2014 - linkI would like to see USB 3.1 replace sata6. It sounds unusual, but with the combination of 10Gbps speeds, the new two-way small connector, and integrated power, I think it would really be useful for the expandability and tidiness inside my computer. Reply
Veramocor - Thursday, March 13, 2014 - linkJust posted that later on. I have an external usb 3.0 hardrive why can't I have an internal one. Even better would be thunderbolt 2 at 20 Gbps. Reply
SirKnobsworth - Thursday, March 13, 2014 - linkThunderbolt 2 is really PCIe x4 + DisplayPort in disguise, and you don't need DisplayPort to your SSD. Reply
MrSpadge - Thursday, March 13, 2014 - linkCouldn't you build a nice M.2 to SATAe adapter in a 2.5" form factor and thereby reuse your existing M.2 designs for SATAe? Reply
Kristian Vättö - Thursday, March 13, 2014 - linkTechnically yes, but the problem is that M.2 is shaped differently. You could certainly fit a small M.2 drive with only few NAND packages in there but the longer, faster ones don't really fit inside 2.5". Reply
Kevin G - Thursday, March 13, 2014 - link"At 24 frames per second, uncompressed 4K video (3840x2160, 12-bit RGB color) requires about 450MB/s of bandwidth, which is still (barely) within the limits of SATA 6Gbps."
This is incorrect:
3840 * 2160 * 12 bit per channel * 3 channels / 8 bits per byte * 24 fps ~ 896 MByte/s
And that figure is with with good byte packing. For raw recording, the algorithm may pack the 12 bits into two bytes for speed purposes meaning you'd need about 1.2 Gbyte/s of bandwidth. Jumping to 4096 x 2160 resolution at 12 bit color and 30 fps, the bandwidth need grows to about 1.6 Gbyte/s.
The other thing worth noting is that uncompressed recording is going to take a lot of storage. A modern phone recording at the highest quality settings with 64 GB of storage would last less than 40 seconds before running out. Reply
Kristian Vättö - Thursday, March 13, 2014 - linkOh, you're absolutely right. I used the below calculator to calculate the bandwidth but accidentally left "interlaced" box ticked, which screwed up the results. Thanks for the heads up, fixing... Reply
Kristian Vättö - Thursday, March 13, 2014 - linkAnd the calculator... http://web.forret.com/tools/video_fps.asp?width=38... Reply
JarredWalton - Thursday, March 13, 2014 - linkAren't there *four* channels, though? RGB and Alpha? Or is Alpha not used with 12-bit? Reply
Kevin G - Thursday, March 13, 2014 - linkNo real way to record with an Alpha channel value to my knowledge. Cameras and scanners etc all presume a flattened image as if everything were solid. The only exception to this would be direct frame buffer capture from video memory which can independently process an Alpha channel.
Input media would generally be 36 bit. During the editing phase an Alpha channel can be added as part of compositing pipeline bringing the total bit depth to 48 bit. Final rendering can be done to a 48 bit RGBA file. Display output on screen will be reduced to 36 bit due to compositing for the frame buffer. Reply
Nightraptor - Thursday, March 13, 2014 - linkWhen I saw the daughterboard Asus provided my instant thought was actually using this (in pcie 3.0 form) to somehow provide the option to add an external GPU to a tablet. I may be the outlier, but my dream would be to have and 11.6" 16:10 1920 x 1200 tablet with the ability to connect a keyboard dock to function as a laptop, or another dock with a discrete graphics card to function as a desktop for occasional gaming (1080p at high setting would be all I'd ask for - so pcie 3.0 4x should be sufficient). If you could somehow get a SATAe cable on a tablet I think this would do it. Reply
vladman - Thursday, March 13, 2014 - linkIf you want speed from storage, get a nice Areca PCIe RAID controller, attach 4 or more fast SSDs, do RAID 0, and you've got anywhere from 1.7 to 2GB/s of data transfer. Done deal. Reply
Guspaz - Thursday, March 13, 2014 - linkThe only justification for why anybody might need something faster than SATA6 seems to be "Uncompressed 4K video is big"...
Except nobody uses uncompressed 4K video. Nobody uses it precisely BECAUSE it's so big. 4K cameras all record to compressed formats. REDCODE, ProRes, XAVC, etc. It's true that these still produce a lot of data (they're all intra-frame codecs, which mean they compress each frame independently, taking no advantage of similarities between frames), but they're still way smaller than uncompressed video. Reply
JarredWalton - Thursday, March 13, 2014 - linkBut when you edit videos, you end up working with uncompressed data before recompressing, in order to avoid losing quality. Reply
willis936 - Thursday, March 13, 2014 - linkThe case you described (4K, 12bpc, 24fps) would also take an absolutely monumental amount of RAM. I can't think of using a machine with less than 32GB for that and even then I feel like you'd run out regularly. Reply
Guspaz - Thursday, March 13, 2014 - linkAre you rendering from Premiere to uncompressed video as an intermediate format before recompressing in some other tool? If you're working end-to-end with Premiere (or Final Cut) you wouldn't have uncompressed video anywhere in that pipeline. But even if you're rendering to uncompressed 4K video for re-encoding elsewhere, you'd never be doing that to your local SSD, you'd be doing it to big spinning HDDs or file servers. One hour of uncompressed 4K 60FPS video would be ~5TB. Besides, disk transfer rates aren't going to be the bottleneck on rendering and re-encoding uncompressed 4K video. Reply
Kevin G - Thursday, March 13, 2014 - linkThat highly depends on the media you're working with. 4K consumes far too much storage to be usable in an uncompressed manner. Upto 1.6 GByte/s is needed for uncompressed recording. A 1 TB drive would fill up in a less than 11 minutes.
As mentioned by others, losses compression is an option without any reduction in picture quality, though at the expensive of high performance hardware needed for recording and rendering. Reply
JlHADJOE - Thursday, March 13, 2014 - linkYou pretty much have to do it during recording.
Encoding 4k RAW needs a ton of CPU that you might not have inside your camera, not to mention you probably don't want any lossy compression at that point because there's still a lot of processing work to be done. Reply
JlHADJOE - Friday, March 14, 2014 - linkHere's the Red Epic Dragon, a 6k 100fps camera. It uses a proprietary SSD array (likely RAID 0) for storage:
http://www.red.com/products/epic-dragon#features Reply
popej - Thursday, March 13, 2014 - link"idling (with minimal <0.05W power consumption)"
Where did you get this value from? I'm looking at your SSD reviews and clearly see, that idle power consumption is between 0.3 and 1.3W, far away form quoted 0.05W. What is wrong, your assumption here or measurements at reviews? Or maybe you measure some other value? Reply
Kristian Vättö - Thursday, March 13, 2014 - link<0.05W is normal idle power consumption in a mobile platform with HIPM+DIPM enabled: http://www.anandtech.com/bench/SSD/732
We can't measure that in every review because only Anand has the equipment for that. (requires a modified laptop). Reply
dstarr3 - Thursday, March 13, 2014 - linkHow does the bandwidth of a single SATAe SSD compare to two SSDs on SATA 6GB/s in Raid0? Risk of failure aside. Reply
Kristian Vättö - Thursday, March 13, 2014 - linkIn theory two SSDs in RAID 0 should achieve twice the bandwidth of one. In practice that's almost true and you should expect maximum bandwidth of around ~1060MB/s (vs 550MB/s with one SSD). Reply
Exodite - Thursday, March 13, 2014 - linkExternal power, and we might get it as a *!*%?1* molex?
Wake me up when we get to a usable revision. Reply
grahaman27 - Thursday, March 13, 2014 - linkMy thoughts exactly. I like sata, but this revision looks like a mess! Reply
invinciblegod - Thursday, March 13, 2014 - linkWhy did they do translation between pci-express and sata in the first place? Was it because in the event of a pci-super-express SATA can just make new chips and the current hard drives would be compatible (like from PCI to PCI-Express)? Reply
npaladin2000 - Thursday, March 13, 2014 - linkI wonder if M.2 is the better solution here, and could be adapted to serve the enterprise niches that SATAe is aiming for? After all, it provides the direct PCIe interface, and also provides power and is a small connector. Reply
SirKnobsworth - Thursday, March 13, 2014 - linkFor bigger, higher performance SSDs I think that actual PCIe cards are going to remain dominant. M.2 provides an x4 interface but the highest performance SSDs will have no trouble maxing that out. I think we may have already seen x8 cards demoed but I'm not sure. Reply
Veramocor - Thursday, March 13, 2014 - linkCould a internal motherboard USB header be used instead? USB 3.1 does about 10 Gpbs (with overhead) and would supply power. The cabling would be much cleaner.
Or an internal Thunderbolt 2.0 connection does 20 Gbps. Imagine a single internal wire supplying both power and data instead of the mess this looks like. It would beat the speed of everything save PCIe 3.0 x4. Reply
Kristian Vättö - Thursday, March 13, 2014 - linkUSB has massive overhead. USB 3.0 manages only around 280MB/s in real world, whereas the theoretical maximum is 625MB/s (5Gbps). That is over 50% overhead! Assuming similar overhead, USB 3.1 would do 560MB/s, which is inline with SATA 6Gbps. However, USB uses CPU a lot more, making it very inefficient.
As for Thunderbolt, it's basically just cabled PCIe. The difference is that TB requires expensive controllers and cabling to work, whereas PCIe alone is much cheaper.
I think SATA-IO just needs to get back to the drawing board and get rid of the external power requirement. PCIe supplies power, so there really shouldn't be need for more than that. Reply
phoenix_rizzen - Thursday, March 13, 2014 - linkJust make a PCIe x2 connector, stick it on a cable, and plug it between the drive and the mobo PCIe slot.
Then it's up to mobo makers to decide whether to just add PCIe x2 slots in the normal space (for use with either PCIe add-in cards or SATAe drives) or to add dedicated PCIe x2 slots over near the normal SATA slots for use with only SATAe drives. Reply
SirKnobsworth - Thursday, March 13, 2014 - linkWhy does it need to be attached with a cable? There are already PCIe form factor SSDs. If that takes up too much space then provide M.2 sockets on the motherboard. M.2 cards provide less area than 2.5" devices but that shouldn't be an issue for smaller SSDs, beyond which you really want more lanes anyway. Reply
phoenix_rizzen - Friday, March 14, 2014 - linkI was thinking more for the situation where you replace the current SATA ports on a mobo with PCIe x2 slots.
So you go from cabling your drives to the SATA ports to cabling your drives to the PCIe ports. Without using up any of the slots on the back of the board/case. Reply
SirKnobsworth - Saturday, March 15, 2014 - linkIf you don't want to use actual PCIe slots then have M.2 sockets on the motherboard. There's no reason to have another cabling standard. Reply
phoenix_rizzen - Monday, March 17, 2014 - linkThat works too, and is something I mention in another comment above.
This cable and connector doesn't make sense, any way you look at it. Reply
Kracer - Thursday, March 13, 2014 - linkAre you able to run any sort of PCI-Device over SATAe (GPUs, capture cards, etc.)?
Two lanes are not enough for GPU use but it would open up much more possibilities.
Are you able to use it as a boot device? Reply
The Von Matrices - Thursday, March 13, 2014 - linkI understand the desire for faster SSDs, but I still fail to see the purpose of SATA express over competing standards. There's nothing compelling about it over the competition.
M.2 already provides the PCIe x2 interface and bandwidth (albeit without the ability to use cables).
Motherboards that support PCIe 3.0 SATA Express without either a high priced PCIe switch or compromising discrete graphics functionality are one to two years away.
SF3700 is PCIe 2.0 x4, meaning that SATA express can only use half its performance and PCIe x4 cards will still be the enthusiast solution.
NVMe can already be implemented on other standards.
The cables are bulky, which is unusual considering that SAS at 12Gb/s (which is available) is using the same small connectors as 6Gb/s. Reply
SirKnobsworth - Thursday, March 13, 2014 - linkM.2 provides a PCIe x4 interface in certain configurations. I think the SATAe specification has the provision for adding another two lanes at some point in the future but that's not going to happen for a long time. Reply
Kevin G - Thursday, March 13, 2014 - linkSATAe and NVMe is fast and important for expandable IO. However I believe that it will be secondary over the long term. I fathom that the NAND controller will simply move on-die for mobile SoCs. The reason for this will be power savings, lower physical area and performance reasons. Some of the NVMe software stack will be used here but things like lane limitations will be entirely by-passed since it all on die. Bandwidth would scale by the number of NAND channels. Power savings will come from a reduction in an external component (SATAe controller and/or external chipset) and the ability to integrate with the SoC's native power management controller. Desktop versions of these chips will put the NAND on a DIMM form factor for expansion.
The SATAe + NVMe will be huge in the server market though. Here RAS plays a bigger role. Features like redundancy and hotswap are important, even with more reliable SSD's compared to their hard drive predecessors. I eventually see a backplane version of a connector like mSATA or M.2 replacing 2.5" hard drives/SSD in servers. This would be great for 1U servers as they would no longer be limited to 10 drives. The depth required on a 1U server wouldn't be as much either. PCIe NVMe cards will fill the same niche today: radically high storage bandwidth at minimal latencies.
One other thing worth pointing out is that since Thunderbolt encapsulates PCIe, using external SATAe storage at full speed becomes a possibility. Working in NVMe mode is conceptually possible over Thunderbolt too. Reply
xdrol - Thursday, March 13, 2014 - linkParallel ATA is back, just look at the cable size.. Reply
JDG1980 - Thursday, March 13, 2014 - linkA ribbon cable *plus* a Molex? Oh, goody. This looks like a massive step backward. Reply
sheh - Thursday, March 13, 2014 - linkWho doesn't love them flatcables? Reply
SirKnobsworth - Thursday, March 13, 2014 - linkWe have both eSATA and SATAe now. This is going to be fun... Reply
sheh - Thursday, March 13, 2014 - linkSadly eSATA isn't that common. Reply
kwrzesien - Wednesday, April 30, 2014 - linkSATAe won't be either. Reply
fokka - Thursday, March 13, 2014 - linkthis is cable design straight from hell. an ide connector is more attractive than this. Reply
tspacie - Thursday, March 13, 2014 - linkOh, please let there be a full review of that Plextor M6e in the near future. I have a computer with no 6Gbps SATA ports, but plenty of PCIe slots just desperate for faster storage. Reply
Gc - Thursday, March 13, 2014 - linkTheSSDReview has looked at a Plextor M6e a couple times now with different host cards.
http://www.thessdreview.com/our-reviews/ioswitch-r... Reply
Kristian Vättö - Friday, March 14, 2014 - linkIt's coming ASAP. I've had the drive for ~2 months now but unfortunately there have been issues with testing (it's the first PCIe drive I'm testing). The drive runs in PCIe 1.0 (i.e. ~350MB/s max) if it's connected to a PCIe 2.0 slot and my motherboard doesn't offer the option to force certain PCIe mode, so I've been waiting for a firmware update to fix this. Similarly, some of our benchmarks don't like the combination of PCIe SSDs and our new testbed and we are still in the process of figuring those issues out. As soon as I'm sure the drive is operating as it should, I'll start working on the review :) Reply
tspacie - Friday, March 14, 2014 - linkThanks for doing all the leg work! Reply
bj_murphy - Thursday, March 13, 2014 - linkCould you clarify what you mean by "half height/length PCIe" when you are speaking about the 4 major form factors of flash storage on the final page? Isn't that the exact same connector as mSATA or am I thinking of something else? Reply
sheh - Thursday, March 13, 2014 - linkhttp://en.wikipedia.org/wiki/MSATA#mSATA
Same connector as mPCIe, different signals. Reply
SunLord - Thursday, March 13, 2014 - linkI like the idea but they should of rolled there own custom connector not twist the sata connector to meet there needs it's looks stupid. A custom high density connector and cable designed specifically for its task would make far more sense then this hodgepodge but I guess they need to cut comers to "keep costs down" on something already aimed at the high end which is even stupider. A nice clean high density interface with an sata adpater would of been far better. Reply
androticus - Thursday, March 13, 2014 - linkUgh. What an immensely cumbersome and kludgy design. Reply
asuglax - Thursday, March 13, 2014 - linkKristian, I completely agree with your final thoughts. I would actually take it a step further and say that Intel should completely do away with the DMI interface and corresponding PCH; they should limit the I/O off the processor to as many as possible PCI-e lanes, 3 DisplayPort (which can be exposed as dual-mode), and however many memory channels. Enterprise could have QPI, additionally. I would like to see I/O controllers embedded into the physical interconnects where PCI-e could be routed to the interconnects and however many USB, SATA, or other connections could be switched and exposed through the devices (I supposed it could be argued that this could be a PCH in itself, only connected through PCI-e instead of DMI). Security protection measures (such as TPM's functionality) should be built-in to all components and, while being independently operative, be able to communicate with one-another through the presented I/O channels. Reply
fteoath64 - Saturday, March 15, 2014 - link@asuglax: Intel is known and has done this. Provide small incremental adds to the processor and chipset features so they can provide as many iterations of SKUs as they can over a period of time. If they do a radical change, then they risk not being able to manage the incremental changes they wanted. It is a strategy to allows for a large variety of product units, hence expanding the market for themselves. Lately, you see that they have reduced the number of CPU skus while expanded the mobile mobile skus. This is possible since in both market segments they are the majority leader and allows them to maximise profits with minimal changes to production. It is a different strategy for AMD and a completely different one yet for the Arm SoC vendors. Intel's strategy seems like it is coercing the market to move to a place and pace they wanted. The Arm guys just give their best shot on every product they have so we got a lot more than we paid for.
You just cannot teach an old dog new tricks. Reply
Babar Javied - Thursday, March 13, 2014 - linkThis SATA 3.2 really doesn't make a lot of sense to me and others also seem to agree from when I've read in the comments. Is this supposed to be a temporary thing or the middle man before we get to the good stuff? like SATA 4.0, is that the reason why it's called SATA 3.2?
So here is a genuine question. Why not just use Thunderbolt? It is owned by intel and they can implement it into their next chipset(s). Also, Thunderbolt uses PCIe lanes so it is plenty fast without wasting lanes. Sure, the controller and cables are expensive but once it starts to be mass produced they should come down as is common with electronics.
It seems to me that SATA is going though a lot of trouble to bring 3.2 when it is only marginally better. I also get the feeling that SSDs are going to get even faster by using more channels (current standard is 8) and NAND chips (current standard is 16) as they become the new standard in storage. Of course the transition from HDD to SDD is not going to happen overnight but it is going to happen and I get the feeling that the 750MB/s is going to become a bottleneck very quickly.
And finally, by switching to Thunderbolt, we also help kickstart the adoption of this standard and hopefully see it flourish. Allowing us to daisy chain monitors, storage drives (SSDs and HDDs), external graphic cards and so much more. Reply
SirKnobsworth - Thursday, March 13, 2014 - linkThere's no point to implementing Thunderbolt internally, which is what SATAe is for. For external purposes you can already buy Thunderbolt SSDs. Reply
SittingBull - Thursday, March 13, 2014 - linkI don't feel like you have proven that there is any need for these faster hard drive interfaces, as you hoped to in the title of your article. The need for, let alone the desire for, higher resolution video is anything but proven by anyone that I know of. 4k video offers only dubious benefits, as only very large displays can show the difference between it and 1080p, ie., 70 or 80 inches! The wider colour gamut would be nice but is not really compelling, and those are the only benefits I am aware of. I seriously doubt that the TV or electronics industry are going to be able to sell the 4k idea to the public as a whole. Even 720p is not shown to be lacking until we get into displays larger than 50 inches.
It is always nice to read up on the tech of the future and I thank you for explaining the SATAe and other interfaces that are in the works. Eventually these advances will be implemented but I can't see it happening until there is some sort of substantial demand, and your entire article is built on the premise that we will need the bandwidth to support 4k video quite soon. But we don't ... :( Reply
BMNify - Sunday, March 16, 2014 - linkSittingBull , perhaps you should stick your head out of the Native American Law Students offices and look to your alumni of the Indian Institute of Science for inspiration in the tech world today,
given that its clear and public knowledge that the NHK/ BBC R&D years of UHD development http://www.bbc.co.uk/rd/blog/2013/06/defining-the-... and now ratified by the International Telecommunication Union are the minimum base for any new Soc design to adhere to and comply with IF they want to actually reuse their current UHD IP for the longest time scales...
the main point is if the PR are not trying to cover up by acts of omission the fact they don't actually comply with the new Rec. 2020 real colour space is better colour coverage due to using 10bits per pixel for UHD-1 consumer grade panels and later UHD-2 12bit grade panels for the 8192×4320 [8K] consumer in 4 years or so.
to put it simply, antiquated Rec. 709 (HDTV and below) 8bit pseudocolor color = only 256 bands of usable colour.
Rec. 2020 real colour space 10bits per pixel= 1000+ bands of usable colour so you get far less banding in lower bit rate encodes/decodes and more compression for a given bit rate so a better higher visual quality at smaller size.
as it happens, NHK announced they are to give another UHD-2/8K 3840 pixels wide by 2160 pixels high Broadcast Demo at the coming NAB Show,"Japanese public broadcaster NHK is planning to give a demonstration of "8K" resolution content over at single 6MHz bandwidth UHF TV channel at the National Association of Broadcasters (NAB) Show coming up in Las Vegas, Nevada, April 5 to 10."
In order to transmit the 8K signal, whose raw data requirement is 16 times greater than an HDTV signal, it was necessary to deploy additional technologies These include ultra multi-level orthogonal frequency domain multiplex (OFDM) transmission and dual–polarized multiple input multiple output (MIMO) antennas. This was in addition to image data compression. The broadcast uses 4096-point QAM modulation and MPEG-4 AVC H.264 video coding.
we could also have a debate about how qualcomm and other cortex vendors might finally provide the needed UHD-2 data throughput and far lower power with ether integrated JEDEC Wide IO2 25.6GBps/51.2GBps or Hybrid Memory Cube 2.5D interposer-based architectures,and using MRAM inline computation etc.
did you notice how the ARM SoC with its current NoC (network On Chip) can already beat today's QPI real life data throughput (1Tb/s,2Tb/s etc) at far lower power,never mind the slower MCI as above, they only need to bring that NoC capability to the external interconnect to take advantage of it in any number of IO ports Reply
Popskalius - Friday, March 14, 2014 - linkI haven't even taken my Asus z87 Plus out of its shrink wrap and it's becoming obsolete. Reply
SittingBull - Friday, March 14, 2014 - linkI just put together my own system with an Asus Z87 Plus mb, an i7 4770k, 16 GB of RAM and an SSD. It is not and will not be obsolete anytime in the near future, ie., at least 3 years. Worry not. There isn't anything on the horizon our systems won't be able to deal with. Reply
willis936 - Friday, March 14, 2014 - linkA 4.5GHz 4770k doesn't render my video, crunch my matlab, and host my minecraft at arbitrarily amazingly fast speeds, but it's a big step up from a Q6600 :p Reply
MrBungle123 - Friday, March 14, 2014 - linkThat cable looks horrible, I'd rather them just move SSD's to a card. Reply
TEAMSWITCHER - Friday, March 14, 2014 - linkSecond That! Hardware makers need to abandon SATA Express and start working on new motherboard form factors that would allow for attaching the flash drives directly to the motherboard. SATA Express is another compromised design-by-committee. Just what the struggling PC industry needs right now! Jeepers!!! Reply
iwod - Friday, March 14, 2014 - linkThe future is Mobile. Where Laptop already overtook Desktop in numbers. So why another chunky ugly old hack for SSD? Has Apple not taught them a lesson where Design matters?
And the speed, It is just too slow. We should at least be at 16Gbps, and since any of these standard aren't even coming out fast enough i would have expected the interface to leap to 32Gbps. Plenty of headroom for SSD Controller to improve and work on. And Intel isn't even bundling enough PCIe Lanes direct from CPU.
Why cant we build something that is a little future proof? Reply
willis936 - Friday, March 14, 2014 - linkCost matters. The first thing they'll tell you in economics 101 is that we live in a world with finite resources and infinite wants. There's a reason we don't all have i7 processors, 4K displays, and 780 GPUs right now. Thunderbolt completely missed it's window for adoption because the cost vs. benefit wasn't there and OEMs didn't pick it up. The solutions will be made as the market wants it. The reason the connector is an ugly hack is so you can have the option for high bandwidth single drives or multiple slower drives. It's not pretty and I'd personally like to just see it as a phy/protocol stack that uses the PCIe connector with some aneg to figure out if it's a SATAe or PCIe device but that might cause problems if PCIe doesn't handle things like that already.
Your mobile connector will come, or rather is already here. Reply
dszc - Saturday, March 15, 2014 - linkThanks Kristian. Great article.
I vote for PCIe / NVMe / M.2. SATAe seems like a step in the wrong direction. Time to move on. SATA SSDs are great for backward compatibility to help a legacy system, but seem a horrible way to to design a new system. Too big. Too many cables. Too much junk. Too expensive. SATAe seems to be applying old thinking to new technology. Reply
watersb - Sunday, March 16, 2014 - linkI don't get the negative reactions in many of the comments.
Our scientific workloads are disk-IO bound, rather than CPU-bound. The storage stack is ripe for radical simplification. SATAe is a step in that direction. Reply
rs2 - Sunday, March 16, 2014 - linkThis will never fly. For one thing the connectors are too massive. Most high-end mainboards allow 6 to 8 SATA drives to be connected, and some enthusiasts use nearly that many. That will never be possible with the SATAe connector design; there's just not enough space on the board.
And the consuming 2 PCI-E lanes per connector is the other limiting factor. It's a reasonable solution when you just need one or two ports. But in the 8-drive case you're talking about needing 16 extra lanes. Where are those meant to come from? Reply
willis936 - Sunday, March 16, 2014 - linkHow many ssds do you plan to use at once? I can't think of a single use case where more than one ssd is needed, or even wanted if bandwidth isn't an issue. One ssd and several hard drives is certainly plausible. So there are 6 instead of 8 usable ports for hard drives. How terrible. Reply
Shiitaki - Monday, March 17, 2014 - linkSo exactly what problem is this fixing? The problem of money, this is a pathetically attempt at licensing fees. SSD manufacturers could simply change the software and have their drives appear to the operation system as a pci-e based sata controller with permanently attached drive TODAY. It would her genius to be able to plug a drive into a slot and be done with it. We don't need anything new. We already have m-pci-e. Moving to a m-pci-ex4 would have been a better idea. The you could construct backplances with the new m-pci-ex4 connectors that aggrate and connect to a motherboard using a lci-ex8/16 slot.
This article covers the story of a organization fighting desperately to not disappear into the history books of the computer industry. Reply
Kristian Vättö - Tuesday, March 18, 2014 - linkBear in mind that SATA-IO is not just some random organization that does standards for fun - it consists of all the players in the storage industry. The current board has members from Intel, Marvell, HP, Dell, SanDisk etc... Reply
BMNify - Thursday, March 20, 2014 - linkindeed, and yet its now clear these and the other design by committee organization's are no longer fit for purpose , producing far to little far to late....
ARM IP =the generic current CoreLink CCN-508 that can deliver up to 1.6 terabits of sustained usable system bandwidth per second with a peak bandwidth of 2 terabits per second (256 GigaBytes/s) at processor speeds scaling all the way up to 32 processor cores total.
Intel IP QPI = Intel's Knights Landing Xeon Phi due in 2015 with its antiquated QPI interconnect and its expected ultra short-reach (USR) interconnection only up to 500MB/s data throughput seems a little/lot short on real data throughput by then... Reply
Hrel - Monday, March 17, 2014 - linkCost: Currently PCI-E SSD's are inexplicably expensive. If this is gonna be the same way it won't sell no matter how many PCI-E lanes Intel builds into it's chipset. My main concern with using the PCI-E bus is cost. Can someone explain WHY those cost so much more? Is it just the niche market or is there an actual legitimate reason for it? Like, PCI-E controllers are THAT much harder to create than SATA ones?
I doubt that's the case very much. If it is then I guess prices will drop as that gets easier but for now they've priced themselves out of competition.
Why would I buy a 256GB SSD on PCI-E for $700 when I can buy a 256GB SSD on SATA for $120? That shit makes absolutely no sense. I could see like a 10-30% price premium, no more. Reply
BMNify - Tuesday, March 18, 2014 - link"Can someone explain WHY those cost so much more?"
due mostly to not invented here is the reason we are not yet using a version of everspin's MRAM 240 pin, 64MByte DIMM with x72 configuration with ECC for instance http://www.everspin.com/image-library/Everspin_Spi...
it can be packaged for any of the above forms M2 etc too rathe than have motherboard vendors put extra ddr3 ram slots decicated to this ddr3 slot compatable everspin MRAM today with the needed extra ddr3 ram controllers included in any CPU/SoC....
rather than licence this existing (for 5 years ) commercial MRAM product and collaborate together to make and improve the yield and help them shrink it down to 45nm to get it below all of today's dram fastest speeds etc they all want an invented here product and will make the world markets wait for no good reason... Reply
Kristian Vättö - Tuesday, March 18, 2014 - linkBecause most PCIe SSDs (the Plextor M6e being an exception) are just two or four SATA SSDs sitting behind a SATA to PCIe bridge. There is added cost from the bridge chip other additional controller, although the main reason are the laws of economics. Retail PCIe SSDs are low volume because SATA is still the dominant interface and that increases production costs for the OEMs. Low order quantities are also more expensive for the retailers.
In short, OEMs are just trying to milk enthusiasts with PCIe drives but ones we'll see PCIe entering the mainstream market, you'll no longer have to pay extra for them (e.g. SF3700 combines SATA and PCIe in a single chip, so PCIe isn't more expensive with it). Reply
Ammohunt - Thursday, March 20, 2014 - linkDisappointed there wasn't a SAS offering compared 6GB SAS != 6G SATA Reply
jseauve - Thursday, March 20, 2014 - linkAwesome computer Reply
westfault - Saturday, March 22, 2014 - link"The SandForce, Marvell, and Samsung designs are all 2.0 but at least OCZ is working on a 3.0 controller that is scheduled for next year."
When you say OCZ is developing on a PCIe 3.0 controller do you mean that they were working on one before they were purchased by Toshiba, or was this announced since they were acquired by Toshiba? I understand that Toshiba has kept the OCZ name, but is it certain that they have continued all R&D from before OCZ's bankruptcy? Reply
dabotsonline - Monday, April 28, 2014 - linkRoll on SATAe with PCIe 4.0, let alone 3.0 next year! Reply
MRFS - Tuesday, January 20, 2015 - linkI've felt the same way about SATAe and PCIe SSDs --
cludgy and expensive, respectively.
Given the roadmaps for PCIe 3.0 and 4.0, it makes sense to me, imho,
to "sync" SATA and SAS storage with 8G and 16G transmission clocks
and the 128b/130b "jumbo frame" now implemented in the PCIe 3.0 standard.
Ideally, end users will have a choice of clock speeds, perhaps with pre-sets:
6G, 8G, 12G and 16G.
In actual practice now, USB 3.1 uses a 10G clock and 128b/132b jumbo frame:
max headroom = 10G / 8.25 bits per byte = 1.212 GB/second.
132 bits / 16 bytes = 8.25 bits per byte, using the USB 3.1 jumbo frame
To save a lot of PCIe motherboards, which are designed for expansion,
PCIe 2.0 and 3.0 expansion slots can be populated with cards
which implement 8G clocks and 128b/130b jumbo frames.
That one evolutionary change should put pressure on SSD manufacturers
to offer SSDs with support for both features.
Why "SATA-IV" does not already sync with PCIe 3.0 is anybody's guess.
We tried to discuss this with the SATA-IO folks may moons ago,
but they were quite committed to their new SATAe connector. UGH! Reply


text:
Join as a member. There's a certificate with your name on it.
If you want a theme for your charity purpose, ST Fiddle is particularly suitable. This theme is one of the most downloaded free Drupal themes provided by Symphony Themes. We upload this theme to Drupal.org so it reaches more people.
Sponsored by Symphony Themes
Live Demo
Please see our live demo here: http://demo.symphonythemes.com/drupal7/fiddle/
Install profile
The install profile is the quickest way to get this theme on a working Drupal site. All are built for you, exact as the demo.
Download the install profile.
This theme is a sub theme of Omega. If you don't use the install profile, please download and install Omega prior to installing this theme. Remember to use Omega 3 (7.x-3.x) as this theme is not yet compatible with Omega 4.
Project Information
- Maintenance status: Actively maintained
- Development status: Under active development
- Reported installs: 52 sites currently report using this theme. View usage statistics.
- Downloads: 4,126
- Last modified: 1 December 2014
- Stable releases for this project are covered by the security advisory policy.
Look for the shield icon below.
|tar.gz (398.8 KB) | zip (428.54 KB)

subset: commoncrawl


text:
Chris Martin Of Coldplay Performs Private Show In NYC {Video}
When you're the frontman in one of the biggest bands on the planet, you don't often get to play small intimate shows. Well, that's exactly what Chris Martin of Coldplay did last night for approximately 200 fans. The location was not announced in advance or the place would have been more of a zoo than it was. We took the train in, had a nice dinner then walked over to the show. Before Chris took the stage we had a chance to head backstage and meet him. What a nice guy! Pictures coming soon, but here's some footage of him performing "Sparks". Enjoy!
Subscribe to WRRV on


text:
Experienced (non manager) Administration jobs in Cranbrook
Found 0 jobs
We do have the following jobs available for Administration, Experienced (non manager)
Showing 1 - 3 of 296
Training Manager
You will be undertaking a range of clerical, administrative and general tasks and providing comprehensive support.
Attendance and Inclusion Clerk
To maintain and conduct the Academy's admissions and attendance procedures and provide administration support to the Inclusion Team.
An exciting opportunity has arisen to join our support service in Birmingham as an administrator.
Related courses
Complete Microsoft Office Diploma - 6 CPD Diplomas in 1 - Best Seller - *NUS Extra Card...
Take this fantastic course and as a Guardian user you will receive a 85% discount - use code - GUARD85
Admin, Secretarial & PA Diploma – CPD certified and IVCAS Accredited
Take this fantastic course on Admin, Secretarial & PA and as a Guardian user you will receive a 85% discount - use code: GUARD85
Foundation Certificate in Higher Education
Enhance and update your English, Maths and study skills in order to study at a higher education level and progress your career.


text:
England winger Josh Charnley will be out for up to two months with a knee injury sustained in Wigan's Challenge Cup win over Dewsbury.
Chorley's Charnley, who has topped the Super League try-scoring chart for each of the last two seasons, twisted his knee in the early stages of the Warriors' 58-6 win over the Rams.
"Josh is going to be out for six to eight weeks," (Warriors head coach Shaun) Wane said. "He doesn't need an operation but needs time off his legs. He's slightly twisted his knee but there's no ligament damage."
Reserve winger Dom Manfredi is set to deputise, starting with Friday's home game against London Broncos, who have yet to win a game in 2014, and Wane admits he is tempted to rest some of his senior players ahead of the Easter schedule.
"I'll pick a very competitive team," Wane said. "We've had a few tough games this year so, if I need to rest someone before the Good Friday game at St Helens, I will.
"I've not made my mind up yet."


text:
Assessment |
Biopsychology |
Comparative |
Cognitive |
Developmental |
Language |
Individual differences |
Personality |
Philosophy |
Social |
Methods | Statistics | Clinical | Educational | Industrial | Professional items | World psychology |
Psychology: Debates · Journals · Psychologists
The International Council of Psychologists is a long established international organization that seek to promote links between psychologists in different countries and to promote the work of the discipline around the world.
See alsoEdit
- International psychology
- International Union of Psychological Science
- International Association of Applied Psychology (IAAP),
- International Association of Cross-Cultural Psychology (IACCP)
- Cautley, P. W. (1992). Fifty years of the International Council of Psychologists.
- Davis, J. M. (2004). The International Council of Psychologists. In A. E. Kazdin (Ed.), Encyclopedia of psychology. Washington, DC: American Psychological Association and Oxford University Press.
- Gielen, L. L. Adler, & N. A. Milgram (Eds.), Psychology in International Perspective:
Fifty Years of the International Council of Psychologists (pp. 3-18). Amsterdam:
- Portenier, L. G. The International Council of Psychologists Incorporated: The first quarter-century, 1942-1967. International Council of Psychologists.


text:
The final resting place of the cougar shot last week in Roscoe Village may be far from his home, but at least he will be among relatives.
A cousin found in 1961 in Surinam. A puma from Peru, 1955. And the skin of a Florida panther from 1895, cataloged by legendary zoologist Charles B. Cory.


text:
U.S. Department of Transportation
Federal Highway Administration
1200 New Jersey Avenue, SEWashington, DC 20590
Home / Briefing Room / Speeches & Testimony
Briefing Room
Subscribe to FHWA Press Releases
Chairman Duncan, Ranking Member DeFazio, and Members of the Subcommittee, thank you for the invitation to appear before you today to discuss accelerating project delivery. One lesson we have learned from the American Recovery and Reinvestment Act is the importance of bringing a greater sense of urgency to our work, and the Federal Highway Administration (FHWA) is committed to helping the highway community deliver projects more quickly. We understand that the longer it takes to deliver a project, the more the project ultimately will cost, and the longer the public will have to wait to enjoy the project's benefits. And, as President Obama has indicated, maintaining and improving our infrastructure is vital to our economic competitiveness and the ability to create good jobs. If we are going to "win the future," as the President says, we are going to have to out-innovate, out-educate and out-build the rest of the world.
There are opportunities to reduce project delivery time while continuing to maintain and enhance the environment and project quality. Today, I will share with you some of the strategies FHWA is employing under my Every Day Counts (EDC) initiative and the Safe, Accountable, Flexible, Efficient Transportation Equity Act: A Legacy for Users (SAFETEA-LU) to maintain and improve project quality and improve project delivery times.
Since the passage of SAFETEA-LU, we have seen some progress in shortening project delivery time. However, much work remains if we are to meet the major transportation challenges of the 21st century—economic challenges, safety challenges, congestion challenges, and environmental challenges.
It is a commonly held perception that it takes an average of 13 years to deliver a major highway project from planning through completion. I know firsthand that major projects can be completed faster. When I served as Director of the Arizona Department of Transportation, we built the Regional Freeway System in the Phoenix area 6 years ahead of schedule and consistently delivered statewide construction programs on time.
We need to work more efficiently. The public wants greater accountability in how we spend their money, enhanced safety on our roadways, and a transportation system that helps support our economy and sustain our environment. To that end, I launched an initiative called Every
Day Counts to shorten project delivery time and to speed the deployment of new and proven technologies into the marketplace. Every Day Counts is an innovation initiative that presents new technologies, new ideas and new ways of thinking. Ultimately, it provides the transportation community with a better, faster, and smarter way of doing business. EDC is about taking a select number of effective, proven processes and market-ready technologies and getting them into widespread use. Both can have a direct impact on shortening project delivery and cost avoidance. All processes and techniques associated with EDC are permitted under current statute and regulations.
In launching the Every Day Counts initiative, I looked at the range of challenges we face today as a society and a transportation community. Without exception, I believe the best way to meet those challenges is through innovation.
Consider the budget constraints that governments at all levels are facing. We are compelled to deliver the best value for every taxpayer dollar. We can meet that challenge by becoming more innovative in the way we deliver projects, so they are completed faster and the public can realize their benefits sooner.
Safety—Secretary LaHood's top priority at DOT —is clearly enhanced by innovation. The Nation has made tremendous progress in reducing traffic deaths to historic lows, but we still have work to do. By delivering better-designed roads to the public sooner, we can help make travel safer. And by making greater use of innovative technologies like the Safety Edge, which makes it easier to steer a vehicle safely back on the road, we will be able to save more lives. Safety Edge is one of the new technologies we are recommending to State and local transportation agencies for rapid deployment.
We must also find ways to meet the public demand for reduced congestion, a cleaner environment, and less energy consumption. These goals, too, are advanced through EDC. Getting projects completed sooner helps reduce congestion and improve air quality. Making greater use of technologies—like assembling bridges from prefabricated elements—allows critical parts of our infrastructure to be built with much less disruption to the traveling public. There are also benefits to be found in new road-building materials that improve the quality of water runoff and new technologies like warm-mix asphalt, which can be produced and placed on the road at lower temperatures, resulting in significant cost and energy savings.
Finally, it is critical that we have an infrastructure system that allows our economy to grow and compete, especially with such economic powers as China and emerging ones like Brazil. That means keeping the infrastructure we have in a state of good repair and providing new infrastructure as quickly and efficiently as possible.
I am pleased that EDC enjoys the strong support of the American Association of State Highway and Transportation Officials (AASHTO), the American Road & Transportation Builders Association, the Associated General Contractors of America, the National Association of County Engineers, and many other organizations. These organizations and others have helped shape EDC with their ideas and their commitment.
We introduced the basic concepts behind EDC more than a year ago. Late last year, in partnership with AASHTO, we held a series of 10 regional summits to present EDC initiatives to our State and local partners, Federal regulatory agencies, and the private sector, including many contractors and consultants. Each summit included delegates from several States. A total of nearly 1,000 transportation professionals attended the summits to discuss how the initiatives could accelerate project delivery and get important technology deployed sooner.
We have built EDC on two pillars. First, we have a toolkit that includes a number of specific strategies to shorten project delivery time. This toolkit includes initiatives for using existing flexibilities in the law and not duplicating efforts in the planning and environmental review process. We also recommend a number of innovative contracting practices.
The toolkit presents approaches for addressing what we have identified as frequently-cited problem areas. In addition to presenting these options, FHWA is playing an active leadership role in helping the people who actually deliver projects—States, metropolitan planning organizations, contractors—understand and accept these practices and technologies. We hope that EDC will help foster a culture of innovation within the highway community and that many of these strategies will become common practice as decision makers are provided with information regarding the benefits of applying these strategies.
This initiative establishes a framework for considering and incorporating planning documents and decisions from the earliest stages of project planning into the environmental review process. It represents an approach to transportation decision-making that takes environmental, community, and economic information collected early in the planning stage and carries it through project development, design, and construction. This can lead to a seamless decision-making process that minimizes duplication of effort, promotes environmental stewardship, and reduces delays in project implementation.
Decisions made early in planning and project development play a substantial role later in the environmental review process. Consultation with FHWA environmental attorneys at early decision points can help decision makers save time and costs by avoiding problems that could negatively affect the legal sufficiency of NEPA and section 4(f) documents. This initiative is also identifying the most common problems in document development, their root causes, and the measures preparers can take to avoid the problems.
Programmatic agreements establish a streamlined process for handling routine environmental requirements for commonly encountered project types. For example, a merger process like the longstanding agreement in North Carolina enables agencies to fulfill the requirements of section 404 of the Clean Water Act and NEPA concurrently. The continued and expanded use of programmatic agreements, where process reviews and permit application procedures have been standardized and agreed upon, has been very effective in saving time. When prior agreements exist for avoiding, minimizing, and mitigating impacts, projects are reviewed more quickly and trust is developed that results in improved relationships between State DOTs and regulatory agencies. The goal of this initiative is to identify and assist in the expansion of new and existing programmatic agreements to a regional or national level.
In December 2010, FHWA, the New Mexico Department of Transportation, the Advisory Council on Historic Preservation, and the New Mexico State Historic Preservation Office signed a programmatic agreement to address expeditiously project effects in accordance with section 106 of the National Historic Preservation Act. This agreement provides for appropriate tribal consultation as well as public participation and minimization of extraneous documentation. It also reduces case-by-case review when historic properties will not be affected or when standard protocols and treatments can be applied. The update of this agreement is an important tool in the efforts to continue to shorten project development.
In projects that will impact waters of the United States, the permitting process under section 404 of the Clean Water Act is an important part of the project development process. The toolkit encourages use of in-lieu fees and mitigation banking where appropriate and allowed under existing statutes, FHWA regulations, State laws, and court decisions. Generally, mitigation banks and in-lieu fee programs provide for mitigation on a larger ecological scale, which is funded by multiple (transportation and non-transportation) projects. In some cases, this approach can save time and support expedited project delivery.
For example, North Carolina has developed an Ecosystem Enhancement Program (EEP) that is recognized as a national model for wetlands mitigation. The EEP's mitigation program addresses environmental impacts proactively, not reactively. Each year, the North Carolina Department of Transportation (NCDOT) provides EEP with an updated list of its 7-year program of construction projects, along with each project's estimated wetland and stream impacts. Funds are invested in environmental protection ahead of the date the impact will occur. Prior to the creation of the EEP, up to 40 percent of NCDOT projects were delayed due to compensatory mitigation problems. Since the inception of the EEP, no NCDOT projects have been delayed due to a lack of compensatory mitigation.
This initiative clarifies which design work meets the criteria as preliminary design and is allowable under current law prior to NEPA completion regardless of contracting mechanism. This initiative also develops guidance to allow this work to be done consistently in all project delivery mechanisms. Implementation of this initiative through our guidance promotes concurrent processes in a manner that does not prejudge environmental analysis under NEPA.
The Right of Way (ROW) process is currently a major part of the project development and implementation processes. This initiative is based on flexibilities allowed under existing regulations and statutes. Significant time savings can be achieved by employing flexibilities already provided for in statute and FHWA regulations. This initiative underlines opportunities for improved coordination of ROW activities with other key project development actions in preliminary design; land acquisition for utilities accommodation and relocation project activities; mitigation for unavoidable environmental impacts; and a number of other areas where streamlined approaches may prove beneficial.
The often-conflicting priorities of State transportation agencies and utility companies can adversely affect the timely completion of transportation projects. Potential utility conflicts exist on most transportation projects. It is estimated that half of all highway and bridge projects eligible for Federal funding involve the relocation of utility facilities, and construction generally takes longer and costs more when utilities need to be relocated. This initiative spotlights existing flexibilities currently in place under Federal law and regulations and describes techniques that foster effective utility coordination during project development and warrant more widespread use.
This initiative provides additional FHWA technical assistance to identify major challenges on ongoing EIS projects and implement solutions to resolve project delays where feasible. Candidate projects ideally include projects where 60 months have elapsed since issuance of the Notice of Intent without issuance of a Record of Decision. FHWA teams focus on facilitating interagency coordination and collaboration to resolve outstanding issues and provide peer-to-peer activities, workshops, training, or specialized on-site assistance.
The Accelerated Project Delivery Methods (APDMs) initiative focuses on the construction phase of a project using methods like Design-Build (DB) and Construction Manager/General Contractor (CM/GC), which have proven to shave years off project schedules in some cases. We are confident that by using APDMs, State DOTs can deliver projects 50 percent faster.
Traditionally, a project is designed, put out for bid to construction firms, and then built by the winning bidder (design-bid-build). With DB, the design and construction phases are combined into one contract, eliminating the separate bid phase and allowing certain aspects of design and construction to take place at the same time. This can provide significant time savings compared with the design-bid-build approach. With DB project delivery, the designer-builder assumes responsibility for the majority of the design work and all construction activities. This provides the designer-builder with increased flexibility to be innovative, along with greater responsibility and risk.
In addition to the time savings, a DB contract provides savings in cost and improvement in quality. Cost savings are realized by transferring many of the construction engineering and inspection costs from the contracting agency to the designer-builder. The arrangement also results in fewer change orders or claims for errors or delays. Finally, the ongoing involvement of the design team throughout the process puts a greater focus on quality control and assurance and allows better coordination between the needs of the project and the contractor's capabilities.
Construction Manager/General Contractor occupies the middle ground between the traditional design-bid-build approach and DB. In a general CM/GC scenario, the project owner hires a general contractor to serve as the construction manager and to provide the owner with constructability, pricing, and scheduling information during the design phase. As the design phase nears completion, if the owner and construction manager are able to agree on a price for construction, they sign a construction contract and the construction manager becomes the general contractor. CM/GC allows State DOTs to remain active in the design process while assigning risks to the parties most able to mitigate them. As with the DB approach, there are potential time savings because of the ability to undertake a number of activities concurrently. This approach provides several other additional benefits, including: increased partnership and team building, which fosters an environment where innovation can be nurtured, rewarded, and flourish; potential for lower project costs, primarily due to risk identification and allocation during early project development; and enhanced cost certainty at an earlier point in design because of real time costing information inherent to CM/GC. Because FHWA does not have general authority to permit CM/GC on a general basis, CM/GC projects under the Federal-aid highway program are carried out under FHWA's Special Experimental Project No. 14 (SEP-14).
Utah DOT (UDOT) used this innovative contracting method to reconstruct 15 bridges and widen Interstate 80. CM/GC allowed UDOT to reduce the project schedule from 3 years to 2 years. By working with the general contractor throughout the design process, UDOT was able to take advantage of the contractor's resources, design the most efficient scope for the project goals, and meet quality and public expectations for maintenance of traffic. UDOT has estimated direct savings for 7 of its larger projects to be $13.8 million, with estimated user cost savings of $289 million.
Our second pillar of EDC provides outreach and education to the highway community on 5 technologies that we believe should be widely deployed into the field today: warm-mix asphalt, prefabricated bridge elements and systems, adaptive signal control technology, the Safety Edge, and geosynthetic reinforced soil. Every Day Counts is not about inventing the next "big thing"—it is about taking effective, proven and market-ready technologies and ensuring their widespread use. By advancing these 21st century solutions, we can accelerate project delivery, improve safety, reduce congestion, and keep America moving and competitive.
Warm-Mix Asphalt (WMA) is the generic term for a variety of technologies that allow asphalt to be produced and then placed on the road at lower temperatures than the conventional hot-mix method. WMA production occurs at temperatures ranging from 30 to 120 degrees lower than hot mix. In most cases, the lower temperatures result in significant cost savings and reduced greenhouse gas emissions because less fuel is required. WMA also has the potential to extend the construction season, allowing projects to be delivered faster. By 2009, more than 40 States constructed WMA projects, with 14 adopting specifications to accommodate WMA.
With Prefabricated Bridge Elements and Systems (PBES), many time-consuming construction tasks no longer need to be done sequentially in work zones. An old bridge can be demolished while the new bridge elements are built at the same time off-site. Because PBES are usually fabricated under controlled climate conditions, weather has less impact on the quality, safety, and duration of the project. The use of PBES also offers cost savings in both small and large projects. The ability to rapidly install PBES on-site can reduce the environmental impact of bridge construction in environmentally sensitive areas. And there is less disruption to the traveling public during construction.
The $4.164 million Phillipston Heavy Lift Bridge Project in Phillipston, Massachusetts used PBES, innovative construction methods, procurement, and communication to surpass its ambitious goal to replace a well-travelled highway bridge while minimizing road user impacts to just a few days. The DB team demolished and replaced the bridge in just 121 hours. Road users and residents were pleased with the brevity of the detour period and rapid construction. The Massachusetts Department of Transportation estimates the cost avoidance totals to users to be approximately $2.5 million.
Adaptive signal control technologies adjust when green lights start and end to accommodate current traffic patterns, promote smooth flow, and ease traffic congestion. The main benefits of adaptive signal control technology over conventional signal systems are that it can automatically adapt to unexpected changes in traffic conditions, improve travel time reliability, reduce congestion and fuel consumption, and prolong the effectiveness of traffic signal timing. An array of adaptive signal control solutions exist, from those that tackle the complexity of large urban areas to those that can be deployed on arterial streets typically found in smaller cities. Selecting the proper products and solutions is a significant element in implementing efficient and cost effective adaptive signal control technology.
The Safety Edge is a simple and extremely effective solution that can help save lives by allowing drivers who drift off highways to return to the road safely. Instead of a vertical drop-off, the Safety Edge consolidates the edge of the pavement at 30 degrees. The Safety Edge provides a strong, durable transition for all vehicles. Even at higher speeds, vehicles can return to the paved road smoothly and easily. By including the Safety Edge detail while paving, this countermeasure can be implemented system-wide at a very low cost. The Safety Edge provides a more durable pavement edge that prevents edge raveling. FHWA's goal is to accelerate the use of the Safety Edge technology, working with States to develop specifications and adopt this pavement edge treatment as a standard practice on all new and resurfacing pavement projects.
Nationwide, thousands of lives are lost each year in crashes where vehicles run off the road or drivers cross into on-coming traffic after trying to over-correct when their wheels leave the pavement. This safety matter is why States such as Iowa have embraced this technology so quickly to address the problems that occur when vehicles leave the roadway. The Iowa Department of Transportation (Iowa DOT) has adopted the Safety Edge as a standard practice and has implemented it across the entire State. The evaluations of Iowa DOT and others have shown that simply providing this slope, allowing drivers to more easily recover when their tires leave the pavement, can reduce total crashes by more than 5 percent. Experiences like Iowa's have shown that rapidly implementing innovation cannot only save lives but can do so at very little cost. Following the conclusion of the EDC summits last fall, 47 States and many of their local agencies have selected the Safety Edge as one of their EDC priority initiatives.
Instead of conventional bridge support technology, Geosynthetic Reinforced Soil (GRS) Integrated Bridge System (IBS) technology uses alternating layers of compacted granular fill material and fabric sheets of geotextile reinforcement to provide support for the bridge. GRS also provides a smooth transition from the bridge onto the roadway, and alleviates the "bump at the end of the bridge" problem caused by uneven settlement between the bridge and approaching roadway. The technology offers unique advantages in the construction of small bridges, including:
Defiance County, Ohio officials are implementing this method to build bridges using readily available materials and common construction equipment. Using this innovative technology on the Stever Road Bridge project, the County reduced construction time by 2 months and reduced construction costs from an estimated $800,000 if built conventionally, to $620,000 using GRS—a net savings of $180,000 on one bridge protect. Defiance County has built 15 bridges using GRS with another 7 bridges planned. The savings the County achieves using GRS helps stretch the limited funds the County receives for its bridge needs.
FHWA recognizes that each State operates in a unique environment and, therefore, decisions on which initiatives to advance must be made at the State level. Accordingly, one of the keys to making EDC successful is working with each individual State to develop an approach that works best for it. Each State currently is selecting its priority initiatives and working with its FHWA partners and local and private stakeholder partners to create an implementation plan tailored to meet the unique needs, laws, and regulations of the State.
Section 6002 of SAFETEA-LU authorized changes to make the environmental review process more efficient, while protecting environmental and community resources. We do not know the full extent to which the enactment of 6002 may have furthered these objectives. However, early results from FHWA's tracking of Environmental Impact Statements (EISs) since SAFETEA-LU's enactment indicate a reduction in the average time of environmental reviews. For the 18 EIS projects initiated and completed after SAFETEA-LU, the average time to complete the process (from Notice of Intent to Record of Decision) was 43 months. In comparison, in the 6 years prior to SAFETEA-LU, the average time to complete this process was 73 months. Additionally, FHWA has seen a positive reaction from agencies and the public regarding their early involvement in the environmental review process.
Section 6004 of SAFETEA-LU allows for FHWA to assign, and for State Departments of Transportation (State DOTs) to assume, responsibilities for determining whether certain highway projects meet criteria to be classified as categorically excluded from the requirements to prepare either an Environmental Assessment (EA) or an EIS. Responsibilities for complying with other related environmental laws and regulations also may be assigned to State DOTs. California, Alaska, and Utah, the 3 States with assignments, have reported that they have been successful in saving processing time of categorically-excluded projects as well as in maintaining and improving decision-making.
Section 6005 of SAFETEA-LU established a pilot program to allow the Secretary to assign, and the State to assume, the Secretary's responsibilities under the National Environmental Policy Act (NEPA) for one or more highway projects. Implementation of the pilot by the California
Department of Transportation (Caltrans) has provided indicators of success in accelerating project review times. In June 2007, FHWA and Caltrans entered into a Memorandum of Understanding (MOU) that established the assignments and assumptions of responsibility to Caltrans. Under the MOU, Caltrans assumed the majority of FHWA's responsibilities under NEPA (excluding project level air quality conformity analysis and tribal consultation), as well as FHWA's responsibilities under other Federal environmental laws, for most highway projects in California. While during this period of time no EIS projects have been processed solely under the pilot program, Caltrans claims time savings in the range of 12 to17 months in connection with about 50 EAs processed. Having such authority for the process has given Caltrans increased confidence in managing its projects.
Section 6009 of SAFETEA-LU also helps accelerate project delivery for projects that impact publicly owned parks, recreation areas, wildlife and waterfowl refuges, or historic sites, which are protected under section 4(f) of the Department of Transportation Act. Specifically, section 6009 provides that section 4(f) requirements will be considered satisfied if the United States Department of Transportation determines that the project will have a de minimis impact on the area in question. It also establishes conditions for de minimis impacts findings. Our Phase I evaluation results suggest that the de minimis impact provision can enable transportation agencies to better balance the timely delivery of transportation projects with protection of these publicly owned facilities. In addition, the de minimis impact provision has simplified the fulfillment of section 4(f) requirements, particularly in cases where the official with section 4(f) jurisdiction initiates or sponsors the transportation project. We are currently surveying State DOTs, other entities, and stakeholders for the Phase II report, which will include an update of de minimis findings and evaluate application of the new feasible and prudent standard.
Our society and the transportation community face an unprecedented list of challenges. We need to deliver projects more efficiently and with greater accountability. We need to find ways to make our roads safer and maintain environmental quality.
But it is not sufficient to simply address those challenges. We need to do so with a new sense of urgency. It is that urgency that I have tried to capture in FHWA's EDC initiative. In challenging times, it is imperative we pursue better, faster, and smarter ways of doing business.
This is a very busy and important year for the transportation community as we work on a new authorization of our surface transportation programs. President Obama's Fiscal Year 2012 Budget released yesterday outlines some of the Administration's ideas for investing in our infrastructure in a way that will support thousands of jobs, make our roads safer and our communities more livable, and lay a foundation for future economic growth. I look forward to working with you and other members of Congress in the weeks and months ahead as we look for innovative ways to make every day—and every dollar—count.
Mr. Chairman, thank you for the opportunity to appear before you today. I would be happy to answer your questions.
FHWA Briefing Room | Speeches and Testimony
FHWA Speeches & Testimony Archive
Return to top


text:
He has been handed his second start for England's second RBS 6 Nations clash against the Azzurri and gave an insight into the Red Rose dressing room prior to the announcement.
Botha revealed interim head coach Stuart Lancaster used Del Rey's debut single Video Games, as well as a montage incorporating the track, to help inspire England to victory at Murrayfield.
It certainly did the job but Saracens lock Botha is adamant it will all count for nothing if England fail show Italy the respect they deserve at the Stadio Olimpico on Saturday.
"The bond we have created is something that we showed on Saturday and it is building towards something special," said Botha. "Stuart got it spot on with the build up of emotions.
"That song was playing in the dressing room as you walked in and it was the backing track to a highlights package that had been made for us featuring all of the players.
"It made the hairs stand up - it gave you the feeling you are ready for this. It was a brilliant occasion at Murrayfield and to be facing something like that again will be a brilliant challenge.
"But Italy will be a big battle. They are one of the sides that have made massive strides over the past few years.
"They are not a wooden-spoon team anymore and at home in their new stadium they will be up for the challenge with 70,000 fans behind them."


text:
COUNCILLORS have agreed to withdraw one of their reasons for objecting to redevelop Weymouth Football Stadium as housing.
West Dorset District Council refused an application by the Wessex Delivery LLP to redevelop the stadium site with up to 170 houses in October last year.
The reasons for refusal included the fact that the site proposed residential development outside the existing development boundary, the loss of playing fields with no firm alternative and the need for a section 106 agreement or other form of undertaking to guarantee affordable housing and local amenity contributions.
The decision to refuse the application was appealed and will now be considered by an independent planning inspector.
However, before that happens members of the council's development control committee have agreed to withdraw the first reason for refusal.
Planning officer Andrew Martin told councillors that because the council now recognised the need for a larger housing supply in the coming years after carrying out further work on its proposed local plan, it could not justify a refusal on the grounds that it did not need to develop outside existing boundaries.
He said: "At that time our view was we didn't need to breach the development boundary in order to reach housing numbers, that situation has clearly changed."
Mr Martin said that the council's chances of defending this reason for refusal at appeal were nonexistent.
He said: "To progress that particular reason we would stand no chance at all of defending that one at appeal."
Mr Martin said that if a satisfactory section 106 agreement could be drawn up with the developers that third reason for refusal could also be withdrawn, leaving only the concern about the loss of playing fields with no firm alternative provision.
The councils agreed to withdraw the first reason for refusal and to inform the Planning Inspectorate and appellant of the decision.


text:
Is distilled water for car battery?-A A +A
Saturday, February 22, 2014
IN MOST times, we forget that health is the most vital part for everyone to possibly live longer. People get shocked when they discover that one gets a lung cancer when he is a non-smoker. Or one gets a liver cancer when he is not an alcoholic.
But life is just once and there are other factors that may lead one to some unexpected illness. Look back to the history of your lifestyle and possibly these are the reasons why healthy life ends so early. Even depression can lead a person to a miserable life and end up with heart attack, poor health condition, and whatever.
While many claim that many in the medical profession never give advice like drink sufficient water every day, or sleep so many hours a day or take those original (not alternative) supplements for a healthier living like garlic, guyabano, carrots, pepper, and more, it is evident that healthy living means taking these healthier foods. And one reliable person speaks of refined sugar and milk as eventually carcinogenic.
One lecturer told a crowd while laughing that he is surprised why people are drinking distilled water which, he said, is intended for auto batteries and steamed iron. Yes many indeed drink distilled water, he said, not knowing that it is highly acidic and not good for children. Well, try to find out for yourself but I would not dare drink distilled since there are those spring and natural drinking water available anyway.
I never liked spicy food but when a Malaysian doctor advised me to eat somewhat spicy food, I have come to believe that it prevents basic illness like colds, fever and more. Many are amused why it is said that eating too much spicy food will bring you to that almoranas thing. If this is true then all Indians, Arabs, Malaysians, Thais, and those Bicolanos and Ilocanos who all love spicy foods should have had that almoranas experience.
Staying healthy would mean eating more fruits worth spending for rather than eating those unhealthy recipes on the table. Guayabano is claimed to be better than chemotherapy. We believe that the best cure is GODmotherapy. Pray to Him in the heavens always. He is the best doctor of the universe.
This column wish to greet Sherwin Damasco of Western Electronics; Roland Jubilag of Circumferential Auto Sports; Mao Vecera of San Miguel Brewery; Nelia Garcia-Neri of Sun.Star Cebu; Honey Jarque-Loop of Philippine Star; Chef Richie Gamboa of 21 Resto; Henry and Ninfa Espinosa of Espinosa Designs; Ernie Hilado of Peugeot Cars; and William and Evelyn Ong of 888 Chinatown Square.
Published in the Sun.Star Bacolod newspaper on February 22, 2014.
Forum rules: Do not use obscenity. Some words have been banned. Stick to the topic. Do not veer away from the discussion. Be coherent and respectful. Do not shout or use CAPITAL LETTERS!


text:
ALSA Installer builds, installs, and help you configure ASLA on your computer so that you can get your sound card working without having to know any of the technical information for it. Simply put, you just run this, and it does the work for you.
Other Useful Business Software
User Reviews
Be the first to post a review of ALSA Installer!


text:
Just Out
A. E. B. Coldiron. Printers Without Borders: Translation and Textuality in the Renaissance. Cambridge: Cambridge University Press, 2015. ISBN 9781107073173. 339pp. £65.00.
"The first book printed in English was not printed in England" and it was not an original English text: William Caxton's Recuyell of the Historyes of Troye, printed in Bruges in 1473, was an "englishing" of the Burgundian author Raoul Lefèvre's Recoeil, itself a medieval mediation of a foundational myth, the history of Troy, which enjoyed great popularity in Tudor, Elizabethan and Jacobean literature, political rhetoric and royal dynastic discourses. Caxton's translation, repeatedly reprinted during the 15th and 16th centuries, contributed to fashioning early modern reception of the myth. A. E. B. Coldiron investigates the continental dimensions of this Englishing, and how printers and translators contributed to such forms of appropriation and acculturation, "performed by means of verbal translation and material-textual mediation. More
John Scheid and Jesper Svenbro. La tortue et la lyre: Dans l'atelier du mythe antique. Paris, CNRS Éditions, 2014. ISBN 978-2-271-07883-4. 229pp. €22.00.
How were Greek myths elaborated? How can we understand them? What critical tools can help us develop a pragmatic approach towards "a poetics of myth"? Such are some of the questions to which John Scheid and Jesper Svenbro offer new answers in their exploration of "the workshop" of the myths of Antiquity. Their inquiry, which started in their preceding book, Le métier de Zeus: Mythe du tissage et du tissu dans le monde gréco-romain (Paris: La Découverte, 1994; rep. Paris: Errance, 2003), is not only continued, but deepened and strengthened in La tortue et la lyre. Read a review on this website.
Phillip John Usher. Epic Arts in Renaissance France. Oxford, Oxford University Press, 2014. ISBN 978-0-19-968784-8. xii+254pp. £60.00 (hb).
This richly documented investigation into Renaissance France's 'intense relationship between epic and art' (205) engages epic texts in a dialogue with their visual sister arts: programmes are considered, such as the Fontainebleau gallery which glorified François Ier and epic texts such as Dolet's Fata, which refashion classical epic material. Ronsard's Franciade was 'part of both a national and a royal project and in constant dialogue with other arts' (159), inspiring a series of paintings by Dubreuil for Henri IV. This dialogue implies rapprochements, 'textualisations' but also differing perspectives, within the French arts but also between French and other European artists and poets. The author recreates visual ambiences, and documents how they would have appeared to sixteenth-century viewers, so as to help his readers glimpse 'the inside spaces as they would have been visible' (175) then and understand how this epic art would have been read.
Colin Burrow. Shakespeare and Classical Antiquity. Oxford University Press, 2013. ISBN 978-0-19-968479-3. 296p. £16.99.
Shakespeare and Classical Antiquity shows the range, extent and variety of Shakespeare's responses to classical antiquity. Individual chapters on Virgil, Ovid, Classical Comedy, Seneca, and Plutarch show how Shakespeare's understanding of and use of classical authors, and of the classical past more generally, changed and developed in the course of his career. Read a review on this website.
Recent additions to this website
Troia Britanica, XIII (Patricia Dorval)
Updated Medea entry (Katherine Heavey)
Reviews<< read more >>
Just Out
New Books
<< read more >>
Our website selected Website of the Week on MLA Facebook page<< read more >>