text:
Data center design: Fire and life safety
In the information age, data centers are one of the most critical components of a facility. If the data center isn't reliable, business can't be done. Fire and life safety issues are tackled here.
- Kevin V. Dickens, PE, LEED BD+C, Mission critical design principal, Jacobs Engineering, St. Louis
- Terrence J. Gillick, President, Primary Integration Solutions Inc., Charlotte, N.C.
- Bill Kosik, PE, CEM, BEMP, LEED AP BD+C , Principal data center energy technologist, HP Technology Services, Chicago
- Keith Lane, PE, RCDD, NTS, RTPM, LC, LEED AP BD+C, President/CEO, Lane Coburn & Associates LLC, Bothell, Wash.
- David E. Wesemann, PE, LEED AP, ATD, President, Spectrum Engineers Inc., Salt Lake City
CSE: What trends and events have affected changes in fire detection/suppression systems in data centers?
Wesemann: The highly sensitive air sampling systems are very common for data centers due to their early detection of potential fires. This coupled with a gaseous clean-agent type suppression system helps to avoid the risk of introducing water from wet sprinklers into the data center (although many codes and jurisdictions still require traditional sprinkler systems even if clean agent suppression systems are present).
Gillick: To varying degrees, philosophical, code, and insurance trends all have affected changes in life safety/fire suppression systems in data centers. From a fire detection standpoint, we are seeing the deployment of early detection warning systems, such as very early smoke detection apparatus (VESDA), which detect the elements of combustion at the atomic level and indicate a pending fire. Another area in which we've seen significant change is within the data center enclosure, where we are being asked to commission various combinations of water, dry-pipe reaction, and gaseous suppression systems depending on the facility. Additionally, many of the medium- and high-density rack enclosures require fire suppression systems within the enclosure, which vary by local jurisdictions and code requirements.
CSE: How have the costs and complexity of fire protection systems changed in recent years?
Gillick: The cost and complexity of dry-pipe and gaseous systems have increased in recent years. As a result, some owners are selecting wet-pipe systems with the approval of their insurance carriers.
CSE: What changes in clean agent suppression systems have you seen in data centers recently? What do you see changing in the near future?
Wesemann: FM200 seems to be a popular suppression system still. I've seen some nitrogen misting systems being used.
Gillick: Due to the cost of clean agent suppression systems and the storage requirements of the gas canisters, owners are considering the volume of space in which they want to deploy these systems: full flood of the white space area between the ceiling grid and the raised floor, within the raised floor plenum or ceiling plenum, or all of the above? We are starting to see the emergence on the market of new gases, fostering the retrofit or replacement of some of the legacy systems. Overall, I do not see owners deploying clean agent systems as extensively now as they did in the past, and that trend may continue in the near future.
CSE: What are some important factors to consider when designing a fire and life safety system in a mixed-use building (data center within an office building, for example)? What things often get overlooked?
Wesemann: In mixed-use buildings, data centers have to be designed as stand-alone facilities with their unique requirements for fire detection and suppression, but then report to the main building fire alarm system. Likewise, the building system needs to report to the data center. Sometimes the "overlay" of the two systems (which can be the same system with two functions) gets confusing, especially if the same signal tone is used to annunciate both types of alarms (those generated within the data center and those generated in other areas of the mixed-use building).
Gillick: There are two very important factors to consider in the context of fire and life safety in a mixed-use building: first, design of a dedicated MEP system for the data center, which will enable it to continue operation as a stand-alone structure in the event of a fire or other catastrophic event; and second, development of contingency plans to protect the space if code requires that a fire alarm condition must unlock all doors. You'd be surprised how often these factors are overlooked until someone has observed the consequences of a fire department shutdown of MEP services to the entire building, or intruders entering unlocked and unprotected doors.
CSE: In a mission critical facility such as a hospital, what unique emergency notification or mass notification systems have you specified, and what challenges did you overcome?
Gillick: More than in any other type of mission critical facility, a hospital requires integration of many layers of internal communication systems—emergency mass notification systems, fire alarm notification, security, paging, nurse-call, handheld online records, etc.—with the building telecommunication and security systems. The challenges include correct zoning of the announcements and coordination with architectural design for signage, assembly places, shelter-in-place areas, and so forth.
Wesemann: Voice annunciation systems with the ability to broadcast prerecorded and live messages are often used. The biggest challenge with the voice systems is the NFPA intelligibility requirements that are difficult to predict using traditional design methods and rules of thumb. We often have to involve our acoustical engineer with computerized design and modeling tools to ensure intelligibility.
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This is not the case in Europe and the Middle East, in particular.
It is disheartening to note and see sprinkler systems used that extensively in data centers and other key sensitive areas. Apparently, the sprinkler lobby here in the US has done a good job and it's time for the rude awakening. A case from the recent NFPA journal may serve as a daring example in this regard. Somewhere in the East Coast, a modern warehouse facility caught fire and despite all the intervening efforts of a number of fire departments from the adjoining Cities and Counties, this modern and recently built facility was a colossal loss.
The insurance company assigned the task to "Hughes Associates" to investigate and suggest provision of early detection systems for future scenarios.....The warehouse had no detection system and just the sprinkler system....read the full story in NFPA journal to be enlightened further on this subject.....Sprinklers are good, even great but please do not be sold out that everything is fine and dandy with just a sprinkler system in place. After all, that day has not dawned as yet where a typical sprinkler head can act in part at least to respond to the presence of dense smoke as well. It's a topic of ........
Lastly, I would like to mention that the use of Water Mist Systems as a substitute for the ozone depleting halons is slowly but surely gaining momentum but again water mist miniscule droplets are not the same as water from sprinkler heads.
Irony of the matter is that even preaction systems which require some form of early detection for system actuation are seeing a push-back in some areas and States. This subject was brought up to our attention during the most recent meeting of the Cascade Chapter of SFPE here in the Portland, Oregon area.
Simply put, this is unacceptable.
Reason: A sprinkler head no matter how fancy a term you can use to describe it (Fast response/Early Discharge) or whatever, are not and will never be a substitute for early warning and very early warning detection systems.
VESDA = (Very Early Smoke Detection Apparatus) system, way to go (thumbs up).
Concluding Remarks:
Fire is the greatest of servants but what a master and master it truly becomes when fire has taken a foot hold. Remember the 3 minute rule.....Early detection and intervention is the key, why wait for the flames to appear. Even for property protection and mission critical facilities and operations, this is of paramount importance.
I sincerely hope that I have not offended any one here. For once, you are to blame for providing all the prompts in your article.
Sharing is power, though.
Keep it up!
M. Malik
The code deferred to protection provisions of NFPA 75, Standard for the Protection of Information Technology Equipment
In NFPA 75 1999 Ed, it stated the following: ( Note this is consistent with the 2013 Edition of NFPA 75.)
The computer area shall be separated from other occupancies within the building, including atria or other open-space construction, by fire-resistant-rated construction. The computer room shall be separated from other occupancies in the computer area by fire-resistant-rated construction. The fire resistance rating shall be commensurate with the exposure but not less than 1 hour for both.
126.96.36.199 The fire resistance rating shall be commensurate with
the exposure but not less than 1 hour for both.
Excerpts from NFPA 70 Article 645, 2011
Information Technology Equipment (ITE). Equipment and
systems rated 600 volts or less, normally found in offices or
other business establishments and similar environments
classified as ordinary locations, that are used for creation
and manipulation of data, voice, video, and similar signals
that are not communications equipment as defined in Part I
of Article 100 and do not process communications circuits
as defined in 800.2.
Informational Note: For information on listing requirements
for both information technology equipment and communications
equipment, see UL 60950-1-2007, Information Technology
Equipment - Safety - Part 1: General Requirements.
Information Technology Equipment Room. A room within
the information technology equipment area that contains the
information technology equipment. [75:3.3.9]
645.4 Special Requirements for Information Technology
Equipment Room. This article shall be permitted to
provide alternate wiring methods to the provisions of Chapter
3 and Article 708 for power wiring, Parts I and III of
Article 725 for signaling wiring, and Parts I and V of Article
725 for optical fiber cabling where all of the following conditions are met:
(1) Disconnecting means complying with 645.10 are provided.
(2) A heating/ventilating/air-conditioning (HVAC) system
is provided in one of the methods identified in 645.4(2) a or b.
a. A separate HVAC system that is dedicated for information
technology equipment use and is separated
from other areas of occupancy; or
b. An HVAC system that serves other occupancies and
meets all of the following:
i. Also serves the information technology equipment room
ii. Provides fire/smoke dampers at the point of penetration
of the room boundary
iii. Activates the damper operation upon initiation
by smoke detector alarms, by operation of the
disconnecting means required by 645.10, or by both
Informational Note: For further information, see NFPA 75-
2013, Standard for the Protection of Information Technology
Equipment, Chapter 10, 10.1, 10.1.1, 10.1.2, and 10.1.3.
(3) All information technology and communications equipment
installed in the room is listed.
(4) The room is occupied by, and accessible to, only those
personnel needed for the maintenance and functional operation
of the installed information technology equipment.
(5) The room is separated from other occupancies by fire-resistant-
rated walls, floors, and ceilings with protected openings.
Informational Note: For further information on room construction
requirements, see NFPA 75-2013, Standard for the
Protection of Information Technology Equipment, Chapter 5.
(6) Only electrical equipment and wiring associated with
the operation of the information technology room is
installed in the room.
Informational Note: HVAC systems, communications systems,
and monitoring systems such as telephone, fire alarm
systems, security systems, water detection systems, and
other related protective equipment are examples of equipment
associated with the operation of the information technology room.
Hypoxic fire prevention is by far (in my opinion) the best way to protect against the risk of fire without need of expensive pressure tests and the chance of accidental discharge.
Further more the implementation of these systems do no adverse affects to sensitive equipment by acoustic shock from discharge or damage by water etc.
I am more than happy to discuss the ins and outs of these systems as I believe they are often misunderstood or unknown.
James Phelps


text:
I'm 29 and in the last two weeks literally, have noticed my frown lines become slightly static. If I train myself to not make this expression and wear my glasses more can I avoid Botox? What else can I do to soften the line in this ver y early stage?
Alternatives to Botox, will this work for very early lines?
Doctor Answers 2
Alternatives to Botox, will this work for very early lines?
I also agree applying spy daily can help slow the signs of aging, you're at a perfect age to start preventing future lines/wrinkles, its best you seek a board certified physician who can provide a natural conservative look you wish to achieve
How to take care of your skin
The best way to keep your skin looking young is to take care of it well. It is worth your while to see a good cosmetic dermatologist or cosmetic surgeon who does cosmetic skin care.
I would suggest, to start off, that you be sure to use a good sun block every day. The best skin block are physical blocks that contain things like zinc or titanium. Those work better then chemical blocks. I would also consider using a good Vitamin C serum. Sun blocks help prevent the formation of free radicals (oxidants). Vitamin C is the best topical anti-oxidant that protects you from some of the damage that occurs despite the use of sun blocks. The best Vitamin C serums tend to come in dark bottles with an eyedropper top. At some point your doctor may suggest Retin-A which helps reverse the sun damage that has already occurred.
At some point you may be ready for Botox, but good skin care will always be an essential part looking your best, and starting young will really pay off.
These answers are for educational purposes and should not be relied upon as a substitute for medical advice you may receive from your physician. If you have a medical emergency, please call 911. These answers do not constitute or initiate a patient/doctor relationship.

subset: commoncrawl


text:
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NORTH ANDOVER, MA. – Saturday's Merrimack hockey game at Vermont will be televised live across the country on the CBS Sports Network at 7:30 p.m.
Locally, the game is on channel 261 or 856 in High Definition on Comcast and channel 613 on DirecTV. This is the first time in program history Merrimack is on the CBS Sports Network.
The Warriors will also be on CBSSN on February 24 against Boston College and March 3 against UMass Lowell, with both games being played at Lawler Arena.
Merrimack (6-8-4, 4-4-1 HEA) defeated and tied Vermont earlier this season at Lawler Arena. The Warriors will enter Saturday's contest with an 11-game unbeaten streak (8-0-3) against the Catamounts.
Log on to cbssportsnetwork.com for more information.
Merrimack returns home next weekend hosting #9 Boston University Friday at 7:30 p.m. and the University of Maine Saturday at 7 p.m. Tickets are available at merrimackathletics.com or by calling 978-837-5324.


text: A suggestive room – two armchairs, painting on the walls, in the center is Richard Bandler, spreading full associations, stories and gestures, with participants creating internal images that stretch the perceptual senses and emotions . . . a long trance, as well as elegantly interlaced patterns processing from depression to stretching belief systems, to sexual conflicts, to decision strategies, to the influence of NLP on neurology and physiology.


text:
Hey there, time traveller!
This article was published 18/1/2014 (1282 days ago), so information in it may no longer be current.
CHARLOTTE, N.C. -- A 16-driver championship field that would be whittled down to create a winner-take-all season finale is among radical changes reportedly being considered by NASCAR.
NASCAR chairman Brian France has repeatedly said he wants to place a greater emphasis on winning, and he's never ruled out tinkering with the Chase for the Sprint Cup championship format in an effort to create the "Game 7 moments" he covets.
The Charlotte Observer first reported Friday night a possible overhaul to the Chase format that France first introduced in 2004 and has made periodic changes to several times since.
Citing anonymous sources, The Observer outlined three major changes beginning with expanding the field from 12 drivers to 16 -- meaning a win during the "regular season" would virtually guarantee a driver a spot in the field.
Once the field is set, The Observer said NASCAR is considering eliminations during the 10-race Chase.
The field would be cut after the third, sixth and ninth races. The proposed eliminations would drop the lowest four drivers from title contention after the third, sixth and ninth races, leaving four drivers eligible for a "winner-take-all" race in the season finale at Homestead-Miami Speedway. The four remaining drivers would go into Homestead with their points reset and tied in the standings, The Observer said.
A statement from NASCAR chief communications officer Brett Jewkes was non-committal on The Observer report.
"NASCAR has begun the process of briefing key industry stakeholders on potential concepts to evolve its NASCAR Sprint Cup Series championship format," Jewkes said. "This dialogue is the final phase of a multi-year process that has included the review of extensive fan research, partner and industry feedback and other data-driven insights. NASCAR has no plans to comment further until the stakeholder discussions are complete. We hope to announce any potential changes for the 2014 season to our media and fans very soon."
But driver Denny Hamlin posted a series of Tweets on Saturday afternoon that supported the format if NASCAR ultimately moves forward with the changes. NASCAR is expected to officially outline any changes later this month.
"This points system change is going to be a really good thing. Trust in it and watch how exciting each chase race is going to be," Hamlin posted.
Hamlin also Tweeted that every Chase race will now be as exciting as the September race at Richmond, which is the final race to set the Chase field. He also responded to two fans who criticized the format. One argued it was "artificially construed excitement" instead of the traditional consistency that NASCAR used for decades in crowning its champion.
"Consistency will keep you up top," Hamlin replied.
Hamlin received support from 2012 Cup champion Brad Keselowski, who replied on Twitter to him that he also liked the reported new format.
"Guess we may be in the minority here," Keselowski said.
NASCAR has been working feverishly behind the scenes to improve its on-track product, particularly at 1.5-mile tracks, and at least some changes are expected to the points system to meet France's desire to put a greater emphasis on winning. France was thrilled with the finish of the March race at California, where feuding drivers Hamlin and Joey Logano relentlessly raced for the win.
The two ended up wrecking -- Hamlin ended up with a broken bone in his back that sidelined him for more than a month -- and Kyle Busch slid through the carnage for the victory as a furious Tony Stewart nearly came to blows with Logano on pit road. It's that kind of competitiveness, compelling action and drama that France seeks every week.
Despite introducing The Chase in 2004, NASCAR has failed to create many of those breathtaking "Game 7" moments in the finale. The debut was successful as Kurt Busch beat Jimmie Johnson for the title by eight points, and five drivers went into the 2005 finale mathematically eligible to win the championship.
But ensuing Chases have lacked the same drama.
-- The Associated Press


text:
How to Buy
Solutions Overview
Ubuntu Security Notice (C) 2006-2016 Canonical, Inc. / NASL script (C) 2006-2016 Tenable Network Security, Inc.
Synopsis :
The remote Ubuntu host is missing one or more security-related
Description :
USN-194-1 fixed a vulnerability in the 'texindex' program.
Unfortunately this update introduced a regression that caused the
program to abort when cleaning up temporary files (which are used with
extraordinarily large input files). The updated packages fix this.
Note that Tenable Network Security has extracted the preceding
description block directly from the Ubuntu security advisory. Tenable
has attempted to automatically clean and format it as much as possible
without introducing additional issues.
Solution :
Update the affected info and / or texinfo packages.
Risk factor :
Family: Ubuntu Local Security Checks
Nessus Plugin ID: 20761 ()
Bugtraq ID:
Get Nessus Professional to scan unlimited IPs, run compliance checks & more
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text: I think the problem is not that qsub uses rsh rather than ssh, but that the authentication uses ruserok(3). Extract from src/lib/Libsite/site_check_u.c : /* * site_check_u - site_check_user_map() * * This routine determines if a user is privileged to execute a job * on this host under the login name specified (in user-list attribute) * * As provided, this routine uses ruserok(3N). If this is a problem, * It's replacement is "left as an exercise for the reader." * * Return -1 for access denied, otherwise 0 for ok. */ HTH Martin Rushton HPC Facility QinetiQ Bldg H4 Rm 6 MoD Fort Halstead Sevenoaks Kent, TN14 7BP Tel: 01959 514777 Email: jmrushton at QinetiQ.com Mobile: 07939 219057 Fax: 01959 51 6050 Web: www.QinetiQ.com QinetiQ - The Global Defence and Security Experts * Please consider the environment before printing this email. |-----Original Message----- |From: torqueusers-bounces at supercluster.org |[mailto:torqueusers-bounces at supercluster.org] On Behalf Of |Lippert, Kenneth B. |Sent: 29 January 2008 18:05 |To: torqueusers at supercluster.org |Subject: RE: [torqueusers] qsub: Job rejected by all possible |destinations - | |I did have ssh set up between all nodes and appropriate |accounts. I guess qsub uses rsh anyway. Perhaps there is a |compile switch I missed. | | |-k | | |-----Original Message----- |From: Miles O'Neal [mailto:meo at intrinsity.com] |Sent: Tuesday, January 29, 2008 12:41 PM |To: Lippert, Kenneth B. |Cc: torqueusers at supercluster.org |Subject: Re: [torqueusers] qsub: Job rejected by all possible |destinations - | |Lippert, Kenneth B. said... | ||Don't know why, and this is really just a work-around I guess, but ||putting the COMPUTE node into the user's .rhosts file on the SERVER |node ||fixed the problem. BOB was already set up, JEFF being new, wasn't. | |torque depends heavily on either rsh or ssh, so this is a |requirement for rsh users, AFAICT. |_______________________________________________ |torqueusers mailing list |torqueusers at supercluster.org |http://www.supercluster.org/mailman/listinfo/torqueusers | The information contained in this E-Mail and any subsequent correspondence is private and is intended solely for the intended recipient(s). The information in this communication may be confidential and/or legally privileged. Nothing in this e-mail is intended to conclude a contract on behalf of QinetiQ or make QinetiQ subject to any other legally binding commitments, unless the e-mail contains an express statement to the contrary or incorporates a formal Purchase Order. For those other than the recipient any disclosure, copying, distribution, or any action taken or omitted to be taken in reliance on such information is prohibited and may be unlawful. Emails and other electronic communication with QinetiQ may be monitored and recorded for business purposes including security, audit and archival purposes. Any response to this email indicates consent to this. Telephone calls to QinetiQ may be monitored or recorded for quality control, security and other business purposes. QinetiQ Limited Registered in England & Wales: Company Number:3796233 Registered office: 85 Buckingham Gate, London SW1E 6PD, United Kingdom Trading address: Cody Technology Park, Cody Building, Ively Road, Farnborough, Hampshire, GU14 0LX, United Kingdom http://www.QinetiQ.com/home/legal.html


text:
Ice Master (TRS-80 CoCo)
Published by
Developed by
Also For
Critic Score
100 point score based on reviews from various critics.
User Score
5 point score based on user ratings.
Not an American user?
DescriptionIce Master is another early Pengo clone. Your small man runs around in a landscape filled with blocks of ice and populated by insects. Your only goal is to crush the insects by pushing ice blocks at them. You can only push one block at a time. Trying to push a block that is blocked by another block will instead destroy the block so that you can push the one behind it. All insects must be crushed before you can go on to the next level, which is made more difficult by the fact that they respawn, so killing all in a quick succession is required. Bonus score is calculated based on how much time is used. The game runs in black and white high resolution mode, with artifact colour on NTSC machines.
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Part of the Following Group
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Игги Друге (44998) added Ice Master (TRS-80 CoCo) on Nov 11, 2006
Other platforms contributed by Игги Друге (44998)
1983 copyrighted:


text:
Our Personalized Vintage Glass Groomsman Flask will be the toast of your bachelor party. Small enough to fit in a jacket pocket, this flask offers plenty of room for his favorite beverage and also includes attached swing tops, which can be removed if desired. Personalize with First Name, Last Name and Date. Groomsman is standard and cannot be changed.
Do you have product questions or suggestions?


text:
|Publication number
|Publication type
|Application number
|Publication date
|Mar 20, 2012
|Filing date
|Aug 4, 2008
|Priority date
|May 16, 2000
|Fee status
|Also published as
|Publication number
|Phillip M. Adams
|Original Assignee
|Phillip M. Adams & Associates
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (35), Non-Patent Citations (7), Referenced by (2), Classifications (12), Legal Events (2)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a continuation of U.S. patent application Ser. No. 11/472,661 filed Jun. 22, 2006, now U.S. Pat. No. 7,409,601 issued Aug. 5, 2008, which is a continuation of U.S. patent application Ser. No. 10/715,132 filed Nov. 17, 2003, now U.S. Pat. No. 7,069,475 issued Jun. 27, 2006, which is a continuation of U.S. patent application Ser. No. 09/571,969 filed May 16, 2000, now U.S. Pat. No. 6,687,858 issued Feb. 3, 2004.
1. The Field of the Invention
This invention relates to software programming for controlling behavior of hardware devices, and, more particularly, to novel systems and methods for inseparably welding a software layer to a hardware device interface, thus precluding insertion of any other software layer therebetween.
2. Background of the Invention
Computers are now used to perform functions and maintain data critical to many organizations. Businesses use computers to maintain essential financial and other business data. Computers are also used by government to monitor, regulate, and even activate, national defense systems. Maintaining the integrity of the stored data is essential to the proper functioning of these computer systems, and data corruption can have serious (even life threatening) consequences.
Most computer systems include media drives, such as floppy diskette drives for storing and retrieving data. For example, an employee of a large financial institution may have a personal computer that is attached to the main system. In order to avoid processing delays on the mainframe, the employee may routinely transfer data files from a host system to a local personal computer and then back again, temporarily storing or backing up data on a local floppy diskette or other media. Similarly, an employee with a personal computer at home may occasionally decide to take work home, transporting data away from and back to the office on a floppy diskette.
Data transfer to and from media, such as a floppy diskette, is controlled by a device called a Floppy Diskette Controller ("FDC"). The FDC is responsible for interfacing the computer's Central Processing Unit ("CPU") with a physical media drive. Significantly, since the drive is spinning, it is necessary for the FDC to provide data to the drive at a specified data rate. Otherwise, the data will be written to a wrong location on the media.
The design of an FDC accounts for situations occurring when a data rate is not adequate to support rotating media. Whenever this situation occurs, the FDC aborts the write operation and signals to the CPU that a data under run condition has occurred.
Unfortunately, however, it has been found that a design flaw in many FDCs makes impossible the detection of certain data under run conditions. This flaw has, for example, been found in the NEC� 765, INTEL� 8272 and compatible Floppy Diskette Controllers. Specifically, data loss and/or data corruption may routinely occur during data transfers to or from diskettes (or tape drives and other media attached via the FDC), whenever the last data byte of a sector being transferred is delayed for more than a few microseconds. Furthermore, if the last byte of a sector write operation is delayed too long then the next (physically adjacent) sector of the media will be destroyed as well.
For example, it has been found that these faulty FDCs cannot detect a data under run on the last byte of a diskette read or write operation. Consequently, if the FDC is preempted or otherwise suspended during a data transfer to the diskette (thereby delaying the transfer), and an under run occurs on the last byte of a sector, the following occur: (1) the under run flag does not get set, (2) the last byte written to the diskette is made equal to either the previous byte written or zero, and (3) a successful Cyclic Redundancy Check ("CRC") is generated on the improperly altered data. The result is that incorrect data is written to the diskette and validated by the FDC. Herein, references to a floppy diskette may be read as "any media" and a floppy diskette drive is but a specific example of a media drive controllable by an FDC.
Conditions under which this problem may occur have been identified in connection with the instant invention by identifying conditions that can delay data transfer to or from the diskette drive. In general, this requires that the computer system be engaged in "multi-tasking" operation or in overlapped input/output ("I/O") operation. Multi-tasking is the ability of a computer operating system to simulate the concurrent execution of multiple tasks.
Importantly, concurrent execution is only "simulated" because only one CPU exists in a typical personal computer. One CPU can only process one task at a time. Therefore, a system interrupt is used to rapidly switch between the multiple tasks, giving the overall appearance of concurrent execution.
MS-DOS� and PC-DOS�, for example, are single-task operating systems. Therefore, one could argue that the problem described above would not occur. However, a number of standard MS-DOS� and operating environments simulate multi-tasking and are susceptible to the problem.
In connection with the instant invention, for example, the following environments have been found to be prime candidates for data loss and/or data corruption due to defective FDCs: local area networks, 327x host connections, high density diskettes, control print screen operations, terminate and stay resident ("TSR") programs. The problem also occurs as a result of virtually any interrupt service routine. Thus, unless MS-DOS� and PC-DOS� operating systems disable all interrupts during diskette transfers, they are also highly susceptible to data loss and/or corruption.
The UNIX� operating system is a multi-tasking operating system. It has been found, in connection with the instant invention, how to create a situation that can cause the problem within UNIX�. One example is to begin a large transfer to the diskette and place that transfer task in the background. After the transfer has begun then begin to process the contents of a very large file in a way that requires the use a Direct Memory Access ("DMA") channel of a higher-priority than that of the floppy diskette controller's DMA channel. These might include, for example, video updates, multi-media activity, etc. Video access forces the video buffer memory refresh logic on DMA channel 1, along with the video memory access, which preempts the FDC operations from occurring on DMA channel 2 (which is lower priority than DMA channel 1).
This type of example creates an overlapped I/O environment and can force the FDC into an undetectable error condition. More rigorous examples include a concurrent transfer of data to or from a network or tape drive using a high priority DMA channel while the diskette transfer is active. Clearly, the number of possible error producing examples is infinite, yet each is highly probable in this environment.
For all practical purposes the OS/2� and newer Windows� operating systems can be regarded as UNIX� derivatives. They suffer from the same problems that UNIX� does. Two significant differences exist between these operating systems and UNIX�.
First, they both semaphore video updates with diskette operations tending to avoid forcing the FDC problem to occur. However, any direct access to the video buffer, in either real or protected mode, during a diskette transfer will bypass this feature and result in the same faulty condition as UNIX�.
Second, OS/2� incorporates a unique command that tends to avoid the FDC problem by reading back every sector that is written to the floppy diskette in order to verify that the operation completed successfully. This command is an extension to the MODE command (MODE DSKT VER=ON). With these changes, data loss and/or data corruption should occur less frequently than otherwise. However, the FDC problem may still destroy data that is not related to the current sector operation.
A host of other operating systems are susceptible to the FDC problem just as DOS�, Windows�, Windows� 95, Windows� 98, Windows� NT, OS/2�, and UNIX�. However, these systems may not have an installed base as large as DOS�, Windows�, OS/2� or UNIX�, and may, therefore, receive less motivation to address the problem. Significantly, as long as the operating systems utilize the FDC and service system interrupts, the problem can manifest itself. This can occur in computer systems that use virtually any operating system.
Some in the computer industry have suggested that data corruption by the FDC is extremely rare and difficult to reproduce. This is similar to the argument presented during the highly publicized 1994 defective INTEL� Pentium� scenario. Error rate frequencies for the defective Pentium� ranged from microseconds to tens-of-thousands of years! The FDC problem is often very difficult to detect during normal operation because of its random characteristics. The only way to visibly detect this problem is to have the FDC corrupt data that is critical to the operation at hand. However, many locations on the diskette may be corrupted, yet not accessed. In connection with the instant invention, the FDC problem has been routinely reproduced and may be more common than heretofore believed.
Computer users may, in fact, experience this problem frequently and not even know about it. After formatting a diskette, for example, the system may inform the user that the diskette is bad, although the user finds that if the operation is performed again on the same diskette everything is fine. Similarly, a copied file may be unusable, and the computer user concludes that he or she just did something wrong. For many in this high-tech world, it is very difficult to believe that the machine is in error and not themselves. It remains typical, however, that full diskette back-ups are seldom restored, that all instructions in programs are seldom, if ever, executed, that diskette files seldom utilize all of the allocated space, and that less complex systems are less likely to exhibit the problem.
Additionally, the first of these faulty FDCs was shipped in the late 1970's. The devices were primarily used at that time in special-purpose operations in which the FDC problem would not normally be manifest. Today, on the other hand, the FDCs are incorporated into general-purpose computer systems that are capable of concurrent operation (multi-tasking or overlapped I/O). Thus, it is within today's environments that the problem is most likely to occur by having another operation delay a data transfer to a diskette. The more complex a computer system, the more likely it is that one activity will delay another, thereby creating an FDC error condition.
In short, the potential for data loss and/or data corruption is present in all computer systems that utilize the defective version of this type of FDC, presently estimated at about 50 million personal computers. The design flaw in the FDC causes data corruption to occur and manifest itself in the same manner as a destructive computer virus. Furthermore, because of its nature, this problem has the potential of rendering even secure databases absolutely useless.
Moreover, more recent FDC devices may be affected by the use of first-in-first-out (FIFO) devices that alter the usual operation. Whenever the FIFO is enabled, detection of the defective controller may be well nigh impossible. Nevertheless, when the FIFO is not enabled, due to the vagaries of some particular operating system or device driver, the defect may appear and cause data corruption.
Various conventional ways of addressing the FDC problem, such as a hardware recall, have significant associated costs, risks and/or disadvantages. In addition to a solution to the FDC problem, an apparatus and method are needed to accurately, rapidly, reliably, and correctly, identify any defective FDC. The identification of defective FDCs is the first step in attempting to solve the problem of defective FDCs. A solution method and apparatus for repairing a defective FDC are disclosed in U.S. Pat. No. 5,379,414 incorporated herein by reference.
In view of the foregoing, it is a primary object of the present invention to provide a method and apparatus for detecting defective Floppy Diskette Controllers ("FDCs").
It is another object of the present invention to provide a software (programmatic) solution that may be implemented in a general purpose digital computer, which eliminates the need for visual inspection and identification of the defective FDCs as well as the need for any hardware recall and replacement.
Consistent with the foregoing objects, and in accordance with the invention as embodied and broadly described herein, an apparatus and method are disclosed in one embodiment of the present invention as including data structures, executable modules, and hardware, implementing a detection method capable of immediately, repeatedly, correctly, and accurately detecting defective FDCs.
The apparatus and method may rely on 1) determining whether or not the FDC under test is a new model FDC (potentially non-defective), and 2) if the FDC under test is not a new model FDC, installing an interposer routine to force the FDC to delay a transfer of a last data byte of a sector either to or from the floppy diskette whose controller is tested. A test condition is thus created in the hardware to cause defective FDCs to corrupt the last data byte of the sector. A second portion of an apparatus and method may confirm a diagnosis. Thus the apparatus and method may ensure that old-model non-defective FDCs are not wrongly identified as defective.
Chips manufactured in recent years may have the data corrupting defect originally identified. Nevertheless, the defect may manifest itself in other ways. Meanwhile, the three needs remain. The failure of the chip needs to be detected, including navigation of the masking features that may limit an ability to detect FIFO-enabled chips. Second, correction of the defect in hardware, by using a software solution is needed. Finally, detection of corruption resulting from previous failures of a FIFO-enabled chip to detect errors will be required.
A system and method in accordance with the invention may be implemented to provide a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may think it knows what it is doing may try to control a hardware device, but may not know about a hardware issue, such as another process or a defect requiring that the device remain in a certain state.
The technique programmatically maintains a persistent hardware state independent of any other control software. To other software, the software layer of the invention is indistinguishable and inseparable from hardware. Nothing can slip in between. Anything insertion attempt will be detected and disallowed. Features of the processor or system chips actually weld the software to the hardware, which disallows any software intervention between the welded software layer and the hardware.
Various uses for this method may include making hardware persistently behave in a given fashion, in spite of ongoing requests from other software to reconfigure the underlying hardware behavior. This may provide a software-only solution to a hardware defect. One may extend hardware capability without replacing hardware, and without concern for insertion of other software layers that would program performance impermissibly if allowed to obtain conventional access, such as I/O port commands, memory-mapped I/O commands. Monitoring capability of access and control of an underlying hardware interface is also available.
One application of a method in accordance with the invention may provide a complete software implementation of overriding a detection process that is capable of detecting defective Floppy Diskette Controllers ("FDCs") without visual hardware inspection or identification. The approach taken includes a multi-phase strategy incorporating programmatic FDC identification, software DMA shadowing, defect inducement, and use of a software decoding network, all of which allows the implementation of the invention to adjust to a wide range of computer system performance levels.
A method and apparatus for detecting and preventing floppy diskette controller data transfer errors in computer systems is also provided. The approach taken may involve software DMA shadowing and the use of a software decoding network.
In certain embodiments, an apparatus for detecting a defective floppy diskette controller may comprise a computer readable medium storing executable and operational data structures. The data structures may include a determination module for identifying a hardware resource associated with a computer system, a welding module for inseparably connecting a persistent software layer to the hardware resource, and a defense module for resisting attempts by other software to unweld the persistent software layer from the hardware resource.
The apparatus may store data structures including a function module for performing a desired function whenever the hardware resource is accessed by the computer system. The function module may be configured to control the hardware resource to provide a function otherwise unavailable from the hardware resource as manufactured. The data structures may include an unweld module for disconnecting the persistent software layer from the hardware resource. The unweld module may be configured to be embedded in the welding module.
In at least one embodiment, a computer readable medium storing data structures may embody steps for effecting a method providing a computer system comprising a processor operably connected to a first hardware resource. It may include installing a driver corresponding to the first hardware resource, and including a resource identifier for identifying available hardware resources. Further the method may include identification of the processor, by the resource identifier, the first hardware resource and executing, on the processor, a welder to inseparably connect a persistent software layer.
The method may include accessing, by the processor, a first hardware interface and automatically engaging the persistent software layer upon accessing, by the processor, to the hardware interface. The method may provide a defense module for responding to attempts to unweld the persistent software layer from the first hardware interface, and provide a controller for controlling the first hardware resource.
The persistent software layer may have a function module, executable to perform an extension function, the extension function being beyond the inherent functionality of the controller. The extension function may have a function lock for overriding requests from other software to reconfigure the functionality of the first hardware resource. The function module may be configured to perform a function selected from detection and correction of a hardware defect in the controller.
The function module may be configured to extend the functional capability of at least one of the first hardware resource and the controller, without replacement thereof. The function module may be configured to monitor at least one of access and control of at least one of the first hardware device and the controller.
In one embodiment, a method for welding a software layer to a hardware layer in a computer system having hardware interfaces may include providing a computer system comprising a processor operably connected to a first hardware resource, with a first hardware interface corresponding to the first hardware resource. Then, the method may install a driver corresponding to the first hardware resource, and including a resource identifier for identifying available hardware resources. After identifying the first hardware resource, the method may execute on the processor a welder for inseparably connecting a persistent software layer.
The method may include accessing, by the processor, the first hardware interface; and automatically engaging the persistent software layer upon accessing, by the processor, the hardware interface. The persistent software layer may have included a function module configured to monitor at least one of access and control of at least one of the first hardware device and the controller. Inseparably connecting may result in rendering the connection unbreakable by other than the welder. Typically it will render substantially impossible an insertion of an executable between the first hardware resource and the persistent software layer.
The foregoing and other objects and features of the present invention will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only typical embodiments of the invention and are, therefore, not to be considered limiting of its scope, the invention will be described with additional specificity and detail through use of the accompanying drawings in which:
It will be readily understood that the components of the present invention, as generally described and illustrated in the Figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of the system apparatus and method of the present invention, as represented in
The presently preferred embodiments of the invention will be best understood by reference to the drawings, wherein like parts are designated by like numerals throughout.
The architecture of an apparatus 10, including a computer system implementing one embodiment of the invention, is illustrated in
In transferring data to a floppy diskette, the CPU 12 may program a Direct Memory Access ("DMA") controller 18 for an input/output ("I/O") transfer. The CPU 12 issues a command to a Floppy Diskette Controller ("FDC") 20 to begin the I/O transfer, and then waits for the FDC 20 to interrupt the CPU 12 with a completion interrupt signal. It is also possible to perform Programmed I/O ("PIO") directly between the CPU 10 and the FDC 20 without involving the DMA controller 18. This latter approach is seldom used; the majority of computer systems 10 employ DMA for I/O transfers to and from the floppy diskette drive 16. The invention will thus be described below with particular reference to the DMA controller 18. If PIO is employed, however, then an I/O transfer is totally controlled by the CPU 12 because the CPU 12 is required to pass each and every data byte to the FDC 16. As a result, the "DMA shadowing" system and method in accordance with the invention may be directly applied to a PIO data stream. This is readily tractable because the CPU 12 already is controlling the I/O transfer, as will become more readily apparent.
A computer system 10 may have a system clock 22. The system clock 22 is beneficial when initiating an I/O transfer to the diskette drive 16 because one must not only control the data transfer, but also a drive motor. In this regard, it is important to know when the diskette drive motor has brought a diskette's spin rate up to a nominal RPM required for a data transfer to be successful.
For example, in IBM� Personal Computers and "compatibles," the system clock 22 interrupts the CPU 12 at a rate of 18.2 times per second (roughly once every 54.9 milliseconds). This interrupt is used to determine such things as diskette drive motor start and stop time. There are also a host of other time-dependent operations in the computer system 10 that require this granularity of timing.
One presently preferred embodiment of an association between application programs 24 (executables), operating systems 26, device drivers and hardware is depicted in
A system suitable for implementing the invention may include an application program 24 including both executable code 25 a and associated data 25 b. The application 24 may interface with the hardware apparatus 10 through an operating system 26. The operating system may include a file system 27 a as well as selected buffers 27 b. The file system 27 a may include an executable for file system management as well as operating system interfacing. The file system 27 a may issue commands to drivers 28.
The drivers 28 may include a timer device driver 29 a, including a timer ISR, interfacing to the system clock 22. Likewise, a media drive driver 29 b, alternatively referred to as a media driver 29 b may be included. The media driver may interface with a floppy diskette drive or other media drive 16 to maintain persistent storage on media 17. Although a media drive 16 may typically relate to floppy diskettes, tape drives and other magnetic media may also be used in an apparatus and method in accordance with the invention.
The media driver 29 b may be responsible for sending instructions and control signals to the media drive controller 20, which is typically embodied as a floppy diskette controller 20. Similarly, the media driver 29 b may instruct and control the DMA controller 18. The DMA controller manages data transfers between the floppy diskette controller (FDC 20) and the main memory device 14. A DMA request (DRQ;DREQ 21 a) may pass from FDC controller 20 to the direct memory access controller 18 (DMA controller 18). Likewise, a DMA acknowledge 21 b or acknowledgment 21 b, alternatively referred to as a (DACK 21 b) may be returned from the DMA controller 18 to the FDC 20.
Referring now to
As will become more fully apparent from the following discussion, once a floppy write operation is detected, in a test 40 a software decoding network call vector of the timer interrupt 54 (see
This delay 60 forces defective FDCs 20 into an undetected data corruption condition. This condition can be tested 120 by reading back 118 the written data to see whether the last byte or the next-to-the-last byte was actually written to the last byte location of the sector.
Referring again to
One could allow the timer 22 (clock 22) to always interrupt at the accelerated rate. Then, a check the timer Interrupt Service Routine ("ISR") 29 c (see
As used herein, "DMA shadowing" may be thought of as programmatic CPU 12 monitoring of data (byte) transfers and timing the last byte of a sector's DREQ 21 a to DACK 21 b signals. Importantly, there are, of course, a number of ways of determining when the DREQ 21 a is present and when the DACK 21 b is present. The present invention may include the use of any "DMA shadowing" whether the DREQ 21 a and DACK 21 b signals are detected at the DMA controller 18, CPU 12, system bus 15 or FDC 20. This includes both explicit means, and implicit means.
For example, inferring the state of the DREQ/DACK cycle is possible from various components in the system that are triggered or reset from transitions of such signals 21 a, 21 b. In one embodiment the DACK 21 b may cause a Terminal Count ("TC") signal to be asserted by the DMA controller 18. Therefore, one may imply from the detection of the TC that a DACK 21 b has occurred.
Whenever an application 24 requests a write operation of the media drive 16, the system clock 22 may be reprogrammed to interrupt, for example, every 4 to 7 milliseconds. Referring again to
Therefore, defective FDCs 20 are forced into an undetected data corruption state. This state may be detected by writing known data patterns to the next-to-the-last and the last data bytes. Reading the data back will reveal which of the two data bytes was stored in the last byte of the sector. Finally, it is possible to also detect defective FDCs 20 by significantly increasing the delay time during the transfer of the last byte of a sector. This forces the next physically adjacent sector to be zeroed out except for the first byte of that sector.
For the system to maintain proper operation, an interposer routine 34 should save the original INT 0x13 (Hex 13th interrupt vector) contents (address of the original INT 0x13 Interrupt Service Routine) and invoke the original when necessary. Additional aspects of the interposer function 34 are discussed below in connection with other features of the device driver 29 b.
This implementation of the apparatus and method of the present invention is contemplated for use on an IBM� Personal Computer running the PC/MS-DOS� operating system. Versions have, however, been developed to operate in the Windows�, OS/2� and UNIX� environments and may be embodied for other operating systems. The invention is not limited to use with any particular operating system, and adaptations and changes which may be required for use with other operating systems will be readily apparent to those of ordinary skill in the art.
As depicted graphically in
Referring to
Although the steps 56, 58 of the module 54 may be implemented with the timer 22 continually interrupting every 8, 16, or 32 microseconds. This level of interrupts may totally consume a PC's processing power, and on most PCs could not be sustained. Thus, in order to perform DMA shadowing without affecting the total system performance it is important to allow normal operations to continue as usual. It is desirable to have an interrupt (the system clock 22) that will interrupt close to the end of the sector transfer so that the DREQ 21 a to DACK 21 b timing may be determined on the last byte of the sector transfer.
Thus, it is possible to DMA shadow 58 all 512 bytes during a sector transfer, but that would cause the CPU to be totally consumed during the entire sector transfer time. The potential of losing processing activities elsewhere in the system are greatly increased, as in serial communications. Therefore, the clock interrupt routine 29 c or method 29 c of
One operation performed in the timer ISR routine 29 c is to vector through the software decoding network 72 to the appropriate processing routine 84, 86, 88. This process is illustrated graphically in
The timer interrupt rate can now be in terms of 10's or 100's of byte transfer times. The vector table 72 may cause the program execution of the CPU 12 to enter a cascade 86 of DREQ 21 a/DACK 21 b checks only when the transfer (sector) will complete prior to the next timer interrupt. In short, the first entries 74 in the vector table 72 will return 84, since another timer interrupt will occur before the sector transfer completes. The latter entries 80, within the desired range, will cascade 86 from one DREQ 21 a/DACK 21 b detection to another (shadowing 58 the DMA transfers) until the last byte is transferred.
On the last byte being transferred, the data byte may be delayed by either activating a higher priority DMA 18 channel or masking the DMA channel of the FDC 20. Although these two techniques are the simplest to program, numerous alternatives may be used to delay 60 data transfers on the DMA 18 channel of the FDC 20, in accordance with the invention.
This software decoding network process 54 is the fastest known software technique for decoding and executing time-dependent situations. Space in the memory space 14 (e.g., the software decoding network vector table 72) is traded for processing time, the amount of time it would take for one routine to subsume all functionality encoded in each of the routines 84, 86, 88 vectored to through the software decoding network vector table 72.
As indicated above, the entire software decoding network table 72 may be initially set to the address of an "exiting routine 84." Then depending upon how slow or fast the system clock 22 interrupts, a certain number of the lower-indexed entries 80 of the table 72 may be set to the address of a processing routine 86. These processing routines 86 may be identical and sequentially located in the routine 54. Thus, the software decoding network vector table 72 may simply vector the timer ISR routine 29 c within the driver 29 a to the first of n sequentially executed processing routines. Here, n represents the number of bytes remaining in the sector transfer. In this way the last few bytes of the sector transfer can be accurately monitored (DMA Shadowing 58) without significantly affecting overall system performance.
Each of the processing routines 86, except the last one 88, may perform exactly the same function. It is not necessary to be concerned with the timing between the DREQ 21 a and DACK 21 b signals until the very last data byte of a transfer. Therefore, the routines 86, 88 above "shadow" 58 the operation of the DMA until the last byte (e.g., corresponding to entry 82 of the vector 72) at which time the DMA channel of the FDC 20 is delayed as previously described.
Thus, through software DMA shadowing, it is possible to reliably determine when the last byte of the transfer is about to be transferred. Therefore, it is possible to force the last data byte's transfer to be delayed. An alternative approach may include a specialized application program 24 to control all aspects of the operation of the media drive 16, e.g., floppy diskette drive 16. This may include a transfer delay of a last byte, as indicated in
Referring now to
Thus, a test 104 does not actually determine whether or not the status of an FDC 20 is defective. A negative response instead may be saved 105 to establish false negative responses programmed in by manufacturers. The display step 106 may include selected post processing to output results of the application 24. Results may include, for example, an indication of whether the FDC 20 being tested is defective or not and whether a false negative response was given to test 104, in view of the results of the test 112. Accordingly, a status not equal to a hex 80 would ordinarily result in the test 104 signifying that an FDC 20 is not defective. The steps 105, 106 thereafter verify defectiveness and improper circumvention of the test 104.
After to the test 104, the application 24 advances to a hook 110. The hook 110 is effective to interpose a timer prefix 124 (see
A test pattern 112 may format the last few (for example, 10) bytes of a sector write buffer 27 b. Any known pattern may suffice, for example, a sequential list of all digits from zero to nine may be used. Importantly, the last two digits in such a sequence should be distinct. Thus, a string "0123456789" may provide a test pattern to be written in the last ten bytes of a sector. The test pattern may then be written from a buffer 27 b to a medium 17 using the BIOS interface for the medium 17 and medium drive 16.
Following the test pattern 112, a test 114 may determine whether or not a write error has occurred in writing the buffer 27 b to the medium 17. A positive response to the test 114 results in an increment step 116. The increment 116 tracks the number of successful detections of errors. Thus, the increment 116 indicates that another write error was successfully detected by the FDC 20. Accordingly, the application 24 may advance from the increment 116 to a test 117. A test 117 may determine the number of sectors to which the FDC 20 has attempted to write. If the response to the comparison of the test 117 is positive, then all tests are completed and the display step 106 follows. On the contrary, a negative response to this test 117 returns the application 24 to the test pattern 112, initiating another test cycle.
A negative response to the test 114 indicates that a write error, known to exist, was undetected by the FDC 20. Accordingly, a negative response to the test 114 advances the application 24 to a read 118. The read 118 reads back the last previously written sector, using the BIOS diskette interface, such as the driver 29 b. The step 118 may then increment the number corresponding to sectors that the FDC 20 has attempted to write.
The application 24 may next advance to the test 120 to determine whether the last byte that the read step 118 has read back from the written sector to a buffer 27 b is the last, or the next-to-last element of the test pattern from the test pattern step 112. That is, for example, in the example above, the test 120 determines whether or not the last byte read back to the buffer 27 b from this sector being tested is correct (e.g., 9, a value other than 9 indicates that the FDC has failed to write the tenth element of the test pattern into the last byte location of the sector). This indicates that the FDC has not indicated a write error in the test 114, and yet has produced the error detected by the test 120. Thus, the last sector written is corrupted.
A negative response to the test 120 indicates that the last byte was not incorrectly written. Accordingly, the application 24 may advance to the test 117 to determine whether or not the testing is completed. A positive response to the test 120 results in an increment step 122. The increment step 122 advances the count of undetected errors found during the operation of the FDC 20 during the testing in question. Thus, a step 122 results in a corruption count for sectors attempted to be written by the FDC 20.
Referring now to
The prefix 124 may begin with a read 126 effective to determine a count corresponding to the number of bytes, or a countdown of the remaining bytes, being transferred by the DMA controller 18 from the main memory 14, through the buffer 27 b to the FDC 20. The read 126 may also include a reading of a count (a tick count) of a timer 22 or system clock 22.
Following the read 126, a test 128 may determine whether or not an operation is in process affecting the FDC 20. The FDC 20 is in operation if a count kept by the DMA controller 18 has decremented (changed) within an elapsed time corresponding to the maximum time required for a byte to be transferred. If no change has occurred during that elapsed time, then one may deduce that no activity is occurring. Accordingly, a negative response to the test 128 results in reexecution of the test 128. Reexecution of the test 128 may continue until a positive response is obtained. Inasmuch as the application 24 is executing a write during the test pattern 112, an eventual positive response to the test 128 is assured. In one embodiment of an apparatus and method in accordance with the invention, the first byte transferred may typically be detected.
A positive response to the test 128 advances the prefix routine 124 to a test 130 to test the countdown or count of the DMA controller 18. The test 128 corresponds to detection of activity, whereas the test 130 corresponds to iteration of a shadowing process.
The test 130, whenever a negative response is received, may advance the prefix routine 124 to the exit 138.
On the other hand, a positive response to the test 130 advances the prefix routine 124 to a test 132 effective to evaluate whether or not the countdown is within some selected range at the end of a sector. A negative response to the test 132 indicates that the countdown is not within some desired end-of-sector range, so the prefix routine 124 should exit 138 without waiting longer. That is, interrupts will continue to occur with a frequency that will detect the desired range at the end of the sector being tested.
A positive response to the test 132 advances the prefix routine 124 to a test 134 for detecting the last byte to be transferred in a sector. If the DMA controller 18 is not counting the last byte to be transferred, then the test 134 may simply continue to test. When the countdown of the DMA controller 18 reaches a value of zero, a positive response to the test 134 advances to a delay step 136.
The delay step 136 corresponds to the delay 60 illustrated in
Referring to
Meanwhile, referring to
Referring to
By contrast, if the test 156 results in a device that is at least as current, or more current than a P5 architecture, then identifying 160 the floppy diskette controller is useful. The identifying step 160 corresponds to a floppy diskette controller, which may control more than floppy diskette types of media. After identifying 160 the nature of the floppy diskette controller (FDC), a test 162 determines whether or not the FDC operates with FIFO enablement. If not, then a do-not-install step 164 follows.
Otherwise, for FIFO-enabled FDCs, a save step 166 saves the content from a control register no. 4 (CR4). Next, the bit assigned to the CR4.DE location is set 168. By the setting 168, the save step 166 is effectively required. Otherwise, the setting step 168 destroys irretrievably the contents of the CR4, control register no. 4, contents.
A saving step 170 saves to another location the contents of the debug register no. 7 (DR7). The saving step 170 may also save debug register no. 3 (DR3). Saving 172 an original interrupt service routine, associated with a first interrupt, then provides installation 174 of a new or alternative interrupt service routine (ISR).
In the installing step 174, a setting step 176 may set the FIFO to an "on" state if executing a solution to the read/write defect of an FDC. The solution represents a curing of the hardware defect of the chip by operating the software solution as described above. Alternatively, setting 178 the FIFO to an "off" state is used for the detection process. The detection process is the determination of whether or not the subject chip has the hardware defect detected and solved by the instant invention.
Following installation 174, a setting step 180 sets values of various debug registers in sequence. For example, a global protect may be set, followed by a global use of a Break Point Register no. 3 (BP3). Thereafter, a binary value of 10 may be set for purposes of controlling input and output. Then, a single byte may be set for a length (LEN3). Finally, an input and output port may be set using the debug register (DR3). Thereafter, the process 150 may return 181.
Referring to
Referring to
Referring to
Referring to
Thereafter, a test 204 determines whether the next instruction contains a first byte value designated by the test 204. For example, the testing value may be 0x0F. This value corresponds to 0000 1111 in binary. If the test 204 is negative, then invocation 199 occurs. Otherwise, the test 206 determines whether or not the second byte has a test value. In one embodiment, the test value is 0x23. This corresponds to a binary value of 0010 0011, which indicated an attempt to write to one of the debug registers.
Again, if a test 206 results in a negative response, then invocation 199 is appropriate. Otherwise, a test 208 directed to the third byte anded with 0x38 determines whether the value is 0x18. This process effectively takes the form of 11ee errr indicating that debug register 3 is the target register. If the response to the test 208 is positive, then the incrementing step 210 follows. The incrementing step 210 increments past the next instruction, thus, repelling an attempt to modify DR3 (unweld). The value of the register EIP plus 3 is loaded into the register EIP because the instruction is three bytes long.
If the results of the test 208 are negative, then a test 212 determines whether or not the third byte anded with 0x38 has a value of 0x38. If not, then the invocation 199 occurs again. However, a positive result to the test 212 means that a debug register 7 (DR7) is the target register. Thereafter, the incrementing step 210 proceeds as described above. Following the incrementing step 210, a return 214 from the interrupt returns the processing to its previous state.
Referring to
Otherwise, a positive response leads to an issuing step 224 to issue a configure command. This configure command turns on or enables the FIFO. The issuing step 224 may include turning 226 or activating 226 the FIFO to a state of "on" if the solution process is the subject of interest. If, on the other hand, detection of the presence of the error solved by the invention is the issue, then the FIFO may be turned off 228. Turning the FIFO off 228 is important for providing the timing required in order to properly detect the presence of the design flaw in the hardware.
Thereafter, a resetting step 230 resets the configure command flag, after which a return 232 returns control of the system from the interrupt.
Referring to
Referring to
The invention described heretofore provides a detection solution that may be completely implemented in software as a device driver 29 b that is capable of detecting defective FDCs 20 without visual inspection and identification of the FDCs. Furthermore, the unique and innovative approach taken, allows the implementation of the invention to accurately and correctly detect defective FDCs even when non-defective old-model FDCs are involved. Simply stated, it is not sufficient to determine whether the FDC under test is an old or new model FDC. Various vendors manufactured old-model FDCs that are not defective. Therefore, a two-phase detection process may correctly determine whether or not the FDC under test is defective.
The number of FDCs installed in computer systems today is well over 100 million. In order to identify defective FDCs, vendors and consumers that have defective FDCs 20 installed have very few alternatives (e.g., recalls; replacement), of which most are extremely costly, for determining whether or not their systems are susceptible to the data corruption presented by defective FDCs 20. Therefore, an apparatus and method that may be implemented as a software-only solution to this problem is a significant advance in the computer industry. Moreover, the robust design allows the apparatus and method of the present invention to address processor speeds that encompass the original IBM�Personal Computers executing at 4.77 MHZ to the latest workstations that execute at well over 1 GHZ.
The function of transfer of data to devices controlled by the FDC is described above in one embodiment as occurring through direct memory access (DMA). Nevertheless, this function may be accomplished with any suitable memory controller or other manner of data transfer. For example, one manner disclosed above involving a memory controller other than a DMA includes programmed input and output (I/O) accomplished directly by the microprocessor. Thus, in this instance, one skilled in the art will understand that in the discussion above, where a DMA is used, programmed I/O or other types of memory controllers may be readily substituted.
A further aspect of the present invention involves specific implementations of a method for detecting and preventing floppy diskette controller data transfer errors in computer systems. One embodiment of the method has been included by incorporating by reference U.S. Pat. No. 5,379,414 issued to Phillip M. Adams on Jan. 3, 1995. Another embodiment of the method has been included by incorporating by reference U.S. Pat. No. 5,983,002
One such specific implementation involves substituting a magnetic tape back-up device or an optical device, or other such peripheral, non-volatile memory device for the floppy drive previously described in the specific embodiment of the method. In so doing, the method substantially as disclosed is employed, substituting the use of the alternate peripheral, non-volatile memory device for the floppy drive. Appropriate commands are also substituted, as would be readily apparent to one skilled in the pertinent art.
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative, and not restrictive. The scope of the invention is, therefore, indicated by the appended claims, rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
|Cited Patent
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|Fortune Systems Corporation
|Data processing system having automatic configuration
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|Data General Corporation
|Unique process for loading a microcode control store in a data processing system
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|Emulation of a data processing system
|Apr 10, 1985
|Oct 18, 1988
|Microsoft Corporation
|Method and operating system for executing programs in a multi-mode microprocessor
|Oct 14, 1987
|Dec 19, 1989
|Little Blue Limited Partnership
|Peripheral device interface and controller
|Feb 7, 1989
|Jul 17, 1990
|Compaq Computer Corporation
|Computer with improved keyboard password functions
|Aug 26, 1988
|Feb 26, 1991
|Stac Electronics
|Write operation with gating capability
|Mar 22, 1990
|Oct 29, 1991
|Xerox Corporation
|System for managing data which is accessible by file address or disk address via a disk track map
|May 31, 1991
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|United Technologies Corporation
|Serial data transmission between redundant channels
|Feb 14, 1989
|Apr 14, 1992
|Hitachi, Ltd.
|Data storage apparatus
|Feb 10, 1992
|May 18, 1993
|California Institute Of Technology
|Programmable DMA controller
|Jan 22, 1992
|Aug 3, 1993
|Micro Technology, Inc.
|Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
|Oct 31, 1990
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|Control Data Systems, Inc.
|Processor communication bus
|Dec 17, 1991
|May 17, 1994
|Jeffries Kenneth L
|Disk drive array with request fragmentation
|Dec 17, 1991
|May 17, 1994
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|Disk drive array with efficient background rebuilding
|Jul 10, 1992
|Jan 3, 1995
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|Systems and methods for FDC error detection and prevention
|Oct 30, 1992
|May 16, 1995
|Intel Corporation
|Method and apparatus for improving data failure rate testing for memory arrays
|Aug 2, 1994
|Jun 6, 1995
|Texas Instruments Incorporated
|Integrated circuit test arrangement and method for maximizing the use of tester comparator circuitry to economically test wide data I/O memory devices
|Jan 31, 1992
|Sep 12, 1995
|Adaptec, Inc.
|Intelligent hardware for automatically controlling buffer memory storage space in a disk drive
|Mar 28, 1994
|Dec 5, 1995
|Dell Usa, L.P.
|Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests
|Dec 17, 1991
|Jan 9, 1996
|Dell Usa, L.P.
|System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities
|Mar 14, 1994
|Apr 9, 1996
|Dell Usa, L.P.
|Method and controller for minimizing reads during partial stripe write operations to a disk drive
|Aug 3, 1994
|Jul 23, 1996
|Bi-Search Corporation
|Method and structure for using defective unrepairable semiconductor memory
|Dec 23, 1994
|Apr 8, 1997
|Emc Corporation
|Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device
|Oct 11, 1996
|Nov 9, 1999
|Phillip M. Adams & Associates, L.L.C.
|Defective floppy diskette controller detection apparatus and method
|Dec 22, 1995
|May 9, 2000
|Compaq Computer Corporation
|Method and apparatus for synchronizing a serial bus clock to a serial bus function clock
|Dec 31, 1997
|Aug 8, 2000
|Samsung Electronics Co., Ltd.
|Method for improving access performance on track with re-allocation sector in a hard disk drive
|Sep 14, 1998
|Feb 27, 2001
|Phillip M. Adams
|Data corruption detection apparatus and method
|Dec 14, 1998
|Jun 4, 2002
|Phillip M. Adams
|Defective floppy diskette controller detection apparatus and method
|Apr 13, 1999
|Jun 11, 2002
|Hewlett-Packard Company
|System and method for recovery from address errors
|May 16, 2000
|Feb 3, 2004
|Phillip M. Adams
|Software-hardware welding system
|Oct 25, 2000
|Apr 27, 2004
|Seagate Technology Llc
|Disc drive with delayed reassignment write
|Jun 22, 2006
|Aug 5, 2008
|Phillip M. Adams & Associates, L.L.C.
|Read-write function separation apparatus and method
|Adams, P.M., Nova University, Department of Computer Science, "Hardware-Induced Data Virus," Technical Report TR-881101-1 (U.S.A., Nov. 14, 1988).
|Advanced Military Computing, "Hardware Virus Threatens Databases," vol. 4, No. 25, pp. 1 & 8 (U.S.A. Dec. 5, 1988).
|Intel Corporation, "8237A/8237A-4/8237A-5 High Performance Programmable DMA Controller" (U.S.A., date unknown) pp. 2-52 to2-67.
|Intel Corporation, "8272A Single/Double Density Floppy Disk Controller" (U.S.A., date unknown) pp. 6-478 to 6-491.
|Intel Corporation, Letter to customers from Jim Sleezer, Product Manager, with attachments, regarding FDC error and possible solutions (U.S.A., May 2, 1988).
|NEC Electronics, Inc., "IBM-NEC Meeting for muPD765A/muPD72065 Problem" (U.S.A., May 1987).
|NEC Electronics, Inc., "IBM-NEC Meeting for μPD765A/μPD72065 Problem" (U.S.A., May 1987).
|Citing Patent
|Filing date
|Publication date
|Feb 13, 2012
|Mar 4, 2014
|Aftg-Tg, Llc
|Software-hardware read/write integrity verification system
|Feb 13, 2012
|Aug 9, 2012
|Phillip M. Adams & Associates, L.L.C.
|Software-hardware welding system
|U.S. Classification
|714/42, 714/47.1
|International Classification
|Cooperative Classification
|European Classification
|Oct 28, 2010
Owner name: AFTG-TG, L.L.C., UTAH
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADAMS, PHILLIP M;REEL/FRAME:025213/0453
Effective date: 20040826
Owner name: PHILLIP M. ADAMS & ASSOCIATES, L.L.C., UTAH
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AFTG-TG, LLC;REEL/FRAME:025213/0814
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|Apr 16, 2015
|Fee payment
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text:
Geeky Feeds
by: Wolf Mountain Apps • 78
All Android applications categories
by: Wolf Mountain Apps • 78
RSS feed reader for popular technology news feeds, such as:
- ArsTechnica
- Gizmodo
- Lifehacker
- Mashable
- NY Times (Technology)
- PC Magazine
- Slashdot
- TechCrunch
- Techdirt
- The Register
- Wired
Note that this is an RSS feeds reader -- you can view the title, description, and date/time of publication for each RSS feed item. To view the full details of a corresponding news story, the browser is opened to the respective webpage.
NOTE: Twitter has discontinued RSS feed support.
- Select the 'Reader' tab for a presentation of the current feed's items.
- Select the 'Feeds' tab for a list of selectable feeds from various sources.
- Select the 'Favorites' tab for a list of your stored favorites.
- Select the 'Settings' tab to view and edit preferences.
Press and hold any feed item, feed, or favorite for additional options.
Feed items can be opened in your browser, and they can also be shared. A given feed can be set as the feed to be shown at startup, and it can be added to your 'Favorites' list.
Feed items previously loaded over 1 hour prior may be hidden by using the 'Hide Older' menu, and hiding older feed items can be the default through checking the corresponding 'Settings' tab item.
Wolf Mountain Apps has no affiliation with the feed providers. All trademarks, logos, and copyrights are the property of their respective owners. We do our best to present the feeds with sufficient fidelity, so please contact us if you believe our feed presentation has errors.
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text:
Research carried out on people considered to be high risk has led to hopes that treatment could be offered to help prevent the onset of the disease.
Experts at the University of Edinburgh have been tracking a group of more than 150 people with a high risk of developing schizophrenia since 1994.
The individuals, who come from all over Scotland, were considered high risk as they had two or more close relatives with the disease.
Since the study began, 20 of the group have gone on to develop schizophrenia.
Psychiatrists compared them with the rest and found clear differences which they claim may be used to help identify the condition at an early stage.
Professor Eve Johnstone, of the university's department of psychiatry, said the research identified 38 different factors between the high risk individuals who have developed schizophrenia and those who had less severe symptoms or who remained completely well.
She added that changes were found in the function and anatomy of their brain and said it was also shown that those who develop the disease suffer from much higher levels of anxiety, depression and memory loss prior to falling ill.
"If we could treat the anxiety, the depression and the memory loss, we may be able to hold them in a state of vulnerability, but in a way that stops the individual cards from falling and bringing the whole house down," she said.
Dr Stephen Lawrie, who was also involved in the research, claimed it may one day be possible to run a diagnostic test for schizophrenia.
"We may be able to detect this condition years in advance which will allow us to use interventions to prevent these patients becoming ill with what has been described as the worst disease affecting mankind."


text:
Whey protein may help overweight individuals lose weight and burn more fat, according to a new clinical trial presented April 2 at the Experimental Biology meeting in
During the study, researchers provided whey protein, soy protein or carbohydrate supplements to 90 overweight and obese, but otherwise healthy individuals. Study participants were randomly assigned to one of three treatment groups: 1) 60 grams per day of whey protein, 2) 60 grams per day of soy protein or 3) a control group receiving 60 grams per day of carbohydrate. All participants were instructed to incorporate the supplement into their normal diet. Body composition and weight were measured weekly.
The results, presented by USDA researchers, found that individuals who ate supplemental whey protein for six months weighed about 4 pounds less and had about 5 pounds less body fat than individuals who consumed a carbohydrate supplement. The change in body weight was associated with a decrease in body fat without a significant loss in lean body mass. In addition, the whey-protein group lost more inches around the waist than the carbohydrate group.
Body weight was not different between the whey and soy-protein groups. However, the whey group lost more inches around the waist than the soy group.
"The findings of this study add to our knowledge about the health benefits of whey protein," commented David Baer, USDA researcher. "It's noteworthy that people who consumed whey protein daily, without any additional exercise or caloric restriction, still had a smaller waist circumference at the end of the study compared to the other groups."
"While research is still emerging on this topic, the results of this study support existing research, suggesting that whey protein may improve body composition by preserving lean body mass and promoting fat loss," said Joseph O'Donnell, executive director of the California Dairy Research Foundation (CDRF) and chairman of the U.S. Whey Protein Research Consortium. The consortium provided funding for the study.


text:
Support and Networking at USU
USU offers a range of supportive services for students enrolled in the traditional on-campus programs and for students utilizing online and distance courses. Please contact the USU Veterans Resource office to discuss your individual needs or check out the information listed below to learn more about individual programs.
Unfortunately, not all programs are available at every USU location across the state. If you will contact the USU Veterans Resource Office at 435-797-7886, we will do our best to point you in the right direction.


text:
Student Spotlight: Michael Johnson
Editor's note: Michael Johnson is now a lecturer for the School of Nursing.
Recent master's degree recipient Michael Johnson was named the School of Nursing's outstanding graduate for the fall semester.
Johnson was also one of just five students honored as a UNLV Outstanding Graduate at the December commencement. He earned his master's degree in nursing with a 3.9 GPA.
Johnson now plans to pursue his doctorate in nursing and was hired to teach clinical courses in mental health at UNLV this spring.
Johnson's master's thesis made a significant contribution to research on one of the most underserved populations in any nursing setting -- the lesbian, gay, bisexual and transgender community. His thesis is being considered for publication in the academic journal "Advances in Nursing Sciences."
"There's a lot of stigma still attached to the gay/lesbian/transgender community, and they may not be receiving the same quality of care as other patients," Johnson said. "This population is more susceptible to health disparities such as depression, suicide and risky sexual behaviors."
Johnson said he strives to shed light on improving the healthcare of underserved populations through teaching and research.
Johnson also works as a pediatric critical care nurse who specializes in nephrology.


text:
I must be honest, I am not particularly pleased with my final artefact. I like the images and the arrangement but the quality of the photo book hasn't lived up to my expectations. The pages aren't aligned accurately, there are some glue smears on the pages, the spine of the cover is slightly too big and the print quality of the images are pretty poor. I printed the images on my computer at home on cartridge paper, a really bad idea. I now know never to do this again. I only did this because I didn't want to stick the actual photos in as I felt it would look too much like a scrapbook. I would like to remake the book, but instead of printing myself, I would go to the print bureau to get quality images printed onto better quality paper with a nicer finish. I would then construct the book again, being careful of applying glue and keeping surfaces clean.
The smaller book I made before hand as a trial was better quality than my final photo book. This could be because the first book I made was considerably smaller and had less room for error. I do prefer smaller books, so may make it smaller in the future.
But I didn't get as much time creating the object as I would have liked. I had only a couple of days to complete it as I could only get the opportunity to have assistance in editing down days after I had completed my images. So for the amount of time I had to create the book, I think I did okay.
I definitely think that presenting my work in a book works well, but the nature of my work can transfer to numerous ways of presenting, I think. I am considering making a photo film, but I had done this before for other modules and wanted to try something new, hence why I am submitting a book.
Overall, I am pleased with the images I have created. I think I convey the story I am trying to get across, well that was the impression I got when I presented the images to my peers and they all understood what was happening in them. This was a huge relief. I have a habit of over thinking an idea and going way off the point. This is something that I am learning to control now. I have found that it is better to keep an idea simple, as too much of an idea only allows for more confusion if not conveyed properly.
This body of work has certainly given me new ideas. I think this is only the start. I would like to play around over the summer with the images I have and different ways of presenting.


text:
One of the most exciting players we signed in January is 23 year-old Moussa Sissoko, and he played some excellent games for Newcastle this year, especially at the start of his time on Tyneside, before getting injured and missing the last few games of the season.
Moussa Sissoko – getting back in the swing of things yesterday
But Moussa was back in Newcastle yesterday, getting back into the swing of things and the 6'2″ powerhouse is hoping he can have a good season coming up, so he can make the French World Cup squad for Brazil next summer.
"The manager played me as a number ten for a large part of last season and I'm very happy to play there. But next season we'll see what happens. We'll see what the manager wants, see where he wants me to play."
"I'll try and adapt the best I can but the objective for me is just to come out and have a good season personally because next summer is a World Cup year." "So I want to try and play well."
"I'll be motivated so I can get into a good position personally to try and attack the French national team and get into the squad." "I have rested up to make sure I come back on top form."
Of course Moussa can play in a number of different positions, and while at Toulouse he played a lot of the time as the defensive midfielder, all 6'2″ of him, but as Moussa Sissoko says Alan Pardew played him in an attacking number 10 position last season.
That was because we had so little threat up front on goal, after we didn't replace Demba Ba in January.
But it's a good question as what position is Moussa's best position, but he was a tremendous buy for the club, and we expect this lad to be a big success on Tyneside in the coming season, after seeing glimpses of what is capable of earlier this year.
Wonder how his English is coming along?
Comments welcome.
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You can also reach Ed at firstname.lastname@example.com


text:
It was a familiar feeling to Austin Ovard, as if defeat was looming once again for the Snow Canyon baseball team.
Just a year before, the Warriors had dropped a pair of crushing losses to finish runner-up to Spanish Fork in the Class 4A championship. This season, in the 3A title match, Juan Diego had forced a second game. Everyone in the Snow Canyon dugout seemed tense.
"It felt like last year," Ovard says. "For me, it was just about avoiding the past. We had to come together and make sure it didn't happen again."
The senior shortstop and pitcher very much took Snow Canyon's season into his own hands, getting a crucial hit that led to a tying run in the second game, scoring the winning run himself and adding two RBIs in a later inning for insurance. He also pitched two shutout innings to clinch the title, completing a performance worthy of The Tribune's 3A MVP award.
But it was far from two games that defined Ovard's season. He was the team's top hitting threat, batting .417 and knocking in 34 runs for the year, but he also pitched for a 6-1 record with a 1.58 ERA and 51 strikeouts against only eight walks.
For a team that needed leadership when it was forced to forfeit games because of an ineligible player, Ovard was the Warriors' man.
"We took that pretty hard at first, but it brought us together," he says. "In the long run, we had been in must-win situations before, so it helped us relax when the championship was on the line."