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Indulge the skin with the Tata Harper Redefining Body Balm a bio-technology body treatment to prevent and minimize the appearance of unwanted stretch marks, provide deep hydration, and leave the skin feeling softened and healed.
By ensuring a toned, defined look, this treatment awakens, rejuvenates and renews the skin.
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Natural and organic skincare ingredients of:
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Handmade in the USA. Certified by EcoCert. This product is not suitable for vegans.
Tata Harper products are gluten free and certified cruelty free.
Can be used anywhere on the body.
Use daily, on areas where stretch marks or elasticity are a concern or all over as an intensive treatment.
Apply the Redefining Body Balm to any area of the body and massage in circular motions.
Safe to use during pregnancy.
Butyrospermum Parkii (Shea) Butter, Rosa Canina Seed extract*, Shea Butter Ethyl Esters, Mangifera Indica (kokum) Seed Butter*, Copernicia Cerifera Cera*, Astrocaryum Murumuru*, Theobroma Grandiflorum Seed Butter*, Cera Alba (Beeswax)*, Camellia sinensis (Green Tea) seed oil*, Olea europea (Olive) Oil*, Theobroma Cacao*, Mangifera Indica (Mango) Seed Butter, Sambucus Nigra Fruit Extract, Dipalmitoyl Hydroxyproline, Caprylic/Capric Triglyceride, Aroma**, Euterpe oleracea (Acai) fruit oil, Phenethyl Alcohol, Calophyllum Inophyllum Seed Oil*, Arnica montana (Arnica) Extract*, Borago officinalis (Borage) Leaf Extract*, Medicago sativa (Alfalfa) Extract*, ilipendula Ulnaria (Meadowsweet) Extract*, Calendula officinalis (Calendula) Flower Extract*, Algae extract, Tocopherol, Limonene, Linalool *Ingredients from Organic farming ** Clinical grade essential oils blend
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The world´s audiovisual content market
Created31 Oct 2006
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MIPCOM is the global content event for co-producing, buying, selling, financing and distributing entertainment content across all platforms. It provides the key decision-makers in the TV, digital and audiovisual content industry with the only forum to network, discover future trends and trade content rights on a global level. The 22nd edition of MIPCOM reported the highest-ever number of participants with 12,509 delegates, representing a 7% increase on 2005. MIPCOM 2006 also reached a new record in terms of participating companies with 4,216 from 98 countries attending the market, an 8% increase compared to the 3,896 companies present last year. The number of buyers rose 10% and a total of 3,847 acquisition heads attended Cannes compared to 3,504 in 2005.

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By Martin Kasindorf, USA TODAY
LOS ANGELES The nation Friday begins six days of farewells to President Gerald Ford in state funeral ceremonies stretching from the California desert to the U.S. Capitol and a Michigan hillside.
Ford, the 38th president and the longest-lived former president, died Tuesday at age 93 at his home in Rancho Mirage, Calif.
Observances are scheduled to begin with a private prayer ceremony for the Ford family at St. Margaret's Episcopal Church in Palm Desert, Calif., where Ford and his wife, Betty, worshiped together for 29 years. From 4 p.m. today to 8 a.m. Saturday, the public is to be admitted to view the closed casket.
MORE: Ford funeral schedule
A military plane will fly Ford's remains Saturday to Andrews Air Force Base, Md. At dusk, a hearse will transport the casket in a motorcade to the Capitol, pausing at the National World War II Memorial to honor Ford's wartime service. After a funeral in the Capitol Rotunda, Ford will lie in state there through Monday night. The National Park Service says the public can expect to wait for up to six hours.
Ford's body will be taken to Washington National Cathedral for services Tuesday. The U.S. Army Military District of Washington says that "at family request" the flag-draped casket will travel in a hearse, not on the artillery caisson that carried presidents Ronald Reagan in 2004, Lyndon Johnson in 1973, Dwight Eisenhower in 1969 and John Kennedy in 1963.
The casket will go from the cathedral later Tuesday to the Ford presidential museum in Grand Rapids, Mich. The body will lie in public repose through the night. Funeral services Wednesday will be followed by interment at a hillside site at the museum.
The Washington Post and the New York Daily News on Thursday released interviews that Ford granted on condition that they not be released until after his death. He criticized the Bush administration for citing weapons of mass destruction in Iraq as the justification for the invasion in 2003.
Contributing: The Associated Press and The Desert Sun of Palm Springs


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by alejandro matias. Date Added: Sunday 29 January, 2012
Riffworks is amazing software. The easy-to-use interface is second to none when it comes to operatio..
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text:
|Publication number
|Publication type
|Application number
|Publication date
|Jan 7, 2003
|Filing date
|Jul 31, 1997
|Priority date
|Jul 31, 1997
|Fee status
|Publication number
|Surya P. Varanasi, Tai Jing
|Original Assignee
|Lsi Logic Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (10), Non-Patent Citations (3), Referenced by (11), Classifications (17), Legal Events (10)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is related to U.S. patent applications Ser. Nos. 08/904,084, 08/904,086, 08/904,088 and 08/903,809; all of the aforementioned applications were filed on Jul. 31, 1997 and are owned by LSI Logic Corporation.
1. Field of the Invention
This invention relates generally to the field of multimedia systems, and more particularly to a video decoding device having the ability to meet particular predetermined transmission and display constraints. The video decoding device is particularly suited for Motion Picture Expert Group (MPEG) data compression and decompression standards.
2. Description of the Related Art
Multimedia software applications including motion pictures and other video modules employ MPEG standards in order to compress, transmit, receive, and decompress video data without appreciable loss. Several versions of MPEG currently exist or are being developed, with the current standard being MPEG-2. MPEG-2 video is a method for compressed representation of video sequences using a common coding syntax. MPEG-2 replaces MPEG-1 and enhances several aspects of MPEG-1. The MPEG-2 standard includes extensions to cover a wider range of applications, and includes the addition of syntax for more efficient coding of interlaced video and the occurrence of scalable extensions which permit dividing a continuous video signal into multiple coded bitstreams representing video at different resolutions, picture quality, or frame rates. The primary target application of MPEG-2 is the all-digital broadcast of TV quality video signals at coded bitrates between 4 and 9 Mbit/sec. MPEG-1 was optimized for CD-ROM or applications transmitted in the range of 1.5 Mbit/sec, and video was unitary and non-interlaced.
An encoded/compressed data stream may contain multiple encoded/compressed video and/or audio data packets or blocks. MPEG generally encodes or compresses video packets based on calculated efficient video frame or picture transmissions.
Three types of video frames are defined. An intra or I-frame is a frame of video data including information only about itself. Only one given uncompressed video frame can be encoded or compressed into a single I-frame of encoded or compressed video data.
A predictive or P-frame is a frame of video data encoded or compressed using motion compensated prediction from a past reference frame. A previous encoded or compressed frame, such as an I-frame or a P-frame, can be used when encoding or compressing an uncompressed frame of video data into a P-frame of encoded or compressed video data. A reference frame may be either an I-frame or a P-frame.
A bidirectional or B-frame is a frame of video data encoded or compressed using motion compensated prediction from a past and future reference frame. Alternately, the B-frame may use prediction from a past or a future frame of video data. B-frames are particularly useful when rapid motion occurs within an image across frames.
Motion compensation refers to the use of motion vectors from one frame to improve the efficiency for predicting pixel values of an adjacent frame or frames. Motion compensation is used for encoding/compression and decoding/decompression. The prediction method or algorithm uses motion vectors to provide offset values, error information, and other data referring to a previous or subsequent video frame.
The MPEG-2 standard requires encoded/compressed data to be encapsulated and communicated using data packets. The data stream is comprised of different layers, such as an ISO layer and a pack layer. In the ISO layer, packages are transmitted until the system achieves an ISO end code, where each package has a pack start code and pack data. For the pack layer, each package may be defined as having a pack start code, a system clock reference, a system header, and packets of data. The system clock reference represents the system reference time.
While the syntax for coding video information into a single MPEG-2 data stream are rigorously defined within the MPEG-2 specification, the mechanisms for decoding an MPEG-2 data stream are not. This decoder design is left to the designer, with the MPEG-2 spec merely providing the results which must be achieved by such decoding.
Devices employing MPEG-1 or MPEG-2 standards consist of combination transmitter/encoders or receiver/decoders, as well as individual encoders or decoders. The restrictions and inherent problems associated with decoding an encoded signal and transmitting the decoded signal to a viewing device, such as a CRT or HDTV screen indicate that design and realization of an MPEG-compliant decoding device is more complex than that of an encoding device. Generally speaking, once a decoding device is designed which operates under a particular set of constraints, a designer can prepare an encoder which encodes signals at the required constraints, said signals being compliant with the decoder. This disclosure primarily addresses the design of an MPEG compliant decoder.
Various devices employing MPEG-2 standards are available today. Particular aspects of known available decoders will be described.
Frame Storage Architecture
Previous systems used either three or two and a half frame storage for storage in memory.
Frame storage works as follows. In order to enable the decoding of B-frames, two frames worth of memory must be available to store the backward and forward anchor frames. Most systems stored either a three frame or two and a half frames to enable B-frame prediction. While the availability of multiple frames was advantageous (more information yields an enhanced prediction capability), but such a requirement tends to require a larger storage buffer and takes more time to perform prediction functions. A reduction in the size of memory chips enables additional functions to be incorporated on the board, such as basic or enhanced graphic elements, or channel decoding capability. These elements also may require memory access, so incorporating more memory on a fixed surface space is highly desirable. Similarly, incorporating functional elements requiring smaller memory space on a chip is also beneficial.
The MPEG-2 standard coincides with the traditional television screen size used today, thus requiring transmission having dimensions of 720 pixels (pels) by 480 pixels. The television displays every other line of pixels in a raster scan The typical television screen interlaces lines of pels, sequentially transmitting every other line of 720 pels (a total of 240 lines) and then sequentially transmitting the remaining 240 lines of pels. The raster scan transmits the full frame at {fraction (1/30)} second, and thus each half-frame is transmitted at {fraction (1/60)} second.
For MPEG storage method of storing two and a half frames for prediction relates to this interlacing design. The two and a half frame store architecture stores two anchor frames (either I or P) and one half of a decoded B frame. A frame picture is made up of a top and a bottom field, where each field represents interlaced rows of pixel data. For example, the top field may comprise the first, third, fifth, and so forth lines of data, while the bottom field comprises the second forth, sixth, and so on lines of data. When B frames are decoded, one half the picture (either the top field or the bottom field) is displayed. The other half picture must be stored for display at a later time. This additional data accounts for the "half frame" in the two and a half frame store architecture.
In a two frame store architecture, there is no storage for the second set of interlaced lines that has been decoded in a B-frame. Therefore, an MPEG decoder that supports a two frame architecture must support the capability to decode the same picture twice in the amount of time it takes to display one picture. As there is no place to store decoded B-frame data, the output of the MPEG decoder must be displayed in real time. Thus the MPEG decoder must have the ability to decode fast enough to display a field worth of data.
A problem arises when the picture to be displayed is in what is called the "letterbox" format. The letterbox format is longer and narrower than the traditional format, at an approximately 16:9 ratio. Other dimensions are used, but 16:9 is most common. The problem with letterboxing is that the image is decreased when displayed on screen, but picture quality must remain high. The 16:9 ratio on the 720 by 480 pel screen requires picture on only ľ of the screen, while the remaining Ľ screen is left blank. In order to support a two-frame architecture with a letterboxing display which takes ľ of the screen, a B-frame must be decoded in ľ the time taken to display a field of data.
The requirements to perform a two frame store rather than a two and a half or three frame store coupled with the desire to provide letterbox imaging are significant constraints on system speed which have not heretofore been achieved by MPEG decoders.
It is therefore an object of the current invention to provide an MPEG decoding system which operates at 54 Mhz and sufficiently decodes an MPEG data stream while maintaining sufficient picture quality.
It is a further object of the current invention to provide an MPEG decoder which supports two frame storage.
It is another object of the current invention to provide a memory storage arrangement that minimizes on-chip space requirements and permits additional memory and/or functions to be located on the chip surface. A common memory area used by multiple functional elements is a further objective of this invention.
It is yet another object of the current invention to provide an MPEG decoder which supports signals transmitted for letterbox format.
According to the current invention, there is provided a system and method for performing an inverse discrete cosine transform (IDCT) calculation based on DCT data. The system is IEEE compliant and transforms one block (8×8) of pixels in 64 cycles.
The system is a part of a larger system which comprises a macroblock core (MBCORE) and a transformation/motion compensation core (TMCCORE). The IDCT processor is a part of the TMCCORE. The TMCCORE receives the DCT input, produces the matrix (QXtQ)P, or XQP, in IDCT Stage 1 and stores the result in transpose RAM. IDCT Stage 2 performs the transpose of the result of IDCT Stage 1 and multiplies the result by P, completing the IDCT process and producing the IDCT output.
The IDCT processor receives 12 bits of DCT data input which ranges with the sign bit from −2048 to +2047. The system performs a sign change to convert to sign magnitude. If necessary, the system changes −2048 to −2047, yielding eleven bits of data and a data bit indicating sign. The system performs the matrix function QXtQ, where X represents the DCT data and Q is a predetermined diagonal matrix. The resultant value is adjusted by discarding selected bits, and the system then postmultiplies this with the elements of a predetermined P matrix, and discards selected bits.
The system converts the sign magnitude to two's complement. The system adds four blocks into each buffer, with the buffers having 22 bits each. A sign change is performed to obtain QXtQP. This completes first stage processing, which is then passed to transpose RAM.
The system then initiates IDCT stage 2, and performs a matrix transpose of QXtQP, yielding (QXtQP)t. The system then performs a twos complement to sign-magnitude, clips the least significant bit, and postmultiplies the result by the P matrix. The system then sign-magnitude converts this value back to 2's complement, and adds four products into each buffer, and performs a sign switch to obtain the elements of (QXtQP)tP. The system then right shifts the data seven bits, with roundoff, and not a clipping, and then truncates the result to between −256 and 255.
Other objects, features, and advantages of the present invention will become more apparent from a consideration of the following detailed description and from the accompanying drawings.
FIG. 1 illustrates the MPEG video decoder 100 according to the current invention;
FIG. 2 is a detailed illustration of the TMCCORE in accordance with the current invention;
FIG. 3 presents the timing diagram for the transmission of data through the TMCCORE;
FIG. 4 shows the staggered timing of data transmission through the TMCCORE;
FIG. 5A illustrates the data blocks received by the MBCORE;
FIG. 5B shows the data blocks received by the MBCORE after 16 bits of data have been transmitted to the system;
FIG. 6 shows the hardware implementation of the Data Steering Logic;
FIG. 7 is a flowchart illustrating operation of the Data Steering Logic;
FIG. 8 is a flowchart of the DCT processor multiplication logic;
FIG. 9 illustrates the implementation of IDCT Stage 1 which functionally calculates XQP;
FIG. 10 is the design for IDCT stage 2, which transposes the result from IDCT Stage 1 and multiplies the resultant matrix by P;
FIG. 11 shows the system design for performing the final functions necessary for IDCT output and storing the values in appropriate positions in IDCT OUTPUT RAM;
FIG. 12 represents the numbering of pels for use in motion compensation; and
FIG. 13 is the mechanization of the motion compensation unit used to satisfy two frame store and letterboxing requirements.
The requirements for supporting a two frame architecture as well as letterbox scaling are as follows, using NTSC. Letterbox scaling only transmits ľ of a full screen, leaving the top and bottom eighth of the screen blank at all times. For letterbox scaling, a total of 360 (or ľ*480) lines of active video must be displayed. For a two frame store system, with a 45 by 30 macroblock picture, 360 lines of active video divided by 30*525 seconds is available, or approximately 0.02286 seconds are available to decode the 45 by 30 macroblock arrangement. With 30 rows of macroblocks, the time to decode one full row of macroblocks is (360/(30*525))/30 seconds, or approximately 761.91 microseconds. The time to decode one macroblock is 761.91/45 or 16.391 microseconds. With two frame store, double decoding is necessary, and the time available to decode a macroblock is 16.391/2 microseconds, or 8.465 microseconds.
Decoder Architecture
FIG. 1 illustrates the MPEG video decoder 100 according to the current invention. The system passes the compressed bitstream 101 to MBCORE 102 (Macro Block core), which passes data to TMCCORE 103 (Transformation/Motion Compensation core) and Reference Subsystem 104. TMCCORE 103 passes information to MBCORE 102, and produces reconstructed macroblocks.
The MBCORE 102 operates as both a controller and a parser. The MBCORE 102 primary function is to parse the compressed bitstream 101 and generate DCT coefficients and motion vectors for all macroblocks. The DCT coefficients then pass to the TMCCORE 103 for further processing, and the MBCORE 102 passes the motion vectors to the Reference Subsystem 104 for further processing.
The MBCORE 102 comprises video bitstream symbol extractor 105 and state machines 106. MBCORE 102 reads the compressed bitstream 101 and if the compressed bitstream is in VLC (Variable Length Coding), the MBCORE decompresses the bitstream using the video bitstream symbol extractor 105, detailed below. The MBCORE further comprises DCT processor 107, which enables the MBCORE 102 to calculate and provide DCT coefficients to the TMCCORE 103 and motion vectors to the Reference Subsystem 104.
The TMCCORE 103 receives DCT and motion vector information for a series of macroblocks and performs the inverse discrete cosine transfer for all data received. The TMCCORE 103 receives the discrete cosine transfer data from the MBCORE 102, computes the inverse discrete cosine transform (IDCT) for each macroblock of data, computes a motion vector difference between the current frame and the reference frame by essentially "backing out" the difference between the current frame and reference frame, and combines this motion vector difference with the IDCT coefficients to produce the new frame using motion compensation. The TMCCORE 103 also executes pel compensation on reference data received from the Reference Subsystem 104, and reconstructs the new frame using information from the Reference Subsystem 104 and the MBCORE 102.
The Reference Subsystem 104 receives motion vectors from the MBCORE 102. The Reference Subsystem 104 determines the location of necessary motion related information, such as previous frame data and current frame data, to support the TMCCORE 103 in compensation and reconstruction. The Reference Subsystem 104 acquires such information and provides it to the TMCCORE 103.
As noted above, the timing for performing the necessary parsing, coefficient generation, transmission, and picture reconstruction functions is critical. Data is transmitted to the MBCORE 102 as follows: a slice header and macroblock data passes to the MBCORE 102, followed by the DCT coefficient data for a particular macroblock of data. The slice header and macroblock data take 30 cycles for transmission, and thus the MBCORE does not transmit DCT data for 30 cycles. Transmission of one macroblock of data requires the initial 30 cycle period, followed by six 64 cycle transmissions, and then the procedure repeats.
The MBCORE 102 takes 50 cycles to parse the video bitstream from the slice start code, i.e. a data block indicating the beginning of a particular bitstream arrangement, to generating the first coefficients for the IQ stage of the TMCCORE 103.
Operation of the MBCORE is as follows. The MBCORE initially accepts and parses the 50 cycles up to the block layer. The MBCORE then generates one DCT coefficient per cycle, and takes a total of (64+1)*5+64 cycles, or 389 cycles, to generate all the DCT coefficients for a given macroblock. The MBCORE passes a total of 384 DCT coefficients (64*6) to the TMCCORE 103, which accepts one block of coefficient data into IDCT Stage 1.
A detailed illustration of the TMCCORE is presented in FIG. 2. After a full block of IDCT coefficient data passes through the IDCT Stage 1 data path, which can conceptually be analogized to a pipeline, IDCT Stage 2 computation begins on the IDCT Stage 1 processed data. Hence IDCT Stage 1 data is stored by the system in RAM and the IDCT Stage 1 data is subsequently received by IDCT Stage 2 within the TMCCORE 103. IDCT Stage 1 operates as soon as it receives the data from the MBCORE 102. IDCT Stage 2, however, is one block delayed due to the processing, storage, and retrieval of the IDCT data. The arrangement of the timing of the IDCT stages and the transmission of data within the TMCCORE 103 are presented below.
Data Transmission Method
FIG. 3 presents the timing diagram for the transmission of data through the TMCCORE 103. From FIG. 3, the zero block of data, comprising 64 units of data and taking 64 cycles, is processed in the IQ/IDCT Stage 1 pipeline initially. A gap occurs between the six 64 blocks of data, taking one cycle. The one block of data is subsequently processed by the IQ/IDCT Stage 1 pipeline at the time the IDCT Stage 2 processes the zero block data. Processing continues in a staggered manner until the four block is processed in IDCT Stage 1 and the three block in IDCT Stage 2, at which time the system begins reconstruction of the picture.
With the 4:2:0 ratio, the TMCCORE 103 receives four luminance pixels and two chrominance pixels. At the end of the four luminance pixels, the TMCCORE 103 initiates reconstruction of the picture.
Total time for the process is 64 cycles multiplied by 6 blocks=384 cycles, plus five one cycle gaps, plus the 35 cycles for header processing, plus a trailing five cycles to complete reconstruction, for a total of 429 cycles. Reconstruction takes 96 cycles.
The staggered timing arrangement for processing the data permits the functions of the MBCORE 102 and TMCCORE 103 to overlap. This overlap permits the MBCORE 102 to operate on one macroblock of data while the TMCCORE 103 operates on a second macroblock. Prior systems required full loading of a single macroblock of data before processing the data, which necessarily slowed the system down and would not permit two-frame store and letterbox scaling.
FIG. 4 shows the MBCORE/TMCCORE macroblock decoding overlap scheme. Again, header data is received by the MBCORE 102, followed by zero block data, which are passed to IQ/IDCT Stage 1 processing. TMCCORE IDCT Stage 2 subsequently processes the zero block data, at the same time IQ/IDCT Stage 1 processes one block data. The staggered processing progresses into and through the reconstruction stage. During reconstruction, the five block is received and processed in IDCT Stage 2, at which time the MBCORE begins receipt of data from the subsequent macroblock. Five block and picture reconstruction completes, at which time zero block for the subsequent macroblock is commencing processing within IQ/IDCT Stage 1. This is the beneficial effect of overlapping processing.
In order to perform full merged store processing, wherein the IDCT data and the motion vector data is merged within the TMCCORE 103, both sets of data must be synchronized during reconstruction. From the drawing of FIG. 4, the motion vector data is received at the same time the IDCT Stage 2 data is received and processed. The sum of the IDCT Stage 2 data and the motion vector data establishes the picture during reconstruction, and that picture is then transmitted from the TMCCORE 103.
The total number of cycles required to decode the video bitstream from the slice header and ship out six blocks of coefficients is 429 cycles. The TMCCORE IDCT Stage 2 and Reconstruction takes fewer cycles than the MBCORE parsing and shipping of data. With the staggered processing arrangement illustrated above, the MPEG video processor illustrated here can decode the bitstream in 429 cycles (worst case).
From the requirements outlined above for the letterbox format and two frame store, the minimum frequency at which the MBCORE 102 and the TMCCORE 103 must operate at to achieve real time video bitstream decoding is 1/8.465 microseconds/429 cycles, or 50.67 Mhz. Thus by overlapping the decoding of the macroblocks using the invention disclosed herein, the MBCORE and the TMCCORE together can perform MPEG-2 MP/ML decoding with a two frame store architecture and letterbox decoding with a clock running at 54 Mhz.
Video Bitstream Symbol Extractor/Data Steering Logic
The decoder of FIG. 1 must have the ability to decode a VLD (variable length DCT) in every clock cycle. The MBCORE 102 receives one DCT coefficient per cycle, and comprises in addition to an inverse DCT function a video bitstream symbol extractor 105. Data in the bitstream is compressed, and thus the MBCORE 102 must extract the necessary symbols from the bitstream, which may vary in size. The largest symbol which must be extracted is 32 bits according to the MPEG standard. The data steering logic for the video bitstream symbol extractor permits enables the MBCORE 102 to read the symbols irrespective of symbol size.
The MBCORE 102 receives compressed video data in a linear fashion as illustrated in FIG. 5A. W0,0 represents Word 0, bit 0, while W1,31 represents Word 1, bit 31, and so forth. Time progresses from left to right, and thus the data bitstream enters the video decoder from left to right in a sequential manner as illustrated in FIG. 5A. As parsing is performed, compressed data consumed by the system is flushed out of the register and new data is shifted into the register. This flushing of consumed data and maintenance of unconsumed data is performed by the data steering logic.
FIG. 5B illustrates the appearance of the data after a 16 bit symbol is consumed . The data comprising W0,0 . . . 15 is consumed by the system, leaving all other data behind. The problem which arises is that upon consuming a 16 bit symbol, the next symbol may be 30 bits in length, thereby requiring excess storage beyond the 32 bit single word length. The tradeoff between timing and space taken by performing this shifting function is addressed by the data steering logic.
Data steering logic is presented in FIG. 6. According to the data steering logic, the CPU first instructs the data steering logic to initiate data steering. Upon receiving this initiation signal, the data steering logic loads 32 bit first flop 601 and 32 bit second flop 602 with 64 bits of data. The data steering logic then resets the total_used_bits counter 603 to zero and indicates that initialization is complete by issuing an initialization ready signal to the CPU.
Once the MBCORE 102 begins receiving video data, state machines 106 within the MBCORE 102 examine the value coming across the data bus and consume some of the bits. This value is called "usedbits" and is a six bit ([5:0]) bus. The total number of used bits, total_used[5:0], is the sum of total_used_bits[5:0] and usedbits[5:0]. total_used_bits are illustrated in FIG. 6 as flop 604. Bit usage via flop 604 and total_used_bits counter 603 is a side loop used to track the status of the other flops and barrel shifter 605.
Data is sequentially read by the system and passed to the barrel shifter, and subsequently passed to resultant data flop 608.
For example, the initial value of usedbits is 0. A consumption of 10 bits, representing a 10 bit symbol, by the state machines 106 yields a total_used_bits of 10. Hence the total_used is 10. These 10 bits are processed using first flop bank MUX 606 and loaded into barrel shifter 605.
total_used is a six bit wide bus. The range of values that may be stored using total_used is from 0 to 63. When the value of total_used_bits is greater than 63, the value of total_used_bits wraps back around to zero.
When total_used is greater than 32 and less than or equal to 63, first flop bank 601 is loaded with new data. When total_used is greater than or equal to zero and less than 32, the data steering logic loads second flop bank 602 with data.
Continuing with the previous example, the first 10 bit symbol is processed by first flop bank MUX 606 and loaded into barrel shifter 605, usedbits set to 10, total_used set to 10, and total_bits_used set to 10. The next symbol may take 12 bits, in which case the system processes the 12 bit symbol using first flop bank MUX 606 and passes the data to barrel shifter 605. usedbits is set to 12, which is added to total_used_bits (10) in total_used_bits counter 603, yielding a total_used of 22.
The next data acquired from RAM may be a large symbol, having 32 bits of length. Such a symbol spans both first flop 601 and second flop 602, from location 23 in first flop 601 through second flop 602 location 13. In such a situation, usedbits is 32, and the data is processed by first flop bank MUX 606 and second flop bank MUX 607. usedbits is set to 32, which is added to total_used bits (22) in total_used_bits counter 603, yielding a total_used of 54.
With a total_used of 54, the system loads new data into first flop 601 and continues with second flop 602.
Barrel shifter 605 is a 32 bit register, and thus the addition of the last 32 bit segment of processed data would fill the barrel shifter 605. Hence the data from barrel shifter 605 is transferred out of barrel shifter 605 and into resultant data flop 608. The 32 bits from first flop bank MUX 606 and second flop bank MUX 607 pass to barrel shifter 605.
Continuing with the example, the next symbol may only take up one bit. In such a situation, used bits is one, which is added to total_used_bits (54) yielding a total_used of 55. The system processes the bit in second flop bank MUX 607 and the processed bit passes to barrel shifter 605.
The next symbol may again be 32 in length, in which case data from the end of second flop 602 and the beginning of first flop 601 is processed and passed into the barrel shifter 605. usedbits is 32, which is added to total_used_bits (54), which sums to 87. However, the six bit size of the total_used indicates a total of 23, i.e. the pointer in the barrel register 605 is beyond the current 64 bits of data and is 23 bits into the next 64 bits of data.
With a value in excess of 32 bits, the single bit residing in barrel shifter 605 passes to resultant data flop 608, and the 32 bits pass to barrel shifter 605. The system then sequentially steps through all remaining data to process and pass data in an efficient manner.
The operation of the process is illustrated graphically in FIG. 7. The first and second flop banks are loaded in step 701 and the system initialized in step 702. The system reads data in step 703 and determines total_used in step 704. The system then determines whether total_used_bits is greater than 32 in step 705, and, if so, first flop bank is loaded with new data in step 706. Step 707 determines whether total_used is greater than or equal to 0 and less than 32. If so, step 708 loads the second flop bank with data.
As long as usedbits is not equal to zero, steps 704 through 708 are repeated. If the CPU initializes the data steering logic in the middle of the operation, the process begins at step 701.
The advantage of this implementation is that it is hardware oriented and requires no interaction from a CPU or microcontroller. Only a single shift register is used, which provides significant area savings. The system obtains the benefits of using the shift register as a circular buffer in that the system uses total bits as a pointer into the shift register and loads shifted data into the resultant data register 608.
IDCT Processor/Algorithm
The TMCCORE 103 performs the IDCT transform using IDCT processor 107. The Inverse Discrete Cosine Transform is a basic tool used in signal processing. The IDCT processor 107 used in MBCORE 102 may be any form of general purpose tool which performs the IDCT function, but the preferred embodiment of such a design is presented in this section.
The application of the IDCT function described in this section is within a real time, high throughput multimedia digital signal processing chip, but alternate implementations can employ the features and functions presented herein to perform the inverse DCT function.
The implementation disclosed herein is IEEE compliant, and conforms with IEEE Draft Standard Specification for the Implementations of 8×8 Inverse Discrete Cosine Transform, P1180/D1, the entirety of which is incorporated herein by reference.
Generally, as illustrated in FIG. 1, the MBCORE 102 receives DCT data and initially processes symbols using the video bitstream symbol extractor 105 and subsequently performs the IDCT function using IDCT processor 107.
The system feeds DCT coefficients into IDCT processor 106 in a group of eight rows of eight columns. Each DCT coefficient is a 12 bit sign magnitude number with the most significant bit (MSB) being the sign bit. The IDCT processor 106 processes a macroblock comprising an 8×8 block of pixels in 64 cycles. After processing, the IDCT processor transmits a data stream of eight by eight blocks. Each output IDCT coefficient is a nine bit sign magnitude number also having the MSB as a sign bit.
The Inverse Discrete Cosine Transform is defined as:
where i,j=0 . . . 7 is the pixel value, X(k,l), k,l=0 . . . 7 is the transformed DCT coefficient, x(i,j) is the final result, and
Equation 1 is mathematically equivalent to the following matrix form:
where XQ(i,j)=QQ(i,j)×(j,i), QQ=Q*Q, where Q is a matrix and QQ is the product of matrix Q with itself. P from Equation 3 is as follows:
where Q is:
and I is a unitary diagonal identity matrix, a is 5.0273, b is 2.4142, c is 1.4966, and r is 0.7071.
The matrix representation of the IDCT greatly simplifies the operation of the IDCT processor 106, since each row of the P matrix has only four distinct entries, with one entry being 1. This simplification of the number of elements in the IDCT matrix means that in performing a matrix multiplication, the system only needs three multipliers instead of eight, the total number of elements in each row.
The system performs IDCT processing by performing multiplications as illustrated in FIG. 8. The IDCT processor 107 receives 12 bits of DCT data input in 2's complement format, and thus can range (with the sign bit) from −2048 to +2047. The first block 801 performs a sign change to convert to sign magnitude. If necessary, block 801 changes −2048 to −2047. This yields eleven bits of data and a data bit indicating sign. Second block 802 performs the function QXtQ, which uses 0+16 bits for QQ, yielding one sign bit and 20 additional bits. Block 802 produces a 27 bit word after the multiplication (11 bits multiplied by 16 bits), and only the 20 most significant bits are retained. Block 803 multiplies the results of block 802 with the elements of the P matrix, above. The P matrix is one sign bit per element and 15 bits per element, producing a 35 bit word. The system discards the most significant bit and the 14 least significant bits, leaving a total of 20 bits. The result of block 804 is therefore again a one bit sign and a 20 data bits.
Block 805 converts the sign magnitude to two's complement, yielding a 21 bit output. The system adds four blocks into each buffer, with the buffers having 22 bits each. Block 805 transmits all 22 bits. Block 806 performs a sign change to obtain QXtQP, and passes 22 bits with no carry to block 807.
Block 807 performs a matrix transpose of QXtQP, yielding (QXtQP)t. Block 807 passes this transpose data to block 808 which performs a twos complement to sign-magnitude, yielding a one bit sign and a 21 bit word. Block 809 clips the least significant bit, producing a one bit sign and a 20 bit word. This result passes to block 810, which multiplies the result by the P matrix, having a one bit sign and a 15 bit word. The multiplication of a 20 bit word with 1 bit sign by a 15 bit word with 1 bit sign yields a 35 bit word, and the system discards the two most significant bits and the 13 least significant bits, producing a 20 bit word with a 1 bit sign out of block 810. The result of block 810 is sign-magnitude converted back to 2's complement, producing a 21 bit result in block 811. Block 812 performs a similar function to block 805, and adds the four products into each buffer. The buffers have 22 bits each, and the output from block 812 is 22 bits. This data is passed to block 813, which performs a sign switch to obtain the elements of (QXtQP)tP. Output from block 813 is a 22 bit word, with no carry. Block 814 right shifts the data seven bits, with roundoff, and not a clipping. In other words, the data appears as follows:
SIGNxxxxxxxxxxxxxXYxxxxxx (22 bit word)
and is transformed by a seven bit shift in block 813 to:
Depending on the value of Y, block 814 rounds off the value to keep 15 bits. If Y is 1, block 814 increments the integer portion of the word by 1; if Y is 0, block 814 does not change the integer part of the word.
The result is a 15 bit word, which is passed to block 815. In block 815, if the 15 bit value is greater than 255, the block sets the value to 255. If the value is less than −256, it sets the value to −256. The resultant output from block 815 is the IDCT output, which is a 9 bit word from −256 to 255. This completes the transformation from a 12 bit DCT input having a value between −2048 and 2047, and a 9 bit inverse DCT output, having a value between −256 and 255.
The coefficiencies for matrix multiplication are as follows. The four factors used which can fully define all elements of the QQ and P matrices are as follows:
The parameters for all elements of the QQ and PP matrix are:
For the P matrix,
The entire IDCT is implemented in two stages. IDCT Stage 1, illustrated in FIG. 9, implements XQP. The second stage, illustrated in FIG. 10, transposes the result and multiplies it by P again.
From FIG. 2, and as may be more fully appreciated from the illustrations of FIGS. 8 through 11, the TMCCORE 103 receives the DCT input, produces the matrix (QXtQ)P, or XQP, in IDCT Stage 1 (i.e., from FIG. 8, completes through block 806) and stores the result in transpose RAM 923. IDCT Stage 2 performs the transpose of the result of IDCT Stage 1 and multiplies the result by P, completing the IDCT process and producing the IDCT output.
As may be appreciated from FIG. 9, the representation disclosed is highly similar to the flowchart of FIG. 8. From FIG. 9, IDCT Stage 1 pipeline 900 receives data from the IQ block in the form of the matrix X. The Q matrix is available from a row/column state machine in the IQ pipeline, depicted by state machine registers 902. The state machine registers 902 pass data from register 902 c to QQ matrix block 903 which contains QQ matrix generator 904 and QQ matrix register 905. QQ data is passed to QXtQ block 901 which multiplies the 16 bit QQ matrix by the X block having one sign bit and 11 data bits in QXtQ multiplier 906. This multiplication is passed to QXtQ register 907, which transmits a one bit sign and a 20 bit word. QXtQ block 901 thereby performs the function of block 802. Output from register 902 d is a column [2:0] which passes to P matrix block 908. P matrix block 908 comprises P matrix generator 909 which produces a sign bit and three fifteen bit words to P matrix register 910.
QXtQ block 901 passes the one bit sign and 20 bit word to (QXtQ)P block 911, which also receives the three fifteen bit words and one sign bit from P matrix block 908. (QXtQ)P block 911 performs the function illustrated in block 803 in three multiplier blocks 912 a, 912 b, and 912 c. The results of these multiplications is passed to (QXtQ)P MUX 913, which also receives data from register 902 e in the form row[2:0]. Data from register 902 e also passes to read address generator 914, which produces a transpose RAM read address. The transpose RAM read address passes to transpose RAM 923 and to first write address register 915, which passes data to write address register 916. The write address from write address register 916 and the read address from read address generator 914 pass to transpose RAM 923, along with the P matrix read row/column generator state machine 1001, illustrated below. (QXtQ)P MUX 913 thus receives the output from the three multiplier blocks 912 a, 912 b, and 912 c as well as the output from register 902 e, and passes data to (QXtQ)P register 917, which passes the (QXtQ)P matrix in a one bit sign and 20 bit word therefrom. As in block 804, these four data transmissions from (QXTQ)P block 911 pass to matrix formatting block 918. Matrix formatting block 918 performs first the function illustrated in block 802 by converting sign-magnitude to two's complement in two's complement blocks 919 a, 919 b, 919 c, and 919 d. The values of these four blocks 919 a-d are added to the current values held in transpose RAM 923 in summation blocks 920 a, 920 b, 920 c, and 920 d. The transpose RAM 923 value is provided via register 921. Transpose RAM 923 is made up of 4 eight bit by 88 bit values, and each 22 bit result from the four summation blocks 920 a, 920 b, 920 c, and 920 d pass to register 922 and subsequently to transpose RAM 923. This completes processing for IDCT Stage 1.
Processing for IDCT Stage 2 1000 is illustrated in FIG. 10. P matrix read row/column generator state machine 1001 receives a transpose RAM ready indication and provides row/column information for the current state to transpose RAM 923 and to a sequence of registers 1002 a, 1002 b, 1002 c, 1002 d, and 1002 e. The information from 1002 b passes to Stage 2 P matrix block 1003, comprising Stage 2 P matrix generator 1004 and P matrix register 1005, which yields the one bit sign and 15 bit word for the P matrix.
From transpose RAM 923, two of the 22 bit transpose RAM elements pass to transpose block 1006, wherein transpose MUX 1007 passes data to registers 1008 a and 1008 b, changes the sign from one register using sign change element 1009 and passes this changed sign with the original value from register 1008 b through MUX 1010. The value from MUX 1010 is summed with the value held in register 1008 a in summer 1011, which yields the transpose of QXtQP, a 22 bit word. Thus the value of the data passing from the output of summer 1011 is functionally equal to the value from block 807, i.e. (QXtQP)t. Two's complement/sign block 1012 performs the function of block 808, forming the two's complement to sign-magnitude. The LSB is clipped from the value in LSB clipping block 1013, and this clipped value is passed to register 1014, having a one bit sign and a 20 bit word.
The output from transpose block 1006 is multiplied by the P matrix as functionally illustrated in block 810. This multiplication occurs in Stage 2 P multiplication block 1015, specifically in multipliers 1016 a, 1016 b, and 1016 c. This is summed with the output of register 1002 c in MUX 1017 and passed to register 1018. This is a matrix multiplication which yields (QXtQP)tP. Conversion block 1019 converts this information, combines it with specific logic and stores the IDCT values. First two's blocks 1020 a, 1020 b, 1020 c, and 1020 d convert sign-magnitude to two's complement, as in block 811, and sum this in adders 1021 a, 1021 b, 1021 c, and 1021 d with current IDCT RAM 1024 values, which comprise four 22 bit words. The sum of the current IDCT RAM values and the corrected (QXtQP)tP values summed in adders 1021 a-d pass to IDCT RAM 1024.
IDCT RAM 1024 differs from transpose RAM 923. IDCT RAM 1024 provides a hold and store place for the output of IDCT Stage 2 values, and comprises two 88 by 1 registers. Note that IDCT RAM 1024 feeds four 22 bit words back to adders 1021 a-d, one word to each adder, and passes eight 22 bit words from IDCT Stage 2 1000.
RAM 1024 also utilizes values passed from register 1002 d, i.e. the position of read/write elements or the state of the multiplication. Register 1002 d passes data to read additional combined logic element 1022, which calculates and passes a read add indication and a write add indication to RAM 1024 to properly read and write data from adders 1021 a-d.
Data also passes from register 1002 d to register 1002 e, which provides information to output trigger generator 1023, the result of which is passed to RAM 1024 as well as out of IDCT Stage 2 1000. The output from RAM 1024 is eight 22 bit words and the output from output trigger generator 1023. The result functionally corresponds to the output from block 812.
FIG. 11 illustrates the implementation which performs the final functions necessary for IDCT output and stores the values in appropriate positions in IDCT OUTPUT RAM 1115. Sign corrector 1101 receives the eight 22 bit words from IDCT Stage 2 1000 and multiplexes them using MUX 1102 to four 22 bit words passing across two lines. These values are summed in summer 1103, and subtracted in subtractor 1104 as illustrated in FIG. 11. The output from subtractor 1104 passes through register 1105 and reverse byte orderer 1107, and this set of 4 22 bit words passes along with the value from summer 1103 to MUX 1107, which passes data to register 1108. This sign corrector block produces an output functionally comparable to the output of block 813, essentially providing the elements of (QXtQP)tP. Shift/roundoff block 1109 takes the results from sign corrector 1101, converts two's complement to sign/magnitude in element 1110, shifts the value right seven places using shifters 1111 a, 1111 b, 1111 c, and 1111 d, rounds these values off using round off elements 1112 a, 1112 b, 1112 c, and 1112 d, and passes these to element 1113. The rounded off values from round off elements 1112 a-d functionally correspond to the output from block 814. The value is limited between −256 and +255 in element 1113, the output of which is a 15 bit word passed to sign block 1114, which performs a conversion to two's complement and passes four nine bit words to IDCT OUTPUT RAM 1115.
Output from the Output Trigger Generator and the chroma/luma values from CBP Luma/Chroma determine the stage of completeness of the IDCT RAM OUTPUT. IDCT RAM address/IDCT Done indication generator 1116, as with elements 914, 915, and 916, as well as elements 1022 and 1023, are placekeepers or pointers used to keep track of the position of the various levels of RAM, including the current position and the completion of the individual tasks for various levels of processing, i.e. IDCT Stage 1 progress, IDCT Stage 2 progress, and completion of the Stages. It is recognized that any type of bookkeeping, maintenance, or pointing processing can generally maintain values and placement information for reading, writing, and providing current location and completion of task indications to blocks or elements within the system while still within the scope of the current invention. The purpose of these elements is to provide such a bookkeeping function.
IDCT RAM address/IDCT Done indication generator 1116 receives output trigger generator 1023 output trigger information and CBP Luma/Chroma indications and provides a write address and a Luma Done/Chroma Done IDCT indication, signifying, when appropriate, the receipt of all necessary luma/chroma values for the current macroblock.
The system writes IDCT information to IDCT OUTPUT RAM 1115, specifically the information passing from sign block 1114 to the appropriate location based on the write address received from IDCT RAM address/IDCT Done indication generator 1116. IDCT OUTPUT RAM 1115 is broken into Luma (Y0, Y1, Y2, and Y3) locations, and Chroma (Cb and Cr) locations. The values of IDCT OUTPUT RAM 1115 represent the complete and final IDCT outputs.
The design disclosed herein provides IDCT values at the rate of 64 cycles per second. The design stores two blocks worth of data in transpose RAM 923 between IDCT Stage 1 and IDCT Stage 2.
Motion Compensation
Motion compensation for the two frame store and letterbox scaling for MPEG decoding operates as follows.
For a 2×7 array of pixels, i.e. 14 pels, the numbering of pels is illustrated in FIG. 12.
The system performs a half-pel compensation. Half-pel compensation is compensating for a location between pixels, i.e. the motion is between pixel x and pixel y. When the system determines the data in FIG. 12 must be right half pel compensated, or shifted right one half pel, the system performs the operation(s) outlined below.
When the system determines the data in FIG. 12 must be down half pel compensated, or shifted downward one half pel, the system performs the operation(s) outlined below.
0′=(0+7)/2; if (0+7)mod 2==1, 0′=0′+1;
Alternately, the system may indicate the desired position is between four pels, or shifted horizontally one half pel and down one half pel. When the system determines the data in FIG. 12 must be right and down half pel compensated, or shifted right one half pel and down one half pel, the system performs the operation(s) outlined below.
The aforementioned logic is implemented as illustrated in FIG. 13. As may be appreciated, a right half pel shift may require the system to point to a position one half-pel outside the block. Thus the system must compensate for odd-pel shifting.
From FIG. 13, the motion compensation unit 1300 comprises horizontal half pel compensatory 1301 and vertical half pel compensator 1302, as well as four banks of 36 flops 1303 a, 1303 b, 1303 c, and 1303 d. Registers 1304 a, 1304 b, 1304 c, 1304 d, and 1304 e contain motion compensation data having 32 bits of information. These registers pass the motion compensation data to horizontal compensation MUXes 1305 a, 1305 b, 1305 c, and 1305 d, as well as horizontal adders 1306 a, 1306 b, 1306 c, and 1306 d as illustrated in FIG. 13. For example, register 1304 e passes motion compensation data to horizontal compensation MUX 1305 d, which subsequently passes the information to horizontal adder 1306 d and adds this value to the value received from register 1304 d. Register 1304 a passes data to adder 1306 a but does not pass data to any of the horizontal compensation MUXes 1305 a-d. This summation/MUX arrangement provides a means for carrying out the right half-pel compensation operations outlined above. The result of the horizontal half pel compensator 1301 is four summed values corresponding to the shift of data one half pel to the right for a row of data.
As a luma macroblock has dimensions of 16×16, movement of one half pel to the right produces, for the 16th element of a row, a shift outside the bounds of the 16×16 macroblock. Hence a right shift produces a 16×17 pixel macroblock, a vertical shift a 17×16 pixel macroblock, and a horizontal and vertical shift a 17 by 17 pixel macroblock. The additional space is called an odd pel.
The compensation scheme illustrated in FIG. 13 determines the necessity of compensation and thereby instructs the MUXes disclosed therein to compensate by adding one half pel to each pel position in the case of horizontal pixel compensation. Thus out of the 32 bits from reference logic, data for each pel may be shifted right one pel using the MUX/adder arrangement of the horizontal half pel compensator 1301.
Vertical pel compensation operates in the same manner. For each of the pels in a macroblock, the data is shifted downward one half pel according to the vertical compensation scheme outlined above. Vertical half pel compensator 1302 takes and sums results from the horizontal half pel compensator 1301 and receives data from the four banks of 36 flops 1303 a, 1303 b, 1303 c, and 1303 d. Data from horizontal half pel compensator 1301 passes to vertical adders 1308 a, 1308 b, 1308 c, and 1308 d along with MUXed data from the four banks of 36 flops 1303 a, 1303 b, 1303 c, and 1303 d.
In cases where vertical and horizontal half pel compensation are required, the four banks of 36 flops 1303 a, 1303 b, 1303 c, and 1303 d are used by the system to store the extra row of reference data expected for down half-pel compensation. This data storage in the four banks of 36 flops 1303 a-d provides the capability to perform the computations illustrated above to vertically and horizontally shift the data one half pel. The result is transmitted to register 1309, which may then be B-picture compensated and transmitted to motion compensation output RAM 1311.
Reference data averaging may be necessary for B-pictures having backward and forward motion vectors, or with P pictures having a dual-prime prediction. Either function is accomplished within the B-picture compensator 1310.
Prediction may generally be either frame prediction, field prediction, or dual-prime. Frame pictures for half pel compensation appear as follows.
In frame prediction, the luma reference data pointed to by a motion vector contains either 16×16 (unshifted), 16×17 (right half-pel shifted), 17×16 (down half-pel shifted), or 17×17 (right and down half-pel shifted) data. The chroma component, either Cr or Cb, contains either 8×8 (unshifted), 8×9 (right half-pel shifted), 9×8 (down half-pel shifted) or 9×9 (right and down half-pel shifted) data.
In field prediction as well as dual-prime predictions, the luma reference data pointed to by a motion vector contains either 8×16 (unshifted), 8×17 (right half-pel shifted), 9×16 (down half-pel shifted) or 9×17 (down and right half pel shifted) data. The chroma reference data, either Cr or Cb, contains either 4×8 (unshifted), 4×9 (right half-pel shifted), 5×8 (down half-pel shifted) or 5×9 (right and down half-pel shifted) data.
Field pictures for half-pel compensation may utilize field prediction, 16×8 prediction, or dual-prime. Field prediction and dual-prime prediction are identical to frame prediction in frame pictures, i.e. the luma and chroma references are as outlined above with respect to frame prediction (16×16, 16×17, 17×16, or 17×17 luma, 8×8, 8×9, 9×8, or 9×9 chroma). 16×8 prediction is identical to field prediction in frame pictures, i.e., luma and chroma are identical as outlined above with respect to field prediction (8×16, 8×17, 9×16, or 9×17 luma, 4×8, 4×9, 5×8, or 5×9 chroma).
The motion compensation unit 1300 accepts reference data 32 bits (4 pels) at a time while accepting odd pel data one pel at a time on the odd pel interface, The system ships luma reference data in units of 8×16 and chroma reference data in units of 4×8. Luma reference data is transferred before chroma reference data, and Cb chroma is shipped before Cr chroma.
In accordance with the motion compensation unit 1300 of FIG. 13, transfer of luma and chroma data occurs as follows.
For luma data, assuming that luma reference data is represented by luma [8:0] [16:0], or that data requires both right and down half-pel compensation. On a cycle by cycle basis, luma data is transferred as follows using motion compensation unit 1300:
Reference Data
Odd-Pel Data
Luma[0] [12:15]
Luma[0] [17]
Luma[0] [8:11]
Luma[0] [4:7]
Luma[0] [0:3]
Luma[1] [12:15]
Luma[1] [16]
Luma[1] [8:11]
Luma[1] [4:7]
Luma[1] [0:3]
. . .
. . .
. . .
Luma[8] [12:15]
Luma[8] [16]
Luma[8] [8:11]
Luma[8] [4:7]
Luma[8] [0:3]
For chroma reference data represented by Chroma [4:0][8:0]. The motion compensation unit 1300 transfers data on a cycle by cycle basis as follows:
Reference Data
Odd-Pel Data
Chroma[0] [4:7]
Chroma[0] [8]
Chroma[0] [0:3]
Chroma[1] [4:7]
Chroma [1] [8]
Chroma[1] [0:3]
. . .
. . .
. . .
Chroma[4] [4:7]
Chroma[4] [8]
Chroma[4] [0:3]
Data expected by motion compensation units for the combinations of picture type, prediction type, and pel compensation are as follows:
Data fetched by vector
(in pels)
16 × 16/8 × 8
16 × 17/8 × 9
17 × 16/9 × 8
17 × 17/9 × 9
8 × 16/4 × 8
8 × 17/4 × 9
9 × 16/5 × 8
9 × 17/5 × 9
8 × 16/4 × 8
8 × 17/4 × 9
9 × 16/5 × 8
9 × 17/5 × 9
16 × 16/8 × 8
16 × 17/8 × 9
17 × 16/9 × 8
17 × 17/9 × 9
16 × 8
8 × 16/4 × 8
8 × 17/4 × 9
9 × 16/5 × 8
9 × 17/5 × 9
16 × 16/8 × 8
16 × 17/8 × 9
17 × 16/9 × 8
17 × 17/9 × 9
Reference data transfer to the TMCCORE 103 occurs as follows.
Luma Data
Reference Motion
Transfer Order to
Vector Data
Motion Compensation Unit 1300
17 × 17
9 × 17
8 × 17
16 × 16
8 × 16
8 × 16
17 × 16
9 × 16
8 × 16
16 × 17
8 × 17
8 × 17
8 × 16
8 × 16
9 × 16
9 × 16
8 × 17
8 × 17
9 × 17
9 × 17
Chroma Data
Reference Motion
Transfer Order to
Vector Data
Motion Compensation Unit 1300
9 × 9
5 × 9
4 × 9
8 × 9
4 × 9
4 × 9
9 × 8
5 × 9
4 × 9
8 × 8
4 × 8
4 × 8
4 × 8
4 × 8
4 × 9
4 × 9
5 × 8
5 × 8
5 × 9
5 × 9
The maximum amount of reference data (in bytes) that the system must fetch for any macroblock conforming to the 4:2:0 format occurs in a frame picture/field prediction/B-picture, a field picture/16×8 prediction/B-picture, or a frame picture/dual prime. The amount of luma reference data expected, excluding odd pel data, is 4*9*16 or 576 bytes of data. The amount of luma reference data (for both Chroma blue and Chroma red, excluding half-pel data, is 2*4*5*8 or 320 bytes.
Data may be processed by the motion compensation unit 1300 at a rate of 4 pels per cycle. The total number of cycles required to process the data is 576+320/4, or 224 cycles. This does not include odd pel data which is transferred on a separate bus not shared with the main data bus.
While the invention has been described in connection with specific embodiments thereof, it will be understood that the invention is capable of further modifications. This application is intended to cover any variations, uses or adaptations of the invention following, in general, the principles of the invention, and including such departures from the present disclosure as come within known and customary practice within the art to which the invention pertains.
|Cited Patent
|Filing date
|Publication date
|Feb 19, 1992
|Jan 3, 1995
|Integrated Information Technology, Inc.
|Video compression/decompression processing and processors
|May 9, 1994
|Jun 27, 1995
|International Business Machines Corporation
|Memory structure to minimize rounding/trunction errors for n-dimensional image transformation
|Jun 24, 1993
|Dec 26, 1995
|Discovision Associates
|Method and arrangement for transformation of signals from a frequency to a time domain
|Sep 22, 1994
|Dec 31, 1996
|Sony Corporation
|Two-dimensional discrete cosine transformation system, two-dimensional inverse discrete cosine transformation system, and digital signal processing apparatus using same
|Dec 6, 1995
|Mar 3, 1998
|Matsushita Electric Industrial Co., Ltd.
|Apparatus for inverse discrete cosine transform
|Jun 20, 1996
|Jul 14, 1998
|Lsi Logic Corporation
|System and method for performing an optimized inverse discrete cosine transform with improved efficiency
|May 3, 1996
|Oct 6, 1998
|Lsi Logic Corporation
|Micro architecture of video core for MPEG-2 decoder
|Oct 20, 1995
|Feb 2, 1999
|Matsushita Electric Corporation Of America
|Inverse discrete cosine transform processor using parallel processing
|May 19, 1997
|Apr 13, 1999
|Matsushita Electric Industrial Co., Ltd.
|Orthogonal transform processor
|Aug 1, 1997
|May 11, 1999
|Lsi Logic Corporation
|Micro-architecture of video core for MPEG-2 decoder
|MacInnis, Alexander G. (Sandy); MPEG Systems Committee Draft ISO/IEC JTCI/SC2/WG11; IEEE; 1991; pp. 338-341.
|Maturi, Gregg; Single Chip MPEG Audio Decoder; IEEE; Aug. 1992; pp. 348-356.
|Systems Committee; International Organization for Standardization; Coding of Moving Pictures and Associated Audio; Sep. 1993; pp. 1-66.
|Citing Patent
|Filing date
|Publication date
|Feb 26, 2001
|May 29, 2007
|Screenpeaks Ltd.
|Digital video broadcasting
|Jul 2, 2003
|Sep 9, 2008
|Kabushiki Kaisha Toshiba
|Picture data recording method, picture data storage medium, picture data playback apparatus, and picture data playback method
|Apr 18, 2007
|Jun 16, 2009
|Screenpeaks Ltd.
|Digital video broadcasting
|May 26, 2006
|Jul 7, 2009
|Seiko Epson Corporation
|Method and apparatus for overlaying reduced color resolution images
|Feb 26, 2001
|Apr 25, 2002
|Telem-Atik Communication Systems (1999) Ltd.
|Digital video broadcasting
|Jul 2, 2003
|Feb 5, 2004
|Kabushiki Kaisha Toshiba
|Picture data recording method, picture data storage medium, picture data playback apparatus, and picture data playback method
|Dec 15, 2003
|Feb 17, 2005
|Pai Ramadas Lakshmikanth
|DMA engine for fetching words in reverse bit order
|May 26, 2006
|Mar 1, 2007
|Atousa Soroushi
|Method and Apparatus for Overlaying Reduced Color Resolution Images
|Apr 18, 2007
|Dec 13, 2007
|Screenpeaks Ltd.
|Digital video broadcasting
|Jun 4, 2010
|Nov 24, 2010
|Method for simulating attention mobility by using neural network
|Jun 4, 2010
|Jul 23, 2014
|Method for simulating attention mobility by using neural network
|U.S. Classification
|International Classification
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UPDATE: Take a listen. I join in at the 23:23 mark.I will be occupying the microphone today at 5:00 p.m. eastern/ 2:00 p.m. pacific.I will be discussing my recent switch to the Green Party on the South Carolina based radio show Occupy the Microphone.You can listen from anywhere by going to this link. Tune in!The show airs from 5:03 p.m. to 6:00 p.m. I expect to one shortly after 5:20 Eastern. … [Read more...]
I will be Occupying the Microphone! (Updated with Audio)
15 years!
15 year ago today, Lyndee Marie Curtis and I were married in the Salt Lake Temple of the Church of Jesus Christ of Latter-day Saints.She has been my rock. Thanks, babe.Help us celebrate by subscribing or donating to Approaching Justice! … [Read more...]
If Nibley Was The Mormon Aquinas, Taylor Petrey is Our Foucault
Taylor Petrey is the most important voice in Mormon theology and Mormon thought today. He is the Lucinda Hinsdale Stone Assistant Professor of Religion at Kalamazoo College specializing in Early Christianity and Biblical Studies, and is director of the Women, Gender, and Sexuality program.His article "Toward a Post-Heterosexual Mormon Theology" in the December 2011 Dialogue: A Journal of Mormon Thought is a masterpiece. In that article, Petrey offers a deep theoretical analysis of gender … [Read more...]
I Am No Longer a Democrat.
Last week, as I obtained my Nevada driver's license, I registered to vote in Nevada. As I went to check the box for political party affiliation...I decided to switch parties.Being an unaffiliated voter is not how I roll. While political parties and partisanship can be among the most frustrating and annoying aspects of politics, parties are an essential element of a healthy democracy. While our parties might have major problems, not having political parties is not the answer.Before anyone … [Read more...]
Being Passive Aggressive Does Not Mean You are Not a Bully
Just Saying.Source: Online Interactive Communication Training. … [Read more...]
Does the U.S. Pay Families When Drones Kill Innocent Yemenis?
by Cora Currier ProPublica, Aug. 12, 2013, 1:48 p.m.There have been nine drone strikes reported in Yemen in the past two weeks – an uptick apparently connected to the Al Qaeda threat that shut down U.S. embassies across the Middle East and Africa. As many as six civilian deaths have also been reported.President Obama has promised increased transparency around drones, but when asked about the strikes on Friday, Obama wouldn't even confirm U.S. involvement."I will not have a discussion about o … [Read more...]


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Lisa Gastoni
Three Men in a Boat
Jimmy Edwards, Laurence Harvey and David Tomlinson play the three somewhat clueless gentlemen who take a pleasure excursion down the Thames in a small boat. The trio expect to do some male bonding and get some rest, but the trip is soon complicated by various adventures and mishaps. However, the complications turn to the more romantic kind when their trip seems fated to cross the path of fetching young ladies.


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The central bank is constantly redesigning and rethinking the design of every bank note—except the lowly $1 bill.
Only in the mid-1990s did the central bank begin to publicly announce changes in interest-rate policy.
No central bank will admit it is keeping rates low to help governments out of their debt crises.
The rump euro zone would be stronger, and currencies can do pretty well during a crisis, depending on how the central bank reacts.
And its central bank and private investors always had a huge portfolio of U.S. government bonds.
Allowances were deposited in a central bank, with elected officers.
Mr. Wilton's case was rendered far worse by the loss of a large private income derived from shares in the central bank.
Japan first copied the national banking system of the United States and after trial abandoned the same for a central bank.
With these funds the central bank was to purchase state bonds, devoting the interest to redeeming the notes of the national banks.
Each Federal Reserve Bank will be a central bank for the section of the country which it is to serve.


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USDA advances on bond mechanism: new $$ source for biofuels expansion?
In Washington, the USDA adopted a bond mechanism into its Business & Industry Loan Guarantee Program to mirror what the DOE already had done in each of its Section 1703 and Section 1705 Loan Guarantee Programs.
The mechanism had been proposed in public comments submitted by Mintz Levin, Stern Brothers and Kreig DeVault. According to Mintz Levin's Mark Riedy, "We expect that USDA shortly will issue final rules for its 9003 and 9007 loan guarantee programs adopting our bond finance mechanism and removing the US ownership restriction. Thus, foreign investors will be able to fully use the USDA programs, and all will be able to use our bond finance model using credit enhanced corporate debt from project companies in lieu of using any commercial debt whatsoever.
"Our bond model has up to a 2% lower interest rate than commercial debt," added Riedy, "and provides a tenor of 15-25 years for our bond mechanism versus 1-7 years for commercial debt, and offers bond terms which are unavailable to those project developers relying exclusively on commercial debt. Plus, this bond mechanism is highly flexible versus the lack of flexibility inherent in commercial debt."
Riedy confirmed that his team had filed client applications exceeding $1 Billion in the USDA Section 9003 Loan Guarantee Program in recent weeks, using hybrid financing models developed by the team.
Category: Policy


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Even before New York Yankees outfielder Carlos Beltran landed on the 15-day disabled list, the case could be made that Ichiro Suzuki deserved more playing time in the team's crowded outfield and lineup.
Now that Beltran is out for the foreseeable future with surgery possible, the door is open for Ichiro to start full time with one less player to compete with for an everyday role.
Suzuki has taken part in 30 of the team's 40 games and done a stellar job bouncing around as a starter, pinch-hitter and even a defensive replacement from time to time. The 40-year-old is hitting an impressive .364 with two RBI and a .397 OBP in only 55 at-bats.
The only hiccup Ichiro has had this season is his current back injury, which was a result of a diving play the outfielder made. Suzuki was available to play Thursday night, but never got into the game. Still, it's a great sign that the veteran is feeling much better and a rainout on Friday gave him an extra day to rest.
Ichiro finally available tonight, Girardi says #Yankees
— Brendan Kuty (@BrendanKutyNJ) May 15, 2014
What Ichiro doesn't have that Beltran does is power. Obviously the Yanks can't just plug Ichiro into the middle of the order and expect him to do what Beltran can, but putting him near the top of the order or towards the bottom could make Suzuki a valuable table-setter in either facet.
Manager Joe Girardi is a man who loves matchups and that bodes well for Ichiro, who is hitting .444 versus lefties this season while posting a .324 average against righties. That's correct, Ichiro (a left-handed batter) has better numbers against lefties this season, thus making it impossible for Girardi to justify sitting Ichiro because of matchup concerns.
Beltran's absence still leaves New York's outfield crowded, however. That's because the Yanks need Alfonso Soriano's power on offense, Jacoby Ellsbury's reliable bat and Brett Gardner's recent hot hand at the dish. No problem there since Ichiro could easily start at designated hitter and platoon with Soriano in the outfield or take over on defense altogether considering he's a better defensive player than Soriano.
Zoilo Almonte cannot be a solution instead of Ichiro. The 24-year-old owns a .236 career average and the Yanks don't need any holes in their lineup after Beltran has already been subtracted. With the current state of their rotation, the Yanks need run production and Suzuki can give them a better chance of doing that than Almonte can by getting on base and racking up hits to keep innings going.
Girardi must realize that Ichiro's bat should be a mainstay in the Yanks' lineup from now until Beltran returns because he is quite simply the best option they have to help score runs and his numbers do nothing but prove that point.
Follow Michael Moraitis on Twitter: @michaelmoraitisTags: Baseball, Carlos Beltran, Ichiro Suzuki, Joe Girardi, MLB, New York, New York Yankees, Zoilo Almonte


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|Home > Entertainment > Article
Made in Australia ... Deep Purple founder Jon Lord gives Nick Stewart from Brisbane band george some last-minute direction for tomorrow's performance of his psychedelic rock epic Concerto for Band and Orchestra. Joining Lord's choice rockers on stage at the Opera House will be the Sydney Symphony Orchestra. The concert is part of the Sydney Festival.
Photo: Fiona-Lee Quimby
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|Expect this concerto to go all the way up to 11
|Today's Sydney Festival highlights
Also in Entertainment
Kylie song second most popular ring tone in Britain
Surviving Bee Gees consign their name to history
Pop diva Anastacia vows to beat breast cancer
Goodnight, Dr Crane
Actors focus on a new direction instead of simply remaining idols
The Man from Elysian Fields
PJ Harvey, Enmore Theatre
Incognita, Stalker Theatre Company
Close Your Little Eyes, Max Lyandvert
Balconies, Erth Visual and Physical
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Organized every two years on behalf of POPAI France, MPV is the one-and-only trade show that brings together an exhaustive range of marketing solutions dedicated to point on sale ! For more than 30 years, MPV has identified market trends and moved with the evolution of large companies.
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Crescioni Moray necklace in oxblood
Crescioni Moray necklace in oxblood
Hand-forged curved brass plate on adjustable burgundy leather cord. Leather and brass will tarnish and patina over time, giving each piece a unique look. Color: Oxblood Origin: Made in USA Materials: Leather, steel Dimensions: 5" pendant length, 1/2" pendant width, 19" cord length Care: Avoid applying lotions, sprays or perfumes while wearing this piece. Patina on brass can be removed with polishing cloth.
Vert & Vogue
Nadira and Ryan Hurley, the founders of Vert & Vogue, met in 2001 at a Parisian men's boutique that Nadira managed. After buying an entire new wardrobe from her, Ryan mustered the courage to ask Nadira on a date. A year later, they were married and, a year after that, living in New York. Vert & Vogue is the child born out of this love story, a combination of Ryan's passion for sustainable business and Nadira's fashion savvy. Look for thoughtfully curated clothing, footwear and home goods.
Do you have questions about this product? We're here to help!


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The Sound Recording Mixer will not open in Vista for Line In recording. I
tried installing the drivers for my Soundblaster but still don't get
anything. Does anyone have any ideas? I tried double clicking the speaker
icon but it doesn't work because it only opens the playing mixer that just
has 2 sliders on it for Main and Apps volume. There is no option anywhere for
switching to the Recording mixer.
Has the Record Mixer been removed because they want the Windows Sound
Recorder to be used exclusively now? The problem is the Sound Recorder
doesn't record MP3's.
This post is a suggestion for Microsoft, and Microsoft responds to the
suggestions with the most votes. To vote for this suggestion, click the "I
Agree" button in the message pane. If you do not see the button, follow this
link to open the suggestion in the Microsoft Web-based Newsreader and then
click "I Agree" in the message pane.


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Mike Taylor = 7-02-2014
Things did not go as planned for the U.S. soccer team at the World Cup
(Courtesy : Getty Images )
"Obviously, it's a bummer," said U.S. coach Jurgen Klinsmann. "We were so close. I mean, I think that we can ... all be very, very proud of this team. What they have done the last couple of weeks has been unbelievable, outstanding."
(Courtesy : Getty Images)
Patty Mills....the injury very few knew about until now.


text: 5. The other effectiveness findings (symptomatic benefits) are generally favorable but, with one exception (the Borg score), are potentially contaminated by unblinding because of injection site pain. And even the Borg and exercise test could be unblinded for the patient. Could some of them be persuasive anyway (e.g., rate of new appearance of a problem not reported at baseline?) and how does one deal with the high level of multiplicity? Slide 4 of 13


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Alleged car thief died of gunshot wound to the head
UPDATED: Tue., March 26, 2013, 9:55 a.m.
The man killed by a homeowner Monday morning after allegedly trying to steal a vehicle died from a gunshot wound to the head, according to the Spokane County Medical Examiner's office.
The man has been identified as 25-year-old Brendon T. Kaluza-Graham.
Kaluza-Graham had a lengthy criminal record, including multiple convictions related to car theft or possessing tools related to car theft. Most recently, he was sentenced to 120 days in jail in November for possession of vehicle theft tools.
He was featured in a 2009 Spokesman-Review story on the rise in area vehicle thefts.
Kaluza-Graham also was charged with several felonies in February 2012 after reaching for a knife in a fight with a Spokane County Sheriff's deputy. Deputies found substances believed to be methamphetamine, cocaine and marijuana on him at that time, according to previously published reports.
Kaluza-Graham died Monday after a homeowner in the 1400 block of Lee called 911 just before 8 a.m. to report that his vehicle had been stolen, that the alleged thief was armed, and that he had fired at the thief, according to Spokane police.
The back window of the SUV was knocked out, which police think is from the single shot fired by the homeowner, said Lt. Mark Griffiths. He would not comment on where the vehicle was when the shot was fired at the driver.
Police spokeswoman Monique Cotton said the vehicle was left running before it was stolen.


text: Last September, we moved to the "Little Rome" section of Northeast Washington, D.C. I expected it to feel a little more "holy" this Holy Week (perhaps "holier-than-me"?) but it's actually felt pretty ordinary, quiet, and not very springy yet. Here and there I see some crocuses insisting on coming up through fall's accumulated leaves, and [Read More…]


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Munch Money by Carissa Bonham
Welcome! You are browsing as a guestWould you like to see 3 projects made from this pattern and much more? create a free account What am I missing?
Munch Money
This pattern is available for free.
A wee little coin purse to hold your change on the way to the bakery (to buy cupcakes, of course!).
This pattern is only available to recipients of Cupcake Factory samples in the April Phat Fiber box and by request from members of the Cupcake Love group.
This pattern is a sample of what can be made by knitting this yarn at a dense gauge ideal for bags and backpacks. Garments, blankets and dishcloths will be happier with larger needles and a looser gauge.


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The Princeton School District levy will drop at least 3.13 percent from the previous levy for the 2014-15 school year.
The School Board set the preliminary, or maximum possible, levy at its Sept. 24 meeting at $4.91 million. The current levy is $5.07 million.
The biggest reason for the decrease is because the state is equalizing more of the funding, according to district Finance Director Michelle Czech. Also, the debt levy is decreasing by $89,595, to end up at a little more than $2.56 million.
The community education levy is also dropping by $10,161 to total $238,402. The general levy part will be at a little more than $2.13 million, a decrease of $59,065 over this year.
The learning levy component of the general levy will be dropping $43,597 to total $767,805. The Princeton School District is in good financial shape because of having passed a referendum to renew a $1.5 million annual operating levy referendum in 2011, according to Czech. School districts that did not pass such a referendum will be forced now by the state to levy extra money for their general education levy, and the taxpayers in those districts will notice the change.
The public's chance to give input on the levy will be at the Dec. 17 School Board meeting, which will begin at 7 p.m. The board will certify the final levy during the meeting.


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This 70 mile round trip tour takes you down stream on the Snake River to the confluences of the Imnaha and Salmon Rivers. We stop at Dug Bar and see the Historical Nez Perce Crossing. You will see exotic rock formations, wildlife and beautiful scenery.
We have lunch along the riverside, take a dip or swim and continue downstream to the confluence of the Salmon River. This tour includes lunch, beverages and great memories of fun in Hells Canyon. You will want to bring your cameras, sunscreen, shorts or swim suits, and a towel.
Morning of the tour – directions and information you will need:
Optional Shuttle fee to Marina – $20.00 per person for the round trip. Reservations required.
If you are not staying with us the night before the tour, you will need the following information:
Day of Tour: Arrive at office in White Bird by 8:45 a.m PDT (Pacific Day Light Time)
Directions to office:
Take the White Bird Exit off of U. S. Hwy 95. This will take you to the only stop sign in the center of town. Take a left at the stop sign and go one mile SW on Old Hwy 95 along White Bird Creek. You will see our signs that say "Killgore Adventures & Hells Canyon Jet Boat Trips & Lodging". Our office and motel facilities are on the right side.
We will have you sign a release form and give you directions to the Marina or you can board the shuttle. You will drive another 17 miles to the Marine and the departure point for the Wild River Tour through the Wilderness in Hells Canyon's Wild River section. This drive will take about 45 minutes. It is a very pretty scenic drive and you may see wildlife along the way. It is graveled most the way but is suitable for two wheel drive passenger cars. Restrooms available at the office, the marina, and the stops we make on the tour.
We are on Pacific Day Light Time (PDT) – The time zone changes to mountain time at Riggins, only 28 miles South of White Bird….Mountain Time is (1) one hour ahead of PDT.
Please allow enough travel time for traffic/construction delays.


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Walkthrough: Creating a Stored Procedure in Managed Code
You can write stored procedures for Microsoft SQL Server 2005 and SQL Server 2008 databases in managed code by using .NET Framework languages such as Visual Basic and Visual C#. Stored procedures that are written in managed code are called SQL Server Common Language Run-Time stored procedures or SQL CLR stored procedures.
You can create SQL stored procedures by adding Stored Procedure items to SQL CLR database projects. After you deploy stored procedures that you created in managed code, those procedures are called and executed like any other stored procedures.
Tasks illustrated in this walkthrough include the following:
Creating a new SQL CLR Database Project
Creating a stored procedure in managed code
Deploying the stored procedure to a SQL Server 2008 database
Creating a script to test the stored procedure on the database
Querying data in the database to confirm that the stored procedure executes correctly
In order to complete this walkthrough, you need:
A connection to the AdventureWorks2008 sample database running on SQL Server 2008. For more information, see the Microsoft SQL Server Product Samples page on the Microsoft web site.
To create the new SQL CLR database project
From the File menu, create a new project.
Select SQL CLR Database Project, name the project SQLCLRStoredProcedure and click OK. For more information, see How to: Create a Project for Database Objects that Use SQL Server Common Language Run-time Integration.
This walkthrough requires a connection to the AdventureWorks2008 sample database running on SQL Server 2008. If a connection to the AdventureWorks2008 sample database is available in Server Explorer, it will be listed in the Add Database Reference Dialog Box.
To connect to the AdventureWorks sample database
Connect to the AdventureWorks2008 sample database included with SQL Server 2008 by completing the Add Connection dialog box. For more information, see Add/Modify Connection (Microsoft SQL Server).
Select an existing connection to the AdventureWorks2008 sample database in the Add Database Reference dialog box. For more information, see Add Database Reference Dialog Box.
After you create your SQL CLR database project, you might need to modify several project properties before you can successfully deploy your project.
To configure properties for the SQL CLR Database Project
In Solution Explorer, select the project for which you want to configure properties.
On the Project menu, click ProjectName Properties, where ProjectName is the name that you gave the SQL CLR database project.
On the Application tab, in Assembly name, specify the name that you want to give the assembly that is built from your SQL CLR database project.
On the Application tab, in Target Framework, click the version of the .NET Framework that is supported by the target version of SQL Server.
SQL Server 2005 and SQL Server 2008 only support SQL Server projects that were built with the .NET Framework 2.0. If you try to deploy a SQL Server project to SQL Server 2005 or SQL Server 2008, an error appears: Deploy error (SQL01268): .NET SqlClient Data Provider: Msg 6218, Level 16, State 3, Line 1 CREATE ASSEMBLY for assembly 'AssemblyName' failed because assembly 'AssemblyName' failed verification. Check if the referenced assemblies are up-to-date and trusted (for external_access or unsafe) to execute in the database (where AssemblyName is the name of the assembly that you are deploying).
On the Database tab, in Assembly Owner, type the name of a user or role as the owner of the assembly.
This value must be either the name of a role of which the current user is a member or the current user must have IMPERSONATE permission. If you do not specify an assembly owner, ownership is given to the current user. This setting corresponds to the AUTHORIZATION owner_name argument for the SQL Server CREATE ASSEMBLY statement. For more information, see CREATE ASSEMBLY (Transact-SQL) on the Microsoft Web site.
On the File menu, click Save All.
After you create the SQL CLR database project, add a stored procedure to it.
To create the SQL Server stored procedure
On the Project menu, click Add New Item.
In the Add New Item dialog box, select Stored Procedure.
Type InsertCurrency as the Name for the new stored procedure.
Click Add.
Replace the code in the Code Editor with the following:
using System; using System.Data; using System.Data.SqlClient; using System.Data.SqlTypes; using Microsoft.SqlServer.Server; public partial class StoredProcedures { [SqlProcedure()] public static void InsertCurrency_CS( SqlString currencyCode, SqlString name) { using (SqlConnection conn = new SqlConnection("context connection=true")) { SqlCommand InsertCurrencyCommand = new SqlCommand(); SqlParameter currencyCodeParam = new SqlParameter("@CurrencyCode", SqlDbType.NVarChar); SqlParameter nameParam = new SqlParameter("@Name", SqlDbType.NVarChar); currencyCodeParam.Value = currencyCode; nameParam.Value = name; InsertCurrencyCommand.Parameters.Add(currencyCodeParam); InsertCurrencyCommand.Parameters.Add(nameParam); InsertCurrencyCommand.CommandText = "INSERT Sales.Currency (CurrencyCode, Name, ModifiedDate)" + " VALUES(@CurrencyCode, @Name, GetDate())"; InsertCurrencyCommand.Connection = conn; conn.Open(); InsertCurrencyCommand.ExecuteNonQuery(); conn.Close(); } } }
After you create a new stored procedure, it can be built, deployed to the SQL server, and debugged by pressing F5. First, in the Test.sql file found in the TestScripts folder of your project, add code to execute and test your stored procedure. For more information about how to create test scripts see, How to: Edit the Test.sql Script to Run Objects that use SQL Server Common Language Run-time Integration.
For more information about how to debug SQL, see Debugging SQL Database Objects.
To deploy, and run the InsertCurrency stored procedure
In Solution Explorer, expand the TestScripts folder and double-click the Test.sql file.
You can specify other scripts as your default debug script. For more information, see How to: Edit the Test.sql Script to Run Objects that use SQL Server Common Language Run-time Integration.
Replace the code in the Test.sql file with the following code:
'VB EXEC InsertCurrency 'AAA', 'Currency Test' SELECT * from Sales.Currency where CurrencyCode = 'AAA'
//C# EXEC InsertCurrency_CS 'AAA', 'Currency Test' SELECT * from Sales.Currency where CurrencyCode = 'AAA'
Press F5 to build, deploy, and debug the stored procedure. For information about how to deploy without debugging, see How to: Deploy SQL Server CLR Integration Database Project Items to a SQL Server.
View the results that are shown in the Output window and select Show output from: Database Output.


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Kate Middleton Gossip
Kate Middleton gossip, latest news, photos, and video.
Smutty Social Media, July 7, 2016
Has Kate Middleton ever knowingly appeared on Snapchat before? And do you think Serena had to ask permission? I'm guessing no. It's Serena Williams. Serena and Kate 😍 pic.twitter.com/wzsmKkJJyh — Shanice Bajin (@SWilliamsFans) July 7, 2016 Full Story
The Cambridges at Royal Ascot
Prince William and Catherine were at Royal Ascot today. It's been a busy few days for the Cambridges – Trooping The Colour, the Garter Day service, then a quick trip to Northern Ireland, the people are getting their fill of "work-shy" Will and "lazy" Katy. Full Story
The Queen in green and the Royal Balcony
Wenn, Max Mumby/ Indigo/ Chris Jackson/ Anwar Hussein/ Getty Images
The Queen's 90th birthday celebrations continued this weekend with a big display of family togetherness on the royal balcony at the end of the Trooping The Colour procession. As always, the placements are key which is why Big G shoved his way to the front, making sure he had the best view. He owns this view. Full Story
Her Majesty's Birthday Weekend
Danny Martindale/ Jeff Spicer/ Stuart C. Wilson/ WPA Pool/ Getty Images
The Queen celebrated her actual 90th birthday in April but this weekend is the mega blowout in London. All mega blowouts start at church, which is where the royal family gathered today for a thanksgiving service. Full Story
The Princess and her portrait
Wenn, Bauer-Griffin
Busy day for Princess Catherine. Three official events ending with a visit to the National Portrait Gallery where her VOGUE portraits are now on display. As revealed earlier this week, Kate covers the new issue of British VOGUE to celebrate their 100th anniversary. Full Story
Princess Kate covers VOGUE
It's the 100th anniversary of British VOGUE. To commemorate the occasion, Katy Cambridge is on the cover of the June issue and the portraits will be on display at the National Portrait Gallery. Full Story
Dear Gossips,
Five years ago today, also a Friday, I was positioned at the Duke of York monument in London reporting from the royal wedding live on CTV, waiting for Will and Kate to pass by on their carriage after getting married at Westminster Abbey. Read Full Intro
Dear Gossips,
Middle fingers up Put them hands high Wave it in his face Tell him… Boy bye Like, what else is there to talk about today? Because, really, there is only Beyoncé. And we will definitely be talking a lot about Beyoncé. Read Full Intro
The Obamas and the young royals
Chris Jackson/ WPA Pool/ Getty Images
President and Mrs Obama are dining tonight at Kensington Palace with the Cambridges and Hot Harry. In other words, two borings and a fun. Is that why the President is standing next to Prince Harry? Because between them and FLOTUS they have to carry the charisma at the table? The thing about a Friday night dinner party is that, well, for non-dignitaries, you have the option of the extra drink(s). Full Story
Dear Gossips,
William and Catherine Cambridge will celebrate their 5th wedding anniversary exactly a month from now on April 29th. To celebrate the occasion Reelz is apparently airing a four part documentary series about their relationship. Read Full Intro
The Cambridges' selective reporting
Twitter, Danny Martindale/ Pool/ Getty Images
Princess Catherine covers this week's issue of PEOPLE Magazine. It's all about how she's following in Diana's footsteps and what a great mother she is to Big G and Charlotte and how she's been able to fit into her role as senior royal and future Queen. Full Story


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Abu Dabab 1
Quick update
I've started working/studying in Abu Dabab (7 days per week...). Unfortunately we have only intermittent access to a 56k modem. When I get a day off I'll try to get to Marsa Alam and upload some pictures and more infos from there.
All is well, diving is fantastic, tempreatures above 25 Celsius. For the kite-/windsurfers out there, there's a lot of wind right now. People say it's going to last until the end of may, so pack your things ;-)
Posted by 5fingerfab 05:28 Archived in Egypt Tagged round_the_world


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The Guitar
Dir: Amy Redford. US. 2008. 93mins.The suggestive metaphor of loss and emotional trauma as divine liberation is treated awkwardly between the outrageous and obscene in Amy Redford's debut feature The Guitar. Saffron Burrows is commanding as a distraught woman who finds a novel way to cope with tragedy, but the movie constantly subverts realistic detail with the fantastic in waysthat are not dramatically satisfying.
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