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| View Exclusive AAUP Compensation Survey Data |
Colleges and universities can't leave it to chance -- they must deliberately change a culture that often encourages female researchers to become isolated in their jobs, write Santa Ono and Valerie Gray Hardcastle.
Women who are expecting a child need a strategy for attending academic meetings, writes Tamara Yakaboski.
New report aims to hold individual athletic programs accountable for failure to hire female coaches on women's teams.
Recently, I had lunch with a group of women who had moved to the upper levels of leadership in higher education. As is usual when such a group gathers, we talked about some of our more "challenging" moments as the first women provosts, deans or presidents. But this time, the stories were about team-building experiences that didn't quite work when a woman was added to the mix.
One dean recounted the weekend retreat she was required to attend at the president's cottage, where after a day of activities, everyone was expected to join the others... in the hot tub, which makes for an awkward splash if you're the only one wearing a two-piece. Another woman described the "bonding" day her executive vice president led that involved a race with her colleagues in the equivalent of bumper cars. And still another described a hunting and fishing expedition more akin to a men's sweat lodge.
Each story left me wondering: with the increasing mix of men and women in prominent leadership roles, is something lost if institutions of learning have to adjust their informal interactions? Do the guys no longer feel free to be, well, guys, if a woman is suddenly in a cabinet meeting? And is that a bad thing? I don't think so.
When I first went to graduate school, a wise senior professor commented one day on how glad he was that more women were in his classes. "It had started to feel too much like a men's club," he announced. Similarly, another colleague once told me that a member of Margaret Thatcher's cabinet had remarked how relieved he was not to be in a "men's club" any longer, now that Thatcher was around. In other words, the presence of women — or I should say the presence of women and men together — moves things up a notch. It makes men grow up.
Or put in a more ladylike way, groups of mixed gender encourage more professional interactions to the benefit of all. Such professionalism allows everyone to develop more balanced lives where colleagues are expected to be just good colleagues, and faculty then see mutual respect modeled. Sure, some may become friends, but that's not the point. And maybe it frees the men from having to join in the hot tub as well!
In fact, the potent combination of women and men in campus leadership together challenges old school thinking. It counteracts men's tendencies to invest everything in their work because when women lean in to opportunities of institutional advancement, men are also required to become partners at home.
And when both contribute in leading both a university and a home, each benefits. Men gain the freedom to develop a rich set of relationships in and outside academe while developing a fuller range of human and emotional experiences, made more possible with the presence of women. And for women, the university begins to recognize — and affirm — the existence of a life beyond the classrooms.
With women now leading more at higher levels of academic institutions, both the workplace and personal lives can shift, allowing us to form real partnerships in the process of negotiating our ever-changing realities. Rather than creating unhealthy dependencies or enabling behavior that responds only to rigid cultural expectations — like the "guys' clubs" can do — both discover a new freedom to grow as human beings. As one author put it, "The difference between the equal sharers (co-parenting and dual career) and other couples was not that mothers cared less, but that fathers cared more."
So when women "lean in" at the academic leadership table, that is, when they advance in their scholarship and campus leadership roles, men begin to care more about their children and others, not less. But when we don't collaborate, women and men alike tend to work under the assumption of stereotypes perpetuated by the popular media and the unfortunate data of lopsided gender roles in higher education, rather than enjoy the range of gifts that each individual can contribute, man or woman.
In short, we rise together. At another "bonding" retreat for leaders, I once played the game where two individuals sit back-to-back on the floor. We had to lean into each other, exerting equal pressure, in order to stand. It's a good metaphor for what can happen when men and women also rise to yet greater heights and health. A woman doesn't hesitate to lean in and a man meets the challenge because they need each other to get off the ground. We rise together when each exerts the same amount of pressure, benefiting students and faculty alike. And when that happens, I suspect the stories will be much different at the next lunch gatherings.
Janel Curry became the first woman provost at Gordon College in 2012. As a cultural geographer, she has served as a professor, chair and dean in higher education for over 30 years.
One college unexpectedly found that female engineering students responded particularly well to its project-based learning approach. Experts say the curriculum could help attract and retain women in the STEM fields.
Political scientists consider whether advances for women in the discipline will come from copying questionable male tactics or from changing the nature of values of the field.
Complaint says college violated Title IX by refusing to allow a student dealing with a high-risk pregnancy and delivery to miss some classes without penalty.
If all the physics professors at a college are men, is that a sign of bias? Not according to analysis by the American Institute of Physics.
This essay is as timely as it is unlikely. Timely, because many studies have correlated economic crises, such as the one corroding the academic job market as well as so many other career prospects, with a rise in domestic abuse. Unlikely, because I am far from the type of person whom one would expect to chronicle personal experience in this area.
None of the stereotypes apply. I am a professor at a respected university with what many people (not just my mother) would describe as an international reputation in her field. The product of a white, upper-middle-class professional household, I seldom heard my father raise his voice to my mother -- his raising his hand would have been inconceivable. Their marriage was perhaps not one made in heaven, but neither was it an instance of cruelty by any stretch of the imagination. And I did not and do not have a pattern of involvement with abusive partners; indeed, for the past 22 years I have enjoyed a very happy and stable relationship with a compassionate and supportive man.
I had thought I had every reason to anticipate a happy and stable relationship in my erstwhile marriage as well. My ex-husband and I shared many cultural interests and were anticipating careers in the same field within the humanities, with similar pedigrees and similarly strong academic records. By chance my career, however, started more smoothly than his, despite his impressive credentials and abilities, indeed gifts. I finished graduate school a year before he did in the '70s — shortly after the precipitous decline in the job market -- and obtained a tenure-track appointment while he was completing his dissertation. We then moved for compelling personal reasons, and I was fortunate enough to find an academic position again, but he did not do so.
My ex-husband had slapped me once early in our marriage when, because I had not understood and hence had not followed his instructions during a household repair, a small amount of water fell on him. I was shocked, but I viewed the episode as an aberration. It was not.
That event suggests that the recurrence of such abuse cannot be wholly blamed on his not having a job. And after all, many unemployed people do not descend into such behavior, while many who are guilty of it hold stable jobs. Nonetheless, the timing persuades me that my ex-husband's not obtaining the sort of position he had hoped for contributed significantly to the recurrence of wife-beating. For shortly after we had moved and I, but not he, held an academic appointment, physical abuse started again. He pinched, shoved, and hit me with some regularity over a period of about a year. Not by any means the most violent wife-beating, but quite enough, thank you, to leave significant black-and-blue marks on one occasion and less visible scars on the others. The physical abuse was accompanied by persistent belittling remarks. Throughout all this, my ex-husband continued to appear in public as a charming and highly educated gentleman and a courteous husband. I later learned that this Jekyll-Hyde scenario is a common symptom of pathologies like his.
Why did I put up with it? Barely able to believe that this was happening between people like us, I made excuses for him, justifying his behavior as a regrettable but understandable response to his unemployment, which was clearly all the more difficult for him because I had an attractive job in the same field. The contrast between his public and private behavior made it harder to confront the events squarely, as did the ways the situation sapped my own self-confidence. Like many victims of domestic abuse, I began to blame myself, not realizing that although I had made real mistakes, such as occasional tactless remarks, they neither explained nor justified this physical and emotional maltreatment.
Moreover, like many wife-beaters, he repeatedly seemed to repent. On the several occasions when I finally resolved to leave, he admitted that situations for which he had blamed only me were in fact in large measure his responsibility, and he promised to get therapy. These apparent reversals were, I was to discover, as much a pattern as the violence itself, and the therapy never materialized.
His career not only got back on track but flourished after that year of unemployment — a good though temporary job one year, a tenure-track job the next, the publication of a well-received book by a leading press, and so on. The physical abuse stopped shortly after he gained those academic positions, though the emotional analogues to it did not, and for that and many other reasons I finally, belatedly, got a divorce.
What I learned is relevant to anyone, man or woman, suffering domestic abuse.
Realizing that stressful circumstances outside the home -- and one's own behavior -- may have contributed to tension is a very different matter from excusing the behavior or shouldering all the responsibility oneself. Distinguish compassion from submission: it's healthy to understand the financial pressures that might bring out this type of violence in some individuals, but no one should accept its continuation. Be alert to connections between the physical and verbal, recognizing that physical abuse often merely goes into remission or resurfaces as verbal wife-beating. Apologies and promises need to be backed up with concrete and reliable evidence for believing that change will occur.
But one step must precede and accompany all of these: Avoid the temptation to excuse or deny the abuse by saying, "This isn't really occurring, and it will stop any minute because things like this don't happen to a professional couple like us." They can. They do. And, sadly, in this academic job market, they will.
The author of this piece, who asked to remain anonymous, is a tenured professor.
After learning that a faculty member at San Jose State was found by the university to have inappropriately touched a student, many want to know why he's still teaching.
Inside Higher Ed
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Subject: Re: [htdig] Problems with iso characters
From: Petri Lankoski (firstname.lastname@example.com)
Date: Wed Oct 18 2000 - 03:57:12 PDT
Torsten Neuer writes:
> Did you set the correct locale in the configuraton file for the db?
> See http://www.htdig.org/FAQ.html#q4.10 for more information.
I have set locale as fi_FI (locale: fi_FI) in htdig.conf. Rest of
system works fine with fi_FI locale. I.e accepted 8 bit characters.
I don't use Finnish dictionatry (except bad word list) because its
useless with Finnish grammar (ispell approach don't work:).
-- Petri Lankoski I love colors I wear firstname.lastname@example.com I wont cut my hair http://www.iki.fi/~kreivi/ d.a.d PGP: http://www.iki.fi/~kreivi/pgp.txt
------------------------------------ To unsubscribe from the htdig mailing list, send a message to firstname.lastname@example.com You will receive a message to confirm this. List archives: <http://www.htdig.org/mail/menu.html> FAQ: <http://www.htdig.org/FAQ.html>
This archive was generated by hypermail 2b28 : Wed Oct 18 2000 - 04:02:11 PDT

subset: commoncrawl


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Irving Park Ice Bowl 2013
Disc golf singles tournament
About this tournament
sam merciers January 20, 2013 at 5:15am
Thanks to you guys for a great tourney and for the $105 in the ace pool throw off. Great course, great tourney and a great cause. Hope to do it again next year.
Marty McKibbin January 19, 2013 at 1:44am
Those not listed Please send me your score card #'s so I can post them ! Thank You again for your support and look forward to seeing you next year !
chad curtis January 15, 2013 at 5:19pm
Sorry for the delay in posting scores. (A few players kept their reg cards for souveniers). We should have all scores posted and linked by Friday.
57,77 Had never been given my score card before. Sorry for taking it.
chad curtis January 13, 2013 at 4:48am
Good tourney today. We collected several hundred pounds of food and a stack of cash for the Foodbank. Congrats to all the Winners, thank you sponsors and volunteers. Golfers-- we hope you had a good time and enjoyed the course. See you next year!
Cody Whitney January 12, 2013 at 11:04am
That's supposed to be Cody Whitney recreational not Kyle Whitney
Jim Knudson January 11, 2013 at 11:41pm
Jim Knudson #45632 (Intermediate , Masters or Grandmasters)
Sam Merciers (Rec)
chad curtis January 11, 2013 at 6:35pm
Tomorrow is the day! Not too icy but it might be the warmest round of golf this winter. Walk up registration is available. Please dig deep and bring as much food as you can donate.
Ben Ross January 11, 2013 at 4:58am
Is there still a pre-pay option? I'm not seeing the link...
it closed on the 31st. If you need to pay with credit. we can still do that. call me 269-245-9397
Tyler Cole January 8, 2013 at 10:12pm
Un reg Tyler cole 56494 am3 thx ill be outta town family stuff sry can't make it anymore.
Jeremy Gattes January 8, 2013 at 4:27pm
Unreg Jeremy gattes am 1 thanks
Christopher Cretsinger January 5, 2013 at 3:58pm
Cj Cretsinger Recreational
Rick McBain January 4, 2013 at 1:08pm
Chad please unregister me, it looks like im going to have to sell drugs this day... :(
randy johnson January 4, 2013 at 9:03am
Randy Johnson am 3 54492
Steve Blink January 4, 2013 at 6:41am
Blink Open 48305
chad curtis January 4, 2013 at 4:07am
Update!! We still have not had PDGA confirmation on the C-tier status of this event. Because the Icebowl is only 9 days away we are going to play it safe and go UNSANCTIONED. If you pre-reg'd and would like a refund, please contact Marty McKibbin or Chad Curtis.
We still intend to make this a top notch event. Great players pack--Icebowl disc, towel and IPA sticker, tons of CTPs and Long Putts, chili, free campfire, and a fresh layout for the tourney.Please support the Foodbank and bring a HUGE donation!!
Why don't you just call them. It can all be worked out in like 5 minutes I am sure
I'm just doing the online promotion for the TD. He wanted to play it safe and call it off ahead of time.
Jeremy Gattes January 3, 2013 at 3:44pm
Jeremy Gattes #16905 Am 1 please and thank you


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Independent state Senate candidate Jeremy Hansen, running in Washington County, today demonstrated a sophisticated beta website where voters can comment, weigh pros and cons, and direct Hansen's potential Statehouse vote.
Hansen pledges, if elected, to make policy decisions solely based on his constituents' online input. He says he will state his own opinion on matters, but will otherwise vote according to the information gathered by this interactive platform.
"People need to have a louder voice in a more direct way," said Hansen, currently an assistant computer science professor at Norwich University. "We have the technologies to do this. Why not make it work?"
Hansen was quick, however, to point out the limitations of the technology. "The difficulty is convincing people that this could work," Hansen said. "I'm the first person to say it's possible that it might not work, though I'm of the opinion that this is a powerful tool for people to ensure that their legislators are actually representative."
If results show that voters are undecided or conflicted on a specific issue, on an issue like protecting Berlin Pond, Hansen said he'd likely vote according to his own views, or possibly abstain.
Hansen wasn't sure whether this sort of "statistical dead heat" would happen often.
The platform itself, which Hansen unveiled via a lunchtime webinar, is being pitched to other political candidates and elected officials nationwide, with some interest from candidates in Vermont, Atlanta and Massachusetts, as a tool they could use come 2014 or sooner.
Some are dubious about whether the platform actually represents an interesting or viable development.
"I doubt his website will engage many people, especially those who do not now participate much in the political process," said Wally Roberts, executive director of nonprofit Common Cause Vermont. Roberts pointed out that enticing even 50 percent of registered voters to a non-presidential election is difficult, and argued that only political, news and computer "junkies" would engage with the website.
Roberts also remarked that basing legislative action mainly on website votes allows special interests to organize a large online bloc vote, to push a partisan agenda.
State Sen. Bill Doyle, R-Washington, an incumbent in one of the seats Hansen hopes to capture, said the website was a smart idea, but that it's sometimes difficult to get in touch with constituents.
"I'm sure there'd be much interest," said Doyle, who noted that many candidates may not be as tech-savvy as Hansen. "I think he's consistent with the information age."
Doyle suggested the website could be a supplement to rather than a replacement of his annual Town Meeting Day survey.
Hansen said he's been pondering this idea for about a year now. He developed the concept with Florida congressional candidate Philip Dodds and computer scientist Dr. Travis Kriplean.
The experiment is also in keeping with recent direct democracy experiments across the nation, like the introduction of participatory budgeting in New York City last year, where community members directly establish government budget items.
Hansen says that so far feedback about the experiment has been positive, but a telling post on his campaign's Facebook page indicates otherwise.
Irvin Eisenberg today wrote: "The only problem people seem to have with it is that it doesn't reflect the voice of those who don't use the computer."
While Hansen has a ready response for this criticism, he said his platform for "direct representation" is somewhat idealistic, given the realities of Statehouse politics. He hasn't yet heard from traditional Vermont party leaders about his website or campaign.


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Home :: SMART PHONES :: Samsung Galaxy S4 LTE
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|13MP rear, 2MP front
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|Quad-core 1.6 GHz & quad-core 1.2 GHz
|Micro SIM
|370 hour standby, 17 hour talktime
|16GB, microSD up to 64GB
|Samsung Galaxy S4
|Download user manual
Capture moments with the 13MP autofocus camera on the new Samsung Galaxy S4. Take simultaneous front and back photos with Dual Camera, edit them right on your phone with Eraser Shot and relive the memories in brilliant clarity with Story Album.
Experience a whole new way to interact with your smartphone. Wave your hand at the screen to accept calls with Air Gesture, read content by tilting your head or phone with Smart Scroll and preview content by barely touching the screen with Air View.
View all your content on a stunning 5-inch Full HD Super AMOLED™ display that's powered by a robust 1.6GHz quad-core processor - all in a light 0.29LB smartphone.


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State 4-H Leaders' Forum
The State 4-H Leaders Forum provides a weekend retreat for 4-H volunteers across California to gather for networking, education, relaxation, and fun. Volunteers of all ages, experiences, and locations share this opportunity to further their volunteering "career," find new inspirations, and bring new ideas home to their counties and clubs.
Some of the best, most practical learning for 4-H leaders happens here. You'll come home loaded with ideas and activities and the enthusiasm to implement them. Your County 4-H Program becomes stronger because of your participation. You will return with a deeper understanding of the 4-H mission, a stronger sense of what has to happen to accomplish it, and an expanded capacity to make it happen.
2016 State Leaders' Forum
Some of our most productive and happiest moments come from connecting with friends, sharing ideas and challenges with people who share your interests, and getting the tools and support to bring your own contribution to a higher level.
The conference will focus on building the capacity of our adult volunteers to be even more competent in helping our 4-H youth thrive. The goal is to provide quality education sessions with take-home strategies and be able to invigorate all attendees for the program year(s) ahead. Get ready to be happy - and engaged!
Spread the word!
NEW! Poster Submissions
We're excited to announce the opportunity to present a poster at this year's State Leaders' Forum!
Got Ideas? Got Experience to Share? Got Questions?
That's what a Poster Session is all about – and we're looking forward to the mix of what you're ready to bring, or trade!
Poster Session Submission Requirements:
1) Poster topics have to be relevant to and supportive of the interests of 4-H Adult Volunteers
2) Posters must be submitted by SLF attendees
3) Contact and Topic information must be provided by 10/15/16 to Linnaea Knisely, Ed Chair, SLF (email@example.com). Please use the Poster Session Form to send Linnaea the information about your poster and any set-up support needed.
See the Poster Tips on creating an effective poster.
The State Leadership Forum provides 4-H volunteers, staff and outside resources the opportunity to share their best practices and newest information for the professional development of the delegates.
Tried and true, clever and innovative, the educational content of the State Leadership Forum is supportive of the need for leader advancement and updated methods and materials.
We've selected speakers who are guaranteed to inform and excite you, a destination that offers a wealth of fun explorations, and a series of workshops which will help you make some of the connections that you've been searching for. Attendees will CONNECT to great information! For example:
- How to make Club Meetings fast, fun and effective! (We're serious!)
- How to successfully gain - and retain members!
- Great tips on fundraising, and fundraising resources!
- How to tap into your "Millenials" AND your recent alums as adult volunteers!
- Great games for fun and learning!
- The best animal management practices from feed to slaughter!
- The best way to teach, so that youth can learn
- Successful practices for problem parents!
- How to understand and positively manage kids across the spectrum!
Please see the Workshop Descriptions and Workshop Schedule for more information.
If you can't make it for the full weekend, plan to join us for a very full day on Saturday, November 12th, as that's the "workshop" day. Registration includes meals, but not lodging.
Register Online
Late Registration: June 16 to October 1
$200/person for entire event; includes five meals.
$125/person for Saturday only
Group Rate
Reference "4-H Leaders' Forum" to get the special room rates starting at $119 per night. The last day for the discounted room rate is Sept. 13, but hurry, the rooms are going fast! Make your reservations directly with the resort.
Flamingo Conference Resort and Spa
2777 4th St., Santa Rosa, CA 95405 (map)
Hotel Phone Number: 707 545-8530
Contact Us
Brenda Vales | Registrar
Linnaea Knisely | Educational Workshops
Charles Hampton | Tours
Alyssa Sankey | Staff Liaison


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Case Conclusion Date: 11.17.2009
Practice Area: Animal law
Outcome: Settlement reached
Description: Client was walking dog when reckless driver ran stop sign and ran over dog. Apprx $6,000 in vet bills to save the dog's life. Insurance initially refused to reimburse dog owner. Lawsuit was filed and settlement reached shortly thereafter.


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Another Program on Teen Consequences Scheduled
It's been called an incredible success in the past, and now the Caddo Sheriff's Office and Judge Scott Crichton are bringing it back again. It's "Don't Let This Be You," a program for teens illustrating the serious legal consequences of criminal behavior. The program is designed for those ages 13 and up and their parents. It'll be held Tuesday, January 17th, from 6 to 9 p.m. at Caddo Correctional Center on Forum Drive in Shreveport. Class size is limited, so you'll need to register in advance…but it won't cost you a thing. Just call the Caddo Sheriff's Office to do that.


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I am considering taking all my stamps our of CD/DVD cases. Have you done this?
View Single Post
Proud Fan Club Member
Join Date: Mar 2012
Location: Southern Florida
Posts: 4,815
I have some from Stampers Best and some are Sunday International Stamp N Stor, and I just ordered some EZ Mount brand from Crafter's Companion so I could compare. I found that the Stampers Best laminated panels are a bit smaller than 8.5 X 11, and this made it easier to slide them in when full of stamps, so I trimmed the others I had from Sunday International and rounded off the corners so they now fit better.
What do people use for the index sheets? Cardstock or just plain printer paper? Cardstock is nicer, but I'm not sure I want to use up so much white CS. I just got four small SU sets on a single panel, and now I have to do the index, and am trying to decide whether to keep using cardstock or not. So far, I have been.
The real voyage of discovery consists not in seeking new lands but in seeing with new eyes...
RachelRose Designs by Robin... GALLERY
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It may have seemed like a good idea in our new, culturally sensitive times: a ban on Christmas decorations at federal government buildings.
But a senior manager's directive to banish tinsel, trees and holiday wreaths from front-line Service Canada offices across Quebec came undone Friday as fast as gift wrap on Christmas morning.
By afternoon, the ban had been reversed by a federal minister who reassured Canadians that the Harper government did, in fact, like Christmas.
The backpedalling capped a day of denunciations, after the Quebec chief of Service Canada sent e-mails to employees telling them they could hang holiday decorations in their personal spaces, but not in areas serving the public.
Within hours, the ban at about 120 federal offices in the province had been ridiculed on Twitter, derided on open-line shows, and criticized by the very religious minorities whose sensibilities the government was ostensibly trying to respect.
The storm reached the House of Commons, where opposition MPs from Quebec seized on the matter.
"Why do the Conservatives want to steal the magic of Christmas from employees of Service Canada?" said NDP MP Alexandre Boulerice.
Human Resources Minister Diane Finley said there was no Canada-wide directive against Yuletide decor. By the end of the day, she issued a statement that she was asking Service Canada to send a new directive to employees telling them they can "celebrate Christmas or the holidays as they please. This includes decorations in Service Canada offices across Canada."
The move makes Santa safe for another year. Beyond the rhetoric, however, the measure struck a chord about cultural and religious displays in the public realm, a controversial issue in Quebec. The anti-decoration rule had already taken hold at Ottawa's major front-line services building in Montreal, the Guy Favreau complex. There was not a shred of holiday decor in the cavernous downtown building.
The union representing Service Canada employees in Quebec initially supported the ban, but retreated by the end of the day.
"It's absurd," said Sylvain Archambault, a spokesman for the Canada Employment and Immigration Union. "But we have trouble in Quebec with handling Christmas. As a society, we're struggling to figure out how to deal with reasonable accommodations [of minorities]"
Mr. Archambault said the measure was meant to keep decorations out of unemployment insurance offices. "We're not supposed to look festive while you're waiting for your UI cheque," he said.
Religious minorities, meanwhile, lined up against the ban. Salam Elmenyawi, head of the Muslim Council of Montreal, said he enjoys seeing Christmas lights and other decorations.
"I guarantee you, for most Muslims this is a non-issue," he said. "I'm not offended by these decorations at all. They remind us of the spirit of giving."
Others denounced the measure as another federal offensive by the Tories that would rub Quebeckers the wrong way. One person on Twitter wrote: "Portraits of the Queen everywhere, but no Christmas trees??!!"
With a report from Gloria Galloway in OttawaReport Typo/Error
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Australia's obsession with building new roads at the expense of rail networks is harming the country's international competitiveness, business leaders have warned amid calls for changes to transport funding.
"The rail industry is not after handouts but rather is seeking a level playing field through pricing and policy reform," said
Grain exporters are becoming increasingly frustrated with Australia's poor freight rail networks, claiming lack of investment in rail infrastructure, which has reduced haulage loads and created track congestion, is forcing more grain onto trucks.
A decade ago, 90 per cent of grain exported by GrainCorp arrived at ports by train but today only 10 per cent does, creating some 44,000 extra truck journeys annually.
Boosting exports
Agricultural companies say farmers would transport more commodities by rail if networks were better.
"Australian exports would be a lot more competitive if we had a better under-rail system and farmgate returns would improve as well," said Cargill Australia spokesman
"Rail is a lot more efficient than road and it's a lot cheaper."
Freight rail operators want regulatory changes to road charges to lower the comparative cost of using rail networks.
"Transport infrastructure investment decisions have typically been incremental in nature, heavily skewed towards road infrastructure and not 'game-changing' or 'nation-building'," said
"These road investments, the lack of game-changing rail investments, and the disproportionate comparative cost of access to use rail compared to road, have all made freight on rail uncompetitive on short haul routes, and much less competitive on long haul routes."
Balanced approach
Both Asciano and Aurizon are pushing for changes to charges applied to trucks for using roads, arguing trucks should pay fees linked to how far they travel and the roads that they use.
The rail industry is facing a 70 per cent drop in funding over the next four years, said
"Rail received $2.7 billion in the federal budget, none of which was new money," Mr Nye said.
"This was a mere drop in the ocean compared to the $26.8 billion for roads produced over the forward estimates."
Freight consultants Juturna Infrastructure, which claim freight represents around 30 per cent of the total cost of grain production, described the east coast's rail networks as "a series of degraded and disconnected 19th century branch line operations" in a report earlier this year.
The Australian Financial Review


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Storage Cube
I like the ikat storage box on the top.
these decorative bone boxes are so pretty. a great way to store small items while keeping your home looking beautifulTags: storage, home decor, cube, organization, glam, home accents, West Elm, rectangle, Cool HuntingAdded 8 Years Ago from West Elm
I would love to buy this for my family room to organize and hide clutter and toys from my 2 year old. :)


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In Australia, professional degrees can be undertaken either straight from high school at the undergraduate level, or after one has completed a university degree at the graduate-entry level.
For professional degrees that train students to become veterinarians, students can study veterinary medicine/veterinary science in Australia via any of the following:
Melbourne's Doctor of Veterinary Medicine (DVM) program is offered only to students who have already obtained an undergraduate Science degree.
Bachelor of Veterinary Science programs in Australia are suitable for students who wish to gain entry into a veterinary professional program directly from high school or after having completed undergraduate studies.
Canadian students have the option of applying to the Bachelor of Veterinary Science program directly from high school or after having completed Bachelor of Science courses or a degree.The following Australian universities offer Veterinary Medicine/Veterinary Science programs:
OzTREKK Admissions Officer: Shannon Tilston


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I once knew a man who lived to be 101. We had a bit of an unlikely friendship, since he had reached retirement age long before I was even born. He was smart, funny, and seems to have no concept of the age gap, reminding me that once his hip was better, he would take […]
Archive | February, 2012
Spinach Quiche In Red Pepper Cups
By Jackie on February 6, 2012 in Breakfast, Gluten Free, Healthy, Vegetarian
Baked Sweet Potato Chips With Cinnamon Caramel Dipping Sauce
By Jackie on February 3, 2012 in Gluten Free, Sides, Vegetarian, Veggies
I made these little chips the other day. The where so cute, slightly chewy and a little crunchy. And they are even healthy. Only about 7 calorie each. But, no one eats ONE, that's insane. So, think of it like 70 calories if you have 10, or 140 if you have 20. And it makes […]
Quinoa Carrot Cake Breakfast Muffins
By Jackie on February 1, 2012 in Bread, Breakfast, Healthy, Vegetarian
I'm a breakfast girl. It isn't possible for me to go the 16 hours between dinner and lunch the following day without eating. I become a crazy person when I'm hungry. Like the plant from Little Shop of Horrors yelling "FEED MEEE!!!" at random strangers. If I ever get stuck on a deserted island, or […]
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FPGA Simulation
A SystemVerilog Primer for VHDL Coders
Ray Salemi
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Version 1.0
June 22, 2009
© Ray Salemi, 2009
The debate between Verilog and VHDL has raged for twenty years, and as an AE for Mentor Graphics I still get questions about which is the better language. The answer to this question has become clear: both languages work for RTL design.
I say this because if there were a clear winner, the market would have shaken it out by now. But because both languages still exist for RTL design, one has to conclude that either can be used to design logic successfully. The same cannot be said in the world of verification. When it comes to writing test benches and simulating complex designs, the clear winner is SystemVerilog.
SystemVerilog is an extension of Verilog. It delivers features such as randomization, functional coverage, and assertions, which allow engineers to create powerful test benches.1 SystemVerilog allows users to create objects and implement object-oriented libraries. Object-oriented programming allows engineers to encapsulate complex behaviors in easy-to-use objects and reuse them. The Open Verification Methodology (OVM) is one such library.
SystemVerilog is an open language that is replacing the proprietary language e, which was the grand-daddy of all verification languages. Engineers learning how to do modern verification are learning how to write in SystemVerilog.
This primer teaches VHDL users about SystemVerilog in the terms of VHDL. People learn faster when they can anchor new concepts to existing concepts. It's easier to say that "a softball is like a baseball, only bigger," than to describe the specifications of a softball from scratch. Likewise, it's much easier for a VHDL engineer to learn SystemVerilog if the latter is described in terms of VHDL.
This primer is not a complete description of SystemVerilog. (The Language Reference Manual for SystemVerilog is over 1400 pages long.) Instead, it describes the basic features of SystemVerilog and provides enough SystemVerilog information so that a VHDL engineer could create test benches like those in FPGA Simulation: A Complete Step-by-Step Guide.
You'll probably have more questions about SystemVerilog after reading this primer than you had before reading it. The website www.fpgasimulation.com hosts forums where you can ask those questions and learn more about SystemVerilog. Also, members of the FPGA Simulation newsletter will receive new versions of this primer as I update it based on feedback.
1 A Matter of Philosophy
The biggest controversy between Verilog and VHDL has been a matter of philosophy. Specifically, how much should the compiler protect the programmer from stupid errors? VHDL represents one side of the argument. The VHDL (and ADA and Pascal) approach says that a language should capture as much of the designer's intent in the language's syntax and semantics. The VHDL philosophy requires designers to be very clear when describing the data in the design, as well as the way that data gets moved around.
Verilog represents the other side of the argument. The Verilog (and C and Perl) approach says that a language should make common assumptions about intent and that the designer is responsible for understanding those assumptions so that the code can be kept relatively sparse, or "terse."
Let's look at an example of these philosophies by implementing an adder in both languages and comparing the code. The adder looks like this in the Precision RTL synthesis tool from Mentor Graphics:
FIGURE 1. A Simple Adder
This adder takes two 8-bit inputs and adds them together on the positive edge of the clock. It produces an 8-bit sum and a carry bit. It is reset asynchronously when the reset is low.
Let's see how we implement this in VHDL and Verilog.
1.1 VHDL Adder
Here is the code for the VHDL Adder:
FIGURE 2. The VHDL Adder
This VHDL code demonstrates something important about VHDL: nothing is left to be handled by the simulator. Every aspect of this adder is clearly defined in the code.
First, the IEEE libraries we are using are clearly defined. You can look up their definitions and fully understand what the
std_logic_vectordata types do and how they work. You can even look up what the
&operators mean.
We can see another sign of clarity in VHDL when we look at lines 19-27. These lines handle the fact that we are taking two 8-bit operands and creating a 9-bit result. Line 27 does the actual summation, and
sum_intis a 9-bit number. This means we need to extend the 8-bit A and B inputs so their data can be used in a 9-bit addition.
Notice also that VHDL separates a component's interface (the entity) from its implementation (the architecture). This allows us to change architectures without changing the interface to the block. Finally, notice that we explicitly set the carry and sum outputs when the clock goes high. Let's compare this to a SystemVerilog module.
1.2 The SystemVerilog Adder
Here is the code for the SystemVerilog Adder:
FIGURE 3. SystemVerilog Adder
The first thing we notice about the SystemVerilog description is its terseness. Where the VHDL adder takes 39 lines, the SystemVerilog adder takes 14. This is because SystemVerilog assumes that the user is engaged in a specific task (describing hardware) and has shared assumptions about how the language works.
The first assumption is that there is no separation between the interface to the module and its implementation. The port list on lines 2-7 apply only to the code below. If we wanted a different implementation of the adder (for example, at the gate level), we would need to compile a different version of the adder.
The biggest difference between the descriptions is that SystemVerilog makes assumptions about the size of the values in this design and they way they are extended and truncated. The addition on line 13 uses the concatenation operators "{}" to create a 9-bit output. Then it adds two 8-bit numbers and places the result in the 9-bit output.
SystemVerilog relies upon the user to understand how the + operator works and whether it will create a 9-bit output. Of course, it works fine in this case, because that is exactly how addition works. If A and B were being multiplied, then the result would get truncated to fit in 9 bits.
This is the crux of the debate over using VHDL or Verilog for RTL design. VHDL designers are horrified by Verilog's cavalier attitude about its data types and how they are used. They don't like relying upon the simulator to "do the right thing." Instead, they want to see what's happening and control it.
The Verilog designers are horrified by the amount of code VHDL takes to do "simple" tasks. They want to use the fact that they understand the simulator's behavior in order to write shorter code that (they feel) does not obscure the design's "intent."
As we can see, this is mostly an argument over taste and personal preference. Both approaches obviously work. The one that appeals to you depends upon factors such as your upbringing, your personality type, and which language you learned first.
Now that we've seen the basic philosophical differences, let's look at the details of SystemVerilog, by using VHDL as a springboard.
2 SystemVerilog is Case Sensitive
It's worth giving a page to this fact. SystemVerilog is case sensitive, so
CLKis different from
All keywords must be in lower case.
Variables with different cases are different variables.
This is, of course, "opposite the case" with VHDL, which is case insensitive.
3 Processes and Sensitivity Lists
VHDL and SystemVerilog create threads to simulate simultaneous behavior. VHDL does this by using the
processblock. Verilog uses
alwaysblocks and
initialblocks. In both languages, the simulator launches the blocks in a random order at time zero.
3.1 A VHDL Process Block
For example, here is the primary process in the VHDL adder:
FIGURE 4. A VHDL Process Block
This process demonstrates the basics of VHDL processes. It does the following:
processblocks loop continually, we need to use a
waitstatement to force them to execute only once.
3.2 SystemVerilog
alwaysBlocks and
The first difference between Verilog and VHDL is that Verilog has two flavors of processes:
alwaysblocks use
endstatements to contain multiple statements. SystemVerilog allows you to put a single statement into a block without the
Here is the
alwaysblock from the SystemVerilog adder:
FIGURE 5. SystemVerilog
alwaysblock acts exactly like the VHDL one in Figure 4. It loops continuously and waits for the sensitivity list in order to start running. We'll discuss the sensitivity list in the next subsection.
The reader may notice that this example has a
beginon line 10 and an
endon line 15. Because the
ifstatement is considered a single statement, the
endwere not strictly necessary in this block; however, if you use them you will not run into syntax errors.
Like an
alwaysblock, an
initialblock starts at time zero, but the latter executes only once.2 Here is the
initialblock from the module that tests the adders:
FIGURE 6. SystemVerilog Initial Block
This block starts at time zero and sets the
rst_nsignals to
0along with the input data. Then it waits for the positive edge of the clock to arrive twice, raises the
rst_nsignal, and exits. Once it is finished, it is removed from the simulation. This is just like a VHDL process with an infinite
waitstatement at the end of it.
Lines 14 and 15 bring us to the issue of waiting and sensitivity lists. This is the topic of our next section.
4 Waiting for Time and Events
VHDL has a
waitstatement that we can use to wait for signals to achieve a value, or for a certain amount of time to pass. SystemVerilog also allows you to wait for things to happen. There are three types of delay in SystemVerilog:
All three of these approaches can control looping through an always block, or control execution in an initial block. We'll look at each in turn.
4.1 Time Delays
SystemVerilog uses the
#operator to specify time. Here is a simple example that creates a clock:
FIGURE 7. SystemVerilog Clock Generator
- Line 3-This
initialblock sets
clockto 0 at the beginning of the simulation.
- Line 7-This
alwaysblock waits 10 ns and then flips the value of
clock.3Then, because it's an
alwaysblock, it goes back to the top and waits another 10 ns before flipping the value of
- Line 8-This is the equivalent of the VHDL wait statement with a time argument.
This example demonstrates basic time control in SystemVerilog. There are additional controls that manage the simulation precision. Those are discussed at www.fpgasimulation.com.
4.2 Event Delays
SystemVerilog events take zero time to execute, as they just represent changes to a signal's value. Signals can change in two ways: they can go up, generating a positive edge event, or go down, generating a negative edge event.
We use the
@(<event>)construct to wait for events. Here is a piece of SystemVerilog code that demonstrates event delays:
FIGURE 8. Event Delays in SystemVerilog
- Lines 5-11-This code creates a clock that toggles every ten nanoseconds.
- Lines 13-16-This code will respond to every change on
clk, such as a VHDL process. (It has no sensitivity list, a topic we'll examine in a later section.)
- Line 14-This event delay responds to every change to
- Line 19-This event delay responds only to the positive edges of
- Line 24-This event delay responds only to the negative edges of
Event delays such as these can go anywhere in your procedural code. They are useful for creating monitors that watch busses and respond to protocol signals.
When we run the code we see the following:
FIGURE 9. Watching Events in SystemVerilog
We can see here that the
@(clk) alwaysblock triggers with every clock edge. The other two
alwaysblocks are limited to triggering on the positive or negative edge. Notice that we can't control which
alwaysblock will trigger first. In this example, the
negedgeblocks triggered first, but that might not always be the case with a different simulator or a different version of this simulator.
You can combine various events with the
orkeyword. This is the same as using a comma in a VHDL sensitivity list.
4.3 Boolean Condition Delays
The SystemVerilog
waitstatement is equivalent to the VHDL
wait untilstatement. The SystemVerilog
waitblocks execution until its argument is nonzero, and then continues. SystemVerilog does not strongly separate boolean operations from conditional operations. Consequently, you can use any statement in the test as long as it returns a zero or nonzero value. For example:
FIGURE 10. Waiting for a
- Lines 5-11-This code sets
10and then counts
xdown to
0, decrementing on each nanosecond.
- Line 14-This line waits until the expression
!xreturns a
1. The exclamation point (called a "bang") reverses the logical sense of the variable. So if
xis zero then bang-
!x) is nonzero, and
!xwill return a true value once
When we run the code it looks like this:
FIGURE 11. Waiting for
xto reach
Now that we've studied the different ways to wait in SystemVerilog, we can look at sensitivity lists.
5 Sensitivity Lists in SystemVerilog
SystemVerilog and VHDL have similar ways of handling sensitivity lists, but with one big difference. VHDL sensitivity lists respond to every change on their signals, and then the programmer uses
ifstatements to sort out the clock edge. SystemVerilog sensitivity lists can limit their responses to a particular edge. Here is a simple D flip-flop in both VHDL and Verilog:
FIGURE 12. Figure 12: Sensitivity Models in SystemVerilog and VHDL
Both of these models create the same design, a simple D flip-flop. Each model has a process that has two signals in the sensitivity list.
The first thing to notice is that SystemVerilog
initialblocks allow you to place a sensitivity list right after the
initialkeyword. In fact, an
alwaysblock with no delay or sensitivity list will hang the simulator, as it causes it to spin infinitely.
The VHDL design has a process with
rston the sensitivity list. This means that this process will suspend until
rstchanges. Then the process will use
ifstatements to check whether the
rstis low or
clkhas just risen.
The SystemVerilog sensitivity list works differently. It uses the edge of the clock as part of the sensitivity. Consequently, it will start running only at the positive edge of
clkor the negative edge of
rst. It still needs to check whether
rstlow; however, after that it can assume that
clkhas just risen, because of the
This additional qualification on the sensitivity list is the primary difference between VHDL and SystemVerilog. Notice also that SystemVerilog uses the
orkeyword to create a list of events on a sensitivity list, whereas VHDL uses a comma.
6 SystemVerilog Data Values
Now that we can create processes in SystemVerilog, we are ready to talk about data types. Here too, SystemVerilog and VHDL have very different philosophies.
VHDL was written to allow future users to create a wide variety of descriptions. Therefore, it allows its users to define anything they want as data types. You could have a data type in VHDL with values such as "red" and "yellow." You could even create a "+" operator for these values, so that
is a legal statement, and
colorcan take on the value of
This means that if you want to use VHDL for hardware design, you need to create a set of data types that describe hardware. Fortunately, because it would be bad for each developer to create a different set of values, the IEEE stepped in and created
std_logic_vector, and all the other libraries.4
As with most things, SystemVerilog took a different approach. SystemVerilog assumes that you are designing or describing hardware, so it has built in four data values that can be used for hardware design:
(Notice that there are no quotes around these numbers.)
All SystemVerilog values are a combination of these values on a bit-wise basis. SystemVerilog converts every integer to a set of these values.
6.1 Multi-Bit Values
VHDL has
std_logicfor single-bit values and
std_logic_vectorfor multi-bit values, where a single-bit value looks like
'0'and a multi-bit value looks like
"00000000". (Both of these values are assumed to be in a binary radix.)
SystemVerilog allows you to combine the radix, the width, and the value into a single string. Constants in SystemVerilog look like this:
<width>-The number of bits in the number. If you ignore this width, then the number indicates the width.
<radix>-This can be
o, or
hfor binary, decimal, octal, or hexadecimal. It could also be
H, because this is a rare case where SystemVerilog is case insensitive. If you don't specify the width or the radix, the simulator assumes that the number is a 32-bit decimal.
<number>-This is a string of numbers in the radix just selected.
Here are some examples of legal SystemVerilog numbers:
TABLE 1-1. SystemVerilog Values String Interpretation
32-bit hexadecimal number
24-bit hexadecimal number
Same as `d48. A decimal integer, 32-bits wide.
Illegal. Numbers with no radix designator must be decimal.
One hundred and one in decimal
A 3-bit binary number representing the value 5.
"00011000" as a VHDL
`1' in VHDL
This is a 32-bit value with 31 zeros and a single bit set. You can put it into a single-bit value, as we'll see below, so it acts like `1'.
An 8-bit octal number (8'b1001_1010). Notice that the underscore is legal in a number in SystemVerilog
Illegal1 binary value.
Binary number with one bit unknown. 16'hZZZZ Driving high-impedance to a 16-bit bus.
Notice that unlike
std_logic_vector, or
std_logic, these numbers are not strings of bits. There is no need to encase them in quotes, because they are just numbers in the program.
Of course, you can't just write programs with numbers. You need variables, and that brings us to the SystemVerilog data types.
7 SystemVerilog Data Types
Creating hardware, or programs that interact with hardware, requires a four-state data model. You need to be able to handle the values
X, and
Z. VHDL implements this with the IEEE data types such as
std_logic_vector. SystemVerilog inherently delivers these data types, so there is no need for additional libraries.
There are two basic kinds of data types. There are 2-state types that can only hold
0s and
1s, and there are four-state types that can hold
Xs, and
7.1 4-State Data Types
The 4-state data types are similar to the data types you'd use for a VHDL signal, usually a
std_logic_vectortype. There are four of these types:
reg-These data types are identical. The
regtype is a holdover from Verilog, but the developers of SystemVerilog felt that it implied the creation of a register where there really didn't need to be one, so they created a synonym called
logic. If you don't declare a width for these data types, they are assumed to be one bit wide.
integer-By default an integer is assumed to be 32-bits wide. It can be longer if you are simulating on a computer with a wider data word. This type is different than the
intdata type which is a 2-state type.
time-This is a 64-bit variable. It is called "time" because you can store the simulation time in it.
Most designs you see will use the
regdata types to store data in procedural SystemVerilog.
7.1.1 4-State Data Types
integer, and
timedata types can store values in procedural code within
alwaysblocks. The bits in these data types can take on the values
X, and
logic, and
regdata types can also be used to connect modules. Variables that connect modules vary their value based on how they are driven from their module blocks. These types take on the value of
Xif they are not driven.
If two or more modules drive the same signal, then the simulator figures out the value. In the default case of logic, reg, or wire the following table applies:TABLE 1-2.Default Conflict Resolution in SystemVerilog
The default conflict in SystemVerilog acts as you would expect a wire to act. SystemVerilog has other resolution behaviors that you can control with different wire types such as
wor, and
wand, and with different drive strengths. But these are beyond the scope of this primer.
7.1.2 2-State Data Types
The 4-state data types can handle the unknown values of X and Z, but they take more memory and run more slowly than 2-state data types. The 2-state data types can only handle 1 and 0, but they need fewer resources, so some people prefer to use them if it isn't necessary to handle unknowns.
The 2-state data types can be further broken down in integral data types and floating-point data types. Here are the integral data types:
7.1.3 Signed and Unsigned
By default, all the 2-state variables (except
bit) are signed. So a byte variable set to
8'b11111111is equal to -1, not 255. A signed 8-bit variable can take the values of -127 to 128, while an unsigned 8-bit value can take the values from 0 to 255.
We change our signed variables into unsigned variables with the
unsignedkeyword, like this:
FIGURE 13. Defining a Variable as Unsigned
This code gives the following result when we run it:
FIGURE 14. Results of
7.2 Defining Data Widths and Depths
reg) data types are one bit wide by default. Of course, there are very few one-bit registers in a design, and we have memories, so we need to be able to define width and depth when we define data.
As an example let's define a register and a memory:FIGURE 15. Declaring Registers and Memories in VHDL
- Line 20-We define halfbyte to be a
std_logic_vectorwith four bits with the MSB at 3 and the LSB at 0.
- Line 22-VHDL uses a type to create an array. Each word in this array starts at bit 1 and goes up to bit 8. Then the array elements are numbered from 7 at the top word down to 0.
- Line 24-Declare a signal of the array type.
This little example shows how VHDL declares registers and arrays. Here's how SystemVerilog declares the same register and memory:
FIGURE 16. Declaring Registers and Memories in SystemVerilog
- Line 3-When we create a register in SystemVerilog, we put the bit addresses immediately after the type name in square brackets. Then every variable declared on this line has the same width. Notice also that SystemVerilog has no
downtokeywords. You use the colon for both directions5.
- Line 5-You declare an array in SystemVerilog by placing the bounds of the array after the variable name within square brackets. You can declare the width of the variable's data word, and the depth of the array in the same line. Notice again, the colon serves double duty.
You access the data bits and the memory words in SystemVerilog using the square brackets as indices. In this example we will load up the memory and assign four bits of it to our register:
FIGURE 17. Bit Select Example
- Lines 10-11-We initialize the memory by storing the address in each memory location. Notice that we did not need
endbecause there is only one statement in this loop.
- Line 13-We select four bits of the memory and place them into half byte. These are the bottom four bits of memory location 6. Notice that we use the square brackets to access the bits. Also notice that when we have multiple indices that we access the memory location first and then the bits.
- Lines 15-18-Display the information.
Here is what happens when we run this example:
FIGURE 18. Bit Select in Action
8 Variable Assignments
Now it's time to take these variables and start moving them around in programs. While both VHDL and Verilog have similar assignment approaches, their philosophy around legal assignments, and what the simulator will do for you, are worlds apart. In this section we'll discuss three topics:
We'll start by talking about type conversion, because this affects all other assignments.
8.1 Type Conversion and Width Management
SystemVerilog was designed to create hardware, and so the simulator automatically implements type conversion and width management policies that match the needs of hardware developers. This is disconcerting to VHDL writers, because a lot of what happens in a SystemVerilog program consists of hidden magic, whereas VHDL requires developers to define the conversions explicitly.
This discussion focuses on the integral data types. Engineers use these types to describe logic or create test benches. Because all these data types describe strings of bits, SystemVerilog simply allows you to assign them to each other. There is no need to explicitly cast an
intto a
reg, for example. SystemVerilog simply "does the right thing" here by moving the bits over.
8.1.1 Boolean Operations and Conditionals
SystemVerilog has no explicit boolean data type. Instead, all conditionals follow the same rule:FIGURE 19. Boolean Conversions in Action
This snippet of code is part of a cache's state machine. The cache checks for two signals:
Neither of these signals was declared as a boolean; in fact, they are both wire types. SystemVerilog treats these signals as boolean operators in this context; they are true if they are nonzero.
In VHDL we would have explicitly written
(cpu_wr='1')to implement the same behavior.
8.1.2 Width Conversion
SystemVerilog allows you to make assignments where the number of bits on the right-hand side (RHS) of the assignment is different from the number of bits on the left-hand side (LHS) of the assignment. The simulator automatically manages the width differences by following these rules:
- If the LHS is shorter than the RHS, then SystemVerilog truncates the larger value by getting rid of the most significant bits.
- If the LHS is wider than the RHS, then SystemVerilog copies the most significant bit of the RHS into the extra space, unless the RHS is unsigned. In that case, SystemVerilog puts zero into the extra space.
This automatic width management can create some surprises for the programmer. For example, if you try to put the constant
4'h8into a 3-bit value, you'll get
3'h0instead, because the top bit will be cut off.
Here is an example from the book FPGA Simulation: A Complete Step-by-Step Guide that demonstrates truncation and extension:
FIGURE 20. Truncation and Extension
- Line 18-The variable
reg8is an 8-bit 4-state variable.
- Line 19-
reg64_zeroare 64-bit variables.
- Line 20-The variables
i, and
seedare 32-bit variables.
- Line 26-The system call
$randomreturns 32 random bits. These go into
- Line 27-
reg8gets the bottom 8 bits of
- Line 28-
reg64_extgets the 32-bits from
my_random. SystemVerilog sign-extends the MSB in
my_randombecause an integer is a signed data type.
- Line 29-The {}'s implement a trick. They concatenate
my_randomwith nothing, but because concatenation returns an unsigned value, SystemVerilog will not sign-extend the MSB in
- Lines 31-35-Display our values. Notice the C-like formatting in
When we run this example we get the following results:
FIGURE 21. Truncation and Extension in Action
- Line 21-We generate a random set of 32 bits. In this case the most-significant bit is set, so the signed view of the number is negative.
- Line 22-The hex view shows the MSB set.
- Line 23-Assigned the 32-bit number to an 8-bit variable, so the top 24 bits are gone.
- Line 24-Assigned the 32-bit signed number to a 64-bit variable, so the top bit was extended.
- Line 25-We used the concatenation trick to convert the signed number to an unsigned number. Then we assigned a 32-bit unsigned number to a 64-bit number and see zeros in the top 32 bits.
- Lines27-31-We did the same things with a different random number, but in this case the most significant bit was zero.
The biggest difference between SystemVerilog and VHDL in the area of assignments is that Verilog tries to do the right thing (and usually succeeds) when you assign data, and VHDL makes you connect all the dots syntactically.
8.2 Concurrent Assignments
Both VHDL and SystemVerilog allow you to define expressions that the simulator evaluates continuously. We call these concurrent assignments in VHDL, and we call them continuous assignments in SystemVerilog. SystemVerilog uses the
assignkeyword to define continuous assignments.
For example, here is a MUX defined in VHDL with a concurrent assignment:
FIGURE 22. VHDL MUX with Concurrent Assignment
We see that the architecture consists only of the concurrent assignment. We use the conditional assignment to implement the MUX functionality.
Here is the same design in SystemVerilog:
FIGURE 23. SystemVerilog MUX with Continuous Assignment
We can see Verilog's C heritage in the conditional assignment operator. This continuous assignment, with the
assignkeyword, is just like the concurrent assignment in VHDL.
8.3 Blocking and Nonblocking Procedural Assignments
Both VHDL and Verilog allow you to create assignments that either (1) happen all together in the same clock edge, to simulate assigning values to a register (nonblocking); or (2) happen sequentially, to implement an algorithm (blocking).
Both languages use the
<=operator to indicate a nonblocking assignment. The difference is that SystemVerilog can use any type for nonblocking assignments, whereas VHDL requires that you use the
variabletype for nonblocking assignments.
Here is an example of a multiply/ADD circuit with blocking and nonblocking assignments in VHDL:
FIGURE 24. Multiply Add with VHDL
- Lines 23-25-We declare variables to use in our blocking assignment. We have a signal (
mulsum) for the nonblocking assignment.
- Line 31-33-These are blocking assignments in VHDL. We know that
cdget calculated before they are added to create
- Line 41-This is a nonblocking assignment. It happens right at the clock edge and then moves on. If there were multiple nonblocking assignments, they would all happen right at the clock edge in no guaranteed order. We declared
mulsumto be a signal in the entity for our multiply add block.
This VHDL design demonstrated both blocking and nonblocking assignments. We used blocking assignments, implemented with the
:=operator, in a combinatorial process to create the multiply/add value. Then we used nonblocking assignments, implemented with the
<=operator, in a clocked process to assign the value to a register. This is a good coding style that avoids race conditions.
Now let's implement the same code in SystemVerilog:
FIGURE 25. Multiply/Add in SystemVerilog
- Lines 2-4-The inputs are all implied to be wires and the output is declared to be
logic. The types have nothing to do with whether the variables are used in blocking or nonblocking assignments.
- Line 7-We've declared the intermediate values to be 17-bit
logicvariables. This allows us to handle the maximum result size easily. Notice that there is no distinction between
variablein SystemVerilog. Both can do blocking and nonblocking assignments.
- Lines 9-13-This combinatorial
alwaysblock has blocking assignments, implemented with the
=operator. You should always use blocking assignments when implementing combinatorial logic.
- Lines 16-20-This clocked block either resets the output register or sets it equal to the result of the combinatorial logic. It uses a single nonblocking assignment by means of the
In this section we learned how to implement blocking and nonblocking behavior in SystemVerilog. We saw that SystemVerilog controls this behavior entirely through the operators
=(blocking) and
Now we'll put all this information together in a test bench example.
9 Example Test Bench
As we've discussed, SystemVerilog is a new language targeted at creating test benches. In this primer, we saw how SystemVerilog works by using the concepts from VHDL. We'll now put those concepts together in an sample test bench. We are going to test our multiplier from Chapter 8. You can find this code in the folder
We will create a test bench that ensures that the VHDL and SystemVerilog multipliers give the same results, and that those results are correct. You could use a similar test bench to check whether your Verilog gate-level simulation gives the same results as your VHDL RTL.6
This test bench demonstrates two features of advanced test benches, even though it is relatively simple. It generates its own stimulus, and it checks its own results.
FIGURE 26. SystemVerilog Test Bench for Multiply/Add
- Line 3-We will use these variables to create inputs randomly. We use lowercase here to conform with variable names in VHDL.
- Line 4-Here we see how
logiccan be used both in procedural code (in a process) or as a wire. The variables
sv_outwill act as wires, while
predictedwill be calculated procedurally.
- Line 5-Our test bench needs to generate the reset and the clock.
- Line 7-We instantiate the VHDL version of the DUT. Notice that SystemVerilog allows you to declare the port and signal connection in instantiation. The connection
.mulsum(sv_out)is the same as
mulsum=>sv_outin VHDL.
- Line 8-We instantiate the SystemVerilog DUT. Notice this trick in SystemVerilog. If you use the wildcard expression
.*, then the simulator will find ports in the component that have the same name as variables in this level and hook them up. As you can see in Figure 25 on page 28, the multiplier has ports named
clk, and
rst. These match the ports in the test bench. We had to connect the port
- Line 10-This
initialblock lives up to its name. It initializes the test bench.
- Line 11-The
$monitorsystem call prints to the screen any time on of its inputs changes. In this case we are printing all the inputs and outputs from the blocks.
- Line 13-Set the
0to start the simulation.
- Line 14-Set the
0to start the simulation.
- Lines 15 and 16-Wait for a clock and a half before raising the reset.
- Line 20-This block generates the clock. It waits 10 ns before inverting the
clksignal. Because the
initialblock set
0at time
0, this block will create the first positive edge of
clkat time
10. This is the positive edge that the
initialblock sees on line 15.
- Line 22-This
initialblock implements the test.
- Lines 23 and 24-Wait for a couple of clocks for the reset to take effect.
- Line 25-We will execute 10 tests. The
repeatloop is the simplest looping tool in SystemVerilog. SystemVerilog also has
forloops and
whileloops. You can also say
forever, but we don't want that here.
- Line 26-We will change the input data to the DUT on the negative edge of the clock.
- Lines 27-30-The
$randomsystem call returns a 32-bit string of random bits. The simulator truncates these to fit
c, and
d. It would have been fancier to say
{a,b,c,d} = $random, because the operands are each a byte wide and there are four of them, making 32 bits-but that would just be showing off. This approach is much clearer.
- Line 31-We calculate the expected result.
- Line 32-Wait for the positive edge of the clock so that the DUTs calculate the value.
- Line 33-Wait for 1 ns to avoid a race condition between the result being generated and checked.
- Line 34-The
assertstatement will fire if the condition inside is not true. The expression says that both the VHDL and SystemVerilog DUT outputs must match the predicted value.
- Line 35-The
$stopsystem call stops the simulation but does not quit out of the simulator. You want
$finishfor that.
When we run the simulation we get the following result:
FIGURE 27. Results of Multiply/Add Test Bench
You can see the
$monitorstatement in action here. It prints twice for each test value, once when the inputs change, and again when the outputs change.
$monitoralways runs at the end of a time step. Notice that the prediction happens in the same timestep in which the inputs change, and then the outputs follow the prediction.
10 Why Learn SystemVerilog?
This primer has covered the basic structure of SystemVerilog in the context of VHDL. While it is far from a complete description of SystemVerilog (the SystemVerilog Language Reference Manual is over 1400 pages long), it does give you enough to get started with SystemVerilog. It also brings us to the question of why you should bother to learn SystemVerilog.
SystemVerilog is worth learning because the industry, that amorphous group of all of us that makes a bandwagon, has decided it is the future of RTL verification. While VHDL can do many of the things that are possible in SystemVerilog (though not some crucial ones such as covergroups), VHDL does not have the industry behind it, and so VHDL does not have free class libraries designed to support RTL verification.
While different EDA companies tout different class libraries (Synopsys supports the VMM, while Cadence and Mentor support the OVM), all three companies support SystemVerilog as their language of choice for verification.
This means that verification libraries and verification IP will soon appear exclusively in SystemVerilog. This is already happening. The Open Verification Library (OVL), which supplies assertions to engineers, has 50 assertions written in SystemVerilog but only eight that are written in VHDL. This trend continues in other areas. This industry support makes it well worth learning SystemVerilog.
I hope that this primer has helped you get started down the path to learning SystemVerilog. If you have any questions about the topics in this primer, please post them at www.fpgasimulation.com/forums. I will answer them there, and use them to create future versions of this primer. I'll notify you of updates on the FPGA Simulation email newsletter.
11 Revisions
TABLE 1-3. SystemVerilog Primer Revisions Revision Changes 0.1 Beta Test release. 0.2 Revisions from Michael Meyer 1.0 Initial release
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text:
The writer describes the days when he began his working career—the pitfalls, the challenges and successes. These last two chapters form the epilogue describes the unknown triumphs and travails of doing international business
An initial overseas assignment for three years became extended to almost four decades due to the circumstances and exciting opportunities that came about. A few were responsible in creating the opportunity; some caused it to happen and I took them as an acceptable challenge to overcome my many drawbacks.
Though I was 'born' in Calcutta, I was 'delivered' in a small village in Tamil Nadu. When I was about four, my parents decided to send me to the loving care of grandparents in the tobacco town of Dindigul. My grandfather (late) Kachapeswara Iyer was a lawyer who worshipped his work and never lost a case because he could distinguish between the good and the bad. As a teen I returned to Calcutta to continue my studies, where my father worked in "Indian Finance", a reputed commercial and financial weekly run by late CS Rangaswami, my uncle, who owned the weekly, and we lived in a huge house on Lower Circular Road.
It was during this time, I had the chance to hear the predictions of a "well-known and reputed" astrologer, who declared that I would have a hand-to-mouth existence. This shook me, and I took refuge in the terrace of a palatial building owned by my uncle as cried my heart out. In the end, I made a deal with God asking him to bless me so that I can at least feed one other person everyday in my life, and that I was ready and willing to do any work that I was assigned.
Oh, yes, he predicted that I would fail in the matriculation examination that I was about to write a few days hence. In fact, just before that, a close family friend and a champion swimmer, Dharmarajan drowned in the Calcutta Lakes in Ballygunge. This shook me too, but when I failed in the examination, it tore me apart.
My father was angry and upset. He swore he was not going to pay any further for my education and told me to earn so that I could continue my studies, if I wanted to. However, he was kind enough to get me a typewriter and taught me...
A quick brown fox jumped over a lazy dog...
I struggled, did odd jobs, including a brief work at the Indian Finance and worked for some two years in the Punjab National Bank in the district manager's office, under the Gandhian, Khadi-clad Kashi Prasad Mishra, a loan officer. Everything was fine until the day I was asked to arrange for a farewell party for Sitaram Mohindroo, the DM, who was on a TCM scholarship to US to study the banking procedures there.
All that I had asked my colleagues was to "come well dressed", and in those days, in the late 1950s, wearing a tie was chic! Mr Mishra blew his head off, and chided me for wearing the tie, calling it a sign of British slavery and taunted saying "your grandfather never wore this". I took an exception to this attack, complained to the DM, made and got an apology and told him that I would never work under him from the next year!
In the next few weeks, I was on a job hunt, and armed with a letter that my father (late) Ananathanaryanan typed for me, I walked into Dunlops seeking a job. I did not have a good reception, but managed to go to the office of the operations manager. Mrs Spencer was kind enough to pass on my visitor's slip to the boss, who forgot all about me, until he walked past me just before lunch. He turned back, apologized for his lapse, and asked me to come back at 2pm!
When he did, he took me along to his office and asked for my application. I had one in hand, but offered to fill up the company's standard form if given. I was sent to Prem Pandhi, manager, imports and exports for an interview. It was brief but Mr Pandhi wanted someone who knew everything about exports, as the department was commencing operations in a big way. It was just couple of days before Christmas; so I requested that I be given time to come equipped and join duty on 2nd January and promised to give him all the info he would need. He phoned to say "Bill, I think I have the man I need". He was addressing to William Sherrat. I had suggested to Prem Pandhi that if I did not know answers to his questions on 2nd January, he could send me home. I think that kind of a confidence got me the job.
In the next few days, I found out that Capexil (Chemicals & Allied Products Export Promotion Council) handled tyres and tubes while Engineering Export Promotion Council (EEPC) covered steel rims. Here is where my association with both the organizations began.
Prem Pandhi was my first guru in management techniques. I learnt not to decline any work by giving excuses; if I did not know a job, I learnt from him that I would seek the answers and talk to others to know. I never left any job for the next day, regardless of the time, whether it was paper work or typing of import license application forms. I had wonderful colleagues like (Mrs) Phil Henderson, (late) Promod Ganguli and Ram Mohan Sinha. We were a fantastic team who were assisted by BK Dey an accurate typist, the most silent person I knew.
Zinc oxide is an item that is used while preparing the rubber mixes for tyres before they go into the moulding machines. Dunlops, like all other tyre manufacturers, had to import zinc metal, which was given to converters like Binani Metals who would process and return the zinc oxide to us. Our exports were picking up, and related imports, under "export promotion licenses" were my responsibility. These would be processed by Capexil or EEPC and I had established good rapport with all officers of the councils as well as the joint chief controller imports & exports in Calcutta. In a likewise manner, establishing drawback of duty, though a very long and cumbersome process, was part of the scene, involving factory visits, submission of statements, customs and central excise, etc. Prem Pandhi would give the job, and ask me to study and get it done; "ask me for any assistance you need" was his friendly approach. He was patient to hear and clear in his advice.
Now when the application for zinc import license was "approved" some smart Alec decided and reduced our import value by 14% all because, when zinc metal was converted, it would produce 14% more of zinc oxide! I had taken up the issue with (late) K Rajagopalan (DGTD) and presented my case, asking the government to give me the full value of export entitlement and, if, in the process of conversion, we received more zinc oxide, which would enable us to manufacture and export more tyres/tubes, this would be indirect incentive, and that it should not be reduced. I won the case, much to the delight of my immediate boss, and others like Moni Mohan Sabherwal and Madhav Lal Capoor, besides the top management.
Encouraged by Prem Pandhi's approach, against the normal permission of using 10% of the import entitlement to use for machinery imports, using similar arguments, I was able to get an ICT data processing machine for our factory, much to the satisfaction of PK Mukherjee our asst works accountant, by utilising 100% entitlement license. But all these good work came to an end when Prem Pandhi's recommendation to the board for making me a "special assistant" (meaning an officer grade) was not accepted. He resigned on the spot; which I came to know some thirty minutes later, and I followed suit, with no job on hand.
Without my idol, I did not cherish the idea of working in Dunlops. Couple of days later, Prem Pandhi offered me a job in the Calcutta Management Association, in which he was closely associated, mentioning to others that "Ramdas has the latent talent that needs to be moulded".
My 'understudy' assignment with CMA lasted for nine months. As I was about to complete this, I began looking for suitable openings, specifically related to export, as I responded to the call that our PM Jawaharlal Nehru had made: "Export or Perish".
After a long and tough interview, I joined the Indian Cables, a subsidiary Indian arm of BICC (British Insulated Callenders Cables of UK, the world's oldest and largest company, at that time). I was one of the three management trainees and reported to Jan Manekshaw (brother of late Field Marshal Sam Manekshaw, who was, at that time GOC at Fort William, Calcutta). My immediate boss was Kishan Kapoor, general sales manager, who was aided by Adi Dalal, a brilliant young man, who passed away very early in life.
After a few months of training, which included three weeks at Jamshedpur, we returned back. My contacts with the EEPC staff were regular and every import enquiry was promptly attended to. Small and regular orders started coming in, and, we took the orders from agents like CIEL (Commercial and Industrial Exports, which had some Tatas association).
Later on, when we started getting enquiries from VD Swami & Co Private Ltd, Bharat Exports and few others, we began to make some headway.
As I regularly attended the various panel meetings of the EEPC and began to take part in workshops, etc, some senior exporters began to notice my activities, resulting in Dr RK
Singh, secretary (at that time, who later became executive director) getting me involved in various committees.
Back in the office, at the Indian Cable, soon after I joined the company, we lost Pillu Shavaksha, our MD. I think he was succeeded by Dr William James John Curry, who came from UK; Arun Basak, a brilliant chartered accountant, who was formerly with Indian Oxygen was already on board; Ronnie Bowyer at the works, aided by Dr A P Sabherwal and S Ganapathy.
Our office timings were 9.30 to 5.15 but I was always the first to come by 8.30 in the morning and the last to go. From time to time, Jan Manekshaw would give special jobs some of which related to the Non-Ferrous Metals Association and I would complete them to his satisfaction. Likewise, when we had some small licensing problems, he would seek my assistance.
In the meantime, our overseas sister companies, all independent operators, began to send their urgent requirements, which came from Malaysia and from Singapore a great number of tenders for their expansion. Our orders began to flow, once we supplied our first lot to a company called Boon Liew. Malayan Cables from Petaling Jaya also placed regular orders.
It was around this time a major upheaval took place, as our rod mill broke down. Apart from the company's own requirements, this mill processed many other companies' needs by converting their bars for further processing. This was a well-kept secret.
I was therefore totally surprised when one morning I found the whole bunch of directors in the lobby seriously discussing something. It was about 8.30 or so, I wished them, as I passed by towards my office. It was Jan Manekshaw who called out: "Ramdas come here. We need a license urgently. Can you get one?" Spontaneously, I replied, "No problem sir" and waited for him to go on. And it was Kish Kapoor who responded, saying "Do you know what we are talking about?" "I have no idea except we need a license."
From the beginning he was not friendly or accommodative and I felt reserved in dealing with him. My efforts to know him were in vain and he was always 'official' in dealing with me. There was no warmth, which was the basis of my relationship with Jan Manekshaw and many others. He continued: "Suppose you cannot?" For me, it was a do or die situation. "Mr Kapoor, if I can not get a license in India, no one else can, that I promise you; but I won't fail." There was absolute silence until Dr Curry announced: "Jan give this job to Ram Dash... I think he will deliver the goods". Saying this, he walked away; the crowd dispersed.
Co-ordinating with Jan Manekshaw, I was able to get the relevant details from Alex Fernie, the purchase manager. Using my contacts with Rajagopalan, Mondal and PC Sen, the joint chief controller of imports & exports in Calcutta, I obtained the license in a record 48 hours, much to the chagrin of Kish Kapoor.
This episode was followed by many relating to dealing with government departments. And at every stage of work matters I depended upon Jan Manekshaw, who became another idol and guru for me.
While writing all this, I forgot to mention that ever since my working career began, I began to read all sorts of success-related books. Everyone reads Dale Carnegie's "How to Win Friends and Influence People". I did too; but, to me, it was Dr Napolean Hill, who authored "Think and Grow Rich" which changed my outlook towards life. Not only did I read this book every time I could lay my hands on it, but the entire series written by him. This is one author whose books should be used as a reading and practicing material for all our students.
Our exports began to grow; while indigenous sales brought profits for the company, exports brought both name and profits. Everything was going fine, until, 6 June 19766, Sachin Chowdhry, our finance minister, devalued the Indian rupee by 57.4% sending shock waves in the country.
We shall discuss the impact and changes that happened thereafter in my concluding chapter...
(AK Ramdas has worked with the Engineering Export Promotion Council of the ministry of commerce and was associated with various committees of the Council. His international career took him to places like Beirut, Kuwait and Dubai at a time when these were small trading outposts; and later to the US. He can be contacted at [email protected])
During the April-June quarter, exports shrunk 1.7% to $75.2 billion while imports also dipped 6.1% to $115.26 billion from same period last year
New Delhi: India's exports contracted by 5.45%, year-on-year basis, to $25.07 billion in June due to the persisting global economic slowdown, reports PTI.
Imports also declined by 13.46% to $35.37 billion, leaving a trade deficit of $10.3 billion, according to the Director General of Foreign Trade A Pujari.
Meanwhile, Commerce Secretary SR Rao told reporters that, "Exports have contracted but trade deficit is also coming down."
During the April-June quarter of this fiscal exports have shrunk 1.7% to $75.2 billion over the first quarter of 2011-12. Imports have also dipped by 6.1% during the first quarter of 2012-13 to $115.26 billion.
Trade deficit in Q1 has declined to $40.06 billion, from $46.30 billion in April-June last fiscal.
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