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Today Nicole and Sophie take us on a road trip to the Yarra Valley for a day out at Medhurst Winery. After reading what the girls from Cookes Food had to say about this wonderful winery, I can't wait to take a weekend trip out there myself! Until then, I'll be happy to have a nice big glass of Medhurst wine with dinner tonight :) – Jenny x
It's probably important to mention that Nic and I are extremely partial to a glass of nice wine. We are not wine experts by any stretch of the imagination, we do however get to know the wines we use and have developed a small wine list based solely on wineries that we have been to and developed a relationship with. Medhurst is one of these! We met the owners of Medhurst, Ross and Robyn Wilson, when we catered Ross's son's engagement party in the Yarra Valley many moons ago. He happily took us for a wonder around the winery, introduced us to Matt Steele, the winemaker, and we tasted the wines while looking out the window of their chic cellar door. For Nic and I it was a special experience and we have since done tours of their new development including a very cool wine cellar, filled to the brim with barrels of wine.
Top right – Medhurst owner Ross Wilson, bottom left – Medhurst wine maker Matt Steele
Both Ross and Matt are extremely passionate about what they do and can both become quite animated when talking about the weather's effect on the grapes etc. From the initial tour of the winery we met Franwa, Ross's daughter who ran the cracking Red Shed Café, now closed and replaced by the Medhurst Cellar door which serves simple and delicious paddles of antipasto and ploughman's specialties (Nic's absolute favorite way to eat!).
To our delight, last year Medhurst introduced my favourite dessert wine, the Frances, named after their lovely Frances "Franwa" Wilson. The best part of our business is the stories and relationships we have created over the past 5 years.
Medhurst Winery
24 – 26 Medhurst Road
Gruyere, Yarra Valley, VIC 3770
(03) 5964 9022


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Join Date: Jun 2006
Location: Joliet
Posts: 383
Gamertag: rdrunr89
Sticky: Achievement Guide and Roadmap
Thanks to ronron1 and Lavindather for their help.
Overview: An all-time arcade favorites gets a second helping as BurgerTime World Tour elevates classic gaming to the next-gen universe. Hero Peter Pepper returns and traverses the globe challenging chefs from around the world. Gamers will tackle 50 total levels and boss fights in each of the four environments. For the first time ever, the game will also feature online and split-screen multiplayer modes for four players with online leaderboard and avatar support. BurgerTime has never been more meaty! (xbox.com)
-Estimated achievement difficulty: 8/10
-Offline: 10 (160)
-Online: 2 (40)
-Approximate amount of time to 200: 15-20 Hours (Skill dependent)
-Minimum number of playthroughs needed: 2 (1 for 5 stars - Skill dependent and then 1 for Online achievements if you play with 2 players immediately and win)
-Number of misable achievements: None
-Glitched achievements: None
-Do cheat codes disable achievements?: No Cheats
Step #1: Normal Playthrough
I gave this a 8/10 on the difficulty because of how hard it is to get the 5 star achievement along with not dying on any level.
There are 2 ways to play through this game, Easy and Normal modes. You can complete all the worlds on Easy mode, however, the scores and stars will not post to the leaderboard, so you don't get credit for the 3* and 5* achievements. Normal mode will post your scores to the leaderboard and is the only way to get the 3* and 5* achievements.
There are Power ups like Spatulas, Rockets, Soda cans.
Step #2: Online play:
There are two achievements for online: Master Chef and Dirty Burger. Use the Achievement Trading Thread to boost. For Dirty Burger, you will need 2 other players.
Clean Up:
Once you complete the levels and depending on your skill, you may need to go through and get 5 stars on the levels you haven't completed.
* If you aren't sure or are having trouble, play the game on Easy Mode. You get more Power Ups and less guys to avoid.
* Grab a Soda Can when possible as this boosts your speed for a bit and make you temporary invincible. Careful because it can make your character harder to control.
* The more guys on your burger part at one time, the further it will drop (2=2x, 3=3x). This will also help with bonus points as well as collecting the B-U-R-G-E-R letters.
American Cheese 10
Complete All USA BurgerTime World Tour Levels
This can be done by completing all 10 levels on the USA map. This is the first map that you will do followed by Mexico, France and Japan. There are 9 levels to do then the last level is the Boss challenge. Basically you need to make X amount of burgers per level. (Tip: Use your Pepper (X) and stun a guy on the part of the burger, it will drop 2 rather than 1)
Luchador Lunch 10
Complete All Mexico BurgerTime World Tour Levels
See "American Cheese"
French Fries 10
Complete All France BurgerTime World Tour Levels
See "American Cheese"
Banzai Burger 10
Complete All Japan BurgerTime World Tour Levels
See "American Cheese"
Hardcore 20
Complete Each Level Without Dying
This will be one of the most challenging achievements as you must complete each level of each map without dying. Remember to load up on pepper and use your power ups (especially the Spatula)
It's Burger Time! 10
Complete All BurgerTime World Tour Levels
This achievement will come once you have done all 4 maps. This can be done on Easy or Normal mode.
Spatula Man 10
Hit 100 Enemies With The Spatula
There are Power Ups throughout the game. One is the Spatula. Grab it and press the (B) button to use it. You get 3 Spatulas per Power Up. You can hit multiple bad guys with one shot. Smack 100 for the achievement.
Master Chef 20
Win An Online Multiplayer Game
Find someone in the Achievement Trading thread to boost this.
Dirty Burger 20
Crush 2 Other Players In Multi-player With A Single Ingredient
Use the Achievement Trading thread to boost this with 2 other players. You can also use 3 controllers to do this (Thanks to ronron1).
Burger Please 20
Collect All Burger Letters In A Level
This will be your first achievement. On Level 4 of the USA map will be your first attempt at this. Just run around and collect the glowing letters to spell B-U-R-G-E-R.
I Am A Grill Champion 20
Get A 3+ Star Ranking On All Levels
See "I Am A Burger God"
I Am A Burger God 40
Get A 5 Star Ranking On All Maps
This will be the other most difficult achievement aside from completing the game without dying.
This is going to be based on score and time. This will need to be done on NORMAL mode in order to post to the leaderboards and get credit. Use your Pepper and Power Ups where possible. Remember Soda Cans give you speed burst and make you invincible. For higher scores, stun the bad guys with Pepper while they are on part of your burger. This will make it drop by 2. If you have more bad guys on the burger part, it will drop more. (2 guys = 4 drop). Also, you need to avoid dying. Make sure to pick up the letters to spell BURGER where possible as you need the bonus points to 5 star (Thanks to ronron1).
100% Retail = 39
100% Arcade = 16
HEY! That Thing Got A Hemi?
Last edited by rdrunr89; 11-12-2011 at 12:10 PM.
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Jayne Meadows
From Wikipedia, the free encyclopedia
|Jayne Meadows
Press photo 1960
|Jane Meadows Cotter
September 27, 1919
Wu-ch'ang, Heilongjiang, China
|April 26, 2015
(aged 95)
Encino, California, U.S.
|Actress, author
|Years active
|Political party
|Milton Krims (m. 1949-1952)
Steve Allen (m. 1954-2000; his death)
|William "Bill" Allen
Jayne Meadows (who was born as Jane Cotter; September 27, 1919 – April 27, 2015) was an American movie and stage actress. She was the older sister for the deceased actress Audrey Meadows. She was married to Steve Allen. Meadows was nominated for three Emmy Awards. Meadows was born in Wu-ch'ang, Heilongjiang, China to an American family.
Meadows died of natural causes at her home in Encino, California, aged 95.[1]
References[change | change source]
Other websites[change | change source]
Media related to Jayne Meadows at Wikimedia Commons
- Official website
- Jayne Meadows at the Internet Movie Database
- Jayne Meadows at the Internet Broadway Database


text: DALLAS, March 8, 2013 /PRNewswire/ -- X-Change Corp. (NASDAQ OTC: XCHC), a U.S. Company specializing in cannabinoid formulation-based health solutions through its Phytiva brand product lines is pleased that in the last two days, medical cannabis bills have easily advanced out of key committees to full votes in both the Illinois General Assembly and the New Hampshire House of Representatives. These actions toward providing safe access to medical cannabis for people with unmet medical needs in both Illinois with House Bill 0030 and New Hampshire with House Bill 442-FN continue the trend of state-by-state recognition of the medical value of cannabis and cannabinoids. Currently 18 states and the District of Columbia have enacted laws which approve and regulate the use medical cannabis, two of which are considering expansion of existing law. In addition to Illinois and New Hampshire, another 17 states have pending legislation to enact a form of legal protection for medicinal cannabis patients. Recent national polls show that approximately 80% of Americans are in favor of medicinal cannabis legalization. "We are incredibly encouraged that more than two-thirds of U.S. states have adopted laws or are formally considering bills to help patients in need of medical cannabis for their ailments. We commend the most recent bipartisan developments in Illinois and New Hampshire. As more and more jurisdictions provide legal safe access frameworks, the Company intends to enter these markets, not only in the United States but also abroad, with its Phytiva brand product lines," stated Robert Kane, President and CEO of X-Change Corp. About Phytiva Brand Product Lines Phytiva expects to develop and launch various innovative product lines. The first is the Phytiva Brand European Line, which is an inventive line that is a hybrid of a proven, existing product line that has been well-managed and conservatively-run for over a decade with a cannabinoid based product line, utilizing the unique and potent benefits of cannabinoids. Phytiva's revolutionary formulations target not just the symptom, but also the cause. Cannabinoids and their sources constitute an ideal base for therapeutic solutions and have been utilized for centuries in skin and other remedies for human ailments.


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This section of the website is dedicated to projects and initiatives of the Malta Environment and Planning Authority. MEPA participates in a number of EU and internationally funded projects whose benefits range from training and capacity building to investments in infrastructure, equipment and systems.
MEPA also regularly runs programmes and schemes itself, aiming to promote specific environmental, planning or corporate objectives.


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What's with the Pineapple?
In the seafaring days of early America, ship captains would place the eye-catching fruit on a fencepost to mark the return home from a long voyage. Gradually, it became synonymous with hospitality. Today, the pineapple's striking good looks have cemented its spot as a design-motif darling. Welcome your guests with one of these fresh picks.
Neighbors refer to this Birmingham home as "The Pineapple House" because of the portico's stylized finial.
Pineapple Side Table powder-coated cast aluminum in White (63600-WHI), $699; frontgate.com
Hospitality Pineapple Door Knocker in Nickel Silver (MH1503), $115; michaelhealy.com
2-Inch Lanai Finial (FIWGLNI), $118; antiquedraperyrod.com
Plantation Pineapple Wall Sconce with Clear Optic Glass in Burnished Brass (RS-03HK-4140BB), $349.90; houseofantiquehardware.com
Petite Pineapple Wallpaper in Black/White (SPW-W1041-01); studioprintworks.com for retailers.


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So after waiting for six months and going through the motions in order get my permit, my application has been denied. The judge (Richard Platkin) stated that due to my driving record, I show instances where I lacked maturity and responsibility, as well as instances of disrespecting the courts (failure to show up to court in 2006 resulted in a suspended license resulting in me getting pulled over and convicted of "aggravated unlicensed operation" in the 3rd degree. So five years ago when I was 18 years old I made a bad decision (though not a criminal act in the form of violence, theft, or drug related) that is now resulting in my denial of my right to possess a pistol, even for target shooting. I also was pulled over four times in a four month period in 2009. Since then I've only multiplied my yearly income, bought a $450k house, 2.5yr relationship with a retired police chief's daughter, and raised my credit score 300pts with all three credit bureaus. But to the judge, I did not show that I have changed one bit.
I already called my lawyer who has handled (successfully) several pistol permit appeals and I just need to go down and pick up all of my application bits and pieces when they're ready and bring them to him.
Side note: Anyone looking for a nice house in Guilderland in a great neighborhood?


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HTC Supersonic EVO 4G Black Line Snap-On Faceplate Cover Case
Personalize and protect your cell phone with this stylish faceplate protector cover case.
Stylish front and back cover designed to fit perfectly. Protect your cell phone with these aluminum alloy cover cases.Tags: gifts, checkers, htc accessories, HTC 4G case, EVO 4g case, HTC Faceplate, htc coverAdded 7 Years Ago from Wirester


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Dr. Terri Gómez
The keynote speaker, Dr. Terri Gómez, captivated the audience with her life story. Although faced with numerous obstacles, Dr. Gómez prevailed, eventually completing her Ph.D. and is now the Chair of Ethnic and Women's Studies at Cal Poly Pomona.
Workshop: The Relationship of the Master's Degree to the Ph.D.
Diversity Forum participants had a variety of workshops to attend throughout the day. In this workshop, Susan Smith moderated panelists Wendy Acosta, Jerry Flores, and Dr. Carlos Grijalva, share their experiences and insight regarding the path to a Ph.D. by obtaining a masters degree first.
Graduate Recruitment Fair
Diversity Forum participants had exclusive access to nearly 200 recruiters representing hundreds of graduate programs across the country.
Diversity Forum Volunteers
The Forum's coordinator, Rebecca Rivas (center), stands proudly with a cluster of Cal Poly's best! Volunteers, such as these, are instrumental to ensuring a successful and smooth event of this scale. Thank you!
The California Forums for Diversity in Graduate Education, planned by a consortium of public and private colleges and universities from throughout California, have been designed particularly to meet the needs of advanced undergraduates and master's candidates who belong to groups that are currently underrepresented in doctoral-level programs. The groups include low-income and first-generation college students and especially African Americans, American Indians, Chicanos/Latinos, Filipinos, Pacific Islanders, Asian American women, and Asian American men in the arts, humanities, and social and behavioral sciences.
Each California Forum for Diversity in Graduate Education will bring together approximately 1,000 pre-selected, high-achieving undergraduate and master's students. The students will explore graduate opportunities and resources by participating in numerous workshops conducted throughout the day. Universities and individual graduate programs offering academic master's and/or Ph.D. degrees are welcome to participate in the recruitment fairs that will take place concurrently with the other planned activities. Note that these events are for all disciplines except programs in medicine, dentistry, optometry, chiropractic, pharmacy, veterinary science, and law, all of which have their own recruiting networks.
Fall 2017 Sponsors
We are thrilled to have committed institutions of higher education as sponsors of the California Forums for Diversity in Graduate Education. To learn more about these institutions and their exciting opportunities, please click on the banners below.


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Hi everybody, i'we been reading all posts, searched google, but found almost "0".
Car 2003 WRX , 136*** miles, no mods to engine, no mods to exaust etc.
Only upgrade is:
4 tokico d-spec adjustable shocks struts i belive on stock springs with stock top mounts.
I got my car 6 month ago, all was fine and tight, after my trip to San Francisco from Colorado my rear driver shock quit, i found 2 used shocks to put in the back of my car for 50$, while i send my bad shock to be replaced under warranty. It happened in September, and i got my new shock in February, so my friend/mechanic took out old ones and put new ones back in.
All top bolt tight and springs installed correctly.
My problem is:
Well i have this awful noise from the back especialy when going over cracks in the road, potholes, even if it's 0.5 -1 inch deep. Sound like something loose, and metal binds to the metal, when under car, can't find any loose parts, don't know what bushings should look like, but seems to me they ok. And the noise is the worst when i go over bump and turn, it feels like whole back going to fall apart, it like you hit the metal covered with plastic.
The same sound comes from front but quiter with the same symphtoms.
It's quiter when it raining outside .......
Help me to identify, or if anyone lives in Denver and willing to help me to identify the problem before i waste my money, i was thinking to replace all bushings , but have no idea if it going to help.
Any reply and advice will be hightly appreciated from you.


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There is no doubt but ZTE is on the up. Not only did it strike the perfect balance between price and performance with its San Francisco model last year, it also jumped into fourth spot of mobile phone vendors globally.
Now however, it is hoping to build on that success with its latest Android model, the 4.3in Gingerbread-running ZTE Skate. Announced at Mobile World Congress in Barcelona, the Skate will be ZTE's flagship model but despite the company's plans to break into North America, reports are suggesting this model won't be heading in that direction. The Skate is the first device that comes under ZTE's "Light Your Smart World" strategy which will see a range tablets, internet boxes and smartphones launched this year.
The ZTE Skate was apparently inspired by the skateboard and despite it's 4.3in screen weighs only 120g – compared to 164g that the similarly sized HTC Desire HD weighed in at. The Skate is powered by an unnamed 800MHz processor and the Adreno 200 GPU, which are not the most awe-inspiring of specs considering we live in the world of dual-core 1GHz superphones. The Skate has a 5 megapixel camera, Bluetooth, A-GPS and Wi-Fi.
The Skate will be available in certain markets around the globe in May of 2011 however no word on pricing has been revealed yet. We will obviously be hoping that the Skate will follow the San Francisco down the budget line as the specs don't exactly scream premium to us but we will have to wait and see.
Source: ZTE


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When I was young I used to look forward to the Summer holidays. Eight whole weeks of no school and having fun. We used to pretty much amuse ourselves, in those days there were three channels on the television and children's programmes were limited to around an hour at tea time. In the Summer we also got an extra hour in the morning and were treated to Flash Gordon, Tarzan and a programme called "Why Don't You". The idea was why not turn off the television set and go and do something less boring instead. We used to wander around the neighbourhood, building dens in the trees, going off on bikes, playing football in the street and playing in a tent that we had in the garden. The days always seemed to be long and sunny and we had fun.
These days kids seem less able to amuse themselves, they don't tend to play out the way we did. When they do spend time with each other they seem to be permanently attached to phones, iPods or video games. I have been trying to get my son to get out and have some Summer fun and these are some ideas that I found worked.
- Check your local sports centre for activities. I found mine was running a number of different activities during the Summer including Laser Tag, Sport and Splash days and Climbing Wall activities. All the activities are supervised so you can drop your child off and collect them later. The prices were reasonable as well.
- Check your local library. They usually run a reading quest over the Summer where you need to read a certain number of books and get rewards as you go. Each Summer the theme is different and it is great for helping encouraging children to read.
- Visit your local museum. They are free and often have lots of activities on over the Summer. We love visiting the Discovery Museum in Newcastle Upon Tyne, they have lots of interactive displays and if your child is a football supporter Toon Times is worth a visit. The Great North Museum is also fabulous with its displays of natural history.
- If you have a bit of money to spend a day at a theme park is always fun. We recently visited Flamingoland where we had great fun enjoying the rides and the zoo. These trips can be expensive so save money by packing a picnic.
- Check the English Heritage and National Trust websites. They have lots of great properties that are worth a visit but over the Summer you often find events going on. We found Vikings at Linidisfarne and Knights at Warkworth Castle, both events were really interesting.
For Summer fun you need to have Summer food. Pick up a picnic and add lots of snacks to keep you going though the day. We have recently been enjoying McVities BN Biscuits in chocolate and raspberry flavours.
They are deliciously tasty, don't melt in the sun and their happy smiling faces make you want to smile. My son loves them and loves me producing a packet to share on a day out.
We are getting up to lots of things this Summer. What are you doing?
This post is an entry for 42 Days of Summer Linky Challenge sponsored by McVitie's BN. Learn more at http://bit.ly/1mRpMCL


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The branch that you searched for does not have a page in your preferred language. Would you like to visit the branch page on the #CODE# site?
As the world leader in paper shredding, we ensure your documents are securely destroyed.
Hard drives could cost you millions in a data breach. Physically destroy your electronic data.
Get a Quote
July 30, 2015
Lynn Brown
Back To Blog
When was the last time your organization updated its information security policy?
A few months ago? A few years? Never?
An information security policy is a document that explains policies and procedures for protecting physical and information technology assets. While the policy should be concise, user-friendly, and aligned to legislation and regulatory frameworks, it must also be a fluid and evolving document that allows an organization to keep up with trends in information security and changes in the threat landscape.
Close to half – 43% – of companies in the 2014 Second Annual Study on Data Breach Preparedness by Ponemon experienced a data breach in the past year. That was an increase of 10% compared to the previous year.
Here is an information security checklist that puts the spotlight on important security trends.
Schedule regular updates of information security policies and procedures. The world of information security has changed so completely that any policy written more than two years ago is almost certainly irrelevant, commented Geoff Webb of NetIQ in a recent Forbes.com article.
Provide leadership. Appoint an individual (Chief Information Security Officer) and committee to be responsible for managing data security procedures.
Conduct regular risk assessments. A security risk assessment will identify areas that are vulnerable to a breach. For example, at this time, the Internet of Things revolution is significantly increasing security risks.
Focus on mobile device security. The highly mobile workforce is here to stay. According to the Global State of Information Security Survey 2015, 54% of respondents say they have implemented a mobile security strategy, and 47% say they employ mobile-device management or mobile-application management solutions.
Support employee knowledge and understanding. According to the 2015 State of the Endpoint study, three-quarters of IT professionals say their company's biggest threat consists of employees who aren't following security policies. Create a culture of security throughout the organization, and provide on-going practical skills training.
Evaluate third-parties. Breaches caused by third parties with trusted network access continue to rise. The Shred-it 2015 Security Tracker showed that 58% of small businesses don't perform security checks when procuring a third-party vendor. Insist that third parties employ security and privacy safeguards.
Simplify safeguarding procedures. In the Forbes.com article, Kevin Epstein of security solutions provider Proofpoint suggested that when users can click 'send' in their email program and have a central policy engine decide if the email needs encryption or violates the privacy policy, "security is less circumvented, more consistent, and thus better". Other recommendations: continuous monitoring of information systems and automatic access control.
Integrate physical security practices too. One important policy is a shred-all policy – all documents are destroyed when no longer needed. Partner with a document shredding company that installs locked consoles in the workplace for documents. Security-trained personnel will collect discarded documents for secure on- or off-site shredding, and a Certificate of Destruction will be issued after every shred.
Schedule hard drive destruction. Ensure that all obsolete technology and equipment (as well as e-media that is no longer needed), is fully destroyed so information cannot be recovered. Speak to your document destruction partner.
Use this Security Risk Pyramid to rate your document security processes. Shredding paper on a predetermined schedule is a best practice.
Fill out the form or call 888.750.6450 to start protecting your business today!


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Category Archives: P is for Prophet
Walk Beside Me LDS Preschool Curriculum: Letter P
I meant to post this yesterday, and you know what happened?
Ugh. It was one of those days where banging your head on the wall doesn't even begin to make a dent in your frustration. Your skull yes; frustration, not so much. So I'm later than I planned on the newest Walk Beside Me LDS Preschool curriculum packet:
P is for Prophet!
This is such a fun packet. I have a great love for President Monson and I hope my children will too. There are many resources to teach your child about our current prophet as well as prophets through the ages. Here is an adorable video made for primary children based on Pres. Monson's General Conference talk, "What Have I Done for Someone Today?" Did you know Pres. Monson has his own website? You can also share this article from the Friend about Pres. Monson. If you need to brush up on your Pres. Monson trivia for those endless questions from your preschooler, check out this biography on our prophet. In the packet I have also included a child friendly biography about President Monson's life.
This week's secular focus is P is for Princess or P is for Pumpkins, both from Confessions of a Homeschooler. Because we went to the aquarium this week, I ultimately ended up finding some great P is for Penguins resources! That's one thing that I love about this curriculum and homeschooling. You can adjust it to your child's interests on the fly.
If this is your first visit to my Walk Beside Me LDS Preschool curriculum, you can find out more here or check out the FAQ page here. Don't forget to check out the Walk Beside Me Store. It's an affliate Amazon store. Amazon offers me a small percentage of profits and for the time I put into these packets, it helps me justify the few dollars I earn here and there. :) Many families have used these to supplement their homeschooling or public schooling, as well as using them for Sacrament meetings, family home evenings, and more! If you have any questions or downloading problems, leave a comment or email me at firstname.lastname@example.com


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Make a swag
This gracefully curving swag creates a leafy half-moon on a garden gate. Japanese maple clippings and liquidambar leaves are tucked into a base of twiggy stems.
If you have a birch or similar tree that drops wispy branches, you can gather several into a bunch and tie them in the middle with florist's wire. Otherwise, buy a twiggy swag base at a craft store (about $10 for one 16 inches long).
Around The Web


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PAULINE and Geraldine met at chapel one day. They appeared to be instantly to have much in like manner. Both had an infant and another kid each under six. What's more, their separate spouses, Brice and Doug, appeared to get along together also. Both families fraternized over the resulting five years, at chapel, in each other's homes, serving others for Christ together, and serving and cherishing each other. Both couples were dynamic in their serving inside their congregation, much to the degree that among them they were about three fulltime proportional peaceful parts (senior pioneers) on the congregation staff. Every couple was a perfect supplement for each other, as well as both couples were a perfect supplement for their congregation. Everything worked so well. Also, best of all, the congregation was developing in venture into the group, and in profound profundity.
Yet, then something happened, which happens in a great deal of connections. A misconception happened, a subject of poor correspondence created, and the relationship broke down.
Geraldine and Doug encountered a sudden misfortune inside their family, and they observed what they regarded to be no comfort from Pauline and Brice. For Geraldine and Doug, it appeared that for Pauline and Brice it was basically the same old thing, and Geraldine and Doug found that to a great degree harmful. Indeed, it was as though their companionship had wilted in extent with their expanded duties at the congregation, and upon their common dependence to run the congregation. The more they cooperated, the less they were companions. How could their companions – best of companions – and ministers at that – turn out to be so icy and cold… overnight?
There's constantly two sides to a two-sided story, be that as it may. Whilst Geraldine and Doug were pondering their misfortune, Pauline and Brice clearly needed to bear the greater part of the congregation workload, and they were at that point wearing out. They hadn't understood that they secretly detested the way that Geraldine and Doug as of now had a plenty of backing, and it appeared as though Geraldine and Doug didn't require their backing. That hurt! In any case, the reality was Geraldine and Doug were secretly looking for backing from Pauline and Brice; bolster that Pauline and Brice had wrongly believed was unnecessary. It was a huge misconception, on account of an absence of correspondence, straightforwardness and helplessness. Both couples needed to be required, and neither one of the couples felt the other minded. The actuality was both couples minded an extraordinary arrangement.
What began as delightful in the domain of connections got to be harsh, then lethal.
The couples came in the end to be so harmed as to disdain each other, and the broke relationship between the couples really brought about conjugal erosion (between accomplices in both relational unions) where there had beforehand been none.
There's a motivation behind why church is troublesome, and why numerous individuals find they've outgrown church. Church requests a power of relationship that can rapidly surpass the development in the relationship.
Presently, these sorts of cracked connections don't simply happen in chapel, yet they do as often as possible happen in the congregation.
Here is an imperative truth we as a whole need to confront: draw near to anybody – as we do in chapels – and we find we're compelled to face truths we would incline toward weren't there.
God places us in group to end up cozy with others, which feels useful for some time, before group turns into the wellspring of torment and the impetus for development.
The astuteness for couples like Geraldine and Doug and Pauline and Brice is as basic as it's excruciating. To rise above the agony they would every experience for their closeness, they each should have been develop enough to long for compromise. It's too simple for couples like Geraldine and Doug and Pauline and Brice to end up captivated. But all they each expected to do was to continue putting Christ first.
Put Christ first and development gets to be unavoidable. The key incongruity encompasses torment. Had it not been for the torment Geraldine and Doug and Pauline and Brice experienced, there would be no driving force or vehicle for development; no need of expecting to put Christ first in a new and significant way.
The developed continue putting Christ to begin with, in light of the fact that to be adult requires consummate responsibility to quietude.
Drawing near to other individuals compels a reaction. Possibly we develop in pleasing individuals or we disdain what closeness drives us to confront.


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White Township
Simple assault
State police at Indiana said Janie Davis, 36, of Indiana, and Florenda Nicholson, 60, of St. Robert, Mo., engaged in a verbal and physical altercation at 10:40 a.m. Friday at 5150 White Oak Drive.
Police said both women suffered minor injuries in the incident.
Both were arrested and charged with simple assault and harassment.
Burrell Township
Criminal mischief
Between 5 p.m. Saturday and 6 a.m. Sunday, someone caused $560 worth of damage to eight exterior windows at the Weir Oil & Gas building at 1519 Route 22.
State police at Indiana said the windows were shot with a BB or pellet gun.
Sign stolen
A large sign reading "Welcome Back Students" was stolen by a male suspect at 3:11 a.m. Saturday from the 1200 block of Oakland Avenue.
Indiana police said the sign measures 10 feet by 2ᄑ feet.
Anyone with information on the missing sign is asked to call Indiana police at (724) 349-2121.
Pine Township
Retail theft
The unknown driver of a gray Toyota Highlander drove away from the Strongstown General Store at 14345 Route 422 without paying for $62.53 worth of gasoline. State police at Indiana said the retail theft happened at 6:30 p.m. Sept. 1.


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Kieron Dyer today announced his retirement as a player at the age of 34, writes Giuseppe Muro.
Dyer was released by Middlesbrough at the end of the season and has decided to focus on a coaching career, even though he had offers from abroad to continue playing.
The injury-plagued former England midfielder has been taking his first steps into coaching at Ipswich, where he started his career. "I am done now, I am content and that is it," said Dyer, who rejected playing offers from clubs in America and Dubai.
"I do not want to move away any more, I just want to spend quality time with my kids.
"Since I went up to Newcastle, I have been all over the country and I have not really had too much quality time with my kids and now I feel that it's the perfect time.
"It has got nothing to do with injuries, nothing to do with money, it is just that I am content with life."
After coming through the ranks at Portman Road, Dyer spent eight years at Newcastle and was part of England's 2002 World Cup squad.
West Ham paid Newcastle £6million for Ipswich-born Dyer in 2007 but he made just 34 appearances in four years at Upton Park before brief spells at Queens Park Rangers and Middlesbrough.
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Coffee. Espresso. Tea.
We know sometimes people get a little confused about what we're selling or what the titles mean. Maybe they're too clever, or too witty, or too complex. Well, for those types of readers... here you go. Coffee. Espresso. Tea. Any simpler and we'd be showing you flash cards.
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text:
|Publication number
|Publication type
|Application number
|Publication date
|Jul 24, 2007
|Filing date
|Jul 20, 2000
|Priority date
|Jul 20, 2000
|Fee status
|Publication number
|Michael R. Arneson, Terrance L. Bowman, Frank N. Cornett, John F. DeRyckere, Brian T. Hillert, Philip N. Jenkins, Nan Ma, Joseph M. Placek, Rodney Ruesch, Gregory M. Thorson
|Original Assignee
|Silicon Graphics, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (50), Non-Patent Citations (15), Referenced by (30), Classifications (11), Legal Events (13)
|External Links: USPTO, USPTO Assignment, Espacenet
The United States Government has rights to use this invention pursuant to subcontract B338314 issued by the University of California, which operates Lawrence Livermore National Laboratory for the United States Department of Energy under Contract No. W-7405-ENG-48.
The present invention relates to methods and apparatuses for communicating data across a communications medium; and, in particular to a system and method for communicating between asynchronous devices.
In the communications industry, the need for faster communication between computer elements is ever increasing. As can be appreciated by the rapid advancements in processor speeds, there is also a need to increase the speed of communicating data across computer systems. However, prior systems have proven limited in their capabilities. The traditional methods of increasing speeds include increasing signal rates or increasing the number of wires used in a communications medium. Increasing signal rates, however, means increasing the speeds of all the electronic components in the communications path. In addition, signal bandwidth must be increased, leading to more distortion in the communications medium. Furthermore, increasing the number of wires creates additional expense in manufacturing, decreases reliability and adds unwanted bulk or stiffness to the communications medium.
There have been some attempts to increase the speed of communications mediums without increasing signal rates or adding more wires. For instance, systems have provided for unidirectional data transfer in both directions on a data bus; the data transfer, however, did not occur in both directions simultaneously, only in one direction at a time. If only the data could be transmitted in both directions at the same time, then the rate of data transfer over a communications medium could significantly increase without having to increase the signal rate or without having to add more bulky and expensive wires.
Previous approaches are not only limited in the speed of data transfer, but also in the cost-efficiency of transmitting data signals across communication mediums. For instance, state of the art communication mediums require that wires be highly toleranced to avoid signal distortions. However, high tolerancing is an expensive manufacturing cost. If there was a way of reducing signal distortion in the communications medium without having to rely on high tolerances, then a great deal of cost could be eliminated from the manufacturing of communications mediums.
The present invention provides solutions to the above mentioned limitations in previous communications systems. Several embodiments are provided below of a communications channel having a link level protocol, a driver, a receiver, and a canceller/equalizer.
The link level protocol provides logic for DC-free signal encoding and recovery. In addition, the link level protocol supports features such as CRC error detection and message resend in order to accommodate bit errors in transfers across the communications medium. The canceller/equalizer provides equalization of the data signal that may have occurred in the medium and also provides for simultaneous bi-directional data transfer, thus allowing for clearer and faster data transfer without increasing the signal rate or the number of wires in the communications medium.
In one embodiment, the receiver provides bit deskewing by removing synchronization error, or skewing, between data signals after they have passed through a communications medium. In another embodiment, the driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium. In yet another embodiment both bit deskewing and impedance controlling are present. The bit deskewer and the impedance controller improve the clarity of signals without having to highly tolerance the wires in the communications medium.
In another embodiment, the invention is directed toward a communications medium consisting of a processor and a transceiver comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. And, in yet another embodiment, the invention is described as a plurality of processors communicating via transceivers comprising link level protocols, drivers, receivers, and canceller/equalizers.
In another embodiment, the invention is directed to a method for driving an output signal as a function of a first signal, receiving a second signal from the communications medium, combining the first and second signals to extract a receive signal, and deskewing the receive signal.
The following detailed description describes the present invention in sufficient detail to enable those skilled in the art to understand and utilize the invention. However, it must be understood that other embodiments exist, and that logical changes may be made to the various embodiments of the invention without departing from the spirit and scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.
Link level protocol 110 provides a uniform interface to transceiver 100, as is generally understood in the art. Link level protocol 110 includes an input/output 112, a driver line 114 connected to driver 130, and a receiver line connected to receiver 140. The link level protocol 110 is used as an exemplary protocol for many reasons. For instance, link level protocol 110 allows for a DC-free signal encoding and recovery over a communications channel. Link level protocol 110 also allows for some degree of asynchronous clocking out of the receiver 140. In one embodiment, link level protocol 110 supports features such as cyclic redundancy check (CRC) error detection and message resend to accommodate bit errors in data transfers across the communication channel.
In one embodiment, link level protocol 110 packages data and allows for data packet framing. The link level protocol 110 computes the CRC for packages the transceiver 100 transmits and checks the CRC for packets it receives. Furthermore, the link level protocol 110 detects the life of another link level protocol to which it is connected and restarts a data transmission if no life is detected from a connecting device or if a connection is lost to that device. In addition, the link level protocol 110, when used in embodiments of the present invention, enables special deskew training signals from the receiver 140.
The driver 130 includes a driver circuit 134 and an impedance controller 132. The impedance controller 132 connects to driver circuit 134 via an impedance controller line 136. The impedance controller 132 continuously monitors the impedance of the communication channel by monitoring signals representing voltage, temperature, or other variation or process characteristics of the communications medium. The impedance controller 132 then interacts with the driver circuit to automatically drive a signal through the driver output 138 with an output impedance matching that of the communication medium. For more specific details on how the impedance controller works, see "Impedance Controller" U.S. Pat. No. 6,703,908, Issued, Mar. 9, 2004, which is incorporated by reference.
The canceller/equalizer 120 connects to the driver 130 via the driver output 138 and receives a driver output signal. The canceller/equalizer 120 also receives signals coming off the driver line 114. "Compensated Canceller and Equalizer for Simultaneous Bi-directional Communications in a Computing System", U.S. patent application Ser. No. 09/441,774, describes a canceller/equalizer 120 which generates an equalized signal that is transmitted to receiver 140. The system and method of bi-directional communication described is incorporated herein by reference.
In one embodiment, canceller/equalizer 120 provides simultaneous bi-directional signaling across the communications channel. Although bi-directional signaling can conceivably occur at any rate, one embodiment of the particular canceller/equalizer discussed in "Compensated Canceller and Equalizer for Simultaneous Bi-directional Communications in a Computing System" is capable of simultaneously transmitting and receiving 40 data signals (4 Bytes) at a data rate of 3.2 GBytes per second in each direction on the communications medium, or 6.4 Gbytes per second composite. Although the canceller/equalizer 120 can transmit simultaneous bidirectionally, it can also transmit unidirectionally, at half the speed of simultaneous bi-directional communication. Of course, these are only a few of the general capabilities of the canceller/equalizer 120. For others, refer to "Compensated Canceller and Equalizer for Simultaneous Bi-directional Communications in a Computing System", U.S. patent application Ser. No. 09/441,774.
In one embodiment, receiver 140 receives the equalized signal from the canceller/equalizer output 121. The receiver includes a receiver circuit 142 connected to the canceller/equalizer output 121, a clock receiver 144 receiving a clock signal 145, and a bit deskew 146 connected to the receiver circuit line 143 and the receiver line 116. As described in "System and Method for Adaptively Deskewing Parallel Data Signals Relative to a Clock" U.S. patent application Ser. No. 09/476,678, the description of which is incorporated herein by reference, the bit deskew 146 continuously tracks data and continuously corrects skew among data lines in the communications medium. The bit deskew 146 can coarse tune or fine tune the received signal with a potential for up to 3.75 ns of deskew at an 800 Mb per second signaling rate. The bit deskew 146 can also center the clock signal on the clock line 145 received by the clock receiver 144. Of course, these are only a few of the general capabilities of the bit deskew 146. For others, refer to "System and Method for Adaptively Deskewing Parallel Data Signals Relative to a Clock" U.S. patent application Ser. No. 09/476,678.
In the embodiment of
The drivers and receivers of the present invention may transmit and receive data utilizing, what can be termed, Path Forward Source Synchronization. If so, driver 130, 230 or 330 may be called a Path Forward Source Synchronous Driver (PFSSD) and receiver 140, 240, or 340 may be called a Path Forward Source Synchronous Receiver (PFSSR). The sections below entitled "PFSSD" and "PFSSR" describe how to implement PFSSDs and PFSSRs into the embodiments of the present invention.
In one embodiment, PFSSD 700 performs 4 to 1 multiplexing on every 4 input data signals at 200 Mb/s to output one data signal at 800 Mb/s. The PFSSD 700 generates two handshake signals, frame_out 704 and data_ready_out 706, to be used by a PFSSR. The PFSSD 700 outputs 40 data bits, dout<40:0> 702, and is capable of performing 4�1 time multiplexing on 160 bits of input data, din<159:0> 701. It forwards a pair of complementary clocks, clk_h 708 and clk_1710. The PFSSD 700 interfaces with the LLP 110 (
Some additional suggestions for PFSSD enablement now follow. The PFSSD should be bit stacked as a hard macro instead of placed randomly. The control block should be placed in the middle, and all 48 single bit slices (12 4-bit slices) should be placed symmetrically along each side. All input ports should be placed in one edge of the PFSSD hard macro, and all output ports should be distributed evenly along the center. The 800 Mhz clock fanout tree should be placed carefully to reduce the clock skew at each output flop. If possible, isolated wire should be used for routing the clock fanout tree. Same attention should be paid to the placement of buffers for fanning out the load signal from the control block to each bit slice. The placement areas should be highly utilized but should not conflict with routability. Because outputs from the PFSSD are complemented, it is critical to have the inverted clock standard cell placed between the PFSSD and all corresponding IO cells to rebuffer the signals. The high speed clock driving the control block must be the earliest clock in the PFSSD. This block produces a control signal which is fanned out to all the bit slices. The fanout has inverters and long routing metal that must make the flop to flop timing within the 800 Mhz clock cycle. The optimum timing would have the clock reaching the control block 50 to 100 ps earlier than the clocks to the rest of the PFSSD, but no more than 250 ps earlier. The edge rate of high speed clocks anywhere inside the PFSSD must be 200 ps (10%-90%). The edge rate of core clocks inside the PFSSD should be no more than 300 ps (10%-90%). The edge rate data signal, including Load 724 and Shift 725 signals, anywhere inside the PFSSD should be no more than 300 ps (10%-90%). The edge rate of test signals must be within 4 ns (10%-90%). And finally, the high speed clock skew at the output flops 763 of all 48 4�1 time multiplexers must be �25 ps from the flop that launches clk_h 708.
The PFSSR 800 performs 4 to 1 time demultiplexing on input data signals at 800 Mb/s to output four data signals at 200 Mb/s. It receives a pair of complementary clocks, Channel Clock 808 and core_clk 809. It also uses two handshake signals, Data_Ready 803 and Frame 802 to synchronize the Channel Data 801 to a core channel frequency. The PFSSR 800 receives 40 data bits 801 (plus Data_Ready 803, and Frame 802) of serialized, high speed data and performs 4 to 1 time de-multiplexing to provide 160 bits of output data, dataout[159:0] 810, to the core. The Channel Clock 808 is received differentially, frequency doubled (CLK 2X 811), and fanned out (fanout 812) to high speed flip flop elements 813. The Channel Data 801 is received by a high speed 4 bit shift register (not shown). The outputs from the shift register are loaded into either one of two banks of 4 bit registers (known as the EVEN and ODD registers). The first set of four bits out of the shift register are loaded into the EVEN register and the following set of four bits are loaded into the ODD register. Data_vld_out 814 is generated from the handshake signal Data_Ready 803 and is a plesiochronous signal received by the core. When received by the core it indicates that the first piece of data is valid in the EVEN register. The data in the EVEN register can then be sampled by the core clock and on the following cycle of the core clock, the ODD register can be sampled. Internal to the PFSSR 800, the Frame 802 signal is treated equivalent to Channel Data 801, with the exception of the CTUNE sequence 816. Frame 802 is used by the LLP for data frame alignment when DC-free data encoding is utilized.
The channel interface from the PFSSR 800 to the LLP 110, 210, 310 is treated as plesiochronous. That is, the source synchronous channel clock and the receive side core clock are referenced to separate oscillators which may be mismatched in frequency by no more than several hundred of PPM. Whenever there is a slower receive side clock there is an undersampling condition which can lead to eventual bit error. Undersampling causes the data "eye" to be sampled later with each new clock cycle. Under sampling is resolved by limiting the maximum length of consecutive data bits before resetting Data_Ready 803. There is a trade-off between hold time margin and the maximum burst length. The synchronization occurs through the use of a two stage synchronizer (not shown). The synchronizer is implemented with common standard cell latches (not shown). There is approximately several hundred nanoseconds of 'start-up' or 'lock' time that must be accounted for (i.e. tolerated) in the interface between LLP/PFSSD and PFSSR/LLP, due to the analog nature of the frequency doubler 811 and delay lines 804 and 815 used in the PFSSR 800. The delay lines 804 and 815 have a significant (RC) time constant to minimize jitter due to rapidly changing conditions. Under normal start-up conditions the frequency doubler 811 has approximately several (clk2x) clocks of latency between an incoming channel clock and a fanned out (clk2x) clock.
Bit Deskew and Clock centering circuitry is added to independently center the capture clock within the center of each data eye. The deskew is achieved by adding additional delay to "early" arriving data signals so they match the "latest" arriving signal. Additional delay may be added to the clock or data signals to position the clock within the data eye. The Delay Line Controller 820 maintains minimum latency through the delay lines once the objective has been met. The delay lines are composed of Fine 804 and Coarse 816 tune stages. The Fine tune stage provides a minimum of 1.5 ns of fine tune deskew range with less than 90 ps step sizes. The Fine tune delay lines are made from differential delay circuits which further offer differential duty cycle correction. An internal muxing scheme eases many timing and physical design concerns encountered when selecting between tap points distributed along a long delay line. The Coarse tune stage provides a frequency dependent amount of additional delay (1, 2 or 3 clock cycles) which corresponds to a range of 2.5 ns at signaling rates of 800 Mb/s. The Coarse tuning technique uses the Frame 802 signal as a references and can deskew �1 clock cycle of delay variation with respect to this signal. Two unique Frame signals 802 are used in bi-directional signaling over a single cable (traveling in opposite directions). The forwarded channel clock is nominally delayed from the Channel Data 801 by 90 degrees (� channel clock period). This takes place on the transmit side of the link by either launching channel clock off of the opposite edge of the high speed transmit clock as the Channel Data 801 (Default) or by launching clock and data off of the same core clock edge and then delaying the clock with an additional PCB foil trace length. A digital Sample and Hold Phase Comparator (not shown) is used to establish the phase relationship between the local capture clock and the Fine tuned deskewed data. Since any individual phase comparison would be subject to significant error due to data edge jitter, a minimum of 256 samples (nominal filter size) are required before a new estimate of "data early" or "clock early" can be made. The individual phase comparisons are digitally filtered inside the Delay Line Controller 820 prior to any adjustments being made to the delay line tap settings. An initial training sequence is required to deskew and center the data and clock. The channel protocol (LLP) will incorporate an initial start-up sequence which provides a sufficiently long sequence of data edges to guarantee that the Delay Line Controller 820 can deskew the data using the Fine Tune Delay Line 804. At the end of this start-up sequence a one-time coarse tune sequence is initiated. The coarse tune sequence is required because the phase comparator 860 has phase ambiguity if the clock is skewed from the data by more than �Tbit/2. In other words the phase comparator 860 cannot distinguish whether the Nth clock edge is being compared against the Nth or (N+1)th or (N−1)th data "eye". Therefore the one time coarse tuning sequence is used to re-align all data bits which have slipped beyond the resolution of the phase comparator 860. Logic inside the Frame data bit slice 806 is designed to detect a Coarse tuning sequence ('110011') which is sent on the incoming Frame 802 signal. Upon detection, a pulse (known as CTUNE) is generated and fanned out to all the data bit slices, Data_Ready bit slice 807, and Frame bit slice 805. The CTUNE pulse delays the incoming data either 1, 2, or 3 clk2x (i.e. frequency doubled version of channel clock) cycles prior to entering the internal high speed shift register, after determining if the data is early, nominal, or late. If none of the slices have late arriving data, as determined via the logical OR of all the data, Data_Ready 803, and Frame 802 'late' signals, then all the data travels through one less coarse tune flip flop of delay to reduce the overall latency by one clk2x clock cycle.
Some additional suggestions for PFSSR enablement now follow. The inverted copy of data at the fine tune delay line input is to be generated locally. The edge rate of the channel clock and the high speed clock (i.e. CLK2X) anywhere inside PFSSR must be no more than 200 ps (10%-90%). The Data and Channel Clock path must be balanced from IO cell to the first capture PFSSR flip flop across all Process, supply Voltage, and junction Temperature (PVT) conditions. This path will include the minimum delay path through the fine tune delay line and the rising edge delay through the clock doubler circuitry. This is especially important for compatibility with other communication channels where bit deskew and clock centering is not active. The edge rate of any data signal, including load signals anywhere inside PFSSR should be no more than 400 ps (10%-90%). The edge rate of all test signals must be no more than 3 ns (10%-90%). The differential input to the Fine tune delay line is to be generated by inverting a single ended input. This inversion should take place local to the delay line input with minimal latency and balanced rise/fall delay. All Clk2X paths should be timed at 1.6 GHz (Nominal PVT) and 1.2 GHz (WC PVT).
The present invention can signal in either unidirectional or simultaneous bi-directional modes.
The present invention can be implemented utilizing both single-ended and differential signaling. The sections below entitled "Single-Ended Signaling" and "Differential Signaling" describe these types of signaling.
Single-Ended Signaling
The single-ended signaling format is binary NRZ (BNRZ), with a low voltage level corresponding to a 0, and a high voltage level corresponding to a 1. Data transmitters are capable of producing an unloaded voltage swing from ground to V dd. However, since both source and destination termination are utilized, the observed voltage swing has nominal values of Vdd/4 and 3Vdd/4 for a single transmitter operating into a quiescent termination to mid-rail (Vdd/2). For bi-directional signaling, the observed channel signal assumes nominal values of 0 V (Left and Right transmitters both 0), Vdd/2 (Left and Right opposite values), and Vdd (Left and Right both 1). Proper termination, nominally matched to the transmission line, is provided at both ends of the channel by connection to communications medium transmitters discussed below. In order to remove variations due to process characteristics, voltage, and temperature, automatic setting of termination resistance is provided in the transmitters. This setting is updated periodically to provide tracking of variations. At the present time, single-ended channels are intended primarily for communications between chips on a single printed circuit board. Specifications for single-ended channels are met for an inter-chip distance of up to ten inches, with both chips mounted on the same printed circuit board. Single-ended communications over longer distances is a future possibility. Unidirectional communications at a nominal rate of up to 800 megabits per second (Mb/s) are supported. Bi-directional communications at a nominal rate of up to 800 Mb/s in each direction, for a composite rate of up to 1600 Mb/s, are supported. The bit-error rate (BER) for each channel, independently of mode of operation, data pattern, and data rate (up to the maximum supported), does not exceed 10−7.
The transmitter utilized in single-ended signaling is a non-inverting three-state CMOS output with digitally controlled AC and DC characteristics. Output levels are either 50-60 ohms to Vdd, 50-60 ohms to Vss, or high impedance. Control is provided to compensate for variations in wafer Process, supply Voltage, and junction Temperature (PVT). Without adjustments, characteristics could vary over a 2:1 range. Output impedance is adjusted with digital controls PVT[30:1]. Of these signals, 15 are used to turn on extra parallel PMOS pullups and the other 15 are used to turn on extra parallel NMOS pulldowns. To improve the linearity of the output impedance to a 5% tolerance, diffused resistors are used in series with the PMOS and NMOS elements. Predriver strengths are adjusted by using the PVT controls, stabilizing output slew rates and power supply current transients.
Although the receiver module, depicted in
In system mode the output data comes from the pfssd through the A0 input of the TX2L driver to the pad. Mode_B is held at 0. The PVT impedance control bus is active and adjusts the output impedance of the TX2L driver. In system mode the input data comes from the C4 pad to the PAD input of the BAPF I/O cell. The data is fed through the canceller to the comparator and out the Z/ZN pin to the pfssr. EXTEST and mode_control are 0 which selects the midpoint voltage to the comparator to come from the common mode reference. The tri-state control for the driver is controlled by the TS pin which is driven by a boundary scan enable cell. In system mode the driver and receiver are enabled at the same time so the BSR enable is always 1. Thus providing simultaneous bidirectional signals. The RI and DI signals are tied to a 1.
One test mode, the Manufacturing LSSD test mode, uses a reduced pin count testing technique where only 64 pins are connected to the tester. All pins not connected to the tester need to be 'io-wrap' compatible, where the data is applied to the pad by the IO cell driver and wrapped back into the die through the IO cell receiver. For LSSD testing the mode_control signal is held to a 1 for two purposes. The first purpose is to provide a local input reference from the MIDBIAS circuit to the comparator. This way the common mode reference does not need to be relied on to be stable. The second purpose is to disable the canceller. With the canceller disabled the data from the pad flows directly through the canceller without being corrupted by the 'BIT' data from the driver. In LSSD testing the value of the Mode_B signal is controlled by the automatic test pattern generator (ATPG). Mode_B selects drive data from the BSR or the pfssd. The data is driven to the pad and captured in the BSR through the ZBSR signal and/or the pfssr through the comparator.
In yet another test mode, the JTAG EXTEST mode, the BAPF is treated as a single ended bidirectional pin. The RI and DI signals are tied to a 1 at the board level. This gives tri-state control to the BSR_ENAB circuit. When the EXTEST instruction is loaded in the jtag instruction register the EXTEST and Mode_B signals are active (1). The EXTEST signal causes the output impedance of the driver to remain at a mid-point value, disable the canceller, and select the complement reference value to come from the local MIDBIAS circuit. The Mode_B signal selects drive data to come from the BSR. The boundary scan patterns determines whether the pin should act as an input or output by loading the proper data into BSR_ENAB. If it's an output the driver is enabled by the BSR_ENAB and data from A1 is applied to PAD. If it's an input the driver is tri-stated by the BSR_ENAB and receive data on the PAD is captured in the BSR through the ZBSR path.
Differential Signaling
The differential signaling format is binary NRZ (BNRZ). Two wires are used as a channel for each data bit in the bus, with true data placed on one of the wires, and complemented data placed on the second wire. (Unless otherwise stated, voltage values hereafter are referred to as differential voltages, measured on the true wire with respect to the complement wire.) Two data transmitters, fed by true and complement data and connected separately to the true and complement wires, are utilized for each data bit. Each transmitter has the same characteristics as those described for single-ended signaling. Consequently, for each transmitter operating, for example, into a quiescent termination to mid-rail, the observed voltage swing on each wire has nominal values of V dd/4 and 3Vdd/4. The corresponding differential values are Vdd/2 (true wire voltage=3Vdd/4, complement wire voltage=Vdd/4) and −Vdd/2 (true wire voltage=V dd/4, complement wire voltage=3Vdd/4). The positive voltage is utilized for a data 1, and the negative voltage is utilized for a data 0. For bidirectional signaling, the observed channel signal assumes nominal values of −V dd (Left and Right data both 0), 0 V (Left and Right opposite values), and V dd (Left and Right both 1). Differential signaling transmitters and receivers are required to communicate over differential, unidirectional channels. PFSSD/PFSSR transmitters sending signals to SSD/SSR receivers provide source termination nominally matched to the transmission line. SSD receivers also provide matched termination, the PFSSD/PFSSR transmitters produce nominal voltage levels on each wire of Vdd/4 and 3Vdd/4 (Vdd refers to the Vdd used for PFSSD/PFSSR circuitry, nominally 1.8 V), corresponding to differential voltages of �Vdd/2. The positive voltage is utilized for a data 1 and the negative voltage is utilized for a data 0. PFSSD/PFSSR receivers provide a resistive termination nominally matched to the transmission line. This equivalent resistance is connected, on both true and complement input wires, to a quiescent voltage equal to Vdd (1.8V) for operation in system mode, however in test mode, both true and complement inputs are terminated to ground. Single-ended voltage levels are approximately 1.8V and 1V in steady state, corresponding to differential values of �0.8V. The positive value is used to represent data 1, and the negative value represents data 0. Proper termination, nominally matched to the transmission line, is provided by connection to a PFSSD/PFSSR transmitter. In order to accommodate variations due to process characteristics, voltage, and temperature, automatic setting of termination resistance is provided. This setting is updated periodically to provide tracking of variations. The BER for each channel, independently of mode of operation, data pattern, and data rate, does not exceed 10−7.
The two differential transmitters are non-inverting three-state CMOS output with digitally controlled AC and DC characteristics. Output levels are either 50-60 ohms to Vdd, 50-60 ohms to Vss, or high impedance.
Although the receiver module, depicted in
In system mode the output data comes from the pfssd through the A0 input of both the TX2L drivers to the PAD and PADN. Mode_B is held at 0. The PVT impedance control bus is active and adjusts the output impedance of the TX2L driver. In system mode the input data comes from the C4 pad to the PAD input of the BDAPF I/O cell. The data is fed through the canceller to the differential comparator and out the Z and ZN pin to the pfssr. The tri-state control for the driver is controlled by the TS pin which is driven by a boundary scan enable cell. In system mode the driver and receiver are enabled at the same time so the BSR enable is always 1. Thus providing simultaneous bidirectional signals. The RI and DI signals are tied to a 1. The LT signals are tied to a 0.
One test mode, the Manufacturing LSSD test mode, uses a reduced pin count testing technique where only 64 pins are connected to the tester. All pins not connected to the tester need to be 'io-wrap' compatible, where the data is applied to the pad by the IO cell driver and wrapped back into the die through the IO cell receiver. In LSSD test mode each side of the differential driver is treated as a single ended bidirectional pin. In LSSD testing the value of the Mode_B signal is controlled by the automatic test pattern generator (ATPG). Mode_B selects drive data from the BSR or the pfssd. The data is driven to the pad and captured in the BSR through the ZBSR signal and/or the pfssr through the comparator.
In yet another test mode, the JTAG EXTEST mode, each side of the differential BDAPF is treated as a single ended bidirectional pin. The RI and DI signals are tied to a 1 at the board level. This gives tri-state control to the BSR_ENAB circuit. When the EXTEST instruction is loaded in the jtag instruction register the EXTEST and Mode_B signals are active (1). The EXTEST signal causes the output impedance of the driver to remain at a mid-point value, and disable the canceller. The Mode_B signal selects drive data to come from the BSR. The boundary scan patterns determine whether the pin should act as an input or output by loading the proper data into BSR_ENAB. If it's an output the driver is enabled by the BSR_ENAB and data from A1 is applied to PAD. If it's and input the driver is tri-stated by the BSR_ENAB and receive data on the PAD and PADN is captured in the BSR through the ZBSR and ZNBSR paths.
In one embodiment, supported data rates for some given lengths and types of channels are as follows: 1600 Mb/s/signal for 10″ printed circuit board (PCB) if signaling is bidirectional and single-ended; 1600 Mb/s/signal for 16″ PCB+3m cable if signaling is bidirectional and differential; 800 Mb/s/signal for 16″ PCB+3m cable if signaling is unidirectional and differential, likewise for 16″ PCB+5m cable. However, it can be appreciated by those skilled in the art that supported data rates can vary within logical bounds and still fit within the scope and breadth of the present invention. Furthermore, any channel interconnects for data lines are not conceptually limited in width or type. Various interconnect types include Ethernet, microstrip, glass, twisted pair or any other type of waveguide. Details of specific embodiments of package, PCB, and cable/connector requirements are included below.
The PCB characteristic impedance for single ended channel PCB traces should be 55�10%, and for differential channel PCB trances, should be 110�10%. Length matching of PCB nets is also required to reduce skew. The PCB length should be matched to within 50 mils for all nets within a data channel. PFSSR bit deskew circuitry can compensate for 3 bit times of skew for PFSSD/R to PFSSD/R communication, and 1 bit time of skew for SSD/R to PFSSD/R communications. The channel clock net requires a quadrature shift from padding of 4.0″ on the transmit side (clock signals are unidirectional) for a negative clock launch out of the PFSSD. The dc resistance of the PCB can be minimized by plating signal layers up from half-ounce copper 0.7 mil in thickness to 1.0 mil in thickness. The PCB should be routed to avoid resonant lengths between two connected devices on the same PCB. These are the lengths at which a data bit has time to propagate down to the load and return to the driver at the time the next data bit is being sent.
The above detailed description is illustrative. It is not intended to be restrictive. Upon review of the above detailed description, one skilled in the art will no doubt see many other embodiments within the full scope and nature of the invention. Therefore, the full scope of the invention should be construed only in reference to the language of the claims and all equivalents thereof.
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|U.S. Classification
|375/257, 333/32, 333/155
|International Classification
|Cooperative Classification
|European Classification
|May 9, 2001
Owner name: SILICON GRAPHICS, INC., CALIFORNIA
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|Aug 20, 2001
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text:
Member Since: February 7, 2013
Country: United States
Added a driver for this display to the object-oriented arduino platform; Cosa. Please find example code at https://github.com/mikaelpatel/Cosa/blob/master/examples/Drivers/CosaPCD8544/CosaPCD8544.ino and source code at https://github.com/mikaelpatel/Cosa/blob/master/Cosa/IOStream/Driver/PCD8544.hh.
This driver supports iostream output with form feed, new line and backspace. It also supports drawing of icons and histogram bars. See the example code.
Have fun.
No public wish lists :(


text:
Underwater grasses covered 79,675 acres of the Chesapeake Bay and its tidal rivers in 2010, a decrease of 6239 acres from the previous year. This represents about 43 percent of the 185,000-acre baywide abundance goal, according to data from scientists with the Chesapeake Bay Program. Despite being a 7 percent decrease from 85,914 acres in 2009, these most recent estimates still rank as the 3rd highest baywide acreage since 1984, when the Virginia Institute of Marine Science (VIMS) began conducting its annual aerial survey.
"We were pleased that grasses remain healthy and abundant in two areas where nutrient pollution was reduced: the upper Potomac River and Susquehanna Flats," said Bob Orth, scientist with the Virginia Institute of Marine Science and leader of the baywide annual survey. "However, the overall condition for bay grasses remains one of concern with many areas still having few, if any, grass beds. In 2010, our big concern arose in the lower Bay where eelgrass appeared to suffer another setback from the incredibly hot summertime temperatures. Since we had mapped those beds prior to the heat wave, losses there are not reflected in our final figures."
Bay grasses -- also called submerged aquatic vegetation (SAV) -- are critical to the Bay ecosystem. They provide habitat and nursery grounds for fish and blue crabs, serve as food for animals such as turtles and waterfowl, clear the water by reducing wave action, absorb excess nutrients and reduce shoreline erosion. They are also an excellent measure of the Bay's overall condition because their health is closely linked to water quality. Annual acreage of grasses is estimated through an aerial survey, which is flown from late spring to early fall.
Orth continued, "We believe the really hot summer temperatures in the early part of the growing season may have just cooked the grasses before we were able to map them, e.g. parts of the Honga River. The changes also occurred in areas dominated by just one species, widgeongrass, which has been shown to be a boom or bust species. 2010 may have been the hottest on record but it was those summer time temperatures in June that may have tipped the scale for SAV in some areas."
Grass Numbers by the Zones
Annual bay grass acreage estimates are an indication of the Bay's response to pollution control efforts, such as implementation of agricultural best management practices (BMPs) and upgrades to wastewater treatment plants. Homeowners throughout the Bay region help bay grasses and overall water quality by using landscaping techniques that keep excess nutrients from flowing downstream where they can harm nearby streams and eventually the Bay. Local watershed groups and online resources such as CBP's "Plant More Plants" campaign – plantmoreplants.com – can offer people more information on how to get started.
"Even with the decreases in the 2010 bay grass coverage, the patterns are similar to previous years," said Lee Karrh, living resources assessment chief with the Maryland Department of Natural Resources and chair of the Bay Program's SAV Workgroup. "Many of the fresh and low salinity areas have very high abundances, including sixteen that have reached their restoration targets, However, the saltier parts of the Bay continue to struggle, with most areas well below the restoration goals, with only the mouth of the James River exceeding the goal."
For additional information about the aerial survey and an interactive map of SAV acreage throughout the Chesapeake Bay, visit www.vims.edu/bio/sav/. For more information about the status of underwater bay grasses in the Chesapeake Bay, visit www.chesapeakebay.net/status_baygrasses.aspx.


text:
Girlie Night: Love Actually
Rated R, 135 min. Directed by Richard Curtis. Starring Hugh Grant, Emma Thompson, Alan Rickman, Bill Nighy, Liam Neeson, Colin Firth, Keira Knightley, Martine McCutcheon, Billy Bob Thornton, Joanna Page and Rowan Atkinson.
This merry skein of loves lost and found is set in holiday-season London. Read a full review of Love Actually.No current showings of this film.