text: Journal of Low Power Electronics and Applications http://www.mdpi.com/journal/jlpea Latest open access articles published in J. Low Power Electron. Appl. at http://www.mdpi.com/journal/jlpea http://www.mdpi.com/2079-9268/7/2/16 Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas requiring near-sensor processing, including elaboration of biosignals. Parallel near-threshold computing is emerging as an approach to achieve significant improvements in energy efficiency while overcoming the performance degradation typical of low-voltage operations. In this paper, we demonstrate the capabilities of the PULP (Parallel Ultra-Low Power) platform on an algorithm for seizure detection, representative of a wide range of EEG signal processing applications. Starting from the 28-nm FD-SOI (Fully Depleted Silicon On Insulator) technology implementation of the third embodiment of the PULP architecture, we analyze the energy-efficient implementation of the seizure detection algorithm on PULP. The proposed parallel implementation exploits the dynamic voltage and frequency scaling capabilities, as well as the embedded power knobs of the PULP platform, reducing energy consumption for a seizure detection by up to 10× with respect to a sequential implementation at the nominal supply voltage and by 4.2× with respect to a sequential implementation with voltage scaling. Moreover, we analyze the trans-precision optimization of the algorithm on PULP, by means of a hybrid fixed- and floating-point implementation. This approach reduces the energy consumption by up to 43% with respect to the plain fixed-point and floating-point implementations, leveraging the requirements in terms of the precision of the kernels composing the processing chain to improve energy efficiency. Thanks to the proposed architecture and system-level approach for optimization, we demonstrate that PULP reduces energy consumption by up to 140× with respect to commercial low-power microcontrollers, being able to satisfy the real-time constraints typical of bio-medical applications, breaking the barrier of microwatts for a 50-ms complete seizure detection and a few milliwatts for a 5-ms detection latency on a fully-programmable architecture. Journal of Low Power Electronics and Applications 2017-06-11 7 2 Article 10.3390/jlpea7020016 16 2079-9268 2017-06-11 doi: 10.3390/jlpea7020016 Fabio Montagna Simone Benatti Davide Rossi http://www.mdpi.com/2079-9268/7/2/15 This paper proposes a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator's magnetic flux and torque by detecting the three-phase current, three-phase voltage, and rotor speed, and eliminates the ripples in the torque and flux by using a fuzzy controller and predictive scheme. The Verilog hardware description language was used to implement the hardware architecture, and the ASIC was fabricated by the Taiwan Semiconductor Manufacturing Company through a 0.18-μm 1P6M CMOS process that involved a cell-based design method. The measurements revealed that the proposed fuzzy PDTC ASIC of the three-phase induction motor yielded a test coverage of 96.03%, fault coverage of 95.06%, chip area of 1.81 × 1.81 mm2, and power consumption of 296 mW, at an operating frequency of 50 MHz and a supply voltage of 1.8 V. Journal of Low Power Electronics and Applications 2017-06-10 7 2 Article 10.3390/jlpea7020015 15 2079-9268 2017-06-10 doi: 10.3390/jlpea7020015 Guo-Ming Sung Wei-Yu Wang Wen-Sheng Lin Chih-Ping Yu http://www.mdpi.com/2079-9268/7/2/14 The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. Much research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power-saving techniques for engineers and researchers. Journal of Low Power Electronics and Applications 2017-05-29 7 2 Article 10.3390/jlpea7020014 14 2079-9268 2017-05-29 doi: 10.3390/jlpea7020014 Emmanuel Ofori-Attah Washington Bhebhe Michael Agyeman http://www.mdpi.com/2079-9268/7/2/13 Static schedules for systems can lead to an inefficient usage of the resources, because the system's behavior cannot be adapted at runtime. To improve the runtime system performance in current time-triggered Multi-Processor System on Chip (MPSoC), a dynamic reaction to events is performed locally on the cores. The effects of this optimization can be increased by coordinating the changes globally. To perform such global changes, a consistent view on the system state is needed, on which to base the adaptation decisions. This paper proposes such an interactive consistency protocol with low impact on the system w.r.t. latency and overhead. We show that an energy optimizing adaptation controlled by the protocol can enable a system to save up to 43% compared to a system without adaptation. Journal of Low Power Electronics and Applications 2017-05-28 7 2 Article 10.3390/jlpea7020013 13 2079-9268 2017-05-28 doi: 10.3390/jlpea7020013 Alina Lenz Roman Obermaisser http://www.mdpi.com/2079-9268/7/2/12 Video segmentation based on the Mixture of Gaussian (MoG) algorithm is widely used in video processing systems, and hardware implementations have been proposed in the past years. Most previous work focused on high-performance custom design of the MoG algorithm to meet real-time requirement of high-frame-rate high-resolution video segmentation tasks. This paper focuses on the System-on-Chip (SoC) design and the priority is SoC integration of the system for flexibility/adaptability, while at the same time, custom design of the original MoG algorithm is included. To maximally retain the accuracy of the MoG algorithm for best segmentation performance, we minimally modified the MoG algorithm for hardware implementation at the cost of hardware resources. The MoG algorithm is custom-implemented as a hardware IP (Intellectual Property), which is then integrated within an SoC platform together with other video processing components, so that some key control parameters can be configured on-line, which makes the video segmentation system most suitable for different scenarios. The proposed implementation has been demonstrated and tested on a Xilinx Spartan-3A DSP Video Starter Board. Experiment results show that under a clock frequency of 25 MHz, this design meets the real-time requirement for VGA resolution (640 × 480) at 30 fps (frame-per-second). Journal of Low Power Electronics and Applications 2017-05-18 7 2 Article 10.3390/jlpea7020012 12 2079-9268 2017-05-18 doi: 10.3390/jlpea7020012 Peng Li Hua Tang http://www.mdpi.com/2079-9268/7/2/11 This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit's architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage. Journal of Low Power Electronics and Applications 2017-05-11 7 2 Article 10.3390/jlpea7020011 11 2079-9268 2017-05-11 doi: 10.3390/jlpea7020011 Soundous Chairat Edith Beigne Ivan Miro-Panades Marc Belleville http://www.mdpi.com/2079-9268/7/2/10 Robotic controllers have to execute various complex independent tasks repeatedly. Massive processing power is required by the motion controllers to compute the solution of these computationally intensive algorithms. General-purpose graphics processing unit (GPGPU)-enabled mobile phones can be leveraged for acceleration of these motion controllers. Embedded GPUs can replace several dedicated computing boards by a single powerful and less power-consuming GPU. In this paper, the inverse kinematic algorithm based numeric controllers is proposed and realized using the GPGPU of a handheld mobile device. This work is the extension of a desktop GPU-accelerated robotic controller presented at DAS'16 where the comparative analysis of different sequential and concurrent controllers is discussed. First of all, the inverse kinematic algorithm is sequentially realized using Arduino-Due microcontroller and the field-programmable gate array (FPGA) is used for its parallel implementation. Execution speeds of these controllers are compared with two different GPGPU architectures (Nvidia Quadro K2200 and Nvidia Shield K1 Tablet), programmed with Compute Unified Device Architecture (CUDA) computing language. Experimental data shows that the proposed mobile platform-based scheme outperforms the FPGA by 5× and boasts a 100× speedup over the Arduino-based sequential implementation. Journal of Low Power Electronics and Applications 2017-05-05 7 2 Article 10.3390/jlpea7020010 10 2079-9268 2017-05-05 doi: 10.3390/jlpea7020010 Syed Rizvi Gianpiero Cabodi Denis Patti Muhammad Gulzar http://www.mdpi.com/2079-9268/7/2/9 Carrier aggregation is one of the key features to increase the data rate given a scarce bandwidth spectrum. This paper describes the design of a high performance receiver suitable for carrier aggregation in LTE-Advanced and future 5 G standards. The proposed architecture is versatile to support legacy mode (single carrier), inter-band carrier aggregation, and intra-band carrier aggregation. Performance with carrier-aggregation support is as good as legacy receivers. Contradicting requirements of high linearity and the low noise is satisfied with the single-gm receiver architecture in addition to supporting carrier aggregation. The proposed cascode-shutoff low-noise trans-conductance amplifier (LNTA) achieves 57.1 dB voltage gain, 1.76 dB NF (noise figure) , and - 6 . 7 dBm IIP3 (Third-order intercept point) with the power consumption of 21.3 mW in the intra-band carrier aggregation scenario. With legacy mode, the same receiver signal path achieves 56.6 dB voltage gain, 1.33 dB NF, and - 6 . 2 dBm IIP3 with a low power consumption of 7.4 mW. Journal of Low Power Electronics and Applications 2017-05-01 7 2 Article 10.3390/jlpea7020009 9 2079-9268 2017-05-01 doi: 10.3390/jlpea7020009 Jusung Kim Bon-Hyun Ku Sanghun Lee Sungchan Kim Keunkwan Ryu http://www.mdpi.com/2079-9268/7/2/7 Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology. Journal of Low Power Electronics and Applications 2017-04-28 7 2 Article 10.3390/jlpea7020007 7 2079-9268 2017-04-28 doi: 10.3390/jlpea7020007 Mahshid Naeini Sreedharan Dass Chia Ooi http://www.mdpi.com/2079-9268/7/2/8 To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications' execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45 % (or 50 % ) in 3D NoCs (or WiNoCs). Journal of Low Power Electronics and Applications 2017-04-26 7 2 Article 10.3390/jlpea7020008 8 2079-9268 2017-04-26 doi: 10.3390/jlpea7020008 Michael Opoku Agyeman Wen Zong Alex Yakovlev Kin-Fai Tong Terrence Mak http://www.mdpi.com/2079-9268/7/2/6 To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art. Journal of Low Power Electronics and Applications 2017-03-29 7 2 Article 10.3390/jlpea7020006 6 2079-9268 2017-03-29 doi: 10.3390/jlpea7020006 Fernando Gutierrez http://www.mdpi.com/2079-9268/7/1/5 Thread-level and data-level parallel architectures have become the design of choice in many of today's energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory subsystem than scalar architectures, making memory latency and bandwidth critical in their overall efficiency. Data reuse exploration aims at reducing the pressure on the memory subsystem by exploiting the temporal locality in data accesses. In this paper, we investigate the effects on performance and energy from a data reuse methodology combined with parallelization and vectorization in multi- and many-core processors. As a test case, a full-search motion estimation kernel is evaluated on Intel® CoreTM i7-4700K (Haswell) and i7-2600K (Sandy Bridge) multi-core processors, as well as on an Intel® Xeon PhiTM many-core processor (Knights Landing) with Streaming Single Instruction Multiple Data (SIMD) Extensions (SSE) and Advanced Vector Extensions (AVX) instruction sets. Results using a single-threaded execution on the Haswell and Sandy Bridge systems show that performance and EDP (Energy Delay Product) can be improved through data reuse transformations on the scalar code by a factor of ≈3× and ≈6×, respectively. Compared to scalar code without data reuse optimization, the SSE/AVX2 version achieves ≈10×/17× better performance and ≈92×/307× better EDP, respectively. These results can be improved by 10% to 15% using data reuse techniques. Finally, the most optimized version using data reuse and AVX512 achieves a speedup of ≈35× and an EDP improvement of ≈1192× on the Xeon Phi system. While single-threaded execution serves as a common reference point for all architectures to analyze the effects of data reuse on both scalar and vector codes, scalability with thread count is also discussed in the paper. Journal of Low Power Electronics and Applications 2017-02-22 7 1 Article 10.3390/jlpea7010005 5 2079-9268 2017-02-22 doi: 10.3390/jlpea7010005 Abdullah Al Hasib Lasse Natvig Per Kjeldsberg Juan Cebrián http://www.mdpi.com/2079-9268/7/1/4 Over the last few decades, computer-aided engineering (CAE) tools have been developed and improved in order to ensure a short time-to-market in the chip design business. Up to now, these design tools do not yet support an integrated design strategy for the development of side-channel-resistant hardware implementations. In order to close this gap, a novel framework named AMASIVE (Adaptable Modular Autonomous SIde-Channel Vulnerability Evaluator) was developed. It supports the designer in implementing devices hardened against power attacks by exploiting novel security-driven synthesis methods. The article at hand can be seen as the second of the two contributions that address the AMASIVE framework. While the first one describes how the framework automatically detects vulnerabilities against power attacks, the second one explains how a design can be hardened in an automatic way by means of appropriate countermeasures, which are tailored to the identified weaknesses. In addition to the theoretical introduction of the fundamental concepts, we demonstrate an application to the hardening of a complete hardware implementation of the block cipher PRESENT. Journal of Low Power Electronics and Applications 2017-02-08 7 1 Article 10.3390/jlpea7010004 4 2079-9268 2017-02-08 doi: 10.3390/jlpea7010004 Sorin Huss Oliver Stein http://www.mdpi.com/2079-9268/7/1/3 This work implements and evaluates the recent complete addition formulae for the prime order elliptic curves of Renes, Costello and Batina on an FPGA platform. We implement three different versions:(1) an unprotected architecture; (2) an architecture protected through coordinate randomization; and (3) an architecture with both coordinate randomization and scalar splitting in place. The evaluation is done through timing analysis and test vector leakage assessment (TVLA). The results show that applying an increasing level of countermeasures leads to an increasing resistance against side-channel attacks. This is the first work looking into side-channel security issues of hardware implementations of the complete formulae. Journal of Low Power Electronics and Applications 2017-02-01 7 1 Article 10.3390/jlpea7010003 3 2079-9268 2017-02-01 doi: 10.3390/jlpea7010003 Łukasz Chmielewski Pedro Massolino Jo Vliegen Lejla Batina Nele Mentens http://www.mdpi.com/2079-9268/7/1/2 Physically unclonable functions (PUFs) have been touted for their inherent resistance to invasive attacks and low cost in providing a hardware root of trust for various security applications. SRAM PUFs in particular are popular in industry for key/ID generation. Due to intrinsic process variations, SRAM cells, ideally, tend to have the same start-up behavior. SRAM PUFs exploit this start-up behavior. Unfortunately, not all SRAM cells exhibit reliable start-up behavior due to noise susceptibility. Hence, design enhancements are needed for improving reliability. Some of the proposed enhancements in literature include fuzzy extraction, error-correcting codes and voting mechanisms. All enhancements involve a trade-off between area/power/performance overhead and PUF reliability. This paper presents a design enhancement technique for reliability that improves upon previous solutions. We present simulation results to quantify improvement in SRAM PUF reliability and efficiency. The proposed technique is shown to generate a 128-bit key in ≤0.2 μ s at an area estimate of 4538 μ m 2 with error rate as low as 10 − 6 for intrinsic error probability of 15%. Journal of Low Power Electronics and Applications 2017-01-12 7 1 Article 10.3390/jlpea7010002 2 2079-9268 2017-01-12 doi: 10.3390/jlpea7010002 Arunkumar Vijayakumar Vinay Patil Sandip Kundu http://www.mdpi.com/2079-9268/7/1/1 The editors of Journal of Low Power Electronics and Applications would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2016.[...] Journal of Low Power Electronics and Applications 2017-01-10 7 1 Editorial 10.3390/jlpea7010001 1 2079-9268 2017-01-10 doi: 10.3390/jlpea7010001 Journal of Low Power Electronics and Applications Editorial Office http://www.mdpi.com/2079-9268/6/4/20 With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs). Journal of Low Power Electronics and Applications 2016-10-20 6 4 Review 10.3390/jlpea6040020 20 2079-9268 2016-10-20 doi: 10.3390/jlpea6040020 Katrine Lundager Behzad Zeinali Mohammad Tohidi Jens Madsen Farshad Moradi http://www.mdpi.com/2079-9268/6/4/19 In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer. Journal of Low Power Electronics and Applications 2016-09-30 6 4 Article 10.3390/jlpea6040019 19 2079-9268 2016-09-30 doi: 10.3390/jlpea6040019 Sebastien Sollier Julie Widiez Gweltaz Gaudin Frederic Mazen Thierry Baron Mickail Martin Marie-Christine Roure Pascal Besson Christophe Morales Elodie Beche Frank Fournel Sylvie Favier Amelie Salaun Patrice Gergaud Maryline Cordeau Christellle Veytizou Ludovic Ecarnot Daniel Delprat Ionut Radu Thomas Signamarcheix http://www.mdpi.com/2079-9268/6/3/18 This work presents a fully integrated hybrid inductive/capacitive converter maintaining high efficiency for a load range of 2 mA to 140 mA (70×) suitable for the dynamic voltage scaling (DVS) based loads. This high efficiency is achieved by using an inductive converter for higher loads (15–140 mA, 0.50–0.9 V) and a capacitive converter for lighter loads (2–5 mA, 0.40–0.55 V) with a 50 mV hysteresis margin. A digital state machine activates the appropriate converter based on the power efficiency and enables the converter hand-over. The functional feasibility of implementing digital circuits as representative loads under the inductor is shown thereby increasing the peak converter power density from 0.387 W/mm2 to 4.1 W/mm2 with only a minor hit on the efficiency. The maximum measured efficiency is achieved in inductive mode of operation and decreases from 76.4% to 71% when digital circuits are present under the inductor. The design was fabricated in IBM's 32 nm SOI technology. Journal of Low Power Electronics and Applications 2016-09-09 6 3 Article 10.3390/jlpea6030018 18 2079-9268 2016-09-09 doi: 10.3390/jlpea6030018 Sudhir Kudva Saurabh Chaubey Ramesh Harjani http://www.mdpi.com/2079-9268/6/3/17 The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have multiple power modes. Achieving high conversion efficiency within the DC–DC converter that supplies these processors is critical since energy consumption of the DC–DC/processor system is proportional to the DC–DC converter efficiency. The DC–DC converter must maintain high efficiency over a large load range generated from the multiple power modes of the processor. This paper presents a fully integrated step-down self-oscillating switched-capacitor DC–DC converter that is capable of meeting these challenges. The area of the converter is 0.0104 mm2 and is designed in 28 nm ultra-thin body and buried oxide fully-depleted SOI (UTBB FD-SOI). Back-gate biasing within FD-SOI is utilized to increase the load power range of the converter. With an input of 1 V and output of 460 mV, measurements of the converter show a minimum efficiency of 75% for 79 nW to 200 µW loads. Measurements with an off-chip NT processor load show efficiency up to 86%. The converter's large load power range and high efficiency make it an excellent fit for energy-constrained processors. Journal of Low Power Electronics and Applications 2016-09-08 6 3 Article 10.3390/jlpea6030017 17 2079-9268 2016-09-08 doi: 10.3390/jlpea6030017 Matthew Turnquist Markus Hiienkari Jani Mäkipää Lauri Koskinen http://www.mdpi.com/2079-9268/6/3/16 Static Random Access Memory (SRAM) has recently been developed into a physical unclonable function (PUF) for generating chip-unique signatures for hardware cryptography. The most compelling issue in designing a good SRAM-based PUF (SPUF) is that while maximizing the mismatches between the transistors in the cross-coupled inverters improves the quality of the SPUF, this ironically also gives rise to increased memory read/write failures. For this reason, the memory cells of existing SPUFs cannot be reused as storage elements, which increases the overheads of cryptographic system where long signatures and high-density storage are both required. This paper presents a novel design methodology for dual-mode SRAM cell optimization. The design conflicts are resolved by using word-line voltage modulation, dynamic voltage scaling, negative bit-line and adaptive body bias techniques to compensate for reliability degradation due to transistor downsizing. The augmented circuit-level techniques expand the design space to achieve a good solution to fulfill several otherwise contradicting key design qualities for both modes of operation, as evinced by our statistical analysis and simulation results based on complementary metal–oxide–semiconductor (CMOS) 45 nm bulk Predictive Technology Model. Journal of Low Power Electronics and Applications 2016-08-24 6 3 Article 10.3390/jlpea6030016 16 2079-9268 2016-08-24 doi: 10.3390/jlpea6030016 Chip-Hong Chang Chao Liu Le Zhang Zhi Kong http://www.mdpi.com/2079-9268/6/3/15 This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits. Journal of Low Power Electronics and Applications 2016-08-12 6 3 Article 10.3390/jlpea6030015 15 2079-9268 2016-08-12 doi: 10.3390/jlpea6030015 Yu Bai Mingjie Lin http://www.mdpi.com/2079-9268/6/3/14 We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, resulting both from using highly configurable devices, as well as from the advancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system. The system overhead requirements require simple email handling, available over almost all network systems with no additional requirements. The system is empowered through large-scale Field Programmable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present a range of experimentally measured examples illustrating the range of user interfacing available for the remote user. Journal of Low Power Electronics and Applications 2016-07-28 6 3 Article 10.3390/jlpea6030014 14 2079-9268 2016-07-28 doi: 10.3390/jlpea6030014 Jennifer Hasler Sahil Shah Sihwan Kim Ishan Lal Michelle Collins http://www.mdpi.com/2079-9268/6/3/13 This paper presents scaling of Floating-Gate (FG) devices, and the resulting implication to large-scale Field Programmable Analog Arrays (FPAA) systems. The properties of FG circuits and systems in one technology (e.g., 350 nm CMOS) are experimentally shown to roughly translate to FG circuits in scaled down processes in a way predictable through MOSFET physics concepts. Scaling FG devices results in higher frequency response, (e.g., FPAA fabric) as well as lower parasitic capacitance and lower power consumption. FPAA architectures, limited to 50–100 MHz frequency ranges could be envisioned to operate at 500 MHz–1 GHz for 130 nm line widths, and operate around 4 GHz for 40 nm line widths. Journal of Low Power Electronics and Applications 2016-07-27 6 3 Article 10.3390/jlpea6030013 13 2079-9268 2016-07-27 doi: 10.3390/jlpea6030013 Jennifer Hasler Sihwan Kim Farhan Adil http://www.mdpi.com/2079-9268/6/3/12 Energy efficiency is a primary design goal for future green wireless communication technologies. Multiple-input multiple-output (MIMO) schemes have been proposed in the literature to improve the throughput of communication systems, and they are expected to play a prominent role in the upcoming fifth generation (5G) standard. This paper presents a novel, high-efficiency MIMO decoder based on the K-Best algorithm with lattice reduction. We have designed a novel hardware architecture for this decoder, which was implemented using 32 nm standard CMOS technology. Our results show that the proposed decoder can achieve on average a four-fold reduction in the power costs compared to recently published designs for 5G networks. The throughput of the design is 506 Mbits/s, which is comparable to existing designs. Journal of Low Power Electronics and Applications 2016-07-14 6 3 Article 10.3390/jlpea6030012 12 2079-9268 2016-07-14 doi: 10.3390/jlpea6030012 Basel Halak Mohammed El-Hajjar Ogeen Toma Zhuofan Cheng http://www.mdpi.com/2079-9268/6/3/11 This paper presents an ultra-low swing level converter with integrated charge pumps that shows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-V output. Lowering the input allowable for a single-ended level converter supports energy harvesting systems that need to use very low voltages. Journal of Low Power Electronics and Applications 2016-06-23 6 3 Article 10.3390/jlpea6030011 11 2079-9268 2016-06-23 doi: 10.3390/jlpea6030011 Yu Huang Aatmesh Shrivastava Laura Barnes Benton Calhoun http://www.mdpi.com/2079-9268/6/2/10 We propose a fully on-chip CMOS temperature sensor in which a sub-threshold (sub-VT) proportional-to-absolute-temperature (PTAT) current element starves a current-controlled oscillator (CCO). Sub-VT design enables ultra-low-power operation of this temperature sensor. However, such circuits are highly sensitive to process variations, thereby causing varying circuit currents from die to die. We propose a bit-weighted current mirror (BWCM) architecture to resist the effect of process-induced variation in the PTAT current. The analog core constituting the PTAT, the CCO, and the BWCM is operational down to 0.2 V supply voltage. A digital block operational at 0.5 V converts the temperature information into a digital code that can be processed and used by other components in a system-on-chip (SoC). The proposed temperature sensor system also supports resolution-power trade-off for Internet-of-things (IoT) applications with different sampling rates and energy needs. The system power consumption is 23 nW and the maximum temperature inaccuracy is +1.5/−1.7 °C from 0 °C to 100 °C with a two-point calibration. The temperature sensor system was designed in a 130 nm CMOS technology and its total area is 250 × 250 μm2. Journal of Low Power Electronics and Applications 2016-06-15 6 2 Article 10.3390/jlpea6020010 10 2079-9268 2016-06-15 doi: 10.3390/jlpea6020010 Divya Akella Kamakshi Aatmesh Shrivastava Benton Calhoun http://www.mdpi.com/2079-9268/6/2/9 In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling ("more Moore") and functional scaling to enhance on-chip functionality ("more than Moore"). Journal of Low Power Electronics and Applications 2016-06-14 6 2 Review 10.3390/jlpea6020009 9 2079-9268 2016-06-14 doi: 10.3390/jlpea6020009 Nadine Collaert http://www.mdpi.com/2079-9268/6/2/8 We present an ultra-low power (ULP) 1 KB SRAM macro for Internet of Things (IoT) battery-less systems-on-chip (SoCs) operating under varying energy harvesting conditions. The unique combination of features within this array allows battery-less SoCs to retain important information for a significantly longer period of time when energy harvesting conditions are poor. The array uses 8T high-threshold (high-VT) static random access memory (SRAM) cells with word line boosting to eliminate write failures coupled with a read-before-write scheme to address read-disturb in half-selected cells. Due to the reduced on current in high-VT devices, read word line boosting is implemented to improve the drive strength of the read buffer, and to eliminate read failures. Leakage currents through the unselected cells during a read operation is addressed by boosting the footer virtual VSS (VVSS) of the read port to the supply voltage (VDD). To reduce the power consumption of instruction memories in battery-less SoCs, two features were utilized in this array: a read burst mode is used when reading consecutive addresses to reduce the read energy, and instructions with higher percentages of "1" data are defined since reading a "1" is less costly than reading a "0" in 8T cells. The proposed array can operate at a wide range of supply voltages (350–700 mV) and has two ULP modes: standby with retention (1.5 pW/bit) and shutdown without retention (0.13 pW/bit). Aggressive power gating of all peripherals during the standby state reduces the array power consumption down to 12.29 nW/KB at 320 mV with data retention. Compared to previously published 8T arrays, the proposed design provides the lowest standby power. The complete shutdown of the array allows further reduction down to 1.09 nW/KB and is suitable for reducing the power consumption of data memories in battery-less SoCs. The measured results from a commercial 130 nm chip show that the proposed array consumes a minimum of 6.24 pJ/access with a 17.16 nW standby power at 400 mV. The read burst mode allows up to 22% reduction in energy/access at 400 mV. Journal of Low Power Electronics and Applications 2016-05-24 6 2 Article 10.3390/jlpea6020008 8 2079-9268 2016-05-24 doi: 10.3390/jlpea6020008 Farah Yahya Harsh Patel James Boley Arijit Banerjee Benton Calhoun http://www.mdpi.com/2079-9268/6/2/7 We propose a fully on-chip clock-source system in which an ultra-low-power diode-based temperature-uncompensated oscillator (OSCdiode) serves as the main clock source and frequency locks to a higher-power temperature-compensated oscillator (OSCcmp) that is disabled after each locking event to save power. The locking allows the stability of the uncompensated oscillator to stay within the stability bound of the compensated design. This paper demonstrates the functionality of a locking controller that uses a periodic (counter-based) scheme implemented on-chip and a prediction (temperature-drift-based) scheme. The flexible clock source platform is validated in a 130 nm CMOS technology. In the demonstrated system, it achieves an effective average temperature stability of 7 ppm/°C in the human body temperature range from 20 °C to 40 °C with a power consumption of 36 nW at 0.7 V. It achieves a frequency range of 12 kHz to 150 kHz at 0.7 V. Journal of Low Power Electronics and Applications 2016-05-16 6 2 Article 10.3390/jlpea6020007 7 2079-9268 2016-05-16 doi: 10.3390/jlpea6020007 Divya Kamakshi Aatmesh Shrivastava Chuhong Duan Benton Calhoun http://www.mdpi.com/2079-9268/6/2/6 Observations of peak and average currents are important for designed circuits, as faulty circuits have abnormal peaks and average currents. Using current bounds to detect faulty chips is a comparatively innovative idea, and many advanced schemes without them use it as a component in statistical outlier analysis. However, these previous research works have focused on the discussion of the testing impact without a proposed method to define reference current bounds to find faulty chips. A software framework is proposed to synthesize high-performance, power-performance optimized, noise-immune, and low-power circuits with current-bound estimations for testing. This framework offers a rapid methodology to quickly screen potential faulty chips by using the peak and average current bounds for different purposed circuits. The proposed estimation technique generates suitable reference current bounds from transistor threshold voltage and size adjustments. The SPICE-level simulation leads to the most accurate estimations. However, such simulations are not feasible for a large digital circuit. Hence, this work proposes constructing a feasible gate-level software framework for large digital circuits that will serve all of simulation purposes. In comparison with transistor-level Nanosim simulations, the proposed gate-level simulation framework has a margin of error of less than 2% in the peak current, and the computation time is 334 times faster. Journal of Low Power Electronics and Applications 2016-05-06 6 2 Article 10.3390/jlpea6020006 6 2079-9268 2016-05-06 doi: 10.3390/jlpea6020006 Ching-Hwa Cheng http://www.mdpi.com/2079-9268/6/2/5 With increasing core-count, the cache demand of modern processors has also increased. However, due to strict area/power budgets and presence of poor data-locality workloads, blindly scaling cache capacity is both infeasible and ineffective. Cache bypassing is a promising technique to increase effective cache capacity without incurring power/area costs of a larger sized cache. However, injudicious use of cache bypassing can lead to bandwidth congestion and increased miss-rate and hence, intelligent techniques are required to harness its full potential. This paper presents a survey of cache bypassing techniques for CPUs, GPUs and CPU-GPU heterogeneous systems, and for caches designed with SRAM, non-volatile memory (NVM) and die-stacked DRAM. By classifying the techniques based on key parameters, it underscores their differences and similarities. We hope that this paper will provide insights into cache bypassing techniques and associated tradeoffs and will be useful for computer architects, system designers and other researchers. Journal of Low Power Electronics and Applications 2016-04-28 6 2 Article 10.3390/jlpea6020005 5 2079-9268 2016-04-28 doi: 10.3390/jlpea6020005 Sparsh Mittal http://www.mdpi.com/2079-9268/6/1/4 An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power. Journal of Low Power Electronics and Applications 2016-03-11 6 1 Article 10.3390/jlpea6010004 4 2079-9268 2016-03-11 doi: 10.3390/jlpea6010004 Ali Fazli Yeknami http://www.mdpi.com/2079-9268/6/1/3 This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source programs similar to MATLAB/Simulink) that converts the high-level block description by the user to blif format (sci2blif), which acts as an input to the modified VPR tool, including the code v p r 2 s w c s , encoding the specific platform through specific architecture files, resulting in a targetable switch list on the resulting configurable analog–digital system. The resulting tool uses an analog and mixed-signal library of components, enabling users and future researchers access to the basic analog operations/computations that are possible. Journal of Low Power Electronics and Applications 2016-02-04 6 1 Article 10.3390/jlpea6010003 3 2079-9268 2016-02-04 doi: 10.3390/jlpea6010003 Michelle Collins Jennifer Hasler Suma George http://www.mdpi.com/2079-9268/6/1/2 The editors of Journal of Low Power Electronics and Applications would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2015. [...] Journal of Low Power Electronics and Applications 2016-01-26 6 1 Editorial 10.3390/jlpea6010002 2 2079-9268 2016-01-26 doi: 10.3390/jlpea6010002 Journal Of Low Power Electronics And Applications Editorial Office http://www.mdpi.com/2079-9268/6/1/1 While non-volatile memories (NVMs) provide high-density and low-leakage, they also have low write-endurance. This, along with the write-variation introduced by the cache management policies, can lead to very small cache lifetime. In this paper, we propose ENLIVE, a technique for ENhancing the LIfetime of non-Volatile cachEs. Our technique uses a small SRAM (static random access memory) storage, called HotStore. ENLIVE detects frequently written blocks and transfers them to the HotStore so that they can be accessed with smaller latency and energy. This also reduces the number of writes to the NVM cache which improves its lifetime. We present microarchitectural schemes for managing the HotStore. Simulations have been performed using an x86-64 simulator and benchmarks from SPEC2006 suite. We observe that ENLIVE provides higher improvement in lifetime and better performance and energy efficiency than two state-of-the-art techniques for improving NVM cache lifetime. ENLIVE provides 8.47×, 14.67× and 15.79× improvement in lifetime or two, four and eight core systems, respectively. In addition, it works well for a range of system and algorithm parameters and incurs only small overhead. Journal of Low Power Electronics and Applications 2016-01-18 6 1 Article 10.3390/jlpea6010001 1 2079-9268 2016-01-18 doi: 10.3390/jlpea6010001 Sparsh Mittal Jeffrey Vetter http://www.mdpi.com/2079-9268/5/4/274 This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an LC oscillator, an envelope detector and a base-band amplifier. To optimize the trade-off between RF performances and power consumption, the cross-coupled based oscillator is biased in moderate inversion region. The proof of concept is implemented in a 65 nm CMOS technology and is intended for the 2.4 GHz ISM band. With a supply voltage of 0.5 V, the demodulator consumes 120 μW and demonstrates the demodulation of OOK and FSK at a data rate of 500 kbps. Journal of Low Power Electronics and Applications 2015-11-30 5 4 Article 10.3390/jlpea5040274 274 290 2079-9268 2015-11-30 doi: 10.3390/jlpea5040274 Thierry Taris Hassène Kraimia Didier Belot Yann Deval http://www.mdpi.com/2079-9268/5/4/257 In this work, a Radio Frequency (RF) Energy Harvester comprised of a differential Radio Frequency-to-Direct Current (RF-DC) converter realized in ST130 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology and a customized broadband Printed Circuit Board (PCB) antenna with inductive coupling feeding is presented. Experimental results show that the system can work with different carrier frequencies and thanks to its reconfigurable architecture the proposed converter is able to provide a regulated output voltage of 2 V over a 14 dB of RF input power range. The conversion efficiency of the whole system peaks at 18% under normal outdoor working conditions. Journal of Low Power Electronics and Applications 2015-11-27 5 4 Article 10.3390/jlpea5040257 257 273 2079-9268 2015-11-27 doi: 10.3390/jlpea5040257 Alessandro Bertacchini Luca Larcher Moreno Maini Luca Vincetti Stefano Scorcioni http://www.mdpi.com/2079-9268/5/4/234 This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-μm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits. Journal of Low Power Electronics and Applications 2015-11-09 5 4 Article 10.3390/jlpea5040234 234 256 2079-9268 2015-11-09 doi: 10.3390/jlpea5040234 Yifei Liu Paul Furth Wei Tang http://www.mdpi.com/2079-9268/5/4/216 This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss. The proposed architecture is analytically proved to be SEL resistant, and by extension, proved to be SEU resistant. The SEL/SEU resistant version of a 3-stage full-word pipelined NCL 4 × 4 unsigned multiplier was implemented using the IBM cmrf8sf 130 nm 1.2 V process at the transistor level and simulated exhaustively with SEL fault injection to validate the proposed architectures. Compared with the original version, the SEL/SEU resilient version has 1.31× speed overhead, 2.74× area overhead, and 2.79× energy per operation overhead. Journal of Low Power Electronics and Applications 2015-10-20 5 4 Article 10.3390/jlpea5040216 216 233 2079-9268 2015-10-20 doi: 10.3390/jlpea5040216 Liang Zhou Scott Smith Jia Di http://www.mdpi.com/2079-9268/5/3/183 As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU. Journal of Low Power Electronics and Applications 2015-09-11 5 3 Article 10.3390/jlpea5030183 183 215 2079-9268 2015-09-11 doi: 10.3390/jlpea5030183 Ravi Nair Scott Smith Jia Di http://www.mdpi.com/2079-9268/5/3/165 This paper presents a cross-layer framework in order to design and optimize energy-efficient cache memories made of deeply-scaled FinFET devices. The proposed design framework spans device, circuit and architecture levels and considers both super- and near-threshold modes of operation. Initially, at the device-level, seven FinFET devices on a 7-nm process technology are designed in which only one geometry-related parameter (e.g., fin width, gate length, gate underlap) is changed per device. Next, at the circuit-level, standard 6T and 8T SRAM cells made of these 7-nm FinFET devices are characterized and compared in terms of static noise margin, access latency, leakage power consumption, etc. Finally, cache memories with all different combinations of devices and SRAM cells are evaluated at the architecture-level using a modified version of the CACTI tool with FinFET support and other considerations for deeply-scaled technologies. Using this design framework, it is observed that L1 cache memory made of longer channel FinFET devices operating at the near-threshold regime achieves the minimum energy operation point. Journal of Low Power Electronics and Applications 2015-08-11 5 3 Article 10.3390/jlpea5030165 165 182 2079-9268 2015-08-11 doi: 10.3390/jlpea5030165 Alireza Shafaei Shuang Chen Yanzhi Wang Massoud Pedram http://www.mdpi.com/2079-9268/5/3/151 This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper) by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable) materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT) era. Journal of Low Power Electronics and Applications 2015-06-25 5 3 Article 10.3390/jlpea5030151 151 164 2079-9268 2015-06-25 doi: 10.3390/jlpea5030151 Federico Alimenti Chiara Mariotti Valentina Palazzi Marco Virili Giulia Orecchini Paolo Mezzanotte Luca Roselli http://www.mdpi.com/2079-9268/5/2/130 The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed "SEU Hardening Incorporating Extreme Low Power Bitcell Design" (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel "cut-off" network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell's robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined. Journal of Low Power Electronics and Applications 2015-06-23 5 2 Article 10.3390/jlpea5020130 130 150 2079-9268 2015-06-23 doi: 10.3390/jlpea5020130 Oron Chertkow Ariel Pescovsky Lior Atias Alexander Fish http://www.mdpi.com/2079-9268/5/2/116 In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips. Journal of Low Power Electronics and Applications 2015-05-25 5 2 Article 10.3390/jlpea5020116 116 129 2079-9268 2015-05-25 doi: 10.3390/jlpea5020116 Yasuhiro Ogasahara Tadashi Nakagawa Toshihiro Sekigawa Toshiyuki Tsutsumi Hanpei Koike http://www.mdpi.com/2079-9268/5/2/101 In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices. Journal of Low Power Electronics and Applications 2015-05-21 5 2 Article 10.3390/jlpea5020101 101 115 2079-9268 2015-05-21 doi: 10.3390/jlpea5020101 Yin-Nien Chen Chien-Ju Chen Ming-Long Fan Vita Hu Pin Su Ching-Te Chuang http://www.mdpi.com/2079-9268/5/2/81 This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster. Journal of Low Power Electronics and Applications 2015-05-18 5 2 Article 10.3390/jlpea5020081 81 100 2079-9268 2015-05-18 doi: 10.3390/jlpea5020081 Liang Zhou Ravi Parameswaran Farhad Parsan Scott Smith Jia Di http://www.mdpi.com/2079-9268/5/2/69 This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT, VB = VG), and the enhanced DT (eDT, VB = kVG) configurations, focusing on low power applications. It is shown that the underlap devices present a lower off-state current (IOFF at VG = 0 V), lower subthreshold swing (S), lower gate-induced drain leakage (GIDL), higher transconductance over drain current (gm/ID) ratio and higher intrinsic voltage gain (|AV|) due to their longer effective channel length in weak inversion and lower lateral electric field, while the eDT mode presents higher on-state current (ION) with the same IOFF, lower S, higher maximum transconductance (gmmax), lower threshold voltage (VT), higher gm/ID ratio and higher |AV| due to the dynamically reduced threshold voltage and stronger transversal electric field. Journal of Low Power Electronics and Applications 2015-04-29 5 2 Article 10.3390/jlpea5020069 69 80 2079-9268 2015-04-29 doi: 10.3390/jlpea5020069 Katia Sasaki Marc Aoulaiche Eddy Simoen Cor Claeys Joao Martino http://www.mdpi.com/2079-9268/5/2/57 To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. Journal of Low Power Electronics and Applications 2015-04-17 5 2 Article 10.3390/jlpea5020057 57 68 2079-9268 2015-04-17 doi: 10.3390/jlpea5020057 Markus Hiienkari Jukka Teittinen Lauri Koskinen Matthew Turnquist Jani Mäkipää Arto Rantala Matti Sopanen Mikko Kaltiokallio http://www.mdpi.com/2079-9268/5/2/38 Modern systems-on-chip (SoCs) today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs) use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM) is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture. Journal of Low Power Electronics and Applications 2015-03-27 5 2 Article 10.3390/jlpea5020038 38 56 2079-9268 2015-03-27 doi: 10.3390/jlpea5020038 Maurizio Palesi Mario Collotta Andrea Mineo Vincenzo Catania http://www.mdpi.com/2079-9268/5/1/3 This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circuit with a very limited number of measurements in order to minimize the total measurement efforts and time. We prove that, through sparsity-promoting transform domain regularization and by strategically integrating compressive sensing with Bayesian learning, more than 98% of the overall measurement accuracy can be achieved with fewer than 10% of measurements as required in a conventional approach that uses exhaustive measurements. Furthermore, we illustrate that the obtained criticality results can be utilized to selectively fortify large-scale digital circuits for operation with narrow voltage headrooms and in the presence of soft-errors rising at near threshold voltage levels, without excessive hardware overheads. Our numerical simulation results have shown that, by optimally allocating only 10% circuit redundancy, for some large-scale benchmark circuits, we can achieve more than a three-times reduction in its overall error probability, whereas if randomly distributing such 10% hardware resource, less than 2% improvements in the target circuit's overall robustness will be observed. Finally, we conjecture that our proposed approach can be readily applied to estimate other essential properties of digital circuits that are critical to designing and analyzing them, such as the observability measure in reliability analysis and the path delay estimation in stochastic timing analysis. The only key requirement of our proposed methodology is that these global information fields exhibit a certain degree of smoothness, which is universally true for almost any physical phenomenon. Journal of Low Power Electronics and Applications 2015-03-13 5 1 Article 10.3390/jlpea5010003 3 37 2079-9268 2015-03-13 doi: 10.3390/jlpea5010003 Mohammed Alawad Ronald DeMara Mingjie Lin http://www.mdpi.com/2079-9268/5/1/1 The editors of the Journal of Low Power Electronics and Applications would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2014:[...] Journal of Low Power Electronics and Applications 2015-01-09 5 1 Editorial 10.3390/jlpea5010001 1 2 2079-9268 2015-01-09 doi: 10.3390/jlpea5010001 Journal of Low Power Electronics Applications Editorial Office http://www.mdpi.com/2079-9268/4/4/304 Thermal sensors (TS) are essential for achieving optimized performance and reliability in the era of nanoscale microprocessor and system on chip (SoC). Compiling with the low-power and small die area of the mobile computing, the presented TS supports a wide range of sampling frequencies with an optimized power envelope. The TS supports up to 45 K samples/s, low average power consumption, as low as 20 μW, and small core Si area of 0.013 mm2. Advanced circuit techniques are used in order to overcome process variability, ensuring inaccuracy lower than ±2 °C without any calibration. All this makes the presented thermal sensor a cost-effective, low-power solution for 22 nm nanoscale digital process technology. Journal of Low Power Electronics and Applications 2014-12-09 4 4 Article 10.3390/jlpea4040304 304 316 2079-9268 2014-12-09 doi: 10.3390/jlpea4040304 Ro'ee Eitan Ariel Cohen http://www.mdpi.com/2079-9268/4/4/292 An ultra-low voltage sixth-order low pass filter topology, suitable for sensing the T-wave signal in an electrocardiogram (ECG), is presented in this paper. This is realized using a cascade connection of second-order building blocks constructed from a sinh-domain two-integrator loop. The performance of the filter has been evaluated using the Cadence Analog Design Environment and the design kit provided by the Austria Mikro Systeme (AMS) 0.35-µm CMOS process. The power consumption of filters was 7.21 nW, while a total harmonic distortion (THD) level of 4% was observed for an input signal of 220 pA. The RMS value of the input referred noise was 0.43 pA, and the simulated value of the dynamic range (DR) was 51.1 dB. A comparison with already published counterparts shows that the proposed topology offers the benefits of 0.5-V supply voltage operation and significantly improved power efficiency. Journal of Low Power Electronics and Applications 2014-11-26 4 4 Article 10.3390/jlpea4040292 292 303 2079-9268 2014-11-26 doi: 10.3390/jlpea4040292 Panagiotis Bertsias Costas Psychalinos http://www.mdpi.com/2079-9268/4/4/268 When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics. Journal of Low Power Electronics and Applications 2014-11-14 4 4 Review 10.3390/jlpea4040268 268 291 2079-9268 2014-11-14 doi: 10.3390/jlpea4040268 Eric Bharucha Hassan Sepehrian Benoit Gosselin http://www.mdpi.com/2079-9268/4/3/252 A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ΔVT . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10-6, with up to 21 unreliable bits. Journal of Low Power Electronics and Applications 2014-09-12 4 3 Article 10.3390/jlpea4030252 252 267 2079-9268 2014-09-12 doi: 10.3390/jlpea4030252 Jonathan Bolus Benton Calhoun Travis Blalock http://www.mdpi.com/2079-9268/4/3/231 Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory. Increases in leakage as a percentage of total power particularly impact applications that rarely access memory. This study examines how the benefits of scratchpad memories have changed in newer processes, based on the measured performance of the WIMS (Wireless Integrated MicroSystems) microcontroller implemented in 180- and 65-nm processes and upon simulations of this microcontroller implemented in a 32-nm process. The results demonstrate that scratchpad memories will continue to improve the power dissipation of many applications, given the leakage anticipated in the foreseeable future. Journal of Low Power Electronics and Applications 2014-09-09 4 3 Article 10.3390/jlpea4030231 231 251 2079-9268 2014-09-09 doi: 10.3390/jlpea4030231 Bennion Redd Spencer Kellis Nathaniel Gaskin Richard Brown http://www.mdpi.com/2079-9268/4/3/214 Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC. Journal of Low Power Electronics and Applications 2014-08-28 4 3 Article 10.3390/jlpea4030214 214 230 2079-9268 2014-08-28 doi: 10.3390/jlpea4030214 Luís Cargnini Lionel Torres Raphael Brum Sophiane Senni Gilles Sassatelli http://www.mdpi.com/2079-9268/4/3/201 The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the transconductance over drain current (gm/Id) method is preferable for variability studies. It is demonstrated that the subthreshold drain current variability in short channel devices cannot be described by threshold voltage variability. It is suggested to include the effective body factor incorporating short channel effects in order to properly model the subthreshold drain current variability. Journal of Low Power Electronics and Applications 2014-07-16 4 3 Article 10.3390/jlpea4030201 201 213 2079-9268 2014-07-16 doi: 10.3390/jlpea4030201 Sergej Makovejev Babak Esfeh François Andrieu Jean-Pierre Raskin Denis Flandre Valeriya Kilchytska http://www.mdpi.com/2079-9268/4/3/188 Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed. Journal of Low Power Electronics and Applications 2014-07-15 4 3 Article 10.3390/jlpea4030188 188 200 2079-9268 2014-07-15 doi: 10.3390/jlpea4030188 Masakazu Hioki Chao Ma Takashi Kawanami Yasuhiro Ogasahara Tadashi Nakagawa Toshihiro Sekigawa Toshiyuki Tsutsumi Hanpei Koike http://www.mdpi.com/2079-9268/4/3/168 Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range. Journal of Low Power Electronics and Applications 2014-07-07 4 3 Review 10.3390/jlpea4030168 168 187 2079-9268 2014-07-07 doi: 10.3390/jlpea4030168 Guerric de Streel David Bol http://www.mdpi.com/2079-9268/4/2/153 The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials. Journal of Low Power Electronics and Applications 2014-06-20 4 2 Article 10.3390/jlpea4020153 153 167 2079-9268 2014-06-20 doi: 10.3390/jlpea4020153 Yongxun Liu Toshihide Nabatame Takashi Matsukawa Kazuhiko Endo Shinichi O'uchi Junichi Tsukada Hiromi Yamauchi Yuki Ishikawa Wataru Mizubayashi Yukinori Morita Shinji Migita Hiroyuki Ota Toyohiro Chikyow Meishoku Masahara http://www.mdpi.com/2079-9268/4/2/138 Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors. Journal of Low Power Electronics and Applications 2014-06-11 4 2 Article 10.3390/jlpea4020138 138 152 2079-9268 2014-06-11 doi: 10.3390/jlpea4020138 Alexander Shapiro Eby Friedman http://www.mdpi.com/2079-9268/4/2/119 Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors. Journal of Low Power Electronics and Applications 2014-05-27 4 2 Review 10.3390/jlpea4020119 119 137 2079-9268 2014-05-27 doi: 10.3390/jlpea4020119 Arijit Banerjee Benton Calhoun http://www.mdpi.com/2079-9268/4/2/110 A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin). Journal of Low Power Electronics and Applications 2014-05-23 4 2 Article 10.3390/jlpea4020110 110 118 2079-9268 2014-05-23 doi: 10.3390/jlpea4020110 Kazuhiko Endo Shinji Migita Yuki Ishikawa Takashi Matsukawa Shin-ichi O'uchi Junji Tsukada Wataru Mizubayashi Yukinori Morita Hiroyuki Ota Hitomi Yamauchi Meishoku Masahara http://www.mdpi.com/2079-9268/4/2/90 With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS) and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works. Journal of Low Power Electronics and Applications 2014-05-07 4 2 Article 10.3390/jlpea4020090 90 109 2079-9268 2014-05-07 doi: 10.3390/jlpea4020090 Jian Lin Albert Cheng Wei Song http://www.mdpi.com/2079-9268/4/2/77 For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation. Journal of Low Power Electronics and Applications 2014-05-05 4 2 Article 10.3390/jlpea4020077 77 89 2079-9268 2014-05-05 doi: 10.3390/jlpea4020077 Pooja Batra Spyridon Skordas Douglas LaTulipe Kevin Winstel Chandrasekharan Kothandaraman Ben Himmel Gary Maier Bishan He Deepal Gamage John Golz Wei Lin Tuan Vo Deepika Priyadarshini Alex Hubbard Kristian Cauffman Brown Peethala John Barth Toshiaki Kirihata Troy Graves-Abe Norman Robson Subramanian Iyer http://www.mdpi.com/2079-9268/4/2/65 Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB's features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The "Perpetuum-Mobile" micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era. Journal of Low Power Electronics and Applications 2014-04-24 4 2 Review 10.3390/jlpea4020065 65 76 2079-9268 2014-04-24 doi: 10.3390/jlpea4020065 Nobuyuki Sugii Yoshiki Yamamoto Hideki Makiyama Tomohiro Yamashita Hidekazu Oda Shiro Kamohara Yasuo Yamaguchi Koichiro Ishibashi Tomoko Mizutani Toshiro Hiramoto http://www.mdpi.com/2079-9268/4/1/63 The editors of the Journal of Low Power Electronics and Applications would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2013. [...] Journal of Low Power Electronics and Applications 2014-02-28 4 1 Editorial 10.3390/jlpea4010063 63 64 2079-9268 2014-02-28 doi: 10.3390/jlpea4010063 JLPEA Editorial Office http://www.mdpi.com/2079-9268/4/1/44 We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead. Journal of Low Power Electronics and Applications 2014-02-27 4 1 Article 10.3390/jlpea4010044 44 62 2079-9268 2014-02-27 doi: 10.3390/jlpea4010044 Meilin Zhang Paul Ampadu http://www.mdpi.com/2079-9268/4/1/26 Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in "big data" companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor. Journal of Low Power Electronics and Applications 2014-01-20 4 1 Article 10.3390/jlpea4010026 26 43 2079-9268 2014-01-20 doi: 10.3390/jlpea4010026 Andrey Mokhov Maxim Rykunov Danil Sokolov Alex Yakovlev http://www.mdpi.com/2079-9268/4/1/15 This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from the "source potential floating effect", which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery. Journal of Low Power Electronics and Applications 2014-01-10 4 1 Article 10.3390/jlpea4010015 15 25 2079-9268 2014-01-10 doi: 10.3390/jlpea4010015 Yasuhisa Omura Daiki Sato http://www.mdpi.com/2079-9268/4/1/1 Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. Journal of Low Power Electronics and Applications 2014-01-09 4 1 Article 10.3390/jlpea4010001 1 14 2079-9268 2014-01-09 doi: 10.3390/jlpea4010001 Marc Bocquet Hassen Aziza Weisheng Zhao Yue Zhang Santhosh Onkaraiah Christophe Muller Marina Reyboz Damien Deleruyelle Fabien Clermidy Jean-Michel Portal http://www.mdpi.com/2079-9268/3/4/368 This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1-dimensional reduced order model (ROM) of the switch; the results given by this simplified model are compared to classical CMOS-based, and sub-threshold CMOS-based adiabatic logic circuits. NEMS-based circuits and CMOS-based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency. Journal of Low Power Electronics and Applications 2013-12-16 3 4 Article 10.3390/jlpea3040368 368 384 2079-9268 2013-12-16 doi: 10.3390/jlpea3040368 Samer Houri Christophe Poulain Alexandre Valentian Hervé Fanet http://www.mdpi.com/2079-9268/3/4/337 Tone mapping algorithms are used to adapt captured wide dynamic range (WDR) scenes to the limited dynamic range of available display devices. Although there are several tone mapping algorithms available, most of them require manual tuning of their rendering parameters. In addition, the high complexities of some of these algorithms make it difficult to implement efficient real-time hardware systems. In this work, a real-time hardware implementation of an exponent-based tone mapping algorithm is presented. The algorithm performs a mixture of both global and local compression on colored WDR images. An automatic parameter selector has been proposed for the tone mapping algorithm in order to achieve good tone-mapped images without manual reconfiguration of the algorithm for each WDR image. Both algorithms are described in Verilog and synthesized for a field programmable gate array (FPGA). The hardware architecture employs a combination of parallelism and system pipelining, so as to achieve a high performance in power consumption, hardware resources usage and processing speed. Results show that the hardware architecture produces images of good visual quality that can be compared to software-based tone mapping algorithms. High peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) scores were obtained when the results were compared with output images obtained from software simulations using MATLAB. Journal of Low Power Electronics and Applications 2013-10-29 3 4 Article 10.3390/jlpea3040337 337 367 2079-9268 2013-10-29 doi: 10.3390/jlpea3040337 Chika Ofili Stanislav Glozman Orly Yadid-Pecht http://www.mdpi.com/2079-9268/3/4/300 As portable devices become more ubiquitous, data security in these devices is becoming increasingly important. Traditional circuit design techniques leave otherwise secure systems vulnerable due to the characteristics of the hardware implementation, rather than weaknesses in the security algorithms. These characteristics, called side-channels, are exploitable because they can be measured and correlated with processed data, potentially giving an attacker insight into the device's secret data. Alternative design techniques such as dual-rail asynchronous designs are capable of minimizing these potential side-channels by decoupling them from the data being processed. However, these techniques are either expensive to implement compared to standard designs or leave exploitable imbalances in the dual-rail implementation itself. Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L) offers security by balancing side-channels both in general and between the dual-rail signals themselves, as well as reduction in circuit overhead compared to previous secure design techniques. Results show that the Advanced Encryption Standard (AES) cores designed using MTD3L exhibit similar security to previous secure techniques with substantially less area and energy overhead. Journal of Low Power Electronics and Applications 2013-10-25 3 4 Article 10.3390/jlpea3040300 300 336 2079-9268 2013-10-25 doi: 10.3390/jlpea3040300 Michael Linder Jia Di Scott Smith http://www.mdpi.com/2079-9268/3/3/279 Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-gain, low-noise integrated neuronal amplifier (NA) with the capability of recording local field potentials (LFP) and spike activity is presented. In vitro and in vivo characterizations of the tissue/electrode interface, with equivalent impedance as an electrical model for recording in the LFP band using macro-electrodes for rodents, contribute to the NA design constraints. The NA occupies 0.15 mm2 and dissipates 6.73 µW, and was fabricated using a 0.35 µm CMOS process. Test-bench validation indicates that the NA provides a mid-band gain of 20 dB and achieves a low input-referred noise of 4 µVRMS. Ability of the NA to perform spike recording in test-bench experiments is presented. Additionally, an awake and freely moving rodent setup was used to illustrate the integrated NA ability to record LFPs, paving the pathway for future implantable systems for neuromodulation. Journal of Low Power Electronics and Applications 2013-09-09 3 3 Article 10.3390/jlpea3030279 279 299 2079-9268 2013-09-09 doi: 10.3390/jlpea3030279 Adeline Zbrzeski Noëlle Lewis Francois Rummens Ranu Jung Gilles N'Kaoua Abdelhamid Benazzouz Sylvie Renaud http://www.mdpi.com/2079-9268/3/3/267 A novel low power CMOS imaging system with smart image capture and adaptive complexity 2D-Discrete Cosine Transform (DCT) is proposed. Compared with the existing imaging systems, it involves the smart image capture and image processing stages cooperating together and is very efficient. The type of each 8 × 8 block is determined during the image capture stage, and then input into the DCT block, along with the pixel values. The 2D-DCT calculation has adaptive computation complexity according to block types. Since the block type prediction has been moved to the front end, no extra time or calculation is needed during image processing or image capturing for prediction. The image sensor with block type decision circuit is implemented in TSMC 0.18 µm CMOS technology. The adaptive complexity 2D-DCT compression is implemented based on Cyclone EP1C20F400C8 device. The performance including the image quality of the reconstructed picture and the power consumption of the imaging system are compared to those of traditional CMOS imaging systems to show the benefit of the proposed low power algorithm. According to simulation, up to 46% of power consumption can be saved during 2D DCT calculation without extra loss of image quality for the reconstructed pictures compared with the conventional compression methods. Journal of Low Power Electronics and Applications 2013-08-08 3 3 Article 10.3390/jlpea3030267 267 278 2079-9268 2013-08-08 doi: 10.3390/jlpea3030267 Qing Gao Orly Yadid-Pecht http://www.mdpi.com/2079-9268/3/3/250 The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. The idea is to supply nominal (high) off-chip voltage to the cores which are then "voltage-stacked" to generate the near-threshold (low) voltages based on Kirchhoff's voltage law through charge recycling. However, the effectiveness of this implicit down-conversion is affected by the current imbalance among the cores. The paper presents a design methodology and optimization strategy for highly efficient charge recycling on-chip regulation using a push-pull switched capacitor (SC) circuit. A dual-boundary hysteretic feedback control circuit has been designed for stacked loads. A stacked-voltage domain with its self-regulation capability combined with a SC converter has shown average efficiency of 78%–93% for 2:1 down-conversion with ILoad (max) of 200 mA and workload imbalance varying from 0–100%. Journal of Low Power Electronics and Applications 2013-07-29 3 3 Review 10.3390/jlpea3030250 250 266 2079-9268 2013-07-29 doi: 10.3390/jlpea3030250 Kaushik Mazumdar Mircea Stan http://www.mdpi.com/2079-9268/3/3/233 Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of [1,2] on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this paper, the equivalent N and P networks are derived based on the best and worst case transition times. The slack available in the best-case timing arc is reduced by using smaller transistors on that path, while the timing of the worst-case timing arc is improved by using bigger transistors. The optimization is done such that the overall area remains constant with regard to the area before optimization. Two sizing styles are applied, one is based on both transistor width and length tuning, and the other one is based on width tuning only. Compared to super-threshold libraries, at 0.3 V, the proposed libraries achieve 49% and 89% average cell timing improvement and 55% and 31% power delay product improvement at 40 nm and 90 nm respectively. From ITC (International Test Conference 99) benchmark circuit synthesis results, at 0.3 V the proposed library achieves up to 52% timing improvement and 53% power savings in the 40 nm technology node. Journal of Low Power Electronics and Applications 2013-07-15 3 3 Article 10.3390/jlpea3030233 233 249 2079-9268 2013-07-15 doi: 10.3390/jlpea3030233 Bo Liu Jose de Gyvez Maryam Ashouei http://www.mdpi.com/2079-9268/3/3/215 This paper presents a model of inductor based DC-DC converters that can be used to study the impact of power management techniques such as dynamic voltage and frequency scaling (DVFS). System level power models of low power systems on chip (SoCs) and power management strategies cannot be correctly established without accounting for the associated overhead related to the DC-DC converters that provide regulated power to the system. The proposed model accurately predicts the efficiency of inductor based DC-DC converters with varying topologies and control schemes across a range of output voltage and current loads. It also accounts for the energy and timing overhead associated with the change in the operating condition of the regulator. Since modern SoCs employ power management techniques that vary the voltage and current loads seen by the converter, accurate modeling of the impact on the converter efficiency becomes critical. We use this model to compute the overall cost of two power distribution strategies for a SoC with multiple voltage islands. The proposed model helps us to obtain the energy benefits of a power management technique and can also be used as a basis for comparison between power management techniques or as a tool for design space exploration early in a SoC design cycle. Journal of Low Power Electronics and Applications 2013-06-24 3 3 Review 10.3390/jlpea3030215 215 232 2079-9268 2013-06-24 doi: 10.3390/jlpea3030215 Aatmesh Shrivastava Benton Calhoun http://www.mdpi.com/2079-9268/3/2/194 Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. Manufacturing tolerances make it difficult to match the Energy Harvesting Device (EHD) resonant frequency to the source vibration frequency, and the source vibration frequency may vary with time. Previous work has recognized that it is possible to tune the resonant frequency of an EHD using a tunable, reactive impedance at the output of the device. The present paper develops the theory of electrical tuning, and proposes the Bias-Flip (BF) technique, to implement this tunable, reactive impedance. Journal of Low Power Electronics and Applications 2013-06-18 3 2 Article 10.3390/jlpea3020194 194 214 2079-9268 2013-06-18 doi: 10.3390/jlpea3020194 Jianying Zhao Yogesh Ramadass Jeffrey Lang Jianguo Ma Dennis Buss http://www.mdpi.com/2079-9268/3/2/174 We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in discrete hardware using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Article 10.3390/jlpea3020174 174 193 2079-9268 2013-05-24 doi: 10.3390/jlpea3020174 Adrian Rothenbuhler Thanh Tran Elisa Smith Vishal Saxena Kristy Campbell http://www.mdpi.com/2079-9268/3/2/159 Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking. The circuit enables flexible tuning of the offset voltage. Measurements taken from a 45 nm test chip show the circuit is able to limit the offset to 20 mV. A 16kB SRAM is designed using the auto-zeroing circuit for the sense amps. The reduction in the total read energy and delay is reported for various configurations of the memory. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Article 10.3390/jlpea3020159 159 173 2079-9268 2013-05-24 doi: 10.3390/jlpea3020159 Peter Beshay Joseph Ryan Benton Calhoun http://www.mdpi.com/2079-9268/3/2/114 This paper presents the concept, structural design and implementation of components of a multifunctional sensory network, consisting of a Mobile Robotic Platform (MRP) and stationary multifunctional sensors, which are wirelessly communicating with the MRP. Each section provides the review of the principles of operation and the network components' practical implementation. The analysis is focused on the structure of the robotic platform, sensory network and electronics and on the methods of the environment monitoring and data processing algorithms that provide maximal reliability, flexibility and stable operability of the system. The main aim of this project is the development of the Robotic Nurse (RN)—a 24/7 robotic helper for the hospital nurse personnel. To support long-lasting autonomic operation of the platform, all mechanical, electronic and photonic components were designed to provide minimal weight, size and power consumption, while still providing high operational efficiency, accuracy of measurements and adequateness of the sensor response. The stationary sensors serve as the remote "eyes, ears and noses" of the main MRP. After data acquisition, processing and analysing, the robot activates the mobile platform or specific sensors and cameras. The cross-use of data received from sensors of different types provides high reliability of the system. The key RN capabilities are simultaneous monitoring of physical conditions of a large number of patients and alarming in case of an emergency. The robotic platform Nav-2 exploits innovative principles of any-direction motion with omni-wheels, navigation and environment analysis. It includes an innovative mini-laser, the absorption spectrum analyser and a portable, extremely high signal-to-noise ratio spectrometer with two-dimensional detector array. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Review 10.3390/jlpea3020114 114 158 2079-9268 2013-05-24 doi: 10.3390/jlpea3020114 Igor Peshko Romuald Pawluczyk Dale Wick http://www.mdpi.com/2079-9268/3/2/99 This paper presents a compact structure of recursive discrete Fourier transform (RDFT) with prime factor (PF) and common factor (CF) algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051) and 11.5 (or 0.1176) mW at 25 (or 0.273) MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications. Journal of Low Power Electronics and Applications 2013-05-24 3 2 Article 10.3390/jlpea3020099 99 113 2079-9268 2013-05-24 doi: 10.3390/jlpea3020099 Shin-Chi Lai Yueh-Shu Lee Sheau-Fang Lei http://www.mdpi.com/2079-9268/3/2/73 In this paper, we demonstrate how a network of dendrites can be used to build the state decoding block of a wordspotter similar to a Hidden Markov Model (HMM) classifier structure. We present simulation and experimental data for a single line dendrite and also experimental results for a dendrite-based classifier structure. This work builds on previously demonstrated building blocks of a neural network: the channel, synapses and dendrites using CMOS circuits. These structures can be used for speech and pattern recognition. The computational efficiency of such a system is >10 MMACs/μW as compared to Digital Systems which perform 10 MMACs/mW. Journal of Low Power Electronics and Applications 2013-05-21 3 2 Article 10.3390/jlpea3020073 73 98 2079-9268 2013-05-21 doi: 10.3390/jlpea3020073 Suma George Jennifer Hasler Scott Koziol Stephen Nease Shubha Ramakrishnan http://www.mdpi.com/2079-9268/3/2/54 Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell's retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz. Journal of Low Power Electronics and Applications 2013-04-29 3 2 Article 10.3390/jlpea3020054 54 72 2079-9268 2013-04-29 doi: 10.3390/jlpea3020054 Pascal Meinerzhagen Adam Teman Robert Giterman Andreas Burg Alexander Fish http://www.mdpi.com/2079-9268/3/1/27 Usually Wide Dynamic Range (WDR) sensors that autonomously adjust their integration time to fit intra-scene illumination levels use a separate digital memory unit. This memory contains the data needed for the dynamic range. Motivated by the demands for low power and chip area reduction, we propose a different implementation of the aforementioned WDR algorithm by replacing the external digital memory with an analog in-pixel memory. This memory holds the effective integration time represented by analog encoding voltage (AEV). In addition, we present a "ranging" scheme of configuring the pixel integration time in which the effective integration time is configured at the first half of the frame. This enables a substantial simplification of the pixel control during the rest of the frame and thus allows for a significantly more remarkable DR extension. Furthermore, we present the implementation of "ranging" and AEV concepts on two different designs, which are targeted to reach five and eight decades of DR, respectively. We describe in detail the operation of both systems and provide the post-layout simulation results for the second solution. The simulations show that the second design reaches DR up to 170 dBs. We also provide a comparative analysis in terms of the number of operations per pixel required by our solution and by other widespread WDR algorithms. Based on the calculated results, we conclude that the proposed two designs, using "ranging" and AEV concepts, are attractive, since they obtain a wide dynamic range at high operation speed and low power consumption. Journal of Low Power Electronics and Applications 2013-03-22 3 1 Article 10.3390/jlpea3010027 27 53 2079-9268 2013-03-22 doi: 10.3390/jlpea3010027 Arthur Spivak Alexander Belenky Alexander Fish Orly Yadid-Pecht http://www.mdpi.com/2079-9268/3/1/9 This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS) process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range. Journal of Low Power Electronics and Applications 2013-02-28 3 1 Article 10.3390/jlpea3010009 9 26 2079-9268 2013-02-28 doi: 10.3390/jlpea3010009 Naser Khosro Pour François Krummenacher Maher Kayal http://www.mdpi.com/2079-9268/3/1/1 Loop control is an essential area of electronics engineering that today's professionals need to master. Rather than delving into extensive theory, this practical book focuses on what you really need to know for compensating or stabilizing a given control system. You can turn instantly to practical sections with numerous design examples and ready-made formulas to help you with your projects in the field. You also find coverage of the underpinnings and principles of control loops so you can gain a more complete understanding of the material. This authoritative volume explains how to conduct analysis of control systems and provides extensive details on practical compensators. It helps you measure your system, showing how to verify if a prototype is stable and features enough design margin. Moreover, you learn how to secure high-volume production by bench-verified safety margins. Journal of Low Power Electronics and Applications 2013-01-24 3 1 New Book Received 10.3390/jlpea3010001 1 8 2079-9268 2013-01-24 doi: 10.3390/jlpea3010001 Shu-Kun Lin http://www.mdpi.com/2079-9268/2/4/282 This paper presents an energy efficient bootstrapped CMOS driver to enhance the switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65 nm low-power CMOS technology (VTN ≈ VTP ≈ 0.5 V) indicates that the proposed driver provides a rising-delay improvement of 37%–50% and a falling-delay improvement of 25%–47% at 0.3 V for a loading ranging from a 0 to 24 mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides a rising delay improvement of 20% to 52% and a falling delay improvement of 23%–43% for VDD ranging from 0.3 V to 0.5 V, while consuming about 15% less average power than the conventional bootstrapped driver driving a 16 mm long M6 wire. Journal of Low Power Electronics and Applications 2012-12-12 2 4 Article 10.3390/jlpea2040282 282 300 2079-9268 2012-12-12 doi: 10.3390/jlpea2040282 Chien-Yu Lu Ching-Te Chuang http://www.mdpi.com/2079-9268/2/4/265 This paper reviews the direct connection of sensors to microcontrollers without using any analogue circuit (such as an amplifier or analogue-to-digital converter) in the signal path, thus resulting in a low-cost, lower-power sensor electronic interface. It first discusses the operating principle and explains how resistive and capacitive sensors with different topologies (i.e., single, differential and bridge type) can be directly connected to a microcontroller to build the so-called direct interface circuit. It then shows some applications of the proposed circuits using commercial devices and discusses their performance. Finally, it deals with the power consumption and proposes some design guidelines to reduce the current consumption of such circuits in active mode. Journal of Low Power Electronics and Applications 2012-11-29 2 4 Review 10.3390/jlpea2040265 265 281 2079-9268 2012-11-29 doi: 10.3390/jlpea2040265 Ferran Reverter http://www.mdpi.com/2079-9268/2/4/242 A low power adaptive digital baseband architecture is presented for a low-IF receiver of IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle the worst case conditions. We show that in a 0.13 μm CMOS technology, for an adaptive digital baseband section of the receiver, power saving can be up to 85% (0.49mW against 3.3mW) in favorable interference and signal conditions. The proposed concepts in the design are tested using a receiver test setup where the design is hosted on a FPGA. Journal of Low Power Electronics and Applications 2012-10-23 2 4 Article 10.3390/jlpea2040242 242 264 2079-9268 2012-10-23 doi: 10.3390/jlpea2040242 Satyam Dwivedi Bharadwaj Amrutur Navakanta Bhat http://www.mdpi.com/2079-9268/2/4/211 This paper reports a multi-channel neural spike recording system-on-chip with digital data compression and wireless telemetry. The circuit consists of 16 amplifiers, an analog time-division multiplexer, a single 8 bit analog-to-digital converter, a digital signal compression unit and a wireless transmitter. Although only 16 amplifiers are integrated in our current die version, the whole system is designed to work with 64, demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. Compression of the raw data is achieved by detecting the action potentials (APs) and storing 20 samples for each spike waveform. This compression method retains sufficiently high data quality to allow for single neuron identification (spike sorting). The 400 MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way, a 1:25 Mbit/s data rate is delivered within a limited band of about 3 MHz. The chip is realized in a 0:35 µm AMS CMOS process featuring a 3 V power supply with an area of 3:1 x 2:7 mm2. The achieved transmission range is over 10 m with an overall power consumption for 64 channels of 17:2 mW. This figure translates into a power budget of 269 µW per channel, in line with published results but allowing a larger transmission distance and more efficient bandwidth occupation of the wireless link. The integrated circuit was mounted on a small and light board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries, the system can continuously work for more than 100 hours allowing for long-lasting neural spike recordings. Journal of Low Power Electronics and Applications 2012-09-28 2 4 Article 10.3390/jlpea2040211 211 241 2079-9268 2012-09-28 doi: 10.3390/jlpea2040211 Andrea Bonfanti Maria Ceravolo Guido Zambra Riccardo Gusmeroli Gytis Baranauskas Gian Nicola Angotzi Alessandro Vato Emma Maggiolini Marianna Semprini Alessandro Sottocornola Spinelli Andrea Leonardo Lacaita http://www.mdpi.com/2079-9268/2/4/210 We have found the following error in the title of this article which was recently published in J. Low Power Electron. Appl. [...] Journal of Low Power Electronics and Applications 2012-09-26 2 4 Correction 10.3390/jlpea2040210 210 210 2079-9268 2012-09-26 doi: 10.3390/jlpea2040210 Ameet Chavan Praveen Palakurthi Eric MacDonald Joseph Neff Eric Bozeman http://www.mdpi.com/2079-9268/2/3/197 A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level. Journal of Low Power Electronics and Applications 2012-07-26 2 3 Article 10.3390/jlpea2030197 197 209 2079-9268 2012-07-26 doi: 10.3390/jlpea2030197 Sakkarapani Balagopal Vishal Saxena http://www.mdpi.com/2079-9268/2/2/180 This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV. Journal of Low Power Electronics and Applications 2012-06-06 2 2 Article 10.3390/jlpea2020180 180 196 2079-9268 2012-06-06 doi: 10.3390/jlpea2020180 Jani Mäkipää Matthew J. Turnquist Erkka Laulainen Lauri Koskinen http://www.mdpi.com/2079-9268/2/2/168 A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold ( < Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab's XLP 0.15 μm fully-depleted SOI CMOS technology—a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%. Journal of Low Power Electronics and Applications 2012-05-24 2 2 Article 10.3390/jlpea2020168 168 179 2079-9268 2012-05-24 doi: 10.3390/jlpea2020168 Ameet Chavan Praveen Palakurthi Eric MacDonald Joseph Neff Eric Bozeman http://www.mdpi.com/2079-9268/2/2/155 We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design. Journal of Low Power Electronics and Applications 2012-05-18 2 2 Article 10.3390/jlpea2020155 155 167 2079-9268 2012-05-18 doi: 10.3390/jlpea2020155 Piotr Olejarz Kyoungchul Park Samuel MacNaughton Mehmet R. Dokmeci Sameer Sonkusale