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Anatomy of a Currency Crisis
Hong Kong's stock index fell 10 percent in a single day in late October, and stock markets around the world reverberated in response. In Boston, members of the financial community watched anxiously as stock prices slumped in Athens and São Paulo as well as Seoul and New York. For weeks thereafter, the financial press spewed tales of Asian flu bugs, typhoons, dominoes, and, in a geographically mixed metaphor, herds of gazelles fleeing lions, real and imagined. Some of the commentary was hyperbole; some depicted the episode as a "blessing" for the United States, with increased competition from Southeast Asia "solving" any problem with incipient inflation. According to most early estimates, however, Round One of the Asian crisis (the devaluations sweeping Thailand, the Philippines, Indonesia, and Malaysia in early July) was likely to slow U.S. GDP growth very modestly -- by just one-quarter to one-third of 1 percentage point in 1998. But clearly, events have outrun this assessment. Currencies and asset prices in developing countries remain under pressure; governments continue to take restrictive measures. Our "Goldilocks" world has suddenly become more complicated.
How did we get to this predicament, not three years after the Mexican peso crisis? First, the global policy setting matters. Over the 1990s, the industrial countries have succeeded in bringing inflation below 2 or 3 percent and their fiscal deficits down sharply. In general, tight fiscal policies have been partially offset by relatively accommodative monetary policies. As a result of this policy mix, interest rates have declined to unusually low levels -- especially in Europe and Japan.
Investors seeking higher returns quickly spotted the Southeast Asian countries, which were gradually opening their capital markets to foreigners. As the table shows, these tiger economies were growing fast. By LDC standards, their inflation was moderate and their fiscal positions prudent. Moreover, currency risk must have seemed small since these countries had long pegged or nearly pegged their currencies to the U.S. dollar. Small, open economies sometimes choose to peg their exchange rates, at least for a time, to encourage trade and investment, to anchor domestic prices, and to signal their commitment to sound monetary policies. With these many attractions, Southeast Asia's miracle countries have experienced huge capital inflows in recent years.
Asian Economic Indicators: Half Full or Half Empty?
Investors focused on the Asian tigers' rapid growth and moderate inflation until 1997, when they noted deteriorating current accounts and accumulating foreign debt.
| Real GDP
(% Change)
| Consumer Prices
(% Change)
| Current Account
(% of GDP)
| Foreign Bank
Claims/GDP (%)Ý
| 1994-1997*
Annual avg.
| 1994-1997*
Annual avg.
|End '95
|End '96
|Hong Kong
Ý= Claims of BIS reporting banks.
* = Projection
Source: I.M.F., WORLD ECONOMIC OUTLOOK, October 1997, and INTERNATIONAL FINANCIAL STATISTICS; DRI, Bank for International Settlements, THE MATURITY, SECTORAL AND NATIONALITY DISTRIBUTION OF INTERNATIONAL BANK LENDING, SECOND HALF 1996,
July 1997, and INTERNATIONAL BANKING AND FINANCIAL MARKET DEVELOPMENTS, AUGUST 1997.
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But, with exchange rates fixed, capital inflows to purchase Thai securities or to expand an Indonesian manufacturing plant required that their central banks buy dollars and supply the needed baht or rupiahs, ballooning the money supply. Central bank efforts to offset these flows, by selling government securities, say, raised domestic interest rates and encouraged further inflows. With inflation even modestly above U.S. levels and exchange rates fixed, these countries' products became relatively costly on world markets. Several developments magnified their problem. The 1994 devaluation of the yuan made China more competitive; the yen's slide against the U.S. dollar made matters worse. Finally, Taiwan's entry into the chip market brought a glut in a major regional industry. So when world trade slowed in 1995-96, one of the first signs of trouble for the Asean-4 (Indonesia, Malaysia, the Philippines, and Thailand) was a deterioration in their current account deficits.
Another yellow flag was the rapid expansion of domestic credit, abetted by lax banking supervision and rapid deregulation. In Indonesia, state-owned banking gave way to a system where anyone with $1million or so could open a bank. Because capital controls continued to deter outflows of domestic capital, much of this new credit flowed into misguided real estate investments and industries already burdened with unneeded capacity. In Hong Kong, real estate prices quadrupled in five years, and Malaysia became home to the world's tallest and longest buildings. Throughout the area, newcomers to the auto industry -- national favorites, presidents' relatives, electronics companies, and others -- insisted on pushing their way onto the crowded field. So by late 1996, bank and nonbank borrowers in these countries had taken on large amounts of foreign debt, much of it short-term, denominated in unhedged dollars, and invested in iffy projects.
In retrospect, it seems surprising that the crisis did not occur sooner. The International Monetary Fund and others had been warning of potential trouble in Thailand since early 1996.
Perhaps these warnings came too soon. As a self-styled Cassandra from investment banking noted, anyone heeding his clear-sighted advice in 1996 would have missed many profitable opportunities; his firm did not remove "buy" and "outperformer" labels from Thai banks until February 1997. Although bank lending did slow from 1995's torrid pace in Thailand, the other Aseans generally enjoyed relatively low international borrowing costs through early 1997 and did not face rating downgrades until quite recently.
But finally, in early 1997, the Thai bubble burst. Default by a Thai property company drew the world's attention to the thousands of empty housing units around Bangkok. Estimates of nonperforming loans began to rise, Moody's downgraded credit ratings, and Texas Instruments withdrew from a joint venture. Facing sporadic currency pressures from February on, the Thais tried to defend the baht by raising interest rates, imposing capital controls, and spending $10 billion in reserves.
But once speculators note a long-run conflict between a government's policy goals -- here, saving the currency peg, which required high interest rates, versus saving the banking system, which required low interest rates -- they enjoy a one-way bet; eventually the central bank will run out of reserves. With over $1 trillion in foreign exchange activity each day, even the largest stock of official reserves is puny. When the Thais finally let the baht float on July 2, its value promptly sank 15 percent.
Within days, the markets had turned on the other Asean countries, which analysts had certified as "fundamentally different" from Thailand just weeks before. Even the IMF staff appear to have been genuinely surprised by how widely the Thai crisis spread. By mid-July, all the Aseans had abandoned their exchange rate pegs. Devaluation by a neighbor or two greatly reduces the stigma of following suit. Furthermore, these countries compete in many markets and could not afford to be left behind. The IMF-led $17 billion rescue package for Thailand did little to calm the markets, and the Asean currencies continued their erratic descent through the summer and fall.
The crisis then swept on to north Asia and Latin America. Once Taiwan released its dollar on October 17, the markets set out to test the determination of the Hong Kong Monetary Authority (HKMA) to defend its currency board and dollar peg. On October 23, the HKMA created a liquidity squeeze that drove overnight interest rates briefly above 250 percent. The shock deflated prices in Hong Kong's real estate and other asset markets and the Hang Seng index fell 10 percent in a day. This sharp decline triggered stock market reactions worldwide. While U.S. and European markets soon recovered, emerging markets generally remain nervous. As of early December, Asian markets are widely down 15 to 60 percent from the start of the year. Key Latin markets fell 10 to 25 percent in late October, but later rebounded and are well up for the year.
More fundamentally, the perceived risk of investing in LDC markets has surged. So interest rates generally remain above early 1997 levels, and currencies are under pressure. At one extreme, in early December, the Thai baht, the Indonesian rupiah, and the Korean won were 40 to 50 percent below their year-end 1996 levels versus the dollar. The Taiwan and Singapore dollars were down just 12 to 15 percent from the start of the year.
For these very open economies, sharp currency depreciations represent supply shocks akin to a large oil price increase -- these depreciations are likely to spur inflation and slow output growth simultaneously. The price of essential imports rises abruptly, creating a surge in inflation. Like a tax increase, it also absorbs funds that might otherwise be spent on domestic products. In addition, many borrowers have unhedged dollar liabilities that are suddenly more expensive in local currency terms; the resulting bankruptcies weaken already fragile banking systems and further dampen domestic demand. Developing a balanced policy response is not easy.
As is typical, the IMF rescue programs for Thailand and Indonesia stress slowing inflation to preserve the long-run competitive benefits of a devaluation and to restore financial stability. They also call for the government to strengthen its fiscal position and to shore up the banking system -- by closing or merging failed banks and by requiring improved accounting practices and disclosure.
To IMF critics like Harvard's Jeffrey Sachs, this approach gives too much weight to restoring price stability versus supporting employment and output. Keeping interest rates high also prolongs asset-price deflation in real estate and in other markets, and the ensuing defaults compound banking system problems.
With the Japanese auto makers all closing their Thai factories for the rest of the year, and Indonesian construction workers being laid off by the thousands, many analysts now forecast that Indonesia and Thailand will face significant recessions next year. Neighboring economies will likely stagnate -- in part because of their own restrictive policies, and in part because these countries do 30 to 50 percent of their trade with each other. Most analysts agree, however, that the long-run fundamentals in these countries remain attractive. So the IMF hopes to see a quick, V-shaped recession and recovery in Thailand and Indonesia, like that in Mexico.
For the United States, the direct impact of slow growth in Asia should be relatively modest. As mentioned above, most analysts forecast that the Southeast Asian phase of the crisis would deduct one-quarter to one-third of 1 percentage point from GDP growth in 1998. The impact is expected to come largely through declining net exports. At the end of 1996, investments in developing Asia plus Hong Kong and Singapore accounted for less than 2 percent of U.S. commercial bank, pension fund, and mutual fund assets. By contrast, the Asean-4 accounted for 4 percent of our exports. With Hong Kong, Singapore, Taiwan, and Korea, the share was 15 percent.
Southeast Asia's problems will affect Japan more seriously. The Asean-4 account for 12 percent of Japan's exports; with Korea, Hong Kong, and Singapore, the troubled Asian economies account for a third of Japan's trade. Thus, stage one of the crisis is expected to cut Japan's already unsatisfactory growth by one-half to three-quarters of 1 percentage point in 1998. In addition, the Japanese hold a large share of total bank loans to Asean borrowers. Although loans to developing Asia, Hong Kong and Singapore represent just 2 percent of the Japanese banks' total assets, the banks do not disclose data that would permit us to assess the impact of the crisis on their bad loan problem.
But individual banks could be exposed. And, without full disclosure of a bank's potential losses, lenders tend to leap to the worst conclusion. Thus, fears about the possible impact of the crisis have led to sharp declines in Japanese equity prices, with bank stock prices leading the way. Because Japanese banks count unrealized capital gains in their equity holdings as part of their required capital base, declines in the Nikkei can force a contraction of credit. Indeed, once the Nikkei falls below 16,000, as it has on several occasions since October 31, several major Japanese banks must take steps to reduce their outstanding loans.
Since markets don't know about not kicking a fellow when he is down, international lenders are charging a premium on loans to the Japanese banks. At this writing, for the first time in post-war history, a major Japanese bank has failed, as have a second bank and two brokerage houses. Japan is, of course, this country's second largest foreign market, accounting for 10 percent of U.S. exports.
The above estimates do not include the impact of the deteriorating situation in Korea or spillover effects in Latin America, where Argentina, Brazil, and Mexico absorb 13 percent of U.S. exports. And spillover is occurring. To defend its currency, the real, Brazil has recently announced a budget expected to reduce GDP growth next year from an anticipated 4 percent to 1 percent or less. In Korea, the world's eleventh largest economy, a string of conglomerate bankruptcies has led to a banking crisis resembling Japan's. With Korean institutions facing a growing liquidity crisis, the government sought and got a $57 billion IMF loan package to help it pay off short-term dollar-denominated debt and strengthen the country's banking system. But new questions about the size of the task and Korea's commitment to reform led to new pressures on the won.
In time, the attributes that once made the tiger economies "miraculous" should reassert themselves. Strengthened by the reforms impelled by the current crisis, these countries should resume above-average growth. It could take several years, however, for them to achieve recent levels of domestic demand, price stability, and investor confidence.
Progress on trade liberalization may also turn out to be more difficult because of Southeast Asia's currency crisis. Granting the president authority to negotiate trade pacts on a "fast track" basis was politically impossible this year. (Under "fast track," Congress could approve or reject the proposed pact but could not amend it.) How much more popular will it be next year, after the U.S. trade deficit has swelled with the currency devaluations and slow growth in Asia?
Similarly, global talks to open markets in financial services to international competition are coming to a head. Will the current difficulties discourage some developing countries from opening their fi nancial markets to foreigners as fast or fully as they might have done? Or will the severity of banking system problems in some countries accelerate foreign entry into previously closed banking markets -- as occurred to good effect in Mexico and Argentina after the Tequila Crisis?
The Asian turmoil has also jostled the political economy of the region. It has let China step forward as one of the lenders backing the multilateral rescue efforts; and Japan and Korea's rivalrous leadership claims within the region have been temporarily weakened. The West's aloof attitude may also have fostered an embryonic sense of Asian solidarity, embodied in modest steps toward monetary cooperation. For example, Singapore and Japan joined Indonesia in intervention to strengthen the rupiah after the announcement of the IMF package. Similarly, proposals for an Asia-only rescue fund (to serve, at U.S. insistence, only as a regional resource for IMF-led programs) could represent a small step toward the type of monetary cooperation that over decades led to the European Monetary Union.
What are the lessons of this currency crisis? Two are well known but bear repeating. A second pair may be more controversial.
1 Developing countries should adopt flexible exchange rate regimes as soon as strains start to become evident. Markets can be extremely strict disciplinarians once participants notice something amiss. Since investors tend to move in herds and momentum traders abound, markets sometimes overshoot. Delay can thus result in excessive devaluations, unwarranted output losses, and setbacks in the fight against inflation that can take years to overcome.
2 LDCs must make their financial markets more transparent by providing more data and by using generally accepted accounting standards -- of course. But data are always subject to interpretation; thus, they are a necessary but not a sufficient condition for avoiding future crises.
3 Multilateral rescue/reform packages must be multilateral and clearly credible. The current turmoil has been less well contained than the peso crisis of 1994-95. The Asean governments' resistance/inability to reform contributed enormously to this outcome. But the West's hands-off attitude may also have played a role.
When the international community decides to provide a rescue package, it does so to curb contagion, as lender of last resort. True, moral hazard is an important issue; the international community should not encourage reckless future behavior by limiting today's losses too quickly or too generously. But at some point, the need to stop accumulating credit contraction takes precedence. In contrast to Mexico's $48 billion package, which far exceeded that country's dollar-denominated Tesobono liabilities, the $17 billion Thai rescue package was probably too small, given the central bank's $23 billion liability for dollars sold forward. In the end, a successful containment effort requires a financially and politically credible commitment from world policy makers -- borrowers and lenders alike.
4 In future, policy makers may want to look more carefully at global asset prices and the reasons for their behavior. Of late, policy makers worldwide have been well satisfied with the benign trends in consumer prices. If asset prices seemed high, that was a supervisory issue, not an issue for monetary policy. But with hindsight, the global asset price inflation seen in Asian real estate prices and in equity prices elsewhere may have been a significant symptom of excess world liquidity.
Brazil's President Cardoso described the currency crisis as "a ball that dropped on us from Asia." He went on, "We are good at soccer, and we plan to send the ball back so it falls on somebody else, or preferably in the middle of the Atlantic." We may all view the crisis as a ball that dropped on us, but the crisis did not grow in a vacuum. These problems reflect the many mistakes of individual developing nations and individual investors. They also reflect the tight fiscal and relatively loose monetary policies of the major industrialized countries. In times of crisis, policy makers usually feel compelled to step forward to halt an asset-price collapse. Perhaps they also have a stake in curbing excessive updrafts. The question is, how?
The fallout from the currency crisis will reach New England through reduced net exports to the devaluing countries and through its impact on the earnings of regional firms with investments in the affected areas. New Englanders will benefit from being able to purchase lower-cost consumer goods and producer inputs, but regional producers will also face increased competition from the devaluing countries. Given the distances involved, New England exporters are slightly less dependent on the eight Asian countries embroiled in the recent currency troubles than are exporters nationally; in 1996 the eight accounted for 14 percent of the region's total merchandise exports compared with 16 percent nationally. Nevertheless, New England exported over $4 billion in merchandise to the Asian eight in 1996 over $1 billion in electronics equipment, almost $1 billion in industrial equipment, and roughly $500 million in instruments. Transportation equipment, fabricated metals, chemicals, and paper were other important New England exports to Asia.
Some of these trade flows occur because many New England firms, particularly in the computer and electronics industries, have production facilities in these countries. These investments are extremely important to both parties. At the national level, U.S. multinationals in computers and other industrial equipment earned over 50 percent of their profits in their majority-owned foreign affiliates in 1995; for electronics companies, 30 percent of their profits came from their foreign affiliates. From the host country perspective, U.S. majority-owned affiliates accounted for 9 percent of Singapore's total GDP in 1995 and for 5 percent of output in Hong Kong and Malaysia. New England affiliates selling to Asian markets will, of course, be adversely affected by the recent disruptions to domestic demand in these nations. By contrast, affiliates producing for export to markets outside the Asia-Pacific region will benefit from the lower production costs brought on by the shift in exchange rates. As occurred in Mexico after the peso crisis, increased investments in these Asian affiliates will help spur recovery in the region.Some of these trade flows occur because many New England firms, particularly in the computer and electronics industries, have production facilities in these countries. These investments are extremely important to both parties. At the national level, U.S. multinationals in computers and other industrial equipment earned over 50 percent of their profits in their majority-owned foreign affiliates in 1995; for electronics companies, 30 percent of their profits came from their foreign affiliates. From the host country perspective, U.S. majority-owned affiliates accounted for 9 percent of Singapore's total GDP in 1995 and for 5 percent of output in Hong Kong and Malaysia. New England affiliates selling to Asian markets will, of course, be adversely affected by the recent disruptions to domestic demand in these nations. By contrast, affiliates producing for export to markets outside the Asia-Pacific region will benefit from the lower production costs brought on by the shift in exchange rates. As occurred in Mexico after the peso crisis, increased investments in these Asian affiliates will help spur recovery in the region.
About the Authors
Jane Sneddon Little, Federal Reserve Bank of Boston


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Member Since: December 28, 2009
Country: United States
Yeap http://www.hobbyking.com/hobbyking/store/uh_viewitem.asp?idproduct=26859
I can't stop watching for the Kool-Aid man to bust through one of the walls
I need a bigger workbench.
I have a feeling I'm going to be spending a large amount of time playing with that lego cad tool.
Sparkfun welding helmets
Going along the lines of having a conductive thread woven through the textile, I'd like to see Pokino offer a conductive material that you can use in 3d Printing so one could print the wiring for whatever right into the object itself.
I agree with Gareth..
No public wish lists :(

subset: commoncrawl


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Selfie: Word of the Year?
It's official: "selfie" is the word of the year.
As someone who tries to appreciate the English language and also as someone loves to get irrationally upset about things, I should probably be at least mildly irritated that such a disposable and goofy-sounding word was selected.
Oddly, I'm not.
In fact, I'm uncomfortable with how comfortable I am with this decision. In fact, I would declare that for its purposes, "selfie" is about as perfect as it gets.
Think about it: it's a stupid, self-involved, generally cutesy activity. "Selfie" has the world "self" in it and ends with a dumb cutesy "ie." It's quick, it's easy, and it's not going anywhere.
And, after all, it's better than the word of the year being "twerk."


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Testing Area: Technical
The 'Technical Test/Portion' of placement exams assesses your academic learning and knowledge. Generally, IT companies and core companies include technical questions in their written tests. In these tests, the focus is on quizzing the students on his core subject knowledge and assess the amount of academic effort he has put in during his graduation. In general, the questions asked focus on the basics of core subjects, and check your conceptual clarity.
The best way to prepare for the technical tests is to review your subjects well and have a grasp of the fundamentals. At times, technical papers pose questions such as constructing a diagram, writing a short code/program, or solving some equations. For computer science students, you should revise flow charting techniques and acquire computer software literacy and the appropriate computer language training.
The syllabus of the technical tests for companies varies according to the company domains and requirements. In the following section, you will find a list of representative topics that can be asked in the technical tests for various companies. The topics given below are only a representation of topics and do not include the complete list.
- Computer Science/IT:
Various core companies like Microsoft, Oracle, Polaris software, HCL, etc. conduct technical test for computer science and IT engineering candidates. The syllabus generally includes questions from C Language Basics, Data Structures, Database Management System, Networking, Operating systems, JAVA, etc.
- Electronics & Communication:
Core companies like Siemens, LG, Samsung, Hewlet Packard, etc, conduct electronics and communication paper. The syllabus of this paper includes question from Computer programming, Basic electronics, Analog & Digital electronics, Signals, Control Systems, Microprocessors & Microcontrollers, Communication Networks, etc.
- Electrical Engineering:
Core companies like BHEL, BEL, SAIL, Schneider Electric, Reliance Communication, Honeywell India, Godrej Electronics, etc, conduct electrical engineering papers. The syllabus of this paper includes question from Network theory, Analog & Digital systems, Electronic devices, Microprocessors, Electromagnetic waves, VLSI systems, etc.
- Mechanical Engineering:
Core companies like L&T Construction, ONGC, SAIL, TATA group, Trident, Godrej group, etc, conduct mechanical engineering paper. The syllabus of this paper includes question from Thermodynamics, Strength of Material, Machine Drawing, Theory of Machines, Automobile, Fluid Mechanics, Heat transfer, etc.
- Civil Engineering:
Core companies like L&T Construction, IOCL, SAIL, GAIL, NTPC, ONGC, etc, conduct a civil engineering paper. The syllabus of this paper includes question from Fluid Mechanics, Surveying, Engineering materials, Structural analysis, Foundation engineering, Hydraulics engineering, etc.
Technical questions that most of the IT companies include in their written tests are generally based on same syllabus. The areas from which questions are asked are:
- C Language Basics:
C is one of the most widely used programming languages that most of the IT companies include in their written tests. It includes basic questions like definitions, symbols, etc.
- Data Structures:
Data structure is the organization of data and its storage allocations in a computer. The topic covers basic questions like definitions or structural based.
- Database Management System (DBMS):
It is the software that handles the storage, retrieval, and updating of data in a computer system. Basic questions are asked from this topic.
- Networking:
It is the practice of linking two or more computing devices together for the purpose of sharing data. This topic also includes basic definition based questions.
- Operating Systems:
Software that supports basic functions of computer like scheduling tasks, controlling peripherals and executing applications. Questions asked in the written exam generally cover entire topic.
JAVA is a programming language and computing platform that many IT companies use. This is the reason their written exam includes questions on JAVA. Exam includes question on core JAVA, JAVA Basics and advanced JAVA.


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Mike Kieser, PGA
Main Address:
Round Mountain, NV 89045
Mike Kieser is a PGA Professional in Round Mountain, NV. The PGA of America comprises 27,000 men and women professionals with one singular goal in mind - to make the game of golf more enjoyable for you.
Professional has not entered award information.
Home » Golf Courses » Nevada » Round Mountain » Mike Kieser, PGA
PGA of America Championships
Olympia Fields Country Club
Olympia Fields, Illinois
Quail Hollow Club
Charlotte, North Carolina
Trump National Golf Club
Washington, D.C.
Le Golf National
Guyancourt, France


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Hotel Dieci
Select your stay dates to check availability at Hotel Dieci
Hotel Dieci
About the Hotel
Property Location
With a stay at Hotel Dieci, you'll be centrally located in Milan, walking distance from Politecnico di Milano and close to Piazza Lima. This 4-star hotel is within close proximity of Porta Venezia and Natural Science Museum.
Make yourself at home in one of the 29 air-conditioned rooms featuring minibars and LCD televisions. Complimentary wireless Internet access keeps you connected, and satellite programming is available for your entertainment. Private bathrooms with showers feature complimentary toiletries and hair dryers. Conveniences include phones, as well as safes and desks.
Take in the views from a rooftop terrace and a garden and make use of amenities such as complimentary wireless Internet access. Additional features at this Art Deco hotel include concierge services and a television in a common area.
Satisfy your appetite at a coffee shop/café serving guests of Hotel Dieci. Quench your thirst with your favorite drink at a bar/lounge.
Business, Other Amenities
Featured amenities include complimentary wired Internet access, express check-in, and express check-out. Free self parking is available onsite.
Hotel Facilities
- Bar/lounge
- Elevator/lift
- Laundry facilities
- Designated smoking areas
- Offsite parking discounted rates available
- Luggage storage
- Free parking nearby
- Coffee shop or café
- Number of floors - 4
- Garden
- Free self parking
- Free newspapers in lobby
- Safe-deposit box at front desk
- Concierge services
- Free breakfast
- Dry cleaning/laundry service
- Express check-in
- 24-hour front desk
- Number of buildings/towers - 1
- Year Built 2008
- Free wired high-speed Internet
- Total number of rooms - 29
- Multilingual staff
- Television in common areas
- Rooftop terrace
- Free WiFi
- Express check-out
Room Facilities
- Desk
- Free toiletries
- Phone
- Shower only
- Free newspaper
- Private bathroom
- In-room climate control (air conditioning)
- Daily housekeeping
- Soundproofed rooms
- Minibar
- Satellite TV service
- Free WiFi
- In-room safe
- Room service
- Hair dryer
- Slippers
Hotel Policy
Know Before You Go
- All guests, including children, must be present at check-in and show their government-issued photo ID card or passport.
- Cash transactions at this property cannot exceed EUR 2999.99, due to national regulations. For further details, please contact the property using information in the booking confirmation.
- Children 1 years old and younger stay free when occupying the parent or guardian's room, using existing bedding.
Mandatory Fees and Taxes
You'll be asked to pay the following charges at the property:
- A tax is imposed by the city: EUR 5 per person, per night, up to 14 nights. This tax does not apply to children under 18 years of age.
We have included all charges provided to us by the property. However, charges can vary, for example, based on length of stay or the room you book.A tax is imposed by the city and will be collected at the property. The amount has been determined by the local administration and depends on the length of stay, property classification, and room price. This tax does not apply to residents of Milan or children under 18 years of age. Please note that further exemptions may apply. For more details, please contact the property using the information on the reservation confirmation received after booking. Show all hotel policy Show less hotel policy


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Sedgeford Hall Bowling Green
In 1913 Holcombe Ingleby installed a bowling green about 150 yards to the north west of Sedgeford Hall. In his book The Charm of a Village (1920) he states that during the construction of the green he "discovered that the workmen were turning up pieces of British and Roman pottery" (p.27). He then describes how he went on to ?nd quantities of pottery in various parts of the Sedgeford Valley, but he does not specify where precisely he dug.
Ingleby certainly found a large quantity of pottery; the picture shows tables in the village hall covered in his pottery ?nds. Unfortunately the pottery does not survive: local folklore has it that it was crushed and used in the hard core of the road between Sedgeford and Snettisham. Apart from the brief references in The Charm of a Village, Ingleby's discoveries were not systematically recorded or published.
During the 2000 season a small team of diggers was deployed to the old bowling green site, aiming to discover what Ingleby had found and assess whether any of the deposits have survived. The bowling green has not been in use for at least half a century and has been planted with trees. However, the position of the rectangular green is still evident, with slight banks to the north west and south east, a more de?ned bank to the north east and a drop towards the Heacham river to the south west.
A ?ve metre trench was placed across the north east bank, and test pits were positioned off the green to the north east, south west and north west. The sequences discovered and pro?les surveyed on and off the bowling green suggest that the green was constructed by cutting into the natural slope to create an appropriately sized ?at surface. The material removed appears to have been deposited fairly evenly to the north east, building up the bank. Few ?nds were recovered by hand from this material, but when the spoil was sieved, numerous small sherds of Iron Age and later pottery were recovered. It seems that when Ingleby's workmen excavated the bowling green they missed these small sherds, just as we did when excavating by hand.
We concluded that the construction of the bowling green had removed the archaeological deposits containing the Iron Age and Roman pottery that Ingleby found. However, the quantities of pottery recovered do suggest there is an Iron Age site somewhere in the vicinity and a programme of investigation into the Iron Age at Sedgeford has been initiated.
The full report on the excavation can be accessed here


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Fostex 3010 Patchbay
- Sold for: Start Free Trial or Sign In to see what it's worth.
- Item Category: Entertainment
- Source: eBay
- Sold Date: Feb 25, 2011
- Channel: Auction House
You're looking at a Fostex #3010 Patchbay designed to help you hook-up and route up to 16 stereo devices or 32 mono sources. This is a very quiet unit and doesn't require any power. It includes the manual and it's a snap to hook up. All of your equipment is plugged into the back of the unit and all of your changes in configuration are made on the front panel. What's really great about how this was designed is the speed that you can make your changes. This is definetly a timesaver!


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|Publication number
|Publication type
|Application number
|Publication date
|Dec 12, 1995
|Filing date
|Nov 18, 1994
|Priority date
|Sep 28, 1990
|Fee status
|Also published as
|Publication number
|William J. Dally
|Original Assignee
|Massachusetts Institute Of Technology
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (13), Non-Patent Citations (4), Referenced by (75), Classifications (10), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention was made with government support under contract Numbers DARPA N0014-88K-0738 and DARPA N00014-87K-0825, awarded by the Department of Defense. The government has certain rights in the invention.
This application is a continuation of co-pending application Ser. No. 07/590,367 filed Sep. 28, 1990, now U.S. Pat. No. 5,367,642, which is incorporated herein by reference in its entirety.
Dally, William J. "Express Cubes: Improving the Performance of K-ary N-cube Interconnection Networks" VLSI Memorandum 89-564, Massachusetts Institute of Technology, Laboratory for Computer Science, October 1989, which is incorporated herein by reference.
An interconnection network serves as a pathway for messages to travel amongst nodes of a data processing system. The messages that are sent over the interconnection network often include both data and synchronization information. The nodes of the interconnection network are typically data processing elements such as memory units or processing units. Such nodes may assume either one of two roles with respect to messages. First, they may act as switches that direct messages to their destinations. Second, they may act as message originators that originate messages which are forwarded to other nodes.
Interconnection networks are generally classified by topology, routing and flow control. The topology of an interconnection network concerns the physical arrangement of its nodes and channels into a graph. The routing strategy of an interconnection network, in contrast, refers to the strategy for creating paths in the network having a given topology. Lastly, flow control relates to the allocation of channel and buffer resources as messages travel along the paths of the interconnection network.
A topology of interconnection networks that has proven especially promising is the k-ary n-cube. A k-ary n-cube is an interconnection network that has k nodes in each of its n dimensions. An example of a k-ary n-cube is a 4�4 grid of nodes wherein each node is coupled to its immediately adjacent neighbors. Such a grid constitutes a 4-ary 2-cube because there are 4 nodes in each of the 2 dimensions. The k in the term "k-ary" is known as the radix. An extreme example of a k-ary n-cube is a hypercube.
Latency and throughput serve as useful benchmarks for measuring performance of an interconnection network. The latency of a message is the elapsed time from when a message send is initiated until the message is completely received. The latency of an interconnection network is the average message latency for a given set of specified conditions. Network latency can be broken down into several components. In particular, network latency is comprised of the latency attributable to nodes of the interconnection network, the latency attributable to the wires and the latency attributable to the message length. Network throughput, on the other hand, is the number of messages a network can deliver per a unit of time.
The present invention provides a class of interconnection networks that do not suffer from the significant drawbacks typically suffered by networks such as low degree (i.e. n=2 or n=3) k-ary n-cubes. Specifically, the present invention provides a class of interconnection networks with better throughput and diminished latency relative to low degree k-ary n-cubes. These benefits are realized by employing alternative parallel channels known as express channels in an interconnection network.
The interconnection network of the present invention is comprised of an array of nodes. Each node in the array is capable of routing messages. Local channels connect the immediately adjacent nodes to each other such that, for a message to travel from a node to another node, the message must travel through local channels and through intermediate nodes interconnected by local channels between the nodes. The local channels may be realized as duplex pairs of unidirectional channels having a separate unidirectional channel for carrying messages to a given node as well as a separate unidirectional channel for carrying messages from the given node. Also included in the network of the present invention is an express channel that runs in parallel with the conventional channels to provide an alternative message path between the first node and the second node. The express channel is a path between a pair of interchanges that bypasses the nodes interconnected between the first node and the second node. As such, messages travelling on the express channel do not incur the latency attributable to the nodes positioned between the first node and the second node. Lastly, the interconnection network additionally includes interchanges for interfacing the local channels with the express channel so that messages may travel over either the local channel or the express channel. Such an interconnection network is particularly well suited for a k-ary n-cube topology.
In the simplest embodiment, only a single express channel is used for any given row of an interconnection network. However, the use of additional express channels as discussed below is generally preferred. The nodes of the interconnection network may comprise processing elements as well as memory elements. These processing elements may include memory. It is preferred that the interchanges are situated periodically throughout the interconnection network.
As mentioned above, multiple express channels may be utilized. A hierarchical interchange organization is well suited for use with multiple express channels. In one hierarchical interchange organization, a first interchange interfaces a first of the express channels with the local channels, and a second interchange interfaces the second of the express channels with the local channels. Other hierarchical interchange configurations include more than two levels of express channels. Further, additional interchanges may be included to interface the multiple express channels with each other. In accordance with one embodiment, the hierarchical interchanges are positioned in stepwise fashion so that a message may ascend to a top level express channel and then descend back down to a bottom local channel level in such a manner as to maximize efficiency. The benefit of a hierarchical organization is that the distance component of latency only increases logarithmically with increasing distance. Still further, the express channels may be provided in multiple dimensions. For instance, express channels may be provided for linear arrays of nodes oriented in each of the multiple dimensions.
The interchanges may also be utilized as module interfaces in a data processing system. A module constitutes a physical component in a data processing hierarchy such as a chip, a circuit board, a chassis or a cabinet. When the interchanges are used as such, a first module has an interchange positioned near its module boundary. The interchange acts as an interface with a second interchange positioned within a second module. The two interchanges create an interface between the first and second modules. The interchanges serve additional purposes other than solely that of interfacing modules. For instance, the interchanges may be used to alter wire densities at module boundaries. Moreover, the interchanges may be used to alter the signalling levels at the module boundaries. Lastly, the interchange may be used to alter the rate of message transmission at the module boundaries.
FIG. 1 illustrates a prior art linear array of nodes interconnected by conventional channels.
FIG. 2 illustrates an express cube configuration for a linear array of nodes.
FIGS. 3a and 3b illustrate express cube configurations having multiple express channels.
FIG. 4 shows an express cube organized in hierarchical fashion.
FIGS. 5a, 5b and 5c illustrate potential hierarchical interchange configurations.
FIG. 6 is a plot of latency versus distance for several interconnection network alternatives.
FIGS. 7a and 7b depict alternative embodiments of multidimensional express cubes.
FIG. 8 shows a sample interface between adjacent circuit modules using interchanges.
FIG. 9 shows a block diagram of the hardware of a unilateral interchange.
The present invention provides a means for diminishing latency and increasing throughput in interconnection networks. The present invention is particularly well suited for k-ary n-cube interconnection networks. As such, the preferred embodiment will be described with reference to a k-ary n-cube network. It, nevertheless, should be appreciated that the present invention is not limited to a k-ary n-cube topology; rather it also embodies many other topologies of interconnection networks.
Low dimensional k-ary n-cube interconnection networks (i.e. these having a small value of n), like many of their network counterparts, suffer two significant shortcomings. First, they have node delays that dominate their wire delays. In other words, for any message sent from a starting node to a destination node, the total delay the message experiences in travelling from the starting node to the destination node is due primarily to delays incurred by travelling through intermediate nodes situated between the starting node and the destination node as opposed to delays incurred by travelling over wire channels. One reason that node latency dominates wire latency is that the delay incurred per node is significantly larger than the delay incurred per unit length of wire. The major cause of large node latency, however, is that messages have to travel through several intermediate nodes to reach their destination node. Wire latency, however, is small because wire lengths are quite short, since wires only interconnect adjacent nodes. As a result of the node latency, the latency experienced with such networks is far greater than the theoretical optimum.
A theoretical limit to diminishing latency is that messages may not travel at a rate greater than the speed of light. Thus, a message may not travel a given distance in a shorter period of time than the time it would take for light to travel the same distance. Hence, an ideal network would transfer messages at close to the speed of light. Unfortunately, low dimensional (i.e. n=2 or n=3) k-ary n-cube interconnection networks have a distance related component of latency that generally falls far below this theoretical limit. In fact, the distance related component of latency for such networks falls more than an order of magnitude below the speed of light limitation.
The second shortcoming often suffered by low dimensional k-ary n-cube interconnection networks is that their channel width is often limited by node pin count rather than by wire density, i.e. the number of wires that can be routed through a unit of area. In theory, the channel width of such networks should be limited by the wire density, but, as a practical matter, it is the pin density and pin count that serve as the primary limitations of channel width. Most integrated circuit boards, have sufficient space available to enable the addition of more wires so as to increase wire density. The difficulty lies in that the available wire density on the boards cannot be exploited because of the pin limitations of the chips that the interconnection network interconnects. In fact, due to this limitation in the channels, most current configurations do not get saturated. As a result, maximum throughput is not realized in such networks.
The present invention is able to overcome these shortcomings by providing additional alternative parallel channels known as express channels that can be used for non-local messages (i.e. those destined beyond a given locality of nodes). These express channels are able to increase wire density within the restrictive framework created by the pin limitations. The channels are denoted as express channels because they act as express paths for non-local messages. These paths do not incur the high node latency cost associated with travelling from one node to the next node in a traditional k-ary n-cube. In this regard, the express channel acts analogously to an express train in that it does not make the additional train stops that typical trains have to make.
The ratio of node delay to wire delay and the ratio of pin density to wire density cannot generally be balanced in a traditional k-ary n-cube. However, if a k-ary n-cube is embellished with express channels, the wire length and wire density can be adjusted independently of the choice of radix (k), dimension (n) and channel width (W). Such an augmented k-ary n-cube will be referred to hereinafter as an express cube. In general, the wire length of the express channels can be increased to the point where the wire delays dominate the node delays so that the latency approaches closer to its optimal limit. Furthermore, the number of express channels can be adjusted to increase throughput until the available wiring media is saturated. This ability to balance node and wire limitations is achieved without sacrificing the wire efficiency of k-ary n-cube networks.
For purposes of illustrating the present invention it is helpful to look at the simplest k-ary n-cube: a k-ary 1-cube otherwise known as a linear array of nodes. FIG. 1 illustrates a portion of such a k-ary 1-cube 10. The linear array 10 is comprised of a sequence of nodes 12a-12h interconnected by local communication channels 14. For present purposes, it is assumed that each channel 14 is comprised of pairs of unidirectional channels. This pair is comprised of a unidirectional channel leading to a node and a unidirectional channel leading from the node. Each node 12a-12h is connected by the local channels 14 solely to its immediately adjacent neighbors. Hence, if a message originates from initiating node 12b which is destined for destination node 12e, the message must travel through the two intermediate nodes 12c and 12d situated between the initiating node 12a and the destination node 12e. As a result, a great deal of latency is added to the network because such messages necessarily incur the added node latency of the intermediate nodes 12c and 12d.
Messages may be broken into one or more packets for transmission across an interconnection network. A packet is the smallest unit that contains routing and sequencing information. Packets contain one or more flow control digits. These flow control digits are known as flits. Flits are used to control flow of messages through the network. Each flit, in turn, is composed of one or more physical transfer units or phits. In general, a phit is a sequence of W bits where W equals the number of bits that may be carried by the physical communication media over which messages travel (i.e. channel width).
Message latency is composed of three components. The first component is node latency. The node latency directly corresponds to the number of nodes traversed by a message times the delay incurred for each node. The second component of latency is the wire latency which refers to the time it takes for a message to travel a given distance of wire. The third and final component of latency is the message length. In particular, longer messages take longer to propagate from an initiating node to a destination node. The three components of latency can be expressed more formally in equation form as
T.sub.α =HTn +DTw +(L/W)Tp
Where T.sub.α =latency of a message of length L sent a distance D;
H=number of nodes traversed by a message (referred to as hops);
Tn =latency of a node;
T=latency of a wire per unit distance;
W=width of a channel in bits; and
Tp =pipeline period of a node.
The present invention overcomes the two described shortcomings by employing an express channel configuration such as shown in FIG. 2. The interconnection network 16 shown in FIG. 2 includes an express channel 20 and interchanges 18a and 18b. The inclusion of these additional components 18a, 18b and 20 enables the express cube 16 shown in FIG. 2 to reduce node latency by reducing the number of hops that a message must traverse When travelling between non-local nodes. The express channel 20 runs in parallel with the local channels 14 that interconnect nodes 12a-12h of the express cube 16. The interchanges 18a and 18b are not processing nodes; rather they perform only communication functions. As such, the interchanges 18a and 18b are not assigned an address. They serve primarily as routing interfaces between the local channels 14 and the express channel 20. The hardware of such interchanges 18a and 18b will be discussed below. It is preferred that such interchanges 18 be placed periodically throughout the express cube 16 to maximize their benefit.
To illustrate operation of the interchanges 18a and 18b, suppose that a message is being sent from node 12b to node 12g (FIG. 2). The message is initially sent from node 12b over a local channel 14 towards interchange 18a. When the message arrives at the interchange 18a, the message is routed directly to the next interchange 18b over the express channel 20. The receiving interchange 18b, then, routes the message over another local channel 14 to the destination node 12g. Such a message is deemed a non-local message because it is not destined to the locality of nodes 12c-12f situated between interchanges 18a and 18b. The advantage of using the express channel 20 in this instance is that the message does not incur the added node latencies that it would incur if it were forced to travel through all of the intervening nodes 12c-12f. Instead, the only node latency it incurs is that associated with the interchanges 18a and 18b. (It is assumed that the interchange latency is at most as great as the node latency). The remaining latency is the less significant wire latency.
Suppose, however, that the message being sent from node 12a is destined for a local node such as node 12e. In that case, when the message arrives at the interchange 18a, it is not forwarded along the express channel 20. It, instead, propagates along the successive local channels 14 interconnecting the nodes until it reaches the destination node 12e. In such instances, the message is routed as it would be routed in a conventional k-ary n-cube except that it passes through interchange 18a. In sum, the general rule of operation for an express cube is that a message arriving at an interchange is routed directly to the next interchange if it is not destined for one of the intervening local nodes. Otherwise, the message is routed along the local channels leading to the destination local node. So as to preserve the wire efficiency of the network (i.e. the efficiency in terms of number of wires required by the network), it is preferred that messages are never routed past their destination nodes on the express channels, even though such routing might reduce the number of hops a message would have to travel.
The latency of such express cubes like the latency for conventional k-ary n-cubes, can also be expressed as a mathematical equation. For purposes of this expression, it is assumed that the latency of an interchange equals that of a node (i.e. Tn), and it is also assumed that the throughput of an interchange is equal to that of a node (i.e. 1/Tp). Further, the wire delay of the express channel is assumed to be iTw for interchanges situated every i nodes. Still further, it is assumed the interchanges add no physical distance to the network. Given these assumptions, the latency of an express cube is:
Tb =((D/i)+i)Tn +DTw +(L/W)Tp
where i|D; and
More generally, an average message traversing D processing nodes travels over Hi =(i+1)/2 local channels to reach an interchange, He = D/i-1/2+ 1/(2i) express channels to reach the last interchange before the destination, and finally Hf =((D-i/2+1/2) mod i) local channels to the destination. The total number of hops is H=Hi +He +Hf, giving a latency of
Tb =((i+1)/2+ D/i-1/2+1/2i +((D-i/2+1/2)mod i))Tn +DTw +LTp /W.
A critical factor in reducing the latency is to properly select a value for i, where i is the frequency with which interchanges are placed in the express cube (i.e. the number of successive nodes between interchanges). For large values of D (i.e. when the messages are sent over large distances) choosing i to have a value of α strikes an excellent balance between node and wire delay, where α is the ratio of node latency Tn to wire latency Tw. Specifically, when i is selected to be equal to α, the latency due to distance is approximately twice the wire latency. Such a choice of i insures that node latency will not dominate wire latency as in conventional low dimensional k-ary n-cube networks. The latency for large distances of large express channel networks (where i=α) is within a factor of two of the latency of a dedicated wire travelling the Manhattan distance (distance travelling non-diagonally in only horizontal and vertical steps) between source and destination. In contrast, for small distances (i.e. D is small) and for large α, the i term in the coefficient of Tn in the above equation for Tb is significant. This indicates that node delay dominates the latency. For such networks the choice of i equal to the D minimizes latency. In particular, the latency due to distance approximates 2(D-1)Tn.
Ideally, the throughput of an interconnection network should be limited by its wire density. Experience indicates, however, that throughput for a conventional system is, instead, dictated by pin limitations of chips in the network because current technology does not facilitate the production of enough pins to match the best potential wire density. If more wires are available to transmit data across the network, the throughput will be increased provided that routing and flow control strategies are able to properly schedule traffic onto these wires. Multiple express channels offer such an option. Specifically, multiple express channels exploit the additional area available on most circuit boards to boost wire density by providing additional alternate channels over which messages may travel. The resulting heightened wire density may be readily scheduled with additional traffic without suffering from the bottlenecks of pinout constraints. Hence, multiple express channels are an effective method of increasing throughput in networks where the channel width is typically limited by pinout constraints. The multiple express channels offset the load imbalance between express and local channels to allow network traffic to be more uniformly distributed.
FIGS. 3a and 3b illustrate examples of how multiple express channels may be integrated into an express cube interconnection network. In FIG. 3a, multiple channel interchanges 28 and 30 are used. The interchanges 28 and 30 are inserted every i nodes such as described previously with reference to FIG. 2. Further, each interchange 28, 30 is connected to its neighbors using multiple parallel express channels 24 and 26. Although FIG. 3a depicts an express cube 32 having only two express channels 24 and 26, it should, nevertheless, be appreciated that larger numbers of express channels may be utilized. The interchanges 28 and 30 can be viewed as acting as concentrators that combine the messages arriving on the express channels 24 and 26 with non-local messages arriving on the local channels 14 to concentrate the messages into outgoing message streams on the express channels 24 and 26.
Alternatively, multiple express channels may be implemented by interleaving simplex interchanges such as shown in the configuration 34 of FIG. 3b. In accordance with this approach, simplex interchanges 36a, 36b, 38a and 38b are inserted into each group of i nodes. Each interchange 36a, 36b, 38a and 38b is connected to the corresponding interchange in the next group of i nodes by a single express channel 25 and 27, respectively. All messages from the nodes immediately before an interchange 36a, 36b, 38a and 38b are routed on the express channel 25, 27 associated with the interchange. Hence, a message originating from node 12b that is destined for node 12g is routed through interchange 38a over express channel 27 to interchange 38b and onto node 12g.
The interchanges may also be organized in a hierarchical fashion for multiple express channels. The hierarchical organization overcomes some of the limitations of use of a single express channel. Specifically, for a single level of express channels, an average of i local channels are traversed by each non-local message. The node delay incurred by travelling along these local channels represents a significant component of latency and causes networks with short distances (i.e. D≦α2) to be node limited. Hierarchical express cubes overcome this problem by using several levels of express channels so that the node delay increases only logarithmically with distance for short distances.
With hierarchical express channels there are several levels of interchanges. Specifically, a first level interchange is inserted every i nodes. Next, a second level interchange then replaces every ith first level interchange every i2 nodes. In general, a jth level interchange replaces every ith j-1 level interchange every iJ nodes. FIG. 4 illustrates an example hierarchical express cube for i=2 and L=2 (L denotes the number of express channels). Thus, interchanges 60a and 60b are inserted every 4 nodes replacing the interchanges 62a and 62b that would otherwise be inserted every 2 nodes. The interchanges 62a and 62b interface the express channel 66 with the local channels 14, whereas the interchanges 60a and 60b interface the express channels 64 and 66 as well as the local channels 14.
In a hierarchical express cube such as the one described with reference to FIG. 4, the jth level interchange has j+1 inputs and j+1 outputs. Thus, for the example shown in FIG. 4, the level 2 interchanges 60a and 60b have 3 inputs and 3 outputs. Messages that arrive are treated identically regardless of the input channel on which they arrive. The messages that are destined for one of the next i nodes that follow the interchange are routed to the local level zero output (i.e. over the local channels 14). The remaining messages that are destined for one of the next i2 nodes are routed to the first level output. For the example in FIG. 4, a message originating from node 12b and destined for node 12e travels first to interchange 62a where it is placed on express channel 66. It then travels to interchange 60b which directs it to local channel 14; whereupon, it travels to node 12e.
Suppose, however, that the message originated from a node (not shown) situated before node 12a and was destined for node 12g. In that instance, the message would reach interchange 60a where it is passed via express channel 64 to interchange 60b. At interchange 60b, the message switches to express channel 66. The message then travels over express channel 66 to interchange 62b. Upon arriving at interchange 62b, the message is switched to local channel 14 where it travels to destination node 12g.
This process of routing continues with all messages in such a fashion until they have all been successfully routed. More formally, the process continues with all messages having a destination between ip and ip+1 nodes away where 0≦p≦j-1, which are routed to the pth output. All remaining messages are routed to the jth output.
In general, a message in a hierarchical express cube is delivered in three phases: ascent, cruise, and descent. In the ascent stage, the message ascends to the highest level of express channel on which it will be travelling. For the ascent phase, an average message travels (i+1)/2 hops to get to a first interchange, and (i-1)/2 hops at each successive level for a total of Ha =(i-1)L/2+1 hops and a distance of Da =(iL -1)/2. During the cruise phase, a message travels along the highest level express channel to which it has ascended. In this phase, a message travels Hc =(D--Da)/iL hops on level L channels for a distance of Dc =iL Hc. Finally, the message descends back through the levels, continuing to travel on a level, j, as long as the remaining distance is greater than ij. This phase is the descent phase for the special case where iL |D, the descending message takes Hd =(i-1)L/2+1 hops for a distance of Dd =(iL +1)/2. This gives a latency of
Tc =(D/iL +(i-1)Tn +Tw D+LTp /W.
Choosing i and L so that iL =α balances node and wire delay for large distances. With this choice, the delay due to local nodes is (i-1)LTn =(i-1) logi αTn. Given that i is an integer greater than unity, this expression is minimized for i=2. Choosing i to be a power of two facilitates decoding of binary addresses in interchanges. Networks with i=4, i=8 or i-16 may be desirable under some circumstances.
In the general case where iL D, the latency of a hierarchical express cube is calculated by representing the source and destination coordinates as h=logi k-digit radix-i numbers: S and D, respectively, where S=sh-1, . . . ,s0 and D=dh-i, . . . ,d0. It is assumed that S<D. During the ascent phase, a message routes from the source S along sh-1 to 0 taking H.sub.α hops where H.sub.α =the summation of ((i-sj) mod i) as j goes from 0 to L-1 and covers a distance D.sub.α, where D.sub.α =the summation of ((i-sj) mod i)ij, as j goes from 0 to L-1. Next, during the cruise phase, the message travels Hc hops where Hc =the summation of (dj -sj)ij-1 as j goes from L to h-1 and covers a distance of Dc = Hc iL. Lastly, in the descent phase, the message travels from dh-1 to d0 to arrive at the destination taking Hd hops, where Hd =the summation of dj, as j goes from 0 to L-1 to cover a distance of Dd =the summation of dj ij as j goes from 0 to L-1. It should be noted that for messages travelling short distances, the cruise phase will never be reached. The message moves directly from the ascent phase to the descent phase as soon as it reaches a node where all non-zero coordinates agree with D.
The physical embodiment of the hierarchical interchanges for a hierarchical express cube may take many forms. In general, a level j interchange requires j+1 inputs and j+1 outputs if implemented as a single module. For instance, as shown in FIG. 5a, a single pin bounded module 40 may be utilized to serve as an interchange among the four channels 42, 44, 46 and 48. Any level j interchange may, however, be decomposed into 2j-1 level one interchanges. The corresponding D composition of the interchange 40 of FIG. 5a (where j=2) is depicted in FIG. 5b. Specifically, a series of j-1 ascending interchanges 50a and 52a serve to route non-local traffic towards higher level express channels 42 and 44. These ascending interchanges 50a and 52a are followed by a single top level interchange 54 that serves as a routing interface with the highest level express channel 42. This highest level interchange 54 is, in turn, followed by a series of j-1 descending interchanges 52b and 50b. The descending interchanges 52b and 50b allow the local traffic to descend down to the lowest level local channel 48.
The decomposition of a single module into ascending and descending modules may be simplified by eliminating the ascending interchanges 50a and 52a. In the example case, a configuration such as shown in FIG. 5c is produced. This alternative configuration results in some degradation in performance but only to a limited extent. In particular, this alternative approach requires extra hops in some cases because a message cannot skip levels on its way up to a high level express channel. In general, each message must traverse at least one level j-1 channel before being switched to a level j channel.
The benefits of the use of standard express cubes or hierarchical express cubes relative to conventional k-ary n-cube can be illustrated graphically. For instance, FIG. 6 is a graph of distance versus latency for a number of alternative interconnection strategies: a flat (i.e. non-hierarchical) express cube with 16 levels (curve 102), a hierarchical express cube where L=4 having three levels (curve 104), a conventional k-ary n-cube (curve 100), and a straight plot of wire delay (curve 101). An examination of the graph in FIG. 6 leads to several general conclusions. First, the latency of a conventional k-ary 1-cube is linear and has a slope of α (see curve 100). Second, the latency of a straight wire has a slope of only 1 (see curve 101). Third, the performance of the flat express cube is significantly better than a conventional k-ary n-cube for large distances (compare curve 102 with curve 100). Fourth, the performance of the hierarchical express cube (curve 104) is generally even better than the flat express cube (curve 102).
The performance of the flat non-hierarchical express cube as expressed by the graph needs additional explanation. The flat express cube has the same delay as a conventional k-ary n-cube for short distances until a first express channel is reached by a message. Once the message begins travelling on express channels, the latency is significantly less than that of a conventional k-ary n-cube. Specifically, until the first express channel is reached, the delay equals TD where TD =αD. Once the message begins travelling on the express channel, the latency increases at the lower rate of 1+α/i. In general there is a periodic variation in delay due to the number of local channels being traversed. The local delay equals (i+1)/2+((D-i/2+1/2) mod i).
FIG. 6 also makes evident that the hierarchical express cube (curve 104) has even a more diminished latency than the flat express cube (curve 102). The latency is logarithmic for short distances and linear for long distances. The delay for short distances is within a factor of i-1 of the best that can be achieved with radix i switches. The long distance latency is approximately twice the latency of a dedicated Manhattan wire. It should be noted that for the hierarchical networks the interchange spacing (i.e. i) can be made small to provide good performance for short distances without comprising the delay of long distances messages. Unfortunately, with flat express cubes it is not possible to simultaneouly optimize performance for both short and long distances.
Thus far, the discussion of express channels has focused on express channels and interchanges oriented purely in one dimension. Express channels and interchanges may, however, be employed in multiple dimensions. For instance, as shown in FIG. 7a, interchanges 60 may be inserted separately between nodes 12 in dual dimensions (i.e. X and Y directions). A similar construction may be realized for higher dimensions as well as for hierarchical networks. This approach helps to minimize pin count because each interchange 60 handles only a single dimension (i.e. it handles only messages travelling in one dimension). Moreover, this design is easy to package into modules because of the organization of the interchanges 60 into regular rows and columns.
An alternative approach is to interleave multidimensional interchanges 64 into the array between nodes 12 as shown in FIG. 7b. In such an alternative approach, the interchanges 64 serve the role of both nodes and interchanges. They are able to interface multiple dimensions. The primary benefit of this approach is that it allows messages on express channels to change dimensions without descending to a local channel.
The interchanges in an express cube may also be utilized to change wire density, transmission rate and signalling levels at module boundaries. An example of such a use is shown in FIG. 8 wherein interchanges 71 and 73 serve as an interface between modules 70 and 72.
To understand how this role of the interchanges may be useful, it is necessary to first understand how large interconnection networks are typically built. Such networks are typically built from many circuit modules organized into a physical hierarchy. A typical physical hierarchy includes integrated circuits, printed circuit boards, chassis and cabinets. The available wire density and bandwidth change significantly between the levels of this physical hierarchy. For example, a typical integrated circuit has a wire density of 250 wires per millimeter for a given layer, whereas a printed circuit board can handle only 2 wires per millimeter for a given layer. The interchanges such as 71 and 73 in FIG. 8 may be placed at the boundaries of module 70 and module 72 to vary the number and width of express and local channels. These boundary interchanges 71 and 73 may also be used to serve additional roles. Specifically, they may be used to convert internal module signalling levels, and they may also be used to adjust the speed at which messages travel. The primary role of such boundary interchanges 71 and 73 is to adjust the available wiring density so that it gets saturated with messages.
The interchanges utilized in express cubes may be constructed using traditional hardware. FIG. 9 shows a block diagram of a unidirectional interchange 101. To provide a bidirectional interchange, an identical circuit is constructed in the opposite direction of a single unidirectional interchange. The basic design of the interchange 101 is similar to that of a conventional router. In particular, two input registers 80 and 82 hold flits of incoming messages arriving on channels 91 and 93, respectively. Similarly, two output registers 84 and 86 hold flits of departing messages. Any of these registers 80, 82, 84 and 86 may be replaced with a buffer such as a FIFO buffer if additional buffering is necessary. Associated with each output register 84, 86 is a corresponding multiplexer 88 and 90, respectively. The multiplexers 88 and 90 select which input is routed to the output registers 84 and 86, respectively.
Routing decisions are made by comparing the address information 92 in the head flit of a given message designating the destination address with the local address specifying which nodes are local to the interchange 101. If the destination address lies within the next i nodes, the local channel 91 is selected. Otherwise, the express channel 93 is chosen. The results of the comparison by comparators 94 act as select inputs to the multiplexers 88 and 90 to insure proper selection of the channel 91 or 93.
State vectors 96 and 98 are kept for each of the registers 80, 82, 84 and 86. The state vectors 96 and 98 include presence bits indicating the presence of a valid message in the respective register. The presence bits 96a are utilized for flit level flow control. In general, a flit is allowed to advance from an input register 80, 82 to an output register 84, 86 if the presence bit of its output register 84, 86 is clear or if the register is to be emptied in the same clock cycle. The state vectors 96 also hold input state bits that encode the destination port and status of the message currently using each input. Lastly, the state vectors 98 hold a bit to identify which input has been granted the output. The logic circuitry necessary to maintain these state vectors 96 and 98 and control the respective data paths is known in the prior art.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined in appended claims.
|Cited Patent
|Filing date
|Publication date
|May 14, 1980
|Oct 12, 1982
|Hitachi, Ltd.
|Data transmission system utilizing loop transmission lines between terminal units
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text: Geneva Auto Show Report 2014 Share Comments The Geneva Moto Show or Salon International de l'Auto as it is known in Geneva, Switzerland is held each March and dates back to 1905. Among the big "international" shows, Geneva is one of the best. Not only is it host to all the typical run-of-the-mill manufacturers, it is also a major "style" show and as such draws everything from famed coach works and design houses like Pinininfarina and Bertone but also aftermarket tuners all on the main show floor. Geneva is unique in this regard and it is part of what makes it such a great show. Geneva is also the last major international stage to debut new vehicles before the auto show season winds down for the summer. This means lots of new introductions to keep things interesting. We'll highlight a few of the things featured by Volkswagen and the group brands in addition to some of the more interesting cars we saw on display. Be sure to click on the full gallery of photos at the very end. VOLKSWAGEN The big concept introduction at Geneva this year is called T-ROC. It is an MQB component-based concept that shows a bit of VW's future SUV design direction as well as an exploration into a coupe-like smaller, lifestyle SUV. The T-ROC is 3 inches shorter than the Golf 7 but 2 inches wider making it sit somewhere between Polo and Golf in terms of overall length but with wider SUV proportions mostly in the fenders. The T-ROC also features two removable roof panels that open up a huge amount of roof space turning it into a virtual convertible. We wouldn't be surprised to see a more utilitarian version coming to market in the future. No idea if we'd see it here though. The GTE also made it's debut at Geneva taking goodies from the GTI and GTD and applying them to a plug-in hybrid drivetrain – a Green GTI if you will. There are a number of cool touches in the GTE including a blue stripe version of VW's signature plaid seats: GTE could be built in Mexico for our market, but Volkswagen is only committing officially to the e-Golf so far. We'll keep you posted. Meanwhile the face lifted Scirocco was on display for its public debut and Volkswagen had this very, very nice retro Brown version: Even better still was the interior retro fabric: We're still tracking down specifics on this particular car, but it was cool to see VW giving a nod to history. Volkswagen has also rolled out a curious Alltrack version of the Multivan: With a more butch look and a ton of interior details it looks great. However at well over €65,000 euros we don't see too many takers: AUDI Meanwhile at the Audi stand were all sorts of cool goodies… Old school and new school RS2 and RS4 in Nogaro Blue no less. The new RS4 looks fantastic to us: The new TT also made its debut but what really stole the spotlight for us was a 420hp TT Quattro Sport Concept: Rumored to be the next TTRS, it has a special high output version of the EA888 2.0TSI engine making 420hp. With aggressive styling that looked great on the show stand, Audi did a great job teasing us with this one. The new A3 Sedan looks great, especially with a few accessories pieces on it: Audi also debuted the convertible version of the S3 as well: Lastly was the very cool little S1: LAMBORGHINI The Huracan (Gallardo replacement) made its public debut at Geneva as well: AFTERMARKET While there were a variety of different aftermarket/tuner cars on display, this one took the cake for us: Yes an Amarok. However not just any Amarok – this one has a 4.2. V8 TDI engine swap with 614 pound feet of torque: Be sure to check out the full gallery of more than 800 images below from the show.


text:
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text:
Family: Meth consumed Fayette attempted homicide suspect
A West Virginia woman accused of attempted homicide in a police chase that ended with a lengthy standoff and a suicide was studying to become a drug rehabilitation counselor before she was consumed by a methamphetamine addiction, her parents and sister say.
"They got her hooked on those drugs," said Margaret Phillips, the mother of suspect Jessica Lynn Phillips. "She tried to get away. It takes your soul."
Phillips, 28, faces 26 charges, including aggravated assault, reckless endangerment, fleeing police, drug possession, criminal trespass and conspiracy, in connection with the Sept. 27 incident.
Police said Phillips and the late Donald Brown, 53, fled a secluded area along the Youghiogheny River in Dunbar Township when a ranger from the Department of Conservation and Natural Resources found the pair with a suspected mobile methamphetamine lab.
The pair allegedly led troopers on a chase south into North Union— firing shots out of a rear sliding window on their pickup — before the truck crashed into a home on North Gallatin Avenue.
Police allege they broke into a nearby home on Center Avenue. Phillips surrendered within 15 minutes.
Troopers tried to reach Brown for about nine hours until they found him dead of a self-inflicted gunshot at about 9 p.m.
Phillips' preliminary hearing on the charges was postponed on Wednesday at the request of Assistant District Attorney Michelle Kelley, who said she cannot prove the case should be held for court until the state police crime lab finishes analyzing suspected drug evidence recovered by troopers.
"I'm not inclined to proceed without those results because I don't have a prima facie case without the lab report," Kelley said. "This started out as a meth lab ... (near) Connellsville. The discovery of the meth lab is why we believe they fled (and) shots were fired."
Phillips' sister, Kimberly, said Jessica Phillips was six months away from receiving a college degree in drug rehabilitation counseling when she apparently began using methamphetamine.
Until then, Jessica had worked to pay her tuition and support herself and her two children, ages 9 and 5, her sister said.
"She got hooked up with the wrong people and the wrong drug," her sister said, describing how Jessica met Brown in their hometown of Buckhannon. "Once she met him, she went away from the family."
Margaret Phillips said her daughter tried to enter a drug-rehabilitation facility but was turned away because no beds would be available for several months.
Jessica Phillips was allowed to stay at a facility for just 72 hours before she was released, her mother said.
"She stayed sober for 60 days, and that was the last we heard from her," Margaret Phillips said.
Methamphetamine and heroin addiction are "rampant" in West Virginia, the Phillips family said.
Jessica Phillips' father, James, said his daughter was never in serious trouble with the law until Sept. 27. He said the only information the family has about the Fayette County ordeal came from news reports.
James Phillips said he and his family made the 2 1⁄2 drive from Buckhannon for the hearing to learn more about the charges and to show Jessica they care about her.
"That's my daughter," James Phillips said. "No matter how much I disagree with what she did, she's in my heart."
District Judge Wendy Dennis denied a motion by defense attorney Mike Garofalo for a reduction in Phillips' $1 million bond, having heard from a state police official who testified Phillips has threatened to flee if released.
Cpl. Joseph Panepinto testified Phillips made the remarks during an Oct. 10 phone call that was recorded at the Fayette County Prison in Uniontown.
"She began a conversation with a female," Panepinto testified. "She stated, 'Don't bond me out. I can't stay clean, and I will run.' "
Jessica Phillips declined to comment as three state troopers escorted her from the courtroom to a patrol car.
She was remanded to the Fayette County Prison pending the rescheduling of her hearing.
Liz Zemba is a reporter for Trib Total Media. She can be reached at 412-601-2166 or email@example.com.
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