text:
|Publication number
|Publication type
|Application number
|Publication date
|Sep 9, 1997
|Filing date
|Apr 21, 1995
|Priority date
|Apr 21, 1995
|Fee status
|Publication number
|Larry G. Jones, David T. Blaauw, Robert L. Maziasz, Mohan Guruswamy
|Original Assignee
|Motorola, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (14), Non-Patent Citations (18), Referenced by (128), Classifications (12), Legal Events (10)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates generally to data processing systems, and more particularly, to methods for designing an integrated circuit.
In order to design an integrated circuit (IC), an integrated circuit designer must first provide a library of computer stored circuit cells and a behavioral circuit model describing the functionality of the integrated circuit. FIG. 1 illustrates a widely used and well known method for generating a library of computer stored logic cells. First, the integrated circuit designer needs to determine what cells are needed for the integrated circuit via a step 10. In this step, the human IC designer makes a human determination as to what logic cells are need to manufacture an integrated circuit. These cells typically include fundamental logic gates such as OR, NAND, NOR, AND, XOR, inverter, and like logic cells with an array of logic gate sizes. Once all the required cells are determined via step 10, a step 12 is performed. In the step 12, the IC designer hand-lays out the cells determined in step 10 via a computer graphical interface. In other words, the integrated circuit designer determines physical placement of transistors within each logic cell and determines conductive routing between electrodes of the transistors to form the required logic gates. Once this placing is determined by the human IC designer, the IC designer uses the graphical interface to enter these human determined positions into a computer data base in a two-dimensional format.
Step 14 in FIG. 1 is then used to verify the logic cells defined by the IC designer in step 12. In many cases, Step 14 will discover that the IC designer improperly connected or improperly placed a physical item within one or more cells. In this case, these errors are flagged to the IC designer so that the layout cells may be fixed so that the layout cells perform their proper logical operation. After the step 14, a step 16 checks the hand-laid-out cells to determine if a plurality of design rules are adhered to. Design rules are provided to integrated circuit designers to ensure that a part can be manufactured with greater yield. Most design rules include hundreds of parameters and, for example, include pitch between metal lines, spacing between diffusion regions in the substrate, sizes of conductive regions to ensure proper contacting without electrical short circuiting, minimum widths of conductive regions, pad sizes, and the like. If in step 16 a design rules violation is identified, this violation is flagged to the IC designer so that the IC designer can properly correct the cells so that the cells are in accordance with the design rules. After step 16, a step 18 is performed. In step 18, device physics parasitics are extracted from each of the library cells generated in steps 10-16 by the human IC designer. Parasitic quantities extracted include resistances, capacitances, impedances, inductance, and other like parameters which physically affect or are physically brought about by the cells designed in steps 10-16. In a step 20, the parameters extracted from step 18 along with the physical two dimensional layout of cells defined in steps 10-16 is used to characterize the cells for use in integrated circuit design. When designing an integrated circuit, it is important to take into account characterizations of the cells in order to ensure a functional integrated circuit. The characterizations are found in step 20 and typically include signal rise time, signal fall time, power consumption, propagation delay times though the device, area of the cell, skew rates, and other parameters which may be applicable to the logic cells. Once steps 10-20 have been performed, a library of unconnected cells having inputs and outputs have been adequately formed for use in integrated circuit design. The cells are used as building blocks which are pieced together into a larger interconnected cell-structure known as an integrated circuit.
Once a library is formed via FIG. 1, the library is used in a step 22 of FIG. 2 to design an integrated circuit from the cells defined in FIG. 1. The human IC designer presents as input to a logic synthesis tool 26, the library of cells from step 22 (see FIG. 1) a behavioral model from step 24 in FIG. 2. The library of cells of step 22 was discussed in detail in FIG. 1. The behavioral circuit model is typically a file in memory which looks very similar to a computer program. The behavioral circuit model contains instructions which define logically the operation of the integrated circuit. The logic synthesis tool of step 26, receives as input the instructions from the behavioral circuit model and the library cells from the library in step 22. The synthesis tool 26 maps the instructions from the behavioral circuit model to one or more logic cells from the library to transform the behavioral circuit model to a gate schematic net list of interconnected cells. A gate schematic net list is a data base having interconnected logic cells which perform a logical function in accordance with the behavioral circuit model instructions. In the prior art, once the gate schematic net list is formed, it is provided to a place and route tool via a step 28.
Even though the gate schematic net list contains the initial library cells interconnected into a data base to function in a manner analogous to the behavioral circuit model, the gate schematic net list does not indicate physical placement of cells on an integrated circuit substrate or dye. In other words, the cells in the gate schematic net lists are not physically positioned with respect to one another. The place and route tool of step 28 is used to access the gate schematic net list and the library cells of step 22 to position the cells of the gate schematic net list in a two-dimensional format within a surface area of an integrated circuit die perimeter. The output of the place and route step 28 is a two-dimensional physical design file which indicates the layout interconnection and two-dimensional IC physical arrangements of all gates/cells within the gate schematic net list.
One problem with the widely used process illustrated in FIG. 2 is that the library (step 22 and FIG. 1) is created and defined in a static manner before the process of steps 26 and 28 are performed. The library is never changed after the step 22 and is not customized for the integrated circuit as steps 26 and 28 precede. For this reason, the IC designers are limited to the logic gates implemented in step 22 when performing steps 26 and 28 regardless of whether these cells are appropriate or not. This results in an integrated circuit having time delay problems, power consumption problems, surface area problems, and yield reduction due to static and unchanging library cell availability. These libraries are difficult to create and it is typical that a single library may be used to design multiple ICs and thereby incorporate the above problems into many ICs within a family of products. Therefore, the need exists for a design process which is more interactive in terms of further defining and manipulating library cells throughout the entire design process.
FIG. 1 illustrates, in a flowchart, a prior art method for forming a library of logic cells;
FIG. 2 illustrates, in a flowchart, a prior art method for using the library cells to form an integrated circuit;
FIG. 3 illustrates, in a block diagram, a file structure used within a data processing apparatus in order to allow dynamic cell processing for IC design in accordance with the present invention;
FIGS. 4-5 together illustrate, in a flowchart, a single process for designing an integrated circuit (IC) using a library cell dynamic process in accordance with the present invention;
FIG. 6 illustrates a initial library which is analogous to a library produced by the step 106 of FIG. 4;
FIG. 7 illustrates graphically the textual contents of a gate schematic net list;
PIG. 8 illustrates a transistor level diagram of the gates of FIG. 7;
FIG, 9 illustrates alternate gate boundaries for the transistor level diagram of FIG. 8.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the FIGURES have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the FIGURES to indicate corresponding or analogous elements.
In general, the present invention teaches a method and apparatus for designing an integrated circuit. The design process and apparatus taught herein begins by providing a behavioral model and an initial library of logic cells to a design synthesis tool. The design synthesis tool (such as Synopsis� design compiler) processes the behavioral model using initial library cells to provide a gate schematic net list. The gate schematic net list is a plurality of interconnected library cells stored in a data file which when functionally tested will perform the required IC logic functions in accordance with the IC behavioral model. The gate schematic net list is then processed to redefine boundaries of logic cells. In addition, cell strengths are altered by altering specific sizes of transistors in the gate schematic net list. This size alteration is used to achieve speed path constraints while minimizing area (die size/footprint) or power impact. Power rail conductors (conductive lines which supply Vdd and ground voltages to the logic cells) are changed in width in order to ensure proper supply of current and voltage so that power inadequacies do not occur in the integrated circuit. Also, cell pitch or cell height of various blocks of circuitry in the gate schematic net list are optimized in order to ensure minimal area and optimized integrated circuit layout.
Once these optimizations are performed to the gate schematic net list the initial set of library cells can no longer be used to form the integrated circuit since transistors have been changed in physical characteristics from the initial library and the outer boundary of what defines the particular logic cells have been changed from the initial library cell entries. These changes resulted in optimizing the integrated circuit design for speed, power, area, noise, etc., far beyond the capabilities possible when using only the initial library. Therefore, due to these optimizations, a new hybrid library must be generated taking into account the changes made by the optimizations discussed above. The new optimized gate schematic net list is provided along with the new hybrid library to a place and route tool.
The place and route tool then places and routes hybrid logic gates (not original/initial logic gates) according to the gate schematic net list in a two dimensional format which is compatible with mask generation and integrated circuit processing. In other words, the place and route tool uses the hybrid cells from the hybrid library in conjunction with the optimized gate schematic net list to physically place the logic cells onto an integrated circuit die in a manner which fits in the reticule mask size required in the industry. Once the physical design file is provided by the place and route tool to indicate a two dimensional layout of the integrated circuit, integrated circuit masks are formed from the physical design file information. These masks are then used to manufacture a plurality of integrated circuit wafers/dies using semiconductor processing techniques widely known in the art. Techniques used to form integrated circuits from masks can be found via "Silicon Processing For the VLSI Era", Volume 1, by S. Wolf and R. N. Tauber, Lattice Press, 1986.
Specifically, the above process can be performed by utilizing a file structure illustrated in FIG. 3. FIG. 3 illustrates a computer 30 having a CPU 32 coupled to a memory 34 via a bus. The bus typically passes address, data, and control information to and from the memory unit 34. In memory 34 are a plurality of computer programs for manipulating data structures/data bases and a plurality of data files. These files, computer programs, and data bases, are used by the CPU 32 to perform the operations illustrated in subsequent FIG. 4-5. Therefore, FIG. 3 will be discussed with reference to FIG. 4-5 since the two figures are closely related. FIG. 3 illustrates a plurality of CAD (computer aided design) tool programs 36 stored in memory 34. These plurality of CAD tools include automated programs for generating the library in step 106 and step 105 both of FIG. 4. CAD tools 36 also includes tools for generating the computer instructions for describing IC logical behavior used within the behavioral model 100 of FIG. 4. CAD tools 36 also includes a logic synthesis tool, such as the Synopsys� design compiler, to transform the behavioral circuit model to a gate schematic net list illustrated in FIG. 4 via the output of step 102.
The aforementioned behavioral model, initial library, gate schematic net list are illustrated in FIG. 3 as behavioral model file 38, initial library of cells data base 40, and gate schematic net list file 42. Once the CAD tools 36 process the model 38 and the library 40 to produce the gate schematic net list 42, the gate schematic net list is optimized via steps 104-114 in FIG. 4. The optimization in steps 104 and 110 can simply involve changes to the original gate schematic net list 42, the writing of a whole new gate schematic net list 50, or simple file additions or addendum files to the gate schematic net list 42. The steps 112 and 114 in FIG. 4 respectively provide power rail instructions 44 and cell pitch instructions 46 to separate data files in memory to use by the step 105 in FIG. 4. After the power rail instructions 44 and instructions 46 are formed and a new gate schematic net list 50 is generated or the gate schematic net list 42 is optimized/changed, then a new hybrid library 48 is created via steps 116-125 in FIG. 4. The new hybrid library from hereon in the process replaces the initial library 40 since the optimization of the gate schematic net list results in altering the logic cells beyond the scope of the initial cells stored in the initial library.
The CAD tools 36 include a place and route program which accepts as input the new hybrid library 48 and the new optimized gate schematic net list 42 or 50 and produces a physical design file 52. The new hybrid library 48 contains separate non-connected logic cells for purposes of cell definition. Gate schematic net list 42 contains several cells from the new hybrid library 48 interconnected in order to properly form the logic function of the integrated circuit described via model 38. Physical design file 52 incorporates information from the gate schematic net list functionality using hybrid cells from library 48 in a two-dimensional layout manner which physically defines the layout structure of the integrated circuit in a two-dimensional graphical data base manner. The physical design file is the output or final file provided via the steps of FIGS. 4-5 and stored in memory 34. It is important to note that there are literally hundreds of possible file organization combinations for the steps of FIGS. 4-5. FIG. 3 is one possible combination of files among the many combinations in which file management can occur for the process of FIGS. 4-5.
FIG. 4 illustrates a step 100 wherein a behavioral integrated circuit model is provided. The behavioral model or register transfer logic (RTL) file contains a plurality of instructions that resemble a high-level computer language. These plurality of instructions logically define a logical operation or functional operation of an integrated circuit. A short except of a behavioral model may look like:
______________________________________module NineCell (a, b, c, d, e, f, g, x, y, z);input a;input b;input c;input d;input e;input f;input g;output x;output y;output z;wire x;wire y;wire z;assignx = c & d & e & f & g | a & c & e,y = a & b & c & e | a & b & c & e & f & g,z = a & c & d & e & f & g | b & f;endmodule______________________________________
where & is a logical AND operation, and | is a logical OR operation. The file may also include other operators describing NOR, NAND, XOR, inversion, add, subtract, multiply, divide, bit-wise operations, shift operations, and like logical operations.
FIG. 4 illustrates that a step 106 provides an initial library comprising a plurality of stored logic cells. The logic cells will contain two dimensional layouts of individual unconnected cells having inputs and outputs that when interconnected among many other library cells form an integrated circuit. For example, an initial library may contain an inverter, a two-input OR gate, a three-input OR gate, a two-input AND gate, a three-input AND gate, a two-input NOR gate, a three-input NOR gate, a two-input NAND gate, a three-input NAND gate, an XOR gate, D flip-flops of varying sizes, multiplexor blocks, tri-state buffers, output buffers, pass transistor layouts, half adder layouts, full adder layouts, and like small "building block" logical cells/components.
In FIG. 4, a logic synthesis tool is used in step 102. The logic synthesis tool receives as input the required interconnection schemes of each library cell and the RTL file from steps 100 and 106. The step 102 transforms the logical instruction operations of the RTL file to a physical gate manifestation by replacing logical representations of the instruction in step 100 with cells/gates from step 106. Therefore, when the step 102 determined that the RTL file contains an instruction a&b, step 102 matches a corresponding/appropriate physical AND logic gate cell from the library to perform this a&b operation. The resulting output of this correlation and interconnection to attain the functionality of the RTL file using logic gates/cells of the initial library of step 106 resulting in the a following example of a gate schematic netlist:
______________________________________module NineCell (a, b, c, d, e, f, g, x, y, z);input a, b, c, d, e, f, g;output x, y, z;wire n63, n64, n65, n66, n67, n68;nand3 U7 {.in-- 0(d), .in-- 1(g), in-- 2(f), .out(n64)};nand2 U8 {.in-- 0(c), .in-- 1(e), .out(n65)};nand2 U9 {.in-- 0(f), .in-- 1(b), .out(n67)};nand2 U10 {.in-- 0(a), .in-- 1(b), .out(n68)};nor2 U11 {.in-- 0(n65), .in-- 1(n68), out(y)};inv U12 {.in-- 0(a), .out(n63)};or3 U4 {.in-- 0(n65), .in-- 1(n63), .in-- 2(n64),.out(n66)};nand2 U5 {.in-- 0(n66), .in-- 1(n67), .out(a)};aoil2 U6 {.in-- 00(n65), .in-- 10(n63), .in-- 11(n64),out(x)};endmodule______________________________________
Example 2 illustrates the output file of step 102 which is typically a text file gate schematic net list representing, in instructions, interconnected library cells. The output of both steps 100 and 102 are functionally equivalent representations although RTL files are easier for a human to generate than gate schematic netlists. Therefore, the RTL file is human generated, and transformation from an RTL file to a gate schematic net list is automated or partially automated. For information regarding gate schematic net list generation, refer to Design Compiler Tutorial Version 3.0b, June 1993, Synopsys�.
After step 102, a step 103 is performed wherein step 103 optimizes the gate schematic netlist on a transistor-by-transistor TELOS basis to improve speed at the expense of area while trying to minimize the overall area impact. The method taught herein will provide one or more of the advantages or improvement an item selected from the group of circuit speed, signal noise, power, capacitive coupling, inductance, circuit surface area, power rail sizing, cell height/pitch, cell 2-D shape, etc.. Step 103 is illustrated in FIG. 4 as several sub-steps 104, 111, 112, and 114. In order to understand these sub-steps, the FIGS. 6-9 are now discussed and FIG. 4 will be returned to later.
FIG. 6 illustrates a initial library 208 which is analogous to a library produced by the step 106 in FIG. 4. This library contains only four cells and is therefore extremely simplified by way of example. Most libraries out of step 106 comprise tens to hundreds of predetermined logic cells. Library 208 comprises a two-input OR gate 200, an inverter 202, a three input AND gate 204, and a two-input NAND gate 206. The two dimensional IC layouts of the cells 200, 202, 204, and 206 are stored in the library in an X-Y data format which is not graphically illustrated in FIG. 6.
FIG. 7 illustrates graphically the textual contents of a gate schematic net list. The gate schematic netlist graphical representation of FIG. 7 resulted from processing a behavioral circuit model (RTL file) which textually described logically three outputs (output 1, output 2, and output 3) which are a function of five inputs (in 1, in 2, in 3, in 4, and in 5) along with a library of cells from FIG. 6.
FIG. 8 illustrates a transistor level diagram of the gates of FIG. 7, and is representative of the textual data stored by a gate schematic net list provided via the step 102 in FIG. 4. FIG. 8 illustrates the boundaries of the initial cells 200, 202, 204, and 206 as used defined in FIG. 6.
FIG. 4 illustrates that a first sub-step in step 103 is used to redefine cell boundaries within the gate schematic net list illustrated graphically by FIG. 8. It is important to note that one library cell may be used hundreds or thousands times in the gate schematic net list to arrive at a function net list. The cell boundary redefirdtion is performed as indicated by the following psuedocode where {. . . } are comment regions (in some embodiments, redefinition of boundaries may not be needed):
______________________________________definitions:cost( ); {determines the impact a specific cell or many cells have in terms of area, delay, power, etc.}glom (x,y) {generates one or more hybrid cells from an x initial cell and a y initial cell}code:begin;input gate level netlist;C=cost(all gates in net list); {determine the initial cost of the gate schematic netlist asdo output from step 102}dochoose x, y such thatcost(glom(x,y)) is minimal; {go through pairs of adjacently coupled gates and attempt to change their boundaries to find a minimal impact cell boundary configuration}if cost (glom(x,y)) < cost (X) + cost(y)then replace x and y with {if the use of the hybridglom (x,y); cells is better than the use of the individual x and y original cells then use the hybrid cells}C=cost(all gates with newly {get a new C value due toadded hybrid cells) the new hybrid improve- ments}for all designated gate pairs in design {do loop over all adjacent gate pairs which require optimization of boundaries}until (C does not decrease); {loop until no more benefit is attained by hybrid boundary redefinition}output a hybrid improved gate schematic net list;end;______________________________________
In general, the gate boundary redefinition is illustrated in FIG. 9 when compared to FIG. 8. Gate boundary redefinition may have freedom to change boundaries on a transistor by transistor basis or may only be allowed to combine whole initial cells in new/larger boundary patterns. In FIG. 9, the output inverter of 204 is combined with inverter 202 of output 202 to form a dual inverter hybrid cell 212 with two outputs. Hybrid cell 210 illustrates that two gates (a 3-input NAND and a two input OR) may be combined to form a hybrid cell 210. FIG. 9 also illustrates that a minimum impact cell is equal to the initial cell. In other words, the cell 202 and the hybrid cell 214 are the same between FIGS. 8 and 9. Hybrid cell 216 in FIG. 9 illustrates that initial cells may be split in a transistor-by-transistor basis to form hybrid logic cells. Hybrid logic cell 218 illustrates that a single transistor may be a cell, and hybrid cell 220 teaches that a hybrid cell can be a portion of an initial or previous cell.
With the exception of hybrid cell 214, the hybrid cells of FIG. 9 are not located in the library of FIG. 6. Therefore a new library must be generated to manufacture ICs using the hybrid logic cells. In addition, other areas of the IC or circuit block may use the initial cells the library of FIG. 6. Therefore, the new hybrid library of cells will usually contain more cells than the initial library cells although, in some seldom-occurring situations, a hybrid library will have fewer cells than the initial library. For example, the hybrid library may need to contain cells 200, 204, 202, 206, 210, 212, 214, 216, 218, and 220 in order to make the IC. Due to the typical resulting volume of different hybrid cells that result, the hybrid library layout generation is typically entirely automated via software since a human-created hybrid library would take too many man hours to create.
The redefinition of cell boundaries is useful for many reasons. By redefining cell boundaries according to one or more predetermined cost criterions (speed, power, area, noise, etc.), a better design can be made. For example, assume that the signal conductor 300 in FIG. 8 is on a critical speed path and that region 300 must be short in conductive length and fast. The redefinition of the upper right-hand cells 204 and 202 in FIG. 8 to hybrid cell 212 in FIG. 9 ensures that line 300 will be small and fast since the two inverters of cell 212 are now ensured to be placed close together. In fact, the cells will be placed directly adjacent one another. Redistributed boundaries may help cell shape and cell area leading to a more dense layout. Also, combining transistor of same conductivity type may result in a more well-efficient layouts result wherein a well is a doped region within the substrate where different dopant-type wells are needed for PMOS transistors versus NMOS transistors.
Therefore, the above discussion describes in detail the function of the step 104 in FIG. 4. The redistribution of cells have numerous advantages.
After the re-defining of the cell boundaries in step 104, a step 110 is performed. In step 100, individual cell transistors are increased and/or decreased in size to modify a channel region size or aspect ratio (Width/Length of the gate electrode/channel region) of the transistor in order to provide a circuit that is in accordance with provided/predetermined speed requirements. Each circuit has speed paths or delay times wherein a signal must travel from point A to point B in an integrated circuit. In an integrated circuit, a specification determines that path A to path B must be traversed in X nanoseconds. By sizing gate electrodes/channel regions of transistors over the circuit path from A to B, one can get the speed of transmission to less than or equal to X.
Step 100 is performed via a TILOS, or a like, sizing scheme described via one or more of: "A set of switch-level synthesis tools", by Hill, D. D., Shugard, D., Dunlop, A., Fishburn, J, 1990 IEEE International Symposium on Circuits and Systems, p.2571-5 vol.4; "Experiments using automatic physical design techniques for optimizing circuit performance", Dunlop, A. E., Fishburn, J. P., Hill, D. D., Shugard, D. D., 1990 IEEE International Symposium on Circuits and Systems, p.847-51 vol. 2; "Optimization-based transistor sizing", Shyu, J., Fishburn, J. P., Dunlop, A. E., Sungiovanni-Vincentelli, A. L., Proceedings of the IEEE 1987 Custom Integrated Circuits Conference p.417-20.
Once step 110 is complete, a step 111 checks to ensure that all speed paths are within specification. If a speed path timing problem is too severe to be acceptable, the step 102 is re-performed and a new gate schematic net list is derived. Many of these feedback paths exist in FIGS. 4-5 and are used to "back-up" and optimize when conditions warrant.
If the speed paths are within predetermined timing constraints, then a step 112 is performed. After step 110, a determination can be made regarding the power that will be needed by the integrated circuit in order to function properly. This power can be related to current flow through P=IV where P=maxmal power over time, I=max current drawn by IC over time, V=voltage supplied when max current drawn. The current I can be used to determine the cross-sectional area required for the metal lines that provide Vdd and ground to the IC. Typically, the depth or height of the wire is process dependent and fixed whereas the lithographic width of the metal power rail lines can be altered by design. The widths of the power rail are adjusted to ensure that the metal will not current limit or fail when the IC requires maximal power consumption. Power rail sizing can be optionally during place and route to adjust power rail sizing by IC row or block. Typically an IC is laid out in circuit blocks or rows which comprise the total IC. These blocks or rows may each have varying power requirements that do not need the maximal power rail sizing determined above.
Once step 112 is performed, a step 114 is performed. Step 114 is used to optimize cell pitch (i.e., cell height) to allow the IC circuit block to fit into a predetermined space/shape or to reduce the total area of the circuit block. Each cell in a block is given the same pitch for block uniformity and a change in height can affect width. A change in cell pitch may either increase or decrease total cell area, therefore, a search over a range of cell pitches is used to minimize the total area. One cell pitch process is as follows:
______________________________________Input:maxH; {maximal allowable cell height}minH; {minimal allowable cell height}deltaH; {cell height quantized step size}gate schematic netlist data;cell area weights; {the number of times a cell is used within IC}Output:bestH; {optimal height value}beginH = best H = max H; {set H and best H to the maximal possible}dogenerate cell library/circuitry at height H via netlist info;if total area is smaller than bestH then bestH = H;H=H-deltaH;while (H>=minH);end;______________________________________
The bestH value that is output from the above method is the optimized value for the cell, IC, or block of cells. In another form, a space/shape may be predetermined and the block of cells may need to be optimized and/or confined within the predetermined space/shape.
After step 114, a step 115 is performed. In step 115, the area of the gate schematic netlist file optimized via step 103 is analyzed to ensure that the area is acceptable. If the total area is not acceptable, the method returns to step 102.
After the step 103 (which includes steps 104, 110, 111, 112, and 114), some cells of the initial library of step 106 will probably not resemble any cells resulting out of step 115. The integrated circuit file output from step 115 contains hybrid cells which may vary from initial cells by one or more of: boundaries, cell strength (transistor sizing), cell pitch, power rail width, and the like. For these reasons, the hybrid cells in the integrated circuit file, which is provided out from step 115, must be used to create a new library via a step 105. Step 105 contains sub-steps 116, 117, 118, 119, 120, 121, 122, 123, 124, and 125.
In the step 116, the hybrid cells are automatically assigned to an optimal 2-D area via an automated layout tool. Layout of library cells can be performed by hand by a designer but the sheer volume of cells that typically results out of the step 115 results in an automated process being of great time saving value. Automated cell layout for a library can be performed by canned software such as Cadence� design tools like the Virtuoso Layout Synthesize™. Automated layout is taught via "Optimal Layout of CMOS Functional Arrays", IEEE Tran. Computer, Vol. C-30, pp. 305-312, May 1981; "GENAC: an automated cell synthesis tool", Ong, Proc. 26th Design Automation Conference, pp. 474-479; and "LIB: a cell layout generator", Proc. 27th Design Automation Conf., pp. 474-479, 1990.
After step 116, a step 117 checks to ensure that the area of the hybrid library cells is satisfactory and if not, the method returns to step 102. If step 117 determines that the area of the hybrid cells is acceptable then the step 118 is executed.
Step 118 is used to verify the logical operation of the laid-out hybrid cells. This step 118 asks the question, "does the layout in step 118 perform the same logical operation the hybrid gates input to step 116?" In a few cases, an automated layout tool or an automated layout optimized slightly by human input can produce a flaw in a logic cell layout. These logical/operational flaws can be found in step 118. If errors are found in step 118, a step 119 re-routes the process back to step 116 so that flaws can be corrected.
In a step 120, the design rules of the hybrid cells are checked. Design rules are rules that limit metal spacing, doped well separation, contact geometries, field isolation minimum widths, closeness of conductive layers, pitch of layers, minimum lithographic dimensions for layers, and the like. The design rules are rules that are usually built up over time and learned by experience. These rules are implemented to avoid structural formation that tend to fail, reduce yield, leakage current, create undue, capacitance, increase detrimental electric field and breakdown of oxides, and the like. If the hybrid cells in the hybrid library are in accordance with the design rules a step 122 is performed else the step 116 is returned to.
In step 122, parasitic parameters are extracted from the cell layout created in step 116. Step 122 determines capacitance, resistance, inductance, and other SPICE-like parameters needed to understand the physics operation of the cell. These parasitic parameters aid in cell characterization and aid in improving or optimizing the library cells. If, in step 123, the parasitics indicate an error, step 116 is returned to, else a step 124 is performed.
In the step 124, the hybrid cells are characterized. Characterization means that the cells are analyzed to define circuit operation parameters such as rise times, fall times, propagation delays, skew, and the like. If characterization via the step 124 indicates an acceptable plurality of hybrid cells, then the step 126 of FIG. 5 is performed, else the step 116 is returned to.
In FIG. 5, a step 126 receives as input the gate schematic net list with all optimizations/changes from step 103 and receives as input the hybrid cells of the hybrid library. From the gate schematic net list and the hybrid cells, the place and route tool lays out the circuit hybrid cells, groups of hybrid cells, and/or portions of the IC to form a larger 2-dimensional (2-D) physical layout file of the circuit described behaviorally via step 100. This larger 2-D circuit may be an entire IC or a portion of yet another larger IC. In general, the net list contains information regarding what cells are connected to what other cells without defining cell arrangement on a 2-D surface and the hybrid library contains detailed 2-D layouts for each cell with no interconnectivity information. By combining the two and interconnecting the cells using conductive interconnects, the step 126 outputs a physical design file that is a 2-D computer graphical database for the physical die of the IC. Place and route tools are available from ArcSys�, and one such tool is ArcCell™. In practice, although referred to as 2-D for simplicities sake, the physical design file contains a plurality of stacked 2-D layers to create a three-dimensional (3-D) data base that describes the actual physical structure of the manufactured IC. For example, the physical design file will contain a 2-D layer for source and drain regions of transistors, a 2-D layer for gate electrode placement, several 2-D layers for interconnection layers of metal and polysilicon, 2-D threshold and field oxide implant regions, layers for contacts openings to connects interconnection layers to one another, and the like.
In a step 127, if the place and route tools results in an unsatisfactory 2-D IC layout, then the choice is made to return to one of either steps 114, 110, or 102 depending upon the severity or type of problem. If the physical design file output from step 126 is within expectations, then the step 128 is performed to extract parasitic information for the entire physical design file. Step 128 is similar to step 122 with only the sheer volume of circuitry analyzed being different.
In a step 130, the timing and power of the physical design file is verified. If the circuit timing and power consumption is within accpetable limits then the step 131 directs the method to one of either step 133 or step 132, else one of either the steps 102 or 110 are returned to. If, in steps 131, the entire IC is completely pieced together the step 132 is directly executed. If the processing of steps 100-130 were simply to create a block of a larger circuit, then step 133 incorporates all blocks together to create a complete IC and then the step 132 is executed.
In step 132, several IC masks are made in accordance with the physical design file. Typically, one mask is equivalent to one layer in the 3-D structure of the physical design file. Layers in the physical design file, and therefore masks, may vary from design-to-design from 5 or so masks to roughly one hundred masks. These masks are each physical replicas of the 2-D layers in the computer-stored physical design file. Masks are made by exposing photoresist covered quartz substrates (that have a thin upper layer of an opaque material) to a light pattern determined by reading data from the physical design file. E beam traces guided by the physical design file database or directionless light focused by small openings created by an X set of blades and a Y set of blades expose only portions of the photoresist on the quartz masks. The mask is then selectively etched to form opaque and transparent regions in accordance with a layer in the physical design file.
In a step 134, the masks are used in a lithographic process to form a plurality of ICs. IC fabrication techniques are known in the art as taught by "Silicon Processing", S. Wolf, Vol. 1, Lattice Press, 1986.
While the present invention has been illustrated and described with reference to specific embodiments, further modifications and improvements will occur to those skilled in the art. For example, further feedback paths can be added to the flow of FIGS. 4-5 as needed to optimize a design process. Many different file structures and databases exist to implement the process of FIGS. 4-5. Plurality as used herein is intended to mean any integer between 2 and infinity and should not be limited to any other sub-range or constant. It is to be understood, therefore, that this invention is not limited to the particular forms illustrated and that it is intended in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention.
|Cited Patent
|Filing date
|Publication date
|Nov 9, 1982
|Sep 23, 1986
|International Microelectronic Products
|Method and structure for use in designing and building electronic systems in integrated circuits
|Dec 22, 1986
|Mar 14, 1989
|The Cadware Group, Ltd.
|Schematic diagram generating system using library of general purpose interactively selectable graphic primitives to create special applications icons
|Mar 29, 1990
|Jan 28, 1992
|National Semiconductor Corporation
|Simulation model generation from a physical data base of a combinatorial circuit
|Jun 28, 1990
|Nov 2, 1993
|National Semiconductor Corporation
|Structured logic design method using figures of merit and a flowchart methodology
|Dec 5, 1990
|Dec 28, 1993
|Ncr Corporation
|Method of estimating logic cell delay time
|Sep 5, 1990
|Apr 11, 1995
|Vlsi Technology, Inc.
|Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler including a cell library
|Nov 13, 1991
|Sep 19, 1995
|Westinghouse Elec. Corp.
|Method and apparatus for converting a programmable logic device designed into a selectable target gate array design
|Apr 11, 1994
|Oct 17, 1995
|Ross Technology, Inc.
|Method and apparatus for optimizing electronic circuits
|Aug 13, 1993
|Jan 23, 1996
|Vlsi Technology, Inc.
|Electronic design automation apparatus and method utilizing a physical information database
|Jun 1, 1994
|Feb 20, 1996
|Lsi Logic Corporation
|Specification and design of complex digital systems
|Jun 13, 1994
|Apr 23, 1996
|Cadence Design Systems, Inc.
|System and method for generating component models
|Nov 15, 1994
|May 21, 1996
|Vlsi Technology, Inc.
|Datapath synthesis method and apparatus utilizing a structured cell library
|Jun 2, 1994
|Nov 5, 1996
|Lsi Logic Corporation
|Method and system for creating and validating low level description of electronic design
|May 20, 1994
|Nov 5, 1996
|Lsi Logic Corporation
|Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
|A. Dunlop, J. Fishburn, D. Hill, D. Shugard, "Experiments Using Automatic Physical Design Techniques for Optimizing Circuit Performance," Intl. Symp. on Circuits & Systems, 1990, pp. 847-851.
|A. Dunlop, J. Fishburn, D. Hill, D. Shugard, Experiments Using Automatic Physical Design Techniques for Optimizing Circuit Performance, Intl. Symp. on Circuits & Systems, 1990, pp. 847 851.
|D. Hill, D. Shugard, A. Dunlop, J. Fishburn, "A Set of Switch-Level Synthesis Tools," 1990 IEEE Intl. Symposium on Circuits and Sytems, vol. 4., pp. 2571-2575.
|D. Hill, D. Shugard, A. Dunlop, J. Fishburn, A Set of Switch Level Synthesis Tools, 1990 IEEE Intl. Symposium on Circuits and Sytems, vol. 4., pp. 2571 2575.
|Dwight Hill, "SC2D: A Broad-Spectrum Automatic Layout System," IEEE 1987 Custom Integrated Circuits Conference, May 4-7. pp. 729-732.
|Dwight Hill, SC2D: A Broad Spectrum Automatic Layout System, IEEE 1987 Custom Integrated Circuits Conference, May 4 7. pp. 729 732.
|J. Fishburn,, A Dunlop, "TILOS: A Posynomial Programming Approach to Transistor Sizing," IEEE Intl. Conference on Computer Aided-Diesign, 1985, pp. 328-328.
|J. Fishburn,, A Dunlop, TILOS: A Posynomial Programming Approach to Transistor Sizing, IEEE Intl. Conference on Computer Aided Diesign, 1985, pp. 328 328.
|J. Shyu, J. Fishburn, A. Dunlop, A. Santiovanni Vincentelli, Optimization Based Transistor Sizing, IEEE 1987 Custom Integrated Circuits Conference, May 4 7, pp. 417 420.
|J. Shyu, J. Fishburn, A. Dunlop, A. Santiovanni-Vincentelli, "Optimization-Based Transistor Sizing," IEEE 1987 Custom Integrated Circuits Conference, May 4-7, pp. 417-420.
|Lee et al., "A Graphic Interface for Power System Simulation," 1993 Power Industry Computer Application Conference, pp. 269-276.
|Lee et al., A Graphic Interface for Power System Simulation, 1993 Power Industry Computer Application Conference, pp. 269 276.
|N. Maheshwari, S. Sapatnekar, "Gate Size Optimization for Row-based Layouts," 38th Midwest Symposium on Circuits and Systems, vol. 2, pp. 777-779, 1996.
|N. Maheshwari, S. Sapatnekar, Gate Size Optimization for Row based Layouts, 38th Midwest Symposium on Circuits and Systems, vol. 2, pp. 777 779, 1996.
|Ramachandran et al., "SYMCELL-A Symbolic Standard Cell System," IEEE Journal of Solid-State Circuits, vol. 23, No. 3, Mar. 1991, pp. 449-452.
|Ramachandran et al., SYMCELL A Symbolic Standard Cell System, IEEE Journal of Solid State Circuits, vol. 23, No. 3, Mar. 1991, pp. 449 452.
|S. Sapattnekar, V. Rao and P. Vaidya, "A Convex Optimization Approach to Transistor Sizing for CMOS Circuits," ICCAD-91, Nov. 11-14, 1991, Santa Clara, CA pp. 482-485.
|S. Sapattnekar, V. Rao and P. Vaidya, A Convex Optimization Approach to Transistor Sizing for CMOS Circuits, ICCAD 91, Nov. 11 14, 1991, Santa Clara, CA pp. 482 485.
|Citing Patent
|Filing date
|Publication date
|Dec 19, 1996
|Nov 24, 1998
|Mitsubishi Electric Semiconductor Software Co., Ltd.
|Semiconductor integrated circuit including a high density cell
|Aug 29, 1996
|Mar 16, 1999
|International Business Machines Corporation
|Method for generating an improved model for evaluating the operation of an integrated circuit design
|Jan 26, 1996
|Mar 23, 1999
|Advanced Micro Devices
|Method for analyzing the performance of a microprocessor
|Feb 7, 1996
|May 4, 1999
|Motorola, Inc.
|Apparatus and method for automatically placing ties and connection elements within an integrated circuit
|Aug 16, 1996
|Jul 6, 1999
|International Business Machines Corporation
|Parameterized cells for generating dense layouts of VLSI circuits
|Oct 15, 1996
|Jul 13, 1999
|Matsushita Electric Industrial Co., Ltd.
|Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof
|Feb 26, 1997
|Sep 21, 1999
|Advanced Micro Devices, Inc.
|Methodology for designing an integrated circuit using a reduced cell library for preliminary synthesis
|Jul 25, 1997
|Oct 26, 1999
|Fujitsu Limited
|Layout algorithm for generating power supply interconnections for an LSI circuit
|Nov 1, 1996
|Nov 16, 1999
|Motorola Inc.
|Automatic synthesis of standard cell layouts
|Mar 7, 1997
|Nov 30, 1999
|Matsushita Electric Industrial Co., Ltd.
|Method for generating transistor placement in an automatic cell layout design
|Nov 14, 1996
|Dec 14, 1999
|Avant! Corporation
|Symbolic constraint-based system for preroute reconstruction following floorplan incrementing
|Nov 1, 1996
|Dec 21, 1999
|Motorola, Inc.
|Method of routing an integrated circuit
|Apr 28, 1997
|Feb 29, 2000
|Chrysler Corporation
|Vehicle electrical schematic management system
|Mar 3, 1997
|Jun 13, 2000
|Motorola, Inc.
|Optimizing combinational circuit layout through iterative restructuring
|Jun 12, 1998
|Sep 12, 2000
|International Business Machines Corporation
|Optimum buffer placement for noise avoidance
|Dec 31, 1997
|Oct 3, 2000
|Intel Corporation
|Method for analyzing and efficiently reducing signal cross-talk noise
|Feb 8, 1999
|Mar 13, 2001
|Invention Machine Corporation
|Computer based system for imaging and analyzing a process system and indicating values of specific design changes
|Apr 29, 1998
|Apr 3, 2001
|Nec Corporation
|Apparatus and method for circuit simulation which accounts for parasitic elements
|Jul 30, 1998
|Apr 24, 2001
|Micron Technology, Inc.
|Semiconductor circuit design method for employing spacing constraints and circuits thereof
|Apr 2, 1998
|May 8, 2001
|Magma Design Automation, Inc.
|Method of designing a constraint-driven integrated circuit layout
|Sep 11, 1998
|Jul 17, 2001
|The United States Of America As Represented By The Secretary Of The Army
|Determination of functionality for integrated circuit modules
|Oct 30, 1998
|Aug 14, 2001
|Lsi Logic Corporation
|Integrated circuit design with delayed cell selection
|Sep 15, 1998
|Oct 9, 2001
|Matsushita Electric Industrial Co., Ltd.
|Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof
|Feb 19, 1997
|Oct 23, 2001
|Matsushita Electric Industrial Co., Ltd.
|Layout input apparatus, layout input method, layout verification apparatus, and layout verification method
|Aug 18, 1997
|Nov 20, 2001
|Altera Corporation
|Apparatus and method for automatically generating circuit layouts
|Sep 17, 1996
|Nov 20, 2001
|Hitachi, Ltd.
|Method of supporting arrangement of semiconductor integrated circuit
|Jun 29, 1999
|Nov 27, 2001
|Advanced Micro Devices, Inc.
|Using a reduced cell library for preliminary synthesis to evaluate design
|Sep 17, 1998
|Dec 11, 2001
|International Business Machines Corporation
|Method for preparing command files for photomask production
|May 26, 1998
|Jan 1, 2002
|Matsushita Electric Industrial Co., Ltd.
|Method and apparatus for designing LSI layout, cell library for designing LSI layout and semiconductor integrated circuit
|Oct 1, 1999
|May 7, 2002
|Lsi Logic Corporation
|Flexible width cell layout architecture
|Sep 30, 1998
|May 28, 2002
|National Semiconductor Corporation
|Zero hold time circuit for high speed bus applications
|Mar 29, 2001
|Aug 13, 2002
|Micron Technology, Inc.
|Semiconductor circuit design methods employing spacing constraints
|Aug 16, 2000
|Sep 17, 2002
|Aeroflex Utmc Microelectronic Systems Inc.
|Method for fabricating integrated circuits
|Mar 15, 2001
|Oct 15, 2002
|Fujitsu Limited
|Design support apparatus for semiconductor devices
|Apr 27, 1999
|Jan 7, 2003
|Magma Design Automation, Inc.
|Method for storing multiple levels of design data in a common database
|Jun 8, 2001
|Feb 18, 2003
|Library Technologies, Inc.
|Apparatus and methods for wire load independent logic synthesis and timing closure with constant replacement delay cell libraries
|Oct 3, 2000
|Feb 18, 2003
|Monterey Design Systems, Inc.
|Method to optimize net lists using simultaneous placement and logic optimization
|Jun 20, 2000
|Mar 25, 2003
|Bae Systems Information And Electronic Systems Integration, Inc.
|Tool suite for the rapid development of advanced standard cell libraries
|Jun 15, 1999
|Apr 1, 2003
|Cadence Design Systems, Inc.
|Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placement
|Jan 25, 2001
|Apr 29, 2003
|Nec Electronics Corporation
|Layout design method
|Jul 6, 2000
|May 6, 2003
|International Business Machines Corporation
|Apparatus and method for buffer library selection for use in buffer insertion
|Aug 24, 2000
|May 6, 2003
|Cadence Design Systems, Inc.
|Apparatus and methods for modeling and simulating the effect of mismatch in design flows of integrated circuits
|Sep 6, 2000
|Jun 3, 2003
|Aeroflex UTMC Microelectronics Systems, Inc.
|Gate array cell generator using cadence relative object design
|Sep 14, 2001
|Jul 1, 2003
|Ampro Computers, Inc.
|PCB/complex electronic subsystem model
|Aug 28, 2001
|Jul 1, 2003
|Conexant Systems, Inc.
|Method and system for predictive layout generation for inductors with reduced design cycle
|Sep 10, 2001
|Nov 25, 2003
|Fujitsu Limited
|Delay characteristic analyzing method and delay characteristic analyzing system for a custom LSI
|May 24, 2001
|May 11, 2004
|Infineon Technologies Ag
|Method for optimizing a cell layout using parameterizable cells and cell configuration data
|Feb 27, 2001
|Jul 27, 2004
|Matsushita Electric Industrial Co., Ltd.
|Method of physical design for integrated circuit
|Oct 29, 1999
|Dec 14, 2004
|Sun Microsystems, Inc.
|Method for reducing noise in integrated circuit layouts
|Apr 7, 2000
|Dec 14, 2004
|Transim Technology Corporation
|Circuit simulator
|Oct 24, 2001
|Jan 4, 2005
|Conexant Systems, Inc.
|Method and system for predictive multi-component circuit layout generation with reduced design cycle
|Dec 5, 2002
|Mar 15, 2005
|Infineon Technologies Ag
|Method for fabricating an integrated semiconductor circuit
|Jun 19, 2002
|May 10, 2005
|Bruno P. Melli
|Systems and methods for generating an artwork representation according to a circuit fabrication process
|Feb 14, 2003
|Sep 20, 2005
|Bae Systems And Information And Electronic Integration, Inc.
|Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements
|Mar 22, 1999
|Apr 18, 2006
|Hewlett-Packard Development Company, L.P.
|Method and apparatus for evaluating the design quality of network nodes
|Sep 26, 2002
|May 30, 2006
|Cypress Semiconductor Corporation
|Method, system, and computer program product for designing an integrated circuit using substitution of standard cells with substitute cells having differing electrical characteristics
|Mar 23, 2004
|Sep 5, 2006
|Taiwan Semiconductor Manufacturing Company
|Method to design and verify an integrated circuit device with multiple power domains
|Sep 15, 2004
|Apr 3, 2007
|Renesas Technology Corp.
|Automatic placement and routing apparatus and automatic placement and routing method
|Jan 20, 2004
|Aug 14, 2007
|International Business Machines Corporation
|Method, circuit library and computer program product for implementing enhanced performance and reduced leakage current for ASIC designs
|Sep 4, 1998
|Mar 18, 2008
|Intel Corporation
|Selecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraints
|Jan 18, 2007
|Jul 8, 2008
|Fujitsu Limited
|Method, device, and computer product for creating height-limited-area information, and method of manufacturing three-dimensional structure
|Nov 19, 2003
|Jul 15, 2008
|Asset Trust, Inc.
|Entity centric computer system
|Aug 8, 2003
|Jul 22, 2008
|Elm Technology Corporation
|Vertical system integration
|Jan 19, 2006
|Mar 17, 2009
|Samsung Electronics Co., Ltd.
|Event driven switch level simulation method and simulator
|Aug 8, 2005
|Aug 25, 2009
|National Semiconductor Corporation
|Use of state nodes for efficient simulation of large digital circuits at the transistor level
|Jan 25, 2006
|Mar 30, 2010
|Easic Corporation
|Programmable via modeling
|Feb 5, 2009
|Sep 20, 2011
|Nangate A/S
|Optimization of integrated circuit design and library
|Sep 16, 2008
|Oct 18, 2011
|Taiwan Semiconductor Manufacturing Company, Ltd.
|Method for shape and timing equivalent dimension extraction
|Sep 11, 2007
|Nov 8, 2011
|Semiconductor Energy Laboratory Co., Ltd.
|Display device
|Oct 30, 2008
|Jul 10, 2012
|National Cheng Kung University
|Driving circuit, and a pixel circuit incorporating the same
|Sep 20, 2011
|Sep 18, 2012
|Nangate A/S
|Optimizing a circuit design library
|Mar 16, 2010
|Jan 22, 2013
|Synopsys, Inc.
|Modeling of cell delay change for electronic design automation
|Jan 19, 2011
|Jan 29, 2013
|Cadence Design Systems, Inc.
|Method and system for power distribution analysis
|Jan 19, 2011
|Feb 5, 2013
|Cadence Design Systems, Inc.
|Method and system for power distribution analysis
|Jan 19, 2011
|Feb 5, 2013
|Cadence Design Systems, Inc.
|Method and system for power distribution analysis
|Jan 19, 2011
|Feb 19, 2013
|Cadence Design Systems, Inc.
|Method and system for power distribution analysis
|Aug 5, 2011
|Jul 9, 2013
|Nangate Inc.
|Optimizing cell libraries for integrated circuit design
|Aug 5, 2011
|Jul 9, 2013
|Nangate Inc.
|Optimizing integrated circuit design based on cell library
|Sep 18, 2012
|Jul 9, 2013
|Nangate Inc.
|Circuit design library optimization
|Jul 8, 2009
|Mar 4, 2014
|Samsung Display Co., Ltd.
|Organic light emitting display device
|Nov 20, 2011
|Apr 29, 2014
|Square Halt Solutions, Limited Liability Company
|Complete context search system
|Nov 4, 2011
|Jun 3, 2014
|Semiconductor Energy Laboratory Co., Ltd.
|Display device
|Mar 28, 2012
|Jun 24, 2014
|Synopsys, Inc.
|Optimizing logic synthesis for environmental insensitivity
|Oct 23, 2013
|Jul 29, 2014
|Glenn J Leedy
|Three dimensional structure memory
|Aug 9, 2013
|Aug 5, 2014
|Glenn J Leedy
|Three dimensional memory structure
|Aug 9, 2013
|Sep 23, 2014
|Glenn J Leedy
|Three dimensional memory structure
|Nov 4, 2011
|Dec 2, 2014
|Semiconductor Energy Laboratory Co., Ltd.
|Display device
|Jan 4, 2013
|Dec 9, 2014
|Glenn J Leedy
|Three dimensional structure memory
|Dec 27, 2012
|Mar 10, 2015
|Synopsys, Inc.
|Modeling of cell delay change for electronic design automation
|Dec 3, 2012
|Jul 14, 2015
|Robust Chip Inc.
|Soft error resilient circuit design method and logic cells
|Aug 12, 2014
|Jul 21, 2015
|Glenn J Leedy
|Three dimension structure memory
|Aug 19, 2011
|Dec 8, 2015
|Cadence Design Systems, Inc.
|Automated adjustment of wire connections in computer-assisted design of circuits
|Sep 12, 2014
|Jan 5, 2016
|The United States Of America, As Represented By The Secretary Of The Air Force
|System and method for identifying electrical properties of integrate circuits
|Nov 20, 2014
|Jan 3, 2017
|Semiconductor Energy Laboratory Co., Ltd.
|Display device
|Dec 5, 2002
|Jun 5, 2003
|Michael Wagner
|Method for fabricating an integrated semiconductor circuit
|Jan 24, 2002
|Jul 24, 2003
|Debashis Bhattacharya
|Context-sensitive constraint driven uniquification and characterization of standard cells
|Jun 19, 2002
|Dec 25, 2003
|Melli Bruno P.
|Systems and methods for generating an artwork representation according to a circuit fabrication process
|Sep 15, 2004
|Mar 17, 2005
|Renesas Technology Corp.
|Automatic placement and routing apparatus and automatic placement and routing method
|Jan 20, 2004
|Jul 21, 2005
|International Business Machines Corporation
|Method, circuit library and computer program product for implementing enhanced performance and reduced leakage current for asic designs
|Mar 23, 2004
|Sep 29, 2005
|Taiwan Semiconductor Manufacturing Co.
|Method to design and verify an integrated circuit device with multiple power domains
|Apr 9, 2004
|Oct 13, 2005
|Zenasis Technologies, Inc.
|System and method for automated accurate pre-layout estimation of standard cell characteristics
|Jan 5, 2006
|Jun 1, 2006
|Van Ginneken Lukas P
|Method for storing multiple levels of design data in a common database
|Jan 19, 2006
|Aug 24, 2006
|Lee Seuk-Whan
|Event driven switch level simulation method and simulator
|Sep 16, 2003
|Nov 9, 2006
|Carlo Guardiani
|Integrated circuit design to optimize manufacturability
|Jan 25, 2006
|Jul 26, 2007
|Easic Corporation
|Programmable via modeling
|Mar 30, 2006
|Oct 4, 2007
|Inventec Corporation
|Computer-aided ultrahigh-frequency circuit model simulation method and system
|Jul 12, 2007
|Jan 17, 2008
|Cray Inc.
|Parasitic impedance estimation in circuit layout
|Sep 11, 2007
|Apr 3, 2008
|Semiconductor Energy Laboratory Co., Ltd.
|Display device
|Jan 18, 2007
|Apr 3, 2008
|Fujitsu Limited
|Method, device, and computer product for creating height-limited-area information, and method of manufacturing three-dimensional structure
|Sep 29, 2008
|Apr 2, 2009
|Innolux Display Corp.
|Electro-wetting display device
|Feb 5, 2009
|Aug 6, 2009
|Andre Inacio Reis
|Optimization of Integrated Circuit Design and Library
|Sep 16, 2008
|Sep 3, 2009
|Taiwan Semiconductor Manufacturing Company, Ltd.
|Method for shape and timing equivalent dimension extraction
|Jun 12, 2009
|Dec 3, 2009
|National Semiconductor Corporation
|Use of state nodes for efficient simulation of large digital circuits at the transistor level
|Jul 8, 2009
|Jan 28, 2010
|Samsung Mobile Display Co., Ltd.
|Organic light emitting display device
|Oct 30, 2008
|May 6, 2010
|Chih-Lung Lin
|Driving Circuit, and a Pixel Circuit Incorporating the Same
|Mar 16, 2010
|Sep 22, 2011
|Synopsys, Inc.
|Modeling of cell delay change for electronic design automation
|Dec 3, 2012
|Jun 27, 2013
|Robust Chip Inc.
|Soft Error Hard Electronics Layout Arrangement and Logic Cells
|Sep 5, 2013
|Mar 5, 2015
|Mentor Graphics Corporation
|Logic-Driven Layout Pattern Analysis
|Oct 30, 2014
|May 21, 2015
|Arm Limited
|Computer implemented system and method for generating a layout of a cell defining a circuit component
|Mar 23, 2015
|Feb 18, 2016
|Klas Olof Lilja
|Circuit and layout design methods and logic cells for soft error hard integrated circuits
|Sep 16, 2003
|Apr 1, 2009
|IC design for optimizing manufacturability
|May 24, 2000
|Dec 6, 2001
|Infineon Technologies Ag
|Integrated circuit cell layout optimisation method has initial cell layout automatically modified after optimisation of component dimensions
|Feb 15, 2002
|Nov 17, 2011
|Qimonda Ag
|Verfahren zum �berpr�fen einer integrierten elektrischen Schaltung
|Dec 22, 2004
|Jul 13, 2006
|Siemens Ag
|Designvorrichtung f�r das Layout einer elektrische Bauteile aufweisenden Vorrichtung
|Jan 27, 2000
|Aug 10, 2000
|Invention Machine Corporation
|Computer based system for imaging and analyzing a process system and indicating values of specific design changes
|Sep 16, 2003
|Apr 21, 2005
|Pdf Solutions, Inc.
|Integrated circuit design to optimize manufacturability
|Mar 16, 2011
|Sep 22, 2011
|Synopsys, Inc.
|Modeling of cell delay change for electronic design automation
|Mar 16, 2011
|Nov 24, 2011
|Synopsys, Inc.
|Modeling of cell delay change for electronic design automation
|U.S. Classification
|716/55, 716/112, 716/134, 716/119, 716/104, 716/113, 716/115
|International Classification
|Cooperative Classification
|European Classification
|Apr 21, 1995
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Marina Del Rey, CA
Chequered Flag International is proud to offer this 1969 Jaguar E-Type Series II 4.2 Litre Coupe in Willow Green with Beige interior. 34132 miles... More
Advertiser since 2005
1994 Jaguar XJS Cabriolet
Delray Beach, FL
Pedigree Motorcars is proud to offer this beautiful Jaguar XJS for sale. For details contact Ken Baker at 561-866-1601. Pedigree sold this car a couple... More
1967 Jaguar E-Type 4.2L Series 1
Huntington Station, NY
1967 JAGUAR E-TYPE 4.2 LITER SERIES 1 COUPE --Black with Red leather interior and Red carpeting, 55,000 Original miles, 4-speed manual gearbox, Matching numbers, Jaguar... More
Advertiser since 1989
1960 Jaguar MK 2 Saloon
Huntington Station, NY
1960 JAGUAR 3.8 LITER MK 2 SALOON --British Racing Green with Green leather interior and Green carpeting, 4-speed manual, Frame off restored, Power steering, Air... More
Advertiser since 1989
1953 Jaguar XK-120 Drophead Coupe
London, United kingdom
It was at the 1948 London Motor Show that Jaguar virtually threw the sports car world into turmoil with its stunning XK120. Here was... More
1974 Jaguar XKE 2-Door Convertible
Bellevue, WA
Park Place Ltd is pleased to present this 1974 Jaguar XKE V12 Roadster. An absolutely gorgeous piece of automotive artwork, this Series III OTS... More
2014 Jaguar XK Convertible
Bellevue, WA
Presented in crisp Polaris White with Warm Charcoal Leather Interior, this 2014 Jaguar XKR Convertible is a sleek and muscular supercharged performance drop-top that... More
2014 Jaguar F-Type Convertible
Bellevue, WA
2014 Jaguar F-Type V8 S Roadster in Ultimate Black Metallic with Jet Black Leather Interior. Supercharged 5.0L/495hp V8 Engine. 8-Speed Automatic Trans. Original MSRP... More
2000 Jaguar XJ8L Vanden Plas
Gladstone, NJ
Local, untouched, almost unmarked, completely original example of the long wheelbase, ultra-luxurious "Vanden Plas" model with just over 15,000 miles. Topaz with supple oatmeal leather... More
Advertiser since 2004
1967 Jaguar E-Type FHC
Beverly Hills, CA
1967 Jaguar E-Type FHC '67 Jaguar E-Type Series 1.5 Fixed Head Coupe in British racing green with green interior. Comes equipped with a manual transmission,... More
Advertiser since 2009
1996 Jaguar XJS 2+2
Sioux Falls, SD
One owner, very rare XJS. Last year of the XJS with the best of everything. One of 1485 made in 1996 making this not... More
1955 Jaguar D-Type Coupe
Milpitas, CA
-3 carburetors-In-line 6 engine , XKE engine, triple weber, -163 XKE vents-Aluminum dash '63-posi traction rear end-D-Type seats-'55 gas cap-4-wheel disc brakes-'57 Tail lights... More

subset: commoncrawl


text:
Entries in 'Electronics Entertainment Expo' (2)
ESA hits back at E3 critics, but is considering inviting consumers
A defiant ESA, the organiser of E3, says the LA expo is 'essential and critical' to the games industry.
OPINION: E3 may be over for you
The words: 'E3 just isn't as relevant as it used to be' are invariably said by two sets of people. Either those with a vested interest in its decline, or ...


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Follow-up Question: 7 weeks post op BA. Left side not dropping. Weird shape. Soreness on left outer breast.
I got 800 ccs smooth implants under the muscle, transaxillary approach. My left side hasn't dropped and it's making my nipple point down. Also, I think I may have massaged too hard and I'm feeling constant ache on my outer left side. Did I break the capsule? When I massage, the implant goes outwards instead of downward. My right one is dropping slowly but surely. My left is the problem.
Doctor Answers 5
Follow-up Question: 7 weeks post op BA. Left side not dropping. Weird shape. Soreness on left outer breast.
You appear to have very large implants for your breast pocket. Therefore, it can take a very long time for the implants to settle. Wait at least 6 months (and in some cases even longer) for the implants to settle. Remember that no two breasts ever look the same or heal at the same rate. Good luck!
Breast augmentation healing
Thank you for the question and photos. It appears that you had fairly small breasts before surgery. Since 800 cc implant require a lot of skin and soft tissue expansion it may be that it will take longer for both breast implants to drop down. If the pockets were created to allow this to happen it is reasonable to assume that this will occur with time and massage. It may also be that the pocket is too tight or insufficiently released to accommodate the large implants. It this is the case, a revision to lower the pockets will be needed. A revision surgery would not be as big of a recovery as your initial breast augmentation. Because of the size of the implants it may be that your plastic surgeon or the plastic surgeon that you choose to go to will need to use a breast fold incision since getting to the breast fold area via the arm pit with 800 cc implants in place may be difficult to accomplish.
I hope this helps.
All the best,
Dr. Remus Repta
I hope this helps.
All the best,
Dr. Remus Repta
Large implants take much longer to settle
Thanks for your question and the photos. I'm sorry that you are having problems. Your very small chest and tight crease made you a set up for implant malposition and asymmetry using such a huge implant. From a transaxillary approach it is also harder to control the fold. There may be some improvement over the next few months. Keep in touch with your surgeon. Best of Luck!
You might also like...
Follow-up Question: 7 weeks post op BA. Left side not dropping. Weird shape = follow up with your plastic surgeon #breastimplant
Patients with questions and concerns about their breast augmentation healing process should address those concerns with the plastic surgeon that performed the operation.
Web reference: http://www.drmesa.com/breast-procedures-new-jersey/gummy-bear-implants/
Large implants, tight fit
You have a small chest area to fill a large breast implants. From the preoperative photo, it also looks like you have a very tight fold which makes it difficult for you breast tissue to expand. 7 weeks is still way too early for your implants to settle. I would wait at least 6 months to make any opinions.
Best Wishes,
Nana Mizuguchi, MD
Best Wishes,
Nana Mizuguchi, MD
These answers are for educational purposes and should not be relied upon as a substitute for medical advice you may receive from your physician. If you have a medical emergency, please call 911. These answers do not constitute or initiate a patient/doctor relationship.


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Making sense of art history
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- Introduction
- Learning outcomes
- 1 What is art?
- 2 The Turner Prize: an annual farce or a celebration of creativity?
- 3 Art works and their effects
- 4 The relationship between effects and techniques
- 5 Colour
- 5 Colour
- 5.1 Introduction
- 5.2 Question 1: Has a wide or narrow palette of colours been used?
- 5.3 Question 2: Have contrasting colours been placed next to each other?
- 5.4 Question 3: Are there more warm colours than cool colours or vice versa?
- 5.5 Question 4: Are the colours largely bright or dull?
- 5.6 Question 5: In what way is dark and light colour used?
- 5.7 Comparing art works
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Home › Forums › Off Piste › Photography › DP Merrills
Apr 28, 2013 at 2:11 pm #1302296
The quality from the Merrill series of Sigma DP cameras is outstanding. Unbeatable and unbelievable for the size/weight.
These are very limited cameras in some ways, but perfect for a very deliberate style suitable for landscapes. I've had excellent experience using all three in the outback, handheld as well as on a tripod (I opt for a Tamrac Zipshot).
Here is a stitched photo from a recent backpacking trip in Auvergne, France:
This panorama was stitched from 9 photos taken with the DP3M. It's been reduced in size so much, posterization is inevitable, but at 880MB for the whole whopper, the color and detail are breathtaking.
Weight of the camera is about 400gr, but you'd better take a quiver of batteries!Apr 28, 2013 at 2:24 pm #1981345Apr 28, 2013 at 2:41 pm #1981351
Brendan SwihartBPL Member
@brendansLocale: Fruita CO
Agreed. I've been using a DP2M for a couple months now and it's nuts what it's capable of for the size, price, and weight. I recently made some 16×20 prints for a show and I don't even want to know what I'd have to spend and carry to get close what the Sigma can do.
Are you only using the DP3? The DP3 is interesting for the close up ability but the DP2 focal length is perfect for the stuff I like to do and stitching is easy enough for wider shots. Just picked up the AML-2 close up attachment in anticipation of plant season.
I bought a bunch of off brand Ricoh DB-65 batteries off ebay for a couple bucks each and used a dremel to make the bottom slots fit in the sigma. Works great.Apr 28, 2013 at 2:59 pm #1981361
Hi Brendan, I was expecting to find threads here about this series. Surprisingly little to date however. Seems like a good fit for a UL kit.
I have and use all three. Usually take the DP1M and the DP3M, each in a waterproof Ortlieb padded pouch strapped to my hipbelt, along with a set of Lee filters. But I have also gone with just the DP2M.
The 3m and the 2M are more suited to stitching than the 1M because of the slight lack of sharpness in the corners on that latter one. But I do like the ease and simplicity of a single frame/single capture.
These are really the cameras I've been waiting for. I don't miss shooting Velvia at all. And since they are fixed lens units that are not that expensive (relatively speaking), I don't have to worry about scratches etc to the body.
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Christmas 2007
Christmas for our family was a mixed affair. We all loved each other in our own ways but some of the family never showed it to anyone. They kept it bottled inside and it emerged as hatred. To this day I still don't know why.
I had arranged for everyone to be at my pub for early evening as it would give me time to whip up some tasty treats in the kitchen. I always imagined myself as a chef and could hold my own in the kitchen. Originally I wanted it to be a sit down meal but both my brother and his girlfriend had told me they would be having christmas dinner with Sean's son Nigel and Sean's daughter Rachel. So instead I prepared a finger buffet.
I was looking forward to this as it had been a long time since we had all been together. There was going to be my mum, my partner Nicola and her sister. My friend and barman James, my Aunty Jean, my sister Janice and her new husband. Also joining us would be Nigel and his partner, and of course Sean, Sarah and Sarah's daughter. A full house! So glad the pub was big enough!
Everyone turned up at around six o'clock in the evening and presents and cards were exchanged. I looked upon their faces and hoped that we could do it again next year and many years to come. It felt complete again.
As usual with our family, whenever we got together we spoke openly about many things. Family, past relationships, the future etc. It helped us to understand each other better. Well, for some of us anyway.
My sister Janice had always had a grudge towards mum. She had always felt that her dad was not her dad as both my mum and Janice's dad were fair skinned and she looked olive skinned. Even myself, I thought the same but my mum was adamant that her dad was her dad.
As the drinks flowed, I could see that Janice was getting more and more agitated. Maybe it was the drink in her system that made her outburst towards mum even worse. The words "You are not my mum" did not go down well with Sean at all. He tried to calm it down and everyone thought that the situation was resolved. How wrong we were.
By the end of the evening, I can say with all honesty that we were slightly tipsy. We must have been because me and my brother tied poor Nigel up and proceeded to shave off his curly locks!! Even my mum stood back and just watched us do it. Now I know you may be thinking "Oh thats evil!" but it was all in jest. We had warned him we would do it. He had sat all night with this awful beenie hat on. Even his girlfriend begged us to do it.
Time was getting late, or should i say early as it was around 1am when I phoned for taxis. The stress of getting a taxi on Boxing Day morning! What a farce. We finally managed to get enough taxis to take everyone home and we were saying our goodbyes. By the time it got around to my mum saying goodbye to Janice though? Janice completely blanked mum and said goodbye to me and Sean only. To me, from that day forth I would never talk to her again.
Just the fact that one persons action could put a dampener on what was a good night hurt more than if she had not turned up at all. On hindsight maybe we should not have invited her but it was christmas. We all deserve a second chance and she blew it.
I sat up for a while after everyone had gone with my partner, her sister and James, just talking about the night. It was the first time they had met my brother and once again he had managed to charm the socks off them.
The phrase "Could sell snow to an eskimo!" springs directly to mind.