text:
Luca: exhausted.Mature
"No, no," he sobs, clinging to me. Oh for fucks sake. Grow some balls you useless faggot.
"Damien, get off! You know, I thought you liked me..."
"No. You were testing me," he whimpers, finally letting go.
"Testing you?" Maybe Gemme deserves an Oscar too. Damien sniffs and sits back against the wall of the bus, looking at me, but speaking to Gemme.
"On that truth or dare game the other night... you asked me to strip someone in the circle. You were watching to see who I went for. If I went for Luca, you'd know."
"Darling, I already knew. You wear your heart on your sleeve." I stop listening as he whines on. I need a shower. And not because I'm still all bloodied from earlier. I push myself up onto the sofa and watch as Rayn, being the terminal retard that he is, thinks that they're still pretending to be snakes. He slithers out of the bathroom and grabs Gemme's leg, kinda like Damien did to me.
She just sighs and rolls her eyes. "Damien, you know, every time you say you love Luca, it hurts me. Because I like you to and I don't want to see you hurt." Damien doesn't say anything, and Rayn, not put off by Gemme ignoring her, kisses her leg before moving over to Damien. He sits and stares at the homo without blinking.
Y'know how ecstasy makes you wanna suck things (it's why ravers take pacifiers with them)? I really wish that thought hadn't crossed my mind. I don't wanna know what those guys have been sucking all evening.
Actually... where's Phil?
"Umm, Gemme," I say, interrupting her little heart to heart with the drugged up queer, "have you seen Phil yet?"
"Umm, no, actually." She mutters, and I look around.
"Hmm..." I should probably go and find him, but I've already turned by back for a few minutes and the next thing I know, Gemme's dying on the floor. You can't really blame me for being kinda edgy about it.
"What's up?"
"Just wondering where he's got to. I hope he didn't overdose... I'm too tired to try and save anyone now," I mutter, looking out the windows, trying to see if he's just passed out on the ground outside.
"Yeah, you did heal multiple wounds, including one fatal one. Guess there's no point talking to these two about him." I look at Rayn. He's still staring at Damien blankly, and Damien is still whimpering like a little baby, glancing up at me.
"No, no there's really not," I shake my head. "Maybe it's not just me that needs to get clean, eh?"
"I could help with these, just don't wanna clean your mind."
"Mmm... I should really go look for him," I hesitate, still not so hot on the idea of leaving her alone. Well... pretty much alone.
"I'll be fine. I promise, go." I stand up and hug her quickly, kissing her on the lips before walking back outside. Phil, sure enough, is outside. He's stretched out on a bench, sucking his thumb, his trousers down by his ankles and he's staring at the sky like it's full of wonderful, entertaining things. I look up. It's cloudy. Shaking my head, I pull up his pants with telekinesis and lift him up, floating him back to the bus. I carry him straight upstairs and put him in one of the beds. He... doesn't actually notice.
"Right, bed time, I think!" I announce as I walk back down the stairs. Damien looks up hopefully at me. Rayn just keeps staring. I don't think he's actually blinked since he let go of Gemme's leg.
"Umm, what's up with him?" I just shrug and shake my head as I grab his upper arms, dragging him over to the stairs. He blinks at last and giggles. "Ahh." I don't wanna touch Damien though. Aside from his queerness, he has a tendency to latch onto me and stay latched on. Me no likey.
"Can you get Damien up here?" I ask as I pull Rayn up.
"Umm, could try..." She murmurs, tugging on Damien's arm. He switches his gaze to her as she pulls and he just whinges again.
"Why can't Luca carry me? He carried the others..."
"Because he knows how much I wanted to, come on." She grins and he lets her pull him up reluctantly. I manage to get Rayn onto one of the beds and he lays there staring, just like Phil. Only Phil's sucking his thumb still. I move out of the way as Gemme manages to get Damien up the stairs and leads him over to the bed furthest from mine.
"Just in time for the sunrise," I smile as I sit on my bed, ignoring Damien staring at me from his.
"Yeah." She smiles, sitting down next to me. "Not much of a sunrise from a bus though." She laughs as I put my arm around her, kissing her warmly.
"No. And I don't really intend to be awake to see it, either. I'm exhausted."
"After dying, beating the living daylights out of someone and tugging Damien off you? Me too." I smile and take my arm back, pulling off my well and truly fucked shirt off. I'm too lazy to find clean joggers so I just strip them off too and climb under the covers in my boxers. Gemme gets changed too and climbs in beside me. The moment my arm is around her and my head is on the pillow, I'm asleep.


text:
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subset: commoncrawl


text:
Casey Jindra and Nikki Call brave the elements in Kansas City – torrential rain, high winds, and Evan's hair nightmare made this one of the most harrowing OCR Warrior showdowns yet! Who will survive the weather and the course to come out on top as OCR Warrior Women's Champion?
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Item: MCB029
Hair Spray from Mill Creek
Regular Hold
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8 fl oz Liquid
This item is only available for shipment within the contiguous United States, excluding California.
INGREDIENTS: SD Alcohol 40 (grain derived), purified water, butyl ester of PVM/MA copolymer, jojoba oil, hydrolyzed keratin, panthenol (provitamin B5), sodium PCA, biotin, cysteine HCl, hamamelis virginiana (witch hazel) extract, benzophenone-4, dimethicone copolyol, aminomethyl propanol, vegetable glycerin, botanical aromas.
DIRECTIONS: Style hair as usual. Hold bottle 10-12 inches away from hair and spray evenly.
Caution: Flammable! Do not use near open flame or while smoking.
Made in U.S.A.
.54 lbs
Hair Spray from Mill Creek
Regular Hold
With keratin, jojoba and panthenol
No artificial colors or build-up
Regular Hold Hair Spray from Mill Creek uses natural and botanical ingredients to bring you naturally styled hair. It features keratin, jojoba and panthenol, and no artificial colors. This blend of effective ingredients brings you natural-looking hair that's not stiff or sticky. It rinses clean with any shampoo. Made in the USA. Cruelty-free.
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Canon EOS 5D Mark II In-depth Review
|17 Previous
18 Features
|19 Next
Image parameters (contd.)
Saturation adjustment
Saturation adjustment allows you to control the strength of color in the final image. At the -4 setting you get quite a muted color response but this could be useful for post-processing, anything above +2 can lead to color channel clipping.
|25% crop
Color tone (hue) adjustment
Color tone subtly adjusts the hue of the image, a negative setting makes red tones appear more blue/purple, a positive setting makes them appear more yellowish. Each step equates to an approximate 4% hue shift, hence +4 = +16° hue shift.
|25% crop
- 1 Introduction
- 2 Specifications
- 3 What's New
- 4 What's New
- 5 Body & Design
- 6 Body & Design
- 7 Body & Design
- 8 Operation & Controls
- 9 Operation & Controls
- 10 Displays
- 11 Displays
- 12 Menus
- 13 Menus
- 14 Performance
- 15 Features
- 16 Features
- 17 Features
- 18 Features
- 19 Video
- 20 Software & Raw
- 21 Photographic tests (Noise)
- 22 Photographic tests (Noise)
- 23 Photographic tests (Noise)
- 24 Photographic tests (Noise)
- 25 Photographic tests (DR)
- 26 Vignetting/Shading
- 27 Photographic tests
- 28 Compared to
- 29 Compared to (JPEG)
- 30 Compared to (JPEG)
- 31 Compared to (JPEG)
- 32 Compared to (JPEG)
- 33 Compared to (RAW)
- 34 Compared to (RAW)
- 35 Compared to (RAW)
- 36 Compared to (RAW)
- 37 Compared to (sRAW1)
- 38 Compared to (High ISO)
- 39 Compared to (Resolution)
- 40 Conclusion
- 41 Samples
I own it
I want it
I had it
Discuss in the forums
what would you say is a fair price to purchase this camera second hand, and how many cycles would you say are acceptable?
I work in Nyc as a fashion photographer and I have to say the the 5d series are the most used cameras out side of medium format cameras .Ive been shooting with the mark 3 for over a year after shooting with the mark 2 for 2 years great both great cameras. You can see the shots I've taken with it for my work on my website www.brianschutzaphotography.com hope it helps!! also note I only shoot RAW format.
Was it really 2009? I'm still in the first flush of my love affair with this camera. And I'm still fathoming the depths of its capability. Okay, she's got a lot of paint missing these days, but the images are still magic. Whenever I use another camera, I sigh and wonder why I didn't use the 5D2.
A brief history of photography:
silver chemistry
flexible roll film
5D Mark 2...
As I know when the original 5D debuted three years ago, it wasn't clear why most enthusiasts would want such a camera. Though it captured excellent, high resolution images, it was slower and bigger and more expensive. Today the market has changed significantly, and it's clear that the market is ready for full-frame digital SLRs that can turn out high image quality. High quality is one thing, but being a camera that can deliver high quality over a wide range of lighting conditions and different ISO settings is what makes the Canon 5D Mark II such a compelling choice, and a clear Dave's Picks.
It's really very very good.
Join DPReview editors Rishi Sanyal and Carey Rose on Facebook Live as they share their experience and answer your questions about the new Sony a9, Wednesday at 9:30 AM Pacific time. Click here for additional details and time zones
German media reports that the founders of the company behind the Panono 360-degree ball camera have filed for bankruptcy at a court in Berlin. Read more
With a claimed 800 new custom parts, Microsoft's updated Surface Pro comes with the latest Kaby Lake processors, better battery life, a new hinge, plus the Surface Pen is updated as well. Read more
DW Photo is attempting to resurrect the Hy6 medium format camera, though the legal tangles of its development may stop it being branded Rolleiflex.
The Kodak EKTRA, the company's 'camera first' smartphone, is now available to purchase in the United States. Read more
Apple and Nokia have settled their years-old patent dispute. Apple will make an undisclosed payment to Nokia and sign a licensing agreement related to digital health products with the Finnish company.
David Gibson, one of Britain's best known street shooters, shares all.
Photographers from the SKYGLOW project travelled 150k miles and took 3 million photos in increasingly rare locations: those without light pollution.
The world's fastest 200mm was produced for 16 years. In that time, only 8000 were made.
Photokina, the biennial photo industry trade show in Cologne, Germany, has announced that it will become an annual event beginning in 2018, and expand its focus to additional areas of imaging technology. Read more
No mic socket? No problem. In this video, Daniel Peters at Photo Gear News shows you how to make a lapel microphone using just a smartphone and a pair of earbuds.
How does the iPhone 7 Plus stack up against the Arri Alexa cinema camera? Watch this short video to find out.
Canon Australia's video series "The Lab" is designed to make photographers experiment and think outside the box. In the latest video a group of photographers create images based on their sense of taste.
The GH5 is expected to get a firmware update this summer to support 400Mbps internal recording. NewsShooter explores what memory cards you'll need to make it work.
Microsoft's new Surface Pro offers Intel's latest processor generation and improved battery life.
Riding a mountain bike downhill is dangerous enough in daylight, but potentially lethal at night. Which is where drones come in.
Rumors abound that Canon (and maybe Nikon) may produce a mirrorless camera based using their existing DSLR mount. Does this guarantee immediate great lens choice or a perpetually second-rate experience? Read more
According to rumors, the next camera from Nest will be able to capture 4K video, though that resolution will be only used for 'virtual' pan and tilt functions.
Boundary's Prima 'fully modular' backpack is expandable to 30L and has a removable camera case and tablet sleeve. Early Kickstarter backers can get one for $189.
Stanley Greene captured 'brutally honest' photographs in the war zones of the Middle East, Chechnya and Georgia. He was also one of the few African-American photographers working internationally.
Owners of Leica M cameras that suffer from peeling CCDs will be able to claim a free repair in the future so long as the camera was purchased within five years of the fault becoming apparent, the company has announced. Read more
The Carl Zeiss Jena BIOTAR 75mm F1.5 Red T lens is very rare and priced accordingly. It can be yours today for the low, low price of $15,000.
The MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL) has developed a drone that does not require any human control for recording tracking shots. Read more
In this terrifying video, Iraqi journalist Ammar Alwaely narrowly misses a sniper's bullet, which takes out his chest-mounted GoPro. Warning: strong language. Watch the video
A new report expects action camera growth to increase about 15% by 2021, with Ultra HD cameras driving demand. Read more
Profiles for Adobe Photoshop and Lightroom have been released for Irix's ultra-wide 11mm and 15mm primes. Like all profiles, these correct for distortion and vignetting.
An upcoming firmware update from DJI will cripple its drones unless they are 'activated' on the company's website. Live streaming will be turned off and flight radius/altitude will be limited.
Brent from ShareGrid rounds up the 10 most common products filmmakers are renting from one another for productions; chances are good you own one or more of them.
DaVinci Resolve is making strong moves to compete with Premiere and Final Cut Pro, including affordable control panels for colorists. According to Premium Beat, they're really good.
If you are not planning to fly your drone commercially you are not required to register it with the FAA anymore. This decision was handed down by a federal court in Washington, D.C.


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|Message view
|« Date » · « Thread »
|« Date » · « Thread »
|Ian Holsman <li...@holsman.net>
|Re: Proposed connection state diagram
|Mon, 05 Sep 2005 12:21:37 GMT
Brian Pane wrote: > On the subject of asynchronous write completion, I've drawn a connection > state model that > combines the current state transitions of the event MPM with new states > for write completion > and the handler phase. > > Comments welcome... Am I missing any state transitions (particularly for > error cases)? > Should there be an "access logger" state? Are there other good use > cases to consider > for a nonblocking handler feature, besides mod_proxy? > > <http://www.brianp.net/work/opensource/apache/async.html> > > Thanks, > Brian > It's late over here.. so I'm sure I'm being stupid.. but here are some things I can't see transitions for: are you missing the case where the client disconnects mid-request (CONN_STATE_READ_REQUEST_LINE -> Connection_deleted) and when the client disconnects mid-response? CONN_STATE_HANDLER/CONN_STATE_WRITE_COMPLETION -> Connection_deleted) case where the client connects/disconnects (TCP-port check) as for non-blocking cases.. when the module needs to issue a TCP/UDP connection to a 3rd party. (eg.. gets a stock quote or performs a LDAP check for authorization, or wordpress doing a trackback/pingback) what about mod-rewrite spawning a program to do a rewrite mapping? like I said at the start.. I'm sure I'm being stupid and not understanding the questions ;-) --ian
|View raw message


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text:
Photo by ISIPhotos.com
By RYAN TOLMICH
HARRISON, N.J. — After arriving only Thursday from Brazil after finishing his time with the Australian National Team, Red Bulls head coach Mike Petke was looking to get Tim Cahill into the game against Toronto FC, albeit in a totally different situation than the 2-1 hole the Red Bulls were facing at the time of Cahill's introduction.
"I was hoping to bring Tim on in the 88th minute, up 3-0 so the fans could clap him for the wonderful World Cup he had," Petke said. "Obviously, things change with the score, with the way the game went and we felt to bring Tim on for 15-20 minutes, perhaps something could happen."
Something did happen for Cahill and the Red Bulls, as the Australian played a key role in the eventual game-tying goal, scored by Bradley Wright-Phillips in the third minute of second half stoppage time to save the Red Bulls a crucial home point in a 2-2 draw with TFC at Red Bull Arena. The goal was Wright-Phillip's league-leading 12th of the season.
TFC opened the game with a barrage of chances, overwhelming a young Red Bulls back line who conceded to bend but not break. However, after spending much of the first half on the back foot, it were the Red Bulls that opened the scoring.
Red Bulls left back Ambroise Oyongo, who was making his first MLS start, picked up his first MLS assist by finding the head of Peguy Luyindula in the 36th minute for the game's opening goal.
Luyindula, who missed a similar header just 13 minutes prior, will get credit for the goal, but it is Oyongo who deserves credit for the play, as the 23-year-old Cameroonian found space on the left side, cut back and placed a cross right into the path of Luyindula.
TFC answered back via a Defoe strike 10 minutes after the start of the second half, as the star striker smashed home his eighth in nine career MLS games. Much like the Red Bulls' opener, TFC took advantage of space down the wings, as the speedy Dominic Oduro found space on the right and found a streaking Defoe, who directed the ball home.
"It was just a run across the front post," Defoe said. "Getting that space just to get my shot on. I just guided it on. It happened so quick, but I was happy to see it go in."
Prior to the finish, Defoe had been largely held in check by the inexperienced Red Bull backline, especially young centerback Matt Miazga. However, Defoe's ability to appear out of nowhere was something Henry pointed to after the game.
"You don't see him a lot in the game, but when you see him, he usually does score," Henry said of his former North London Derby rival. "That's him though. He doesn't see who's around him and he tries to smash it. He got a good ball from Oduro… He buried it. That's what he does."
This paved the way for a highlight reel strike from TFC sub Gilberto, who had failed to register an MLS goal to this point. The Brazilian put an extra special exclamation point on his breakthrough strike by dismissing Defoe from the dead ball and firing into the top corner, leaving Red Bulls goalkeeper Luis Robles helpless on a 25-yard rocket of a free kick.
"Sometimes as players, you just get feelings for things,"said TFC head coach Ryan Nelsen. "Obviously, Gilberto had a feeling that he was going to do something. Unfortunately, his English isn't that good, so he couldn't say 'Jermaine, I've got a funny feeling I'm going to put this one into the top of the net."
"To be fair, he looked confident," added Defoe, who appeared frustrated prior to Gilberto's finish. "When he stepped up and had that feeling, I thought he was going to score. You can see from his celebrations. I'm so happy for him."
The happiness didn't last long, as the Red Bulls finally brought on Cahill in the 78th minute and the Australian was received with a standing ovation from the Red Bulls crowd.
Cahill quickly made his presence felt and while the Red Bulls struggled to thread in passes around the box, Cahill played a huge role in the game-tying-goal. A long ball sent into the box in the third minute of stoppage time was re-directed into the path of Wright-Phillips, who slotted home for his league-leading 12th goal of the season.
Despite conceding the late equalizer, Nelsen is far from disappointed in his team's effort, citing the importance of ever-elusive road points.
"Any point away from home in a league full of parity is priceless," Nelsen said. "Three points are obviously extremely good, but that point against the MLS Supporters Shield holders is still very valuable for us.
"It shows, I think where Toronto FC have come in the last 18 months, that we're all gutted here that we didn't pick up three points and that we didn't put ourselves in a very, very good position in the table, but a point is very valuable."
TFC will look to rebound with a short turnaround, as the victors visit the Chicago Fire Wednesday, much to the pleasure of Defoe.
"Sometimes it's good when there's a lot of games in a short space of time because if you get a little disappointment, you can sort of like bounce back within the next game," Defoe said. "Obviously, we're disappointed we didn't win today. I thought we deserved to win. They scored a late-minute goal. Hopefully, we learn from our mistakes and next time, we just see the game out."
Meanwhile, the Red Bulls will look to build on the momentum of a last-second draw on the Fourth of July when they head to Houston to take on the Dynamo.
Hand Solo
This game made MLS history: the most black players ever starting on the pitch at once (15). The Red Bulls started 8 blacks for the first time in franchise history, plus Alexander, Miazga, and Robles). Toronto started 7 black players, as well as Bendik, Caldwell, Bloom, and Osorio. Only three of these fifteen players have American citizenship, and Doneil Henry (Canadian) makes four for the North American tally.
With the MLS so carefully crafted toward salary and international allotment, I wonder exactly why and how two 'power market' teams came to trend in this direction.
Thanks to the department of useless statistics for the info
I didn't know there were stats on players' races. Focusing on race is pretty lame. Who cares?
Quit whining about US soccer
How the heck do you know that ?
Serious question.
MLS has no appearant issues with race biases that I can see, should I be concerned ?
Red Bull Nats
I thought Toronto was the better team but very pleased the Red Bulls were able to steal a point here. Cahill had a tremendous and immediate impact. He won at least a dozen headers in what must have been a five minute span. We were just lobbing long balls into the box and some how, Tim was getting his head on everything. It was ugly football but at the same time you could see the havoc it was reeking on Toronto. When the goal came, it was almost no surprise. As a fan, you have to love Cahill. He just gives it everything he has all the time.
Spot on and right there is a big reason we've been very mediocre this season. Not enough Tim Cahill


text:
Download document:
Bermuda Shipping News — July 2013 - .PDF file.
The Minister of Economic Development of Bermuda, Grant Gibbons, recently announced the acceptance of the Bermuda Department of Maritime Administration (DMA) into the US Coast Guard QUALSHIP 21 (quality shipping for the 21st century) programme for its commitment to safety and the quality of its fleet. As such, going forward, owners of Bermuda-registered vessels will not be targeted for inspection in US waters by the US Coast Guard.
The QUALSHIP 21 programme provides incentives for well-run, quality vessels that are operated responsibly, and are typically found with few or no deficiencies. These quality vessels are recognised and rewarded for their commitment to safety and quality.
The Bermuda Ship Registry is a quality international ship registry that takes pride in the high standards of safety and pollution prevention of its ships. This fact is reflected by it being continuously listed on the 'White List' of the Paris MOU showing Bermuda-registered vessels as having a very low detention rate, which is testimony to the Bermuda Registry's commitment to quality and safety. This means that Bermuda-flagged vessels suffer fewer delays while in port and can be used more profitably…
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KAHU-FM 91.7 has returned to the airwaves in Pahala, Naalehu and other isolated areas of Hawaii island's southern half.
Hawaii Public Radio bought the previously silent station earlier this year and restored radio service to the southernmost part of the United States Wednesday.
The station carries the HPR-2 program stream originated on KIPO-FM 89.3 in Honolulu.
"It is absolutely essential that this population be served, particularly when it comes to emergencies and civil defense," said Michael Titterton HPR president and general manager.
While KAHU initially will only be heard in the Ka'u District, HPR plans to incrementally rebuild and expand the station's signal coverage throughout East Hawaii. HPR-2 can be heard in West Hawaii KIPM-FM 89.7 and KHPH-FM 88.7.
The HPR-1 program stream can be heard on all islands.


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text: Every time I open a folder with an MPG ( or MPEG) file,((( In windows 7 Build 7000 & RC1 ))) Windows Explorer crashes. (don't Problem with wmv file) I used CCleaner, and even installed the Win7 Codec pack and removed broken codecs, and still, I am having the same problem. Anyone help please?


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Zilwa Attitude is situated on the north coast of Mauritius, in Kalodyne, close to the fishermen's village of Grand Gaube. The 214 rooms, some more family orientated others quieter and slightly in the background for couples, have a rustic atmosphere and a contemporary charm. It is the ideal pl...
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Hampton Inn Ann Arbor-South
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Backpack Ready to Go
... of my mind for having embarked on this journey in the first place), I will walk another 90km (56 miles) to Finisterre (a village at the Atlantic Ocean, historically known as "the ends of the earth"). Plans are to return to the good old USA on Oct. 27th.
Wear One... Wash One: My loaded backpack (with trekking poles) weighs in at a svelte 10lbs/4oz. This required my packing only the barest of necessities. Thus, only two sets of ...
Grab the Klennex for this one
... we looked at the markers.
These were only a few that I took.
So touching.
Steve and Kim
Here's the ...
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... to deliver to the community that we will be working with.In honesty, I've always felt compelled go on a service trip, and feel lucky that the stars have aligned, and my family has so graciously figured out a way that now is the time to make it happen! How is it all happening? This trip is an enrichment class via the DREAM Organization for credit through Washtenaw International HS. Kayley had never been out of the country without us, never been interested ...
Game 3 - Notre Dame at Michigan
... for best player. On the Notre Dame side, receiver T.J. Jones pulled down 9 receptions for 94 yards and a touchdown while fellow receiver Troy Niklas had 6 receptions for 76 yards and a touchdown of his own. But, they lost. So, let's look at the Michigan side of the equation. An obvious choice would be quarterback Devin Gardner, who threw for 294 yards and 4 touchdowns while leading the team with 82 yards rushing ...
112,450 Rabid Fans
Nance and Kath (Nancy Culotta and Kathy Reilly) live about 6 blocks away from THE BIG HOUSE, the largest college football stadium in the country, home of the Michigan Wolverines. And as luck would have it, Nancy - Mary's best friend from Holy Child High School in Potomac, Maryland - as you now know, works for the University with a connection to the athletic department ...


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Central Piedmont - North Carolina
1701 - John Lawson, Surveyor General of the Province of North Carolina, declared he has seen no other land that exceeds the land of Rowan County.
1749 - The Cathey settlement is established on the head waters of Second Creek by James Cathey.
1753 - Rowan County is Established and land is deeded to the congregation for "ye lower meeting house." Later to become Thyatira Presbyterian Church.
1762 - Millbridge community is settled.
1794 - Dr. Samuel McCorkle opened the Zion Parnassus Academy - First normal school in the United States - near Thyatira Church.
1823 - Joseph Kerr constructs Kerr Mill on his 1500 acre plantation located between Sills and Cathey's Creeks.
1861-1865 - Dr. Samuel Kerr, son of Joseph Kerr, strongly supports the Confederacy and by the end of the war Dr. Kerr was destroyed financially.
1865-1872 - Kerr Mill operates on a small scale to serve the needs of the small group of tenant farmers who were working the run down and neglected fields of the Kerr Plantation.
1872 - James Samuel McCubbins purchases 593 acres, the Kerr Mansion, and the mill for $8,140.
1876 - James McCubbins operates Kerr Mill using an undershot wheel which was fed by a long mill race and canal.
1887 - McCubbins and his partner, John Harrison, complete retooling of Kerr Mill to a roller mill powered by a steam engine.
1895 - John W. Page acquires complete title to Kerr Mill.
1900 - Pleasant Owen Tatum purchases the mill from John Page and operates the mill until 1908.
1908 - James Wiseman Sloan purchases Kerr Mill for $3,000.
1925 - Kerr Mill is now powered by a Bessemer diesel engine.
1927 - James W. Sloan sells Kerr Mill to his nephew, James Andrew Sloan, for "one dollar and other valuable considerations."


text:
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21:38 19th November 2010
Burton slipped to a 3-1 defeat after an inspired second half performance from promotion hopefuls Bury. The sides went in level at the break following James Collins equaliser after Mike Jones opening goal, but a Tony James error allowed Nicky Ajose to steal in to make it 2-1 early in the second half and Efe Sodje's bullet header from a corner wrapped up the points for the Shakers.
Paul Peschisolido chose to name an unchanged eleven for the Friday evening visit of Bury to the Pirelli Stadium. Top goalscorer Shaun Harrad remained on the bench after coming on to grab the winner 8 minutes from time at the b2net Stadium last weekend.
Centre back Nathan Stanton recovered from the groin strain he picked up against Chesterfield to take his place in the starting line up alongside Tony James.
The Brewers headed into the match on a foggy evening in Burton knowing that a win would put them level on points with the play off positions, with the rest of the league fixtures taking place on Saturday.
Scott Malone sparked the first danger for the Brewers, his cross across goal just eluded Aaron Webster and James Collins before skidding out of play just beyond the far post.
But it was the visitors who took the lead in the 10th minute. Mike JONES picked up the ball 40 yards from goal and went past Jacques Maghoma before cutting inside and unleashing an unstoppable 25 yard drive into the top right corner of Adam Legzdins' net.
Ryan Lowe had another chance for Bury in the 16th minute but curled his 18 yard shot high and wide. It had been Bury though looking the brighter in the early stages.
But the Brewers responded with a flowing move three minutes later culminating in John McGrath's deep cross from the left being headed just over the bar by Aaron Webster. Webster then fizzed a low shot narrowly wide from 25 yards two minutes later after Ryan Austin's cross was headed back out of the area.
Burton levelled the match in the 29th minute when James COLLINS followed up Adam Bolder's 25 yard shot which was parried away by Owain Fon Williams. Collins beat the Bury defender to the rebound to grab his fourth goal in Brewers colours.
Bury nearly went back ahead straight away when Steven Schumacher's freekick went through the wall, Legzdins producing a superb save after seeing the ball late and then reacting even better to keep out Efe Sodje on the rebound.
The Brewers ended the half with some lovely football. Maghoma, Bolder and Penn were all involved before Malone swung the ball over just to high for Collins to get a header on goal. Penn then surged down the left and saw his cross evade Fon Williams and bounce off the top of the crossbar out of play.
Half time: Burton Albion 1 - 1 Bury
Peter Sweeney came on for Steven Schumacher for Bury in the only change made at the break.
Bury retook the lead in the 53rd when Tony James misjudged a long ball forward allowing Nicky AJOSE to steal in and lob the ball over Legzdins. Shaun Harrad was brought on for Russell Penn as Peschisolido responded to going a goal down.
Andy Haworth the almost extended the visitor's lead, twisting and turning on the edge of the area before firing a fierce shot across Legzdins which smashed against the crossbar. Ajose then shot dorectly a Legzdins two minutes later when space opened up for him.
Burton should have levelled again in the 62nd minute when Adam Bolder headed Shaun Harrad's cross wide following good play from Webster and Malone. Lewis Young then came on for Jacques Maghoma.
Bury continued to pressure though and went close with a succession of corners in the 71st minute. And they extended their lead in the 73rd minute with an Efe SODJE bullet header from Peter Sweeney's corner kick.
With the Brewers trailing Paul Peschisolido made his final change, bringing on Jimmy Phillips for John McGrath in the 79th minute.
Adam Legzdins saved in the 85th minute from Peter Sweeney before the Brewers took the ball up the other end with Shaun Harrad testing Fon Willians from 18 yards.
Aaron Webster should have grabbed one back for the Brewers in the 89th minute, putting his free header wide from Scott Malone's free kick.
Nicky Ajose then missed a great chance to make it 4-1, rolling his 8 yard shot just wide of Legzdin's left hand post.
Full time: Burton Albion 1 - 3 Bury
Attendance: 2738
Scorers: Brewers - Collins (29) Bury - Jones (10) Ajose (53) Sodje (73)
Referee: Mr G.D Scott
Brewers: LEGZDINS, WEBSTER, STANTON, JAMES, MCGRATH (PHILLIPS 79), AUSTIN, PENN (HARRAD 54), MAGHOMA (YOUNG 62), COLLINS, BOLDER, MALONE. Subs: POOLE, MOORE, CORBETT, HARRAD, WALKER, PHILLIPS, YOUNG.
Shakers: FON WILLIAMS, PICKEN, SKARZ, LEES, SCHUMACHER (SWEENEY 46), HAWORTH (WORRALL 79), JONES, LOWE (JOHN-LEWIS 89), SODJE, MOZIKA, AJOSE. Subs: SWEENEY, WORRALL, CARLTON, JOHN-LEWIS, BENNETT, GUNNING, BRANAGAN.
TAKE a look back at the ups and downs of the 2016/17 Sky Bet Championship season as a Burton Albion supporter.
THE line-up for the 2017/18 Sky Bet Championship season is almost complete.
KEY dates for the 2017/18 season have been confirmed by the EFL as the Sky Bet Championship season returns on the first week in August.
JACKSON Irvine has been called up to Australia's provisional 30-man squad for the 2018 FIFA World Cup Qualifier against Saudi Arabia at Adelaide Oval on June 8.
DEFENDER Shaun Barker has signed a six-month deal with Burton Albion Football Club.


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Home > Low Fat Recipes II > Wild Rice Squash Risotto
Wild Rice Squash Risotto
Low Fat Recipe
This creamy Wild Rice Squash Risotto dish conjures all the taste and texture of risotto without the time-consuming stirring procedure.
2/3 cup water
1/3 cup uncooked wild rice
1-1/4 cups diced peeled acorn squash
2 poblano chiles (about 1/4 pound)
1 cup fat free reduced sodium chicken broth
1-1/2 cups cooked Arborio rice
1/2 cup (2 ounces) grated fresh Romano cheese
2 tablespoons butter
1 tablespoon chopped fresh or 1 teaspoon dried thyme
1/4 teaspoon salt
1/4 teaspoon black pepper
Recipe Directions
Bring the water to a boil in a medium saucepan. Add wild rice; cover, reduce heat, and simmer 1 hour or until tender. Set aside. Cook squash in boiling water 4 minutes or until tender. Rinse squash with cold water; drain. Preheat broiler.
Cut the poblanos in half lengthwise; discard the seeds and membranes. Place pepper halves, skin sides up, on a foil-lined baking sheet; flatten with hand. Broil for 10 minutes or until blackened, turning occasionally. Place in a zip-top plastic bag; seal. Let stand 15 minutes. Peel and chop poblanos. Set aside.
Bring the broth to a boil in a large saucepan. Add the cooked wild rice and Arborio rice; cook 2 minutes, stirring constantly. Reduce the heat to medium, and add the cheese and butter, stirring until the cheese melts. Add squash, poblanos, thyme, salt, and pepper; cook 2 minutes or until thoroughly heated.
Nutrition Information
Recipe makes 4 servings
Serving size: 1-cup
Calories: 322; Fat: 10g; Protein: 10.7g; Carbohydrates: 47.8; Fiber: 2.4g; Cholesterol: 30mg; Sodium: 500mg


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UK: Tate & Lyle to dispose of molasses business
Food ingredients group Tate & Lyle is to sell its molasses business to UK grain importer W&R Barnett for GBP67m (US$105.6m).
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Online 9 months ago
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I'm currently working full time and living in a 3 bedroom house with 7 people! I know it's crazy!.. So I am looking for a nice place where I can have space to myself as I work full on hours.. If you have anything that I may be interested in please send me a message. I would love to meet up and discuss things further.. Thanks :)
Ruby is also interested in Teaming-Up and starting a new share house.


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The purpose of this project is to sample groundwater in 5 new "sentinel" monitoring wells, conduct additional groundwater monitoring at other existing wells near the former Atlas E missile site on the Coeur d'Alene Reservation and assist in updating the Coeur d'Alene Tribe's Strategic Project Implementation Plan
****Proposals must be received by 4:30pm PST on Friday March 17, 2017****
RFP download here
The Coeur d'Alene Tribe is requesting proposals to assist the Tribe with the identification and compilation of information on potential Brownfields sites, research assessment and clean-up opportunities on the Reservation, research and develop a draft public participation plan, and research clean-up plans to better understand the process. Additionally, the Tribe would like assistance in developing a criteria to prioritize potential Brownfields sites for assessment, select one potential site to assess, develop a site eligibility form for the site, complete a Quality Assurance Project Plan and Sampling and Analysis Plan for the site, conduct a Level I and II Environmental Site Assessment and complete assessment reports, develop next steps for the site and identify potential funding sources for clean-up if needed. The Tribe is planning for these activities to be completed by September 30, 2017.
Download Brownfield RFP
The Coeur d'Alene Tribe's Environmental ProgramsOffice (EPO) is seeking a qualified entity to provide on-site electronicdocument imaging services in Plummer, Idaho using a Tribal DocuWare license fora minimum of 30 file boxes and up to 40 file boxes. Most of the files are 8.5 x11 inches but some pages are larger such as legal sized. Some of the files aredouble-sided and some are single-sided. The files in the boxes will need to beprepared for scanning in terms of removing staples, binder clips, etc. Thisproject is expected to occur during the month of September
****Reply by Sept 9th 2016****
Download RFP here
CDA Tribe Natural Resources RFP: Groundwater monitoring for the Former Atlas E Missle Facility on reservation
Proposals must be received by 4:30pm PST Friday February 27, 2015
Download RFP link information
Please contact the Tribe at 208.686.1800 for more information.


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Arsenic (As) is not easily dissolved in water. Therefore, if it is found in a water supply, it usually comes from mining, metallurgical operations or runoff from agricultural areas where materials containing arsenic were used as industrial poisons. Arsenic in water has no taste, odor or color. Arsenic and phosphate easily substitute for one another chemically; therefore commercial grade phosphate can have some arsenic in it. Arsenic is highly toxic and has been classified by the EPA as a carcinogen. These cartridges contain an Arsenic-selective Resin specifically designed to filter Arsenic V and Arsenic III.
These cartridges contain a combination of special Arsnic-selective resin, specifically designed to filter Arsenic V and Arsenic III, Eagle Redox Alloy® 6500, Eagle Redox Alloy® 9500, and Shell GAC media.
$57.00Arsenic Removal Water Cooler / Reverse Osmosis Filter Cartridge View full product details
Removes chlorine, chloramines, VOC's, THM's, pesticides, sulfur, heavy metals, hydrogen sulfide ("rotten egg" odor), iron oxides ("rust water"), dirt, sediment and other odors. Water travels through both ERA-6500 and ERA-9500 media for de-chlorination and enhances pH balance. Periodic reversing of disk ensures balanced filtration, eliminates the potential for channeling, and extends the useful life of the disk.


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Silvio Berlusconi's declining political fortunes and never-ending legal woes were yesterday overshadowed by claims that one of his inner circle had been held hostage in a bid to extract €35m from the ex-premier.
The 76-year-old billionaire's trusted accountant, Giuseppe Spinelli, whose job it was to hand envelopes stuffed with cash to young women attending the tycoon's notorious adult parties, has told police that six armed men kept him and his wife captive in their home on 15 October.
Police announced yesterday that three Albanians and three Italians had been arrested in connection with the incident. The ringleader was named as Francesco Leone, a 51-year-old convicted criminal with links to the Sacra Corona Unita – the Puglian mafia.
Mr Spinelli, 71, said the masked men forced him to call Berlusconi to communicate their intention to sell the mogul documents that could extricate his Fininvest holding company from a €560m compensation payment it owes a rival firm.
The head of Milan's anti-mafia police squad Alessandro Giuliano, said: "According to the account of Spinelli, while he was returning home on the 15 October, he was threatened by hooded men on his door step. He was then held captive in his home for the whole night, until nine the next morning when he was made to make a direct phone call to Berlusconi."
But within hours of recounting Mr Spinelli's version of events, the Italian press began to ponder the stranger aspects of the case. It was unclear why Mr Spinelli waited 36 hours after his captors had gone before calling the police or why he was then whisked away by Berlusconi's personal bodyguards. It was reported yesterday that he has since been living in a secret location.
Niccolo Ghedini, Berlusconi's lawyer, said he was confident the documents brandished by the bandits were false: "We never saw them, but judging from what they were claiming, I would say we're talking about a complete bluff," he said.
Mr Spinelli was told by his captors that the evidence could reverse the fortunes of Berlusconi's business empire as it appeals against the giant compensation payment it was ordered to pay the CIR company, owned by the rival mogul Carlo de Benedetti.
Fininvest wrestled control of the Mondadori publishing house from Mr De Benedetti in 1991, in a takeover battle settled in a Rome courtroom. But in 2007 a court in Milan found Berlusconi's former lawyer and close ally Cesare Previti had bribed one of the two Rome judges to rule in favour of Fininvest. Berlusconi himself was cleared of responsibility.
A verdict in the "Rubygate" case, in which Mr Berlusconi is accused of paying for sex with an underage girl and of abusing his office to cover up the crime, is expected in February next year.
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|Publication number
|Publication type
|Application number
|Publication date
|Mar 20, 1984
|Filing date
|Jun 11, 1981
|Priority date
|Sep 27, 1980
|Fee status
|Also published as
|Publication number
|Hans J. Heinrich, Dieter Schutt
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Non-Patent Citations (1), Referenced by (44), Classifications (11), Legal Events (4)
|External Links: USPTO, USPTO Assignment, Espacenet
This invention relates to a priority level controlled interrupt handler unit for providing rapid handling of interrupt requests.
Rapid handling of interrupt requires is an important function in electronic data processing systems, particularly in systems for real time process control. For example, in process control systems, interrupt requests from many data sources, associated with sampled process variables, e.g. temperature, pressure, humidity, flow quantities, etc., may require rapid real time analysis potentially leading to changes in process execution.
Similarly, in other data processing applications requiring intermodule communication and control, rapid and adaptive processing of interrupt requests is desirable. For example housekeeping functions of structured programs performed in a multi-programming mode may require rapid and adaptive execution for optimal effectiveness.
Previous solutions for rapid servicing of interrupt requests are based on very expensive devices having complex circuit structures. Although such devices may provide requisite speeds of reaction they are unreliable due to their complicated structures.
For example, German Auslegeschrift No. 1 234 059, discloses a control device applicable to a multi-processing system for allocating priority levels to various computers of the system which mutually assign or re-assign programs or program parts having different priority levels. Each computer receives dynamically only the priority level of the program part it is processing at the moment, as long as it contains said particular program part. The system allocates program levels under control of a shift register structure which assigns priority levels in fixed associations with groups of shift stages. The assignment is conducted by shifting a computer address, or other identification number, in the shift register in the direction associated with increasing or decreasing priority levels, depending on the priority of the program part being executed in the addressed computer.
However, this device does not provide priority-controlled servicing of interrupt requests having differing priority, but merely allocates priority levels to different computers of a multi-processor system.
A priority level controlled interrupt handler device which is particularly applicable to data processing systems offering medium to lower range performance but requiring extremely fast reaction to interrupt requests, is disclosed in U.S. Pat. No. 4,172,284 granted Oct. 23, 1979 to H. J. Heinrich et al. That device includes a shift register having stages permanently and fixedly associated with specific interrupt levels (priority levels). The stages are connected to associated comparison units for comparing interrupt levels indicated in shifted interrupt requests with interrupt levels associated with respective stages. The device also contains a stack which buffers priority sublevel functions also contained in the interrupt requests. For controlling entries into this buffer, circuits are provided for testing the state of the stack (full, not full, empty, etc.). Each stage is also associated with a base address register and an instruction address register, the latter receiving an address formed by adding a function associated with the respective interrupt level to the base address. The address received by the instruction address register indicates the first instruction of an interrupt routine required for the execution or servicing of an interrupt request of a corresponding interrupt source.
Due to the serial transfer of interrupt requests through the shift register and the fixed allocation of interrupt levels to the stages of the shift register, and thus to the control facilitates connected to the outputs of the shift register, the associated request servicing operations are too slow for many applications and not sufficiently adaptable.
Therefore an object of this invention is to provide interrupt handler apparatus having faster reaction speed and better adaptability than the apparatus characterized above. Embodiments and features of this apparatus are characterized in the accompanying claims.
A priority level controlled interrupt handler device in accordance with this invention is faster, more adaptable, and more reliable than the abovementioned known devices. Faster, because it stages the interrupt requests in an associative memory, which permits parallel access to requests and concurrently preprocesses requests of different interrupt (priority) levels in linear arrays of independent preprocessing elements.
Adaptability is achieved through dynamic allocation of level assignments to the preprocessing elements and through a masking feature disclosed herein.
In addition to increasing reaction speed, the subject hardware controlled preprocessing of interrupt requests also provides better reliability since it does not require program level switching, table lookup or other switching functions associated with prior systems.
Other significant advantages derive from the present direct generation of memory starting addresses for the interrupt handling routines, and the use of programmable base address registers to improve memory utilization.
Depending on the complexity of its combinatorial logic a preprocessing element in accordance with the present invention can be packaged on a plug-in card, or in a linear array of micro-processors.
The subject invention can support concurrent execution of plural interrupt routines relative to one interrupt level, if plural instruction address registers are provided for that level.
The foregoing and other objectives, features and advantages of the subject invention will best be understood from the following description when read in conjunction with the accompanying drawings.
FIGS. 1, 2 and 2A contain block diagrams showing a priority level controlled interrupt device in accordance with the invention;
FIGS. 3A to 3D illustrate the data format of an interrupt request at various stages of handling in the subject device;
FIG. 4 contains a flow diagram illustrating operations of the subject device;
FIG. 5 contains a block diagram of a mask circuit and a transformation table;
FIG. 6 contains a pulse waveforms demonstrating the time relation of two clock series T and t;
FIG. 7 contains block diagrams of two gate enable pulse generators, and
FIG. 8 contains flow diagrams illustrating concurrent handling of several interrupt processing operations in several respective processing elements.
FIG. 1 illustrates, in block diagram form, a control unit for rapid and adaptable processing of interrupt requests from different interrupt sources. Each interrupt source comprises at least one register 0, 1, 2 or 3 in which it stages its formatted interrupt requests for presentation to control ST via common interrupt register 4.
As shown in FIG. 3A, a formatted interrupt request comprises a field LV designating an interrupt level, a field SLVL designating an interrupt sub-level, an interrupt bit IB and a special bit SB. The level represented in LV corresponds to the priority level, or priority for short, which is assigned to the respective source by the system.
Requests having interrupt bit IB set to 1 require immediate servicing from the interrupt control ST. This is necessary because the interrupt requests are entered into control ST sequentially, via the common register 4, and distributed by ST sequentially to predetermined preprocessing elements PE0 to PE1, in accordance with their priorities. These elements pre-process the requests to convert request information into instruction addresses which designate locations of first instructions of routines for specific processing of respective request tasks in a not-shown single or multi-processor system.
As will be described in reference to FIG. 4, the operating system and circuits of control ST set interrupt level compare words into the processing elements PE which define the interrupt requests to be preprocessed by the respective elements, and also test whether the compare word is allowed, altered or unaltered by masking.
As shown in FIGS. 2, 2A, interrupt requests having various interrupt levels or priorities i are transferred from interrupt register 4 into associative memory (AM) 5 which is contained in control ST. At the same time, ST tests the availability of a processing element PEi associated with the respective priority. This test can be effected, for example, by determining for each processing element PEi having its D register 13 loaded with a value i representing this interrupt level, if associated buffers and storage stacks are not full.
If an element PEi is available for preprocessing interrupt requests of the respective priority i, specific parts of the i level requests, i.e. interrupt bit IB and interrupt sublevel field SLVL, are transferred in a byte-parallel mode from memory 5 to the buffer BU of that processing element. Such a PE is called a primary or standard PE. If no processing element is available the requests of priority i are transferred into the buffer BU of another processing element assigned to level i as a reserve processing element RPE.
As suggested previously, interrupt requests queued in the buffers BU of the processing elements PE are preprocessed, to form an initial routine address, by adding to a predetermined part of each request (i.e., the SLVL field) a base address, via an arithmetic and logic unit ALU in each processing element. Each routine address is transferred via a second buffer operated in accordance with the known FIFO algorithm into one or more instruction address registers IAR in the respective processing element for transmittal to a single or multi-processing system which performs the task routine. The logical combination of base address and interrupt sublevel functions can also be effected by means of other structures, e.g. through ORing.
When tasks for interrupt requests having higher priority than level i are not being processed the routines for interrupt level i can be performed. The initial addresses of these routines are in instruction address registers IARij. At such times, processing elements PEm which are processing interrupt requests of a lower interrupt level must be blocked. Interrupt routines of higher level cannot be interrupted.
Furthermore, if a reserve processing element RPEi assigned to the same interrupt level i has been activated the interrupt requests in the primary processing element PEi must first be processed before routines can be started for the interrupt requests in the reserve processing element.
After having processed all its interrupt routines, the primary processing element PEi is redesignated as the reserve processing element for level i, while the associated reserve processing element is designated as the primary processing element.
Relevant details of the foregoing preprocessing operations are shown in FIG. 4. Associated circuit details are shown in FIGS. 2 and 5 to 7. The following table lists the control signals which control the circuits of the device, the components to which they are applied, and the circuits by which they are generated. This table also shows the status of the controlled component, and the code name of each control signal. The legend below the table indicates the meanings of the abbreviated status notations.
TABLE OF CONTROL SIGNALS (FIG.__________________________________________________________________________2)SYSTEM COM- REFERENCE GENERATEDPONENT STATUS CODE BIT BY__________________________________________________________________________ INT-REG (4) E/NE ##STR1## 2 (FIG. 3A) SG (3) AM (5) F/NF ##STR2## 2 (FIG. 3A) SG (12) AM-COMP. (5) M/MM ##STR3## 0,1,2 (FIG. 3A) Hi (11) PE B/NB ##STR4## -- CU (9) P-REG (13) S/RS ##STR5## -- SG (14) COMP (19) M/MM ##STR6## 0,1 (FIG. 3A) COMP (19) BU (15) E/NE ##STR7## 2 (FIG. 3B) SG (20) FIFO E/NE ##STR8## 0 (FIG. 3C) SG (24) FIFO F/NF ##STR9## 0 (FIG. 3C) SG (23) IAR E/NE ##STR10## -- SG (23,29,30) RES-PE NC/NNC ##STR11## -- CU (9) OPE-REG S/RS ##STR12## -- SG (31) SV-MASK NEF/EF ##STR13## -- SV (6) B-REG S/RS ##STR14## -- SG (17) RPE-REG S/RS ##STR15## -- SG (32) PE PR/NPR ##STR16## -- CU (9)__________________________________________________________________________ LEGEND: B/NB--blocked/not blocked E/NE--empty/not empty EF/NEF--effective/not effective F/NF--full/not full M/MM--compared positive/negative NC/NNC--necessary/not necessary PR/NPR--processed/not processed S/RS--set/reset
As suggested in FIG. 2, the subject priority level-controlled device can service up to n+1 (in the present embodiment n=3) interrupt sources INT-SO to INT-Sn which are coupled sequentially to ST via separate respective registers 0 to n and common register 4. It is of course possible, in principle, to perform this coupling function in parallel. For controlling transfers of requests into interrupt register 4 gates G10, G11, and G1n, interposed between respective registers 0, 1, 2 and n, are scanned sequentially by gate control signals τ0 to τn. Within ST the interrupt requests are held in associative memory 5.
As previously noted each interrupt request consists of a 2-bit field LV designating the interrupt level assigned to the associated source, a 1-bit field IB containing an interrupt bit indication, a 4-bit field SLVL designating an interrupt sublevel, and a 1-bit SB field for special usage. The interrupt bit IB and special bit SB are used to perform specific control functions, e.g. to derive control signals representing the status of different system components. To give an example: the interrupt bit field in the top stage of associative memory (AM) 5 is used for generating control signal X2 or X2 indicating whether memory 5 is full (F) or not full (NF).
As shown in FIGS. 2 and 7, gate control signals τ0 to τn are generated by means of clock signals T and t0 to tn, and control signal X1 generated by signal generator (SG) 3. The time relation of clock signals T and t0 to tn is shown in FIG. 6. Control signals X1 and X1 are respectively generated by signal generator 3 when interrupt register 4 is respectively empty (E) and not empty (NE). The empty or not empty state of register 4 is represented by the presence or absence of an interrupt bit IB in register 4.
Interrupt requests are transferred from interrupt register 4 into associative memory 5 via gate G2 (FIG. 2). This gate is controlled by gate control signal τ4 generated by gate control signal generator (CPG1) 34 (FIGS. 2 and 7). This signal is raised at coincidence of clock signals T and t0 with control signal X2 (see FIG. 7).
As previously noted, control signal X2 or X2 indicates the full or not full status of associative memory 5, and is generated by a signal generator 3 responsive to an interrupt bit IB field in memory 5. Obviously, requests can be transferred from register 4 to memory 5 only when the latter is not full.
Control ST also comprises a mask circuit 6 (SV) associated with a mask register 7 (MA-REG), and a level register 8 (LV-REG).
Interrupt requests in memory 5 are pre-processed under control of a control unit (CU) 9 which itself is controlled by a control program contained in a control program storage (PS) 10. Control unit 9 initializes the system by loading interrupt/priority level information into the interrupt level registers (D-REG) 13 in the processing elements PEi, by setting to 0 the one-stage control registers RPE-REG and OPE-REG in each PE, by loading register 8 in control ST with e.g. the highest interrupt level and mask register (MA-REG) 7 with an intial mask.
The flexibility/adaptability of the present interrupt device derives from the co-operation of memory 5, controls 9, and masking circuit (SV) 6, the latter circuit controlling the assignments of levels to the processing elements PEi, if required, and the manipulation of interrupt levels through masks, if necessary.
Control unit 9 also supplies additional control signals, e.g gate control signals τL (FIG. 2) for activating gate G5 between interrupt level register 8 and both the masking circuit 6 and associative storage 5. In an unmasked operation interrupt requests stored in memory 5 are associatively searched for a match to the interrupt level LV currently stored in register 8. A hit indicator (HI) 11, connected to associative storage 5 responds to a match by generating control signal X3, and to a mismatch (or non-comparison) by generating control signal X3.
Interrupt requests coinciding with the level stored in register 8 are transferred through output gate G3 when signal X3 is generated by hit indicator 11. At such times gate enable pulse generator 34 (FIG. 7) generates gate control signal τ5 which enables gate G3. When gate G3 is operated, interrupt requests having the designated level (i) are transferred from memory 5 through main bus 38 (MB) into buffer (BU) 15 of the respective processing element PEi 38 whose interrupt level register 13 stores a value designating the associated level i. As shown in FIGS. 3A and 3B, bits 0 and 1 of the interrupt request which characterize the interrupt level field LV of the interrupt request, and which are transferred through interrupt register 4 and associative storage 5 are not transferred to buffer 15 (refer to FIG. 3B) since they are not required by the respective element PEi. Accordingly, buffer 15 receives only interrupt bit IB, interrupt sublevel field SLVL, and possibly special bit SB if it is required for specific control functions described later.
A transfer into buffer 15 of processing element PEi is permitted only when the element is not busy by a preceding operation, for in the latter case gate control signal τ6 for controlling gate G6 cannot be generated with gate enable pulse generator (CPG2) 37. As shown in FIG. 7 control signal τ6 is generated by coincidence of clock pulses T and t0, and control signals X5 (from signal generator 14, FIG. 2, when interrupt level register 13 is loaded), X6 (from comparator 19, FIG. 2, when the value stored in interrupt level register 13 equals the level value transferred with the request via main bus 38 into interrupt level register 18), X7 (from control signal generator 20, FIG. 2, when buffer 14 is empty), X11 (from control unit 9, FIG. 2, when the latter determines by means of control signals X10 or X10 whether or not reference to a reserve processing unit RES-PE is necessary (NC), and a control signal X13 (from masking circuit 6 when masking is not effective (NEF)).
Buffer 15 has as many rows (words) as associative storage 5. Consequently, in cooperation with the F1FO stack 22 to which it is serially coupled it permits the respective processing element to service requests on the assigned interrupt level in excess of the capacity of memory 4. All interrupt requests then may be transferred, in a parallel by byte mode via gate G6, into buffer 15 of selected processing elements PEi.
Now assume that processing element PEi, associated with the currently compared interrupt level i, can receive a new interrupt request. In a following step it tests the occupancy status of its base address register (B-REG) 16 by causing control signal generator 17 to produce control signal X14 if a base address is prepared in register 16, or control signal X14 if this register is empty. As pointed out above, signal generator 20 generates an output signal X7 when buffer 15 is empty, and a control signal X7 when buffer 15 is not empty. The coincidence of control signals X7 and X14 means that input registers A and B of arithmetic and logic unit (ALU) 21 contain, e.g. as values to be added, a base address from base address register 16 and an interrupt sublevel of an associated interrupt request from buffer 15. In that case, control signal pulse τ7, generated by gate enable pulse generator 37 (see FIG. 7), causes arithmetic and logic unit 21 to combine these two input values and latch the result in its output register O-REG.
The real address thereby formed is transferred from O-REG into FIFO stack 22, via gate G7, when the conditions for generation of gate control signal τ8 are satisfied; e.g. when control pulse generator 23 has generated output signal X9 which, with reference to the Table of Control Signals supra, indicates that the stack is not full (NF). As shown in FIG. 7, control signal τ7 is generated upon coincidence of a T clock pulse, a t0 clock pulse, a control signal X7 and a control signal X14. The information thereby entered into F1FO stack 22, which is the real address of the first instruction of an interrupt routine, has the format shown in FIG. 3C; i.e. the sum of a base address (derived from base address register 16) and the interrupt sublevel field SLVL of a respective interrupt request.
Before such real addresses of respective first instructions of interrupt routines can be transferred, via gates G80 to G8K(FIG. 2), into instruction address registers 25 to 27 (IAR 0 to IAR k), a test is made to determine if these instruction address registers do or do not contain previously loaded addresses. For that purpose, signal generators 28 to 30 are operated to generate control signals X10/0 to x10/k, or X10/0 to x10/k when these registers are empty and not empty, respectively. The respective control signals are used (FIG. 7) to form gate control signals τ9/0 to τ9/k which allow gates G80 to G8k to load respective instruction address registers IAR 0 to IAR k.
As shown in FIG. 7, the generation of the above-mentioned gate control signals requires a clock pulse T, clock pulses t0 to tk, control signals X8 and X10/0 to x10/k. The control signal X8 or x8 is produced by signal generator 24 (FIG. 2) in response to interrupt bits stored in stack 22 indicating whether the stack is empty or not empty.
The number k of parallel instruction address registers provided in a processing element should correspond to the number of the following processing units or processors provided e.g. in a multi-processor system.
However, before beginning the processing of an interrupt routine some additional operating conditions have to be examined. As shown in FIG. 2, real addresses are released for transfer from the instruction address registers to the control systems of connected processors by means of gate control signals τ10/0 to τ10/k produced by generator 37. FIG. 7 shows that these gate control signals are conditioned on clock signals T and t0 to tn, and control signals X4 and X12. Control signal X4 and X4, generated by control unit 9, indicate the accessibility status of the respective processing element, i.e. whether or not it is blocked (blocked for example because interrupt requests of a higher interrupt level are being processed at the moment).
The above specified operation could be called a standard or non-exceptional operation. By comparison a non-standard or exceptional operation is illustrated in the middle one of the three diagrams of FIG. 8. However, before explaining this operation reference is first made to the standard operation as shown in the upper diagram of FIG. 8
FIG. 8 is to be viewed in connection with FIGS. 2 and 7. In cooperation with gate control signals τ0 to τ3, control signal X1 invokes operating step I for transferring requests from the various interrupt sources into interrupt register 4. Then step II is invoked by control signal X2 and τ4 for transferring the request into memory 5.
Then step III is performed to transfer selected contents of the memory 5 into buffer 15 of a selected processing element PEi under control of control signals X3, X5, X7, X11 and X13 in conjunction with timing signals τ5 and τ6.
Then step IV transfers the contents of buffer 15 together with a base address through the arithmetic and logic unit of the processing element, to produce the effective address, which is stored in stack 22 of that element. This operating step is controlled by signals X7, X9, X14, and gate control signals τ7 and τ8.
When stack 22 contains an effective instruction address, step V transfers such an address into an instruction address register IAR. The necessary criteria are the presence of control signals X8 and X10 which lead to the generation of gate control signal τ9.
In the last operating step VI of standard operation an instruction in the interruption handling program is located via passage of the initial instruction address of an interrupt routine to the associated processor, and executed while transfers from processing elements with lower interrupt levels are blocked.
In the operation according to the middle diagram of FIG. 8 steps I and II are preceded by a previously undiscussed operating step VII associated with a blocking of transfers of interrupt requests into interrupt register 4 because control signal X1 signifies that this register is not yet empty. When register 4 becomes accessible, steps I and II are performed as explained previously.
Subsequently, another "non-standard" operating situation, characterized as operating step VIII, allows for loading of a reserve processing element because the associated primary processing element is fully loaded. Even if a reserve processing element is not available the respective primary processing element should be blocked in this operating step VIII. This operating situation is characterized first by control signal X7 which is generated when the buffer of the processing element is not yet quite empty. Furthermore, control signal X11 is generated which characterizes an operating status requiring a reserve processing element.
There follow the above described operating steps III to V which however in the present case refer to the reserve processing element rather than to the primary processing element.
As shown in the middle diagram of FIG. 8 the step VI which normally would immediately follow step V, i.e. the execution of instructions and the blocking of lower priority processing elements, may be delayed by one or more "idling" steps IX each having a T clock time duration. This delay is required when the interrupt requests still queued in the primary processing element have not yet been fully processed. The idling step IX is dependent on control signals X4 and X12. Its duration is determined by control signal X12 which is produced by signal generator 31 (FIG. 2) when the OPE register is set. Control unit 9 sets this register via a control signal X16 and the register is reset (control signal X12) only when all interrupt requests of the primary processing element have been processed, that causing control unit 9 to produce control signal X16.
If the OPE register is still set (control signal X12) at the next T clock time the reserve processing element has to wait again for the processing of its first interrupt request. As shown in FIG. 8, this is only possible at T clock time 9, when control signal X12 is produced. At this time operating step VI can be executed.
The lower diagram in FIG. 8 shows how in the initial phase, due to unavailability of the interrupt register, operating steps VII are repeated until control signal X1 indicates that the interrupt register is ready to receive a new interrupt request from the interrupt sources.
Arrows in FIG. 8 indicate how parallel pre-processing is achieved in the total of all processing elements.
Below, reference will be made to some specific features of control ST in FIG. 2 which are processed by the operating system of control unit 9. Furthermore, the function of control unit 9 in connection with its program storage 10 and masking circuit 6 can also be controlled by the operating system of one of the connected processors and therefore does not absolutely have to be provided as a separate unit. Reference is also made to the fact that control signals directed by the individual processing elements PE0 to PE1 towards control unit 9, as e.g. control signals X10/0 to X10/k, X9 and X9 would have to be individually marked with respective identification indicia to identify the processing elements from which they originate. The same applies for control signals which are derived from specific operating situations and from the above-mentioned control signals, and which are directed from control unit 9 to individual processing elements, since these would equally have to be marked with the identifying indicia of those processing elements to which they are individually directed. However, to simplify the specification, these details in the marking of the control signals have been omitted in FIGS. 1, 2, 7 and 8, the more so as FIGS. 2 and 7 show in detail only the conditions for processing element PE0.
At the beginning of initialization, there exist in the interrupt control only so-called neutral processing elements (neutral PE), i.e. such elements which have not yet been allocated to an interrupt level LV. Neutral processing elements are recognized as such by their RPE registers, OPE registers and D registers all being set to 0.
As pointed out at the beginning of the specification, the initialization phase comprises the setting of the D registers with the information of interrupt levels LV which are to be allocated to respective processing elements.
Such processing elements whose D-registers are now loaded with interrupt levels, and in which the RPE-register and the OPE-register are still set to 0, are called standard processing elements (standard PE).
If, due to an overflow of other kind of blocking condition, a reserve processing element must be added to an overflowing standard processing element the interrupt level which had been allocated to the overflowing element is read into the D-register of a neutral processing element which is then characterized as a reserve processing element by a "1" set into its RPE-register. The RPE-register in the standard element remains reset to 0.
However, the overflowing, standard processing element connected to a reserve processing element must then be characterized as an old processing element to make sure that interrupt requests of this interrupt level queued in the reserve element are not processed until those in the old element have been fully processed.
A characterization for such an old processing element (old PE) is an OPE-register set to 1, an RPE-register reset to 0, and a D-register loaded with the corresponding interrupt level.
The operating system carries out this control function e.g. by preparing lists of free processing elements and such processing elements which cause an overflow.
The blocking of processing elements with lower interrupt levels, performed in operating step VI (FIG. 8), can be effected by means of known priority control circuits operating to generate signal X4 or X4.
Finally, FIG. 5 shows a basic circuit diagram of masking circuit 6 which is represented in FIG. 2 and which with its control signals X13 or X13/0 to X13/1 is in the position of preventing the associative search operation with respect to an interrupt level characterized by a mask. With reference to signals X13/0 to X13/1 it is pointed out that these are generated individually by control ST for the various processing elements PE0 to PE1. Masking circuit 6 substantially consists of a decoder DEC for transforming the interrupt level code LV into another code represented in the lower part of FIG. 5. Furthermore, it includes four AND gates whose outputs are ORed together to produce control signal X13.
Each AND gate has two inputs, one connected to an output line of the decoder and the other to an output of mask register 7. In the embodiment of FIG. 5 therefore priority level 00 is blocked by a mask with form 1000 since the AND condition for the AND gate in the upper left is satisfied. In this manner, control signal X13 is generated which indicates that interrupt level masking is effective.
Control signal X13 is generated by means of an inverter I connected at the output of the above-mentioned OR gate.
While we have illustrated and described preferred embodiments of our invention, it is to be understood that we do not limit ourselves to the precise construction herein disclosed and the right is reserved to all changes and modifications coming within the scope of the invention as defined in the appended claims.
|J. D. Erwin et al., Interrupt Processing with Queued Content-Addressable Memories, Fall Joint Computer Conference, (Nov. 1970), pp. 621-627.
|Citing Patent
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|U.S. Classification
|710/264, 365/195, 365/49.15, 365/49.18, 365/49.17, 365/230.08
|International Classification
|Cooperative Classification
|European Classification
|Sep 16, 1981
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMON
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HEINRICH, HANS J.;SCHUTT, DIETER;REEL/FRAME:003909/0315
Effective date: 19810605
|May 18, 1987
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|Aug 11, 1995
|Fee payment
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