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|01st week of 2009 patent applcation highlights part 31
|Patent application number
|AUTOMATIC WARNING LIGHT CONTROL DEVICE FOR AUTOMOBILES - An automatic warning light control device is applicable to an automobile and includes a controller electrically coupled to directional signal lights of the automobile. The controller is electrically coupled to a warning light system, a windshield wiper system, at least one door of the automobile, and a trunk lid. When the windshield is activated in a rain condition, or when the door or the trunk lid is not properly closed, the controller automatically activates the warning light system, wherein both directional signal lights blink simultaneously. When the directional signal lights are used for indication of direction, the directional signal lights are automatically switched from the warning mode to a direction indication mode where only the designated directional signal light blinks. Once the direction indication operation is completed, the directional signal lights automatically go back to the warning mode to blink simultaneously.
|Vehicular Lamp - A vehicular lamp includes a semiconductor light source and a switching means arranged to switch between a first lighting mode, in which the semiconductor light source stays on, and a second lighting mode, in which the semiconductor light source repeatedly turns on and off. The lamp is arranged so that a peak current flowing through the semiconductor light source in the second lighting mode is smaller than that in the first lighting mode. The arrangement can help suppress overshooting and undershooting in the light source current.
|Seat Condition Detection Device and Illumination Direction Adjustment Device for Vehicle Head Lamp - A seat state detecting apparatus is provided with a sensor unit including a plurality of pressure sensitive switch units connected in parallel to each other. Each of the pressure sensitive switch units is switched to an on state or an off state in correspondence to a pressure. A plurality of pressure sensitive switch units are arranged in the seat in a dispersed manner. The seat state detecting apparatus determines a load applied to the seat on the basis of the on/off state of a plurality of pressure sensitive switch units. The sensor unit is provided with a short-circuit detecting resistor which is connected in series to a plurality of pressure sensitive switch units. Accordingly, it is possible to reliably detect a short circuit of a power source line for feeding electricity to the sensor unit.
|LED lamp module - An LED lamp (
|VEHICLE LAMP - A vehicle lamp includes a convex lens and a light emitting device. Light directly reaching a rear surface of the convex lens from the light emitting device is deflected through the convex lens to form a light distribution pattern having a horizontal cutoff line and an oblique cutoff line. The light emitting device includes a light emitting chip having a rectangular light emitting surface oriented to face the rear surface of the convex lens, and a corner of the rectangular light emitting surface is disposed on a rear focal point of the convex lens. A front surface of the convex lens includes a horizontally diffusing region which diffuses a part of the light in the horizontal direction, and an obliquely diffusing region which diffuses another part of the light toward the self lane side in an oblique direction forming an upward angle with respect to the horizontal plane.
|Fairy lights - Fairy lights have at least one light assembly connected to a wire cable. Each light assembly has at least one shell, a film attached to the at least one shell and at least one lighting device. The film has a mounting ring and multiple branches radially extend outward from the mounting ring, and may be coated with a reflective layer and have optical fibers arbitrarily mounted on the branches. When changing the branches to different shapes, the film is formed to have a particular pattern. With the films, the light string generates festinating decorative effects when the light assembly is activated.
|Lighting tree - A lighting tree has a base, a stand mounted on the base, multiple lighting branches connected to the stand, multiple lighting leaves expanding from each lighting branch, and a control box incorporated with a speaker. Each lighting branch has a lighting element mounted in one end of the lighting branch. The control box determines whether the lighting elements should be activated. Based on different types of music output by the speaker, the control box determines the lighting branches and lighting leaves to be turned on or off.
|OVERSPEED PREVENTION STRUCTURE USING PLASTIC OPTICAL FIBER - An overspeed prevention structure is disclosed herein. The overspeed prevention structure according to the present invention comprises a structural body having a curved convex upper surface; an external light source; and a plastic optical fiber embedded in the structural body and connected electrically to the external light source so as to emit the light outside the structural body.
|Light Guides, Illuminated Articles and Devices - A side-emissive flexible polymeric light guide
|Light Guide Device and Back Lighting Module Comprising the Same - A light guide device is used in a back light module that more uniformly mixes different colored light emitted from a plurality of LEDs and transfers the mixed light to a display panel, wherein a light loss can be minimized during the light mixing process and the light can be more uniformly mixed. A light guide device is disclosed for mixing different colored light emitted from a plurality of light emitting diodes (LEDs) and guiding the mixed light to a display panel, wherein the light guide device comprises a light guide portion in the form of a plate arranged at a rear of the display panel; and a light mixing portion formed integrally with the light guide portion and including a light incidence surface adjacent to the plurality of LEDs and a light mixing area for mixing the light with difference colors incident through the light incidence surface.
|Light Guide, Lighting Device and Image Reading Device - To provide a rod-like light guide and a line lighting device including the rod-like light guide, both of which are easy to include in an image reading device, a contact-type image sensor and an image reading device. For instance, a protruding portion having a flat or curved surface is formed by grinding an end face of a rod-like light guide in a longitudinal direction while leaving at least 80% of the surface area of the end face, and a reflective surface is formed by bonding a heat transfer film to the protruding portion. Thus, even if a portion of the protrusion portion melts when performing thermal processing on the heat transfer film, the portion will not jut out beyond a cross-sectional area of the rod-like light guide, and the rod-like light guide can be easily contained in a case.
|LIGHT CONTROL PLATE, SURFACE LIGHT SOURCE DEVICE AND TRANSMISSIVE IMAGE DISPLAY DEVICE - A light control plate
|DC TO DC CONVERSION CONTROL SYSTEM AND METHOD - A direct current to direct current (DC/DC) converter control systems and related methods are disclosed. An exemplary embodiment provides a control circuit configured to modulate the duty cycles of a first switching device and a second switching device, and is further configured to compensate for a voltage drift at a monitoring node by varying the modulation for at least one of the switching devices.
|SYNCHRONOUS RECTIFICATION CIRCUIT FOR POWER CONVERTERS - A synchronous rectification circuit for power converters operable under fixed and/or variable frequencies where no current sense circuit or phase-lock circuit are needed is provided. It has a power switch coupled to a transformer for the rectification. A signal-generation circuit is used for generating a control signal in response to a magnetized voltage of the transformer, a demagnetized voltage of the transformer, and a magnetization period of the transformer. The control signal is coupled to turn on the power switch. The enable period of the control signal is correlated to a demagnetization period of the transformer.
|Cross current control for power converter system - A system and method for controlling cross current in an interleaved power converter system having a plurality of converter threads coupled in parallel includes collecting a feedback current from each thread and obtaining a normal current and a differential mode current for each thread, based on its respective feedback current. The normal current of each thread is regulated to a commanded thread normal current value via a respective normal current control loop based on d-q rotating frame parameters. A differential mode cross current of each thread is regulated to zero via a respective differential mode cross current control loop based on d-q rotating frame parameters; while a differential mode cross current DC offset of each thread is regulated to zero via a respective differential mode cross current control loop based on stationary frame parameters.
|CHOPPER TYPE DC-DC CONVERTER - A chopper type DC-DC converter includes a voltage converting circuit, a comparative wave generating circuit, a comparator group, and a switch control circuit. The voltage converting circuit converts a first voltage into a second voltage. The comparative wave generating circuit generates first and second comparative waves such that the voltage range of the first comparative wave is different from the voltage range of the second comparative wave. The comparator group generates a first comparison result signal indicating a result of comparison between the first comparative wave and an error signal indicating an error between the second voltage and target voltage and a second comparison result signal indicating a result of comparison between the second comparative wave and the error signal. The switch control circuit controls the voltage converting circuit based on the first and second comparison signals. The comparative wave generating circuit includes first and second comparative wave generating circuits. The first and second comparative wave generating circuits respectively generate the first and second comparative waves based on different source voltage groups.
|Non-Contact Power Supply System - A non-contact power supply system is provided in which current phases of induction lines are matched. According to the output current of a power supply unit (
|METHOD AND SYSTEM OF CONTROLLING A POWER INVERTER - Methods and systems for controlling a power inverter are provided. In accordance with one embodiment, a system for converting a direct current into an alternating current may include a switching module, a sensing module, and a control module. The switching module may have an input and an output, and may be operable to receive a direct current at the input and to generate at the output a corresponding alternating current with a desired output characteristic. The sensing module may be coupled to the switching module output, and may be operable to sense a power factor associated with a load coupled to the switching module output. The control module may be coupled to the power inverter and the sensing module, and may be operable to control the desired output characteristic based at least on the sensed power factor.
|Inverter - The invention relates to an inverter for converting a DC voltage into an AC voltage having one or more phases, comprising
|DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY - Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4 f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
|SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.
|PRODUCTION METHOD FOR SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A pair of power supply lines that are orthogonal to the border with the cell array are placed, for each one-bit processing circuit of the data processing unit, in a semiconductor storage device such as SRAM or the like comprising a data processing unit for writing data to memory cells and reading it therefrom, a row decode unit for driving the word lines of the memory cells, and a timing control unit for generating a control pulse for the data processing unit, all of which are arranged around the circumference of a cell array in which memory cells are arrayed in a grid-like fashion. MOS transistors are placed between the power supply lines in such a position that the principal axis direction of the gate pattern is orthogonal to the two aforementioned wirings, and are closely arrayed in the longitudinal direction of the power supply lines.
|Carbon nanotube fuse element - In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
|SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device having a volatile memory therein, high-speed operation is enabled and the density of the memory can be enhanced. The volatile memory includes a word line, a complementary bit line having bit lines, a plurality of common source lines, and a memory cell that is coupled with the word line and the complementary bit lines. The memory cell includes transistors. The gate electrodes of the transistors are coupled with the word line, and the drain electrode of one of the transistors is coupled with one of the bit lines. The drain electrode of the other transistor is coupled with the other bit line. The respective source electrodes of the transistors are coupled with any one of the common source lines, or brought in a floating state, thereby storing storage information in the memory cell.
|METHODS FOR FERROELECTRIC DOMAIN READING - Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material between 1 nanometer (nm) and 50 nm in thickness. The embodiments may also include applying another voltage through the tip, thereby generating a current responsive to an orientation of the polarized domain. The embodiments may also include measuring the current and determining the orientation of the polarized domain, based upon the measuring.
|Computation Processing Circuit Using Ferroelectric Capacitor - A computation processing device executes logic computation based upon input data X(t) and data X(t−1) stored in memory. A ferroelectric capacitor includes a first terminal and a second terminal, and provides a function as memory. A bit line driver switches the voltage to be applied to the first terminal or the second terminal of the ferroelectric capacitor. A sense amplifier outputs a computation result according to the voltage that occurs at either of the first terminal and the second terminal of the ferroelectric capacitor. For example, the bit line driver switches the direction of the voltage to be applied to the ferroelectric capacitor according to the input data X(t).
|INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL HAVING A PLANARIZED SURFACE - An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.
|QUASI-DIFFERENTIAL READ OPERATION - A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate, and to charge a second line at a second rate, the first and second charge rates based on a state of a memory cell coupled between the respective lines. The read circuit may further include a ground circuit configured to pull the respective lines to a ground potential, and a sense circuit coupled to the line pair configured to sense a differential voltage between the line pair in response to the state of the memory cell.
|MULTIPLE WRITE CONFIGURATIONS FOR A MEMORY CELL - One embodiment of the present invention relates to a method of programming an array of memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, each of which can write at least two data states to the memory cells of the array. Other embodiments are also disclosed.
|CONDITIONING OPERATIONS FOR MEMORY CELLS - One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.
|Method of making 3D R/W cell with reduced reverse leakage - A method of making a nonvolatile memory device includes forming a semiconductor diode steering element, and forming a semiconductor read/write switching element.
|INTEGRATED CIRCUIT WITH MEMORY HAVING A CURRENT LIMITING SWITCH - An integrated circuit with memory having a current limiting switch. One embodiment provides a memory cell having a programmable resistivity layer and a writing line. A switch is arranged between the resistivity layer and the writing line. The switch includes a control input connected to a select line. The switch is configured to limit a current through the resistivity layer for a write operation.
|Capacitor supported precharching of memory digit lines - Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.
|Electromechanical Memory, Electric Circuit Using the Same, and Method of Driving Electromechanical Memory - A memory element which has high affinity with a conventional semiconductor process, which has a switching function of completely interrupting electric conduction paths by in a mechanical manner, and in which nonvolatile information recording is enabled is realized. An electromechanical memory which is formed on a substrate, which is formed by interposing a memory cell by electrodes, and which has a movable electrode that is a beam stretched in the air via a post portion is realized. According to the configuration, a nonvolatile memory can be realized by a simple structure, and it is possible to realize a high-performance electromechanical memory which is conventionally difficult to be realized, and in which the power consumption is low and the cost is low, and an electric apparatus using it.
|Method and System For Encoding to Eliminate Parasitics in Crossbar Array Memories - A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of '1' bits and '0' bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.
|Semiconductor memory device and read method thereof - A semiconductor memory device comprises a plurality of memory cells each capable of storing at least three different states; a first sense amplifier for amplifying a ternary potential read out in accordance with a state stored in a selected memory cell based on a comparison with a first reference potential; and a second sense amplifier for amplifying a ternary potential read out in accordance with a state stored in the selected memory cell based on a comparison with a second reference potential. In the semiconductor memory device, the ternary potential comprises a high potential, a medium potential and a low potential, the first reference potential is set between the low potential and the medium potential, and the second reference potential is set between the high potential and the medium potential.
|MAGNETIC MEMORY DEVICE USING DOMAIN STRUCTURE AND MULTI-STATE OF FERROMAGNETIC MATERIAL - Disclosed is a memory device using a multi-domain state of a semiconductor material, and more particularly to a magnetic memory device, in which a ferromagnetic layer for recording magnetic data serves as a sensing layer so as to have a simple structure, shorten a manufacturing process, and reduce the unit cost of production. The planar hall effect or magneto-resistance is used to measure multi-domain states so as to read data stored in a multi-level state.
|Method for switching magnetic moment in magnetoresistive random access memory with low current - A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current.
|PROGRAM METHOD WITH LOCALLY OPTIMIZED WRITE PARAMETERS - A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.
|CMOS-PROCESS-COMPATIBLE PROGRAMMABLE VIA DEVICE - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer.
|MEMORY WITH DYNAMIC REDUNDANCY CONFIGURATION - One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.
|RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array blocks arranged in a bit line direction, and first and second bit lines are selected from the first and second cell array blocks, respectively, to constitute a pair and coupled to differential input nodes in the sense amplifier array.
|NONVOLATILE MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT AND ASSOCIATED OPERATING METHOD - A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.
|PHASE CHANGE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
|FLOATING BODY MEMORY ARRAY - Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
|Semiconductor Memory Device and Semiconductor Device - The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor
|SYSTEM THAT COMPENSATES FOR COUPLING BASED ON SENSING A NEIGHBOR USING COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
|SYSTEM THAT COMPENSATES FOR COUPLING BASED ON SENSING A NEIGHBOR USING COUPLING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).
|DOUBLE PROGRAMMING METHODS OF A MULTI-LEVEL-CELL NONVOLATILE MEMORY - A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line.
|METHOD FOR PROGRAMMING MULTI-LEVEL CELL FLASH MEMORY DEVICE - A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory cells have a positive threshold voltage. An LSB of a particular memory cell is programmed to a predetermined level, and data of the programmed LSB is sensed. An MSB of the particular memory cell is programmed to a predetermined level according to the sensed data of the LSB.
|NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.
|NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-LEVEL CELLS USING MODIFIED READ VOLTAGES AND METHODS OF OPERATING THE SAME - Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.
|FLASH MEMORY DEVICE AND METHOD FOR ADJUSTING READ VOLTAGE OF FLASH MEMORY DEVICE - A flash memory device includes a cell array and a read voltage adjuster. The cell array includes a first field having first memory cells and a second field having second memory cells. The read voltage adjuster determines a read voltage for reading first data from the first memory cells of the first field with reference to second data read from the memory cells of the second field.
|SEGMENTED BIT LINE FOR FLASH MEMORY - A memory device including segmented bit lines with memory cells coupled to a data cache is provided. A segmented bit line includes a bias transistor to selectively connect the bit line to a source line. Further, a physical implementation showing a segmentation pattern of the memory device is also provided.
|High density NOR flash array architecture - In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions.
|Select gate transistors and methods of operating the same - Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.
|Non-volatile semiconductor device - A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.
|METHOD AND DEVICE FOR DEMULTIPLEXING A CROSSBAR NON-VOLATILE MEMORY - A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.
|FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE - A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.
|Flash cell with improved program disturb - Memory cells, memory arrays, memory devices and methods are disclosed, such as those involving a memory cell comprising a floating gate comprising lightly doped polysilicon, wherein the lightly doped polysilicon has a substantially uniform doping concentration. One such memory cell further comprises a control gate and dielectric disposed between the floating gate and the control gate.
|Non-volatile memory system and programming method of the same - A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operations. The programming the multi-page program data includes programming memory cells of the memory block using a first threshold voltage lower than a desired threshold voltage based on the multi-page program data sequentially buffered by the page buffer in units of pages and programming the memory cells using the desired threshold voltage by increasing a threshold voltage of the memory cells by a predetermined level at each successive program operation.
|Non-volatile memory device for reducing layout area of global wordline decoder and operation method thereof - A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.
|METHOD FOR SOURCE BIAS ALL BIT LINE SENSING IN NON-VOLATILE STORAGE - Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.
|NON-VOLATILE STORAGE WITH SOURCE BIAS ALL BIT LINE SENSING - A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.
|SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell string provided on a semiconductor substrate, and a first select transistor including a gate insulation film, which is provided on the semiconductor substrate having a recess structure which is lower, only at a central portion thereof, than the semiconductor substrate on which the memory cell string is provided, and a gate electrode provided on the gate insulation film, the first select transistor selecting the memory cell string.
|SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD - A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
|NON-VOLATILE MEMORY DEVICE - A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon generated by the nose of the source line can be reduced. That is, at the time of a verifying operation performed during a program operation, the current concentrated on a common source line can be distributed and, therefore, the occurrence of under-programmed cells can be prevented.
|Rd Algorithm Improvement for Nrom Technology - Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.
|Scalable Electrically Eraseable And Programmable Memory (EEPROM) Cell Array - A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V
|FLASH MEMORY DEVICES AND PROGRAMMING METHODS THAT VARY PROGRAMMING CONDITIONS IN RESPONSE TO A SELECTED STEP INCREMENT - A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.
|MEMORY DEVICE AND READING METHOD - A memory device according to an embodiment of the present invention, comprises a common source line current detection unit for detecting current in a common source line of a memory cell array and outputting a control signal; and a control unit for controlling an evaluation time for reading data of a page buffer coupled to the memory cell array according to the control signal output from the common source line current detection unit.
|NON-VOLATILE MEMORY DEVICE - A non-volatile memory device for adjusting level of a verifying voltage supplied to a word line in accordance with occurrence of a source line bouncing phenomenon is disclosed. The non-volatile memory device includes a bouncing sensing circuit configured to compare a source line current passing through a common source line with a reference current, and output a bouncing sensing signal in accordance with the comparing result, and a word line voltage controller configured to provide a verifying voltage increased by a certain level to a word line in accordance with level of the bouncing sensing signal.
|Program-verify method - Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.
|METHOD AND CIRCUIT FOR PERFORMING READ OPERATION IN A NAND FLASH MEMORY - Disclosed is a method and semiconductor circuit for providing a read operation in a NAND flash memory. The NAND flash memory includes an array of bit lines. The method includes selecting a first set of bit lines of the array of bit lines for performing the read operation. The first set of bit lines are pre-charged to a pre-defined voltage level. At the same time, a second set of bit line are also charged to the pre-defined voltage. The second set of bit lines are in anti-phase to the first set of bit lines. Further, reading of the first set of bit-lines is performed. The second set of bit lines is maintained at the pre-defined voltage level during the reading of the first set of bit lines.
|METHOD OF DEPRESSING READ DISTURBANCE IN FLASH MEMORY DEVICE - A method of reading a NAND flash memory device includes a cell string having a drain selection transistor, a plurality of memory cells and a source selection transistor which are in series connected to each other. The method comprises the steps of applying a first voltage to a gate of the drain selection transistor in order to turn on the drain selection transistor, applying a read voltage to a gate of a selected memory cell among the plurality of memory cells, and applying first and second pass voltages to gates of unselected memory cells of the plurality of memory cells, wherein the first pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are adjacent to the selected memory cell and wherein the second pass voltage of a relatively high level is applied to the gates of the unselected memory cells which are not adjacent to the selected memory.
|Non-volatile memory and method of manufacturing same - The number of process steps for manufacturing a non-volatile memory is reduced while the performance of the non-volatile memory is improved. The non-volatile memory has a memory cell in which first, second and third P-type diffusion regions are formed in an N-type well, a select gate is formed via a select-gate insulating film over a channel between the first and second P-type diffusion regions, and a floating gate is formed via a floating-gate insulating film over a channel between the second and third P-type diffusion regions. The non-volatile memory has a peripheral circuit in which fourth and fifth P-type diffusion regions are formed in an N-type well, and a peripheral-circuit gate is formed via a peripheral-circuit gate insulating film over a channel between the fourth and fifth P-type diffusion regions. The film thickness of the floating-gate insulating film is greater than that of the select-gate insulating film and peripheral-circuit gate insulating film.
|Method of making memory cell with voltage modulated sidewall poly resistor - A method of making a two terminal nonvolatile memory cell includes forming a first electrode, forming a charge storage medium, forming a resistive element, and forming a second electrode. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes, and a presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.
|Memory cell with voltage modulated sidewall poly resistor - A two terminal nonvolatile memory cell includes a first electrode, a second electrode, a charge storage medium, and a resistive element. The charge storage medium and the resistive element are connected in parallel between the first and the second electrodes. A presence or absence of charge being stored in the charge storage medium affects a resistivity of the resistive element.
|Driving Method of Flash Memory Device - In a driving method of a flash memory device including a selected first bit line and an unselected second bit line, a program voltage of a pulse is applied to word lines of all memory cells in a block passing an erase verify operation. After the first and second bit lines are precharged to a predetermined level, a ground voltage is applied to the word lines of all the memory cells in the block. The memory cells are evaluated for a predetermined time shorter than an evaluation time of a read operation. Whether or not a memory cell passing a verify operation exists among the memory cells is sensed. Resultantly, when the memory cell passing the verify operation exists, the memory cells in the block are programmed to a desired level using a predetermined program voltage and a step voltage.
|NONVOLATILE MEMORY SYSTEM, SEMICONDUCTOR MEMORY, AND WRITING METHOD - A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
|Semiconductor memory device including output driver - A semiconductor memory device has a data output device. The data output device is provided with a slew rate control unit for detecting a transition number of a plurality of output data to output slew rate control information; and an output driving unit for driving the plurality of output data with a pull-up drivability and a pull-down drivability adjusted based on the slew rate control information.
|Memory device bit line sensing system and method that compensates for bit line resistance variations - Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.
|SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of measuring internal voltages via a shared pad to reduce a chip size. The semiconductor memory device includes a selector and a monitoring pad. The selector is configured to select one of a plurality of internal signals in response to a test signal and output the selected internal signal. The monitoring pad is configured to output an output signal of the selector to an outside of the semiconductor memory device.
|Semiconductor memory device having input device - A semiconductor memory device includes a pad for receiving an external signal through a first external pin, a reference voltage pad for receiving an external reference voltage through a second external pin, an internal reference voltage generator configured to generate an internal reference voltage using an external voltage in response to a reference voltage select signal, a reference voltage supply unit for generating the reference voltage select signal in response to a plurality of select signals, and selecting one reference voltage between the external reference voltage and the internal reference voltage to output the selected one as a reference voltage, a buffer for converting an output signal of the pad into an internal voltage level on the basis of the reference voltage, and a signal selector for controlling an internal signal to be inputted/outputted through the reference voltage pad in response to the plurality of select signals.
|Impedance adjusting circuit and semiconductor memory device having the same - An impedance adjusting circuit includes: a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance; a transmission line circuit configured to transfer the first calibration code during a first section and to transfer the second calibration code during a second section; and a termination resistor circuit adapted to match an impedance with a resistance determined by receiving the first and second calibration codes.
|Semiconductor Device - There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.
|DEVICE SELECTION CIRCUIT AND METHOD - Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals).
|FUSE READING CIRCUIT - Correction data is written in fuse circuits of q bits. A reading circuit sequentially reads information of the fuse circuits through a selector and writes the information in a storage circuit. Therefore, read data is output from the storage circuit in parallel.
|SEMICONDUCTOR MEMORY DEVICE HAVING REFRESH MODE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device can control the toggling of signals corresponding to internal addresses during an auto-refresh mode. The semiconductor memory device includes an internal address generator configured to generate a plurality of first word line driving information signals and a plurality of first to seventh address information signals, which are sequentially activated in response to a driving signal and a refresh signal, a toggle controller configured to generate first and second toggle control signals in response to the third to sixth address information signals during an auto-refresh mode or a self-refresh mode, and a driving controller configured to generate a plurality of bit line driving signals and a plurality of second word line driving information signals corresponding to the first to third and seventh address information signals in response to the first and second toggle control signals.
|Column access control apparatus having fast column access speed at read operation - A column access control apparatus comprises a column signal control unit for controlling a write CAS pulse signal and an internal CAS pulse signal in response to a first signal, and a column decoder for outputting a column decoding signal using an output signal of the column signal control unit and the first signal. The column signal control unit delays the internal CAS pulse signal and the write CAS pulse signal to output delayed signals when the first signal is activated.
|Semiconductor memory device - A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.
|OUTPUT CONTROL SIGNAL GENERATING CIRCUIT - An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.
|Method for Hiding Defective Memory Cells and Semiconductor Memories - A method for hiding defective memory cells in a semiconductor memory having a plurality of memory cells coupled with word lines for controlling is suggested. In the method, at least one word line is determined, where one control signal selects the at least one defective memory cell. For hiding the at least one defective memory cell, a signal inverted with regard to the selection signal is applied to the at least one determined word line during addressing of the plurality of memory cells.
|MEMORY TEST MODE FOR CHARGE RETENTION TESTING - One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer circuit external to the memory circuit die. Other embodiments are described and claimed.
|SEMICONDUCTOR MEMORY DEVICE AND METHOD OF INPUTTING ADDRESSES THEREIN - A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses to an internal circuit and store one or more of the received normal addresses. The second address buffer unit is configured to transmit one or more external bank addresses to the internal circuit as internal bank addresses in a normal mode and transmit addresses stored in the first address buffer unit to the internal circuit as the internal bank addresses in a test mode.
|APPARATUS AND METHOD OF SETTING TEST MODE IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
|METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE - A method for testing a semiconductor memory device is provided. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Each word line is controlled by a corresponding control line and a corresponding driving line. The method includes selecting a plurality of word lines controlled by one driving line; enabling a plurality of control lines respectively corresponding to the selected word lines; actuating one of the selected word lines; and adding a disturbing signal on the actuated word line and measuring signals on the plurality of bit lines.
|SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER - A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.
|Test circuit and method for use in semiconductor memory device - A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled.
|SEMICONDUCTOR DEVICE - A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.


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District Institute of Education and Training is situated at College Road, At, Post, Taluka :- Santrampur-389 260 District :- Panchmahal in Panchmahal.
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District Institute of Education and Training - DIET
In the National Education Policy-1986, teacher training has been is considered as a land mark for qualitative education. In the past improvement in the quality of primary teaching was a challenge. As a solution to this problem training institutions were established at national level With reference to the above the PTC college of Santrampur, District – Panchmahal was formerly recognized as "Buniyadi Purush Adhyapan Mandir." It was upgraded and transformed as Insirvials DIET on 6/4/1990. This Institute has hostel facility, administrative building, computer room, T.L.M. room, prayer room, staff quarters and all other modern amenities. At district level this Institute provides teachers training, research programmes, and has been working for innovative at the level of primary education, (retention and improvement and quality). This institution is continuously trying to set up novel experiments and programmes and it is actively working for improved quality of teaching in a remarkable way. The modern teaching methodology assists the students in getting an all around view of engineering, technology and the entrepreneur world. The diligent faculty team of the college possesses hands-on experience and up to date knowledge of their subject and area of expertise. The infrastructure and facilities of District Institute of Education and Training consists of spread-out campus alongside various amenities in the form of library, computer center, classrooms with proper teaching and learning aids, medical facilities etc. The institute seeks to place each of its students in an organization/company of great repute.
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Scientific evidence shows that marine reserves usually boost the abundance, diversity, and size of marine species living within their borders. To bring this evidence to audiences around the world in innovative ways, the Science of Marine Reserves team has developed a range of tools.
The first step towards producing the Science of Marine Reserves tools is to synthesize the most up-to-date scientific information available in peer-reviewed publications. This large body of work, describing the effects of marine reserves through field-based research, presents a wealth of information that can be useful to guide decisions about whether to establish a reserve, how to do so, and how to evaluate their success. This information has been used in synthetic studies including meta-analyses of reserve effects across the globe, impacts of marine reserves versus partially protected MPAs, and spillover from reserves.
The team, working with a Science Writer, translates information from technical scientific papers into a format that is accessible to broad audiences. Working with a Graphics Designer, Design Staff, and Web Developers, the team has created engaging and easy-to-understand graphics that communicate general concepts about the effects of marine reserves. These resources use actual data from peer-reviewed research presented in unique ways.
The graphics, including both static images and interactive animations, and the accompanying text developed by the team form the basis for the most recently developed tools: the Science of Marine Reserves web resources. Along with a range of other partners, the Science of Marine Reserves Team has provided the scientific information about marine reserves in the newly released Ocean in Google Earth Marine Protected Area (MPA) Layer. The data and graphics are connected to geographic locations, allowing users to dive from reserve to reserve across the globe. Interactive graphics in the new Ocean in Google Earth MPA Layer illustrate the results of research inside marine reserves, revealing how communities of animals and plants respond to full protection.
The goal for all of these tools is to provide an easily accessible and engaging resource for those who are asking questions about marine reserves by connecting scientific information to educate scientific, public, and political audiences.
As the director of the Science of Marine Reserves (SMR) Project, Dr. Kirsten Grorud-Colvert is responsible for coordinating all aspects of the PISCO educational tools that communicate the science of fully protected, no-take marine reserves to diverse national and international audiences. This scientific information forms the basis for a number of resources, including the most recent versions of The Science of Marine Reserves booklets and the geospatial reserve data viewed in the MPA Layer of Ocean in Google Earth. With a background in field research, Kirsten actively works to bridge the gap between scientific findings, policy implementation, and public understanding of marine reserves as a conservation tool, both in the US and internationally. She is involved in both research studies and syntheses of the effects of marine reserves, which have led to peer-reviewed publications and outreach materials aimed at diverse audiences.
Dr. Steve Gaines, a Primary Investigator of PISCO, provides guidance for the Science of Marine Reserves Team as a convening lead author of the 2002 version of The Science of Marine Reserves and all subsequent resources developed from this large-scale synthesis. Steve has a special interest in making scientific information more accessible in web-based formats, and through work with Google and other web partners, has provided leadership in tailoring science for the web. Steve has led the way in scientific studies of marine conservation, biogeography, effects of climate change on coastal ecosystems, effects of ocean circulation on dispersal, and sustainable fisheries. He is the director of the Marine Science Institute at University of California, Santa Barbara, where he oversees UCSB studies of coastal ecosystems in southern and central California and around the world.
Dr. Phillip Fenberg is the EU Marine Reserves Science Coordinator and the Project Director of the European version of the Science of Marine Reserves educational booklet. This booklet applies global lessons to a European context and features case studies from relevant marine reserves in the region. As part of this work, Phil leads the research and production of the booklet, development of associated online case studies and animations, and is conducting a regional meta-analysis aimed at investigating the effects of EU marine reserves and associated data gaps.
Dr. Satie Airamé is a founding co-author of The Science of Marine Reserves booklet series and served as a production advisor on the most recent booklet versions. Satie works with policy makers, managers, and the public to listen, learn and share information to support science-based policy and management. The primary avenues for communication are public meetings, workshops, booklets and brochures, popular articles, web-based resources, and video. She also serves as an internal resource for PISCO scientists by tracking policy issues and working with PISCO scientists to provide relevant information to policy makers and managers, identify information gaps, and adapt or augment PISCO's research to address management priorities.
Monica Pessino has been part of the Science of Marine Reserves Team since the first version of The Science of Marine Reserves was published in 2002. As creative director she is responsible for the design and production of the booklets and collateral material. Monica works closely with the team to communicate scientific information by creating enticing visuals. She handles the interaction with printers for estimates, production issues, and quality control in order to reach superior final products. Monica is the Creative Director of Ocean o' Graphics, the Marine Science Institute graphic design and production studio, at University of California Santa Barbara. Ocean o' Graphics is a full graphics studio, meaning the projects may start from conceiving an original idea to developing it. The studio offers a wide gamut of services: print material, website design, video production and editing, signage, and wearables.
Dr. Sarah Lester is a Project Scientist at the University of California, Santa Barbara. Sarah joined the Science of Marine Reserves team when she conducted, with the help of numerous colleagues, the most recent global synthesis of scientific studies of biological effects within marine reserves. The data from this synthesis is the foundation of the interactive graphics in the Google Earth MPA layer. Sarah was also a contributing author on the 2007-08 Science of Marine Reserves booklets. Sarah enjoys helping to find innovative ways to connect scientific information to diverse audiences and believes the internet and Google Earth offer exciting new opportunities to reach more and more people. Sarah is actively involved in studying the effects of marine reserve protection, in addition to conducting and coordinating research on ecosystem-based management, ecosystem services, and sustainable fisheries.
Michaela Clemence is a graduate student at the Bren School of Environmental Science at the University of California, Santa Barbara studying coastal marine resources management. She joined the PISCO team as the Assistant Project Director for the European version of the Science of Marine Reserves booklet, where she worked to translate complex scientific information into accessible figures, case studies, and content for the booklet. Michaela has previous experience working with the National Marine Fisheries Service investigating the role of marine protected areas in resource management in the U.S. Virgin Islands. Her graduate work is focused on marine spatial planning, and she is interested in using this approach to bridge communication gaps and reduce conflicts between resource user groups.
Chad Burt is a Web Developer for the University of California, Santa Barbara, and a graduate of its Biology program in the College of Creative Studies. Chad was responsible for programming the original interactive animations that make up the Science of Marine Reserves content in Google Earth. This involved developing code that translates data of reserve effects into accurate visual indicators such as the size, number, and diversity of fishes in a scene. Chad also contributed artwork for the California Channel Islands animation. Beyond serving as a technical advisor to the Science of Marine Reserves Project, Chad is involved in developing applications to visualize ecological monitoring data, and tools used to plan new marine protected areas along the California coast.
As the science writer for the Science of Marine Reserves booklets, Peter H. Taylor integrated and distilled pertinent scientific information to make it accessible and useful for policymakers, managers, and stakeholders. He worked closely with SMR's team of science and policy experts to ensure that the best, most up-to-date science was communicated accurately. Peter is the principal of Waterview Consulting in Yarmouth, Maine. His primary interest is finding and implementing innovative methods for transferring science from the knowledge realm to the action realm. For more than a decade, Peter has planned and produced communication resources (printed and interactive) for non-profit, government, academic, and commercial organizations at local to international scales. His writing and photography have also been published in Outside, National Wildlife, Sierra, and other magazines.
Molly Thomson is a graphic designer at Ocean o' Graphics, the graphic design studio within UC Santa Barbara's Marine Science Institute (MSI). She works with the Science of Marine Reserves team in order to create visuals of marine life and their habitats, which are used to illustrate collected data in Google Earth's MPA layer animations.
Tom Rassweiler is a game developer and ex-coral reef researcher. Tom is the Web Developer in charge of updating and creating the Science of Marine Reserves animations visible in Google Earth, with a special focus on animations created for the European marine reserve case studies and booklet.


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Lightweight soft case for keyboard, w/ wheels & handle featuring: strong black nylon covering - large zippers and heavy duty stitching throughout - top and bottom protective plywood plates - thick foam padding with hard reinforced base - removeable plush interior - large zippered music pouch - strong webbing handle with Velcro locking - pull out handle and skate-style wheels for easy carrying and secure transportation - Fits most of the keyboards currently on the market - Inner Dim.(LxDxH): 111 x 49 x 18 cm / 43.7 x 19.3 x 7.1 in.
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... everything up! Oh well, plenty of time yet.
Sunday February 8th
Didn't realise we'd stayed at the hotel hosting the international door banging contest last night, but it appears we had. The French team definitely won.
Left Calais and set off to Belgium. Poor Calais, does anyone stay longer than the one night? Even if you put two nights into Expedia it automatically reverts back to one. Had an ...
Paris, Amiens and finally, Calais
... Orsay. This should be a must if you want to see the works of Masters (Monet, Renoir, Cezanne, Picasso and others) in a wonderfully simple setting and with no crowds. In fact there was so much it was overwhelming. So, that was the culmination of another fabulous day. Tomorrow is Versailles day.
When we said Versailles day, we should have stipulated 'all things Versailles but not the Chateau'. This is because we 'did' the Chateau big-time last time. Not ...
Beware of Luxembourg, It is small and sneeky
... out to be 70 miles and an hour ride in twisty hills.
But Calais is only about 600 kms, and on the German roads, we are traveling at around 130 kph.
The concept of " we'll leave after breakfast" was a lot more immediate than I expected, too.
As we finished breaky, and the dozen or so that were leaving now were saying to each other "see you down at the bikes", so I went to my room to gather my packed bags, and went down to ...


text:
"Professional engineers and surveyors dedicated to building a better California."
Member login
2016 Legislative Report Card
ACEC California monitors and tracks all state legislation, and at the end of each legislative session a report card is developed and made public. Such a report allows our members to clearly see where their elected officials stand on issues important to the engineering and land surveying industry and helps us hold our state representatives accountable.
To calculate the percentages shown on the report card, the final Floor votes of 9 bills voted on in the Assembly and 9 bills voted on in the Senate were used. It is important to remember that while this report card is a collection of ACEC California's highest priority bills, it is only a snapshot of the thousands of votes that take place over the course of the year. One unfavorable vote drops one's "grade" significantly. Furthermore, it takes great courage to stand up and vote counter to one's party leadership. In many cases, the member who does that is more valuable to our legislative advocacy efforts than the member with a higher percentage rating.
Please take a moment to review ACEC California's 2016 Legislative Report Card. Click here.
16 hours agoACEC in the California High-Speed Rail Authority's Newsletter


text:
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Free personalized radio that
plays the music you love
Collection: THUG (The House Of Urban Grooves) JAZZ
Selected Discography
Track List: THUG (The House Of Urban Grooves) JAZZ
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From my elementary school trumpet roots of 1966 to now, this encompasses the whole package of soul, funk, and rhythmic jazz. Thank you Pandora.
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"I have offers from Kentucky, Penn State, Kansas State, Wake Forest, UMass, Miami of Ohio, UNC-Charlotte, Wofford, Mercer and South Alabama," said Amari Henderson. "Michigan is also recruiting me."Wake Forest and Kentucky are recruiting me the hardest. It definitely means a lot to me that they are showing so much interest."
His most recent offer was from an SEC school.
"Kentucky offered me during the spring evaluation period," said the 6-foot-1, 170-pound Henderson. "The SEC is a big-time conference, so it means a lot for a school from that conference to come down to North Carolina and offer me. It's a nice program and they have great coaches. I'm definitely interested in them."
What's next for Henderson?
"I plan on visiting Michigan, Kentucky and Wake Forest," he said. "I'm going to Wake Forest on July 18, Kentucky on July 22 and Michigan on July 28.
"I'm looking forward to seeing the atmospheres and academics at the schools. I also want to see the chemistry I have with the coaches."
He has a timeline for his college decision.
"I'm going to narrow it down between three and five schools during the season," Henderson said. "Then after the season, I plan on committing."
Henderson claims no favorites at this time.


text:
Sylvester Stallone in Cliffhanger is a poor example of a top male climber. There are too many to cite but Chris Bonington and Doug Scott spring readily to mind, neither of whom have huge shoulders, barrel chests or gritted teeth.
Besides, women climbers climb for themselves not to compete with or against male counterparts. Julie Tullis, who was killed on K2, when asked why she climbed said: "In my personal experience mountaineering is far more than a sport. It has a deeper meaning, trying to achieve a harmony with nature."
This harmony can be achieved by women climbers at whatever level they climb. No male image is needed to achieve this.
T M Sanders
Little Eaton, Derbyshire
- More about:
- Actors And Actresses
- Climbing
- Derbyshire
- Sylvester Stallone


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quite place somewhere good conversation quite music.
Our first date from MY point of view.....Perfect, I wanna have coffee of course. Best conversations always begin with a cup of coffee;-)
A stroll around London Zoo, followed by a hearty meal in a fine gastro-pub. Good food is preferred, good company is essential.
Something simple.
Walk on a pier
i'm not sure but fun.........maybe dinner and drink's
dinner or a nice drive in the country. Maybe a movie
something simple like going to the movies or out to eat.
basically getting to know each other is my first idea:))
How about a movie and dinner followed by a nice walk in the park.
For our first date we may go for coffee or cold drink maybe a pinic in park I am open to suggestions. What a Lady wants a Lady gets. If you have a pet would like to meet him/her also.
just sit down and talk it doesn't matter where we go just have some fun...
There are so many ideas here. The one requirement is being able to carry on a conversation.
LargeFriends does not conduct background checks on the members of this website.


text:
Peter Ebdon staged a magnificent recovery at Wembley Conference Centre last night to defeat Stephen Hendry 5-4 in the quarter-finals of the Benson and Hedges Masters.
The Londoner fought back from 4-2 down to inflict only Hendry's second defeat in 26 games in the Masters. "Considering the circumstances, pressure, tension and occasion I am delighted," Ebdon, the world No 10, said.
Both Ebdon and Hendry, seeking to win the tournament for the sixth time in seven years, made poor starts. Ebdon, who beat the Scot on his way to the 1993 Skoda Grand Prix title, took the fifth frame with a 67 break. But a 141 clearance gave Hendry the sixth frame, a chance of the £10,000 bonus for the tournament's highest break and a 4-2 lead that put him on the verge of a semi-final against Ronnie O'Sullivan.
Ebdon, the former world junior champion, dominated the next two frames with runs of 46 and 47 to make a sudden death deciding frame necessary. Once again Hendry looked the more likely winner when he established a 37-1 lead but, on a break of 36, overcut a red to a top pocket to throw Ebdon a lifeline. Ebdon replied with a 53 break but looked to have missed his chance when he failed to pot an extremely difficult last red across the top cushion. Hendry potted the red and a black but, with tension at fever pitch, missed a yellow with the rest. It was his last mistake.
Terry Griffiths found time to laugh despite taking a 5-2 beating from O'Sullivan. The Welshman was trailing 4-2 when O'Sullivan put together a break that put him in command of the seventh frame, and someone in the crowd shouted "taxi for Terry Griffiths". "By that time I'd well and truly lost and I thought it was amusing," Griffiths said.
Benson and Hedges Masters (Wembley): Quarter-finals: R O'Sullivan (Eng) bt T Griffiths (Wal) 5-2; P Ebdon (Eng) bt S Hendry (Sco) 5-4.
- More about:
- Ronnie O'Sullivan
- Snooker
- Stephen Hendry
- Steve Davis


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I worked for a company where my job was in California ("at
Customer Question
I worked for a company where my job was in California ("at will" state) but the parent company is in Portland, Oregon (not sure if it's "at will" too). I believe I have a discrimination case to pursue but have been told that in an "at will" state, they can lie and say anything and if there's no contract in place, there is no recourse. Is this correct?
5 years ago.
California Employment Law
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Patrick, Esq.
replied 5 years ago.
Hello and thank you for entrusting me to answer your question. I'm so sorry that you have been treated poorly by your former employer.
Since you worked in California, the labor laws of California would apply to your claim, typically speaking. It is true that California is an "at will" employment state, meaning that an employer can terminate an employee without a contract guaranteeing a specific term of employment for any reason or no reason, upon giving notice. (Labor Code 2922)
One of the exceptions to the "at will" employment doctrine (and there ARE several exceptions) is that an employer CANNOT terminate an employee for reasons that relate to the employee's race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, marital status, sex, age (over 40), or sexual orientation. (See Govt. Code 12921.)
Of course, employers rarely if ever admit that the reasons for an employee's termination relate to their race, religion, etc. Employers are smarter than that, and yes, they will often times "say anything" to make it seem as though the employee's termination was legitimate.
But, just because an employer can CLAIM termination was for legitimate reasons pursuant to the "at will" employment doctrine does NOT mean that they are free to terminate an employee for discriminatory reasons and then simply lie about their true motivations.
The Department of Fair Employment and Housing will examine all of the circumstances surrounding an employee's termination, including the employer's past history of complaints, a culture (if any) of discrimination within the company, remarks made to the terminated employee in passing, and anything else that is relevant to determine what the employer's TRUE motivations were.
If you believe that you have been the subject of unlawful discrimination and wish to file a lawsuit, you must first file a formal complaint of discrimination with the federal Equal Employment Opportunity Commission (EEOC) or California's Department of Fair Employment and Housing. Either the EEOC or the DFEH will issue you an authorization to sue after they investigate your claim. You don't need to file with both agencies. Finally, if you decide to sue, don't miss your deadline. Under federal law in California, you have 300 days from an act of discrimination to file a complaint.
For information on how to bring a claim through California's DFEH, visit this link: http://www.dfeh.ca.gov/Complaints.htm For information on how to brig a claim through the EEOC, visit this link: http://www.eeoc.gov/employees/charge.cfm
I sincerely XXXXX XXXXX this information helps you and I wish you the very best of luck. Bear in mind that none of the above constitutes legal advice nor is any attorney client relationship created between us.
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replied 5 years ago.
thank you for your help and answer. In using my current membership, I wasn't sure if I get to continue asking you questions or if I need to go back to the "pool". If I can ask you, here are some additional questions:
If I contact EEOC, is it a complaint or a suit?
If I have grounds to pursue a lawsuit, are these normally contingiency suits or pay as you go?
Are there any legal guidelines for severence packages? how many months a person should be paid for years of service?
Thank you
Patrick, Esq.
replied 5 years ago.
Hello and thank you for your followup. Normally new questions must be asked separately, but I will be happy to address your additional concerns here.
If I contact EEOC, is it a complaint or a suit?
It's not a lawsuit until you file in civil court. The EEOC will investigate your claim, issue an "EEOC complaint," and then potentially issue a ruling of its own, which can have binding effect on an employer even though it is not a judgment from a lawsuit.
The DFEH is a California agency which essentially does the same thing.
For information on the EEOC complaint process, visit this link: [urlhttp://www.eeoc.gov/federal/fed_employees/complaint_overview.cfm[/url]
If I have grounds to pursue a lawsuit, are these normally contingency suits or pay as you go?
These cases are often pursued on a contingency fee basis. If you have a reasonably strong case, you should be able to find an attorney willing to take you on as a client. However, since a "contingency fee" means the attorney doesn't get paid unless you win, it might be hard to find an attorney willing to risk his time on a case that is not strong and may lose.
Are there any legal guidelines for severence packages? how many months a person should be paid for years of service?
Under the federal WARN Act, an employer with at least 100 employees that lays off at least 50 during a 30-day period must either give 60 days notice of the lay off or pay 60 days wages. This is the only circumstance in which severance is mandatory. Otherwise, there is no law, either state or federal that requires an employer provide any severance at all. Thus, the employer is entitled to impose whatever requirements it wishes concerning the severance -- including, simply changing its mind and not offering any severance -- unless it violates the WARN Act.
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