text: Distribution decisions in international context External factors Structure of distribution/channel Conflict & Control issues Managing logistics Role of channel intermediaries 1. coordinate and assemble international buyer demand and product availability reduce bargaining asymmetry between buyers and sellers in different countries and cultures 2. protect buyers and sellers from opportunistic behavior to serve as agents of trust in cross-cultural context 3. reduce market transaction costs 4. match buyer and sellers in different countries – establish contacts and customer relations in selected markets 5. provide physical distribution/logistical support necessary for the company's product category Considerations in developing an international distribution strategy Customer characteristics Product characteristics Distribution channels Environmental characteristics Corporate objectives Financial Control Profit potential Investment requirements Distribution channel selection criteria Distribution density refers to the coverage a product will have within a market, I.e. can you reach all your customers? Channel length refers to the number of intermediaries directly involved in the physical or ownership path from producer to customer. Number of intermediaries are influenced by: (1) a product's distribution density, (2) the average order quantities and (3) channel membership availability. Channel alignment aims to ensure that all the distribution intermediaries co-ordinate their actions to ensure efficient delivery of products. Distribution logistics - refers to the physical movement of goods through the distribution channels. Guidelines for anticipating and correcting problems with international distributors Select distributors – do not let them select you Look for distributors capable of developing markets Treat the local distributors as long-term partners Support market entry by committing money, managers, and proven marketing ideas Maintain control over marketing strategy Make sure distributors provide you with detailed market and financial performance data Build links among national distributors at the earliest opportunity Multiple Channels serve international markets Home Country International Market End-user/ Customer Firm Regional distribution centre Wholesaler Sales Subsidiary Trading Company Buying Organisation Export Agent Distributor/ Importer Retailer Selecting an international intermediary to be considered: geographical area and market segments covered the need to avoid domain conflict among agents or distributors range of products and companies already presented complementary or competitive customers served and trade contacts used product knowledge and application experience servicing and after-sales service capability level and form of commission of margins required legal rights and responsibilities Conflict of interests? Manufacturer Intermediary Value added in the downstream channel Supplier replaceability Transaction costs reduction Mutual support and trust Intensive, selective and exclusive distribution M = Manufacturer W= Wholesaler R = Retailer Source: Lewison, 1996, p. 271. Channel cooperation, conflicts and trust channel conflict arises when one channel member perceives another to be impeding the achievements of its goals There are three main sources of conflict: incompatible goals between large manufacturer exporters and small retailers domain conflict where manufacturers compete with wholesalers for market territory incongruent perceptions of the distribution task and how it should be performed Support measures the company can take: to provide sales and promotional materials written in the local language to visit the agent or distributor regularly and to visit customers together invite agents-distributors to company premises regularly to ensure that the price structure provides a genuine financial incentive to provide updates on products, markets, and company developments


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Fasth or Hiller
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I don't know why, but I'm not really in the Fasth bandwagon yet. Yes, he plays well and is a good goalie, but I think a lot of it is due to the team in front of him playing very good. Sure he's a part of it, but he's not the reason we're winning right now. He makes the stops he has to keep us in the game, but it isn't like he's stealing games for us like Hiller sometimes does. Fasth seems to let that one easy goal in every second game, but so did Hiller. The only real thing I don't like about Fasth is his stick play. Sometimes he gives some nice Hail Mary passes, but last night in Nashville he gave at least two turnovers by hitting the puck along the borders instead of letting the D take it behind the net.
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subset: commoncrawl


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A Quagmire for the Arts Industry
The non-profit arts research group, Americans for the Arts, announced yesterday that there have been losses in charitable giving and a declining attendance at larger cultural institutions, even as the number of arts organizations has grown.
The study, called the National Arts Index, based its research on 76 national-level research indicators produced by the federal government and private research organizations.
It found that there was a steady increase in the number of artists, arts businesses and nonprofit arts organizations, and arts-related employment from 1998 to 2008. Nonprofit arts organizations alone grew in number from 73,000 to 104,000 during this period, according to the non-profit's website, but one third of them failed to achieve a balanced budget.
Another key finding in the report is that public participation in art, including making art and playing music, is up. But, attendance at mainstream nonprofit arts organizations is in decline. Only half the music and CD stores that were open five years ago are still open, while online downloads have grown exponentially in the past three years.
Arts and culture groups are also losing their market share of philanthropy to other charitable areas, even as the demand for arts education has increased. College arts degrees conferred annually have increased from 75,000 to 120,000 in the past decade.
To view the entire report, head to the Americans for the Arts website.


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View the rest of your items by clicking on the link below
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Find out how much of this scent to use
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Zanzibar Spice: This fragrance is a hint on the masculine side but women will love using it too. Your nose will first pick up on the Mandarin Leaf, Agave Nectar and African Lotis then you'll notice they're perfectly paired with spices like cardamom, Nutmeg and Black Peppercorn. The dry base notes of Safari Sandalwood, Patchouli and Tonka Bean hold it all together for the perfect combination of "sugar and spice and everything nice". This fragrance will discolor to a medium brown and works great in cold process.
Vanilla Content: 3.3%
NOTE: This medium-flashpoint oil (199ºF) cannot ship via USPS regardless of the shipping method you choose at checkout.
Photo Attribution: © Can Stock Photo
This behaved well in cp for me, a little acceleration but definitely workable. I was able to do a nice design with plenty of time. The smell is just ok for me. I wasn't expecting this to be a run of the mill vanilla musk smell so it was a little bit of a bummer but it wouldn't be a nice blending fragrance I think. It came through very strong at .7oz pp.
Amazing scent, very exciting...soaps well and stays long and hard in CP. I have some that is about 6 months old and it is still going strong. Very pleasing scent to smell and work with!!
Definitately one of my favorite Brambleberry fragrances. Everyone that smells my soaps with this has LOVED it over the past two years. Awesome stuff.
I bought this fragrance after reading the reviews and am so happy I did! I thought it smelled great out of the bottle but the real surprise was from the cold process soap! AMAZING!! My husband and I both love it!! It sold super fast at my shows too!! Off to buy a bigger bottle now!
This is one of my best sellers with the men. To me it smells like an exotic island, a rich fragrance. Definitely a fan.
We're a friendly group who love social media. See you 'round the web!


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Un pequeño paraíso: aislado del mundo, es un lugar en el que se puede estar tranquilamente
The house is located in La Marsa Corniche one of the most beautiful, clean and save neighborhoods in Tunisia. It's in walking distance to shops, restaurants, bars, beach promenade and ice cream parlors as well as the train station where you can take the train straight into the capitol. Taxi are available and very affordable on every street. Sidi Bousaid, a traditional Blue and white seaside town and tourist magnet is just a 5 minute taxi ride as are the numerous Roman archaeological sides in Carthage.
Para organizar un intercambio de casa, debes ser miembro


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Let us know when your receive great advice so we can thank our lawyers and point others with similar questions in the right direction.Got it!
I was in a car wreck eight months ago and did not hire a lawyer is it to late now?
No, the most likely deadline is two years, but there are MANY exceptions that can make that deadline much shorter. For example, I recently closed a case for $1 million dollars for a Texas accident, but we had to file it in Kentucky, where the safest deadline was only 1 year.
Also, the better the attorney, the less likely they are to accept your case the closer you get to the deadline.
And, the more time passes, the harder it is to secure evidence that can make a huge difference.
Feel free to call: 88.473.2820.
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|Fearne Cotton's Midnight Manicure
I adore the packaging too. You can pick up the Fearne Cotton range at Boots.
Unless otherwise indicated products reviewed are press or brand samples. Links may be affiliate links which means that if you make a purchase through one of our links we receive a small commission which helps support and run this website.
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7 Responses to Fearne Cotton's Midnight Manicure
Tanya Prendergast January 5, 2012 at 10:22 am #
Love these! I recently bought a gold revlon nail polish and I love the metallic. I am now in need of a decent silver.
xsuziebellx January 5, 2012 at 10:55 am #
Ohhh yeah the silver is fab!! I love the dark red also.
I got a fab little nail kit for christmas also! Its a 17 set with lovely metallic nail polish, nail jewels and little stickers. I wore the lovely gold polish for new year as it was so lovely and glam!!xx
samantha fox February 26, 2012 at 5:36 pm #
i love these, i tried to buy some but every time i went they had run out, I am sooo jealous lol x


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Public Patches (PC Windows) (6)
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Battlestations introducing the plugin that transforms your browser into a lightning fast, cinematic way to enjoy photos. We are ready for that, get free plugin for your browser here.
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Ria: Dream World
The rest of the afternoon went well and we soon found our selves settling down to sleep.
I have a bunk bed so I was up top and El was below on the fold out sofa.
"Night, El" I yawn.
"Night, Ria" she says back. It doesn't take me long to fall to sleep. I mean we did stay up till 2 in the morning.
Then I enter my dream.
"What the?" I look around. I'm in a sort of citidal. Yeah, thats what I would call it.
"Ahh" Vee comes tumbling out of the wall. The portal she came through closing after her. I run over and help her up.
"Ria?" she says shocked. She looks around amazed. "Where are we?"
"I don't know but.... I think its something to do with the bracelets" Just as the words are out of my mouth. El and Sam come tumbling out of walls opposite each other and collide.
Me and Vee look at each other then split running over to help out friends. I go to El and Vee to Sam. We help them up.
"What we share each others dreams now?" Sam says a bit angry. "I do have private thoughts you know who did this?"
We look around at each other no one steps forward.
"I didn't do it, did you two?" I say. They both shake there heads.
"I think the bracelets did it" El says. "Oh my gosh, look at our outfits"
And I do, we all do. Its then I notice we are all wearing pure white summer dresses. "This is taking the mick" I say.
"Agreed" everyone choruses. Then a happy bright look comes across Vee face that we all know the meeting off.
Before Sam has time to say something Vee shouts. "Adventure time. Lets check this place out"
Its a bit annoying cause we don't know where we are but we all agree as long as we stick together.


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In this exercise, you will add a top navbar to the Nan & Bob's Online site, build new pages for "Books" and "Contact", and set specific page transitions. The solution should look something like this:
We use
$.mobile.defaultPageTransition = 'flip'; to set the default page transition to
flip in a
script block in the
head of index.html; note that the script comes after we link the jQuery library but before we link jQuery Mobile.
We add a navbar to the
div with links to
#books, and
We add two new
divs with
data-role="page", one each for the
#books and
#contact pages.
We set, using
data-transition="slideup", a custom page transition between the
#books and
#home pages and between the
#contact and
#home pages


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Welcome to PlowSite. Notice a fresh look and new features? It's now easier to share photos and videos, find popular topics fast, and enjoy expanded user profiles. If you have any questions, click HELP at the top or bottom of any page, or send an email to firstname.lastname@example.com. We welcome your feedback.
Removing packed snow and ice from sidewalks
Discussion in 'Ice Management' started by Leanworks, Dec 28, 2011.
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It seems like most businesses are marketing online these days, but not all of them are seeing the success that they want. Snaptech Marketing helps companies get the results they want online using data-driven strategies while constantly adapting to the digital landscape.
On June 9th, Snaptech will be co-hosting an event with Google at the Vancouver Club that will teach businesses how to laser focus their digital marketing. Learn with Google will feature both a morning and afternoon seminar, as well as one-on-one sessions with Google experts. To register, visit MasterDigital.ca.


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Palm Pre 2 webOS smartphone
Palm Pre 2 review: The Palm Pre 2 has outdated hardware compared to its rivals, but webOS' handling of multitasking and notifications is excellent
Palm Pre 2 review: The Palm Pre 2 has outdated hardware compared to its rivals, but webOS' handling of multitasking and notifications is excellent
The Palm Pre Plus effortlessly handles multitasking and notifications, but its hardware feels dated
The long-awaited Palm Pre lives up to the hype with a responsive touchscreen and an engaging interface, but a few hardware design flaws keep it from being the perfect smartphone.
In case you missed it, HP overnight launched three new devices based on Palm's webOS platform; a TouchPad tablet, a Pre 3 smartphone and a compact Veer smartphone. Sadly, none of these slick looking products are ever likely to make it down under.
Palm's official webOS app store has come a long way. With only 30 apps available> at the App Catalog's launch last June, there wasn't much for early Palm Pre owners to get excited about. Today, however, the App Catalog sports well over a thousand tit...
Palm opened up its WebOS developer program to the public on Thursday, saying it expects to see a flood of new applications developed for the mobile OS.
A Palm Pre user is suing Palm and Sprint Nextel, alleging they caused him to lose most of the data from his phone, and he wants to turn the suit into a class action.
Artifex Software is suing Palm over the PDF (Portable Document Format) viewer in Palm's Pre smartphone, it said on Thursday.
Palm has stayed very quiet since its releases of the Palm Pre and Pixi devices this summer, which debuted the WebOS that was at one point seen as a key rival to Apple's iPhone.
Motorola's Droid has a tough game of catch-up to play, but not as tough as what faces Palm's Pre as both challenge Apple's iPhone. Longer term, this may be a two horse race, with Android winning in the end and BlackBerry still chugging along.
The release of the iTunes 9.0.2 update on Thursday yet again disables Palm's workaround to sync with Apple's popular jukebox software. Perhaps it's high time Palm moved on and created its own software.
Browsing the Web while you're on the move is one of the perks of owning a smartphone. The new touchscreen phones now entering the market are ideal for this job, as they're equipped to display Web pages on their large, high-resolution screens.
The Palm Pre's WebOS browser is a relatively recent entrant in the mobile browser arena, arriving in early June of this year. But the Pre's new mobile browser comes fully prepared for a battle royale with other leading smartphone browsers.
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HP OfficeJet Pro 8730
A smarter way to print for busy small business owners, combining speedy printing with scanning and copying, making it easier to produce high quality documents and images at a touch of a button.
HP OfficeJet Pro 8730
I've had a multifunction printer in the office going on 10 years now. It was a neat bit of kit back in the day -- print, copy, scan, fax -- when printing over WiFi felt a bit like magic. It's seen better days though and an upgrade's well overdue. This HP OfficeJet Pro 8730 looks like it ticks all the same boxes: print, copy, scan, and fax. (Really? Does anyone fax anything any more? I guess it's good to know the facility's there, just in case.) Printing over WiFi is more-or- less standard these days.
HP OfficeJet Pro 8730
As a freelance writer who is always on the go, I like my technology to be both efficient and effective so I can do my job well. The HP OfficeJet Pro 8730 Inkjet Printer ticks all the boxes in terms of form factor, performance and user interface.
Windows 10 for Business / Dell XPS 13
I'd happily recommend this touchscreen laptop and Windows 10 as a great way to get serious work done at a desk or on the road.
Windows 10 / HP Spectre x360
Ultimately, I think the Windows 10 environment is excellent for me as it caters for so many different uses. The inclusion of the Xbox app is also great for when you need some downtime too!
Windows 10 / Lenovo Yoga 910
For me, the Xbox Play Anywhere is a great new feature as it allows you to play your current Xbox games with higher resolutions and better graphics without forking out extra cash for another copy. Although available titles are still scarce, but I'm sure it will grow in time.


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Clementine (Clockwork Century Series #2)by Cherie Priest
Adding insult to injury, her first big assignment is commissioned by the Union Army.
- LendMe LendMe™ Learn More
Maria Isabella Boyd's success as a Confederate spy has made her too famous for further espionage work, and now her employment options are slim. Exiled, widowed, and on the brink of poverty...she reluctantly goes to work for the Pinkerton National Detective Agency in Chicago.
Adding insult to injury, her first big assignment is commissioned by the Union Army. In short, a federally sponsored transport dirigible is being violently pursued across the Rockies and Uncle Sam isn't pleased. The Clementine is carrying a top secret load of military essentials--essentials which must be delivered to Louisville, Kentucky, without delay.
Intelligence suggests that the unrelenting pursuer is a runaway slave who's been wanted by authorities on both sides of the Mason-Dixon for fifteen years. In that time, Captain Croggon Beauregard Hainey has felonied his way back and forth across the continent, leaving a trail of broken banks, stolen war machines, and illegally distributed weaponry from sea to shining sea.
And now it s Maria's job to go get him.
He's dangerous quarry and she's a dangerous woman, but when forces conspire against them both, they take a chance and form an alliance. She joins his crew, and he uses her connections. She follows his orders. He takes her advice.
And somebody, somewhere, is going to rue the day he crossed either one of them.
Product Details
- 9781596063662
- Publisher:
- Subterranean Press
- Publication date:
- 12/31/2010
- Series:
- Clockwork Century Series , #2
- Sold by:
- Barnes & Noble
- Format:
- NOOK Book
- Sales rank:
- 337,451
- File size:
Customer Reviews
Average Review:
Most Helpful Customer Reviews
See all customer reviews
I got into this author after reading boneshaker... I jumped right in and read this book. Its good, but slow and never picks up hopefully the next book i read from her will be less mediocre.
A fun expansion into the greater world introduced in Boneshaker. This book follows Croggon Hainey as he chases down his stolen airship, and former CSA spy turned Pinkerton agent Maria "Belle" Boyd chases him. We get to see more of country and the impact of the long-running Civil War. This is a fast-paced adventure that kept me wanting more. Really enjoying this series.
Cherie Priest scores another hit in her rich world of an alternate 19th Century USA in which the Civil War is stretching out for decades. She creates very distinctive lead characters and then does a good job of putting them through the ringer in this short (208 pages) book, picking up the thread of a plot about escaped slave and air pirate Captain Croggin Beauregard Hainey, who had a small part in the novel Boneshaker. In pursuit of him is a new character, too-famous-to-be-a-spy ex-Confederate spy Maria "Belle" Boyd, now working for the Pinkerton Detective Agency on behalf of the Union Army. The action is kept fast and furious and fairly believable. The use of geography over mid-America is made interesting by using powered airships (she's never precise about how the engines work, propellers?) to move quickly between cities. I had a little trouble believing that landing a powered and armored dirigible anywhere within a mile of a remote building could be done with any amount of stealth. Perhaps the commonplace nature of airships in this world allow for it. Another failing, if I may call it that, is that there is no clear antagonist in the story. Well there is one, but they are kept all too mysterious and unexplored. Upon reflection, Boneshaker could be seen to have a similar shortcoming. In any event, the whole thing is an enjoyable and all too short romp that reminded me of one the better episodes of The Wild Wild West. Belle Boyd would certainly give James West a run for his money.


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|Scout.com's complete coverage of The Opening 2012 presented by NIKE
Has always stood out on the camp and combine scene, but this chance to show it with the pads on will be right in his wheelhouse. Tanacious is a good word to describe him.
QB Tyrone Swoopes - Whitewright HS (Texas) -Texas Commit
Plays on a small stage in high school, but should be used to the big stage by now. So far at the major events he has started off slow to then come on very strong at the end.
RB Ezekiel Elliott - John Burroughs HS (Mo.) - Ohio State Commit
Will not get the chance to run over anybody, but will be one of the more impressive specimens. The future Buckeye won RB MVP honors at the Chicago NFTC.
S Kameron Miles - West Mesquite HS (Texas) - Tennessee Commit
A safety prospect who is packed in to the frame of linebacker. He does play downhill from his safety spot, but has quick feet which allows him to stay strong in coverage.
WR Corey Robinson - San Antonio Christian HS (Texas) - Notre Dame
Robinson shed his sleeper status with a strong showing at the DFW NFTC, where he earned Scout.com All-NFTC honors. Long and smooth possession style receiver.
WR Eldridge Massington - West Mesquite HS (Texas) - USC
Massington just keeps getting better. He has great straight line speed and is fearless about going up in the air to get snag balls. A true deep threat who will stretch the field.
WR Jacorey Warrick - Cypress Falls HS (Texas) - Texas
A slick receiver who operates most effectively out of the slot. He is quick in and out of his cuts and has long arms that he uses to catch the ball where DBs can not knock it out.
WR Jake Oliver - Dallas Jesuit HS (Texas) - Texas
An interesting receiver. Runs good routes, which makes him tough to cover, but is also strong. Could play inside or outside. A devastating blocker in real games.
WR Ra'Shaad Samples - Dallas Skyline HS (Texas) - Undecided
Coming off of a foot injury that he suffered at the DFW NFTC (where he was on his way to MVP honors). If he is ready to perform he will be one of the treats to watch. Will be announcing his decision.
WR Ricky Seals-Jones - Sealy HS (Texas) - Undecided
The number one player in the state of Texas is the ultimate weapon. He is a huge target who can run good routes, has strong hands and will put up possible NFL combine times.
WR Torii Hunter Jr. - Prosper HS (Texas) - Undecided
A well-rounded weapon. He is silky smooth and has the ability to contort his body to get in to a position to make tough catches. He does this effortlessly.


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37 year old female with rolling acne scars. Should I try dermapen, lasers, or facelift? (Photo)
Had cystic acne as a teen and was on a myriad of medicines (accurate twice etc). At age 23, co2 laser resurfacing. Now after two children and aging, my skin is starting to sag and elasticity is wearing. Scars are showing more deeply. My normal surgeon (performed mainly 5 lipo surgeries on me and a temporary lift), suggests a mini facelift to smooth out the scarring. Is there anything that will work better? Seems I will just have this complaint again in another 10+ years when my skin ages again.
Doctor Answers 3
Acne Scarring -- Requires a Combination of Fractional Laser Resurfacing, Fillers Like Bellafill, Subcision and Eclipse Micropen
this type of scarring needs a combination of lasers, fillers, subcision, surgery. I suggest you see an expert. Best, Dr. Emer.
Web reference: https://www.youtube.com/channel/UCa6C2fuS-AgOnvBjr6_VSQg
Rolling acne scars
Dear JuneSorry that you have suffered so much with this through your life. Your surgeon is partly correct that a limited mini high facelift, aka cheek lift will help because the acne scars will be released from below and the skin tightened. I have had such patients.However, I do not think that it is your best option. The scars can be released via subcision without undergoing the minilift. Moreover, the contour deficiency in the "holes" of the scar are best filled with refined auto fat stem cells. There has been great success in recent times with the processing of a patients on fat for reinjection into their own body.I have seen many like you and encourage you to consider subcision with autofat. ThanksGreat question
Web reference: http://acnescarflorida.com/before-after/auto-fat-stem-cell-transplant/
Facelift for acne scars?
A facelift is not the way to correct acne scars. If you have volume loss, scars will look worse and volume replacement with fillers will help. I would treat with Infini for 2-3 sessions me then fill deeper scars with Bellfill as well as correcting volume loss with it. Please get another opinion.
You might also like...
These answers are for educational purposes and should not be relied upon as a substitute for medical advice you may receive from your physician. If you have a medical emergency, please call 911. These answers do not constitute or initiate a patient/doctor relationship.


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Gen. Ret. Pervaiz Musharraf (APML) in a fresh episode of 11th Hour with Waseem Badami.
3 thoughts on "11th Hour – 3 December 2012"
Here is a brutally honest man who tried to do his best for Pakistan. He has made mistakes in the past but they were mostly errors in judgement and bad counsel. Another government under Musharraf may not be entirely bad for the country.
Great leader. I doubt he will ever make government but I salute him for all the good he has done for his country.
There is no government in the entire history of Pakistan that has not made mistakes. We do forget that we the people of Pakistan are not all that good and we can blame Ayub or Zia or Bhuttos or Nawaz or Pervaiz or Zardari for these mistakes but when the majority of populous is corrupt then nobody can do much to put this country straight.
@Saima Khan
The thing is if you look at the history of this region, for centruries different people attacked this area, be it Ghaznawi or Bin Qasim or Alexander … you can make a big list. But were they able to win the hearts of people, or make people accept islam, the answer is NO.
On the contrary if you look at Sufi buzurgs and scholars like Khawaja Moeen-ud-din, Data Gangbush, Bara Farid Shakar etc, their message got through more successfully and thousands of people accepted islam on their hands.
So what's the bottom line, even if you are the best Dictator, still you can not win over the hearts and minds. It's the slow but steady spreading of your message which can win the hearts. For me Musharraf and all army dictators destroyed this country. They should be held accountable, no matter what they say.


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New Delhi, March 24: Prime Minister Narendra Modi on Monday, March 23 congratulated Bollywood veteran Shashi Kapoor for winning Indian cinema's top honour--the Dada Saheb Phalke award and described him as a "stalwart" of the film industry.
"Shashi Kapoorji is a fine actor & a stalwart of the film industry. I congratulate him for the Dadasaheb Phalke Award," Modi tweeted.
Shashi Kapoor has starred in over 100 Hindi films and is best known for his powerful portrayals of characters in hits like "Namak Halaal", "Deewar" and "Kabhie Kabhie". The award consists of a Swarn Kamal (Golden Lotus), a cash prize of Rs 10 lakhs and a shawl.


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Mysteryville 2
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Genre and what to do:Seek and find game. Mysteryville 2 is an exciting sequel to the challenging Mysteryville game. The game takes you to the exciting world full of challenging tasks and missions. Assume the role of Laura and have an exciting journey to Mystryville for a visit, but, unfortunately, you will not have rest instead, you will spend this journey solving the mystery of your friends' disappearance. Be ready to deal with numerous puzzles trying to reach your goal. The sequel suggests lots of new characters, features and items, which make it even more interesting than ever before. Most of the tasks suggest you to find the certain hidden objects within the time limit. Playing the game you will go through different stages and locations searching for clues. Coming closer to the end of the game, you will understand that the game will be continued.
Style and atmosphere inside the game:Mysteryville 2 is an exciting game designed with nice graphics and well-selected audio. You will watch nicely represented detailed characters, and beautifully rendered backgrounds. The game sets lots of tasks before you, fulfilling them you will search for properly hidden objects. All your actions are accompanied by well-selected sound effects as well as quite suitable background music. Overall, it is a very challenging adventure game, which needs all your attention.
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Percy's preparationsMature
I stood in the courtyard as servants rushed around me, finishing the last of the preparations for our journey. I saw Ella coming down the stairs with Agatha and beckoned them over, eager to talk to my female companions.
"Ella, Agatha, how are you this morning?"
"Well your highness." They both replied. I smiled and escorted them to their horses.
"Are you ready to embark on our journey?" I asked Ella while I helped Agatha on to her mount.
"Of course your highness. It should be an interesting visit." Her smile made me feel deliciously warm, and I wondered once again what I felt for her. I had spent the evening thinking over every moment we had spent together, wondering if she felt the same. If I had come to the conclusion that she did, I would have called off the trip and proposed to her on the spot, but I could not think that she did. So I helped her on to her horse, and smiled as she did.
I swung myself on to my mount and circcled him around the courtyard.
"Onwards my friends, unto my future bride!" We galloped from the gates, my brother on my right, and Ella and Agatha to my left. We would travel for two days, spending the night camped in the woods that boarded the kingdoms. Then I would ride to meet the princess who was destined to be mine, even though my heart forbade it through my feelings for Ella. I urged my horse forward, desperate to fling the ideas from my head, determined that this passing fancy should not ruin my chances at the union that would please my country. This was one thing I would have to do by the book, this was one thing I would let myself be forced in to.
We rode on until darkness settled.


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|Publication number
|Publication type
|Application number
|Publication date
|Sep 26, 2006
|Filing date
|Sep 29, 2003
|Priority date
|Sep 29, 2003
|Fee status
|Publication number
|Michael A. Baxter
|Original Assignee
|Xilinx, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Non-Patent Citations (3), Referenced by (13), Classifications (19), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
This application includes a computer program-listing appendix on a single compact disc, the contents of which are incorporated herein by reference in their entirety. The compact disc contains a first 5 KB file entitled "boole32_v.txt", a second 23 KB file entitled "gpr_regfile_v.txt", and a third 37 KB file entitled "slr32_v.txt", all of which were created on Sep. 12, 2003. A portion of the disclosure of this patent document contains material, which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
This invention relates generally to computer architecture, and more particularly to a reduced instruction set computer architecture using a field programmable gate array.
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays.
As chip capacity continues to increase, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized microprocessor. Notably, a FPGA is a programmable logic device (PLD) that has a number of electronic gates approaching that of large ASICs, however a FPGA is significantly more flexible. Notably, FPGAs can be designed using a variety of architectures that can include user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or "plugin card." Advancement of FPGA technology has led to the development of FPGA-based system-on-chips (SoC) including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, an embedded processor SoC would include all required ancillary electronics within the chip. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. A SoC could also include multiple processing modules coupled to each other via a bus or several busses. It should also be understood herein that "FPGA-based embedded processor SoCs" are a specific subset of FPGA-based SoCs that would include their own processors.
In order for device manufacturers to develop FPGA-based SoCs or FPGA-based embedded processor SoCs, it is necessary for them to acquire or develop system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC. More generally, the IP cores can form one or more of the processing modules in an FPGA-based SoCs. The processing modules can either be hardware or software based.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. One of the challenges includes communication among multiple hardware and software processors embedded in a FPGA-based SoC. Typically, such communication occurs over a bus. Unfortunately, the embedded processors in a FPGA-based SoC are treated as a separate computer requiring the use of a C compiler and a runtime stack or a conventional heap data structure. Additionally, existing FPGA-based embedded processor SoCs require several programming languages to specify the entire design system. In particular, a system may require both a high-level software language and a hardware descriptive language (HDL) to define the hardware in the FPGA for the system solution. Furthermore, such existing systems require a Real Time Operation System (RTOS). FPGA based embedded processor SoCs are being introduced into the market, but there are no solutions that allow users to customize the system, the hardware and software processing modules and the associated software, nor are there systems that enable a user to tradeoff a function that is implemented in hardware (FPGA fabric) or software (running on the embedded processor). Nor is there a system that is optimized for a soft-fabric processor (or "soft" processor) to be implemented efficiently in the fabric of a field programmable gate array. It would be desirable to have a reduced instruction set computer (RISC) core that is intended for efficient physical implementation using an FPGA, well-balanced for embedded applications within the FPGA fabric, and able to be synthesized from HDL code with high performance. With this in mind, the RISC core would be ideally implemented with efficient resource utilization, small footprint utilization within the FPGA, high performance, as well as capable of supporting the unique problems of realtime software.
A reduced instruction set computer implemented on a FPGA in accordance with the present invention includes the attributes of having a highly efficient FPGA resource utilization and a datapath having a unique Boolean unit and an efficient parallel shifter as well as an immediate instruction designed for the architecture of the present invention.
In a first aspect of the present invention, a reduced instruction set computer architecture implemented on a field programmable gate array comprises a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter, and an immediate instruction function that, via modes, variously manipulates the distribution of a set of literal bits of a half-word literal field from an instruction word across a full-length data word. Also, the Reed-Muller Boolean unit can perform any Boolean operation and an inverse of the Boolean operation on bit-parallel data words by changing only a single control bit value.
In a second aspect of the present invention, a system-on-chip comprises a reduced instruction set computer processor capable of implementation on a field programmable gate array fabric and a simple and balanced instruction set utilizing a minimal amount of resources from the field programmable gate array fabric, wherein the processor is synthesizable from hardware description language.
In a third aspect of the present invention, a method of forming a reduced instruction set computer processor can comprise the steps of embedding a processor core in look up tables of a field programmable gate array and deploying a simple instruction set optimized for a compiler, where the processor is directly synthesizable from a hardware description language.
In yet another aspect of the invention, a system-on-chip can include a reduced instruction set computer processor implemented on a field programmable gate array fabric, a simple and balanced instruction set utilizing a minimal amount of resources from the field programmable gate array fabric and a horizontally scalable immediate instruction using multiple vectorized versions of an N-bit architecture.
A software RISC processor in accordance with the present invention is an extremely fast, architecturally-balanced, compiler-friendly RISC soft-processor that can be implemented in less than 1200 look-up tables in a FPGA fabric. In one embodiment using Virtex-E technology available from Xilinx, Inc., it is estimated to operate at 180–200 MHz and offer at least 50 MIPs in performance. In one aspect of the invention, the architecture, using a 32-bit RISC processor as a base, is designed for upwardly compatible expansion with new instruction capabilities, such as for DSP or network processing, as well as a 64-bit or higher version. The architecture preferably uses a simple instruction set that is further synthesizable from HDL code, such as Verilog code, for minimal FPGA resources and optimal C compiler development effort. The architecture further preferably includes balanced instructions and addressing modes well-suited for embedded applications. For example, bitfield layouts of machine words are made for compatibility with on-chip FPGA IP cores and a standard well-specified bus, the On-Chip Peripheral Bus (OPB), is used. SoftRISC, as the invention is termed herein, is an entire enabling technology for several processors, all extremely fast.
Field programmable gate arrays (FPGA) have become very popular for a variety of other end user applications including telecommunication, Internet, switching, and routing applications. An FPGA includes programmable logic fabric (including programmable logic gates and programmable interconnects) and programmable input/output blocks. The programmable input/output blocks are fabricated on a substrate supporting the FPGA and are coupled to the pins of the integrated circuit, allowing users to access the programmable logic fabric. The programmable logic fabric may be programmed to perform a wide variety of functions corresponding to particular end user applications and may be implemented in a variety of ways.
In an embodiment of the SoftRISC processor, 5 major instruction formats are used, with one additional format available for the reserve for future use (rfu) instruction. In all instruction formats, except for the X-Form, bits 0–7 consist of a 5-bit F-field, which is a prefix opcode, and a 3-bit H-field, which is a C/C++ compiler hinting resource. The compiler hinting bits in the H-field are optionally used, and have the effect of optimizing instruction fetch operations when used. Each of the instruction formats can have a delineation as to how the 32 bits of the instruction are to be used. Note that data bit-orderings of the instructions, as shown in
As shown in
As shown in
As shown in
The C-Form bitfields can be delineated with bits 0–4 containing the F-field, or opcode, and bits 5–7 having the H-field compiler hinting bits. Bits 8–11 are the CM-field, which specifies 16 combinations for how the I16 literal data in bits 16–31 should be used to generate a bit mask, and what arithmetic or logical operation is performed with the bit mask and the selected GPR. Bits 12–15 are a T-field, which selects one of the GPRs. This GPR provides the source data and receives results of modification of the source data with the bit mask data. This process is controlled by the CM-field mode.
As shown in
As shown in
As shown in
The code necessary for implementing the design of an FPGA-based SoC can be in a format such as a hardware description language (HDL). Note that in traditional SoC designs, the hardware is represented in HDL and the software portion in C. A HDL is a language used to describe the functions of an electronic circuit for documentation, simulation and/or logic or circuit synthesis. Verilog and VHSIC Hardware Description Language (VHDL) are standardized HDLs that are well known by those skilled in the art. Verilog and VHDL can be used to design electronic systems at the component, board and system level. They can facilitate the development of models at a high level of abstraction. Other HDLs and similar constructs now known or to be discovered can also be used to represent the system model. When an FPGA based SoC includes an embedded processor, such systems require the use of both high-level (or manually produced assembly) language and a HDL to define the hardware in the FPGA. The present invention has an advantage of obviating the need to compile conventional programming languages (such as C) into HDL or lower level logic.
An exemplary SoftRISC design in accordance with the invention requires between 980 and 1200 look-up tables (LUTs). This well-designed logic was developed using computer-generated design techniques, where any amount of Verilog code can be created quickly, compared to code generated manually. This allows the sidestepping of naive behavioral synthesis, substituting instead informed judgment for highly detailed structural Verilog that implements very efficiently in Xilinx's Virtex FPGAs. This solution can result in an extremely fast datapath logic for FPGAs. The architecture and the implementation are inherently intended to scale horizontally, such as to support strongly DSP-enabled and packet-processing variations. The implementation can also scale vertically, where the entire architecture could efficiently scale up to 64-bits and beyond, with simple O(n) complexity.
Aspects of a SoftRISC processor in accordance with the present invention include: an architecture that is balanced; an instruction set that is small yet complete and compiler friendly, requiring fewer emitted instructions for common operations in C/C++; a parallel shifter design affording reversible shifts and bit-reversal in a small number of slices of FPGA fabric; an immediate instruction having 16-bit literals to be used as 32-bit constants in entirely new ways compared to prior art computer design; a novel Reed-Muller Boolean unit, which eliminates the output multiplexer used in the canonical normal form of Boolean logic units that perform all 16 dyadic operations; clock speeds rivaling a PowerPC core when the SoftRISC processor is implemented, for example, in a Xilinx Virtex-II FPGA, which would further make hard/soft processor interconnect significantly easier for FPGA users and reduce the overall complexity of clock logic; an extremely efficient structural layer for FPGA devices due to the vast majority of the Verilog HDL being computer-generated; inherently expandable via X-code reserved-for-future-use instructions; upward scalability up to 64-bits or more (even up to 1024-bits) while impacting implementation complexity virtually linearly, thereby enabling implementation of a fast 64-bit soft-processor in about 2200 slices or less; and downward scalability down to 16- and 8-bits with virtually linear implementation complexity. The parallel shifter may contain integral bit-reversal hardware, facilitating, for example, FFT addressing for both decimation-in-time (DIT) and decimation-in-frequency (DIF) algorithms. The immediate instruction can be reused for processors from 8-bits to 64-bits and beyond in size, as well as deployed in state-machine designs.
It should be understood that embodiments in accordance with the present invention can be both horizontally (number of bits in a machine word) and vertically (number of architectural variants) scalable. In a system-on-chip (SoC), for example, having a software reduced instruction set computer (RISC) processor synthesizable from HDL, implemented on a field programmable gate array fabric and having a simple and balanced instruction set, an immediate instruction can be horizontally scalable using multiple vectorized versions of an N-bit architecture. The N-bit can be multiple 16-bit, 32-bit, 64 bit, 128-bit, 256-bit, 512-bit or 1024-bit vectorized versions of the architecture. For example, versions larger than 64-bits can be viewed as vectorized versions of the architecture, where 2 or more concurrent 64-bit words in the same computer can be supported. This capability can be in the realm of Xilinx DSP FPGA applications, where 2–4–8–16 words may be used concurrently for a digital filtering operation. Additionally, a 1024-bit variant may be used in a large-scale datacom switching application. Such a variant might be described as supporting multiple concurrent integer words of some smaller size, such as 16-bits. Again, the immediate instruction and the base architecture can scale to support such variants. This architecture can be thought of as a "hypervector," which contrasts with existing "hyperscalar" architectures.
With respect to the concept of a simple and balanced instruction set, embodiments in accordance with the present invention can use single and paired instructions that affect 3 system characteristics simultaneously: 1. hardware runtime efficiency (providing efficient FPGA realization); 2. software runtime efficiency (providing a small set of instructions to achieve a goal of operating C programs efficiently at runtime); and 3. compiler implementation efficiency (compiler simplicity as a result of depending on 1 and 2 above). Thus, with respect to the reduced complexity of the compiler, the instruction formats include a balance of single and paired instructions well-suited for compilation, such that after a first-issued instruction is considered by a compiler for issue, the compiler beneficially considers no more than 30 alternative instructions for a second-issued instruction to pair with the first-issued instruction. With respect to the reduced complexity of the instruction sequences required at runtime, instruction formats can include a balance of single and paired instructions well-suited for a C runtime software environment, such that instruction sequences required to implement C language constructs naturally break into sequences comprising at least one among one instruction and two instruction sequences. The single or paired instruction overhead can minimize interrupt latency and the minimal instruction overhead and the single and paired instructions facilitate interrupt driver software design directly in the C language.
In another embodiment, the immediate instruction can be for an 18-bit or 36-bit microcontroller version in an FPGA fabric that can use the respective 18-bit aspect ratio or 36-bit aspect ratios of a Xilinx Virtex-II, Virtex-II Pro, or Spartan 3 FPGA BlockRAM. For that matter, conceivable embodiments can include N-bit architectures having multiple 18-bit, 36-bit, 72 bit, 144-bit, 288-bit, 576-bit and 1152-bit vectorized versions.
The immediate instruction can also be used for a digital signal processor (DSP) version in relation to generating immediate data for an 18-bit embedded multiplier in a FPGA device. In one embodiment, the DSP can generate two N-bit words of constant data using an N/2-bit immediate instruction having N/4 bits dedicated for immediate data. The two N-bit words can comprise constants for a Fast Fourier Transform or in-phase and quadrature data (I & Q) for complex signal processing in algorithms for radio or data communications signal processing.
As previously mentioned, embodiments in accordance with the invention can also be vertically scalable. To enable such vertical scalability, an instruction set can include an rfu instruction (the X-Mode instruction) that enables vertically scalable architectural variants implemented on the field programmable gate array fabric irrespective of horizontal scalability. The rfu instruction can enable upward compatible single and double-precision floating-point arithmetic operations via the field programmable gate array fabric and can also use a single standard extension at a hardware/software boundary for variant architectures while minimally impacting a compiler design for the variant.
For example, DSP or multimedia instructions are supported by the rfu instruction for such architectural variants. Or, alternatively, in a 16-bit microcontroller form, the rfu instructions may support access for specialized peripheral registers as implemented in that form of architectural variant. In all these cases, the core compiler algorithms (for implementing a C++ compiler, for example) would be greatly overlapping, thereby reducing the effort required to support numerous similar-but-different architectural variants.
The SoftRISC processor in one embodiment is a 32-bit RISC architecture intended for efficient physical implementation as a soft processor core in Xilinx Virtex-E FPGAs. In this section, the general organization of the processor is summarized as an introduction to the facilities of the architecture. It should be understood that the present invention as claimed is not limited to the exemplary implementation described below, but can apply to other FPGA embedded processor architectures which can vary significantly from the exemplary implementation.
The implementation of a soft processor core having a very small footprint, for example a soft processor core comprising less than 1200 LUTs, is a significant challenge and goal. Further practical implementation issues have also brought to light additional concepts such as those relating to instruction buffering, minimal instruction, pipelining, uniform instruction size, branch address lengths, immediate instruction capability, software management of exceptions, alternative logics and datapath design.
With respect to instruction buffering, a key issue in RISC computers is attaining a high instruction throughput rate, such as the goal in this design of 1 clock cycle per instruction (CPI). Rather than use multiple sets of memory I/O buses typical to the Harvard computer architecture, this design used a much simpler traditional Von Neumann architecture. The key is to exploit a simple shift-register as a pipelined instruction buffer, and to perform instruction fetch with burst fetch operations. This logic achieves close to 1 CPI for most non-pathological code sequences, and does not require or even benefit from a cache. To support this simple implementation hardware, the architecture includes an advanced instruction look-ahead bitfield encoding capability, which are the H-field compiler hinting bits (available with all instructions except the rfu instruction). This concept is adapted from some aspects of multithreading architecture (MTA) in that the instruction-issue logic may re-order and concurrently schedule instructions that have non-conflicting hints (as encoded in their respective H-fields). The present invention, however, does not require the aspect of MTAs involving multiple program counters.
The main idea of minimalism in this embodiment is to support only the instructions that a C compiler needs, while reducing the total opcode space to a small size (only 31 of 32 opcodes were used). Then, for some instructions that need to have additional dependent functionality, instruction modes are provided to these instructions to expand their capability. The overall effect of the SoftRISC machine instruction set on the control logic implementation is very efficient instruction decoding, and shallow pathways into a relatively small set of programmable logic arrays (PLAs) driven by sequential logic that follows along with pipeline processing.
With respect to pipelining issues in this Load/Store pipelined machine, datapath logic that is pipelined is more individuated, rather than grouped. For instance, the concept of a single ALU is not as efficient as separate logic for addition and shifting. So, one goal of the implementation is seeking an optimal mix of separate datapath elements that are individually pipelined, rather than forcing a procrustean aggregation of logic having conventional boundaries. This is facilitated in flexible implementation technologies such as FPGAs, for example the Xilinx Virtex FPGA, and not a custom silicon design. Thus, it is more desirable to formulate computer logic based on what the FPGA "wants", rather than any preconceived or conventional notion of the designer's wants.
Having essentially only one instruction size, and having that size be the normal 32-bit machine wordlength (for this exemplary 32-bit design) simplifies the design. There are many fewer cases to manage for pipelining, and much simpler instruction addressing logic results.
A large branch address length is necessary to avoid procrustean limitations in the compiler and linker. This advantageously has no additional cost in the implementation, since 32-bit addressing is already part of the design. All instruction addressing can be left-shifted two places in order to point to an actual word address for an instruction. This results in no wasted bits.
In one aspect of the present invention, the branch offset may be preplaced within the instruction already shifted in-place. The 2-bit branch mode indicator fills the bottom 2 bits of the instruction, allowing routing of the branch offset within address processing logic with no shifting. This is shown in
The literal mode or immediate instruction provides a mechanism for compilers to implement many essential parts of programs. Compilers for modern processors tend to generate a lot of code that works with tiny units of data, such as small constants, or increments used for loop accounting and indexing. Thus, it is important to have an immediate instruction capability that is sufficiently capable and that is mindful of FPGA implementation issues. For example, a C++ compiler may use this mode to produce very fast inlined arithmetic code in numerous cases, in contrast to other computer architectures. For general processing, this facility also gives the compiler very flexible capabilities for generating fast code containing, for instance, ordinals (e.g., unsigned numbers used for addressing), integer constants, offsets, array indexing, bounds checking, and some floating-point constants. This very flexible immediate instruction capability can also speed the inner loops for common situations encountered by a compiler with general code, irrespective of the benefits to arithmetic or library code. The immediate instruction, as implemented and described herein, provides immediate data in an instruction without requiring either additional instruction words or instructions in non-integral machine word sizes. The immediate instruction may be used in alternative soft-fabric FPGA computers, and other embedded processor cores and microprocessor designs.
Software management of exceptions works well in a SoftRISC implementation. Exceptions are either synchronous or asynchronous in SoftRISC. For the asynchronous exception, only a single interrupt pin is provided, with the expectation that software may be used to manage substantially all interrupt processing in the embedded application. This has the impact of greatly simplifying the control path logic over a multi-level priority scheme. Additionally, the computer architecture literature supports a software-based schema; hardware schemes only complicate software interrupt dispatch. Accordingly, this works well for reducing FPGA LUT utilization.
With respect to alternative logics, it is desirable to use a Boolean unit for multiple functions, such as for bit generation and multiplexing. A highly efficient implementation uses Reed-Muller logics. The Reed-Muller logic results in a solution requiring only 2 LUTS per bit processed. This is more efficient than a Boolean unit constructed with a conventional Disjunctive Canonical Form (DCF) expression, because only a final OR (not a multiplexer) is necessary to join the output of two 4-LUTs. There may be additional beneficial uses of Reed-Muller logic schemas, such as for accelerating arithmetic and other operations.
A block diagram of a SoftRISC implementation 20 in accordance with the present invention is shown in
The GPR datapath unit 26 will now be discussed in further detail, particularly with respect to the implementation of the Boolean Unit. The subject of Reed-Muller logics is beyond the scope of this application and is well known to those of ordinary skill in the art. An efficient implementation of a complete binary function unit 40 is shown in
Included within the GPR datapath unit 26 is a parallel shifter 60 as shown in
When synthesized from structural Verilog, the complete parallel shifter only requires 224 LUTs in Virtex-E. This is more optimum than synthesis using behavioral Verilog, which results in a utilization of 340 LUTs. In addition, in an example using a Virtex-E-8 FPGA, the logic in pure combinatorial form has a propagation delay of approximately 18 nS when tied to external IOB pads. This allows single-cycle operation at faster than 50 MHz rates. Pipelining may be done at relatively arbitrary places, such as in halfs, (approximately) thirds, or fourths of the ranked logic. The resultant clock speed may be well over 100 MHz, making this section of the datapath not a critical path. The decision of where to pipeline may be based on other factors, such as the design of the multiplier or how the adder/subtractor is pipelined. The SoftRISC datapath logic is essentially suitable for superscalar use, aside from an extreme minimum in LUT count for this particular embodiment of the core.
The control signals in
Rank 1 selects between 2 input groups, whereas ranks 2–4 select among 4 input groups. At the cell level, the rank 1 input groups are nomenclatured P and Q. The rank 2–4 cells have their input groups nomenclatured P, Q, R & S. The control signals effecting these selections are SD and rank-specific subset of M[0:4]. This division is shown in
With respect to DSP capabilities, the parallel shifter logic may be optimized to split the shift direction control signal into two lines, one at rank 1 of the logic, and the other at rank 4 (note that
An exemplary SoftRISC processor in accordance with the present invention can have the following general resource characteristics:
32-bit datapath, registers, and instructions
16 General Purpose Registers (GPRs)
7 Special Purpose Registers (SPRs)
Simple, balanced instruction set
6 instruction forms
32-bit address space, byte-addressed
Byte, half-word, and word addressing
Big endian byte ordering (although, other embodiments can use little endian byte ordering)
Bit and Byte Ordering
With respect to data, a SoftRISC processor can be considered to have a big endian architecture. The order of bits and bytes within a 32-bit word can follow that of the On-Chip Peripheral Bus (OPB) specification, which is the processor bus interface used within many Xilinx FPGAs, or can follow that of any other bus architecture.
The way that individual bytes can be addressed within a 32-bit word is shown in
Addresses are essentially unsigned 32-bit integers, and have resolution for bytes, half-words (16 bits) and words. The SoftRISC processor can be a load-store computer capable of addressing memory in at least the three aforementioned resolutions of data size. When addressing bytes, as depicted in
Addressing for half-words can select either the right or left half of a 32-bit word. As shown in
Similarly, when addressing words, only the most significant 30 bits are used, with the 2 least significant bits ignored. Because instructions in SoftRISC are always 32-bits in length and aligned to word boundaries, instructions also use only the most significant 30 bits of an address. Exemplary word addressing is illustrated in
The SoftRISC architecture preferably uses a register model having for example 7 Special-Purpose Registers (SPRs) and 16 General-Purpose Registers (GPRs). This number of GPRs was chosen for efficient implementation in certain FPGAs, but is not necessarily limited thereto. In one embodiment, all registers are 32-bits in size. The appendix includes file gpr_regfile_v.txt, which has an example of a GPR register file in accordance with the present invention.
Special-Purpose Registers can include a Program Counter, a Processor Status Register, a Debug Instruction Register, and a Debug Data Register. The Program Counter, or pc, can be a 32-bit register that holds the address of the next instruction to be fetched from memory. By design, the instructions of the SoftRISC processor are all the same size, namely 32-bits in size for this embodiment. As a result, instruction addressing to memory is always aligned to a 32-bit word boundary. Hence, only the 30 most significant bits (MSBs), or bits 0–29, of the pc participate in instruction addressing. In instruction addressing, the two least significant bits are considered to be zeros, regardless of the actual value stored in the pc. The pc is illustrated in
The Processor Status Register, or psr can be a 32-bit register used in implementations to provide arithmetic and logical status flags, and to provide bitfields for capability assertion for control and management of interruption, timers, traps, caches, and buses. In the SoftRISC architecture, only some of the psr bitfields are defined architecturally. Referring to
psr (0)
negative flag
psr (1)
overflow flag
psr (2)
carry flag
psr (3)
zero flag
These flags are the machine status flags. Bit 18 (TE) is the trap enable indicator, which enables the trap instruction when asserted. Bit 19 is the interrupt enable indicator, which enables external interrupts from within the FPGA when asserted. Bits 20–31 contain the IV12 interrupt vector. Bits 4–17 are dependent on the particular implementation of the SoftRISC as a soft core.
The Debug Instruction Register or dir can be used to insert a single instruction from an external JTAG controller for diagnostic and debugging use. The dir, shown in
The Debug Address Register or dar is used to address data for memory access using an external JTAG controller. The capability is designed to be coordinated with the ddr and the dir using the GDB debugger. The dar, shown in
Two additional SPRs in the SoftRISC architecture are the Context Registers 0 and 1, or CR0 and CR1. These registers are used for storage of the processor state, such as PC return address and the PSR context data, during traps and interrupts, and are illustrated in
The SoftRISC instructions are introduced in mnemonic form as follows: and or xor add sub sh rot mul br bnz bz bnc bc bnv by bnn bn blt bgt imm and_spr or_spr rts rft jrr jsr trap gdb_rd gdb_wr ld st rfu
The following is a summary of the Opcodes and Forms:
The arithmetic and logical instructions, which use the A-Form instruction, are: and, or, xor, add, sub, sh, rot, and mul. The A-Form instructions (
The and instruction performs a bitwise and of GPRs R and S. The or instruction performs a bitwise or of GPRs R and S. The xor instruction performs a bitwise xor of GPRs R and S. The add instruction performs a two's complement addition of GPRs R and S. The sub instruction performs a two's complement subtraction of GPRs R and S.
The sh instruction performs a left or right shift operation on GPR R, shifting a number of bits specified by GPR S[27:31]. Note that effect of the instruction may be modified through the use of the left-or-right and zero-or-sign fill bits of the AM-field. The rot instruction performs a left or right (based on the value of the left-or-right AM-field bit) circular rotate operation on GPR R, rotating a number of bits specified by GPR S[27:31]. The mul instruction performs an unsigned multiplication operation on the lower half-words of GPRs R and S (e.g., R[16:31] and S[16:31]) to produce an unsigned 32-bit result in GPR T.
The branch instructions, which use the B-form instruction (
The br instruction is an unconditional branch. The bnz instruction is a conditional branch not zero that branches if the psr zero flag (psr(3)) is not asserted. The bz instruction is a conditional branch zero that branches if the psr zero flag is asserted. The bnc instruction is a conditional branch not carry that branches if the psr carry flag (psr(2)) is not asserted. The bc instruction is a conditional branch carry that branches if the psr carry flag is asserted.
The bnv instruction is a conditional branch not overflow that branches if the psr overflow flag (psr(1)) is not asserted. The by instruction is a conditional branch overflow that branches if the psr overflow flag is asserted. The bnn instruction is a conditional branch not negative that branches if the psr negative flag (psr(0)) is not asserted. The bn instruction is a conditional branch negative that branches if the psr negative flag is asserted.
The blt instruction is a conditional branch less than that branches if (N xor V) is true, where N is the psr negative flag (psr(0)) and V is the psr overflow flag (psr(1)). The bgt instruction is a conditional branch greater than that branches if (Z and not(N xor V)) is true, where Z is the psr zero flag (psr(3)), N is the psr negative flag, and V is the psr overflow flag.
The next group of instructions provides capabilities for managing exceptions, modifying program flow (non-branching), and reading/writing diagnostic data. These instructions use the D-Form instruction (
The and_spr and or_spr instructions allow for indirect bitwise control over SPRs. The and_spr instruction performs a bitwise and between a general purpose register (GPR) and a special purpose register (SPR), and allows for bit-clearing specified fields of the SPR. The or_spr instruction performs a bitwise or between a GPR and a SPR, and allows for bit-setting specified fields of the SPR. For both instructions, the S-field specifies the source GPR, and the P-field specifies the target SPR.
The jsr and rts instructions provide subroutine and return capabilities. Specifically, the jsr instruction performs a jump subroutine operation that stores a return address (e.g., address of the instruction following the jsr instruction) in the memory word addressed by GPR T, and then uses the address stored in GPR S to set the value of the program counter (pc). After executing the subroutine, the rts instruction can be used to perform a return from subroutine operation that retrieves the previously stored return address from the memory word addressed by register T and sets the pc to that stored value. The jrr instruction performs an unconditional jump register relative. The signed value stored in GPR S is added to the current pc value to generate the new pc value. This operation is similar to an unconditional relative branch instruction except that a much larger addressing range is possible since the full 32-bit signed value of the S register is available.
The trap and rft instructions are used to provide running programs with a synchronous interrupt capability. The trap instruction performs an unconditional trap that first saves the current context of the processor, and then starts execution at an address specified by the trap vector TV12 (embedded within the trap instruction). The context may be saved in the context registers CR0 and CR1, where the return address (e.g., the instruction following the trap instruction) is stored in CR0 and the current state of the psr (processor status register) is stored in CR1. Similarly to branch instructions, the value of TV12 may be left shifted by two places (since addresses are word-aligned) and zero-filled to form an address used to set the pc. The rft instruction performs a return from trap after processing a synchronous interrupt. The rft instruction may cause the psr to be loaded with the data stored in CR1 and the pc to be updated with the data stored in CR0.
The debug_rd and debug_wr instructions may be used with a debugger to provide access to diagnostic data. The debugger may be running on an external system and coupled to the SoftRISC processor through a JTAG or other hardware interface. The debug_rd instruction allows the value of any GPR register S to be stored in any writeable SPR, which is specified by the P-field. Similarly, the debug_wr instruction allows any SPR, specified by the P-field, to be written to a GPR S.
The ld and st instructions provide memory reference capabilities and use the M-form instruction (
The ld instruction moves data from memory to the processor using the transfer mode specified by the TM-field. The st instruction moves data to memory from the processor using the specified transfer mode. In a preferred embodiment, if the S and R are the same GPR register, the memory address for either the load or the store operation may be obtained by adding the value of GPR S to the SI8 data embedded in the instruction. If S and R refer to different GPR registers, the memory address may be obtained by adding the values of GPR S and R together and adding the SI8 data.
Finally, operation of the imm instruction is explained in greater detail below and operation of the rfu instruction is explained in greater detail above.
The immediate instruction (imm) solves two particular problems that merged at the hardware/software boundary in the design of the SoftRISC processor. First, a need was recognized to have a powerful immediate capability in the computer architecture in order to facilitate bitfield masking, loading of immediate values, and arithmetic with small constants. A particularly difficult constraint is that a simple system for having an impact on 32-bit registers has to be accomplished with a 32-bit instruction that cannot have all of its bits dedicated to a literal field. Immediate operations are used quite often by compilers for indexing and loop iteration. Secondly, it is desirable for the implementation of immediate capability to be efficient for FPGA realization. Therefore, elements necessary for software could not end up being very expensive in FPGA hardware resource utilization.
An effective solution that resolves both problems is using a half-word literal field in the instruction word (refer to
In one embodiment, the imm, or immediate instruction, has 4 arithmetic-logical operating modes and 6 different bit mask generation modes. Taken together, these sets of 4 modes and 6 modes form a matrix of composite instructions imm that are encoded by the CM-field of this sole C-Form instruction.
The 4 arithmetic-logical operating modes supported are: AND, OR, XOR, and ADD. These operations differ from A-Form instructions in that three-address register selection is not done. Instead only one GPR register is selected by the T-field of the instruction to be a source and destination register.
The arithmetic-logical operating modes are typically used as follows. The AND mode is used for zeroing unwanted literal bits, or for masking of an operand (such as prior to shifting). The OR mode is used for inserted desired literal bits into the selected GPR. When complementing select bits of an operand in the GPR is necessary, the XOR mode is used. For doing immediate arithmetic operations, such as for loop and iteration counting, the ADD mode is used.
The 4 main bit mask generation modes are named LOW, HIGH, DPLX, and SIGN, with 2 additional modes FILL LOW and FILL HIGH. Each of these modes causes a certain action to take place with the I16 immediate data embedded in the instruction. These modes, and some of their uses will be further detailed below.
In the case of the LOW bit mask generation mode, the I16 immediate data bits are processed as shown in
The HIGH bit mask generation mode works similarly to the LOW mode for the upper 16 bits of the word. The I16 immediate data bits are processed as shown in
For creating nybble, byte, and half-word mask values flexibly and quickly, the DPLX bit mask generation mode is used. Each bit of the I16 immediate data is duplexed into 2 adjacent bits in a 32-bit bit mask. Through the simple technique of bit-duplication, the generation of either left- or right-aligned masks is possible. The I16 immediate data bits are processed as shown in
In the case of the sign bit mask generation mode, the I16 immediate data bits are processed as shown in
The table in
The variable combinations possible with the constant modes of the immediate instruction, especially when combined with another instruction (including possibly another immediate mode instruction), afford powerful capabilities, for example for the C compiler to emit indexing or loop accounting code, as well as for operand masking and shifting. The composite immediate instructions are relatively simple, and are included in the SoftRISC architecture because of their efficient FPGA realization.
In light of the foregoing description of the invention, it should be recognized that the present invention can be realized in hardware, software, or a combination of hardware and software. A method and system for dynamic reconfigurable computing of a system having at least one microprocessor implemented on a field programmable gate array according to the present invention can be realized in a centralized fashion in one computer system, or in a distributed fashion where different elements are spread across several interconnected processing modules. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the invention described herein.
The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which, when loaded in a computer system, is able to carry out these methods. Computer program or application in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduction in a different material form.
Additionally, the description above is intended by way of example only and is not intended to limit the present invention in any way, except as set forth in the following claims.
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Owner name: XILINX, INC., CALIFORNIA
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text:
For Cardozo Students, a Broad Menu of Lunchtime Possibilities
For high school students, lunch period has been one of the most expendable on their schedules, with many skipping lunch to cram in more classes or leave for work. How students and schools handle the lunch issue varies, according to a recent article in The Verdict, the student newspaper at Benjamin N. Cardozo High School, in Bayside, Queens. The article, below, has been lightly edited.
By Rafina Rahman
10th Grade
The Verdict
Benjamin N. Cardozo High School
The average high school student spends six to seven hours a day in school. However, some of those students have no scheduled lunch period, leaving them famished throughout the day.
In elementary and middle school, lunch is guaranteed and programmed into every student's schedule. However, in high school, because of scheduling conflicts, lunch is not an option for every student.
Lunch is served from period three until period eight. "We serve 200-300 students per period," said Susan Marroquin, the cafeteria manager. While most students look forward to their lunch period, others have different opinions.
"The lunchroom is mad crowded and it's such a hassle getting through the doors," said Safa Sarker, a sophomore.
"I like having lunch because the school lunch is good," said Zaid Ahmed, also a sophomore.
Students are only permitted to eat in the cafeteria if their program shows that they have lunch during a particular period, and they are not allowed to leave the cafeteria with lunch trays unless they are service monitors that period.
Most freshmen have a scheduled lunch period. It is in the upper grades that a lunch period is sometimes eliminated. However, "Getting complaints from parents about their child not having a lunch period is very seldom. We can change their program and add a lunch, if requested," said Sarah Lui, guidance counselor.
According to Barbara Nunziata, the parent coordinator, a student can bring lunch from home and eat it during a class depending on the teacher's rules.
"I allow students to eat lunch in class because they are old enough to clean up after themselves," said Phil Ackerman, a social studies teacher.
On the other hand, not all teachers are lenient about allowing lunch to be eaten during class.
English teacher Binnie Sommer said, "Students are not allowed to eat food in the class because we have mice and roaches in the building. I once had a mouse running around during a class and it was very chaotic."
Some students, mostly seniors, don't have a lunch period because they have a short school day regardless, and adding lunch would give them a longer schedule.
"Not having a lunch period allows you to get out earlier, and if you have hardcore classes you can get what you want done faster," said Deval Mehta, a senior.
Other seniors who have jobs after school prefer getting home early. "If I had lunch in school, I would cry," said Max Resetar, a senior. He gets home at 12:30 p.m. and prefers "having my own lunch at home before I have to go to work or do homework."
Lacking lunch concerns newcomers and their parents.
Sophomore Antonella Castellano provides another student's perspective, "The disadvantage of not having a lunch period is that you have to eat in class and people give you weird stares."
"Lunch is an essential part of every child's diet because it helps keep the student energized throughout the day," said Shermin Ahmed, the mother of Safa Sarker.
While some students have no lunch periods, others have more than one.
"It's really annoying that I have double lunch because I just sit in the dirty lunchroom for two periods straight with nothing to do. I can't even finish my homework since my lunch falls at the end of the day," an anonymous sophomore says.
In high school, students with a lunch period should take advantage of the opportunity. Changing the amount of food you intake throughout the day or skipping meals can affect a student's overall health. It can cause harmful metabolic changes in the body.
Eating lunch can make a student more active and focused throughout the day. With approximately 4,000 students, there isn't a perfect recipe for lunch, but we can at least start with providing a more flexible and practical alternative.


text:
UUCA provides reliable childcare in a safe and nurturing environment, allowing families to fully participate in the activities of the congregation. Childcare is staffed by both paid and volunteer childcare providers. All children must be signed in to childcare and picked up by a parent or designated responsible adult. Registration is required for regular participation.
- No reservations are required for Sunday morning childcare (September to May from 9 am to 1 pm; Memorial Day through Labor Day weekend from 9:30 am to 11:30 am).
- Reservations are required at all other times, including Sunday afternoons and Wednesday evenings. Contact the Childcare Coordinator at email@example.com with questions.
- Parents are also invited to use the "Quiet Room" at the top of the stairs in the lobby or via lift to the upper level of the Sanctuary on Sunday morning.
Event planners please note that event reservations are due a minimum of 14 days out from your event. Of course extra notice time is always helpful.


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He suddenly felt his woolly hat loosening and he began to fall to the ground. Could it be that his hat was sacrificing itself for him?
He landed on the ground again. BUMP! He looked up and saw the hat flying in the other direction. It landed in the duckpond. Oh no... he'd liked that hat, and it was the only thing keeping his head warm.
He had heard somehere that most of the body's heat is lost through the head. He couldn't remember where he'd heard that. Maybe it was in one of the programmes that Katy's mother watched all day. Anyhow, he wasn't sure if it was true, and if it was, did it even apply to teddy bears, or indeed, soft toys in general?
He watched as two booted feet approached him again. He was going to be picked up and shaken again, probably even more violently this time. He was sure of it.
He was wrong. This time the insult was a kick, which lifted him into the air and sent him flying in the same direction as the woolly hat. On the upward trajectory, he sees the grinning, acne-ridden face of his assaulter...


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|"Amar Kamat (JIRA)" <j...@apache.org>
|[jira] Commented: (HADOOP-4189) HADOOP-3245 is incomplete
|Fri, 19 Sep 2008 09:12:44 GMT
[ https://issues.apache.org/jira/browse/HADOOP-4189?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel&focusedCommentId=12632591#action_12632591 ] Amar Kamat commented on HADOOP-4189: ------------------------------------ Arun, I was not sure as to what the optimal values are. If we use default values from FileSystem then the amount of data recovered is very low. For long running jobs with less maps, these values should be low so that every update gets logged while for long running jobs with large maps, it is ok to use system defaults as the frequency of updates are high. So instead of using some heuristics and making it hardcoded, I thought its better to keep it (admin)configurable and then come up with some better heuristics or technique to set the defaults. Any thought on what the default values should be considering various types of jobs that can be run? > HADOOP-3245 is incomplete > ------------------------- > > Key: HADOOP-4189 > URL: https://issues.apache.org/jira/browse/HADOOP-4189 > Project: Hadoop Core > Issue Type: Bug > Components: mapred > Affects Versions: 0.19.0 > Reporter: Amar Kamat > Assignee: Amar Kamat > Priority: Blocker > Fix For: 0.19.0 > > Attachments: HADOOP-4189-v1.patch, HADOOP-4189-v2.patch, HADOOP-4189-v3.1.patch, HADOOP-4189-v3.patch, HADOOP-4189.patch > > > There are 2 issues with HADOOP-3245 > - The default block size for the history files in hadoop-default.conf is set to 0. This file will be empty throughout. It should be made null. > - Same goes for the buffer size. > - InterTrackerProtocol version needs to be bumped. -- This message is automatically generated by JIRA. - You can reply to this email to add a comment to the issue online.
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