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Good Way to send USB to HDMI wirelessly
Wireless USB never really took off, despite a lot of effort being put into making seemingly pointless products, but now accessory company Good Way Technology has come up with a potentially cunning use for it.
The company has created what it calls a Wireless USB HDMI Dock, which we found skulking at the back of a Taiwanese trade fair. It's a two-part solution, a dongle that you install in your notebook or PC and a small unit that you connect to your TV via an HDMI cable.
This setup then turns your TV into a wirelessly connected display for your computer. Pretty clever, especially as it allows you to stream 720p video content to your TV with audio. The caveats being its 10-metre range and that you can only use it with Windows.
In a way, this is similar to Intel's WiDi technology which was announced earlier this year, but it will work with any notebook, rather than the limited option of WiDi-enabled PCs.
You'll have to be eagle-eyed to spot one though, and we advise scouring import websites and accessory suppliers, as Good Way doesn't appear to sell products under its own name.
Let us know if you spot something similar...
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The myriad of functionality that comes with Snare, from Verbose Truncation to Output Driven Filtering have been helping companies around the world zero in on threats in record time while spending less on their SIEM. This is made possible by reducing the noise in your log collection while delivering the critical data for both forensics and analytics, dependably. Snare just works. Try our agents free today!Sponsored Listing
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Bastille Linux
This tool locks down Linux and UNIX systems.40 weekly downloads
chainssh is a shell script to smplify the ssh login via multiple sshgateways/firewallgateaways. e.g. connect from homehost via sshgateway to a clusternode with one command.
There's no event quite like OSCON—the best place on Earth to sharpen your skills and discover new techniques, making you better at what you do and igniting your love of all things digital. You'll find everything open source: languages, communities, best practices, products and services. Join us May 8-11 in Austin, TX, and let OSCON ignite your love of all things digital!Sponsored Listing
The TruongQuangDuocIDS (tqdids) is an IDS that works on multi-platform, from Solaris/SPARC to HP-UX/Alpha. This IDS has features like other IDSs (snort etc.) but it has a special feature inside the binary-pattern-matching algorithm that makes it faster.

subset: commoncrawl


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The wigwam
Explore related topics
The Wigwam Motel, Route 66, Holbrook, Arizona; Wigwam#3 (too cool) // photo and writer Anne McKinnell
Sleep in a wigwam at the Wigwam Village! One of the most unique motels in Cave City, Kentucky. Thanks for sharing, instagrammer @sharelouisville. #travelKY
Wigwam Motel on Old Route 66 in Holbrook, Arizona
jennifer lucey-brzoza
Tepee and wigwam. Made from pipecleaners and felt and paper.
Wigwam Motel Arizona in Holbrook United States of America : Unusual & Unique Hotels of the World
The Tepee vs. the Wigwam and other related Thanksgiving learning activities
Hotel in Holbrook, AZ, USA - off the old Rt 66 - stayed in the first one shown here...that '59 Impala was there as well. The inside of the "wigwam" was so cute! I could have stayed there a few more nights.
Elizabeth Arden Red Door Spa at The Wigwam
The Wigwam Cabins Identity pattern by Oat Studio via Design is Yay!


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About this Deal
Walmart Halloween Sale!
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Owner Financing Homes in Cleveland, MO
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You can Own this 3000sf Executive Home for just $2035 per month. Take over financing, all you need
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Rent To Own in Grandview! This 3 Bedroom / 2 Bath home is located approximately 1 block from John Anderson Park with tennis courts,...
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Zanelle Breedt
Today's Daily Babe is South African model Zanelle Breedt. She's a normal girl who likes challenges in life. She has a good personality, loves nature, the people around her, dancing, partying, KFC and her Blackberry. She has learned to go foward and to work hard for what she wants. She's a down to earth person, who takes things day by day. She was a South Africa Hunnies RWC Mascot and she was in the FHM Models Top 100 for 2012. Zanelle Breedt is definitely worthy of being handed the Daily Babe title on Running Wolf's Rant for the 14th of April 2012.
Yesterday Basia Tyrkalska (from Johannesburg, South Africa) was the Daily Babe on Running Wolf's Rant, feel free to check her out. Watch this space for daily updates in the Babes and Photography category on this blog. Feel free to comment on anything that you find interesting or disgusting here. Feedback is appreciated and welcome.
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Question about Canon - SUPER G3 FAX BOARD-T1 (0450B002AA)
I have a problem with the error fax light not shuuting off. Ever since this has happened I can not use my letter paper tray. It always tells me to check the paper. I am having to load letter paper in the legal tray and fool it. do you have any suggeationjs on how to fix this. I have read and looked all through the manuels and it says nothing. Your help will be greatly appreciated.
Thank you,
Posted by kellicorners on
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a 6ya expert can help you resolve that issue over the phone in a minute or two.
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With its Galileo navigation system, the European Union intends to become independent of America's GPS (Global Positioning System). Now the Mobile and Distributed Systems Group of Ludwig-Maximilians-Universität (LMU), München, is also involved in developing Galileo services.
The Federal Ministry of Education and Research recently approved the two-year project "Indoor", which will run until the end of 2010. In this project, LMU computer scientists working with Professor Claudia Linnhoff-Popien shall be developing positioning and navigation technologies to be used in the field of traffic logistics and for emergency services. What they are focusing on in particular is indoor positioning and navigation.
The project aims at a fundamentally new development: Solutions so far have relied on the terminal device periodically sending position data to a server, even when the user, and therefore the terminal, is not moving at all. The LMU computer scientists, on the other hand, assign boundary circles to the users according to given queries and the movement of the persons or objects being monitored. The terminal only gets in touch with the server if the user moves beyond his circle. This method is more effective and economical, since the position data is only sent to the server when there is movement, and costs are only incurred at that moment.
This technology so far works best with GPS-supported terminals – and it will now be exciting to see how the new challenges of a Galileo module and the addition of indoor positioning will be met. As it is, the crux of the problem with large buildings is the given architecture and furnishing, both of which can lead to all kinds of wild shadowing effects and reflections. The present technology goes back to research done in the Mobile and Distributed Systems Group, which has been being published in prestigious international journals over the past five years, and which has led to numerous dissertations, one habilitation and a number of patent applications.The aim of the "Indoor" project is to improve certain algorithms that will increase the energy and cost efficiency of location-based service applications. Localization algorithms for indoor applications shall be enhanced, existing platforms and concepts technically evaluated, and a user study conducted.
The scientists have daunting challenges ahead as they forge on with the project, since precise localization inside a large building is considerably more difficult to achieve than outdoors. Aside from the technical difficulty of achieving this, there is one nasty problem that stands in their way: the "semantics" of buildings. There is no way of knowing from a public building's floor plan alone, for example, whether a door drawn on the plan is actually accessible to every public person, or whether it is perhaps only accessible to certain staff or to certain groups of people.
Together with a spin-off of the Mobile and Distributed Systems Group, Aloqa GmbH Munich, and a hardware developer for satellite navigation systems, Ifen GmbH Poing, a prototype shall be developed during the project, which shall implement the methods developed at the group as a tangible hardware module. And there is one more partner who will be involved in the testing phase: the Walt Disney Company, Germany. Disney is namely interested in this budding technology because it could be just what they need for their theme parks.
The introduction of Galileo will mark the independence of the European Union from America's GPS (Global Positioning System) and the Russian Federation's global navigation satellite system GLONASS. While Galileo, a joint project of the EU and the ESA (European Space Agency), is compatible with GPS, it guarantees independent and reliable availability in Europe.Contact:
Kathrin Bilgeri | alfa
Further information:
Further reports about: > GPS > Galileo > Indoor project > LMU > Positioning > emergency services > navigation system > satellite navigation systems > traffic logistics
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On January 15, 2009, Chesley B. Sullenberger was celebrated world-wide: after the two engines had failed due to bird strike, he and his flight crew succeeded after a glide flight with an Airbus A320 in ditching on the Hudson River. All 155 people on board were saved.
On January 15, 2009, Chesley B. Sullenberger was celebrated world-wide: after the two engines had failed due to bird strike, he and his flight crew succeeded...
In the field of nanoscience, an international team of physicists with participants from Konstanz has achieved a breakthrough in understanding heat transport
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Tungsten density
Tuf-Flite 90% Tungsten 18 Gram Soft Tip Dart Set TF-24-18 by Dart Brokers. $39.95. MSRP $79.95 HIGH DENSITY 90% TUNGSTEN BARRELS, SLIM CENTER-BALANCED DESIGN. Extra strong aluminum shafts. Double Thick Tuf-Flite Flights. Flight color may vary between Red, Blue, Black, Purple, Pink or White to best match dart. Professionally balanced and designed for the player that really takes the game serious. Dart Brokers ships next business day. We are one of the largest dis...
The #PXG 0811 driver has platinum colored weights made of high-density tungsten and black weights made of low-density titanium. The tungsten provides a significant moveable mass in the clubhead, easily adjusted to optimize launch, spin and direction. Fine-tuning will alter the initial launch conditions allowing the golfer to achieve the best possible results without altering his or her swing. #TechTuesday
$8.99 (Buy here: https://alitems.com/g/1e8d114494ebda23ff8b16525dc3e8/?i=5&ulp=https%3A%2F%2Fwww.aliexpress.com%2Fitem%2FHigh-Quality-Capo-for-6-string-Guitar-Unique-High-Density-Tungsten-Steel-Forging-For-Folk-Guitar%2F32739147882.html ) High Quality Capo for 6-string Guitar Unique High-Density Tungsten Steel Forging For Folk Guitar & Other Similar Instruments for just $8.99
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Cuesoul Black Scorpion Steel/Soft Tips #Darts Series, Very Cool and Fashional design ,another great choice for primary #dartsplayer, Now available on #Cuesoul.com , #Amazon.com ,#Amazon Europe (uk,de,fr,es,it),#eBay and #Wish etc.High density tungsten materials for black scorpion series are coming soon ...
Winmau Stratos Dual Density Darts 85/95 Tungsten 24gms only RRP $149.99 now $85 #Winmau
cobra Golf L4V X Speed Driver The ultra-lightweight carbon composite crown and sole, along with high-density tungsten backweighting of the Cobra L4V X Speed Driver work together to shift weight low and back, generating a MOI (mome http://www.comparestoreprices.co.uk/golf-equipment/cobra-golf-l4v-x-speed-driver.asp
Mens Womens 5mm Tungsten Carbide Ring Turquoise Wedding Engagement Band High Polished Beveled Edges Comfort Fit. As a heavy metal, tungsten carbide is a very hard and dense with hardness between 8.5 and 9.5 on the hardness scale (Diamonds come to a 10). Its density allows tungsten to be used in jewelry as an alternative to gold or platinum. Tungsten carbide is about 10 times harder than 18k Gold, 4 times harder than titanium stainless steel, and it never fade, deform and always keep...


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Brand newLOWEST PRICE
Franklin of Philadelphia (Belknap Press) Esmond WrightAU $45.46+ AU $7.50 postage
- Brand new condition
- Sold by roxy*books
- See details for delivery est.
Nearly newLOWEST PRICE
Franklin Of Philadelphia by Wright Esmond - Book - Soft CoverAU $20.50Free postage
- Like new condition
- Sold by marlowes_books
- Est. delivery by 6 Mar
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USED (VG) Franklin of Philadelphia (Belknap Press S) by Esmond WrightAU $20.95+ AU $12.95 postage
- Very good condition
- Sold by ausreseller
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About this product
- DescriptionThe most original and most delightful of the Founding Fathers, Benjamin Franklin was publisher and printer, essayist and author, businessman and general, scientist and philologist, politician and diplomat, moralist and sage and a thoroughly rational patriot who was a major force in winning his country s independence and securing its life in the Constitution. Born poor in Cotton Mather s Boston, he was soon at ease in Quaker Philadelphia, and later in royal London, and in elegant Paris. Born with advantages, he died wealthy and esteemed. He was the quintessential American, almost totally free of the limits of his environment, ready to accept any challenge, to speculate, experiment, and question.Esmond Wright, the distinguished English scholar of America, sees Franklin as an Old England Man and a reluctant revolutionary; civilized, urbane, devious, and on occasion just a little unscrupulous. For, despite his charm and genius, Franklin was t admired by everybody. His contemporary John Adams thought little of his political abilities, and the Federalist pamphleteer William Cobbett called him a crafty and lecherous old hypocrite. In the next century, Mark Twain, Hawthorne, and Melville did t value him; still later, D. H. Lawrence despised the middle-class morality he promoted. Many today deplore his lack of interest in the arts or metaphysics, his lack of passionate commitment, his opportunism, his occasional coarseness. Yet his success in business, his many-faceted public career, his ingenious inventions and world-rewned scientific genius, his splendid prose style, his worldly wisdom, and the attractive personality that shines through his remarks and writings, made Benjamin Franklin the new man of the eighteenth-century dream and also vastly appealing to the modern temper. Wright s new biography presents a fully rounded portrait of this remarkable man for all ages.This first comprehensive biography of Franklin in fifty years has taken advantage of Yale s massive edition-in-progress of Franklin s papers and of the many specialized studies inspired by the correspondence. Franklin of Philadelphia, designed for the general reader, is also a work for scholars, for the author appends a thorough analysis of other interpretations of Franklin s career and personality. Sales Points
- Author BiographyEsmond Wright is Professor of History, Emeritus, University of London.
Key Features
- Author(s)Esmond Wright
- PublisherHarvard University Press
- Date of Publication01/07/1988
- LanguageEnglish
- FormatPaperback
- SubjectBiography: General
- Series TitleBelknap Press S.
Publication Data
- Place of PublicationCambridge, Mass
- Country of PublicationUnited States
- ImprintHarvard University Press
- Content Note17 halftones, 1 map, and 4 line illustrations on 12 inserted pages
- Weight617 g
- Width152 mm
- Height233 mm
- Spine30 mm
Editorial Details
- Edition StatementNew edition
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Check rates!
Free WiFi! WiFi is available in all areas and is free of charge.
Free parking! Free public parking is possible at a location nearby (reservation is not needed).
From 14:30 Until 16:00 hours
From 09:00 Until 12:00 hours
All children are welcome.There is no capacity for extra beds in the room.
Pets are not allowed.
This property only accepts cash payments.
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Hello all!
It has been a veeerrrrryyy long time since our last official release but finally we are proud to annouce the availability of easyrec 1.0.
We have added a new JSON based profile system in the new release which enables the use of content based recommendation approaches in addition to
the existing action based ones. Therefore - after all those years in beta - we feel confident to call easyrec feature complete (for the time being) and
think the move to 1.0 is justified.... read more
Due to the changes in the sourceforge platform, we had to move our blog here from its former location to this one. See you soon!


text:
List all words ending with luxuriousnesses
Only the word luxuriousnesses was found, nothing longer.
Some random words: maar eerie ordos juba amoeba dreg equabilities
This is not a dictionary, it's a word game wordfinder.
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Monthly Archives: March 2012
One Week (the film): What would you do?
The 2008 film "One Week" starts with the main character, Ben Tyler, sitting across the table from his doctor, as he receives the news that he has gotten a very aggressive form of cancer and needs to immediately start an … Continue reading
Posted in Film Reviews, The Book Tagged film, life, norton motorcycle, one week 2 Comments
High Pass, Snow, Low Pass
Finally I can report here the first ride of the year. And what a ride it was, what a great way to start the new riding season! Before the weekend I had checked the weather forecast and those wise people … Continue reading
Posted in Riding the Yamaha Tagged Gravel and snow riding, motorcycle, motorcycles, oregon, Prairie Mountain, WR250R, Yamaha Leave a comment
Brazilian Carnaval @ Cozmic Pizza in Eugene
This was the best so far. Since I've moved to Eugene in 2005 I've attended annual Carnaval events at Cozmic Pizza if I was in town. It is a great opportunity for people to enjoy the bands dedicated to Brazilian … Continue reading
Posted in Random Thoughts 2 Comments
American Samoa (Places to Stay)
I can't believe it, but I have not ridden a motorcycle in 2012 yet. Weather and work have conspired to keep me away from the bikes. I'm getting anxious… but I know very nice riding days will soon be here. … Continue reading
Posted in Travel Tagged American Samoa, La Falepule, Moana O Sina, Pago Pago, South Pacific, travel 8 Comments


text:
Makeup gives patients a boost
Relevant offers
Helping women feel better about themselves while undergoing cancer treatment keeps Denise Leighs volunteering.
The Christchurch mother began giving her time to the Look Good Feel Better charity shortly after she lost her house in the September 2010 earthquake and her son, Sam, was diagnosed with testicular cancer.
The charity offers free workshops for women undergoing cancer treatment, where volunteers show them how to use makeup and skincare products, donated by the cosmetic industry.
"Obviously I couldn't do [Sam's] makeup, but . . . when you're up at the hospital and you see all these people, and especially women, their skin's changing dramatically. They're trying to hold it all together and this programme gives them something back," Leighs said. "I think makeup helps. It gives them more confidence."
Her 26-year-old son is now in remission.
The diagnosis came only a week after the family's home was destroyed in the September quake, but the experience made Leighs realise "things don't matter".
"It's about your family and getting them to feel better."
Leighs, an interior designer and consultant for Mary Kay cosmetics, said many women who came to Christchurch from other parts of the South Island for cancer treatment often did not have time to bring makeup or skincare products with them.
Speaking ahead of International Volunteer Day today, Leighs said volunteering was "just giving something back to someone else".
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Should fluoride in water be the responsibility of central government?


text:
How do I get my 2000 dodge durango slt out of 4 low locked?
I recently bought a 2000 Durango and it is stuck in 4 low locked. The person we bought it from drove it on a daily basis and didn't know it was in 4 low cause the light never came on. The front end is now knocking and acting up. ABS light and check engine light is on.
1 Answer
Your truck´s tranny must be in neutral and if it is stiff you can try to rock the truck back and forth to loose the tension. If the lever is very loose you might have a broken connection from the lever to the T-case. The truck must not be driven on paved or concrete roads in 4WD low or high only on loose ground like gravel, mud or snow. Hope your front or rear dif is ok and the T-case.
Your Answer
Search Dodge Durango Questions
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text:
Note: Do not Buy Premium account from Reseller
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» Vuimedia.org » Application » Autodesk HSMWorks 2017 R1.41441 for SolidWorks 2010-2017 Win32/Win64-SSQ
Autodesk HSMWorks 2017 R1.41441 for SolidWorks 2010-2017 Win32/Win64-SSQ
Author: rukensai on 10-01-2017, 15:18
Autodesk HSMWorks 2017 R1.41441 for SolidWorks 2010-2017 Win32/Win64-SSQ | 586 MB
Description: HSMworks (High Speed ââMachining) – high-speed processing module for SolidWorks.
HSMWorks designed from the ground up to work inside SolidWorks, and is a logical extension of the parametric SolidWorks environment to the CAM strategies. Experienced SolidWorks users will feel
at home working with HSMWork, and will be able to create high-quality treatment programs for a few minutes.
New users will be able to take advantage of 2D and 3D CAD in SolidWorks and implement design and design decisions in the CAM process, resulting in improved design quality and reduce product development time.
HSMWorks and SolidWorks interface is the same for all users – CAD and CAM. If you know, SolidWorks, familiarity with HSMWorks will be easy and successful. HSMWorks gives the possibility of obtaining high performance at an optimal trajectory intrumenta movement. For processors, HSMWorks allows you to create the most modern, most effective CAM program in a shorter time and with the least effort.
HSMWorks CAM system is a new generation that is able to reduce the time to develop the machine control programs and CNC processing times many times, with respect to existing CAM systems.
Year / Release Date: 2016
Version: 2017 R1 Build 41441
Developer: Autodesk
Developer website:
Russian site about HSMWorks:
Bit depth: 32bit + 64bit
Language: Multilingual (Russian available)
Medicine: Present (TeAM SolidSQUAD-SSQ)
System Requirements: Operating System
⢠Windows 10
⢠Windows 8
⢠Windows 7
⢠Windows Vista
64-bit (x64) versions are recommended.
NTFS File System is recommended.
CAD System
⢠SolidWorks 2010 or newer.
⢠Internet Explorer 8 or newer.
CPU Type
⢠Intel® Pentium® 4 or AMD Athlon ⢠Dual Core, 3.0 GHz or Higher with SSE2 technology.
⢠On 32-bit operating systems: 2GB. 4 GB or more is recommended when working with complex parts.
⢠On 64-bit operating systems: 4GB.
Display Resolution
⢠1,024 x 768 with true color (1,600 x 1,050 with true color recommended)
Hard Disk
⢠Installation 6 GB
Pointing Device
⢠A mouse with 3 or more buttons and a scroll wheel is recommended.
Multiple Processors
⢠Dual / Quad core CPUs will be utilized when calculating toolpaths.
⢠English, German, Spanish, Japanese, Czech, Polish
Display Card
⢠Any SolidWorks certified graphics card. Please see
Download link:
Links are Interchangeable - No Password - Single Extraction
Back 20 0
Category: Application


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text:
TripAdvisor Traveller Rating
Based on 108 reviews
Hotel description L'Altineige
The residences are situated at the entry of the resort, at the foot of the ski slopes and first ski lifts, and close to shops and facilities. The residence is linked to the commercial gallery and to the sports' centre by a covered passageway.A stay at Val Thorens, Europe's highest ski resort, implies the choice of an exceptional site and the chance to benefit from an unprecedented network of ski lifts. As well as skiing, Val Thorens also places the accent on entertainment and activities and extends its welcome especially to children.The apartments are all fully equipped: kitchenette (fridge, mini-oven, hot-plates, dishwasher), bathroom or shower, separate toilet(except the Altineige studio appartments for 2 pers) and balcony.
Hotel type
- • Residence
Methods of payment
- • Visa
Room facilities (Standard room)
- • Balcony
- • Bathroom
- • Bathtub
- • Cooker
- • Fridge
- • Ironing set
- • Kitchenette
- • Shower
Hotels nearby L'Altineige
- At 0.39 miles
Residence Pierre et Vacances Les Temples du Soleil
The Les Temples du Soleil residence is located near the entrance to the dynamic resort of Val Thorens, with direct access to the slopes.It has a number of facilities and shops on the ground floor: a mini-market, newsagent, bar and restaurant.The Relaxation and Fitness area in the residence gives you access to two Jacuzzis, a sauna and a hammam (open in season).A full range of amenities and shops are in the centre of the Val Thorens resort, 500 m from the Les Temples du Soleil residence: restaurants, mini-markets, bakeries, banks, doctor's surgery, pharmacy, bowling and more.Customer reviews3.0/5of 1 Opinions
See more
- At 2.31 miles
Les Bruyeres
This ski hotel is in the Savoie, some 30 km from Moûtiers and 100 km from Chambéry, in the Belleville valley. The completely renovated hotel offers an exceptional location in the heart of the Bruyères district and at the foot of the ski slopes. The hotel is set in the ski resort of Les Ménuires and guests will find numerous restaurants, bars, pubs and shops in the immediate vicinity. The nearest train station is in Moûtiers, a 30-minute drive away, whilst Geneva and Lyon are approximately a 2-hour and 3-hour drive away respectively.Facing due south, the 95 guest rooms offer exceptional panoramic views. The hotel has a lobby and guests can enjoy the convenience of a 24-hour reception service. There is a hotel safe and a bar with a fireplace, plus restaurant serving Savoyard specialties. The hotel has a kids' club to keep younger guests entertained and for an additional fee guests can make use of the laundry service.The rooms feature private bathroom and include facilities including hairdryer, direct dial telephone, satellite TV, Internet access, minibar and room safe. Guests can enjoy the magical views from the balcony or terrace.The 3 Vallées ski area is one of the largest in the world, with 600 km of downhill ski runs, 118 km of cross-country skiing, plus direct links to Val Thorens, Méribel and Courchevel. Furthermore, the hotel itself has an Après-ski centre with a sauna, hammam and gym.Le Frontenac restaurant is situated on the 9th floor and serves a breakfast buffet as well as dinner featuring traditional cuisine with Savoyard specialities. L'Olympique panoramic bar with fireplace and terrace offers an unimpeded view over the mountains.By car: Take the motorway to Albertville and then the dual carriageway to Moûtiers, followed by the D915. By Train: Moutiers TGV Railway Station is 27 km from the hotel.
See more
- At 2.48 miles
Chalet Du Mont Vallon Spa Resort
The hotel is located on D117 highway in Les Menuires resort in the 3 Valleys area and just a few metres from the ski lifts. Situated in the largest ski area in the world, linked together by ski runs and lifts, with 600 kms of interconnected slopes, this is the perfect resort for a winter holiday. With 85% of the area located above 1800m altitude, snow is guaranteed. The hotel has a restaurant. Guests can also enjoy a drink on the terrace or beside the open fire in the guest lounge. Access to high-speed wireless Internet is provided throughout the premises. There are 2 meeting rooms available for conferences. In addition to an indoor pool, the hotel has a wellness centre with whirlpool and sauna for guests to relax in.
See more


text:
|Publication number
|Publication type
|Application number
|Publication date
|Oct 28, 2008
|Filing date
|Nov 28, 2006
|Priority date
|Nov 28, 2006
|Fee status
|Also published as
|Publication number
|Michael William Morrow
|Original Assignee
|Qualcomm Incorporated
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (7), Classifications (9), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates generally to the field of pipelined processors and, in particular, to a method of recognizing subroutine call in order to reduce power and increase utilization of the pipelined processor.
Microprocessors perform computational tasks in a wide variety of applications. Improved processor performance is almost always desirable, to allow for faster operation and/or increased functionality through software changes. In many embedded applications, such as portable electronic devices, conserving power is also an important goal in processor design and implementation.
Many modern processors employ a pipelined architecture, where sequential instructions are overlapped in execution to increase overall processor throughput. Maintaining smooth execution through the pipeline helps achieve high performance. Most modern processors also utilize a hierarchical memory, with fast, on-chip cache memories storing local copies of recently accessed data and instructions.
Real-world programs include indirect branch instructions, the actual branching behavior of which is not known until the instruction is actually evaluated deep in the execution pipeline. Most modern processors employ some form of branch prediction, whereby the branching behavior of indirect branch instructions is predicted early in the pipeline, such as during a fetch or decode pipe stage. Utilizing a branch prediction technique, the processor speculatively fetches the target of the indirect branch instruction and redirects the pipeline to begin processing the speculatively fetched instructions. When the actual branch target is determined in a later pipe stage such as an execution pipe stage, if the branch was mispredicted, the speculatively fetched instructions must be flushed from the pipeline, and new instructions fetched from the correct target address. Prefetching instructions in response to an erroneous branch target prediction adversely impacts processor performance and power consumption.
One example of indirect branch instructions includes branch instructions utilized to return from a subroutine. For example, a return call from a subroutine may include a branch instruction whose return address is defined by the contents of a register. A return address defines the next instruction to be fetched after the subroutine completes and is commonly the instruction after a branch instruction from which the subroutine was originally called. Many high-performance architectures designate a particular general purpose register for use in subroutine returns, commonly referred to as a link register.
For convenience, a return call may also be referred to as a branch return instruction. In order for a processor pipeline to utilize branch prediction for a branch return instruction, conventional software includes an explicit subroutine call such as a branch and link instruction to record the return address into the link register. Many high performance implementations include a link stack structure at the decode stage of processing the branch and link instruction. Link return values are pushed onto this stack, in order to allow for accurate branch prediction when the corresponding subroutines return. Conventional link stack structures contain a list of return addresses in order to support multiple subroutine calls flowing through a pipeline and to support the nesting of multiple levels of subroutine calls. Subsequently, when the branch return instruction within the subroutine is being decoded, the return address is read from the link stack structure to be utilized in branch prediction to predict the target address if other branch prediction hardware dictates that the processor should redirect the pipeline. If the predicted result indicates to redirect the pipeline, the pipeline begins fetching instructions from the return address that was read from the link stack structure.
However, there exists many compilers and legacy code which do not generate or incorporate conventional branch and link instructions when calling a subroutine. Therefore, in those situations, the link stack structure is not utilized resulting in the integrity of the link stack structure to be compromised. For example, the conventional popping of a return address from the link stack structure may not correlate to the return instruction which stimulated the popping of the return address in the first place. One effect of a compromised link stack structure includes increased mispredictions on return instructions. Furthermore, in those situations where a subroutine call is not recognized in a program segment, the problem is compounded because branch prediction hardware may not be utilized to populate the link stack structure on subsequent unrecognizable subroutine calls. By way of example, refer to the following table containing a code segment which would run on an ARM Ltd. compatible processor:
Code Segment.
LDR LR, 0x00899818
BR 0x00990000
. . .
The program flow of the code segment in Table 1 includes processing the instructions in sequential order starting at address 0x00899808 and through to address 0x00899814. At address 0x00899814, a branch instruction changes the program flow so that the next instruction processed is located at address 0x00990000, the start of a subroutine.
The combination of setting the link register (i.e. LDR LR, 0-00899818) and the branch instruction (i.e. BR) prepare the processor for a subsequent branch to a subroutine. In this example, the actual subroutine to which the call is made begins at address 0x00990000 and ends at address 0x0099000C. The LDR LR, 0x00899818 instruction indicates that address 0x00899818 should be copied into a link register (LR) resulting in storing the return address, address 0x00899818, into the link register. At the end of the subroutine, the return address is retrieved from the link register. More specifically, the return address is retrieved when executing BX LR, the branch return instruction. Other code segments which imply a subroutine call exist and include instructions which modify the link register such as the sequential combination of instructions MOV LR, PC BR [A] where [A] is the address of the beginning of a subroutine.
The present disclosure recognizes the pervasiveness of such legacy software, compilers that produce code segments having two or more instructions which correspond to a subroutine call, and the cost involved in re-writing legacy software to utilize conventional branch and link instructions when calling a subroutine. Furthermore the present disclosure recognizes a need for microprocessors developed today to recognize instruction sequences which imply a subroutine call in order to utilize a link stack structure and effectively predict the return address when a branch return instruction.
According to one embodiment, a method of recognizing a subroutine call is provided. The method includes detecting a non-sequential change in program flow, retrieving a next sequential address after the detected non-sequential change in program flow, and comparing the next sequential address with the contents of a register to determine whether the non-sequential change is a subroutine call.
Another embodiment relates to an apparatus for recognizing a subroutine call. The apparatus includes a circuit having three inputs. The first input is configured to receive contents of a register. The second input is configured to receive a non-sequential change in program flow. The third input is configured to receive the next sequential address after the non-sequential change in program flow. The circuit is configured to compare the next sequential address and the contents of the register to determine whether the non-sequential change in program flow is a subroutine call.
According to yet another embodiment, another apparatus is disclosed. The apparatus comprises a processor pipeline for processing instructions and a circuit coupled thereto. The circuit is configured to receive contents of a register, an indication of a non-sequential change in program flow, and the next sequential address after the indication of the non-sequential change in program flow. The circuit is also configured to compare the contents of the link register with the next sequential address to determine whether the indication of a non-sequential change in program flow is a subroutine call.
It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
The processor 100 also includes an instruction pipeline 105 for processing instructions and a branch prediction circuit 132 for predicting a target address for an indirect branch instruction and predicting whether to redirect instruction pipeline 105 to process the target address. If the branch prediction circuit 132 predicts to redirect the instruction pipeline 105, the indirect branch instruction is said to have been "predicted taken." If the indirect branch instruction has been "predicted taken," the branch prediction circuit 132 predicts a target address of the indirect branch instruction and redirects the instruction pipeline 105 to begin fetching instructions at the target address.
The processor 100 processes instructions in an instruction pipeline 105 according to control logic circuit 122. In some embodiments, the pipeline 105 may be a superscalar design having two or more parallel pipelines. The pipeline 105 includes various pipe stages: an instruction fetch unit (IFU) stage 102, a decode (DCD) stage 106, an instruction queue (IQ) stage 108, a register access (RACC) stage 112, and an execution stage (EXE) 120. In some embodiments, a pipe stage may process a single instruction at a time. In another embodiment, a pipe stage may concurrently process two or more instructions at a time. It should be noted that pipe stages may be added to or subtracted from pipeline 105 without limiting the scope of the present disclosure. The processor 100 also includes a General Purpose Register (GPR) file 118 which includes registers that, through microarchitectural convention, are accessible by pipe stages 112 and 120.
The instruction fetch unit (IFU) stage 102 attempts to retrieve an instruction from in I-cache 110. If an instruction address is not found in I-cache 110, the instruction fetch unit (IFU) stage 102 initiates a request to retrieve the corresponding instruction from memory 138. The decode stage 106 fully decodes an instruction. Furthermore, in addition to conventional functions performed at a decode stage, decode stage 106 recognizes conventional subroutine call instructions such as ARM Inc.'s branch and link instruction and writes a return address into a link stack structure 134. The link stack structure 134 may be a set of registers managed as a circular buffer. The return address is an address of an instruction to which pipeline 105 is to be redirected at the completion of a subroutine. On an indirect branch instruction, the decode stage 106 may invoke the branch prediction circuit 132 in order to determine whether to begin fetching instructions to pipeline 105 from a speculative target of the branch instruction.
The instruction queue stage 108 buffers one or more instructions in order to allow speculative fetching to continue during stalls, if any, of the execution pipeline. The register access stage 112 retrieves one or more operands from the general purpose register 118 as may be needed by an instruction. Execute stage (EXE) 120 includes known components such as arithmetic logic units and the like in order to execute instructions. The results produced from execute stage 120 are written to the GPR file 118. During execute stage 120, actual branch resolution takes place to determine if branch prediction made during decode stage 106 is correct. If the actual branch resolution differs from the predicted destination, a branch is said to have been mispredicted.
The execute stage 120 also invoke the IsCall logic circuit 114 to determine if a branch instruction corresponds to an implicit subroutine call. The IsCall logic circuit 114 records this result in the branch prediction (BP) circuit 132 in order for subsequent execution of the branch instruction to be interpreted as an implicit subroutine call during an earlier pipe stage such as DCD 106 or IFU 102. In one embodiment, the recorded result is a flag which is stored in the BP circuit 132 and is associated with the branch instruction. If the branch instruction is an implicit subroutine call, the IsCall logic circuit 114 updates the link stack structure 134 with the address of the instruction following the branch instruction. The IsCall logic circuit 114 will be described in more detail in connection with the discussion of
Those of skill in the art will recognize that numerous variations of the processor 100 are possible. For example, the processor 100 may include a second-level (L2) cache for I-cache 110. In addition, one or more of the functional blocks depicted in the processor 100 may be omitted from a particular embodiment. Other functional blocks that may reside in the processor 100, such as a translation lookaside buffer, data cache, and the like are not germane to a description of the present invention, and are omitted for clarity.
Columns 210A-210E of timing diagram 200 correspond to the stages of pipeline 105. Rows 1-11 correspond to sequential timing cycles. For explanation purposes, each pipe stage processes one instruction per cycle. However, it should be recognized by one skilled in the art that the teachings of the present disclosure apply to both multiple cycle pipe stages and to pipe stages that are able to process multiple instructions per cycle.
Column 210F of timing diagram 200 corresponds to the contents of a flag named IsCallFlag which indicates whether an indirect branch instruction results in a subroutine call. Column 210G corresponds to the contents of the link register (LR). Column 210H corresponds to the contents of a link stack structure such as link stack structure 134 as a result of the IsCall logic circuit 114.
In general, instructions enter the IFU stage 210A and propagate to the next stage in the next cycle. In cycle 1, the LDR LR, 0x00899818 instruction is in the IFU stage 210A. Instructions ADD, SUB, BR, and generic instruction, INSTRA, are sequentially fetched from IFU pipe stage 210A. In cycle 5, at point in time 215, decode stage 210B decodes the BR instruction and invokes branch prediction such as branch prediction circuit 132. Branch prediction predicts that the BR instruction will be taken and, thus, the pipeline 105 is redirected to sequentially fetch the subroutine instructions ADD, SUB, MOV, and BX. The subroutine comprises all the instructions beginning with the ADD instruction and ending with the BX instruction as shown in Table 1. Before redirecting the pipeline 105, INSTRA is flushed from the pipeline 105 since it was fetched prior to branch prediction. The blank cycle following the BR instruction depicts the position of the INSTRA instruction in the pipeline 105 would have taken if it had not been flushed.
From cycles 1-5, the LDR instruction propagates through pipe stages 210B-210E. In cycle 5, at point in time 205, the execute stage 210E executes the LDR instruction to load the return address 0x00899818 into the link register (LR). At point in time 220, the return address (RA) 0x00899818 is available in the link register. The return address refers to INSTRA in Table 1 meaning that at the end of executing the subroutine beginning at address 0x00990000, the flow of instruction execution should return to address 0x00899818.
At point in time 225, the execute stage 210E executes the BR instruction. The execute stage 210E validates whether the BR instruction should have been taken. The execute stage 210E also invokes the IsCall logic circuit 114 to determine whether the BR instruction is a branch to a subroutine. The phrase "branch to a subroutine" is also referred to as a subroutine call. The IsCall logic circuit 114 utilizes the next address following the BR instruction which is the address of INSTRA even though INSTRA was previously flushed from the pipeline 105. Since the address of the next instruction equals the return address stored in the link register (LR), the IsCall logic circuit 114 sets the is CallFlag 210F associated with the BR instruction and stores it with the address of the BR instruction in the branch prediction circuit 132. An exemplary branch prediction storage element will be described in connection with
The final instruction of the subroutine, BX, is decoded in cycle 10, point in time 235. Decode stage 210B recognizes the BX instruction as a return call and, thus, branch prediction 132 predicts the program flow by popping the return address (RA) off of the link status structure 210H. Decode stage 210B redirects the pipeline 105 to begin fetching from INSTRA whose address is the same as the return address (RA). See reference point 240. Also, in cycle 11, since the RA was popped (i.e. read and removed from the link status structure), the link status structure 210H no longer contains return address. Utilizing the processor of
The next time a BR instruction is processed by the pipeline 105, branch prediction circuit 132 may utilize the set IsCallFlag associated with the address of the BR instruction stored therein to populate the link status structure earlier than the first time the BR instruction was processed by pipeline 105.
At clock cycle n, the same BR instruction enters the pipeline 105 at IFU stage 210A. At clock cycle n+1, INSTRA enters the TFU stage 210A and the BR instruction is decoded by DCD stage 210B. During the DCD stage 210B, the branch prediction circuit 132 looks up the address of the BR instruction and finds that it has a corresponding IsCallFlag set indicating that the BR instruction is a subroutine call. Consequently, the DCD stage 210B pushes the next address, the address for INSTRA on to the link status structure 210H as shown at reference 245.
If the detected non-sequential change in program flow has not been previously indicated as a subroutine call, the method 500 proceeds to block 520. At block 520, the next sequential address after the detected non-sequential change in program flow is retrieved. For example, the next address after the branch instruction. The next address may be provided by various means including a preceding pipe stage, a next program counter (PC) generation circuit in the IFU stage 102, or the like. At block 530, the next sequential address is compared with the contents of a link register. As discussed above in connection with
At block 550, the contents of the link register is pushed on to a link stack structure. For example, when a branch instruction is executed as illustrated in
The method 500 proceeds to wait block 580 which waits for the next non-sequential change in program flow. Once the next non-sequential change in program flow arrives in a pipeline, the method 500 proceeds to block 510 and then to block 515. If the next non-sequential change in program flow has been previously detected, the non-sequential change in program flow will have been already indicate, thus, block 515 will proceed to block 550.
The various illustrative logical blocks, modules, circuits, elements, and/or components described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
While the invention is disclosed in the context of embodiments, it will be recognized that a wide variety of implementations may be employed by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below.
|Cited Patent
|Filing date
|Publication date
|Oct 10, 1986
|May 16, 1989
|International Business Machines Corporation
|Branch and return on address instruction and methods and apparatus for implementing same in a digital data processing system
|Feb 17, 1998
|Oct 26, 1999
|International Business Machines Corporation
|Apparatus and method for performing subroutine call and return operations
|Mar 22, 2000
|May 24, 2005
|Fujitsu Limited
|Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof
|Jan 4, 2002
|Dec 6, 2005
|Advanced Micro Devices, Inc.
|Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction
|Jan 8, 2003
|May 22, 2003
|Fujitsu Limited
|Predicted return address selection upon matching target in branch history table with entries in return address stack
|Jul 12, 2006
|Nov 9, 2006
|Nec Electronics Corporation
|Instruction prefetch apparatus and instruction prefetch method
|Aug 31, 2006
|Mar 6, 2008
|Brian Michael Stempel
|Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Nov 28, 2006
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October 3, 2016
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Wednesday, January 22, 2014
Salmon River 62, Garden Valley 43
GARDEN VALLEY — Having started a couple of freshmen in lieu of two regular starters in a win over Tri-Valley earlier in the week, Salmon River kept up an unbeaten record in the Long Pin Conference with a 62-43 win over Garden Valley last Saturday, Jan. 18. Leighton Vander Esch scored 44 points for the 10-2 (5-0 league) Savages.
Prairie 63, Genesee 53
COTTONWOOD — Rhett Schlader stepped up with a team-high 20 points last Saturday, Jan. 18, as Prairie ran its record to 10-0 and opened up a two-game lead over Genesee in the Whitepine League standings.
Chiming in with 15 points and 12 points, respectively, were Jake Bruner and Lucas Arnzen.
After an even first quarter, Prairie slowed Genesee's offense — albeit not enough to strangle a 27-point night for Genesee's top scorer. Prairie continued to score apace during the middle periods, and carried a 12-point lead to the fourth quarter.
Earlier in the week, the Pirates allowed just five field goals and a couple of foul shots in a lopsided win over Potlatch.
Up next for Prairie are league games at home against Troy (Jan. 24) and Lapwai (Jan. 30); PHS will visit Orofino on Jan. 23.
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You are here > Home > Baseball Newsstand > Baseball Primer Newsblog > Discussion
Baseball Primer Newsblog
— The Best News Links from the Baseball Newsstand
Tuesday, February 12, 2013
Baseball America: International Reviews: Tampa Bay Rays
This is interesting, I had no idea the Rays had been blowing past the international spending cap like this. I believe a primate recently asked why a team wouldn't spend excessively one year on international free agents to load up on top-end talent and then accept that the next year they would be very limited in what they could do. The Rays haven't gone massively over budget but it appears they are making use of that suggested strategy.
Jim Wisinski Posted: February 12, 2013 at 12:30 AM | 2 comment(s) Login to Bookmark
Tags: international, prospects, rays
Reader Comments and Retorts
Statements posted here are those of our readers and do not represent the BaseballThinkFactory. Names are provided by the poster and are not verified. We ask that posters follow our submission policy. Please report any inappropriate comments.1. John Northey Posted: February 12, 2013 at 10:40 AM (#4367733)
Given the penalties given out to the Rays I say go for it if I'm a ML team. Try to see which year will be strong and which will be weak so you take advantage at the best possible time. Then when you go over don't do a Tampa, go totally nuts and grab everyone you can. Blow $10 million ($18 after penalties) and get the top 10 players available. Force MLB to create an international draft due to this, but grab the top talent for yourself first. I think the Rays were very smart to do it this year before others decide to do it as well.2. Der-K: downgraded to lurker Posted: February 12, 2013 at 11:00 AM (#4367769)
I believe a primate recently asked why a team wouldn't spend excessively one year on international free agents to load up on top-end talent and then accept that the next year they would be very limited in what they could do.
I did, for one.
For what it's worth, Tampa hasn't gone _that_ nuts with spending. If we accept BA's pre-signing period rankings as gospel, they landed the #3, #6, and #14 guys (of the top 20). That's impressive, but they haven't exactly tried to buy up the market (which would be expensive from both a supply v. demand aspect, as well as the tax). Their share of top players will be less than what we've recently seen with Toronto, Texas, and Seattle (to name three) in the pre-pool era. Also, the timing is notable - this year, all teams had the same pool, that's changing to one that varies by success (which would hurt Tampa with the top dudes). Even with the penalty, they'd still be able to sign all the other guys they've tabbed since July (bonus < 250K), so it's not going to cripple their Caribbean operations or anything.
I think this is a better strategy with the int'l market than with the domestic draft - where I think I'd try to stick within the league's parameters (after you account for the buffer).
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