text:
|Publication number
|Publication type
|Application number
|Publication date
|Apr 26, 2005
|Filing date
|Nov 15, 2001
|Priority date
|Nov 15, 2001
|Fee status
|Also published as
|Publication number
|Elizabeth A. Richard, John E. Larson
|Original Assignee
|Hewlett-Packard Development Company, L.P.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (14), Referenced by (34), Classifications (13), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Field of the Invention
This invention relates generally to memory systems and, more particularly, to processing requests in a memory system.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Computers today, such as personal computers and servers, rely on microprocessors, associated chip sets, and memory chips to perform most of their processing functions. Because these devices are integrated circuits formed on semiconducting substrates, the technological improvements of these devices have essentially kept pace with one another over the years. In contrast to the dramatic improvements of the processing portions of a computer system, the mass storage portion of a computer system has experienced only modest growth in speed and reliability. As a result, computer systems failed to capitalize fully on the increased speed of the improving processing systems due to the dramatically inferior capabilities of the mass data storage devices coupled to the systems.
While the speed of these mass storage devices, such as magnetic disk drives, has logged in recent years, the size of such disk drives has become smaller while maintaining the same or greater storage capacity. Furthermore, such disk drives have become less expensive. To capitalize on these benefits, it was recognized that a high capacity data storage system could be realized by organizing multiple small disk drives into an array of drives. However, it was further recognized that large numbers of smaller disk drives dramatically increased the chance of a disk drive failure which, in turn, increases the risk of data loss. Accordingly, this problem has been addressed by including redundancy in the disk drive arrays so that data lost on any failed disk drive can be reconstructed through the redundant information stored on the other disk drives. This technology has been commonly referred to as "redundant arrays of inexpensive disks" (RAID).
To date, at least five different levels of RAID have been introduced. The first RAID level utilized mirrored devices. In other words, data was written identically to at least two disks. Thus, if one disk failed, the data could be retrieved from one of the other disks. Of course, a level 1 RAID system requires the cost of an additional disk without increasing overall memory capacity in exchange for decreased likelihood of data loss. The second level of RAID introduced an error code correction (ECC) scheme where additional check disks were provided to detect single errors, identify the failed disk, and correct the disk with the error. The third level RAID system utilizes disk drives that can detect their own errors, thus eliminating the many check disks of level 2 RAID. The fourth level of RAID provides for independent READs and WRITEs to each disk which allows parallel input-output operations. Finally, a level 5 RAID system provides memory striping where data and parity information are distributed in some form throughout the disk drives in the array.
The implementation of data redundancy, such as in the RAID schemes discussed above, creates fault tolerant computer systems where the system may still operate without data loss even if one drive fails. This is contrasted to a disk drive array in a non-fault tolerant system where the entire system is considered to have failed if any one of the drives fail. Of course, it should be appreciated that each RAID scheme necessarily trades some overall storage capacity and additional expense in favor of fault tolerant capability. Thus, RAID systems are primarily found in computers performing relatively critical functions where failures are not easily tolerated. Such functions may include, for example, a network server, a web server, a communication server, etc.
One of the primary advantages of a fault tolerant mass data storage system is that it permits the system to operate even in the presence of errors that would otherwise cause the system to malfunction. As discussed previously, this is particularly important in critical systems where downtime may cause relatively major economic repercussions. However, it should be understood that a RAID system merely permits the computer system to function even though one of the drives is malfunctioning. It does not necessarily permit the computer system to be repaired or upgraded without powering down the system. To address this problem, various schemes have been developed, some related to RAID and some not, which facilitate the removal and/or installation of computer components, such as a faulty disk drive, without powering down the computer system. Such schemes are typically referred to as "hot plug" schemes since the devices may be unplugged from and/or plugged into the system while it is "hot" or operating.
Although hot plug schemes have been developed for many computer components, including microprocessors, memory chips, and disk drives, most such schemes do not permit the removal and replacement of a faulty device without downgrading system performance to some extent. Furthermore, because memory chips have been traditionally more reliable than disk drives, error detection and correction schemes for memory chips have generally lagged behind the schemes used for disk drives.
However, certain factors may suggest that the reliability of semiconductor memory systems may also require improvement. For instance, in the near future, it is believed that it will be desirable for approximately 50% of business applications to run continuously 24 hours a day, 365 days a years. Furthermore, in 1998, it was reported that the average cost of a minute of downtime for a mission-critical application was $10,000.00. In addition to the increasing criticality of such computer systems and the high cost of downtime of such systems, the amount of semiconductor memory capacity of such systems has been increasing steadily and is expected to continue to increase. Although semiconductor memories are less likely to fail than disk drives, semiconductor memories also suffer from a variety of memory errors. Specifically, "soft" errors account for the vast majority of memory errors in a semiconductor memory. Such soft errors include cosmic rays and transient events, for instance, that tend to alter the data stored in the memory. Most soft errors are single bit errors that are correctable using standard ECC technology. However, some percentage of these errors are multi-bit errors that are uncorrectable by current ECC technology. Furthermore, the occurrence of soft errors increases linearly with memory capacity. Therefore, as memory capacities continue to increase, the number of soft errors will similarly increase, thus leading to an increased likelihood that the system will fail due to a soft error. Semiconductor memories may also suffer from "hard" errors. Such hard errors may be caused by over voltage conditions which destroy a portion of the memory structure, bad solder joints, malfunctioning sense amplifiers, etc. While semiconductor memories are typically subjected to rigorous performance and bum-in testing prior to shipment, a certain percentage of these memories will still malfunction after being integrated into a computer system. Again, as the number of memory chips and the memory capacities of computer systems increase, a likelihood of a semiconductor memory developing a hard error also increases.
Many systems include multiple processing units or microprocessors connected via a processor bus. To coordinate the exchange of information among the processors, a host controller is generally provided. The host controller is further tasked with coordinating the exchange of information between the plurality of processors in the memory system. The host controller may be responsible for the exchange of information in the typical Read-Only Memory (ROM) and the Random Access Memory (RAM), as well as the cache memory in high speed systems. Cache memory is a special high speed storage mechanism which may be provided as a reserved section of the main memory or as an independent high-speed storage device. Usually, the cache memory is a portion of the RAM which is made of high-speed Static RAM (SRAM) rather than the slower and cheaper Dynamic RAM (DRAM) which may be used for the remainder of the main memory. Alternatively or additionally, cache memory may be located in each processor. By storing frequently accessed data and instructions in the cache memory, the system can minimize its access to the slower main memory and thereby increase the request processing speed of the system.
The host controller may be responsible for coordinating the exchange of information among a plurality of system buses as well. For example, the host controller may be responsible for coordinating the exchange of information from input/output (I/O) devices via an I/O bus. Further, systems often implement split processor buses wherein the host controller is tasked with exchanging information between the plurality of processor buses and the memory system. With increased processor and memory speeds becoming more essential in today's fast-paced computing environment, it is advantageous to facilitate the exchange of information in the host controller as quickly as possible. Due to the complexities of the ever-expanding system architectures, which are being introduced in today's computer systems, the task of coordinating the exchange of information becomes increasingly difficult.
In complex systems, which include multiple processors and multiple buses, the host controller generally implements a complex queuing structure to maintain proper ordering of requests being initiated to and from various components in the system. Disadvantageously, to facilitate processing through the complex queuing structure, additional considerations may be necessary to maintain proper priority levels and provide a mechanism for out-of-order processing of requests to minimize system latency. Traditional systems may sacrifice cycle time to simplify the processing of requests.
The present invention may be directed to one or more of the problems set forth above.
The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
Turning now to the drawings and referring initially to
Each of the buses 14A and 14B is coupled to a chip set which includes a host controller 16 and a data controller 18. In this embodiment, the data controller 18 is effectively a data cross-bar slave device controlled by the host controller 16. The data controller 18 may be used to store data from one area of the system 10 awaiting transfer to a requesting area of the system 10 and to implement data manipulation and checking operations. Because of the master/slave relationship between the host controller 16 and the data controller 18, the chips may be referred to together as the host/data controller 16, 18. The host/data controller 16, 18 is further coupled to main memory 24 via one or more memory controllers. In this particular example, the host/data controller 16, 18 is coupled to five memory controllers 20A-20E via five individual bus segments 22A-22E, respectively. The individual bus segments 22A-22E may be referred to collectively as the "MNET" or "MNET bus." Each of the memory controllers 20A-20E is further coupled to a segment of main memory designated as 24A-24E, respectively. As discussed in detail below, each of the memory segments 24A-24E is typically comprised of dual inline memory modules (DIMMs). Further, each memory segment 24A-24E and respective memory controller 20A-20E may comprise a single memory cartridge 25A-25E which may be removable. In the present configuration, data may be stored in a "4+1" parity striping pattern wherein one of the memory cartridges 25A-25E is used to provide redundancy for the collective memory system 26. The 4+1 parity striping in conjunction with the ability to power down individual memory cartridges 25A-25E through each respective memory controller 20A-20E and associated bus segment 22A-22E facilitates hot plug capabilities for the memory cartridges 25A-25E. Further, the system 10 also includes an area of cache memory, functionally illustrated as cache memory 33. However, as previously described, the cache memory 33 may be located in each CPU 12A-12H.
The memory segments may be organized on a single channel or on 2N channels, where N is an integer. In this particular embodiment, each of the memory segments 24A-24E is divided into two channels—a first channel 29A-29E and a second channel 31A-31E, respectively. Since each memory segment 24A-24E in this embodiment is capable of containing up to eight DIMMs, each channel is adapted to access up to four of the eight DIMMs. Because this embodiment includes two channels, each of the memory controllers 20A-20E may include two independent memory controllers.
As will be appreciated from the discussion herein, the number of memory segments 24 may vary depending upon the type of memory system desired. In general, redundant memory systems will utilize two or more memory segments 24. Although the five memory segments 24A-24E illustrated in the exemplary embodiment facilitates a "4+1" striping pattern of data and parity information as discussed in detail below, a memory system having two memory segments 24 may be used in which data is mirrored on each segment to provide redundancy. Similarly, a memory system having three or more memory segments may be used to provide various combinations of data and parity striping.
Each of the memory controllers 20A-20E and its associated main memory segment 24A-24E forms a portion of the main memory array 26. The five memory controllers 20A-20E operate in lock-step. In this example, each of the memory controllers 20A-20E handle a separate quad-word of each cacheline of data (assuming a 42 byte cacheline) that is being transferred to or from the host and data controllers 16 and 18. For example, the memory controller 20A handles the first quad-word of every data READ and WRITE transaction, the memory controller 20B handles the second quad-word, the memory controller 20C handles the third quad-word, and the memory controller 20D handles the fourth quad-word. Instead of receiving one of the four quad-words, the memory controller 20E handles data parity for the four quad-words handled by the memory controllers 20A-20D. Thus, as described below, the memory array 26 forms a "redundant array of industry standard DIMMs" (RAID) memory structure.
During a data READ operation, the host/data controller 16, 18 receives four quad-words of data plus parity from the five memory controllers 20A-20E, validates data integrity of each quad-word and parity using ECC codes, and, if necessary, corrects bad data using an exclusive OR (XOR) engine before forwarding the data to its destination. During a data WRITE operation, the host/data controller 16,18 uses the XOR engine to calculate data parity and transfers the four quad-words of data and the quad-word of parity to the five respective memory controllers 20A-20E. In this embodiment, all data transfers between the host/data controller 16, 18 and the five memory controllers 20A-20E are an entire cacheline, and partial WRITEs are translated into read-modify-write operations.
Furthermore, the five memory bus segments 22A-22E (MNET bus) provide electrical isolation to each of the respective five memory controllers 20A-20E to facilitate hot-plug removal and/or replacement of each of the five memory segments 24A-24E. The RAID functionality described herein allows any one of the five memory segments 24A-24E to be removed while the system 10 continues to operate normally, albeit not in a redundant mode. Once the removed memory segment is reinstalled, the data is rebuilt from the other four memory segments, and the memory system resumes operation in its redundant, or fault-tolerant, mode.
In this embodiment, each of the memory segments 24A-24E may include one to eight dual inline memory modules (DIMMs). Typically, such DIMMs are organized in an X4 or an X8 fashion. In other words, the memory chips on the DIMM are either 4 bits wide or 8 bits wide. To produce a 72 bit quad-word using an X4 memory organization, an exemplary DIMM may include nine 4 bit wide memory chips located on one side of the DIMM and nine 4 bit wide memory chips located on the opposite side of the DIMM. Conversely, to produce a 72 bit quad-word using an X8 memory organization, an exemplary DIMM may include nine 8 bit wide memory chips located on a single side of the DIMM. The memory chips on each DIMM are typically selected from one or more DRAM technologies, such as synchronous DRAM, double data rate SDRAM, direct-RAM BUS, and synclink DRAM.
The host/data controller 16, 18 is typically coupled to one or more bridges 28A-28C via a suitable bus 27. The opposite side of each bridge 28A-28C is coupled to a respective bus 30A-30C, and a plurality of peripheral devices 42A and B, 44A and B, and 46A and B may be coupled to the respective buses 30A, 30B, and 30C. The bridges 28A-28C may be any of a variety of suitable types, such as PCI, PCI-X, EISA, AGP, etc.
The host controller 16 also includes a processor controller PCON for each of the processor and I/O buses 14A, 14B, and 27. For simplicity, the processor controller corresponding to the processor bus 14A may be designated as "PCON0." The processor controller corresponding to the processor bus 14B may be designated as "PCON1." The processor controller corresponding to the I/O bus 27 may be designated as "PCON2." Essentially, each processor controller PCON0-PCON2 serves the same function which is to connect a respective bus, which is external to the host controller 16 (i.e., processor bus 14A and 14B and I/O bus 27), to the internal blocks of the host controller 16. Thus, the processor controllers PCON0-PCON2 facilitate the interface from the host controller 16 to each of the buses 14A, 14B, and 27. In an alternate embodiment, a single processor controller PCON may serve as the interface for all of the system buses 14A, 14B, and 27. Further, additional processor controllers (e.g., PCON3 and PCON4) may be designated for a system comprising additional processor or I/O buses. Any number of specific designs for the processor controller PCON may be implemented in accordance with the bus configurations described herein, as can be appreciated by those skilled in the art.
The host controller 16 also includes a tag controller TCON. The tag controller TCON maintains coherency and request cycle ordering in the cache memory 33. "Cache coherence" refers to a protocol for managing the caches in a multiprocessor system, such as the system 10, so that no data is lost or over-written before the data is transferred from the cache memory 33 to a requesting or target device. Because frequently-accessed data may be stored in the cache memory 33, the agent requesting data stored in memory should be able to identify which area of the memory 26 (cache or non-cache) it should access to retrieve the required information as efficiently as possible. A "tag RAM" is an area that identifies which data from the main memory 26 is currently stored in each cache line. The values stored in the tag RAM determine whether the actual data can be retrieved quickly from the cache 33 or whether the requesting device should access the slower DRAM portion of the main memory 26. Thus, the tag controller TCON maintains coherency and controls access to the tag RAM. Any number of specific designs for a tag controller TCON for maintaining cache coherency may be implemented in accordance with the bus configurations described herein, as can be appreciated by those skilled in the art.
Turning now to
Because high-cycle latency associated with the processing of requests generally reduces system efficiency, the queuing structures and associated processing mechanisms are generally configured to optimize the request processing speed. The front end 42 described herein processes the requests by implementing a complex queuing structure which allows for out-of-order execution of requests and handles multiple entries loading from the various buses 14A, 14B, and 27 in a single clock period. The master memory controller MCON also provides for the retention of proper priority levels for outstanding requests to maintain request ordering from the oldest to the newest requests. Further, by minimizing the number of system stalls associated with processing the requests, the cycle time is decreased and the system 10 is advantageously more efficient.
The control interface block 56 prepares incoming requests to be transferred to the MCON control block 46. Each request or transaction is registered and delivered to the MCON control block 46 upon assertion of a control block select signal in the request received from one of the PCON interfaces 52A-52C. The control interface block 56 delivers transactions from the PCON interfaces 52A-52C to the MCON control block 46, as well as transactions initiated from the RAM initialize, rebuild and verify (IRV) queue 58 which is implemented during a hot-plug operation. During a hot-plug operation, a memory segment 24A-24E may be replaced. Once the corresponding memory cartridge 25A-25E is re-inserted into the system 10, the memory segment 24A-24E is generally powered-up and initialized. After initializing the memory segment 24A-24E, the data that should be stored in the memory segment 24A-24E is rebuilt using the remaining memory segments 24A-24E. Once the data is re-written to the corresponding memory segment 24A-24E, the data is re-read or verified. The IRV queue 58 maintains a structured order during the initialize, rebuild, and verify operation of the associated requests implemented during a hot-plug procedure.
As will be discussed further herein, the various queues in the MCON front end 42 initiate various requests to pass data to the MCON back end 44 for processing. However, when no queues are initiating such requests, a bypass block 60 may be provided such that certain incoming transactions, such as READ transactions, may be forwarded directly to the MCON back end block 44 prior to being saved in the queues. Thus, if each of the request signals for each of the queues in the MCON front end 42 are de-asserted, a transaction, such as a READ request, may be passed directly to the MCON back end 44 through the bypass block 60. Conversely, if any of the queues contain unprocessed requests, the bypass block 60 may be de-asserted such that incoming requests are delivered to a respective queue for proper ordering before being delivered to the MCON back end 44.
As previously discussed, the MCON front end 42 comprises a plurality of queues such as an IRV queue 58, a READ queue 62, a WRITE queue 64, an Implicit WriteBack (IWB) queue 66, and a Tag-castout WriteBack (TWB) queue 68. Generally speaking each of the queues in the MCON front end 42 maintains an ordered list of a corresponding request type. Each of the queues will be described generally and then an exemplary embodiment of the READ queue 62 will be further described with reference to FIG. 5. Each of the techniques described herein will be described with reference to the READ queue 62. However, as can be appreciated by those skilled in the art, the techniques described herein with reference to
The READ queue 62 maintains an ordered list of the READ requests delivered from the processor controllers PCON0-PCON2. Generally, the READ queue 62 stores and tracks READ requests initiated from an agent on one of the processor buses 14A and 14B or the I/O bus 27 and directed to one of the memory controllers 20A-20E. The READ queue 62 may include a READ queue depth checker 70 to monitor the combined depth of the READ sub-queues 62 a-c. The READ queue depth checker 70 monitors the READ sub-queues 62 a-c to insure that the READ sub-queues 62 a-c do not exceed some threshold number of entries. READ requests are optimized to request the memory system 26 immediately. Many of the READ requests eventually will be retried, however, and in these cases the data returned from the memory system 26 will be ignored. If the system is saturated with READ requests, this "head-start" on fetching READ data is turned off by requiring each transaction to wait for a Read Ready signal. This allows more access to the memory system 26 by those transactions which will not be retried. The READ queue 62will be discussed further with reference to FIG. 5.
The WRITE queue 64 maintains an ordered list of the WRITE requests delivered from the processor controllers PCON0-PCON2. Generally, the WRITE queue 64 tracks the entries that are WRITE transactions which are bound for the memory controllers 20A-20E. The WRITE queue 64 may include a plurality of WRITE sub-queues 64 a-c, each sub-queue corresponding to a unique processor controller PCON0-PCON2. Further, the WRITE queue 64 may include a WRITE arbiter (not shown) which determines which of the requests from the various WRITE sub-queues 64 a-c will be sent to the MCON back end 44 for processing. The WRITE arbiter may for instance, receive a sub-queue depth indicator from each of WRITE the sub-queues 64 a-c and prioritize a request from the WRITE sub-queue 64 a-c containing the most requests. Further, the WRITE arbiter may perform a similar function to the READ queue depth counter 70 in that it may facilitate the flushing of any of the WRITE sub-queues 64 a-c once they reach some predetermined threshold which may slow system performance.
The MCON front end 42 may include various other queues depending on the system configuration. For example, the present exemplary embodiment includes an IRV queue 58, an IWB queue 66 and a TWB queue 68. As previously explained, the IRV queue 58 generally includes requests associated with initializing, rebuilding, and verifying memory segments 24A-24E after a hot-plug procedure. When a transaction is received from a CPU 12A-12H, the address is hashed into a tag index by the tag controller TCON (FIG. 2). The cache state is stored in the cache memory 33 based on the tag index. If the incoming transaction's tag index collides with an existing valid tag entry in that cache memory 33, and that existing state is owned, then a Tag-castout WriteBack (TWB) transaction is generated to snoop the CPU 12A-12H which had the tag in the owned state. The requesting information for these TWB snoop transactions are stored in the MCON front end TWB queues 68. If the CPU 12A-12H had not modified the data, then the snoop response will indicate an unmodified hit. In this case, the request stored in the TWB queues 68 is discarded. If the CPU 12A-12H had modified the data, it will respond by writing this data back to the memory 26. In this case, the transaction is moved from the TWB queues 68 to the Implicit WriteBack (IWB) queues 66 in the MCON front end 42.
If a transaction is stored in the READ queues 62 and the tag controller TCON determines that the address is owned on another processor bus 14A or 14B, the tag controller TCON will snoop the CPUs 12A-12H on that bus 14A or 14B. If a CPU 12A-12H had modified the data at that address, it will write this data back to the memory 26. In this case, the READ transaction becomes a WRITE to the system memory 26. Consequently, the entry in the READ queues 62 for this transaction is transferred to the IWB queues 66. Similarly, a WRITE request to the system memory 26 may also be modified by another CPU 12A-12H. In this instance, the entry in the WRITE queues 64 for this transaction is copied to the IWB queues 66.
A variety of information corresponding to a request may be stored in a respective field in the queue entry pool 72 which may be referenced by the QEP index. Fields such as a valid entry field, entry ready field, entry sent field, entry pending field, and entry address may be stored in the QEP 72 for each request, for instance. However, as can be appreciated by those skilled in the art, other desirable information may be retained and stored in the QEP 72, as well.
In the present embodiment, the valid entry field is set when a request is written to the queue entry pool 72. Once an entry is written to the QEP 72, the MCON control block 46 sets the valid entry bit (i.e., stores a "1") for the corresponding request in the QEP 72. The valid entry bit indicates that a particular slot in the QEP 72 contains a request waiting to be processed. Once the twit entry is retired, the bit may be cleared and another request can be stored in the corresponding slot of the QEP 72.
An entry ready field may be stored in the QEP 72 to indicate whether a transaction is ready to be delivered to the MCON back end 44. Thus, once the entry ready bit is set by the MCON control block 46, the request is ready to be sent to the MCON back end 44 for processing. Further, if the READ queue depth checker 70 sends a signal to the queue entry pool 72 indicating that the combined depths of the READ sub-queues 62 a-62 c are above a set threshold, the entry ready bit waits for a read ready signal from the MCON control block 46 before the bit is set, although the rest of the entry is immediately stored in the queue entry pool 72.
The entry sent field is used to indicate that a particular entry has been received at a corresponding location. The entry sent bit is set when either the entry receives an acknowledgement signal from the MCON back end 44 or an implicit writeback request from the MCON control block 46. When an entry is created in the queue entry pool 72, the entry sent bit is cleared. If a re-read request is received from the MCON control block 46 corresponding to an implicit writeback for this particular entry, the entry sent field is cleared thereby allowing the entry to be re-sent to the MCON back end 44 for eventual transmission to the host controller 16.
The entry pending field is set when the MCON back end request is sampled as asserted or when the incoming entry is used as an automatic arbitration winner. The entry pending bit is cleared when the entry sent bit is set. By setting the entry pending bit, the priority encoder 74 (which will be discussed further below) ignores the entry and thus prioritizes other requests in the queue entry pool 72 ahead of the request with the entry pending bit set.
Generally speaking, the fields stored for each request in the QEP 72 may create a state machine providing a road map for the processing of the requests in the QEP 72. The specific fields and the sequence of execution dictated by these fields may be specific and unique for a particular system design. For this particular application, it is enough to know that various information delivered with each request and with corresponding control signals are stored in the queue entry pool 72 such that they may be interpreted and used by the other components of the READ sub-queue 62 a to prioritize the processing of the requests in the queue entry pool 72.
An exemplary state diagram is illustrated in FIG. 6. The State Machine Flags in the QEP 72 can then also be considered to be a queue of state machines. Initially, a state value is in the "Invalid" state 80. If either a Read Done signal or a Retry signal arrives for the transaction, then the state value returns to this state no matter what state it had been in. The Read Queue Select signal asserts when a new transaction arrives. The state will transition from the Invalid state 80 to one of several other states depending on the state of other signals, as described below.
If the incoming transaction is a Zero Byte Snoop, then all data that should be sent has already been sent (i.e. none). As a result, the state value is set to the "Sent" state 88. These transactions are used by a CPU 12A-12H to force a second CPU 12A-12H to mark any cacheline containing data for the specified address as invalid. If that second CPU 12A-12H had previously modified the data associated with that address, then the CPU 12A-12H will execute an Explicit WriteBack (EWB) transaction to write the data back to memory. It is the address rather than the data that is important in the Zero Byte Snoop transactions.
If the incoming transaction is not a Zero Byte Snoop, but there are no entries in the queue that have not already been sent to the MCON back end 44, then this incoming transaction is automatically the priority winner. In this situation, arbitration may be bypassed and a Take Incoming signal is asserted by the priority encoder 74. In this case, the state value goes from the Invalid state 80 to the "Pending" state 86.
If the incoming transaction is not a Zero Byte Snoop or an automatic priority winner, and a Read Ready Required signal is not asserted, then the transaction need not wait any longer and is delivered to the MCON back end 44 at the next opportunity. The state value goes from the Invalid state 80 directly to the "Ready" state 84.
If the state value is in the Valid state 82, it waits in the Valid state 82 until the Read Ready signal is asserted for this transaction. When this signal is asserted, the state value transitions from the Valid state 82 to the Ready state 84. If, however, an IWB Request signal arrives for a transaction in this queue, then the transaction is moved from this queue to the IWB Queues 66. Since it has been moved, the queue no longer needs to send the request. The state value transitions to the Sent state immediately insteady of following the usual path discussed above. The IWB Request can be initiated from any of the IWB Sources.
Once the entry is in the Ready state 84, the priority encoder 74 (
Once the entry is in the Pending state 86, it will no longer be considered in the arbitration of the priority encoder 74. The arbitrator in the MCON back end 74 determines which entry to send next, but waits until the current entry exits the Pending state 86 before selecting the new winner. The state value remains in the Pending state 86 as long as the transaction is being sent to the MCON back end 44. Once the MCON back end 44 acknowledges receipt of the transaction, the state value transitions to the Sent state 88. However, as previously described, with reference to the valid state 82 above, an IWB Request will transition the entry to the Sent state 88 without waiting for an acknowledge signal. In this instance, the priority encoder 74 will also select the next priority winner without waiting for the acknowledge signal. In the present embodiment, this is the only case where a pending request need not wait for an acknowledge signal.
The state value will remain in the Sent state 88 until the above mentioned Read Done signal arrives. At that time, the state value returns to the Invalid state 80. If, however, a Read Ready Request signal arrives for this transaction, then the state value is sent back to the Ready state 84 to be sent once again. As previously discussed, the various states and flags, which cause the transition among the states, may vary depending on specific system designs. Accordingly, the state diagram discussed with reference to
Returning to
The registers in the index shifter 76 include a multiplexor which can either hold current data or capture data from the previous register, or force the register to point to an invalid entry in the QEP 72. A register will capture data from the previous register if the valid entry flag is cleared for the current entry or if the entry following the current entry register is also capturing data from its previous register (i.e., the current register). This collapses the lowest (closest to the tail) invalid slot and simultaneously creates an available slot at the head by pointing the head slot to an invalid QEP entry. Similarly, if an entry is being retired, as it becomes invalid it will collapse if possible. Since the multiplexor in the index shifter 76 only points to its nearest upstream neighbor, only one available slot can be moved to the head on any clock cycle. The shifting operation guarantees that if an entry anywhere in the index shifter 76 points to an invalid QEP slot, then each index shifter slot between the available one and the head move immediately toward the tail. This leaves an available slot at the head to receive a new entry regardless of where the available slot was before the move. If more than one slot is available at any time, then each of the index shifter slots between the available one and the head immediately move toward the tail, including any other slots which may also be available. This leaves an available slot at the head to receive a new entry regardless of where the collapsed available slot was before the move. The other available slot will then be collapsed in turn, once per clock, beginning with the next closest available slot to the tail. A register will be forced to point to an invalid entry when the data it contains is being retired and it is not shifting, or when the previous register's entry is being retired and is shifting. This process keeps a re-used transaction identification from aliasing as the older transaction which had been retired but had not yet shifted fully out of the shifter.
The priority encoder 74 determines which READ request stored in the QEP 72 to send to the MCON back end 44 by checking the flag states of the QEP 72 sorted in the order specified by the indicies in the index shifter 76. The flag MUX 78 is used to perform the sorting. The selected index number is returned to the QEP 72 which multiplexes that entry onto the bus to send the entry to the MCON back end 44. If any such entry is chosen, the priority encoder 74 also sends a corresponding request signal to the MCON back end 44. Had an incoming transaction won immediate access to the MCON back end 44 via the bypass block 60, the priority encoder 74 will take a "hand-off" to maintain the request to the MCON back end 44 until the normal path through the READ queue 62 is established.back end The send ready bus from the flag MUX 78 is used to determine when an entry is ready to be sent. The oldest entry which is ready to be sent has the highest priority. As previously described, the oldest entry ready to be sent is determined by its position in the index shifter 76. The index closest to the head of the index shifter 76 and with a send ready flag set is selected as the outgoing entries index. Once the values of the index of the QEP entry and the READ request are determined, they are locked into a register until the cycle completes. The cycle completes when the MCON back end 44 sends an acknowledge signal to the READ sub-queue 62 a, or if the QEP signals associated with the current entry are no longer valid. The MCON back end 44 sends an acknowledge signal in reference to the information it sampled on the previous clock. Thus the request and index delayed one clock cycle with reference to the acknowledge signal to ensure they all refer to the same clock cycle. When the current entry being sent to the MCON back end 44 is an implicit writeback, a new arbitration occurs to get the next oldest entry that is ready to be sent. This arbitration occurs without waiting for an acknowledgement signal from the MCON back end 44. As previously stated, this is the only case where a pending request need not wait for an acknowledgement signal from the MCON back end 44.
Other QEP 72 bits may be reserved for other flags such as the entry ready flag which may be stored in QEP bit 1, the entry sent flag which may be stored in QEP bit 2, and the entry pending flag which may be stored in QEP bit 3, for example. As previously described, the settings of each of these bits which corresponds to a particular request provide the priority encoder 74 with the necessary information to process the request from the QEP 72 in a desirable order. This particular scheme provides for out-of-order processing of requests. That is to say, rather than processing the requests in the order in which they are received, the state diagram described with reference to
When an entry is stored in the QEP 72, the entry index corresponding to the storage location in the QEP 72 is also delivered to the index shifter 76 via path 92. The index shifter 76 includes as many registers as there are entry slots in the queue entry pool 72. In the present example, there are four entry slots 0-3. Each entry slot has a corresponding register 76A-76D in the index shifter 76. Because the requests in the QEP 72 remain in the slot in which they were placed until the request is retired, it is the corresponding index which is stored in the index shifter 76 in a particular register 76A-76D which shifts and dictates the order of request processing. The index stored in the index shifter 76 retains information corresponding to the particular slot in which a request is stored in the queue entry pool 72. Thus, if the request corresponding to the index stored in the register 76C is processed, each of the indices stored in registers 76B and 76A will shift up one register in the index shifter 76 on a respective clock cycle. Advantageously, since the registers 76A-76D in the index shifter 76 only retain location information (i.e., the index of a given request) the registers need only be configured to provide enough storage for a corresponding index. In the present example, where the queue entry pool 72 only comprises four entry slots, each register 76A-76D only needs to include enough storage space for two bits to store each binary index 00, 01, 10, or 11. For a QEP 72 with 16 entry slots, for example, 16 four-bit registers 76A-76D may be implemented. As previously discussed, the selection of the request by the priority encoder 74 is dictated by the state of the flags for each request, as dictated by the invalid and enable rules illustrated in the state diagram in FIG. 6.
The flag multiplexor 78 may include a plurality of multiplexors 78A-78D, each corresponding to an entry slot in the QEP 72. Each multiplexor 78A-78D receives a corresponding input signal from the QEP 72 and the index shifter 76. Each flag multiplexor 78A-78D produces an output to the priority encoder 74. Based on the flag settings of each request and the position of the corresponding index in the index shifter 76, the request is finally delivered to the MCON back end 44 through a multiplexor 98. Alternatively, the request may be reassigned to the IWB queues 66, as described above. The request may be delivered to the IWB queues 66 through the multiplexor 100.
By using the index shifter 76 and the configuration described with reference to
An alternate configuration of the present READ sub-queue implements a similar technique. However, instead of storing and shifting the index for a particular request to allow for out-of-order processing, the queue entries themselves may be stored in a shift register. In this case, the entries can still be retired out-of-order. Other than retiring the oldest entry and shifting the rest down in the shift register, the shift register may retire entries in the middle as they become invalid and shift each of the entries above the oldest invalid entry. This does not effect the valid entries below the invalid entry. The oldest entries in the shift register then have the highest priority regardless of the out-of-order execution. Disadvantageously, however each register in the shift register must include additional storage capacity since the entire entry is stored and shifted. Further, the content of the queue may be modified while the corresponding entry is in the queues. Without fixing the position of the data, tracking the location of the data may be difficult if modification of the data is necessary.
Still another alternative embodiment involves implementing a masking structure in the place of the index shifter 76 and flag MUX 78. A queue, such as the read sub-queue 62A may be implemented as a circular first-in, first-out (FIFO) queue. A mask which is twice as wide as the FIFO may be constructed to properly prioritize out of order entries in the queue 62A. The mask value is determined by the position of the current output pointer. For an output pointer point to an entry number N, the first half of the mask contains N "0" bits. Each of the remaining bits are filled with a logical "1." The second half of the mask contains N "1" bits with each of the remaining bits filled with "0." Thus, the second half of the mask entry "wraps" to the same entry as the first half. As the output pointer progresses, previously processed entries are pushed to the lowest priority in favor of the closest upcoming entries.
Regardless of whether the index shifter, entry shifter, or mask is incorporated, the present embodiments handle a complex queuing structure which requires out-of-order operation and multiple entries loading in a single clock period. Proper priority level is maintained for all outstanding cycles such that the oldest entry will be processed first when it is ready. Advantageously, these techniques reduce stalls which would normally be associated with systems which do not permit out-of-order processing of requests. The present system is thereby more efficient than prior systems.
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
|Cited Patent
|Filing date
|Publication date
|Dec 6, 1984
|Jul 21, 1987
|American Telephone & Telegraph Co., At&T Bell Lab.
|Queue administration method and apparatus
|Aug 8, 1989
|Dec 8, 1992
|Bull S.A.
|System having constant number of total input and output shift registers stages for each processor to access different memory modules
|Dec 17, 1991
|May 17, 1994
|Jones Craig S
|Disk drive array with efficient background rebuilding
|May 8, 1992
|Jul 19, 1994
|Compaq Computer Corporation
|Error correcting code technique for improving reliablility of a disk array
|Mar 23, 1993
|Nov 22, 1994
|Eclipse Technologies, Inc.
|Fault tolerant hard disk array controller
|Mar 16, 1995
|Sep 23, 1997
|Apple Computer, Inc.
|Method and apparatus for atomically accessing a queue in a memory structure where LIFO is converted to FIFO
|Sep 30, 1997
|Aug 1, 2000
|Compaq Computer Corporation
|Installation and removal of components of a computer
|Sep 30, 1997
|Apr 24, 2001
|Compaq Computer Corporation
|Fault tolerant memory
|Jan 19, 2001
|Mar 12, 2002
|Compaq Information Technologies Group, Lp
|System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
|Jul 9, 2002
|Sep 30, 2003
|Broadcom Corporation
|Out of order associative queue in two clock domains
|Apr 7, 1999
|Oct 14, 2003
|Nokia Corporation
|Method and apparatus for avoiding packet reordering in multiple-class, multiple-priority networks using a queue
|Jul 21, 2000
|Nov 4, 2003
|Silicon Integrated Systems Corporation
|Method and apparatus for controlling order dependency of items in a multiple FIFO queue structure
|Sep 6, 2001
|Sep 19, 2002
|Tai Quan
|Method of synchronizing arbiters within a hierarchical computer system
|Title not available
|Citing Patent
|Filing date
|Publication date
|Dec 6, 2001
|May 9, 2006
|Sun Microsystems, Inc.
|Method and apparatus for arbitrating master-slave transactions
|Feb 24, 2005
|Sep 25, 2007
|International Business Machines Corporation
|Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability
|Feb 24, 2005
|Sep 25, 2007
|International Business Machines Corporation
|Pipeline bit handling circuit and method for a bus bridge
|Feb 24, 2005
|Feb 12, 2008
|International Business Machines Corporation
|Transaction flow control mechanism for a bus bridge
|Feb 24, 2005
|Dec 23, 2008
|International Business Machines Corporation
|Computer system bus bridge
|Jun 23, 2005
|Apr 28, 2009
|International Business Machines Corporation
|Method and apparatus to launch write queue read data in a microprocessor recovery unit
|Aug 15, 2004
|Jun 23, 2009
|International Business Machines Corporation
|Increased computer peripheral throughput by using data available withholding
|Jan 27, 2009
|Oct 13, 2009
|International Business Machines Corporation
|Method and apparatus to launch write queue read data in a microprocessor recovery unit
|Dec 23, 2003
|Oct 13, 2009
|Unisys Corporation
|Programmable request handling system and method
|Aug 11, 2004
|Jul 6, 2010
|Hitachi, Ltd.
|Input output control apparatus with a plurality of ports and single protocol processing circuit
|Aug 20, 2008
|Jul 13, 2010
|International Business Machines Corporation
|Computer system bus bridge
|May 20, 2010
|Jan 3, 2012
|Hitachi, Ltd.
|Input output control apparatus with a plurality of ports and single protocol processing circuit
|Jun 9, 2008
|Mar 27, 2012
|Emulex Design & Manufacturing Corporation
|Method for re-sequencing commands and data between a master and target devices utilizing parallel processing
|Apr 5, 2011
|Jun 12, 2012
|Kabushiki Kaisha Toshiba
|Semiconductor memory device
|Sep 30, 2008
|May 7, 2013
|International Business Machines Corporation
|Main processing element for delegating virtualized control threads controlling clock speed and power consumption to groups of sub-processing elements in a system such that a group of sub-processing elements can be designated as pseudo main processing element
|Feb 1, 2013
|Apr 28, 2015
|International Business Machines Corporation
|Managing out-of-order memory command execution from multiple queues while maintaining data coherency
|Sep 27, 2013
|May 5, 2015
|International Business Machines Corporation
|Managing out-of-order memory command execution from multiple queues while maintaining data coherency
|Apr 7, 2015
|Oct 20, 2015
|International Business Machines Corporation
|Managing out-of-order memory command execution from multiple queues while maintaining data coherency
|Aug 3, 2015
|Apr 19, 2016
|International Business Machines Corporation
|Managing out-of-order memory command execution from multiple queues while maintaining data coherency
|May 19, 2014
|Jun 7, 2016
|International Business Machines Corporation
|Virtualization across physical partitions of a multi-core processor (MCP)
|Dec 21, 2012
|Jun 28, 2016
|Foundation Of Soongsil University-Industry Cooperation
|Semiconductor chip and method of controlling memory
|Dec 6, 2001
|Jun 12, 2003
|Protip Roy
|Method and apparatus for arbitrating master-slave transactions
|Aug 15, 2004
|Jan 20, 2005
|Berg Thomas B.
|Increased computer peripheral throughput by using data available withholding
|Aug 11, 2004
|Mar 17, 2005
|Takashi Tamura
|Input output control apparatus
|Feb 24, 2005
|Aug 24, 2006
|International Business Machines Corportion
|Computer system bus bridge
|Feb 24, 2005
|Aug 24, 2006
|International Business Machines Corporation
|Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer abvailability
|Feb 24, 2005
|Aug 24, 2006
|International Business Machines Corporation
|Transaction flow control mechanism for a bus bridge
|Jun 23, 2005
|Jan 11, 2007
|Mack Michael J
|Method and apparatus to launch write queue read data in a microprocessor recovery unit
|Sep 20, 2007
|May 15, 2008
|Drive Sentry Inc.
|System and method to secure a computer system by selective control of write access to a data storage medium
|Aug 20, 2008
|Dec 11, 2008
|International Business Machines Corporation
|Computer system bus bridge
|Jun 9, 2008
|Dec 10, 2009
|Emulex Design & Manufacturing Corporation
|Method for adopting sequential processing from a parallel processing architecture
|Sep 30, 2008
|Apr 1, 2010
|Duvalsaint Karl J
|Delegated virtualization in a multi-core processor (mcp)
|Apr 5, 2011
|Jul 28, 2011
|Kabushiki Kaisha Toshiba
|Semiconductor memory device
|Dec 21, 2012
|Jul 18, 2013
|Foundation Of Soongsil University-Industry Cooperation
|Semiconductor chip and method of controlling memory
|U.S. Classification
|710/5, 710/55, 710/310, 710/54, 711/154, 711/159, 710/52, 711/109
|International Classification
|Cooperative Classification
|European Classification
|Nov 15, 2001
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Broccoli Casserole
Total Time
Prep 10 mins
Cook 30 mins
This is a dish that my mom made for me all the time when I was a kid. I am sure it must have been a Campbell's Soup Recipe.
Ingredients Nutrition
- 20 ounces frozen broccoli
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- 1 cup mayonnaise
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- 1⁄2 cup grated cheddar cheese
- 4 slices bread
- Put Broccoli in a 9X13" pan.
- Mix Turkey, Soup, Mayonnaise and Lemon Juice. Layer on top of the Broccoli.
- Cut the slices of bread into cubes. Layer on top of the above Turkey Mixture. Then cover with Grated Cheese.
- Bake at 350 degrees for 25-30 minutes.


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veri.live magazine issue 6
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text: The Probers - Mad At the World ep (1982, Hyperion) • Pop New Wave Dance • Year : 0 • On demand! (album available 128-320kbs)* 0 Label Facebook Twitter Google+ Pinterest Hide/Show Album Info I may not have of a wealth of background info to regale you with regarding this seven-piece Rhode Island set, but I do know a rock solid power pop disk when I hear one, and The Probers near-30 year old Mad at the World ep is the cats meow. Plenty of rollicking fun here, and very much of the era I might add. "Betsy," "Tell Me," and "Take It Like a Man" recall the finest work of their (slightly) more renown contemporaries, The A's and Donnie Iris, and while we're at, thrown in a dash of candy-coated pop sheen a la the Rubinoos. It's seems someone has posted a non-LP Probers track via a makeshift video on , and as a bonus you can glean a little bit more about the band in the rather lengthy comments section.01. And Violets Are Blue02. Betsy03. Mad at the World04. Anonymous Affair05. Tell Me06. Take It Like a Manhttp://rapidshare.com/files/455940719/probers.rar #tags The album code is : ODI179073 You may also like ... Prime Suspect - Prime Suspect (2010) Prime ... Donnie - The Colored Section CD - 2002 Donnie - ... S.O.S. Band - S.O.S. Band III (1982) S.O.S. Band ... Iris - Discografie (1977-2007) Iris - ... Hyperion - Drop Psychosis (2008) Hyperion - ... Thalisha - Ear Candy Thalisha -


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- Worldwide Rank #34,748,459
- Follower/Following Ratio 1.54
- Daily New Followers 0
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Hurricane Matthew's Impact On The UGA - South Carolina Game This Saturday; Lesson Learned?For the second year in a row, a hurricane will impact one of the two major universities in the state of South Carolina's biggest home game. Let's stop right here and acknowledge that the storm's impact on a ballgame is the...
John Fricke: Where College Football Stands Right Now (Nov 15, 2015)This wild, crazy, incredible season just keeps getting better (or worse, depending on your personal viewpoint). A few thoughts on where we stand heading to week-12...
This Week In College Football: Arkansas' 'Cupcake Game' Karma & The State Of The SECArkansas' head coach ended up with his foot in his mouth this past weekend, and the SEC has some early scares.
Top 5 "Next To The Best" College Basketball Teams As Of Right Now
Top 10 College Basketball Teams In Week 9
2014 College Football Countdown: Notre Dame Fighting Irish
Top 5 Greatest Team Rivalries In SportsIsn't it better when the teams hate each other? Here are the top 5 team rivalries in sports.


text:
Hokkaido Washida was Asahikawa District Court Judge (Koichi Sato), the old significant other, Saeko turned into a respondent in stimulants occurrence (Machiko Ono) and the gathering in court. However just that has put his better half and kids in Tokyo, it would restore the relationship. Be that as it may, it hurt profoundly lost her after the six months. Later, from 25 years, Washida quit the judge, his better half and kids and goodbye, had sent the everyday forlorn as a court-selected safeguard legal advisor in Kushiro.
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text:
It's inauguration day
As I'm sure you already know, today is the day Barack Obama becomes the 44th President of the United States. The festivities continue; the actual swearing-in ceremony is at 8:30 a.m. (and I checked in with the folks at Comcast, who were slated to do service-interruption-making work this week – they said they'll hold off on that this morning).
Anyway, you can get inauguration info and photos right here; we'll get the skinny on local happenings and post it right here.


text:
In-Depth Trends
Covers Preview -
Derek Carr's spirited play during the Oakland Raiders' six-game winning streak has placed the third-year quarterback in the lively discussion for NFL MVP honors. Carr has thrown seven touchdown passes over his last three games and 12 during the winning streak as the first-place Raiders head into an AFC West showdown with the host Kansas City Chiefs on Thursday night.
Continue to the full preview.
See All RankingsPower Ratings compute offensive and defensive statistics into one number for each team, while accounting for factors like recent performances and strength of schedule. Power Ratings can be used as a baseline for relative moneyline index to compare current or future match-ups between two teams. The relative moneyline does not account for non-statistical factors like home-ice advantage, recent injuries, game time decisions, rivalries, and publicity.


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Music Gear News
Webber penning music with Gary Barlow
According to an interview in The Sun, the Joseph and His Amazing Technicolor Dreamcoat composer is on music duties on one track, with famed songwriter Barlow penning words.
"I've come up with the tune this time and he's already emailed me with lyrics this morning. It hasn't got a title yet," Lloyd Webber said.
And he suggested that the musical collaboration would continue somewhere nice and warm, saying: "Gary's going to be down in Majorca this summer and so will I, so we'll get together and something will come out of it."
It comes after Lloyd Webber and Barlow penned Sing, a song designed to mark the recent Diamond Jubilee.
Lloyd-Webber is currently taking part in an ITV1 programme that revolves around another of his musicals, Jesus Christ Superstar.
It aims to discover the man who will play Jesus in an upcoming production of the show. Spice Girl Mel C, who will star in Jesus Christ Superstar's new version, too, is one of the judges.
Published by KT.Posted on 10 Jul 2012 12:06 to category : Music News
Related Music News
Featuring a whole host of professional grade components, Antelope Audio's Zen Studio is available now at an incredibly discounted price.
Chief executive of UK Music expects difficulties in the near future for UK artists wishing to work in the USA
Ticket touters have been routinely slammed by artists and promoters for quite some time. Now, the government are to host an evidence session in which ticket touters and secondary tickets websites will be investigated.
Shure announce their 'Call for Legends- Live Contest' in which the company search high and low for the next living music legends.
In August controversy was in the air as the Dirty Dancing stage show fired its live musicians in favour of a backing track. Now the Musicians' Union urge its members to join in the protest.
In recent times, the theft of musical instruments and gear seems to be more prevalent than ever. With this GPS guitar pedal, users can track their stolen equipment simply by logging in online on their phone or tablet.
Recent Music News
For those who want to emulate the massive tone of one of the contemporary music scene's biggest percussive heroes, the 'Spooky' signature drum is this winters must have addition to your kit
Some formats of compressed MP3 have been linked with negatively effecting individuals emotional state due to their inherent tonal characteristics
Once again Cubase continue to pave the path of innovation with Cubase Pro 9
Changing colour from its previous grey to a sleek black, the Launch Control XL's appearance has been re imagined to keep it inline with its Launch key and Launchpad counterparts.
Designed to simulate various classic amp tones, Supro's Tremolo Pedal introduces the new school to the old school
A premium belt-drive turntable that features wireless streaming, the BT-500 has been designed to extract every musical detail of your record collection


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The average cost for a Coolant Reservoir Replacement is between $137 and $186. Labor costs are estimated between $96 and $123 while parts are priced between $41 and $63. Get a personalized estimate based on your location and specific car. Estimate does not include taxes and fees.
Coolant Reservoir Replacement Cost for Honda Insight
Coolant Reservoir Replacement Estimate (National Average)
Validated estimate range for national average.
View Estimate Details
Parts & Labor Breakdown
Labor: $96 - $123
Parts: $41 - $63
Estimate does not include taxes and fees.
Best Practices
We highly recommend replacing the coolant cap when replacing the expansion tank.
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The company who brought you what you need to vape all day, now brings you our All Day Vapes!
Fried Flurry is a tasty creation based on savory fried ice cream. Fried light cinnamon sugar batter in the foreground, wrapped over a frozen vanilla bean ice cream note. As of early 2016, the staff touts this flavor as the favorite LV creation to date!
Store in a cool dry place. Shelf life is 12 months from date of manufacture
For disposal, contact your local waste management facility for proper protocol.
If spilled on skin, wash immediately. Nicotine is toxic, and may be absorbed though the skin.


text:
Super 44 Muffler on 96 Ram 5.2
Reviewed By L Gordon J (Omaha, NE) Reviewed for a 1996 Dodge Ram —8/6/2008 8:51 PM
Great muscle sound, Very deep and loud. Sounds perfect with headers. Noticable HP and mpg gains.
Reviewed By Evan H (Burke, VA) Reviewed for a 1996 Dodge Ram —11/8/2007 6:13 AM
I originally had a series 70 muffler with my flowmaster exhaust. It took a little welding, but overall the 40 series sounds amazing, and there is definitely no power drawback from going down to a smaller muffler. Great product and get service.


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Does this restaurant offer free wifi?
Is this restaurant good for brunch?
Is this restaurant good for special occasions?
Is this restaurant good for lunch?
Is this restaurant good for dinner?
Is this restaurant good for scenic view?
Does this restaurant have parking?
Does this restaurant offer valet parking?
Does this restaurant have private dining rooms?
Does this restaurant offer validated parking?
Thanks for helping!
Amazing Italian! Doesn't matter how busy this restaurant is, the quality of the food is never compromised! Not ridiculously priced. Our waitress was lovely. Will be back soon!
Had lunch here recently - specials are always good.
Pizza's or Platters and glass of wine or beer for a good price.
Have been a few times and always happy.
nice afternoon with pizza ,wine, Caesar salad, quite a good deal for hastings street,nice thin based pizza, nice spot
This is our go to place for lunch in Noosa. The Pizza is great- so fresh and delicious. The cajun chicken caesar salad is consistently one of the best salads I have ever had- the sauce is to die for and you definitely get your money's worth for adding chicken. Nachos look great, but have never tried. Seats by the...
We love setting up our chairs by the river as the sun goes down, listening to the squawking of the loorikeets as they settle down for the night and a couple of Zacharys pizzas in front of us ready to be devoured. For us, this seems to be the best of the bunch having tried them all near the river....
Yes it was a busy night but being completely ignored when trying to collect takeaway pizzas is unnecessary. Clearly did not have a system and staff were dismissive and rude. Pizza's were very good!
Nice to stand and enjoy a couple of nice cold beers whilst waiting for takeaway and were greeted by hungry families that enjoyed what we "delivered"
After a walk around Hastings Street in the centre of Noosa, our fmily decided it was a good time for lunch. Having a three year old in tow makes our choices a bit of a challenge but the wife chose Zachary's. The menu does give you a lot of choice in the way of pizzas, but we settled on the...
On returning to Noosa for our annual holiday I was surprised to find that Zachary's has moved. Not quite the same ambiance as previously, but ok and with more seating. It was a very busy night and standing in the queue we were tempted to go elsewhere. However the maitre'd was excellent and quickly got us a seat at the...
Great food, really reasonable prices and family friendly. We ate here twice on our visit to Noosa, early sittings both times to accommodate our little one. My husband thought the carbonara on our first visit was the best he'd ever had, although it was nowhere near as good the second time. Kids bolognese was rich and tasty. Lovely open windows...
Own or manage this property? Claim your listing for free to respond to reviews, update your profile and much more.


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Saw this posted over in August 12. A few of those are truly strange and/or creepy!
Saw this posted over in August 12. A few of those are truly strange and/or creepy!
lol. I am hoping to get pics done this time. Had one with my first, but then never got around to it with the other 2. Gotta say, I WONT be going with any of those ideas though lol
Those made me L O L.. haha
Some of them seem like a good "idea" haha and some are kinda funnyish like i'd laugh if my friends sent them to me, while others are just..wrong.. hahaha
Kinda funny the ones with the naked dads....Makes me think why is this so weird?? Theres a naked mom so I guess it might be weird if the dad was clothed...but its so weird that hes naked.....hahaha...
I have to say the one about she used to be so good at hide and seek made me laugh... the rest, we're um..... Yeah. I can't even bring myself to say interesting.
Oh wow now thats so funny!!!!!!! I def laughed out loud at some of those for sure!!


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Doctor insights on:
Synovial Fluid Injections
Is a synthetic synovial fluid injection in the hip joints that have osteoarthritis in them any good to have to relieve the pain?
Hip osteoarthritis: There are studies to support that viscosupplementation for osteoarthritis of the hip can have the same efficacy as viscosupplementation for the knee. However, patients respond differently and one person may experience greater pain relief than another. ...Read more
Synovial Fluid (Definition)
The lining of your joints called synovium produces fluid that assists joint lubrication/nourishment. If a joint becomes injured or inflamed then excessive fluid can be produced causing joint swelling which you should check out ...Read more
Pimple-like eruption on my second toe - synovial fluid? Previously treated with steroid injection - it's back - treatment?
Sounds like: a mucous cyst. These are small cysts over a joint which is filled with synovial or joint fluid. Steroid injections may help. In recurring or painful ones, sometimes surgery which includes addressing the affected joint is necessary. See Podiatrist for examination and discussion. ...Read moreSee 2 more doctor answers
If synovial fluid analysis shows "klebsiella species" is this really bad?
Not good: Iv the specimen was obtained sterile, you have a joint infection. Klebsiella can be drug resistant, but often is not. It is treatable, but you may be on antibiotics for 6-8 weeks. ...Read more
Why would a person need a synovial fluid fungal culture test?
Septic arthritis: A fungal culture would be performed on the fluid collected from a joint if the joint was infected and not responding to typical antibiotic therapy. Joint infections caused by fungal infections are not common. ...Read more
What does a surgical puncture of the joint space to remove synovial fluid for analysis mean?
Taking fluid out of: A joint as a sample, to analyze it. It usually is done in the office with a needle or can be done surgically through a small puncture/ incision to obtain a sample of the fluid. ...Read more
What is the best medication to increase the synovial fluid between knee joints ?
Synovial fluids : There are no medications that increase synovial fluid in knee joints. Proper hydration and plenty of fluids will be of help. ...Read moreSee 2 more doctor answers
Bf had meniscus surgery, now has synovial fluid leaking?
Synovial Fistula: A rare complication of arthroscopic surgery is a synovial fistula, where the synovial fluid of the knee leaks from the incision site. Close monitoring by the surgeon is required to make sure this is not an infection or becoming an infection. ...Read moreSee 2 more doctor answers
How long does infection of synovial fluid due to wrist injury last?
Until cured: Synovial fluid infection can destroy the joint unless treated aggressively with drainage and antibiotics. ...Read moreSee 1 more doctor answer
How painful is aspiration of synovial fluid for possible gout in hands? Is anything used for anesthesia? The possibility of this scares me.
Routine procedure: Depending on your degree of fear or anxiety, different levels of sedation may be required. A numbing anesthetic cream (EMLA) might be placed on the skin over the joint, usually 60 minutes before the procedure. In some cases, a patient receives oral or IV sedation during the aspiration. ...Read moreSee 1 more doctor answer
- Talk to a doctor live online for free
- Increase in synovial fluid
- Lack of synovial fluid
- Synovial fluid leak
- Ask a doctor a question free online
- Synovial fluid deficiency
- Synovial fluid analysis
- Too much synovial fluid
- Cell count and diff synovial fluid
- Synthetic synovial fluid injections


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|22 Avaliações
|Tipo de imóvel
|Estadia Mínima
|3 - 7 noites
Localizado em Hollywood La Villa Marquês fica a 20 minutos da praia ou do Aeroporto Fort Lauderdale. Da casa você tem acesso fácil a restaurantes e lojas, bem como muitos campos de golfe.
A propriedade é um 3 quartos, mais den / 2full banheiro casa com uma cozinha totalmente equipada (inoxidável roubar eletrodomésticos), acesso sem fio à internet, uma churrasqueira, BlueRay, lavadora e secadora, e uma piscina privada aquecida.
Há uma cama queen-size no quarto principal, uma rainha no segundo quarto, duas camas de solteiro no terceiro e um sofá-cama para duas pessoas na sala.
A casa está muito bem decorado e tem tudo que você precisa para umas férias relaxantes em família!
* Esta casa exige um mínimo de 3 noites para alugar e pode acomodar até 8 pessoas. *
This is our second home we have experienced with the same owner and property manager and once again everything went very well. The place and location is accommodating. Gorgeous and spacious home. Thank you so much Francois for making my transition to my permanent home easy and pleasurable. My grandmother enjoyed feeling like she is on vacation!!!😉. This place is a great vacation spot.
This house was conveniently located for our many outings to Ft. Lauderdale and Miami.
The house was clean, stocked, and comfortable. The outdoor pool area is great with nice foliage. The neighborhood is average.
Check in and check out were easy, and we were well instructed on use of the house. A great house at a good value.
We will consider this house again for future visits.
5 stars - excellent value for the area!
Communication was great! Check in and out process very easy.
The place was clean, and well stocked. Pleasantly surprised by how well the interior appeared and was maintained. The area doesn't appear to be very nice, but we always felt safe and the neighbor was very friendly.
The pool was so much fun for all ages 1-60.
BBQ area was nice as well.
Central AC was awesome! It cooled the house very well in the high heat.
It is close to the freeway, but the noise was only noticeable outside and only a few times. Not a nuisance at all.
Plenty of room for the 8 people that stayed on our trip.
All amenities were provided, any questions we had were answered promptly, great service. We enjoyed our stay very much!
Perfect is the only way I can describe this place. We came to the Hollywood area for my daughters wedding and rented the house for 4 adults and 4 children ages 14, 11, 2 and 9 months. This was the perfect place... The pool kept all of the older kids busy during the down time from the wedding. The crib and highchair were perfect for the 9 month old. Plenty of living space to sit and visit with company that stopped by or breakfast for all of us. All the kitchen appliances were new and worked great. Very grateful for the washer and dryer so we didn't have to pack a ton of cloths. There were plenty of towels for swimming and beach going. Thanks to who every left the beach toys and umbrella. If you rent this look in the shed in the backyard we left some coolers and added to the beach toys. Took us just a couple of days and we were able to get to the grocery store and beach with ease. Great neighborhood and the neighbors all waved and said hello.
Thanks again
We stayed at this property for 4 nights. Located about 15 min from FLL airport, on a nice quiet block. The house was impeccably clean and had modern updated furniture/appliances. The master bedroom had a large master bath with a large shower. There were 2 other decent sized bedrooms and a second full bath. The heated pool was perfect for us, always at the right temp. The backyard is great if you want to eat outdoors or just sit around near the pool. It was fully enclosed and offered a lot of privacy. The house is close to supermarkets if you want to buy food, and a short drive to the beach. Both the owner and caretaker of the property were a dream to deal with. We got quick responses to any questions that we had prior to our stay. I would not hesitate to stay here again! Highly recommend this house to anyone who does not want to stay in the super busy hotel zones. Thanks for a great stay!
|Validade da Tarifa
|por noite
|Noite (fim de semana)
|por semana
|por mês *
|Pacote ou Evento
Holiday Season
dez 17 2016 - jan 8 2017
Estadia mínima: 7 noite(s)
High season 2017
jan 29 2017 - abr 29 2017
Estadia mínima: 3 noite(s)
A partir deR$ 841
Tarifa Básica
Estadia mínima: 3 noite(s)
A partir deR$ 723
|Observações: As tarifas levam em consideração a estadia de 6 hóspedes, adicione R$ 34 por noite, por pessoa adicional
|R$ 673 + Imposto
Check-in : 3.00 PM
Check-out: 11.00 AM
smoking not allowed Inside the house
* Tarifa mensal aproximada. O valor real dependerá dos dias em que você de fato se hospedar no imóvel.


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Treat yourself to chic style and comfort with the Trotters Arianna. The smooth leather upper of this sophisticated loafer features dual side goring for a snug, flexible fit. A padded footbed offers cushioned comfort, while the durable rubber sole provides stabilizing traction.
- Soft leather upper
- Patent toe and heel panels
- Dual elastic goring for a flexible fit
- Cushioned leather footbed
- Slip-resistant rubber traction sole
Delivery and Returns
Estimated delivery date: 2 (based on standard shipping).
We offer free shipping on orders over $99, and free returns and exchanges for up to 30 days.


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Everybody's got their somewhere
If you're honestly searching for love, head to the shelter and save a pup. More love than you'd ever imagine.
I live to create and I feel it in every atom in me
Reconnected with @Cody after a century, and we're neighbors!? Dope things dope things


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Cymax Stores vs Lazboy
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Cymax StoresFurniture and Decor
Customers like
- Ease of placing order 5
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- Free shipping 2
- Shipping 2
- Liars 2
Customers don't like
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- Chair 5
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- Sales personnel 4
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Decorațiuni Ziua Recunoștinței
Low Lighting - Thanksgiving Day Tables That Are #Goals - Photos
14 Easy Ideas for DIY Thanksgiving Decor That Will Stun Your Guests
Thanksgiving turkey veggie tray. Such a cute idea! Great way to get kids to eat their veggies. Use hummus to make it #dairyfree and #vegan. From http://EatingRichly.com
14 Easy Ideas for DIY Thanksgiving Decor That Will Stun Your Guests More
Pinecone Door Decor for Thanksgiving
Log Centerpiece | 19 Creative Thanksgiving Decorations You'll Wish You'd Thought Of First
Customizable Name Cards. Free Printable!
This is an amazing Thanksgiving tablescape that you can totally create on a budget using things you have around the house.


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Driving Schools in Kingston upon Thames (Surrey)
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promotional offers we run from time to time. Simply click the "Like" below, or from our
Facebook page.
It's just that simple!
This is one of baseball's hottest new products this year. It protects and insulates bats by keeping them 32% warmer, which translates to a more reactive bat adding distance and velocity and damaging less in colder temperatures. The BAT INSULATOR is ideal for softball and baseball bats alike and was a semi-finalist for Sports Product of the Year. The 2 1/4" size fits all softball and little league bats. This unique cover is designed to protect and lengthen the life of your favorite bat. They are proudly Made in the USA.Available different colors. Make your selection above.
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Second Liners Mardi Gras Club Parade
February 11, 2017
Location: Nichols Elementary, 590 Division St, Biloxi
Phone: (228) 324-5194 or (228) 623-3511
Time: 1pm
Price: Free
This parade includes floats and bands galore. Starting at Nichols Drive and Division Street, this family friendly event culminates with free food and entertainment for all in Busch Park on Esters Blvd. The throws and goodies will be plentiful and the fun immeasurable.
Route: Starting at the intersection of Division Street and Nichols Drive going west on Division Street to Cailliavet Street. South on Cailliavet crossing the railroad tracks and making a left turn onto Esters Boulevard. Then right onto Reynoir Street south to Martin Luther King Boulevard turning left (north) onto Main Street. Main Street turning right onto Esters Boulevard and ending at Doris C. Busch Park at Alexander Avenue.


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A 12-Step Approach to the Sunday Readings / Edition 1by Jim Harbaugh S.J., Ji Harbaugh
Pub. Date: 10/31/2002
Publisher: Rowman & Littlefield Publishers, Inc.
Building upon his best-selling A 12-Step Approach to the Spiritual Exercises of St. Ignatius, Father Harbaugh now applies his extensive recovery wisdom to crafting insightful meditations based upon the weekend scriptural readings of the Common Lectionary. Readers familiar with the 12-Steps can now more effectively employ the readings they encounter at Sunday worship to consciously connect with their higher power. People of prayer that may not be familiar with the 12-Steps will surely benefit by this fresh and enlightening perspective. The 12-Step flavor is distinctly down-to-earth and remarkably makes accessible biblical history and theological concepts that often seem ethereal. Harbaugh's sense of humor enlivens even the most abstruse passage. A 12-Step Approach to the Sunday Readings will be welcomed by people who have been working any of several 12-Step programs and are interested in continuing and broadening their growth. It will also appeal to persons interested in the Spiritual Exercises or who make weekend retreats, and RCIA program directors who are looking for a fresh slant on spirituality.
Product Details
- 9781580511285
- Publisher:
- Rowman & Littlefield Publishers, Inc.
- Publication date:
- 10/31/2002
- Edition description:
- First Edition
- Pages:
- 192
- Product dimensions:
- 5.54(w) x 8.50(h) x 0.76(d)
Customer Reviews
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Most Helpful Customer Reviews
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Finger weights
available in 10 finger
and 5 finger standard
and universal models.
Drum heads and accessories, sets including acoustic, electronic drum head sets as well as drum machines for sale online! The biggest brand name manufacturers include tama, pearl, ludwig, yamaha, dw and more. We also carry a complete line of junior childrens drum sets for the beginner.
←back 44 45 46 47 48 49 50 51 52 53 54 next→
Aquarian Response 2 Drumhead 14 In.
"Response 2s are 2-ply heads that can be tuned tight or loose, played soft or hard, and sound great either way.Clear headPowerful soundOutstanding durability"
Remo Fiberskyn Ambassador Batter Head 14 In.
"FiberSkyn 3 drumheads feature an exclusive lamination process that combines Remo films and synthetic fibers to re-create the vintage sound, look, and feel of calfskin. The dark, warm, round tone is highly recommended for traditional jazz, R&B, and classi
Remo Fiberskyn 3 Simulated Calfskin Medium Bass Head 26 In.
"FiberSkyn 3 drumheads feature an exclusive lamination process that combines Remo films and synthetic fibers to re-create the vintage sound, look, and feel of calfskin. The dark, warm, round tone is highly recommended for traditional jazz, R&B, and cl
Remo Ebony Ambassador Head 8 In.
"Ebony series Ambassador drumheads from Remo give you the same sound you've come to expect from clear Ambassador heads. They feature excellent live sound projection with open, clear tone. Explosive attack with ringing sustain. Medium weight excels in a wi
Remo Renaissance Emperor Snare Batter 14 In.
"The Remo Renaissance Emperor heads have a warm sound that's great for melodic expression and affords a wider, more balanced sound spectrum for tympani, snares, toms, and bass drums in any drumming application. These replacement drumheads are the new worl
Remo Ebony Powerstroke 3 Resonant Bass Drum Head 26 In.
"Resonant heads are responsible for the projection and sustain of your drums. With fresh resonant heads you achieve more clarity and vibrancy in your drum sound.The Powerstroke 3 Black Resonant drumhead features a thin underlay at the outer edge of the he
Evans Genera Hd Dry Batter Coated Snare Head 13 In.
"The Genera HD yields an aggressive rimshot and balanced response. This durable two-ply head (7.5mil external, 5mil internal) with 2mil overtone control ring barks live, yet is ideal for the studio. Additional dry vents eliminate stray harmonics.Finish:
Evans Emad Resonant Bass Drum Head Black 18 In.
"With accentuated low-end response, the EMAD Resonant is constructed using a 7.5mil black film with a 6.5mil fixed internal control ring. It comes with an Externally Mounted Adjustable Damping system installed around the 4"" offset microphone port that al
Evans Genera Resonant Clear Drumhead 12 In.
Evans Genera Resonant Clear Drumheads are 10 mil single-ply heads. They allow bright overtones for enhanced high-end brilliance and projection without sacrificing sustain.
Aquarian Texture Coated Studio-X Drumhead 10 In.
"The Texture Coated Studio-X Drumhead is the coated version of a single ply, Studio-X drumhead. The Satin Finish texture coating gives the drumhead a firm attack and extra warmth."
Aquarian Classic Clear Drumhead Black 13 In.
"These clear, medium-thin single-ply heads have an open, sustained tone with a bright attack and full frequencies from top to bottom. They excel as resonant heads and for all playing styles."
Evans G1 Clear Batter Drumhead 13 In.
"The G1 Clear Batter is a single-ply, 10 mil-thick head with a bright attack, warm sustain, and a broad tuning range.Clear finishWide attackMedium warm toneOpen sustainSoft feelHighly durable"
Evans Emad Clear Batter Bass Drumhead 22 In.
"The Evans EMAD Clear Batter Drumhead comes with 2 damping rings, each of which affects the head's sound and pedal response. EMAD stands for Externally Mounted Adjustable Damping and this external system maximizes natural attack characteristics. It offers
Remo Weather King Ambassador Coated Head 10 In.
The most widely used drumheads in the world. The ones all others are judged by. Medium thickness. The Weather King Ambassador heads are the reigning champs for studio recording.
Remo Clear Ambassador Bass Drumhead 22 In.
"Single-ply, medium-weight, batter head is made with single-ply 10 mil Mylar film to produce an open and resonant sound with plenty of attack. Excellent for jazz and studio applications.Batter headSingle-plyMedium-weight10 mil Mylar filmOpen and resonant
Remo Clear Emperor Batter Drumhead 6 In.
Dual 7-mil films for maximum durability and clear resonance.