text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 26, 1991
|Filing date
|Sep 6, 1990
|Priority date
|Sep 6, 1990
|Fee status
|Publication number
|Todd A. Kline, Warren A. Rosen, William J. Bermingham, Eric A. Alfonsi
|Original Assignee
|The United States Of America As Represented By The Secretary Of The Navy
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (2), Referenced by (23), Classifications (6), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The invention described herein may be manufactured and used by or for the government of the United States of America for governmental purposes without the payment of any royalties thereon or therefore.
This invention relates to network interface integrated circuits for transferring high speed parallel digital data or commands which may be input at variable rates over a single asynchronous high speed serial data link.
Advanced highly parallel distributed data processing architectures rely increasingly on high speed fiber optic links to interconnect processing elements such as computers, signal processors, and sensors. In the past, to achieve high data rates for such interconnects, many parallel links were required. This resulted in increased power consumption and increased size due to the need for many optical transmitters and receivers. An additional problem with such interconnects was that the various elements of the architecture operated at different data rates making it difficult to implement a universal data link. This difficulty resulted because the receiving end of the link and the clock recovery devices usually could not cover a very extended bandwidth. Additionally, attempts were made to develop high speed interface integrated circuits which multiplexed the parallel data onto a serial data link. However, these integrated circuit multiplexers did not achieve the required speeds. Furthermore, this method required several integrated circuits to perform their function resulting in greater size and power consumption.
It is known in the art to provide chip sets which perform several of the required functions. For example, a chip set has been provided for this purpose by Gazelle. However, this chip set has not achieved data rates sufficient for optical interconnects in a computer environment having advanced signal processing equipment. Furthermore, this chip set requires two chips in order to perform both encoder and decoder functions. The Gazelle chip set has a forty bit wide input data word. Therefore this chip set is less suited to sensor or signal processor applications where size is a very important consideration. A Honeywell chip set provided for this purpose offers both a command mode and a data mode with a limited number of word commands. If both modes are provided in an integrated circuit embodiment a more efficient use of space is permitted. Moreover neither chip set offers both an eight bit mode and a sixteen bit mode.
A method is provided for decoding an input data stream formed of data words having word boundaries and a synchronization word in a network interface unit of a high speed computer network. The input data stream is applied to a serial-to-parallel shift register to provide parallel boundary determination words for locating a word boundary within the data stream. There is no serial shifting of bits within the parallel boundary determination words. The parallel boundary determination words are shifted through a register file in parallel and simultaneously applied to synchronization word detectors which provide a series of synchronization word detection windows shifted from each other by one bit. When one of the detection windows detects the synchronization word a word boundary is determined in accordance with the detection.
Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings wherein:
FIG. 1A shows a functional diagram of the high speed switched network using the optical interconnects of the present invention.
FIG. 1B shows a more detailed representation of a network interface unit within the high speed switched network of FIG. 1A wherein the network interface unit includes the optical interconnects of the present invention.
FIG. 2 shows a block diagram representation of the network interface chip encoder section of the network interface unit of FIG. 1B.
FIG. 3 shows a block diagram representation of the network interface chip decoder section of the network interface unit of FIG. 1B.
FIGS. 4a,b show more detailed block diagram representations of the register file of the interface chip decoder section of FIG. 3.
FIG. 5 shows a plan view representation of an integrate circuit embodiment of the network interface unit of FIG. 1B.
Referring now to FIG. 1A, there is shown a functional diagram of high speed switched network 10 of the present invention. High speed switched network 10 includes network crossbar switch 16 as well as a plurality of high speed nodes 12 and network interface units 14. High speed nodes 12 or high speed computers 12 of high speed switched network 10 communicate with each other by way of crossbar switch 16 and network interface units 14.
Referring now to FIG. 1B, there is shown a block diagram representation of network interface unit 14 of high speed switched network 10. Network interface unit 14 of high speed switched network 10 allows bidirectional communication over full duplex, point-to-point links 15 between network interface units 14 and crossbar switch 16. Data can be transmitted by way of point-to-point links 15 at one gigabit per second or any slower rate within switched network 10. Additionally sixteen user-defined commands may be transmitted over point-to-point links 15. Two functional sections 42, 44 are included within network interface unit 14. One of the sections within network interface unit 14 is interface transmitter section 42. Interface transmitter section 42, including transmitter data encoder 40 and clock oscillator 31, transmits data to point-to-point link 15 by way of optical transmitter 30. The other section within network interface unit 14 is interface receiver section 44. Interface receiver section 44 includes receiver data decoder 38. Receiver data decoder 38 receives data from point-to-point link 15 by way of optical receiver 37.
One external host computer 12 of the plurality of high speed computers 12 within network 10 presents parallel data and control signals to the encoding logic of interface transmitter section 42 within network interface unit 14. Transmitter data Encoder 40 can input either eight-bit parallel data words or sixteen-bit parallel data words on data buses 18a,b. Data lines 18a may receive bits zero to seven and data bus 18b may receive data bits eight to fifteen during parallel operation. Thus the low order byte and the high order byte are received by separate parallel data buses 18a,b during sixteen-bit operation of transmitter data encoder 40. Transmitter data encoder 40 of interface transmitter section 42 is configured for the selected data word length by way of data word mode control line 20.
Host computer 12 can input data as either data words or user-defined command words. Command/data control line 22 of transmitter data encoder 40 indicates to encoder 40 what type of information is on data buses 18a,b. Data words are accepted from the host computer using a conventional DATA READY/ACKNOWLEDGE handshake on encoder control lines 19a,b. Data can be transmitted by interface transmitter section 42 at the maximum clock rate of sixty two and one-half megahertz for sixteen-bit words or one hundred twenty five megahertz for eight-bit words. The parallel data word is encoded and converted to a serial stream and transmitted at one gigabit per second. Any rate from host computer 12 less than the maximum is accepted by transmitter data encoder 40 of interface transmitter section 42.
Interface receiver section 44 of network interface unit 14 accepts data from an interface transmitter section 42 of a differing network interface unit 14 by way of optical receiver 37 and presents the correct eight-bit or sixteen-bit words to receiving host computer 12 by way of decoder data lines 24a,b. Command/data control line 26 of interface receiver section 44 indicates to host computer 12 whether the received information is a command or data word. A DATA STROBE signal applied to decoder control line 25 indicates to the host computer when each new word is available. An error signal on decoder control line 28 indicates if information is received incorrectly by interface receiver section 44.
After power-on and after periods with no signal on point-to-point link 15, clock recovery circuitry 36 of interface receiver section 44 must acquire synchronization with the incoming signal received by optical receiver 37. When this happens, interface transmitter section 42 of a transmitting network interface unit 14 sends a unique symbol, called SYNCH, to interface receiver section 44 of the receiving host computer. Different SYNCH symbols allow receiver data decoder 38 to synchronize at the correct eight-bit or sixteen-bit boundary of the received information.
By decoding these SYNCH and data symbols, receiver data decoder 38 may signal receiving host computer 12 of the selection of either the eight-bit word size or the sixteen-bit word size. Additionally receiver data decoder 38 signals receiving host computer 12 whether the command mode or the data mode is selected. Transmitting host computer 12 may transmit at rates less than one gigabit per second, for example in the case of a slow sensor. For this type of host computer 12, interface transmitter section 42 of network interface unit 14 inserts SYNCH symbols when data are not available from host computer 12 at the one gigabit per second rate. In this way clock recovery circuitry 36 of interface receiver section 44 may remain locked to a constant frequency regardless of the rate at which the data is presented to transmitter data encoder 40.
Referring now to FIG. 2, there is shown a more detailed block diagram of transmitter data encoder 40 within interface transmitter section 42 of network interface unit 14. The internal operation of network interface unit 14 and the operations of the serial transfers over point-to-point links 15 are transparent to a user. Within transmitter data encoder 40 the parallel data are clocked by way of data input buses 18a,b into internal encoder input register 39a. When the data are thus stored in internal encoder input register 39a, b and the DATA READY signal of encoder control line 19a is detected by encoder control logic 43 within transmitter data encoder 40, an ACKNOWLEDGE signal is returned to the user by way of encoder control line 19b. The input of transmitter data encoder 40 is double-buffered using internal encoder input register 39b to permit access to internal input registers 39a,b within transmitter data encoder 40 for loading data for the following cycle while data for the current cycle are being encoded by transmitter data encoder 40.
Within transmitter data encoder 40, a 4B5B encoding scheme is used to encode the data in 4B5B encoders 41a-d. In this 4B5B encoding scheme, a four bit nibble is encoded into a five-bit symbol. In order to transfer input data from host computer 12 at one gigabit per second, the five-bit symbols from 4B5B encoders 41a-d must be transmitted at a one and one-quarter gigabit per second rate. In the resulting five-bit code, thirty-two symbols are possible. Sixteen of these thirty-two symbols are used for data and several others are dedicated for commands and maintaining synchronization of interface receiver section 44 with incoming data. The remaining symbols are not allowed. Limiting the number of valid five-bit symbols in the encoding scheme has several advantages. These advantages include ensuring a minimum number of transitions for each five-bit symbol, limiting the run-length between transitions, and minimizing the DC component in the serial data stream transmitted by way of serial data line 51. In this way pulse width distortion due to DC drift is minimized in interface receiver section 44. To further minimize the DC component, the non-return to zero (NRZ) data is converted to invert-on-one (NRZI) before being transmitted by interface transmitter section 42.
Within transmitter data encoder 40, either two four-bit nibbles or four four-bit nibbles are encoded in parallel, depending respectively on whether the network interface unit 14 is operating in the eight-bit mode or the sixteen-bit mode as indicated by encoder mode control line 20. Two four-bit nibbles of input data are encoded by 4B5B encoders 41a,b when the eight bit mode of network interface unit 14 is selected. Two additional four-bit nibbles are encoded by 4B5B encoders 41c,d when the sixteen-bit mode is selected. Each symbol is converted from parallel to serial within shift register 49 and further encoded by NRZ to NRZI encoder box 47.
The cycle time signal of clock line 45, eight hundred picoseconds, is applied to clock generator 46. Ten clock cycles of this time duration are needed to transmit two five-bit symbols. Therefore, each encoded data word takes eight nanoseconds to transmit by way of transmitter data encoder 40. Encoder control logic 43 operates at twice this speed with a four nanosecond cycle time. This is a speed of two hundred and fifty megahertz. Since the user interface to transmitter data encoder 40 is asynchronous, by running the control logic at twice the eight-bit data rate and thereby double sampling, transmitter data encoder 40 is assured of never missing any data words input from host computer 12. Every four nanoseconds, a pulse is generated to load five data bits into shift register 49 for transmission to point-to-point link 15.
As previously described, if no user data is present at the input of transmitter data encoder 40, a SYNCH symbol is transmitted instead. The SYNCH symbol is transmitted until new data is applied to the input of transmitter data encoder 40 for transmission. If the new data is applied while transmitter data encoder 40 is in the process of transmitting a SYNCH symbol, transmitter data decoder 40 delays the transmission of the new data and finishes the transmission of the current SYNCH symbol before beginning the transmission of the new data. This is performed by applying the data to multiplexer register 46 which applies a selected five-bit word to multiplexer register 63 in accordance with a control signal from control logic 43.
The internal logic of 4B5B encoders 41a-d runs at the same speed as encoder logic control 43. It therefore takes four nanoseconds to encode user data into valid 4B5B code symbols within 4B5B encoders 41a-d. Thus if a DATA READY pulse on decoder control line 19a just misses a parallel load pulse, the use data can still be encoded in time to catch the next load pulse.
Output shift register 49 of transmitter data encoder 40 is implemented in Source Coupled FET Logic (SCFL logic). SCFL logic is large and has high current requirements and will be discussed in more detail below. Therefore in the preferred embodiment of transmitter data encoder 40, output shift register 49 is only five bits wide, rather than the ten bits necessary to load a complete SYNCH character. This saves space and power within transmitter data encoder 40. However, it presents a timing problem with respect to user data. The problem arises because the first half of a SYNCH character must be followed by the second half during data transmission before any user data may be transmitted by interface transmitter section 42.
If input register 39a is in the eight-bit mode and operating at the maximum rate of one-tenth the rate of clock line 45, there are ten pulses on clock line 45 for each pulse on line 19a. Control logic 43 operates at one-fifth the rate of clock line 45, or twice the maximum rate of input register 39a. This maximum rate is the control cycle length. On every control cycle, line 19a is examined by control logic 43 to determine whether new user data is present within input register 39a. Also, during every control cycle, a five-bit data symbol, or one half of a SYNCH character, is loaded into multiplexer register 63 for a transfer to shift register 49 during the next control cycle.
Table 1 shows one possible transmission pattern. In this transmission pattern it is assumed that the user has just started sending data after some number of SYNCH characters. The bottom row of Table 1 represents the actual data placed on serial output line 51 by NRZ-to-NRZI connector 47. The other rows of Table 1 represent the contents of registers 39a,b and multiplexer registers 46, 63. In Table 1, dnb,a represents an eight-bit data word where n takes the values from one to three. Dnb,a represents a ten-bit encoded data word wherein n may take the values from one to three. Dnb and Dna are five-bit data symbols wherein n again, may take the values from one to three. J and K are five-bit symbols used to form the ten-bit SYNCH character. Table 1 shows that by the time more data is entered during cycle n+2, the old data in register 39b has already been loaded into multiplexer register 63 and transmitted by way of serial output line 51.
TABLE 1______________________________________ControlCycle: n n + 1 n + 2 n + 3 n + 4 n + 5______________________________________Load 39a d1b,a -- d2b,a -- d3b,a --Load 39b D1b,a -- D2b,a -- D3b,a --Load 46 -- D1b -- D2b -- D3bLoad 63 J D1a D1b D2a D2b D3aLoad 49 K J D1a D1b D2a D2b______________________________________
Referring now to Table 2, data D1b has not yet been loaded into multiplexer register 63 when D2a,b is loaded into register 39b. If D1b had not been saved in multiplexer register 46 in the previous cycle, it would be lost. Thus, by adding multiplexer register 46 to the data path from register 39b to output shift register 49, and making control of transmitter data encoder 40 somewhat more complex, the amount of SCFL logic used in shift register 49 is reduced by fifty percent. Because multiplexer shift register 46 saves D1b and shift register 49 can be five bits worth of SCFL logic rather than ten, significant power and size enhancements are realized in the preferred embodiment of transmitter receiver encoder 40.
TABLE 2______________________________________ControlCycle: n n + 1 n + 2 n + 3 n + 4 n + 5______________________________________Load 39a d1b,a -- d2b,a -- d3b,a --Load 39b D1b,a -- D2b,a -- D3b,a --Load X -- D1b -- D2b -- D3bLoad Q K J D1a D1b D2a D2bLoad 49 J K J D1a D1b D2a______________________________________
Referring now to FIG. 3, there is shown a more detailed block diagram representation of receiver data decoder 38 of interface receiver section 44. Within interface receiver section 44, the clock information embedded in the incoming data stream of decoder input line 50 is extracted by clock recovery circuitry 36 using conventional clock recovery techniques. The extracted clock information is used to generate a synchronized clock signal for receiver data decoder 38. The incoming data on decoder input line 50 is converted from NRZI to NRZ by NRZI-to-NRZ converter 52 and clocked into five bit serial-to-parallel decoder input shift register 54.
Every four nanoseconds, the five serial bits which have been shifted into decoder input shift register 54 are clocked into five-bit wide by three-word deep register file 56 for a determination of the boundaries of adjacent data words within the serial input data stream. Register file 56 therefore contains fifteen bits which are shifted through register file 56 as three five-bit boundary determination words. Thus register file 56 allows the testing of a relatively large portion of the serial bit stream of decoder input line 50 from optical receive 37 at the same time in order to facilitate the finding of word boundaries within the input data stream by receiver data decoder 38. Even though this method therefore requires a larger number gates, it permits the use of slower gates. In GaAs technology the slower gates are smaller thereby allowing receiver data decoder 38 to be smaller.
Each SYNCH symbol is composed of two five-bit words. There are therefore five possible positions in which the SYNCH symbol can occur within register file 56 depending upon where within register file 56 the first bit lies. SYNCH detection logic 68 searches the fifteen bits within register file 56 to locate the relative position of the SYNCH symbols within the serial bit stream. SYNCH detection logic 68 also controls five port multiplexer 58 by way of control line 69 to select the proper word boundary. SYNCH detection logic 68 also sets control flip-flops within decoder control logic 70 to signal either the eight-bit mode or the sixteen-bit mode by way of decoder control line 27.
Referring now to FIGS. 4a,b, more detailed representations of register file 56 are shown. Within register file 56 three five-bit registers 56a,b,c are provided. Each register 56a,b,c contains a parallel boundary detection word for use by receiver data decoder 38 in determining the word boundaries of the imput data stream after a period during which the SYNCH bit pattern is transmitted by receiver data decoder 38 of a different node 12 within high speed switched network 10. Five bit data buses 57a,b,c of five-bit registers 56a,b,c are joined end-to-end to form fifteen-bit data bus 57 for applying the concatenated boundary detection word to multiplexer 58 and SYNCH detection 68. SYNCH detection 68 contains five sets of gates (not shown). Each set of gates in SYNCH detection 68 is ten bits wide and is adapted to recognize the same unique SYNCH bit pattern.
Thus five ten-bit synchronization word detection windows 68a-e ar provided within SYNCH detection 68 for detecting the ten-bit SYNCH pattern within the fifteen bits being shifted through register file 56 in parallel as three five-bit boundary detection words. The five ten-bit synchronization word detection windows 68a-e thus provided within SYNCH detection 68 monitor the five possible positions which a ten-bit SYNCH word may occupy within register file 56. Thus each successive synchronization word detection window 68a-e is shifted one bit with respect to another detection window 68a-e. Five-bit output buses 57a,b,c of each of the three registers 56a,b,c within register file 56 containing the boundary detection words are applied end to end to the five sets of gates in SYNCH detection 68. This method provides a virtual serial detection scheme while permitting parallel shifting of the boundary detection data, allowing the use of slower and smaller circuitry.
When one of the five sets of gates in SYNCH detection 68 determines the presence of the SYNCH bit pattern in one of the five possible positions within register file 56, it signals multiplexer 58 to apply a selected five-bit word having correct word boundaries to register 60 by way of five-bit bus 61. SYNCH detection 68 signals multiplexer 58 which channel within bus 57 to select by way of five-bit bus 69 in accordance with which of the five synchronization word detection windows 68a-e determines that the SYNCH bit pattern is present. Thus, multiplexer 58 applies to register 60 one of several possible five-bit words within the single concatenated boundary detection word applied to multiplexer 58 by way of fifteen-bit bus 57. Which five-bit word is selected from bus 57 by multiplexer 58 is determined according to the signal applied to multiplexer 58 by way of bus 69. Multiplexer 58 then remains locked on the channel corresponding to the selected five-bit word. Thus, while SYNCH detection 68 determines synchronization of receiver data decoder 38, multiplexer 58 maintains the synchronization.
SYNCH detection may be performed using the serial bit stream of decoder input line 50. However, use of the serial bit stream requires a large number of very high speed high power Source Coupled FET Logic (SCFL) cells. SCFL cells are considerably larger and consume more power than conventional lower speed cells. Thus, even though the parallel SYNCH detect method of the present invention uses more logic gates, it consumes less power and is smaller than a corresponding serial SYNCH detection method. The parallel SYNCH detection method of the present invention increases the pipeline depth of boundary determination data and permits the fifteen bits of the parallel boundary determination words used for SYNCH detection to be available to SYNCH detection 68 for a long period of time. During this long period of time relatively slow circuitry may be used within register file 56 because the boundary determination data is shifted as parallel words rather than as a serial data stream while the three parallel boundary determination words are applied to SYNCH detection 68 as a single concatenated boundary detection word by bus 57. The additional eight nanoseconds required for the method of the present invention is small compared to the propagation time between high speed nodes 12 of high speed switched network 10.
Once output port 59 of multiplexer 58 is set to the proper word boundary, one five-bit symbol is decoded into the original four-bit nibble per four nanosecond control cycle within 4B5B decoder 62. If the bits received by way of decoder input line 50 are not a valid SYNCH symbol, they are assumed to be data. At this time a test for invalid symbols is performed by decoder control logic 70. Any invalid symbols detected by decoder control logic 70 are reported to host computer 12. Valid data are packed into either eight-bit or sixteen-bit words within register 64 depending on the mode as indicated on line 27. The data words are then strobed into receiving host computer 12 by way of decoder data output lines 24a,b. The correct status for a command word or data word is also presented to host computer 12.
Referring now to FIG. 5, there is shown a plan view of integrated circuit 100. Integrated circuit 100 is the preferred embodiment of receiver data decoder 38 and transmitter data encoder 40 of network interface unit 14 of high speed switched network 10. The logic of receiver data decoder 38 and transmitter data encoder 40 of network interface unit 14 are preferably implemented in a gallium arsenide (GaAs) application specific integrated circuit (ASIC) such as integrated circuit 100 using the Vitesse Semiconductor VCB 50K Standard Cell Product. Both receiver data decoder 38 and transmitter data encoder 40 may be implemented on the same GaAs die. Packaged one-hundred thirty-two pin integrated circuit 100 for implementing receiver data decoder 38 and transmitter data encoder 40 network interface unit 14 may have dimensions of approximately one-inch by approximately one-inch by approximately one-tenth of an inch. Integrated circuit 100 may have a nominal power consumption of three and one-third watts to five watts. While the internal logic of network interface unit 14 implemented within integrated circuit 100 may operate at GaAs levels, ECL compatible interface logic may also be provided to interface integrated circuit 100 with other elements of high speed switched network 10.
Receiver data decoder 38 and transmitter data encoder 40 share the common feature of handling high speed parallel data as well as very high speed serial data. They must therefore convert between serial and parallel data formats. Because power consumption is strongly influenced by operating frequency, it is desirable to limit the number of very high speed signals within network interface unit 14. There are two types of logic cells in the Vitesse standard cell library. As previously described, there is the very fast, high power source coupled FET logic (SCFL). Additionally, fast, low power direct coupled FET logic (DCFL) cells are available. Integrated circuit 100 provides physical locations for SCFL region 102, DCFL region 104, and translator region 106. The very high speed lines (not shown) of integrated circuit 100 are located near SCFL block 102. Network interface unit 14 may thus be formed of integrated circuit 100 along with optical input and output circuitry as well as a clock.
The high power SCFL cells of SCFL block 102 can operate at toggle rates up to approximately three and one-third gigahertz. They are best suited for implementing the serial logic of network interface unit 14. The low power DCFL cells of DCFL block 104, which toggle at speeds up to six hundred fifty megahertz, can be used for parallel logic. The SCFL logic cells consume anywhere from approximately nine to approximately fifty times the power of the slower DCFL logic depending upon which cells are compared.
It should be noted that only part of the difference in power consumption between the two types of logic is due to the frequency of operation. The SCFL cells have a structure similar to bipoplar ECL and therefore use more transistors than NMOS-like low power cells. As a result, the very fast cells not only consume more power, they also tend to occupy two to five times the area of an equivalent low power cell. As in some forms of very fast bipolar ECL logic, the high power cells use differential signal lines while the low power cells are single ended. The high power cells are also much less sensitive to fan out than the low power cells. Because of power/size considerations for both receiver data decoder 38 and transmitter data encoder 40, only serial shift register 54, state machine clock generation circuitry 66, NRZ-to-NRZI converter 47, NRZI-to-NRZ converter 52, and clock generator 46, may use the high power logic.
The problem of testing network interface unit 14 as embodied in integrated circuit 100 is complicated by the fact that since the data word is encoded, the presence of a bad bit results in corruption of the entire word. This means that the concept of bit error rate is difficult to define and more difficult to measure. Moreover, the NRZ/NRZI conversion within network interface unit 14 further complicates the testing problem. This is because each NRZI data bit really defines a bit boundary in the original NRZ Data. Thus if one NRZI bit is in error, two NRZ bits are corrupted when the NRZI stream is decoded by transmitter data decoder 40 of interface transmitter section 42. If these two corrupted bits straddle the boundary between two NRZ words, both NRZ words may be corrupted.
Thus it is believed that the word error rate is an appropriate error measurement for testing network interface unit 14 as embodied in integrated circuit 100. The word error rate of integrated circuit 100 may be measured using a custom test fixture (not shown). The custom test fixture may consist of a test computer (not shown) and a high speed memory board (not shown). At the start of a test sequence, the test computer (not shown) loads a pseudo-random bit pattern into one bank of memory. The pseudo-random data is clocked out as either eight bit words or sixteen bit words at one hundred twenty five megahertz or sixty two and one half megahertz respectively. The pseudo-random data is transmitted through integrated circuit 100, and collected in a second bank of memory. The contents of the two memories are then compared to locate any errors. The number and nature of any errors are recorded and the sequence is repeated until sufficient data is obtained to achieve statistical significance.
Integrated circuit 100 within network interface unit 14 provides full duplex bidirectional communications with a DATA READY/ACKNOWLEDGE handshake by way of control lines 19a,b of transmitter data encoder 40. Network interface unit 14 may achieve a data rate of one gigabit per second throughout in a single low profile, low power chip, such as integrated circuit 100, suitable for use in such standard packaging forms as SEM-E modules. Any input rate up to the maximum may be transmitted by network interface unit 14. Network interface unit 14 also offers such advantages as selectable eight bit word size or sixteen-bit word size modes, selectable command mode or data mode.
It will be understood by those skilled in the art that over short distances, interface transmitter section 42, interface receiver section 44, and point-to-point fiber link 15 may be replaced with electrical line drivers (not shown), electrical receivers (not shown) and coaxial cable (not shown).
Many modifications and variations of the present invention are possible in view of the above disclosure. It is therefore to be understood, that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.
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|U.S. Classification
|375/368, 370/513, 370/514
|International Classification
|Cooperative Classification
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|Sep 6, 1990
Owner name: UNITED STATES OF AMERICA, THE, AS REPRESENTED BY T
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KLINE, TODD A.;ROSEN, WARREN A.;BERMINGHAM, WILLIAM J.;AND OTHERS;REEL/FRAME:005440/0428
Effective date: 19900829
|May 22, 1995
|Fee payment
Year of fee payment: 4
|Jun 22, 1999
|Maintenance fee reminder mailed
|Nov 28, 1999
|Lapse for failure to pay maintenance fees
|Feb 8, 2000
|Expired due to failure to pay maintenance fee
Effective date: 19991126


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Though green
Black Tea
The variety of tea that most people are familiar with is black tea. After the tea leaves are picked, they are snapped, broken or rolled, which produces oxidation, and then they are dried. The drying process stops the oxidation, but the oxidized process itself does remove most of the antioxidants called polyphenols that provide nutritional benefits. Though much of the health benefits are removed, the flavor of black tea is a familiar, pleasing, and very palatable taste, and is widely consumed.
Studies Suggest Green Tea Has Therapeutic Properties
Green tea is not only available in the traditional bag form, but in leaf form, as vitamin supplements, and as the ever popular trendy beverages. However one chooses to consume the delectible beverage, i
Green tea has been shown to be beneficial in reducing the occurrence of or even the prevention of certain cancers by inhibiting the growth of cancer cells. Evidence in some studies suggest that the tea aids in weight loss by boosting metabolism, assists in regulating blood sugar and insulin spikes, as well as helps the digestive process. The effective and very powerful antioxidants in green tea make it a natural remedy for certain ailments, the consumption of which can contribute to a healthy lifestyle.
The legendary beginnings of Chinese green tea that is enjoyed all over China, goes back 4,000 years. Drinking the refreshing beverage in the ever popular and authentic tea houses that are found throughout parks, cities, on the roadsides, or in the hills and valleys is a very special and memorable experience. The plants are grown either in sun or shade, typically in rows, and harvested several times a year. The procedure is a refined process, and a particular well-known Chinese tea has even won several national awards. There is even a National Chinese Tea Museum, the largest such museum in the world, and a very popular tourist attraction.


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Don't let your home improvement project become a horror story. This workshop will help you avoid common pitfalls so that the end result of your project is in line with your expectations for both quality and budget. In Part 1, you will learn about how to define your own expectations for the work you need and how to find, evaluate, and choose a contractor, with a particular focus on maintaining good communication. Parts 1 and 2 (December 17) can be taken separately.
Paul Kiefer is on staff at Boston Building Resources. He has more than 20 years' experience as a woodworking contractor and coordinates deconstruction services for the Reuse Center at BBR.
Register for both Parts 1 and 2 and save $10! Call 617-442-2262 for the coupon code!


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Toys Will Be Toys
5 S Section St Fairhope, Alabama 36532(251) 432-6363
Print | Save | Directions
AboutToys Will Be Toys is located at the address 5 S Section St in Fairhope, Alabama 36532. They can be contacted via phone at (251) 432-6363 for pricing, hours and directions.
Toys Will Be Toys has an annual sales volume of 501K - 999,999. .
For maps and directions to Toys Will Be Toys view the map to the right. For reviews of Toys Will Be Toys see below.
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Ritchey WCS Carbon Link Flexlogic Zero Offset Seatpost
RRP $252.71Save 10%
Code: PRD2081
Ritchey WCS Carbon Link Flexlogic Zero Offset Seatpost
The Ritchey two-bolt post reinvented—Lighter, more compliant and more versatile than ever.
- Patented LINK clamp works with all standard saddle rail designs as well as Ritchey Vector Evo™ and Selle Italia MonoLink™ saddles with separate adapter
- LINK Carbon Posts use FlexLogic carbon layup developed for ProTour team bikes from Stevens, Canyon and Scott – 15% more vertically compliant with no loss of lateral or torsional stiffness
- 15mm of offset and a reversible clamp which allows for an additional 10mm of fore-aft saddle adjustment
- Monocoque Carbon Construction
- Diameters: 27.2, 30.9, 31.6mm
- Offset: 15mm
- Reversible clamp allows for an additional 10mm of fore-aft saddle adjustment
- Lengths: 350, 400mm
- Matte UD finish
- 181g (27.2x300)
Please enter your e-mail address below then click Notify Me to be notified when this item comes back into stock. We will not use your e-mail address for any other purpose.
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Help ! Today I bought a Samsung Infuse 4G. I can NOT figure out how to assign a downloaded song snippet to a contact. And where are the downloaded tones/song snippets that I purchased from ATT Music Store ? They're not in my downloads file. I know how to assign a tone that's IN the phone but NOT a separate tune. THANK YOU so much ! Signed...Frustrated !
Welcome to the AT&T Community Forums!!! Stop by the Community How-To section for tips on how to get started.
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Strawberry-Rhubarb Freeze
Total Time
Prep 10 mins
Cook 0 mins
Ingredients Nutrition
- 1 pint strawberry
- 2 cups cooked rhubarb
- 2 tablespoons lemon juice
- 1⁄8 teaspoon salt
- 1 1⁄2 cups sugar
- 3⁄4 cup heavy cream
- Wash berries, hull and mash.
- Press rhubarb through sieve, add remaining ingredients, pour into freezing tray of refrigerator and freeze without stirring until firm.
- When ready to serve, scrape up thin layers of the mixture with an inverted spoon, beat back and forth in the tray until smooth and serve immediately.


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Unto The Breach
RRP £19.50 Save £3.01
£16.49 Limited availability Ask us a question about this product
Please allow an additional 4 - 8 working days before despatch
This item is coming from a different warehouse and may take slightly longer than usual to despatch. Once the item has been despatched, usual delivery time applies.
Price Drop Notification
Unto The Breach Product Description
This title is a sequel to "Ghost", "Kildar" and "Choosers of the Slain". Michael Hannon has been there and done that - rescued co-eds, killed major terrorists, stopped nuclear assaults. Now he'd just like to kick back and relax with his harem of lovelies. Unfortunately, the world keeps turning. Mike and the Keldara are back tracking down terrorists, rogue Russian bio-scientists and the doomsday weapon to end all doomsday weapons. It's going to take some very tough, hard and nasty people to stop the end of the world. Fortunately, there's Mike Hannon. The hero of "Ghost", "Kildar" and "Choosers of the Slain", along with his company of elite mountain fighters, is sent on a mission to stop an advanced smallpox plague from being turned over to terrorists. But that will only be the beginning as the Kildar and his Keldara rush to stop a host of WMD attacks, coordinated to take out the very heartland of terrorism's enemies. It's a battle for culture, and this time the terrorists aren't aiming at just one building.
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Additional Information
|Mass Market
|Black & White
|Recommended Ages
|Mature Readers (ages 16+)
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Eureka Seven
Don't You Want Me?
Episode 45 | TV-14
Jurgens and Dominic board the Gekko and confront Dr. Bear. After learning the truth about the Scub Corals, they begin to question their allegiances. On Earth, stress builds between Renton and the kids regarding Eureka's transformation.
Dub Expires: 12-01-2014
Sub Expires: 12-01-2014
Official Site: www.funimation.com/shows/eureka-sevenHide Details


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Welcome to EscambiaVotes.com
News & Notes
News Release - Voter Survey Results Released
Escambia County Supervisor of Elections David H. Stafford partnered with the University of West Florida's Haas Center on a comprehensive survey of Escambia County voters during this year's primary and general elections in order to measure voter satisfaction with polling locations and staff, knowledge of election rules, voting method choice, and other factors.
News Release - Students Made Their Voices Heard in Mock Presidential Election
Escambia County Supervisor of Elections David H. Stafford partnered with Escambia County School District and Double Click Democracy, an online election service supported by the Lou Frey Institute at UCF and Kids Voting USA, in offering Escambia County students the opportunity to vote in a mock Presidential election. More than 10,000 students in multiple grade levels from various schools around the county participated in the online election and cast their ballot in two contests: President and Vice President, and United State Senator.


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4 bedroom, 3 bathrooms, in a stunningly beautiful setting. Sleeps 8-12
Nestled in an enchanting private pine and oak forest, this very pretty villa is a dream for those wishing to escape the daily grind and have a totally relaxing provencal break. The villa was completely refurbished 2 years ago and manages to mix the new with the old: modern on the inside and typically provencale on the outside. The newly built pool (15m x 4.5m) is a modern version of a traditional "bassin" and comes with an innovative filter system to reduce chemicals and a robot that does all the hard cleaning work. Hammocks and sun loungers are provided along with pool towels and a selection of outdoor toys (boules/ badminton). Lavender, thyme and rosemary grow in abundance in the newly landscaped garden and around the enormous terrace. A large outdoor dinning table under the pergola is perfect for al-fresco lunches on the terrace, while an outdoor "sitting room" means that you can spend all your days outside. But what makes Les Fauquieres so special and totally different to any other villa is its stunning forest location. Oaks, pines and poplars grow on ochre land and the forest is the perfect playground for kids wanting to build camps and grown ups wanting to have long walks or bike rides. For those who love antiques we are 40 minutes away from the world famous Isle sur La Sorgue antiques market and there are "brocante" sales weekly in the surrounding villages. We are a 10 minute drive from Apt and its famous Saturday market.
Top Traveller Review
Perfect - stunning property & idyllic location!Perfect - stunning property & idyllic location!
About the Owner
This stunning property has been in Pierre's family for over a century. In 2013 he undertook a large scale renovation of the house and added the pool and the terrace. Pierre and his family live in London, they try and get home to Les Fauquieres as often as possible.
Guestbook comments from the owner
"The most relaxing place in the world. Yoga by the pool, walks in the woods, fresh food...Heaven!" Beth and Linda, London (visitors 2 years in a row)
"A perfect playground for children which gives us adults the chance to read and relax. We loved our trips into the Luberon and we plan to come back again in the summer" Philippe and Irene, Paris
Wow, Italy had always been our top choice of holiday destination, but our stay in Les Fauquieres has changed our mind! 2 years in a row and we are planning a 3rd.
2 Reviews
2 holidaymaker reviews
Perfect - stunning property & idyllic location!
Villa Les Fauquieres was quite simply the best property we have stayed in during our numerous family holidays to the South of France! Truly exceeds the description & photographs, as not only is the exterior of the house (the pool, the seating area & the terrace) gorgeous, the interior is so well designed with superb taste & fantastic modern fixtures & fittings. We have never visited the Luberon region before, but I think this has now become my new favourite part of Southern France; amazing views, wonderful hillside towns - simply beautiful. If you're looking for the definition of peace & quiet and need somewhere to relax & recharge - Villa Les Fauquieres is the perfect property for you! Thanks to Faiza & Pierre for their hospitality & their ease of communication! We will be back!!
It's an extraordinary place for Holidays, hidden in the "Provence" landscape, very clean and very well and nicely restored with a beautiful swimming pool and outdoor terrasse. It's close to all markets and to the beautiful picturesque small villages on the hills of the Lubéron like Gordes, Bonnieux and Lacoste. Highly recommended.
Activity and Interests
Marseille Airport 1hr 15mins minutes away
Avignon TGV 50 minutes away
You will need a car
These are some of the villages that are within a 20 minute drive
Roussillon 10 minutes
Joucas 15 minutes
Gordes 20 minutes
Bonnieux 20 minutes
Rental rates
|Rental Period
|Minimum Price
|Additional Nights
|Weekend Night
|Event Price
Rate 1
1 Apr 2017 - 24 Jun 2017
7 night minimum stay
for 7 nights
Main Season
25 Jun 2017 - 30 Sep 2017
7 night minimum stay
for 7 nights
Rate 2 2017
1 Oct 2017 - 1 Apr 2018
7 night minimum stay
for 7 nights
My Standard Rate
7 night minimum stay
for 7 nights
Additional pricing information
|No additional mandatory fees
|Refundable Damage Deposit
Booking Notes:
1/3 deposit payable on booking. Refundable if cancelled within 90 days of booking. Balance is payable 6 weeks before arrival, along with a breakages deposit of €1000 a which will be refunded the week after your stay.
Changeover Day:
Minimum 1 week rental.
Saturday changeover but we will try and accommodate other requests if it is possible.
Departures by 11am and arrivals at 4pm
Notes on prices:
Please feel free to contact us as depending on the size of the party, the availability and the length of stay as we are happy to discuss a possible discount.
Owner's Cancellation Policy
- 12
- Available arrival
- 12
- Available
- 12
- Unavailable
From the Owner
"We love coming home to Les Fauquieres for the sheer pleasure of total rest and relaxation. While there are thousands of beautiful villas in the Luberon, few offer the magical location and ochre richness of Gargas/ Roussillon. It especially wonderful for those who love the outdoors and for those with children who want the freedom to run wild!"
Property Type
- villa
- Ceiling Fans
- Hair Dryer
- Heating
- Internet
- Iron & Board
- Linens Provided
- Living Room ...
- Parking
- Telephone
- Towels Provided
- Washing Machine
- Coffee Maker
- Dishes & Utensils
- Dishwasher
- Freezer
- Kitchen ...
- Microwave
- Oven
- Refrigerator
- Hob
- Toaster
- Dining Area
- Games
- Ping Pong Table
- Satellite / Cable
- Stereo
- Television
- Toys
Pool / Spa
- Private Pool
- children welcome
Location Type
- rural
- village
- Bathroom 1 - Toilet, Bath (no shower), Shower Enclosure
- Shower room 1 - Shower Enclosure
- Shower room 2 - Shower Enclosure
- En-suite Bathroom for Bedroom 1, with bath Shared Bathroom for Bedrooms 2 and 3, with Italian shower Ensuite Bathroom for Bedroom 4, with Italian shower
- 4 Bedrooms, Sleeps 12
- Bedroom 1
- Bedroom 2
- Bedroom 3
- Bedroom 4
- Description of sleeping capacity: Sleeps 12 (4 Bedrooms) Notes on bedrooms: Bedroom 1: superking double, ensuite bathroom (sleeps 2) Bedroom 2: kingsize double (sleeps 2) Bedroom 3: 1 bunkbed, 1 truckled bed (sleeps 4) Bedroom 4: 1 superking double and 1 double sofabed (sleeps 4) bedroom 1, 2, 3 have fans for summer and elec
- Terrace
- Garden
- Self-catering
- Outside: Private 15 x 4.5 meter swimming pool. Elecric hard cover. Robot cleaning and latest technology in filtration ensuring minimum use of chemicals. Electric BBQ (due to Luberon National Park fire regulations, no naked flames are allowed outside) Large outdoor dinning room table with parasol Outdoor "sitting room" with armchairs, sofa and table 2 hammocks can be provided Outdoor Seating area (2 armchairs, 1 sofa and table) Table Tennis table and other outdoor toys Utility Room: Washing machine, iron, hoover Cleaning / Towels / Linen / Maid service: Egyptian cotton bed linen, bath towels and pool towels provided. The house is extensively cleaned before every visit. Additional mid-week cleaning (and babysitting) can be organised direct with the cleaner.


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Ramzy Baroud
- Separating fact from fiction in the many 'truths' on SyriaThe Japan TimesFrance
- Honor Aylan Kurdi by ending the Syrian warThe Japan TimesMiddle East
- United Nations Must End Hamas and PLO Stranglehold On Powercanadafreepress.comAustralia
- Divisions weaken PalestiniansThe Japan TimesMiddle East
- Arts in Gaza, police in Kenya, nuclear power in Japan, tech skills for students, lessons from Indiacsmonitor.com
- The 100 year IntifadaAl JazeeraMiddle East
- Blair to Gaddafi: I Just Called to Say... 'Find a Safe Place'Sputnik (EN)Europe
- Israel approves use of sniper fire against Palestinian rock-throwers – reportsRT.com English
- One Long Minute: Europe's Immigration CrisisThe Huffington Post (UK)
- More Deaths on Libyan Waters While ISIL Makes Ground On ShoreSputnik (EN)Mediterranean Sea
- Western Legacy in Libya Leaves a Hole Filled by Migrants Fleeing for EuropeSputnik (EN)
- Libya Calls for Airstrikes to Save Country from Islamic StateSputnik (EN)
- The rise and fall of Arab revolutionary discourseThe Japan TimesMiddle East
- The deep roots of Turkey's war on ISILAl Jazeera
- A dispossessed Palestinian advises a refugee from SyriaThe Japan TimesDamascus
- Racism and war in America and beyondPressTVKabul
- 'Palestinians not to abandon resistance'PressTV
- Israel, Egypt plotted phony ceasefirePressTVUnited States
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Play Airsoft in Louisiana + Add to My Sports
Airsoft in Louisiana
Sportsvite makes playing Airsoft in Louisiana hassle free.
- Find recreational Airsoft games and events in Louisiana
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Players & Teams in Louisiana
Kailee Kailee is looking for someone to go hiking with! not in the past month
Age: 25 · Location: New Orleans, LA
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Friends: John
Louisiana Airsoft Cities & Neighborhoods
Manage Airsoft Teams
Create and organize your own Airsoft team! Sportsvite has the web's best team management tools, and they just got even better, with overhauled rosters, schedules and more!
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Join Date: Mar 2004
Location: West MI
Posts: 2,899
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We are a family of Jesus loving urban-nesters living the granola life in a not-so-crunchy city. Our kids (DS 8, DS 7, DD 4) are home birthed and educated, and we just found out that a new Little will be added to our roost mid-April '14!
But I would far prefer to make it to September - we are in the midst of a remodel and I'm far from ready
We will be 37 weeks on friday and are down to weekly Dr's visits now....we go to the drs again today at 11:30....last visit she was were 50% effaced so it will be intresting to see if there is anymore progression. Dp last day of work is the 20th and mine the 22nd. I told dp she as to wait at least until then if she can hahaha. Our dr said he can induce when we are at 39 weeks if we havent gone by then or for sure at 40. Its so surreal to imagine that in 2 1/2 weeks I will be holding my first child!!!
"So let us be loving, hopeful and optimistic. And we'll change the world." - Jack Layton
One Mom, Three Kids. Life is Great.
Me. Full-time ,,x2 Momma. Part-time Doula & WAHM. Married to my bff USMC CWO2. Momma to the big M 11/06 -- the lil' C 09/08 and expecting our 3rd & last 12/12.
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text:
Strange Offload Behaviour - Most Offloads acting as Startup Offloads
p { margin-bottom: 0.25cm; line-height: 120%; }
I am trying to offload computation to two Xeon Phi's using a code similar to the following -
Window x64 17.0.1 compiler, Visual Studio 2015, and std::list checked iterators issue
I have encountered a number of mysterious crashes on Windows x64 using 17.0.1 in _DEBUG mode only. In _DEBUG mode on Windows, various STL functions are validated using what are called "checked iter
missing dll for viewing watch variables
Hello! When I try to use watch variables I get the message: "An error occurred while attempting to load an expression evaluator dll". I get this with FORTRAN XE Composer 2016 and the new 2017, de
Incorrect warning on STOP range ?
When using IVF with /stand:f08, and a statement like "STOP 2147483647", I get the following warning:
icc 17.0.1 crashes on valid C++ code on x86_64-linux-gnu (Segmentation violation signal raised)
Compiler version and platform:
Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 126.96.36.199 Build 20161005
icc 17.0.1 miscompiles valid C code at -O2 (only) on x86_64-linux-gnu
Compiler version and platform:
Intel(R) C Intel(R) 64 Compiler for applications running on Intel(R) 64, Version 18.104.22.168 Build 20161005
Documentation of Lapack ?GBSV()
The documentation of Lapack routine ?GBSV omits one important detail.
Is there an example of a simple neural network from start to finish using the MKL dnn primitives that are included in the MKL library?
KNL thread binding to tiles.
Intel® Software Innovator Program HomeThe Intel® Software Innovator program is a global developer community program.
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This download looks like an addon. You need to extract the downloaded zip and put the addon folder in your Garry's Mod addons folder. You should end up with a directory structure similar to below:
Don't know where the Garry's Mod folder is or how to extract zip files? See more useful installation tips.
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Beautiful collection of 7 antique prints. Each is hand colored.
These are highly collectible uniform studies and sell for up to $50 each.
Would look beautiful framed.
9 7/8" by 7 1/16"
Uniform dates 1806, 1813, 1814, 1807, 1810, 1800
All prints are in the photos above.
Each is signed in the print "E. Bucquoy" and dated 1907. The engraver is "J. Leroy", Paris.
All in excellent condition, there may be a spot of foxing here and there, barely visible. If you need photos of a specific print just let us know.
This a great collection of military engravings.
Another shopper has this item in their Cart or Wish List .
See something you like - make us an offer! We are clearing inventory and considering all offers!
We will consider offers on nearly all of our items - please contact us!
|Shipping & Handling :
Price for shipping to USA
change location
USPS Priority Mail


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2 Bedrooms Semi Detached House for sale
Roots estate agency offer to the market this delightful two bedroom semi detached home, overlooking open grasslands set within one of thatcham's most sought after developments.…
Thinking of selling or renting your property?
Get a instant valuation today!
Free Instant Valuation
Find out if you are charging enough rent or what your property would be worth if you were to sell now


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NAP Barstool
Kasper Salto for Fritz Hansen
Fritz Hansen NAP KS59 Bar Stool
Designed by Kasper Salto
Made in Denmark by Fritz Hansen
Dimensions (in): 22 w | 22.2 d | 43 h | seat: 30 h
The NAP KS59 is a bar stool about 2in (5cm) taller than the NAP counter stool.
The NAP KS59 Counter Stool has a high gloss back, and the front of the shell is matt with ripples to emphasize the geometry of the chair. The chair is also available with seat upholstery - assembled when delivered or purchased separately. The base is available in chromed steel.
Danish Design Store is an Authorized Dealer for the Fritz Hansen Collection. All products are licensed and designed in Denmark. Call Fritz Hansen Product Specialist at 800.688.0974 for questions or to place order by phone.
Fritz Hansen
Danish Design Store is an authorized USA dealer for all Fritz Hansen products.
Founded in 1872, the Republic of Fritz Hansen has a proud history of furnishing the world's...
Designed by Kasper Salto
Kasper Salto - the designer of the Ice™ Series, Little Friend™ and NAP™ - was trained as a cabinetmaker with...


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Skip to Content
The World's Greatest Music
Email the show or Text 61812
Leicester Square was turned into Middle Earth especially for the Royal Premiere of The Hobbit: An Unexpected Journey. Here are all the pics from the red carpet (which was actually green) of stars like Sir Ian McKellen, Martin Freeman, Cate Blanchett and director Peter Jackson - oh, and Prince William as well.
Picture 25 of 26
Don't forget to take some popcorn home for Kate, William!
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|Separate WC's
|Property type
|Minimum Stay
|2 nights
Your booking will be backed by our Book with Confidence Guarantee when you complete your reservation online and finalise payment on HomeAway.Learn more
Walk in the door of this home and the lake view is a show stopper. Stare out to the lake from any chair in the great room or walk out to the deck and immediately relax into vacation mode.
Awesome lake front home complete with 4 bedrooms, 2.5 baths, cathedral ceilings with open concept kitchen, living, and dining. Kitchen boasts granite counter tops, extended bar with 8 stools, wine fridge, and plenty of take-away mugs and cups for bringing your beverages down to the dock! Microwave, dishwasher, stainless steel fridge and stove provide all the comforts of home, but with the tranquil views that let you know you are officially on vacation. Wood-burning fireplace inside and great fire pit outside. The huge deck provides plenty of chairs and space for grilling, dining, and enjoying the sunsets over the water. Complete privacy on back deck with no neighbors to left or right. Gas grill with side burner provided.
Dock has spacious swim platform and is situated just inside a quiet cove so you can spend your days floating leisurely without the hassles of lots of boat traffic on big water. Want big water? Swim about 50 feet and you are in open water where you can look across to the South Carolina side. Water is DEEP and perfect for bringing your boat or rent one from the Marina in Hartwell. The Mary Anne launch is about 10 minutes away and you can tie up the boat to the swim platform. We also have a canoe that you can use. Please make sure to wear a life jacket! Plenty of shore line for skipping rocks or building red clay castles :)
Like wild life? Watch the numerous bird species at the bird feeder, catch a glimpse of a red fox, and you're sure to see herons and cranes when down at the dock.
Further on the comforts of this vacation dream house: Hi-speed wireless internet access. Cable package and netflix capabilities on the 50in Flatscreen. Comfortable queen beds in all 4 rooms, towels and linens furnished.
Easy day trips to Clemson, Athens (UGA,) & Asheville. Atlanta is just a short 1.5 hours away also. You can even get to Clemson by boat!
15 minutes to Grocery store (Ingles,) WalMart, and downtown Hartwell with plenty of restaurants, shops, and the marina. Dollar General is less than 10 minutes away if you need just a couple of quick things or need to refresh the ice in your cooler.
Lavonia Antique market is a great way to spend a few hours if you need to get out of the sunshine.
Cateechee Golf Course/ Waterfall Grill about 20 minutes away for dining and golfing
Have more questions? Just ask us. We're here to help you to enjoy this home as much as we do!
We enjoyed a lovely fall weekend here. House is well-stocked and a nice set up for our family of five.
The house is set up well. The kitchen, living room and dining room area is wide open with a huge sliding glass door and windows across the back. You always have a view of the lake from here. There are two Jack and Jill bathrooms connecting two nice bedrooms on both sides of the house and there's a third bathroom in the laundry room. The kitchen has ample counter space where my grandchildren could sit and eat. There is a relaxing porch area with tables and chairs to enjoy anytime of the day. The dock and lake area is wonderful. It's in a cove protected from boats but not far from the open lake. We went swimming everyday. We enjoyed fishing from the dock. My daughter and two teen age granddaughters loved the board games and were thankful for the wifi. We watched movies, baked cookies and brownies and played cards. Everyone was happy to stay at the house. On Friday, my nine year old grandson told me this spot was perfect. He said you can swim and dive into the water here. He could fish plus he could play all his games with the wifi. The best of both worlds! It was a wonderful week enjoyed by all. Thank you!
We truly enjoyed our stay, we found the house to be very comfortable, everything we needed to make our stay enjoyable. There was plenty of space in the house and on the lot, so you definitely have room to move around. While we didn't have enough time to really take advantage of the great location right on the lake, we did get a chance to take the kayak for a quick paddle on the lake. Definitely recommend this house for those looking to get away!
This house surpassed expectations! Easy to get to in a cute location. Pictures don't do it justice! And we had awful weather but the house is stocked with games, books and Apple TV! Not to mention the most comfortable bed I have ever slept in. We stayed here for a Clemson game and while it's a bit of a distance from there. The price point is perfect and when the weather was nice we enjoyed sipping our morning coffee from the dock! Will certainly be back! Also owners are very responsive and helpful, even asked us to text when we got in so they knew we arrived safely. Couldn't have asked for anything better! Super happy we found this gem! Thank you again Jamie!
My family and I thoroughly enjoyed the house, the lake and the jumping off the dock at night! Everything was first class in the house and very comfortable to relax inside due to comfortable layout.
The house was perfect for my family, love the views and the layout of the house with the jack and jill bathrooms between the bedrooms. I don't enjoy cooking but with the large open counter tops, it made it much more fun to slice/dice some of the wonderful produce from the local Ingle's. The water was perfect, dock is big enough to fish from, pull up a boat and quiet enough to just float in the cove. Hartwell is much better than Lanier and not nearly as crowded. The house was well stocked with amenities, very clean and very well maintained, my three year old felt right at home in this warm, inviting lake house. Wifi worked great and we will definitely be back.
|Rental Period
|Minimum Price
|Additional Nights
|Weekend Night
|Event Price
My Standard Rate
2 night minimum stay
for 2 nights
|Refundable Damage Deposit


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Double Deception
Release Date: January 1st, 1993
Not Yet Rated|1 hr. 38 min.
Plot Summary
An ex-prostitute (Sally Kirkland) and a police detective (Burt Young) work on a murder case with a Venice Beach, Calif., private eye (James Russo).
Cast: James Russo, Sally Kirkland, Burt Young,
Director: Jan Egleson
Genres: Crime drama


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- Home
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Apologies for not giving an update sooner, but this vintage has been one to test the limits of our abilities. Almost 80% of our fruit has come in over the past two weeks, including all the whites and reds at the same time. This is a result of a very warm summer and the heat wave over the last two weeks in this region. The hot temperatures and amount of fruit has pushed our cooling system to the limit which helps regulate the ferment, resulting in late nights closely monitoring tank temperatures. Thankfully the coffee machine has been working very reliably!
To add to this pressure there have been several players sidelined or carrying injuries. Our basket pressing guru, Andy, has powered through a persistent ligament injury in his shoulder. One of our leading hands, Simon, has spent the past week in hospital with a blood infection. I have been on crutches until two weeks ago after having a knee repair done in early January. To add to this, there have been toothaches, skin irritations, and other weird ailments to challenge us. But power on we shall.
Despite all this we are very happy with the quality of the fruit with beautiful delicate flavours in the Riesling and Chardonnay and lots of richness and spice coming through in the reds. We know all this hard work and sleep deprivation will pay off in several months, after we produce some elegant and classic Great Western wines for you all.
Until next week,
Baacco The Community Based Wine Marketplace
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Senior boys' high school basketball teams aren't going to win many games by scoring just three points in a quarter.
That was the offensive production of the Bishop Tonnos Titans during their 57-41 loss to the visiting St. Mary Crusaders on Thursday (Nov. 28). The Crusaders went on an 18-3 run down the stretch to break open the Hamilton-Wentworth Catholic Athletic Association contest which St. Mary led by one point after three quarters.
With the victory, St. Mary improved to 2-0. It was the season opener for Tonnos.
Elsewhere, the defending champion Cardinal Newman Cardinals evened their record at 1-1 with a 60-44 decision over the St. Jean de Brebeuf Braves (1-1) and the St. Thomas More Knights (1-1) defeated the Bishop Ryan Celtics, 54-33. The loss dropped the Celtics to 0-2.
"When you score three points in the fourth quarter, that's attributed to them working hard and wearing us down," Tonnos coach Luc DiDiomede said. "They're a well-coached, disciplined team. When they play defence like that it's tough to score. They're a quality squad. They dictated the game."
Tonnos has a young lineup and, according to DiDiomede, the team will have to adjust to the loss of several veteran big players from last year's squad. St. Mary, in comparison, has a more veteran lineup with a pair of athletic 6-foot-4 post players.
"We'll have some growing pains," DiDiomede said, "but it's going to be fun to watch. I think we can do OK. We'll be in the middle of the pack."
Veteran Adrian Browne scored 15 points for the Titans – five three-point baskets, all during the first three quarters. Guard Adam Carnicelli added 12 second-half points for Tonnos.
The top point-getter for the Crusaders was Mathew Elcock, who poured in 26 points.
"He works hard on his shot all year round," St. Mary coach Pat Papalia said of Elcock, "and it shows in the game."
Back-to-back mid-range jump shots by Elcock broke a 39-39 tie. And 10 of his points came in the final quarter.
"We definitely started competing and playing on defence," Elcock said of the Crusaders finishing kick.
Said DiDiomede: "Elcock is a stellar player. Hats off when a kid can shoot like that. Nothing beats veteran leadership."
Brandon Francois Jean-Pierre added 11 points for the Crusaders, while his teammates Shawn Carey and Macbeth Madziba chipped in with nine and seven points, respectively.
"If we could guarantee we would play like we did for that five minute stretch in the fourth quarter, we would be a good team," Papalia said.
In its game at Brebeuf, Newman was led by guard David McCulloch's 14 points. Rommel Calura replied with 11 for the Braves.
At Bishop Ryan, the Knights got 19 points by Xavier Ellis and 10 by Jaylen Clarke. The top score for the Celtics was Chris Lloyd, with nine.


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Boru Pratt McCullagh Model
LILIClothing Designer Female London, England, United Kingdom
My Website: snapshots of 2nd yearMy MM URL: http://www.modelmayhem.com/lili_maria
Mayhem # 2913062
About MeHi everyone,
I'm a fashion design student currently studying BA Menswear at London College of Fashion. I signed up as I constantly need models (professional and amateur) for my clothing creations for both college and independent work.
ask me anything as I'm happy to work for people although I'm primarily here to recruit creatives myself.
Have you worked with LILI? Add Credits for LILI! >>
Boru Pratt McCullagh Model
NikolayRoz... Model
danielmoly... Model
Ella Sadika Photographer
amy hillyard Clothing Designer
Leonardo Taiwo Model
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text:
Out of The Past.
Postgate, R. W.
• Terms • Ask a Question
New York: Vanguard Press, 1926. 12mo. 110 pp. Cover lightly worn at eges and soiled. Pages discolored at edges, but clean and tight. A collection of short pieces about the French Revolution. Very Good Cloth (Item ID: 26947)
- More: HISTORY: EUROPEAN
- By This Author: Postgate, R. W.


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What are you most proud of? I am a very impatient knitter. I am proud that I actually ripped out when I found that I had goofed a few rows back instead of throwing it in a bag and calling it quits because I really got great satisfaction out of completing this. What advice would you give someone starting this project? Hang in there. Don't give up if it doesn't look perfect. Mine looked a little funny at the line where I switched from circular to DPNs but Stephanie told me that blocking it with my steam iron might take care of it. She was absolutely right! After I made this one, I immediately had to make another and put a tassle on it. This hat knits up fast. I highly recommend the class for making hats that fit. I made two so far and both fit perfectly.
No completed Q&As yet.


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Post Contents List
Step By Step Tutorial How to Update Galaxy S2 I9100 Official ICS 4.0.4 XWLPM Firmware
Cautions Before The Format Root Soft or Hard Reset ::
- For Completing the UpdateHow to Install clockworkmod recovery on Redmi 2. Read more ... » GalaxySamsung Android for Galaxy, Note and Tab Series Secret Codes. Read more ... » S2 I9100 Official ICS 4.0.4 soft resetSamsung Secret Codes ALL SAMSUNG SECRET CODES NEW Hidden Codes part -1. Read more ... » or hard resetSamsung Secret Codes ALL SAMSUNG SECRET CODES NEW Hidden Codes part -1. Read more ... » CodeSamsung Secret Codes ALL SAMSUNG SECRET CODES NEW Hidden Codes part -1. Read more ... » Process it took some time to complete so First charge your battery to 100% full,
- backup your important data if possible and in most cases take out SIM and SD card. Because your data cant be recovered from phone if once lost during the reset process.
- SuperGeek Suggest Backup from your RootHow to Root Micromax Canvas Fun A63. Read more ... » Update Galaxy S2 I9100 Official ICS 4.0.4 For all of your data, a backup should be done on an external device, hard drive, raid system or media.
- Because It is impossible to recover your data from your Formatted Update Galaxy S2 I9100 Official ICS 4.0.4 ,after doing a FormatSamsung Secret Codes ALL SAMSUNG SECRET CODES NEW Hidden Codes part -1. Read more ... » or hard reset, so online backup is always important.
- So keep backup first
Warning! for Format & Reset
- It's all your responsibility to Hard Reset or Format or Root or UnlockSamsung Secret Codes ALL SAMSUNG SECRET CODES NEW Hidden Codes part -1. Read more ... » your How to Root Galaxy TabSamsung Galaxy Tab Android Powered Full feature and Specifications with Price. Read more ... » 10.1 Wi-Fi P7510 phone we are not responsible for any kind of loss to you or your Mobile.
- By performing "Factory ResetHow to Format Samsung Galaxy Grand i9080,i9082,Premier hard reset Code. Read more ... »", all user data will be ERASED. You MUST took a proper backup PRIOR to running factory reset & Web update.
- If your Format How to Root Update Galaxy S2 I9100 hard reset isn't responding
How to Format Update Galaxy S2 I9100 Mobiles
- Disable or remove the security suites such as antivirus or firewall from your Computer and LGHow to Root LG Optimus L3 E400. Read more ... » device so that they won't interrupt the procedure.
- Go through the path 'Settings > Applications > Development > USB debugging' and turn on to Enable USB Debugging option.
- Download USB drivers for all Samsung Galaxy Devices from 32-bit here and 64-bit here.
Steps and Procedure to Update Galaxy S2 I9100 :
- Download the XWLPM Firmware zip package file from here to your PC.
- The file name is I9100XWLPM_I9100OXELP8_SER.zip and size will be 510 MB.\
- Extract it by using either winzip or winrar. Once extracted the file,
- you will get file with name like this I9100XWLPM_I9100OXELP8_I9100XXLQ6_HOME.tar.md5.
- Download Odin3-v 1.85 flash tool from here to your PCHow to Automatically Delete Internet Explorer History and all temporary file on exit. Read more ... ». Extract the Odin package then you get odin3-v 1.85.exe inside the folder.
step 2:;
- Double click to launch the odin3-v 1.85.exe application on your Computer.
- It's'time to switch off your Tab to enter into download mode by pressing and holding Volume Down + Home + Power buttons simultaneously till you see a warning message on your screen. Then, press the Volume up button to get into download mode.
6. After entering in the download mode, you need to connect your Tab to the Computer via USB data cable when Odin is opened in your Computer. On connecting the device, the ID: COM section will turns Yellow in colour which means the connection has been made successfully.
- 7. Now click on 'PDA' and select the I9100XWLPM_I9100OXELP8_I9100XXLQ6_HOME.tar.md5 file which you have got from the extracted folder in step 2.
- 8. After selecting the file, click on 'Start' button in Odin to start flashing the firmware update.
- It take around 6-7 minutes to complete the update.
- 9. after complete the device will reboot automatically and you will see a green color Pass message in Odin. now just disconnect your device from the Computer.
- 10. Reboot your device in recoveryHow to Install clockworkmod recovery on Redmi 2. Read more ... » mode by pressing and holding press and hold :: Home + Volume Up + Power keys together. In recovery mode, you need to select 'wipe data / factory reset' and then 'wipe cache partition' to clear cache from your device.
NoteSamsung Android for Galaxy, Note and Tab Series Secret Codes. Read more ... »: If your Any error comes like reboot etc, then remove the battery and reinstall the same.
- 11. Select Go Back to menue 'reboot system now' option to restart your Galaxy S2 I9100 Official ICS 4.0.4 . After restarting the device, no longer you will face any loop problem.
- Note: If your Odin hangs in any step or it display the FAIL message then you need to unplug your device from the Computer and take out the battery and place it back to its previous position, close the Odin and repeat the process again from step 2
That's all now the format,root, unlock, Update Galaxy S2 I9100 Official ICS 4.0.4 XWLPM Firmware hard reset Code device is formatted perfectly without any problems. In case if you find any issues with above procedure comment here. SuperGeekForum will try to solve your problem


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Creamy BBQ Dipping Sauce
Total Time
Prep 5 mins
Cook 0 mins
This sauce is great for dipping with my Crunchy Potato Wedges or raw veggies and it's quick and easy to prepare. It will keep in the refrigerator up to two weeks.
Ingredients Nutrition
- 3⁄4 cup mayonnaise
- 1⁄4 cup barbecue sauce
- 1 garlic clove, minced
- 3 tablespoons cider vinegar
- 1⁄4 teaspoon pepper
- 1⁄8 teaspoon salt
- Combine all ingredients.
- Serve.
Most Helpful
This was nice with some wedges but maybe a little too much tang for our tastes, a little less vinegar would have suited us better but still enjoyed. thanks for posting!