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Because cyberhackers find easy points of entry into consumers' accounts, it has become increasingly clear to the SEC and advisory firms' IT departments that a computer network is only as strong as its weakest link.
"We try to preach to our users, 'verify, verify, verify,'" Mr. Sundberg said. "Never download an attachment or accept a weird friend request if it can't be verified."
For example, he said, if an advisory firm employee receives a phone call and the person at the other end of the line says he's from Microsoft tech support and has noticed a computer virus in the firm's system, the employee should hang up immediately and not let the unidentified caller connect to the firm's system.
"Or, if you get an e-mail from somebody saying they've been mugged on vacation or have lost their wallet and passport or some other doom-and-gloom scenario, most likely their e-mail has been hacked," Mr. Sundberg said. "Contact that person another way, not through email, whether on a home land line or cellphone."
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An integral part of an effective security protocol is the appropriate use of security systems, equipment, and applicable technology.
"It's important to understand that there must be an integrated approach to the use of security systems and security operations," says Robert Koverman, a senior consultant at SAKO & Associates, Arlington Heights, IL. "In today's business world, proactive and integrated security practices are crucial to a company's success."
A recent survey, commissioned by the Washington, D.C.-based Building Owners and Managers Association (BOMA) International and Urban Land Institute (ULI), showed that the security measures most widely used before September 11 included building alarm monitors, lobby security controls, surveillance cameras, and employee background checks.
After 9/11, the single security upgrade most frequently used by survey respondents was tighter vendor security. Respondents reported they have established requirements for vendor identification, vendor check-in, and requests that vendors perform employee background checks within their own operations.
That's not to say companies aren't upgrading their security technology, too. Here's a look at some other security technologies in use today:
These systems provide protection by establishing identity verification at designation locations, usually at the perimeter of a building or at entrances to sensitive rooms or areas.
These systems are used to alert a security department to possible incidents. Once alerted, they can follow a prescribed set of procedures for reaction.
"These systems, although noted separately, are best used when integrated with one another," says Koverman, when discussing both CCTV and electronic intrusion detection systems.
Since 9/11, some buildings also are installing detection technology in addition to other security systems, Koverman notes. Such systems include walk-through metal detectors at strategic entry points to a building and X-ray machines. However, statistics from the BOMA/ULI survey show that perimeter barriers were cited as the least common security practice prior to 9/11 and that less than 6 percent of respondents added barriers after the attacks.
While technology contributes to an enhanced security presence, you need to take further internal steps beyond installing a good system, Koverman says. "An effective program involves the use of well-trained security personnel, educated employees, and the development of well-thought-out security plans and procedures," he says. "This integrated approach also mandates periodic drills to test the effectiveness of security plans and procedures."
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text:
Patent application title: SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT
Lee D. Whetsel (Parker, TX, US)
IPC8 Class: AG01R313177FI
USPC Class:
Class name: Pulse or data error handling digital logic testing built-in testing circuit (bilbo)
Publication date: 2010-11-25
Patent application number: 20100299571
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A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be
controlled and accessed from a test bus (13) via a single TAP interface
1. An integrated circuit comprising:A. a serial data in lead:B. a mode
select lead;C. a select lead; andD. TAP access circuitry having a serial
data input connected with the serial data in lead, a mode select input
connected with the mode select lead, a select input connected with the
select lead, and gated mode select outputs, the access circuitry
including gating circuitry having a first input coupled with the serial
data in lead, a second decoded state machine signal input, a third input
coupled with the mode select input, a fourth input connected with the
select lead, and an output connected with a gated mode select output.
[0001]This application is a divisional of prior application Ser. No.
12/817,353, filed Jun. 17, 2010, currently pending; [0002]Which was a
divisional of prior application Ser. No. 12/560,717, filed Sep. 16, 2009,
now U.S. Pat. No. 7,765,447, granted Jul. 27, 2010; [0003]Which was a
divisional of prior application Ser. No. 11/936,884, filed Nov. 8, 2007,
now U.S. Pat. No. 7,610,536, granted Oct. 27, 2009; [0004]Which was a
divisional of prior application Ser. No. 10/962,921, filed Oct. 12, 2004,
now U.S. Pat. No. 7,310,756, granted Dec. 18, 2007; [0005]Which was a
divisional of application Ser. No. 09/938,254, filed Aug. 22, 2001, now
U.S. Pat. No. 6,804,725, granted Oct. 12, 2004; [0006]Which was a
divisional of application Ser. No. 09/458,313, filed Dec. 10, 1999, now
U.S. Pat. No. 6,324,614, granted Nov. 27, 2001; [0007]Which was a
divisional of application Ser. No. 08/918,872, filed Aug. 26, 1997, now
U.S. Pat. No. 6,073,254, granted Jun. 6, 2000; [0008]Which claimed
priority from Provisional Application No. 60/024,884, filed Aug. 30,
[0009]The invention relates generally to evaluation of the functionality of electronic integrated circuits and, more particularly, to improvements in the control and design of test access ports (TAPs) within integrated circuits.
[0010]IS The IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE STD 1149.1) is a well known IEEE test standard that provides scan access to scan registers within integrated circuits (ICs), and is hereby incorporated herein by reference. FIG. 12 shows a schematic of the 1149.1 test logic. The test logic comprises a TAP controller 120, an instruction register, and plural test data registers. The TAP controller is connected to test mode select (TMS), test clock (TCK), and test reset (TRST*) pins. The TAP controller responds to control input on TCK and TMS to scan data through either the instruction or data registers, via the test data input (TDI) and test data output (TDO) pins. TRST* is an optional pin used to reset or initialize the test logic, i.e. TAP controller, instruction register, and data registers. The inputs to the instruction and data registers are both directly connected to the TDI input pin. The output of the instruction and data registers are multiplexed to the TDO pin. During instruction register scans, the TAP controller causes the multiplexer 121 to output the instruction register on TDO. During data register scans the TAP controller causes the multiplexer 121 to output the data register on TDO. The instruction scanned into the instruction register selects which one of the plural data registers will be scanned during a subsequent data register scan operation. When the TAP controller is scanning data through the instruction or data registers, it outputs control to enable the output stage to output data from the TDO pin, otherwise the TAP controller disables the output stage.
[0011]FIG. 13 shows how four ICs, each IC including the TAP controller, instruction register, and data registers of FIG. 12, would be connected at the board level for serial data transfer (TDI, TDO) and parallel control (TMS, TCK).
[0012]FIG. 14 shows the state diagram operation of the FIG. 12 TAP controller. The TAP controller is clocked by TCK and responds to TMS input to transition between its states. The logic state of TMS is shown beside the paths connecting the states of FIG. 14. The Test Logic Reset state is where the TAP controller goes to in response to a power up reset signal, a low on TRST*, or an appropriate TMS input sequence. From Test Logic Reset the TAP controller can transition to the Run Test/Idle state. From the Run Test/Idle state the TAP controller can transition to the Select DR Scan state. From the Select DR Scan state, the TAP controller can transition into a data register scan operation or to the Select IR scan state. If the transition is to the data register scan operation, the TAP controller transitions through a Capture DR state to load parallel data into a selected data register, then shifts the selected data register from TDI to TDO during the Shift DR state. The data register shift operation can be paused by transitioning to the Pause DR state via the Exit1 DR state, and resumed by returning to the Shift DR state via the Exit2 DR state. At the end of the data register shift operation, the TAP controller transitions through the Update DR state to update (output) new parallel data from the data register and thereby complete the data register scan operation. From the Update DR state, the TAP controller can transition to the Run Test/Idle state or to the Select DR Scan state.
[0013]If the Select IR Scan state is entered from the Select DR Scan state, the TAP controller can transition to the Test Logic Reset state or transition into an instruction register scan operation. If the transition is to an instruction register scan operation, Capture IR, Shift IR, optional Pause IR, and Update IR states are provided analogously to the states of the data register scan operation. Next state transitions from the Update IR state can be either the Run Test/Idle state or Select DR Scan state. If the TAP controller transitions from the Select IR Scan state into the Test Logic Reset state, the TAP controller will output a reset signal to reset or initialize the instruction and data registers.
[0014]FIG. 15 shows that state transitions of the FIG. 12 TAP controller occur on the rising edge of the TCK and that actions can occur on either the rising or falling edge of TCK while the TAP controller is in a given state.
[0015]The term TAP referred to hereafter will be understood to comprise a TAP controller, an instruction register, test data registers, and TDO muxing of the general tyme shown in FIG. 12, but differing from FIG. 12 according to novel features of the present invention described with particularity herein. The 1149.1 standard was developed with the understanding that there would be only one TAP per IC. Today, ICs may contain multiple TAPs. The reason for this is that ICs are being designed using embedded megamodule cores which contain their own TAPs. A megamodule is a complete circuit function, such as a DSP, that has its own TAP and can be used as a subcircuit within an IC or as a standalone IC. An IC that contains multiple megamodules therefore has multiple TAPs.
[0016]In example FIG. 1, an IC 10 containing four TAPs is shown. TAP1 is shown connected to the boundary scan register (BSR) to provide the 1149.1 standard's conventional board level interconnect test capability. TAP1 can also be connected to other circuitry within tithe IC that exists outside the megamodules. TAP2 is an integral part of megamodule MM1. Likewise TAP3 and TAP4 are integral parts of megamodules MM2 and MM3. Each TAP of FIG. 1 includes a conventional 1149.1 TAP interface 11 for transfer of control (TMS, TCK and TRST) and data (TDI and TDO) signals. However, the 1149.1 standard is designed for only one TAP to be included inside an IC, and for the 1149.1 TAP interface of this one TAP to be accessible externally of the IC at terminals (or pins) of the IC for connection via 1149.1 test bus 13 to ail external test controller.
[0017]It is therefore desirable to provide an architecture wherein all TAPs of an IC can be controlled and accessed from an external 1149.1 test bus via a single externally accessible 1149.1 TAP interface.
[0018]The present invention provides an architecture which permits plural TAPs to be selectively accessed and controlled from a single 1149.1 TAP interface. The invention further provides access to a single register via any selected one of a plurality of TAPs. The invention further provides a TAP controller whose state machine control can be selectively overridden by an externally generated override signal which drives the state machine synchronously to a desired state. The invention further provides a TAP instruction which is decodable to select an external data path. Also according to the invention, sequential access of TAPs from a single 1149.1 TAP interface permits test operations associated with different TAPs to timewise overlap each other.
[0019]FIG. 1 illustrates a test controller connected to an integrated circuit having multiple TAPs therein;
[0020]FIG. 2 illustrates an integrated circuit having multiple TAPs therein according to the present invention;
[0021]FIG. 3 illustrates the TAP Linking Module of FIG. 2 in greater detail;
[0022]FIG. 4 illustrates the TLM TAP Controller of FIG. 3 in greater detail;
[0023]FIG. 5 illustrates another exemplary integrated circuit having multiple TAPs therein according to the present invention;
[0024]FIG. 6 illustrates in greater detail the TAP Linking Module of FIG. 5;
[0025]FIG. 7 illustrates TAP4 of FIGS. 2 and 5 in greater detail;
[0026]FIG. 8 illustrates multiplexing circuitry associated with the scan input of TAP4 of FIG. 5;
[0027]FIG. 9 shows a state diagram associated with the TAP controller of FIG. 7;
[0028]FIG. 9A illustrates in more detail a portion of the TAP controller of FIG. 7;
[0029]FIGS. 10-11 are timing diagrams which illustrate examples of how the TAPs of FIGS. 2 and 5 can be synchronously linked to and unlinked from the test bus of FIGS. 2 and 5;
[0030]FIG. 12 illustrates the architecture of a conventional 1149.1 TAP;
[0031]FIG. 13 illustrates a plurality of integrated circuits connected in a conventional manner for 1149.1 testing;
[0032]FIG. 14 is a state diagram associated with the conventional TAP controller of FIG. 12;
[0033]FIG. 15 is a timing diagram which illustrates when state changes and other actions can occur in the conventional TAP architecture of FIG. 12;
[0034]FIG. 16 illustrates in greater detail a portion of prior art FIG. 12;
[0035]FIG. 16A illustrates conventional instructions associated with the architecture of FIG. 16;
[0036]FIG. 17 illustrates in greater detail a portion of TAP4 from FIG. 7; and
[0037]FIG. 17A illustrates a set of instruction pairs associated with the architecture of FIG. 17.
[0038]FIG. 2 shows an exemplary IC according to the invention, including a TAP Linking Module (TLM) 21 which is coupled to each TAP via select (SEL1-4) and enable (EN1-4) signals, and to an externally accessible 1149.1 interface 20 including TDI, TCK, TMS, TRST*, and TDO pins. The TAPs are connected to the TCK and TMS pins and to the Reset output from the TLM. The SEL1-4 signals are outputs from the TAPs to the TLM, and the EN1-4 signals are output In from the TLM to the TAPs. Each TAP's select signal is output in response to a special instruction scanned into its instruction register. The instruction sets the select output from the TAP high, which causes the TLM to be selected as the data register scan path between the IC's TDI and TDO pins 26 and 27. A conventional data register scan operation is used to capture data into and then shift data through the TLMI from TDI to TDO. During such a TLM scan operation, the TLM Select output signal from TLM makes a connection from the TLM's TDO output 25 to the IC's TDO output 27, via the multiplexer 3SMUX. Also during a TLM scan operation, an Enable output from the currently enabled TAP (one of Enable 1,2,3,4) enables a TDO output buffer (in 3SMUX) via OR gate 29. This is analogous to enabling the output stage in FIG. 12. Following the TLM scan operation, TLM outputs EN1-4 signals to the TAPs and TAPSEL0-1 signals to the multiplexer 23 to establish a TAP link configuration. The data scanned into the TLM selects one of the four outputs EN1-4 to be active to enable the corresponding one of the TAPs. Also the TAPSEL0-1 and TLM-Select signals will cause the TDO of the enabled TAP (one of TDO1-TDO4) to be connected to the IC's TDO pin 27.
[0039]From this description it is seen that the TLM 21 operates to selectively enable one of the TAPs to be accessed via the IC's 1149.1 test pins. The circuit coupled to the enabled TAP (BSR, MM1, MM2, MM3) can therefore be accessed directly from the 1149.1 test pins. A presently enabled TAP can select and scan the TLM 21 which in turn will select and enable another TAP. When another TAP is enabled, the previously enabled TAP is disabled and remains so until it is enabled again by the TLM. The EN1-4 inputs to the TAPs can enable or disable the TAPs in many ways. For example, the EN1-4 inputs could simply be used to gate TCK on and off. Alternatively and preferably the EN1-4 inputs could be included in the designs of the TAP controller state machines to keep the TAP in its Run-Test/Idle state when disabled. This preferred method of using the EN1-4 signals is described below in connection with FIGS. 9 and 9A.
[0040]FIG. 3 shows one circuit example implementation of TLM 21. The circuit comprises a TLM TAP controller 31, a 2-bit shift register, decode logic, and a link update register. The TLM TAP controller 31 is always enabled to follow the test bus protocol on the TCK and TMS pins, i.e. the TLM TAP controller is always synchronized to the state of the 1149.1 test bus 13 connected to the TCK and TMS pins. However, the outputs of the TLM TAP controller (i.e. TLM-ShiftDR, TLM-ClockDR, TLM-UpdateDR, and TLM-Select) are only enabled during a data register scan operation and only if the select input (SEL1-4) from the currently enabled TAP is high.
[0041]If the currently enabled TAP inputs a high select input at one of SEL1-4, the TLM TAP controller 31 will respond to TCK and TMS to output control on TLM-ShiftDR, TLM-ClockDR, and TLM-Select to capture and shift data through the 2-bit shift register, and then output TLM-UpdateDR control to update the decoded output from the shift register to the link update register. This capture, shift, and update operation is a well known TAP controller scan operation taught in IEEE STD 1149.1 and shown in FIGS. 5-1 and 5-7 thereof. During this scan operation the TLM TAP controller outputs TLM-Select control to couple the TDO output of TLM 21 to the IC's TDO pin 27, via the 3SMUX of FIG. 2. Also during the scan operation, the output of the 3SMUX is activated by the enabled TAP (one of Enable1-4) to output data on the IC's TDO pin 27. The data from the link update register is output as EN1-4 and TAPSEL0-1 to enable the desired TAP and its TDO connection (one of TDO1-4) to the IC's TDO pin 27. The active one of enable signals EN1-4 qualifies a corresponding one of select signals SEL1-4 at one of AND gates 33-36, whereby the corresponding one of SEL1-4 can be input to the TLM TAP controller via the OR gate 37. Select signals from disabled TAPs are gated off by the AND gates associated with the inactive ones of enable signals EN1-4. The decode from the 2-bit shift register allows each of TAP1, TAP2, TAP3, or TAP4 to be individually selected, accessed, controlled and scanned from the 1149.1 pins at 20.
[0042]Exemplary FIG. 4 shows a detail view of the TLM TAP controller 31. The TLM TAP controller comprises the conventional 1149.1 TAP controller 120 of FIG. 12 and gating to enable or disable the TLM-Select. TLM-ClockDR, TLM-ShiftDR, and TLM-UpdateDR outputs of the TLM TAP controller. After power up reset, the 1149.1 TAP controller 120 is always synchronized to the state of the 1149.1 test bus. Note that the output signal 39 of the FIG. 3 AND gate 38 is connected to 1149.1 TAP controller 120 at input node 123 thereof where the TRST* signal would conventionally be connected (contrast FIG. 12). The 1149.1 TAP controller's conventional outputs are gated off by the OR gates 41 and 43, and AND gates 45 and 47 so that the state of the TLM's shift register and link update register are not disturbed during data register scans occurring while the SEL input from OR gate 37 (FIG. 3) is low. TLM-Select and TLM-ClockDR are high while SEL is low, and TLM-UpdateDR and TLM-ShiftDR are low while SEL is low. These output conditions match what the conventional 1149.1 TAP controller 120 would output on the analogous signal types (i.e. Select, ClockDR, ShiftDR, UpdateDR) when data register scans are not being performed. When the SEL input is high, the gated outputs from the TLM TAP controller follow the conventional 1149.1 TAP controller outputs. The Reset output from the TLM TAP controller is always enabled to output the conventional 1149.1 Reset signal to the TAPs within the IC. The TLM TAP controller can be viewed as the master TAP controller in the IC since it has reset authority over all other TAPs.
[0043]When the TLM TAP controller is reset (i.e. forced to the Test Logic Reset state of FIG. 14) by the power up reset circuit, or by activation of the TRST* pin, or by an appropriate TMS sequence, it outputs a Reset signal. Either the power-up reset circuit or the TRST* signal can drive the output 39 of AND gate 38 (see FIG. 3) low and thereby force the Test Logic Reset state. An appropriate sequende of logic 1's on TMS can also put the TLM TAP controller in the Test Logic Reset state (see FIG. 14). Internal to the TLM 21, the Reset signal loads the link update register with EN1 and appropriate TAPSEL0-1 control (see FIG. 3) to enable and link TAP1 between the TDI pin 26 and 3SMUX (see FIG. 2). TLM Select is driven high when controller 31 is in the Test Logic Reset state because the Select output from the conventional 1149.1 TAP controller 120 goes high in the Test Logic Reset state. When TLM Select is high, the output of MUX 23 is connected to TDO pin 27 via 3SMUX. By initially selecting TAP1 to be active the IC appears to test bus 13 to be operating as would a one-TAP IC described in the 1149.1 standard. Following the initial selection of TAP1, the TLM can be selected by TAP1 and then scanned to select any other TAP in the IC to become the active TAP. External to the TLM 21, the Reset signal initializes all the TAPs to the Test Logic Reset state of FIG. 14.
[0044]FIG. 5 shows another example IC according to the invention, including a TAP Linking Module (TLM 51) which is coupled to TAPs, 1149.1 test pins, and multiplexers similarly to FIG. 2. Additionally, the TLM 51 is coupled to the TAPs 2-4 via Link Control (LC2-4) signals. The operation of TLM 51 is similar to TLM 21 of FIG. 2, except: (1) the TLM 51 can be loaded with data to enable more than XS one TAP at a time in the IC; and (2) the TLM 51 outputs link control to the TAPs to allow linking the TAPs together in different arrangements within a single scan path between the TDI 26 and TDO 27 pins. The linking and enabling of multiple selected TAPs permits the circuits associated with the TAPs (BSR, MM1, MM2, MM3) to be accessed at the same time.
[0045]In FIG. 5 it is seen that TAPs 2-4 have multiple scan inputs. In particular, the TAPs 2-4 have scan inputs as follows: TAP2 has TDI pin 26 and TDO1; TAP3 has TDI pin 26, TDO1 and TDO2; and TAP4 has TDI pin 26. TDO1, TDO2 and TDO3. This is to allow for serially concatenating enabled TAPs together in different ways. For example TAP1 and TAP4 can be enabled at the same time and linked together into the serial path between TDI 26 and TDO 27. In this arrangement, TAP1 and TAP4 can participate together during test while TAP2 and TAP3 are disabled. The Link Control signals LC2-4 to TAPs 2-4 select the appropriate scan input to the TAPs to make a particular serial link between TAPs. TLM 51 can provide the following TAP linking arrangements between TDI 26 and TDO 27:
[0046]TAP1 Links: TAP1, TAP1&2, TAP1&3, TAP1&4, TAP1,2&3, TAP1,2,&4, TAP1,2,3&4, TAP1,3&4
[0047]TAP2 Links: TAP2, TAP2&3, TAP2&4, TAP2,3&4
[0048]TAP3 Links: TAP3, TAP3&4
[0049]TAP4 Links: TAP4
[0050]The more scan inputs per TAP, the more possible linking arrangements. For example, TAP3 could also have TDO4 as a scan input in addition to those shown in FIG. 5. The multiplexing circuitry associated with the multiple scan inputs of the FIG. 5 TAPs is not shown in FIG. 5 for clarity, but an example is described below relative to FIG. 8.
[0051]FIG. 6 shows one circuit example implementation of the TLM 51. The TLM 51 is similar to the TLM 21 of FIG. 3 except: (1) the shift register is longer due to the additional decode required for linking multiple TAPs; (2) the decode circuit and link update register provide additional output for link controls LC2-4; and (3) select inputs from all enabled and linked TAPs will be qualified by the corresponding active enable signals for input to the TLM TAP controller 31 via the AND and OR gates 33-37.
[0052]Example FIG. 7 shows a portion of the design of TAP4 of FIG. 2. The other TAPs of FIG. 2 can be analogously designed. The TAP controller 71 includes an input for the EN4 signal from the TLM 21, which is used to enable or disable the TAP controller 71. Also. TAP controller 71 has an input 73 connected to the Reset output from the TLM 21 to provide global reset of all TAPs. The TAP4 instruction register decode includes the SEL4 output to the TLM 21. Also, an instruction is provided to allow setting the SEL4 output high to enable scan access of the TLM 21.
[0053]Example FIG. 8 shows TDI pin 26, TDO1, TDO2 and TDO3 multiplexed onto the scan input of TAP4 to support the design of FIG. 5. The scan inputs of the other TAPs of FIG. 5 are multiplexed analogously. In this example, a 4:1 multiplexer 81 is connected to the TLM 51 via two link control signals LC4A and LC4B to control which scan input (TDI pin 26, TDO1, TDO2, or TDO3) is connected to the TAP's TDI input.
[0054]FIG. 9 shows an example TAP controller design to support enabling and disabling TAPs 1-4 of FIGS. 2 and 5 using the EN1-4 outputs from either TLM 21 or TLM 51. The TAP controller state diagram of FIG. 9 corresponds to the TAP controller 71 of FIG. 7, and includes a Run Test/Idle state wherein the enable signal (in this case EN4) is evaluated along with the TMS signal to determine the next state transition. In the Run Test/Idle state of FIG. 9, the next state will always be the Run Test/Idle state if EN4 is low, regardless of the logic level on THIS. If EN4 is high, the next state from Run Test/Idle is determined by the logic level on TMS. In the UpdateDR state the EN4 signal is evaluated along with the TMS signal to determine the next state transition. In the UpdateDR state of FIG. 9, the next state will always be Run Test/Idle if EN4 is low, regardless of the logic level on TMS. If EN4 is high, the next state from UpdateDR is determined by the logic level on TMS. Although FIG. 9 illustrates an example state diagram for the TAP controller of TAP4, TAPs 1-3 can be analogously designed.
[0055]The Run Test/Idle state of FIG. 9 provides, in addition to its conventional run test or idle functions, a stable state for the TAP controller to assume and remain in when it is not enabled to be linked to the 1149.1 test bus pins. Using the Run Test/Idle state as the stable state for unlink is advantageous because one well known method of initialing test operations associated with a given instruction is to transition the TAP into Run Test/Idle with the given instruction in the instruction register. An example of this advantage of using Run Test/Idle as the stable state for unlink is described hereinbelow with respect to the RunBist instruction.
[0056]The UpdateDR state of FIG. 9 provides, in addition to its conventional data update function, a link change state where a presently enabled TAP controller gets disabled and goes to the Run Test/Idle state while a new TAP controller becomes enabled to follow the ICs test bus pins.
[0057]For example, in FIG. 2 and after a Reset, the TLM TAP controller 31 and all the TAP controllers of TAPs1-4 will be in the Test Logic Reset state of FIG. 9. The IC's 1149.1 test bus pins will also be in Test Logic Reset state as driven by the external test controller. When the test bus moves from Test Logic Reset to Run Test/Idle, all the TAP controllers of TAPs1-4 will follow the test bus. However when the test bus moves from Run Test/Idle to Select DR Scan, only the TAP controller of TAP1 (TAP1 is enabled at reset to be the linked TAP as previously described) will follow. The other TAP controllers of TAPs2-4 will remain in Run Test/Idle because their enable inputs EN2-4 are low. TAP1 will continue following the test bus until another TAP is enabled by scanning the TLM 21. When the TLM 21 is scanned, the new enable and TAPSEL0,1 control will be updated from the TLM 21. For example if TAP2 is the new TAP to be selected, the EN1 for TAP1 will go low and the EN2 for TAP2 will go high in the UpdateDR state. Also, the TAPSEL0.1 outputs will change to output TDO2 from multiplexer 23. When the enable outputs from the TLM 21 change, the TAP controller of TAP1 will see a low on EN1 and it will be forced to transition from the UpdateDR state to the Run Test/Idle regardless of the logic level on TMS. When the TAP controller of TAP2 sees a high on EN2, it will be enabled to either (1) transition from the Run Test/Idle state to the Select DR Scan state if TMS is high, or (2) remain in the Run Test/Idle state if TMS is low. So while a TAP being unlinked is forced to transition from the UpdateDR state to the Run Test/Idle state regardless of the logic level on TMS, a TAP being linked can either stay in the Run Test/Idle state if the next state of the test bus is the Run Test/Idle state (TMS=0), or transition to the Select DR Scan state if the next state of the test bus is the Select DR Scan state (TMS=1).
[0058]FIG. 9A shows an example of how TAP controller 71 of FIG. 7 can use the EN4 signal to realize the state diagram of FIG. 9. The TAP state machine circuit 97 of FIG. 9A can be the conventional 1149.1 TAP state machine that implements the state diagram of FIG. 14. However, the input 95 where TMS is conventionally applied to the state machine is connected in FIG. 9A to the output of a multiplexer 90 whose data inputs are TMS and the output 91 of an AND gate 93 whose inputs are TMS and EN4. The multiplexer 90 is controlled to select AND gate output 91 when the decoded state of the TAP state machine is Update DR or Run Test/Idle, and to otherwise select TMS.
[0059]Apart from the improvements associated with FIGS. 7-9A (and FIG. 17 below), TAPs1-4 of FIGS. 2 and 5 can otherwise conform to the conventional 1149.1 TAP design of FIG. 12. In fact, the TAP controller 71 of FIGS. 7-9A will operate as conventional 1149.1 TAP controller 120 of FIG. 12 if EN4 is tied high. Note that input 73 of TAP controller 71 corresponds to the TRST* input of conventional TAP controller 120 (see FIG. 12).
[0060]The examples in FIGS. 10 and 11 illustrate two ways a TAP can be synchronously linked to the test bus 13. The FIG. 10 example shows how a TAP is synchronously linked to the test bus 13 when the test bus transitions from UpdateDR to Run Test/Idle state. The FIG. 11 example shows how a TAP is synchronously linked to the test bus 13 when the test bus transitions from UpdateDR to Select DR Scan.
[0061]FIG. 10 shows a timing example wherein unlinked TAP2 becomes linked and linked TAP1 becomes unlinked while the test bus transitions from the UpdateDR state to the Run Test/Idle state to the Select DR Scan state. The link change occurs on the falling edge of the TCK in the UpdateDR state with ENI of TAP1 going low and EN2 of TAP 2 going high. On the next rising TCK edge, the test bus transitions into the Run Test/Idle state, TAP1 (now unlinked) is forced to transition to Run Test/Idle (see FIG. 9), and TAP2 (now linked) remains in Run Test/Idle (see FIG. 9). On the next rising TCK edge, the test bus transitions to the Select DR-Scan state, TAP2 transitions with the test bus to the Select DR Scan state, and TAP1 remains in the Run Test/Idle state.
[0062]FIG. 11 shows a timing example wherein unlinked TAP2 becomes linked and linked TAP1 becomes unlinked while the test bus transitions from the UpdateDR state directly to the Select DR Scan state. The link change occurs on the falling edge of the TCK in the UpdateDR state with EN1 of TAP1 going low and EN2 of TAP2 going high. On the next rising TCK edge, the test bus transitions into the Select DR Scan state, TAP1 is forced to transition to Run Test/Idle (see FIG. 9), and TAP2 transitions with the test bus from Run Test/Idle to the Select DR Scan state (see FIG. 9). On the next rising TCK edge, the test bus transitions to the Select IR Scan state, TAP2 transitions with the test bus to the Select IR Scan state, and TAP1 remains in the Run Test/Idle state.
[0063]After completing all TAP accesses, the test bus can transition to the Test Logic Reset state. TAP(s) currently linked to the test bus will follow it into the Test Logic Reset state. TAP(s) not linked to the test bus (i.e TAPs unlinked and left in Run Test/Idle state) will be forced to the Test Logic Reset state by the Reset output from the TLM TAP Controller 31 (FIGS. 3 and 4) which always follows the test bus transitions and will output the Reset signal to all TAPs (see FIGS. 2-5) when the test bus enters the Test Logic Reset state.
[0064]To provide flexibility in using TLM 21 or TLM 51 to enable and disable TAPs within an IC, the TLMs should preferably be selectable during some or all of the instructions defined for each TAP. For example the 1149.1 standard defines the following list of required and optional TAP instructions: Bypass, Extest, Sample/Preload, Intest, RunBist, Clamp, Highz, Idcode, and Usercode. During Bypass, Sample/Preload, Idcode, and Usercode instructions, the functional circuit associated with the TAP remains in its normal operation mode. During Extest, Intest, RunBist, Clamp, and Highz instructions, the functional circuit associated with the TAP is disabled from its normal operation mode. Users of the 1149.1 standard may define and add instructions to achieve customized test operations, such as internal scan, emulation, or on-line BIST.
[0065]The flexibility of using the TLMs is enhanced if each of the aforementioned conventional instructions is replaced by a pair of instructions according to the present invention, which pair of instructions determine whether or not the TLM is selected. For example, the conventional Extest instruction selects the boundary scan register to scan data between the IC's TDI and TDO pins, but does not at all comprehend the select output SEL4 shown in FIG. 7. Accordingly, one instruction of the Extest replacement pair would (1) select the boundary scan register like the conventional Extest instruction, (2) inactivate the SEL4 output to deselect the TLM, and (3) otherwise affect the IC the same as the conventional Extest instruction. Another instruction of the Extest replacement pair would (1) deselect the boundary scan register, (2) activate SEL4 to select TLM for scanning, and (3) otherwise affect the IC the same as the conventional Extest instruction.
[0066]One advantage is that TLM can be operated to disable one TAP and enable another while maintaining the effect of the current instruction on the functional circuit associated with the TAP being disabled. For example, in FIGS. 2 and 5 it may be desirable to disable the IC's I/O while performing a test or emulation operation on MM1. To do this, TAP1 would be enabled and scanned with a Highz instruction version that selects the TLM and deselects the bypass register but otherwise affects the IC the same as the conventional Highz instruction, which will disable the IC's I/O. Next, a data register scan to the TLM disables scan access to TAP1 and enables scan access to TAP2 to enable the desired test or emulation operation on MM1. While test or emulation occurs on MM1, the Highz instruction version, left in effect in TAP1, keeps the IC's I/O disabled. Other 1149.1 instructions or user defined instructions can be similarly replaced by a first instruction that deselects TLM and selects a data register within the TAP and a second instruction that deselects the In TAP data register and selects the external TLM, both replacement instructions otherwise affecting the IC the same as the corresponding conventional instruction.
[0067]Example FIGS. 16-17A illustrate the above-described replacement of a given conventional instruction with a pair of replacement instructions which select or deselect TLM. FIG. 16 illustrates various functions which are controlled by the instruction register in the conventional IEEE STD 1149.1 architecture of FIG. 12. In FIG. 16, an instruction is shifted into the shift register 162, and shift register bits SRB3, SRB2, and SRB1 (i.e. the instruction) are then decoded by decode logic 165. The output of the decode logic is loaded into an update register 167 whose outputs control various functions in the test architecture. In the FIG. 16 example, six signals are output from the update register to control the various functions. Signal BR enables the bypass register to scan data therethrough signal BSR enables the boundary scan register (BSR) to scan data therethrough, the MODE signal applied to BSR determines whether BSR is in a test mode for handling test data or a transparent mode for passing normal functional signals therethrough, the HIGHZ signal can disable the output buffers 163 of the integrated circuit or core megamodule, the BENA signal is a Bist enable signal for enabling Bist operations, and the REGSEL signal controls multiplexer 161 to determine which data register (in this example the bypass register or BSR) will be connected to the input of multiplexer 121, which in turn determines whether a data register or the instruction register will be scanned.
[0068]FIG. 16A shows conventional instructions for use with the conventional architecture of FIG. 16. Each of the instructions is decoded to produce the indicated logic levels on the six control signals of FIG. 16. For example, the HighZ instruction enables the bypass register for scanning (BR=1) disables BSR for scanning (signal BSR=0), places BSR in the transparent mode (MODE=0), disables the output buffers 163 (HIGHZ=1), disables Bist (BENA=0), and selects the bypass register at multiplexer 161 (REGSEL=0). As another example, the conventional Extest instruction disables the bypass register for scanning (BR=0), enables BSR for scanning (signal BSR=1), places BSR in the test mode (MODE=1), enables the output buffers 163 (HIGHZ=0), disables Bist (BENA=0), and selects BSR at multiplexer 161 (REGSEL=1).
[0069]Exemplary FIG. 17 illustrates in more detail the instruction register control within TAP4 of FIG. 7 according to the present invention. The remaining TAPs 1-3 can be designed analogously. The update register 175 of FIG. 17 outputs the six control signals of FIG. 16 plus the signal SEL4 to select TLM. The shift register 171 of FIG. 17 has an additional shift register bit SRB4 because the six example instructions from FIG. 16A require twelve replacement instructions according to the present invention as shown in FIG. 17A. The additional bit SRB4 is thus needed to uniquely encode the twelve instructions of FIG. 17A.
[0070]Referring to FIG. 17A the replacement pair for the conventional HighZ instruction is seen at the third and ninth entries of the table of FIG. 17A. More specifically, the HighZ instruction with TLM not selected is decoded at 173 (see FIG. 17) to output the same logic levels as the conventional HighZ instruction and additionally to output a logic 0 on the SEL4 output in order to ensure that TLM is not selected. The decoded output of the HighZ instruction with TLM selected is the same as the decoded output of the HighZ instruction with TLM not selected, except BR=0 and SEL4=1 to ensure that TLM is selected and the bypass register is deselected. Similarly, the decoded output of the Extest instruction with TLM not selected includes the same six logic levels as the conventional Extest instruction, plus a logic 0 on SEL4 to ensure that TLM is not selected. The decoded output of the Extest instruction with TLM selected is the same as the decoded output of Extest with TLM not selected, except the BSR signal is at logic 0 to deselect BSR, and SEL4=1 to select TLM. Thus, the above-described instruction pairs and the other instruction pairs shown in FIG. 17A permit selection of either TLM or an internal data register (such as the bypass register or BSR) for scanning, but both instructions of each instruction pair otherwise provide the identical control signals provided by the corresponding conventional instructions illustrated in FIG. 16A. Thus, the instruction pairs of FIG. 17A permit TAP4 to select for scanning either the external data path in TLM, or an internal data register such as the by-pass register or BSR, while otherwise outputting control signals which are identical to those associated with the corresponding conventional instructions of FIG. 16A.
[0071]Execution of RunBist operations is improved by using the RunBist replacement instructions. The conventional RunBist instruction initiates a Bist (Built-In-Self-Test) operation when the TAP enters Run Test/Idle, but the conventional RunBist instruction selects a data register inside the TAP (boundary scan register in FIGS. 16-17) for scanning A first TAP can be enabled and scanned with the replacement RunBist instruction that selects the TLM and deselects the boundary scan register. After scanning the TLM to enable a second TAP, the first TAP gets disabled and automatically transitions into the Run Test/Idle state (FIGS. 9-11) where the replacement RunBist instruction takes effect to initiate the Bist operation. While the first TAP is executing the Bist operation in Run Test/Idle, the second TAP can be scanned with the aforementioned replacement RunBist instruction that selects the TLM and deselects the boundary scan register. Scanning the TLM to enable a third TAP will force the second TAP to the Run Test/Idle state where the replacement RunBist instruction takes effect to initiate a Bist operation. This scheme can continue to sequentially select TAPs and initiate Bist testing in as many TAPs as desired. Thus, BIST operations in the selected megamodules can occur in time overlapping fashion rather than purely sequentially. This of course provides time savings.
[0072]To obtain the Bist result from BSR of FIG. 17, TAP4 can be enabled via TLM, and then loaded with the replacement RunBist instruction that deselects TLM and selects BSR. With BSR selected, the Bist result can be scanned out of BSR by a data register scan operation.
[0073]The architecture of FIG. 5 can also execute the above procedure to initiate multiple RunBist operations, or it could simply enable/link all or selected ones of the TAPs together, scan in a conventional RunBist instruction to each, then enter Run Test/Idle to concurrently execute the RunBist instructions. After linking a first group of TAPs together in FIG. 5, each of them can be loaded with the replacement RunBist instruction that selects TLM 51, and thereafter the first group can be unlinked via TLM 51 so the first group can execute Bist operations in Run Test/Idle while TLM 51 is In linking a second group of TAPs to repeat the same procedure. So while the FIG. 2 architecture allows for enabling a TAP, loading RunBist, and then disabling the TAP to effect Bist operations in a megamodule, the FIG. 5 architecture allows enabling/linking a group of TAPs, loading RunBist, and then disabling/unlinking the group of TAPs to effect concurrent Bist operations in a group of megamodules. The capability of sequentially selecting groups of TAPs so that each group performs Bist operations concurrently within the group and in time-overlapping fashion relative to other groups provides additional flexibility to choose the most time-efficient approach for a given IC's megamodule layout.
[0074]Although providing a replacement instruction pair for each instruction will allow for leaving any instruction in effect after a TAP has been disabled, a single instruction can be defined to select the TLMI if desired. When using a single TLM select instruction, the TAP cannot maintain the effect of a specific instruction on the IC when the TLNI is accessed.
[0075]The TAP linking approach described herein could be accomplished on a substrate (e.g. multichip module or board) comprising individual circuits (e.g. die or IC), each having a TAP with externally accessible select and enable signals corresponding to SELL-4 and EN1-4. Also required on the substrate would be a TLM circuit (e.g. die or IC). Further, to support the plural TAP linking scheme of FIG. 5, multiplexer circuits (e.g. die or IC) would be required on the TDI inputs of some or all of the TAP'ed circuits.
[0076]Although exemplary embodiments of the present invention are described above, this description does not limit the scope of the invention, which can be practiced in a variety of embodiments.
Patent applications by Lee D. Whetsel, Parker, TX US
Patent applications by TEXAS INSTRUMENTS INCORPORATED
Patent applications in class Built-in testing circuit (BILBO)
Patent applications in all subclasses Built-in testing circuit (BILBO)
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realmagick.com The shrine of knowledge.
Kelantan History
A selection of articles related to kelantan history.
Original articles from our library related to the Kelantan History. See Table of Contents for further available material (downloadable resources) on Kelantan History.
- Indian History Rewritten
- The Indian civilisation, considered to be the product of clash and subsequent inter mixture of the white-skinned civilised invaders and the dark savages native to India, has been rightly questioned in recent years, and the mischievously fabricated history of...
History & Anthropology >> Indic / Vedic
- The Truth Behind the History of the Necronomicon
- I don't think there are many people out there who haven't heard of the Necronomicon and the dreadful things connected with it. We've all heard the theories about how it is a Satanist tool; actual copies of the book are bound in human skin and how you risk...
Deities & Heros >> Chthulu
- History of the Egyptian Religion, part I: Early Dynastic Period
- I - Predynastic - Early Dynastic Period. The temples were in essence the *Home of the God* and thus a place where only Pharaoh as the Son of God and those he appointed as his deputies, could meet with the god. This goes all the way back to Archaic and...
Religions >> Egyptian
- History of the Egyptian Religion, part II: The Old Kingdom
- II - The Old Kingdom ca 2686-2181 BC During the Old Kingdom the Egyptian society moved from tribal communities to a fully developed theocratic system, where the power of the king was absolute. The great pyramids of Dynasty 4 was made possible by technological...
Religions >> Egyptian
- History of the Egyptian Religion, part IV: Middle Kingdom
- First Intermediate - Middle Kingdom (ca 2181 -1786 bc.) The powers that built the solar temples of the 5th dynasty and the pyramids of the 6th dynasty weakened towards the end of the Old Kingdom, perhaps as a result of eroding economics, leaving the King less...
Religions >> Egyptian
Kelantan History is described in multiple online sources, as addition to our editors' articles, see section below for printable documents, Kelantan History books and related discussion.
Suggested News Resources
- Panthers lack the sting, says coach Tiago
- "Teams like Kelantan have a rich history of playing in the Super League ... their players know how to cope even when they're not playing well." Penang are sixth in the 12-team Super League standings with five points from four matches.
- 'Khabar dan Angin': Three artists explore faith in Kelantan
- Picture by Choo Choy MayKUALA LUMPUR, March 3 — Did you know that there are Buddhist wats (temples) in Kelantan? These wats are the historical heritage of the Thai-Buddhist community in this East Coast state but many Malaysians haven't even heard ...
- Archbishop Emeritus takes residence at OLGH
- The parishioners of the Chapel of Our Lady of Good Health (OLGH) officially welcomed Archbishop Emeritus Murphy Pakiam on Feb 28, during the Sunday evening Mass celebrated by the retired prelate with Chapel Administrator, Fr Edwin Peter.
- State of faith in Kelantan
- "Kelantan is a place often remarked on for its difference. It is a place with a different local dialect, different food, different history, different politics and soon to be, a pink football stadium," says Ong.
- What the map of Peninsula Malaysia would look like today if...
- History has narrated that the Sultanate of Malacca was the first unified sovereign State established on the Peninsula. Despite the fact that Kedah predated Malacca, the former did not thrive into a ...
Great care has been taken to prepare the information on this page. Elements of the content come from factual and lexical knowledge databases, realmagick.com library and third-party sources. We appreciate your suggestions and comments on further improvements of the site.
Kelantan History Topics
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Fight Network's John Pollock talks with the head trainer of the Tristar Gym, Firas Zahabi, about "Fund-A-Fighter," and George St-Pierre's preparation for the welterweight unification bout at UFC 154 against Carlos Condit on Nov. 17 at the Bell Centre in Montreal, QC.
Fight Network's John Pollock speaks with UFC's John "The Bull" Makdessi at the TriStar Gym in Montreal, QC. about his preparation for his upcoming bout against Sam "Hands of Stone" Stout at UFC 154.
Fight Network's John Pollock chats with the UFC's Patrick "The Predator" Cote at the TriStar Gym in Montreal, QC., about his upcoming bout at UFC 154 against Alessio "Legionarius" Sakara on November 17, 2012 and UFC's Canadian "Movember" plans.
Fight Network's John Pollock interviews the UFC's Francis "Limitless" Carmont at the TriStar Gym in Montreal, QC., and talks about his upcoming UFC 154 bout with Tom Lawlor at the Bell Centre.


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Best Fishing Times: 4:15AM to 6:15AM, and 4:45PM to 6:45PM
Alternate Fishing Times: 1:09PM to 3:09PM
Fishing Magnussen Lake, AB on 10/22/2016 will be best from 4:15AM through 6:15AM, and from 4:45PM to 6:45PM. If those times won't work for you, 1:09PM to 3:09PM looks promising. Remember to adjust these times based on barometric pressure, and weather changes.


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Fair ~
High: 76°F ~ Low: 50°F
Monday, Oct. 24, 2016
Wonder why the County and City recycling program is in flux?Posted Wednesday, January 14, 2009, at 9:14 AM
Here is a good look at the turmoil going on in the recycling industry and why the outlets have disappeared. http://www.packagingdigest.com/article/C...
We are using most of our recycled paper and cardboard in our garden or in our wood stove.
Plastic is just as bad, if not worse. Regrettably when the price of oil goes down, so does the value of recycled plastic. How can you win?
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Steve Mills and his wife have one daughter. They previously owned two coffee/ice cream shops, currently operate an internet sales company and teach classes, but his primary job involves the paper industry worldwide. Hobbies and interests lie in gardening, photography, recorded music and of course, their pets.
Hot topicsA non-political question, brought up by today's politics.
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realmagick.com The shrine of knowledge.
Dream Analysis Salt Water
A selection of articles related to dream analysis salt water.
Original articles from our library related to the Dream Analysis Salt Water. See Table of Contents for further available material (downloadable resources) on Dream Analysis Salt Water.
- Everyday Water
- When you think of "Water" what comes to mind? A tranquil lake, gentle rain, or raging sea? Whether magical element or just a simple cup of tea, water can be a very special part of your life. Water Spirits Every body of water is an entity. Each lake,...
The Elements >> Water
- A History Of Dreaming - From Ancient Egypt To Modern Day
- Dreams have been an important part of the human experince since time immemorial. Fragments of the earliest books come from Egypt, where dreams were considered to be the messages sent from the gods. The Egyptians divided their dreams into three categories: 1....
Parapsychology >> Dreams
- Psychic Protection - Barriers
- Introduction: The countermeasures given in these short articles are extremely basic. They only contain the bare bones of what is necessary to use them. To understand the principles behind these countermeasures, please get a copy of 'Practical Psychic Self-Defe...
Psychic Abilities >> Psychic Protection
- An Overview of Different Types of Scrying
- Scrying is a method of divination. It consists of gazing into a crystal, a mirror or some water for example, anything shiny really, in order to enter altered mind states...A good cliché that best describes scrying is the gypsy fortune-teller and her large...
Divination >> Scrying
- Self Dedication - a Ritual for You
- Self Dedication Explained Initiation is a process of "death and rebirth" - the old self dies, and the new and magickal self is born. A rite of self-dedication marks a serious commitment and dedication to the path, and should not be taken lightly....
Paganism & Wicca >> Ritual
- Ostara - The Vernal Equimox
- ABOUT OSTARA | RITUAL | FOODS | REFERENCES ABOUT OSTARA Ostara (pronounced Oh-star-ah) is also called Eostre, Easter, Vernal Equinox, Spring Equinox, and the First Day of Spring. This is the time of year when day & night are equal, and heralds the return of...
Holidays >> Ostara
- Hulse, David Allen
- From an early age, David Allen Hulse has made a diligent study of the alphabets of the ancient world. Even as a child, David possessed a great affinity for the alphabets of Egypt, Phoenicia, and Greece. In college, a reading of MacGregor Mathers' Kabbalah...
Real Interviews >> Authors
Dream Analysis Salt Water is described in multiple online sources, as addition to our editors' articles, see section below for printable documents, Dream Analysis Salt Water books and related discussion.
Suggested News Resources
- An Art-and-Design Island Destination: Naoshima, Japan
- Chichu means underground, and the galleries are buried into a hillside so that they become part of the island's dramatic landscape. Yet the spaces are filled with natural light.
- Lisa McInerney and Anne Enright on Baileys Women's Prize for Fiction longlist
- Jackie Copleton, A Dictionary of Mutual Understanding, Hutchinson. When a badly scarred man knocks on ... Clio Gray, The Anatomist's Dream, Myrmidon.
Great care has been taken to prepare the information on this page. Elements of the content come from factual and lexical knowledge databases, realmagick.com library and third-party sources. We appreciate your suggestions and comments on further improvements of the site.
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Get Forex buy/sell signals directly to your email and by SMS.
To learn more click here
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The gold markets fell during the session on Wednesday, but remain in a fairly tight trading range as the markets simply have no new news to move upon. We are still stuck between the $1540 level, and the $1640 level. Because of this, we are very cautious to trade this market as it seems very choppy at this moment in time and seems to be looking for a catalyst to break out.
In summer trading, we need to look at this as a range bound market predicated mainly upon the fact that many traders will be gone. Because of this, we can advocate buying closer to $1540 and selling closer to the $1640 levels. Until we break out of this range, all trades should be closed by the end of the day and only taken at the extremes of the range.


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Swedish Massage & Mani Pedi£24 instead of £101 for a Mother's Day pamper package inc. a 45-min Swedish massage and luxury mani pedi at Celestial Beauty - save 76%
Save 76%
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- Treat your mum to a relaxing Mother's Day pamper package.
- Includes a 45-minute Swedish massage with consultation.
- Plus a luxurious mani pedi.
- Experienced and friendly therapists.
- Based in Market Harborough.
The Fine Print
- One per person.
- May buy multiples as gifts.
- Voucher valid until 26th Jun 2014.
- 24-hour cancellation policy applies.
- Subject to availability.
Full Details
Mother's Day is always tricky: how can a gift show that you care? Rather than the same old flowers and chocolate, why not give an experience with today's deal...
Today we're offering you a Mother's Day package including a 15-minute consultation, a 45-minute Swedish massage and a luxurious mani pedi for only £24, saving you 76% off Celestial Beauty's price of £101.
The friendly and experienced therapists at Celestial Beauty are dedicated to the art of relaxation, what with their well-honed massage skills and the calm surroundings of this renowned salon. This Mother's Day, why not treat your mum (or yourself!) to a truly memorable experience with today's deal? This unrivalled pamper package includes a 45-minute Swedish massage that aims to de-stress and rejuvenate. As if that wasn't tempting enough, you'll then get a luxury mani pedi with a hand, arm and half leg massage, a soak and glamorous polish to finish the look. Lovely!
How to Redeem
- When the deal ends we'll send you your unique wowcher code.
- Call Celestial Beauty to book using the number we send you.
- Quote your full wowcher code.
Once purchased, you can redeem this wowcher towards another wowcher or claim a Wowcher Wallet Credit. Click here for more info.
Email Tarot Card Reading£6 for a tarot card reading via email with one question, or £9 with two questions from Extreme Relaxation - save up to 60%
Save 60%
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There are a number of alternative treatments available for lympoma. The following is a list of references concerning Lymphoma: Buglio, D., et al. Histone Deacetylase Inhibitors in Hodgkin Lymphoma. Invest New Drugs. 2010 Dec;28 Suppl 1:S21-7. Department of Lymphoma/Myeloma, Houston, TX, USA. PMID: 21127943. Buglio, D., et al. The Class-1 HDAC Inhibitor MGCD0103 Induces Apoptosis […]View Post
AHCC for Tumor Surveillance and Immune Responses.
Activated hexose correlated compound (AHCC) is a mixture of polysaccharides, amino acids, lipids and minerals which come from Basidiomycete mushrooms. Twenty percent of AHCC is composed of alpha-1,4-glucans. AHCC has been shown to change immune function, fight infections, increase liver detoxification enzymes and act as an antioxidant. It increases natural killer (NK) cells in cancer […]View Post
Mushroom Glucans and Proteoglycans in Cancer Treatment.
Fifty mushroom species have been shown to contain chemicals that have anti-cancer activity in animal studies. Six varieties of mushrooms have been studied in human cancers. Active Hexose Correlated Compound (A.H.C.C.) has shown clinical promise (2000) in cancer. Maitake D-Fraction has some proof of clinical usefulness (2000) against cancer. Two fractions of Coriolus versicolor mushroom […]View Post
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text: If you are one who is always cold, refuses to hide indoors, or spends a lot of time in the backcountry, then the [ak] BK Down Insulator Jacket isn't nice to have, it's a necessity. Ultra lightweight and extra-packable, the BK's weather-repellent ripstop fabric encapsulates ultra-premium 550 down for breathable, radiant heat. Venting Pit Zips™ give all that heat a quick escape, while the chest pocket is perfect for your wallet, keys, and phone. Ride this jacket under your shell or stuff it in your pack for a quick warm-up at the summit; whatever you do, just make sure you bring it.


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Related terms for "recycling equipment ":
material recycling equipment companies
, can recycling equipment companies
, plastic recycling equipment companies
, slop-oil recycling equipment companies
, chemical recycling equipment companies
, used recycling equipment companies
, metal recycling equipment manufacturer companies
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PEL is a manufacturer of bottle crushers, vertical balers for cardboard and plastic, bin compactors and oil filter crushers. PEL delivers innovative waste handling solutions. An Irish manufacturer with over 15 years experience supplying the hospitality, retail, corporate and industrial sectors PEL products are used by our customers Ireland, UK, Europe, Asia, Australia & ...
based in Balla, IRELAND.
We offer: ICT and computer recycling, refurbish and remarketing; Television recycling; Fridge and freezer recycling; Consumer electronic goods recyling; mobile phone recyling, refurbish and reuse; mobile devices recycling, refurbish and reuse, WEEE recycling and a bespoke recycling, reuse and recovery service to meet your business needs.
based in Stratford upon Avon, UNITED KINGDOM.
MERCODOR GmbH Sondermaschinenbau KG in Frankfurt am Main was founded in 1973. The family-owned company has always made shredders and manufactures them individually from start to finish in its own factory in Trebur according to customer specifications. The company`s shredding systems are now successfully employed, for instance, in industrial and commercial establishments, ...
based in Frankfurt am Main, GERMANY.
The BIC Group, with strong bases in Belgium and Singapore, designs & builds plant for the thermal destruction - and energetic valorization of non-recyclable waste. BIC Group`s lead engineers have been supplying equipment for over 30 years.BIC Group is amongst very few manufacturers worldwide who have used their own equipment to operate a commercial waste treatment plant ...
based in Gent (SDW), BELGIUM.
Shimadzu Scientific Instruments (SSI) is the American subsidiary of Shimadzu Corporation, headquartered in Kyoto, Japan. Shimadzu is a $3 billion multinational corporation with three major divisions: Medical Diagnostics, Aerospace/industrial, and Analytical Instruments. The Analytical Division is one of the world's largest manufacturers of analytical instrumentation and ...
based in Columbia, MARYLAND (USA).
ProMedUSA Pte Ltd is a Singapore Private Limited Company.We are the exclusive importer and distributor in Asia for the entire range of Crystal Air Ozone Generators (ozonizers or ozonisers) for both air and water treatment.Most of Singapore's 3,4,5 and 6 star hotels, resorts hospitals, F&B Outlets, Tobacco and Cigar Divan's, Cleaning Contractors, Recycling Enterprises and ...
based in Singapore, SINGAPORE.
Autoclaves for biohazardous waste treatment. Vacuum or gravity type. Customers: Hospitals, airline catering, pharmaceuticals, regional processing. Capacity: 102kg to 1,360 kg per one hour cycle. manual to total automation operation ancillary equip: compactors, grinders, dumpers. 49 years in business. One of least expensive to purchase and maintain in industry.
based in Carson, CALIFORNIA (USA).
Vecoplan AG is an industrial pioneer in the development of shredding and recycling technologies for the plastics, wood, paper and waste industries.The design of Vecoplan shredders and related products, particularly the single-shaft shredder, is extremely unique in its universal capability to process a wide range of different waste materials. As such, many different types ...
based in Bad Marienberg, GERMANY.
Industrial and Environmental Health and Safety Instrumentation: Air Sampling Pumps, Calibrators, Equipment, and Accessories. Colorimetric Gas Detector Tubes. Point Gas Monitors. Open Path Gas Detection. Sound, Noise, and Vibration Measurement Instruments. Real-time Dust Monitors. Flame Detectors.
based in St. Petersburg, FLORIDA (USA).
ClearWater Tech, LLC is a leading designer and manufacturer of ozone generation equipment for commercial laundries, swimming pools, spas, water features and a wide range of other water purification needs. ClearWater Tech has earned its industry leading reputation through technical distinction in ozone generation applications since 1986. For over a quarter century we have ...
based in San Luis Obispo, CALIFORNIA (USA).
Belgian company AMB Ecosteryl is a manufacturer of medical waste treatment technology.AMB s.a. is a manufacturer and specialist of the medical waste treatment industry. We work closely with our customers to provide market-leading alternative medical waste treatment equipment – delivering quality; reliability; compliance and cost-efficiencies.Our technology is used by ...
based in Mons, BELGIUM.
Mar Cor Purification (MCP) is owned by Cantel Medical Corp., a NY Stock Exchange listed company (CMN). The business consists of several familiar companies integrated to offer filtration, water purification and disinfection technologies, including Minntech Filtration Technologies Group, Mar Cor Services, Biolab Equipment, GE Medical Water and the Gambro US Medical Water ...
based in Plymouth, MINNESOTA (USA).
Bibby Scientific focuses on the design, manufacture and distribution of four world leading benchtop laboratory equipment brands, Jenway, Stuart, Techne and Electrothermal. The Jenway extensive product range includes UV/Vis Spectrophotometers, Life Science and Environmental Spectrophotometers, Flame Photometers, Colorimeters, Portable and Laboratory meters and probes, for ...
based in Stone, UNITED KINGDOM.
Flekso-Pak Sp. z o.o. (ltd.) is a manufacturer and supplier of polythene films and flexible packaging for various businesses also offering flexo printing service. We own most modern machinery like single und multilayer film blowing machines, flexographic CI press, bag-on-roll making machines, bag sealing machines, slitter rewinder.
based in Lubianka, POLAND.
Adedge Water Technologies, LLC specializes in the development and supply of innovative technologies, adsorbent-based products, and systems that remove contaminants from process or aqueous steams. We are an organization based on solid deliverable, scalable, scientifically proven technology and experience for the removal of arsenic and other contaminants from water. Our ...
based in Buford, GEORGIA (US) (USA).
Enhesa is a global environmental, health and safety consulting firm, providing EHS regulatory compliance assurance support to businesses worldwide. Over the past 20 years, Enhesa has built a knowledgebase of EHS regulations which includes the `What` of business requirements, the `How` to develop cost-effective solutions and the `When` of enforcement activities in over 200 ...
based in Brussels, BELGIUM.
ICOS PHARMA, thanks to the specialization reached over the years, is a company able to enter successfully the various markets by means of its 3 divisions: Colussi Medical Division • ICOS Pharmaceutical Division • ICOS Laboratory Division. Our Company designs, manufactures and installs high quality devices such as washers, disinfectors and steam sterilizers meant for the ...
based in Cusano di Zoppola (Pordenone), ITALY.
We're the Oil Filter Crusher Specialists! Filter crushers are the only product we sell so you can rely on us to provide the best solution to your oil filter disposal needs. For over 20 years, Magnum Force crushers have proven their outstanding performance because they are: Dependable -Heavy gauge steel construction & chrome drive shafts, built for long lasting operation; ...
based in Milwaukee, WISCONSIN (USA).
Established in 1984 to meet the demands of Northwest loggers, Vulcan On-Board Scales are built to last in the harshest environments. Today we provide products to the trucking markets including timber, refuse, aggregate, and general trucking, as well as solutions for the aerospace, marine, medical, heavy machinery and process controls markets. Vulcan On-Board Scales are ...
based in Kent, WASHINGTON (USA).
Ceram is an independent, international materials technology consultancy that focuses on innovation, sustainability and quality assurance of materials. Headquartered in Staffordshire, UK, and with approved laboratories around the world, Ceram solves product and process challenges across a range of materials to help clients improve performance, comply with regulations and ...
based in Stoke-on-Trent, UNITED KINGDOM.
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Say Hello! Introduce Yourself...
My name is Robin and I live in New Jersey with my husband and 3 kids - ages 6, 3 and 1.
We have fun going to Disney World together and I enjoy planning trips and sharing tips and pictures with friends.
I'm looking forward to talking about Disney with everyone here!
I hope you'll introduce yourself, too!
Amy here, mom of 2 with one more coming in a few weeks. We just had our first family Disney trip this past October and are going again next October as a 10th anniversary trip.
Hiya! Married with 2 handsome boyz ages 17 & 9. I am a Disney Mom and an AP holder. Love all Disney things same as my boyz but not as much as mama, LOL! I collect from Disney pins, snow globes to vinylmations. Yes, i have Disney shoes, too! Everyone one tells I might as well live there since I do go there mostly every weekend my my disney girls...yes, i live in SoCal, drought county of Los Angeles, LOL! If you ladies are at Disneyland....let us know!
Hi! I'm Calyn. I am a mom of 2 kids and we are in the Atlanta, Georgia area. We are Disney Vacation Club members and Disney World Annual Passholders. We love Disney and go 2-3 times a year. :)
Hi Robin! Our whole familly loves Disney and I'm excited to join this group!


text:
German Apple Pancake
Total Time
Prep 15 mins
Cook 25 mins
While not authentic, this is a wonderful & easy recipe for a baked apple pancake.
Ingredients Nutrition
- 2 tablespoons butter
- 2 medium apples, pared, cored & sliced
- 4 tablespoons brown sugar, firmly packed & divided
- 3⁄4 teaspoon ground cinnamon
- 3 eggs
- 1⁄2 cup milk
- 1⁄4 cup flour
- 1⁄2 teaspoon salt
- Preheat oven to 450º.
- Melt butter in a 9 or 10 inch skillet with an ovenproof handle (cast iron works great).
- Arrange apple slices in a single layer over butter.
- Combine 2 tablespoons brown sugar with the cinnamon & sprinkle over the apples.
- Cook over medium heat, stirring gently, until apples are slightly tender ( 5-6 minutes).
- Beat eggs, milk, flour & salt till smooth; pour over apple mixture.
- Bake for 8 minutes; remove from oven.
- Lower temp to 375º.
- Sprinkle remaining 2 tablespoons brown sugar over pancake.
- Return to oven & bake till evenly browned; 8-10 minutes.
- Loosen pancake around the edges & cut into wedges.
Most Helpful
This was fabulous in taste Susie. It reminded me more of french toast than pancake's because of the sweetness. DH put maple syrup over his even though I thought it was fine w/o any type of topping. Added a bit of nutmeg to the sprinkling over top. Made only two servings..Glad I tagged for 123 HitWonders 08~
I've been looking for something quick, simple, easy to use up a bag of apples before I'd have to toss them. I'm not opposed to pie, but I'm just not in the mood for the time (or calorie) investment. This was just perfect! I only added half the sugar and it was just sweet enough! (and about 5 WW points if you're interested in that sort of thing). This is going to be a standard breakfast I have a feeling. While it is good cold, a few minutes in a hot oven makes it even better! It didn't get puffy for me like other German pancake recipes I've made, but that's ok. The pancake was almost like a VERY firm custard and not "cake" at all in texture. I might try adding an extra egg to get the protein up even more. Oh yeah, and by the way, I thought I had all the ingredients on hand, so while the apples were cooking away in the pan, I opened the fridge and realized NO MILK! I did have non fat powdered milk on hand and it worked just perfectly! 5 stars all the way!
This is a delicious, easy breakfast. Used two grannysmith apples and my Sweet Spice Blend instead of just cinnamon. Served with warm maple syrup and applewood smoked bacon for a wonderful Sunday morning breakfast!


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To mark the one-year anniversary of Tropical Storm Irene, communities are banding together partly to remember the destruction it caused, but more to recall the camaraderie and sense of community that arose from the disaster. Prattsville in Greene County was devastated by flooding, but an advertisement at www.prattsville.org for its first "MudFest" makes it clear the town's spirit is strong. "On Aug. 28, 2011, life dealt the people of Prattsville mud — and plenty of ...
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Description: Diorles Creations is located in Osolo Way, Mayo Plaza, Ajao Estate, Oshodi Isolo, Lagos. Our compan
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Belgravia College — Fraud College
3 Reviews
Dhdharmesh - patel on Jan 22, 2012
Fraud Belgravia College in London is cheating students with not refundiong their fee for any reasons if you dont get a visa. You may loose Rs 2.5 Lacs if you apply in this college. Their management is all Pakistani & they have employed Indians just to cheat Indian Students through agents in India.
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Don't do it.
Don't be that person Saturday who stays away from the West Texas A&M home football opener because you don't like the recent mess played out in Canyon.
The West Texas players deserve better than that.
Oh, I know you have been fuming for a month now.
"I'll show that university they made an epic mistake and they aren't getting another dime from me."
I'm not looking for you to apologize for still shaking your head and wondering when the smoking gun will be fired by WT officials on the real reasons Don Carthel was suddenly fired before the season started.
Because I'm like all of you I have talked to and listened to during the past month.
A lie of not admitting to buying a couple of prominent WT players Texas Rangers tickets results in being fired? A game or two suspension, dang right. But fired?
You and I lie to our boss and there are consequences. So I have no issue with some punishment. But make the punishment fit the crime.
I mean, from what we have been told, this appears to me to be a guy sentenced to life for getting caught by one of Amarillo's red light cameras.
It wasn't like Carthel had just been hired.
I mean the man took over a WT football program in 2005 that Google maps couldn't find. All he did was become the winningest coach in Buff history along with packing a 20,000 seat stadium a couple of times.
That act ranks in the top five accomplishments in sports that I have witnessed in 32 years working here.
So I get the built up frustration over losing your coach over something appearing to look like a middle-school power tiff.
Now, to be fair, I also know Carthel could stretch things to the limit with WT officials on certain issues. So WT has a side of this story.
That's my point here.
Let all this crud go when it comes to this WT game against Texas A&M-Commerce on Saturday.
Remember that feeling you had in July before all the controversy went down? Mention the Buffs 2013 football season and it was 100 percent positive.
Look, if you side with Carthel, or you side with WT, or you hate what I've said today, or if you like, or don't like interim WT head coach Mike Nesbitt, it doesn't matter at 6 p.m. Saturday.
What matters is a group of young men who love to play football, not politics.
What matters is a group of young men who have already proven in a comeback win last week they will play with heart this year.
What matters Saturday is the WT football players.
Please, don't do it.
Don't stay away from the stadium Saturday. Pack the place.
What better way to send a message to these WT players that sometimes well-paid, intelligent, educated adults can mess up a good thing, but we won't take it out on you.
Lance Lahnert is the AGN Media sports editor and can be reached at email@example.com and 806-345-3312.


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80Th Birthday Cake
This was for my grandpa's 80th birthday party. We own a family run dairy, that is what the cows and milk cans represent. It was a surprise and he loved it. The cows and milk cans are fondant (my first time making figures) and the sign is fondant wrote with the edible markers. The cake is buttercream icing. The wheat looking grass is silk. Thanks for looking
Comments (17)
Dixiegal01 on
Oh, this is so adorable, kudos to you on your fondant figures, they are fantastic!
Wendoger on
awww sooo cute!!! I love this cake!!!!!
ShirleyW on
Oh, how adorable! This is just the sweetest thing, your grandpa must have loved it.
laly on
Congratulations on this beautiful cake, and I am glad Grandpa enjoyed!
Eshed on
Amazing!! So creative!
janine1972 on
its lovely, the cows are so gorgeous well done
JenniferMI on
I'll bet grandpa was grinning from ear to ear when he saw this masterpiece!!!!! Bravo!
bobwonderbuns on
Oh how cute!!!
cakemommy on
How cute are those cows! What a wonderful surprise for your Grandpa.
rmelendrez on
Just adorable....May I borrow your design sometime?
ac2steachk on
The wheat adds a great little detail. I like the milk cans, too.
thecakemaker on
moooo cute! your cows are adorable!
turtlemom on
Thank you all so much for the nice comments. I was worried about this cake at first but I think it turned out great. My grandpa was surprised and he loved it!!! I hope to make his 100th birthday cake too in 20 years!
CKelly on
"Hello! This is Chick-fil-A calling..umm..we have some cows missing"..LOL..This is soooo cute. Great job.
turtlemom on
thank you to everyone for all of your nice comments!!
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