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Are we leaving the arts out of journalism?
Like most journalists, I look to reports like the recently released Tow Center report on the changing nature of the field for guidance, for ways of thinking about what I do. But what I find is that what I do as a critic is increasingly marginalized or ignored by such studies.
In the thousands of words in the report from Tow, based at the Columbia School of Journalism and written by some of the finest minds in the field, there is a glaring void. There is no real consideration of cultural dialogue and criticism, perhaps the fastest shrinking segment of mainstream media today. Journalism worth doing is defined as investigative, watchdog journalism, the stories that somebody, somewhere doesn't want written. I would agree that this is the core of good journalism. »Read Full Blog Post(9)
'Sopranos' star James Gandolfini reading Maurice Sendak's 'In the Night Kitchen'
Here's a look at 'Sopranos' star James Gandolfini in a distinctly different role: reading Maurice Sendak's story 'In the Night Kitchen':
Gandolfini died of a heart attack while on vacation in Italy Wednesday. He was 51. »Read Full Blog Post
The Story of TRUE Skool: A Short Film
Words can't express how much working at the youth organization TRUE Skool has meant to me and many others in and around the Milwaukee area. Because of this, when people ask me why I chosen to become the music director there, my answer of "because it's dope", admittedly isn't very descriptive. »Read Full Blog Post
Crisp Pizza Bar on Brady closed; Jack's American Pub to open
Crisp Pizza Bar, 1323 E. Brady St., closed Tuesday, and a new bar called Jack's American Pub will open in its place.
Scott Schaefer, owner of Milwaukee Brat House on Old World 3rd St. and an owner of Three Lions in Shorewood, confirmed that the sale of Crisp was finalized Tuesday and that a new bar will open. »Read Full Blog Post(4)
Full map of Wisconsin pick-your-own berry farms
Wisconsin's lingering cold front may have delayed strawberry ripening, but local orchards are still preparing for a bountiful pick-your-own berry season. Whether its blueberries, raspberries, strawberries or pea pods, you can find a number of pick-your-own places with our complete location map.
Farmers advise that you call them before planning a trip to their orchard to confirm hours of operation and to prepare for any weather advisories. All phone and hotline numbers are provided in map details. »Read Full Article
How well do you know the Summerfest headliners?
ANSWERS: 1. Pitbull; 2. Florida Georgia Line; 3. John Mayer; 4. Eagles; 5. Boyz II Men; 6. Rush; 7. Tom Petty and the Heartbreakers; 8. Jason Aldean; 9. fun.; 10. Luke Bryan »Read Full Article
Milwaukeeans Chill on the Hill with social media
Bluegrass music filled Humboldt Park last night in Bay View's latest Chill on the Hill concert.
But photos, videos and tweets filled the social media sphere as musicgoers shared their experiences. Read our social media story of last night's Chill on the Hill, which featured Pay the Devil / The Best Westerns. »Read Full Article
Garlic Fest to sprout on Sunday in Walker's Point
Food, drinks, games, music, artists and other vendors will be on hand for Garlic Fest on Sunday in Walker's Point.
It takes place from 10 a.m. to 3 p.m. outside Braise restaurant, at 1101 S. 2nd St. »Read Full Blog Post
On Tap Today: Jewel, Jesus, bikes and disclaimers
She grew up yodeling and performing cafes before being discovered. And then there was the time she was Karen, the frozen food princess singing Karaoke. Tonight, she's Jewel and she's performing at the Potawatomi Casino-Northern Lights Theatre.
If you're in the mood for a bike ride with your musical adventure this evening, consider the cycling-centric theme for the Sounds of Summer Concert Series. Or how about this, a little Jesus coupled with culinary medicine, a first we are told. »Read Full Blog Post


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|Publication number
|Publication type
|Application number
|Publication date
|May 15, 1990
|Filing date
|Dec 28, 1988
|Priority date
|Dec 28, 1988
|Fee status
|Also published as
|Publication number
|Stamatis Vassiliadis, Eric M. Schwarz, Baik M. Sung
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (12), Non-Patent Citations (6), Referenced by (39), Classifications (6), Legal Events (6)
|External Links: USPTO, USPTO Assignment, Espacenet
Sj =(Yk-(s-2))-W(0)
-W(0)=(Yk-(s-2) Yk-(s-1) Y.sub.(k-s) . . . Y.sub.(k) Y.sub.(k+1))+(-Yk-(s-2) -Yk-(s-1) -Y.sub.(k-s) . . . -Yk -Y.sub.(k+1))
b=→[(Xsign V Sj)W(0)]
bit=→[(Xsign V Sj)→W(0)]
bits=[(Xsign V Sj)�W(0)].
Φj =Sj Xtc |Wj |
Sj =Y.sub.(k-s-2) -W(o)
W(o)=(Y.sub.(k-s-2) Y.sub.(k-s-1)Y(k-s) . . . Y.sub.(k) Y.sub.(k+1))+(-Y.sub.(k-s-2) -Y.sub.(k-s-1) -Y.sub.(k-s) . . . -Y.sub.(k) -Y.sub.(k+1)).
This invention relates to multiplication of binary digits by overlapped, multiple-bit scanning and, more particularly, to a multiplier which multiplies two multi-bit, binary digits, both being either sign magnitude or signed binary numbers.
The realization of a multiplier which multiplies a pair of binary digits to produce a result is complexified when the form of the numbers is considered. As is known, binary digits can be represented as a combination of a plurality of magnitude bits with an appended sign bit. The magnitude bits represent an absolute magnitude of the number, while the sign bit denotes a positive or negative magnitude. Another type of representation is signed binary, which is rendered by complementation of the absolute value of the number. Most frequently used is two's complement. In this representation, complementation of the original magnitude embeds the sign of the number in the representation of its magnitude.
Since the sign of a two's complement number cannot be separated from its absolute value, as is the case with the sign magnitude representation, multiplication hardware for both representations requires correction or conversion of one representational form. Correction and conversion, of course, imply the necessity of additional hardware and time.
There are at least three common ways to perform two's complement multiplication using the sign magnitude multiplier. In the first method, the two's complement operands are precomplemented to produce sign magnitude numbers. The resulting sign magnitude numbers are then multiplied, with the result being rendered back into two's complement form with post complementation. This scheme exacts an additional cost in hardware and procedure cycles. Hardware must be added to perform the complementation, and time is consumed to perform it. Hardware can be saved if the pre- and post-complementation are performed in the adder hardware. This may result, however, in more cycles yet to perform the multiplication, and require addition of multiplexing hardware for adder inputs.
In another technique, operands are sensed prior to multiplication and conditionally complemented. If both operands are positive, neither pre-, nor post-complementation is required. Multiplying two oppositely signed numbers requires only precomplementation of one operand and post complementation; and multiplying two negative numbers requires precomplementation for both operands. The implication is that sensing the operands will improve the overall performance of signed magnitude multiplication. This technique also requires extra hardware and adds operation cycles. This approach is the most commonly used in the realization of binary multipliers; for example, see U.S. Pat. No. 4,594,679.
Last, two's complement multiplication using sign magnitude circuitry can be realized with the use of specialized types of adders to perform element addition and subtraction. See, for example, S. D. Pesaris, "A Forty-ns 17-bit Array Multiplier, "IEEE TRANSACTIONS ON COMPUTERS, Vol C-20 TP 442-447, Apr. 1971. This case requires the availability of four types of adders which are frequently not realized fully in a selected technology. A full adder is required which requires the creation and manipulation of a multiplication matrix. In a matrix, correction rows are added to the existing matrix for negative terms presented in the two's complement multiplication. This requires additional hardware and delay for the overall multiplication.
A significant advance in the design of multipliers would result from a multiplier capable of multiplying a pair of operands, which are either both sign magnitude or both two's complement, to produce a result, the multiplication being conducted without precomplementation, post-complementation, specialized adders, extra correction rows for a matrix, or operand sensing requiring additional branching to perform two's complement multiplication.
In the invention, a new scheme is provided for hardware implementation of a multiplier capable of multiplying either two sign magnitude operands or two two's complement operands without the requirement for complementation, operand sensing, or complicated matrices.
A further object of this invention is to establish a scheme that utilizes a sign magnitude multiplier to perform multiplication of either sign magnitude or two's complement operands with a slight elaboration to the basic complement of hardware, with no additional time for performing the operation, and without the encumbrances of the prior art multipliers.
A further object of this invention is to produce an apparatus for two's complement multiplication which multiplies a pair of two's complement operands in the same amount of time as a pair of sign magnitude operands.
An advantage of this invention is the elimination of pre- and post-complementation cycles in hardware through operands end result.
Another distinct benefit of this invention is elimination of the need for specialized circuitry for element addition/subtraction and for expansion of the basic partial product matrix.
According to the invention, in the multiplication of the pair of operands, a matrix of partial product terms is formed in accordance with an algorithm, with each partial product including appended sign encoding bits. For two n-bit operands, the matrix is developed by scanning the multiplier operand to obtain a sequence of bit groups. Each group includes s successive bits of the multiplier and overlaps an adjacent group by one bit, and s≧3. A matrix assembler receives the partial products obtained by multiplying the multiplier with the multiplicand bit groups and produces the sequence of partial products assembled into a matrix including m+1 offset rows, where m=INT[n-1)/(s-1)], each matrix row including one of the partial products. A sign encoder is included in the matrix assembler and responds to the sequence of multiplier bit groups or to a multiplicand sign bit by appending sign encoding bits onto a partial product to complete a respective row of the matrix. Last, an adder circuit is connected to the matrix assembler for adding the partial products, with sign encoding bits appended, to produce the product of the two operands.
As the algorithm described below sets out, the sign encoder, in generating the sign encoding bits in response to either the multiplier bit group or a multiplicand sign bit, improves the prior art sign magnitude overlapped scanning multiplier by enabling it to multiply operands which are in either sign magnitude or two's complement form without pre or post complementation.
Other advantages and objects of this invention will become evident when the following detailed description is read in reference to the below-described drawings.
FIG. 1 illustrates, in block diagram form, an embodiment of the invention.
FIG. 2 illustrates the generation of terms in the middle rows of an offset partial product matrix.
FIGS. 3, 4 and 5 illustrate forms of a partial product matrix that trace the development of the matrix according to the invention.
FIGS. 6, 7A, 7B, 8A, 8B, 9A and 9B are schematic diagrams illustrating the formation of a matrix of the invention.
FIG. 10 is a schematic circuit diagram illustrating a matrix assembler of the invention.
FIGS. 11 and 12 are schematic circuit diagrams illustrating means for aligning and sign-extending two's complement operands.
FIGS. 13a, 13b, 13c, 13d, 13e are schematic circuit diagrams of a portion of the COMBINE circuit of the embodiment of the invention which produce coefficients used in formation of an offset partial product.
FIG. 14 is a schematic circuit diagram illustrating a partial bit generator in the matrix assembler of the embodiment of the invention.
FIGS. 15-17 are circuit schematic diagrams illustrating row generation circuitry used to generate partial products in the embodiment of the invention.
FIG. 18 is a block diagram illustrating a carry-save adder tree for adding the partial product matrix.
Array multiplication is a known technique for obtaining the product of two n-bit, binary digital numbers. A broadly used algorithm for such multiplication is the overlap shift method for three-bit scanning reported by MacSorley in "High-Speed Arithmetic in Binary Computers", PROCEEDINGS OF THE IRE, VOL 99, Jan. 1961. In the scanning multiplication technique, a multi-bit multiplicand is multiplied by a multi-bit multiplier to produce a multi-bit product. The scanning of the technique involves "scanning" the multiplier by taking sequential multiplier bit groups and then multiplying the multiplicand by each bit group to produce partial product terms, thereby effectively reducing the numbers of partial products required. In U.S. patent application Ser. No. 116,172 filed on Nov. 3, 1987, and assigned to the assignee of this application, a representative technique and means for overlapped multiple-bit scanning are taught in which the bit groups of the multiplier consists of more than three bits. For the example of its specific embodiment, that patent application is incorporated herein by reference.
In the incorporated patent application, an overlapped scanning multiplication system assembles modified partial products in a reduced matrix by increasing the size of multiplier bit groups with which the multiplicand is scanned beyond three. In addition, each multiplier bit group is overlapped by one bit with an adjacent bit group. When a negative partial product term is produced, a "hot 1" is encoded in an extension to the partial product term in the previous row, thus avoiding the need for adding a row for this purpose. Instead of extending each row to the left edge of the matrix, rows are extended with bands of encoded extensions of limited length at each end of the partial product terms.
In this description, a sign magnitude operand is taken to be a multi-bit binary digit with n consecutive bits. A multiplicand operand X has the following notation:
X0 X1 X2 . . . Xn-2 Xn-1
where X0 is the sign bit, and bits X1 -Xn-1 present the magnitude in descending significance from X1 through Xn-1.
Similarly, a multiplicand operand in sign magnitude form includes n bits numbered from Y0 through Yn-1, with Y0 being the sign bit, and Y1 through Yn-1 magnitude bits whose significances decrease from Y1.
In this embodiment, signed binary operands are at most (n-(s-1)) bits wide. Thus, a signed binary multiplicand operand has bits X0 -Xn-s with X0 being the sign bit, and the remaining bits decreasing in significance through Xn-s. The signed binary multiplier operand has similar notation. In the embodiment, s-1 replications of the sign bit of a signed binary number are appended to the left of the sign bit, thereby giving these numbers the n-bit width of sign magnitude numbers.
In the system of FIG. 1, a multiplicand X is provided to an alignment and extension circuit 10 activated by a two's complement indicator (tc). If the tc signal is activated, X is a two's complement number. Activation of the tc signal will align the least significant bit of the operand X with the least significant bit of a sign magnitude number and extend the sign bit X by s-1 replications, thereby rendering X as an n-bit signed binary number. If the tc signal is inactive, X is a sign magnitude number requiring no alignment or extension. A 3X multiplier 14 multiplies a bit Xi of X by standard left-shift and add technique to producer 3Xi. multiplier Y is subjected to an align/extend circuit 18 identical with that indicated by reference numeral 10. The n-bit operand is then scanned in the scan means 20. As is known in the art, the scan means 20 will produce a sequence of multiplier bit sets, each bit set including s bits, successive bit sets overlapping one bit of an adjacent bit set. For example, in the illustrative case, when s=4, the first scan of Y will output the values of the first four bits of Y, that is, Y0, Y1, Y2, and Y3. The second scan will output the values of Y3, Y4, Y5, and Y6. The third scan will output the values of the sixth through ninth bits of Y and so on until all of the bits of Y have been scanned. If, for example, Y consists of 56 bits plus a sign bit, 19 scans of Y will be output by the scan means 20.
The output of the scan means is applied to a combining circuit 22, which combines the bits of a multiplier bit set to produce values of a coefficient W for the current scan. In addition, the current scan of Y is provided to a sign encoding circuit 24. The sign encoding circuit 24 receives the multiplicand sign bit X0, the coefficient W[0], and bits from the current scan of Y to encode bits which are appended onto the partial products.
The coefficients, the values of X including 3X, and sign encoding bits are all provided to a matrix assembler 26 which produces an overlapped scanning matrix, row-by-row, in which each row includes a partial product with appended sign encoding bits. The matrix is indicated by reference numeral 28, which may denote, for example, main storage, or RAM storage where current results are stored. It is also contemplated that the practice of this invention will accommodate carry-save addition techniques in which an entire matrix will not be assembled. Rather, as each row is produced, it will be combined with the sum of all the previous rows until the final product is achieved. For an understanding of this technique, see the incorporated patent application.
A matrix is then added by an adder circuit to produce the multiplication result. Many adder circuits are known which can be used for combining the partial products to produce the result. For example, a set of carry save adder trees 30 can be provided which reduce the columns of the matrix to no more than two terms: carry and sum. These columns are added, typically in the next cycle, by a 2:1 adder 34, yielding the result. This set of adder components can be understood, for example, with reference to the incorporated patent application.
Turning now to the encoding of the matrix for s-bit overlapped scanning, the following describes a multiplier for fixed point operands in two's complement notation using the hardware of a floating point, sign magnitude notation multiplier. The fixed point and floating point operations are computed in the same number of cycles after the loading of the operands. The changes needed to sign magnitude hardware to compute both types of multiplication are described.
Let Xsm be a n-bit sign magnitude fraction number, then, ##EQU1## Assume the multiplication of the two absolute values of two sign magnitude numbers, Xsm and Ysm, and their sign manipulation separately. Then it can be stated that: ##EQU2## such that: m=INT[(n-1)/(s-1)] where INT=integer division, s is the number of bits being scanned, and s≧2. ##EQU3## and let k be proportional to j such that k=(s-1)j-1.
Sj Xsm |Wj | can be rewritten as ##EQU4## with the possibility of a "hot 1" added, where
π-2 =(X0 *→W[3]→W[0])+((3X)0 *W[3])(2.1)
π-1 =→W[0][(X1 *W[4])+((3X)1 *W[3])+(X0 *(W[2]+W[1]))] (2.2)
π0 =→W[0][(X2 *W[4])+((3X)2 *W[3])+(X1 *W[2])+(X0 *W[1])] (2.3)
πi =→W[0][(Xi+2 *W[4])+((3X)i+2 *W[3])+(Xi+1 *W[2])+(Xi *W[1])] (2.4)
and such that Xi *=Xi if Sj =0 or Xi *=→Xi if Sj =1, with W[L] "ON" when |W|=L and (W[L] mutually exclusive W[K]) when L≠K.
NOTE: Some bit positions (π) and W(L) depend on j. For ease of comprehension and notation such dependencies have been omitted.
Given that |Wj |≦22 ((Sj Xsm |Wj |)max =22 Xsm) and because sign extension preserves values, Sj Xsm |Wj | can be represented as in FIG. 2. From FIG. 2, it can be easily verified that: If Sj =0, then θj * is the correct representation of Sj Xsm |Wj |. If Sj =1, then a "hot 1" must be appended at position 2-(n-1) position. Therefore, theorem 1 holds true.
It may be observed that X0 is always equal to (3X)0. Thus, π-2 =X0 * W[0]. It is also true that because X0 =0, π-2 =X0 *. However, this may not always be the case for other representations such as the two's complement notation to be considered later.
Let Sj Xsm |Wj |=θj, then it can be proven that for every 1≦j≦m,
θj =θj *+δ2-[(n-1)+3]
such that: δ=0 if Sj+1 =0, or δ=1 if Sj+1 =1. When j=m+1,
Sm+1 Xsm |Wm+1 |=θm+1 *
This is because no more extension is necessary due to the fact that there are no more rows (or scans) to follow, Given that W1 ≧0, δ1 is always positive and there is no need for an extra row for adding a possible "hot 1". Thus,
Xsm Ysm =θ1 2-2 +θ2 2-5 + . . . +θj 2-[3j-1 + . . . +θm+1 *2-[3(m+1)-1](2.5)
(2.5) represents a matrix containing m+1 rows starting at column 20 and ending at column 2-[3(m+1)-1+n-1],
Given that sign extension will not change θj for 1≦j<m+1, it can be stated that ##EQU5## thus, the j-th row of (2.5) can be written as: ##EQU6## Analogous conclusions can be reached for Φm+1 *. The representation of Φj in (2.6) implies that the Xsm Ysm matrix will not change value when added as represented in FIG. 3. Given that the positions of the product starting at 2-1 are of interest, the product bits corresponding to the positions 21, 20 need not to be considered. In regard to the multiplication, it can be stated that the matrix in FIG. 5 corresponds to the matrix in FIG. 4. Note that, in FIG. 5, α=π-2, or is of interest in the product. In the incorporated patent application it is proven that the lower triangle matrix containing the α's is equivalent to: ##EQU7## where αj represents the sign of the j-th row. Now, αj =1 if and only if the j-th row is negative. It also can be proven that the lower triangular matrix is equivalent to a sign encoding into the band of the matrix. The encoding can be embedded in Φj as follows:
The sign encoding depends on Sj because Sj alone determines the 1 or 0 extension. That is, given that X0, the sign bit, is always 0, Sj determines if Φj is a positive or negative number. Therefore,
Case 1:
Sj =0, meaning that Wj ≧0, ##EQU9## The implication is that "1 1 1" has been added on the j-th row if Sj =0, which proves the validity of Theorem 2 by placing the right encoding as taught in the incorporated patent application.
Case 2:
Sj =1, meaning that Wj <0, and ##EQU10## which is equivalent to: ##EQU11## which corresponds to the right encode "1 1 0" for Sj =1 as taught in the incorporated patent application. Therefore, Theorem 2 holds true.
Case 1:
Sj =0 then ##EQU13## which is equivalent of encoding '1 0 0 0' in the front |Φm+1 |. This corresponds to the right encode of the last row as taught in the incorporated patent application.
Case 2:
Sj =1 then ##EQU14## which is equivalent to encoding "0 1 1 1" in front of |Φm+1 | and which corresponds to the right encode as taught in the incorporated patent application when Sj is negative. Thus, Theorem 3 holds true.
Trivial from theorems 1, 2, and 3 and equation (2.6).
Theorem 4 dictates the formulation of a sign magnitude multiplication. It may be asked whether such a device can be used to compute a two's complement number multiplication. The following derivations describe how the sign magnitude multiplier can be used to compute both sign magnitude and two's complement multiplication with neither hardware correction nor extra delay and with but minimal modification on the hardware. Assume two n-bit two's complement non-fractional numbers, Xtc and Ytc, and consider multiplication, Xtc Ytc, ##EQU17## The implication is that the non-fractional numbers Xtc and Ytc can be seen as fractional with appropriate decimal point shifting and proper renaming of the bit position.
Let ##EQU18## Ytc * with proper renaming, can be written as: ##EQU19## To prove that a sign magnitude multiplier will accommodate a two's complement multiplication, it must be proven that Theorems 1, 2, 3, and 4 hold true for both multiplications. Except for shifting the decimal point, Xtc, Ytc and Xsm, Ysm have equivalent expressions if one of the two is named differently.
In hardware, this translates to forcing the operands into the registers with the LSB's at the same position, which is only a convention and not a hardware requirement. It can be easily verified that Theorem 1 holds true for both multiplications.
Thus, θj =θj *+δ2-[(n-1)+3] and θm+1 =θm+1 *
In order to avoid an extra row (extra partial product) and preserve the matrix, it must be shown that W1 ≧0. For sign magnitude numbers, Y0 =0, which means W1 ≧0. This is not true for two's complement notation. Yn-1 may be either 0 or 1 and thus to preserve the matrix,
-4Yn-1 +2Yn-2 +Yn-3 +Yn-4 ≧0 (4.1)
This requires that Yn-1 =Yn-2 =Yn-3 =Yn-4, which implies that in order to preserve the matrix, the first decode must be all sign bits. Theorems 2 and 3 do not hold true. This is because sign extension has been encoded and, for sign magnitude multiplication, X0 =0 (i.e., Xsm has been forced to be positive). Thus, Sj determines the sign of Φj. This is not true for two's complement multiplication. Xn-1 may be 1 or 0. Thus, Sj alone can not determine the sign bit of Φj. The following holds true.
The sign of Φj for both sign magnitude and two's complement is determined by π-2 =[Xsign V Sj ]→W(0)with W(0)=1 if and only if |W|=0 with Xsign being equal to the most significant bit of X, and Sj being the sign of Wj.
It must be proven that X0 *→W(0)=(Xsign V Sj)→W(0), with X0 being equal to the most significant bit of X, in essense, Xsign.
Case 1:
|W|≠0 implying that →W(0)=1 and π-2 =Xsign V Sj. Table 1 describes the computation of the sign of Φj.
TABLE 1______________________________________The correction of sign of ΦjXsign Sj Sign of Φj______________________________________0 0 00 1 11 0 11 1 0______________________________________
It can be easily verified that π-2 respects the computation of Table 1. Thus, Xsign V Sj will compute the resulting sign of Φj.
Case 2:
|W|=0 i.e., W(0)=1 and π-2 =0
From (a) X0 →W(0)=0. Thus, Theorem 5 holds true for case 2.
Theorems 2 and 3 are valid if and only if→Sj and Sj are substituted with →π-2, and π-2, respectively, with π-2 =(Xsign V Sj)→W(0).
For Theorem 2, the following holds true when Sj is substituted by π-j. ##EQU20## such that 2≦j≦m and π-2 =(Xsign V Sj)→W(0). ##EQU21## Case 1:
|W|≠0, thus W(0)=0, implying that →[Xsign V Sj)→W(0)]=→[Xsign V Sj ]
Subcase 1: Sign Magnitude
Sj =0, then→(Xsign V Sj)=→Xsign. Thus, '111' has been added in the j-th row.
Sj =1, then →(Xsign V Sj)=Xsign. Thus, '110' has been added in the j-th row and Theorem 2 holds true.
Subcase 2: Two's Complement Multiplication
If Sj =0, then→(Xsign V 0)=→Xsign
If Xsign =0, then the j-th row is positive and '111' has been added.
If Xsign =1, then the j-th row is negative and '110' has been added.
If Sj =1, then→(Xsign V 1)=Xsign
If Xsign =0 then the j-th row is negative and '110' has been added.
If Xsign =1 then the j-th row is positive and '111' has been added.
Therefore, Theorem 2 holds true for subcase 2.
Case 2: |W|=0 which implies W(0)=1.
Thus,→[(Xsign V Sj)→W(0)]=1 and '111' is added which implies that Theorem 2 holds true for case 2.
For Theorem 3, the following holds true: ##EQU22## Case 1: |W|≠0 then→W(0)=1, π-2 =(Xsign V Sj)
Subcase 1:
If Sj =0, then π-2 =Xsign
When the sign magnitude notation is considered, then π-2 =0 and '1000' has been added in front of Φm+1.
For two's complement notation, either '1000' is appended to the front of Φm+1 if X is positive, or '0111' if negative. Thus, Theorem 3 holds true for subcase 1.
Subcase 2:
If Sj =1, then π-2 =→Xsign
For the sign magnitude notation, Φj is negative and '0111' has been appended in front of Φm+1.
For two's complement notation, either '0111' is appended if X is positive, which also indicates Φj negative or '1000' if negative, which indicates Φj positive.
Thus, Theorem 3 holds true for subcase 2.
Case 2:
|W|=0, then W(0)=1 and π-2 =0 implying that '1000' has been added in all cases meaning Theorem 3 holds true for case 2.
For every Φj with 1<j≦m, three bits must be added and computed by→π-2 and π-2. Two bits are 1's and the third bit (b) is equal to:
(b)=→[(Xsign V Sj)→W(0)]
also for the row in which j=m+1, four bits must be added computed by π-2, and π-2 while Xsign is known Sj and W(0) must be calculated. Sj determines π-2 and also the inversion; and also determines addition of a `hot 1` on the previous row.
Given that W, consider 4 bits at the time, namely, Yk-2, Yk-1, Yk, Yk+1. W<0 if and only if Yk-2 =1 and it is not the case that W=0. Sj =Yk-2 →W(0) and →Sj =→Yk-2 +W(0).
Thus (b)==>→[(Xsign V Yk-2)→W(0)]
W=0 if and only if Yk-2 =Yk-1 =Yk =Yk+1
i.e., W(0)=(Yk-2 Yk-1 Yk Yk+1)+(→Yk-2 →Yk-1 →Yk →Yk+1) →W(0)=→[(Yk-2 Yk-1 Yk Yk+1)+(→Yk-2 →Yk-1 →Yk →Yk+1)]
(b)==>→(Xsign V Yk-2)+(Yk-2 Yk-1 Yk Yk+1)+(→Yk-2 →Yk-1 →Yk →Yk+1) and Sj =Yk-2 →((Yk-2 Yk-1 Yk Yk+1)+(→Yk-2 →Yk-1 →Yk →Yk+1))
It can be observed that a partial product with W=0 can be represented in two different ways since their sums are equal: ##EQU23##
The previous discussed version used encoding (a); for completeness and to show a reduction in control logic an equivalent method which uses both versions (a) and (b) is shown. If both versions are assumed, then the following holds true:
π-2 =((Xsign W(0)) V Sj)
with Sj =Y.sub.(k-(s-2)) and Sj+1 =Y (k+1) and Xi *=Xi if Y.sub.(k-(s-2)) =0 or Xi *=Xi if Y.sub.(k-(s-2)) =1 and δ=0 if Yk+1 =0, or δ=1 if Yk+1 =1, If W does not equal 0, then as proven previously, π-2 =(Xsign V Y.sub.(k-(s-2))) will compute the right encoding.
If W=0, then π-2 =Y.sub.(k-(s-2)) and Sj =Y.sub.(k-(s-2)). If Y.sub.(k-(s-2)) =0, then both the previously discussed encoding and this encoding give version (a)'s representation of W=0. If Y.sub.(k-(s-2)) =1, then the previous encoding yields (a) and this encoding gives (b)'s representation of W=0. Since both are equivalent, this encoding is valid. Thus, for the given 1<j≦m, the encoding is valid. For j=m+1, the following encodings are used which are equivalent. ##STR1## Version (c) is used in the previous discussed method and both are used in the alternative method depending on Y.sub.(k-(s-2)). Thus, an alternative method of encoding the partial products has been discussed which uses less hardware. For more details on this see the figures and diagrams in the attachment.
Xsm Ysm and Xtc Ytc are equivalent to a matrix P, where: ##EQU24## such that Φ1 is guaranteed to be positive and equal to ##EQU25## and such that for every Φj, π-1, π0 and πi equal to the corresponding bit of X or its inversion depending on Sj corresponding to the row.
Thus Sj =Yk-2 →W(0) for any given j and δ=1 if and only if Sj+1 =1, π-2 =(Xsign V Yk-2)→W(0) where Xsign is the most significant bit of X, and →W(0) is computed by →((Yk-2 Yk-1 Yk Yk+1)+(→Yk-2 →Yk-1 →Yk →Yk+1)).
Now, Sj =Yk-2 →W(0)=Yk-2 →(Yk-2 Yk-1 Yk Yk+1 +→Yk-2 →Yk-1 →Yk →Yk+1), where Yk-2, Yk-1, Yk and Yk+1 are the four bits of Y considered by the j-th scan, with Yk-2 being the first bit, Yk-1, the second, Yk, the third, and Yk+1, and the fourth bit of the scan or with Sj, π-2 alternatively produced by Sj =Yk-2, π-2 =(Xsign →W(0)) V Yk-2.
Trivial from theorems 4, 5, and 6, and the alternative encoding.
Assuming the design of a sign magnitude multiplication given in "A Two's Complement Parallel Array Multiplication Algorithm" by Bough et al., IEEE TRANSACTIONS ON COMPUTERS, Vol. C-22, Pg. 1045-1047, Dec. 1973, the changes needed to accommodate both two's complement and sign magnitude multiplication on the same multiplier are now considered. Based on the previous theorems and observations, the following can be stated:
1. Place the two operand's bits properly. i.e., for both two's complement and sign magnitude, the Least Significant Bits should be at the same positions. Hardware and time cost nothing.
2. Xtc and Ytc must be properly sign-extended, which means that multiplexing is necessary when placing operands. Hardware addition is 10 buffers for repowering due to 32 and 48 fanouts from sign bit of X and Y multiplexor, respectively.
3. Proper calculation of 3X. One OR and one XOR (exclusive-OR) are needed as an extra.
4. Scan the j-th row.
5. Compute Sj properly.
6. Create Φj and Φm+1.
7. Create the sign extension encoding using π-2 instead of Sj. It costs 18 more XORs.
8. For the last row, it costs 6 cells more by changing the AND to an XOR.
9. For the cycle synchronization with other data, latches for sign extension will be added at XREGB and YREG, which adds 3 latches more.
As proven in [4], |Wj |≦2.sup.(s-2). Thus, s-2+n-1 bits are needed to represent Sj Xsm |Wj |. Then, there is Φj * such that it will represent Sj Xsm |Wj | with a possible `hot 1` added.
The incorporated patent application dictates the number of bits to be added in order to encode the sign extension, namely, s-1 for all the rows except for the last row that needs s.
Guarantee the first row is positive by having a first scan of s-1 sign extension extra bits for every scan 1<j≦m must be computed by π-2 =(Xsign V Sj)→W(0) so as to add s-1 one's if Φj ≧0 and s-2 one's followed by a zero if Φj <0. Also, π-2 will compute the s bits properly so that if Φm+1 ≧0, then a `0` will be added followed by s-1 `one`s. Or if Φm+1 <0, then a `1` will be added followed by s-1 `zero`s.
Using these theorems, an algorithm for forming the matrix is formulated. One first assumes s-bit overlapped scanning with m+1 partial products, m being =INT[(n-1/(s-1)], with INT being the integer division, and n the length of the multiplier Y. The value of s may be determined after conducting a comparative study of the hardware and timing requirements of an application to calculate the multiples with due consideration of the adding circuitry.
In the explanation to follow, it is assumed, for the purposes of illustration, that n=57 and s=4. In this case, m+1=19. None of these values are intended to, and should not, limit the teachings of this description. In fact, the ranges of n, s, and m are limited only by design considerations and the relationships established above.
Referring to FIG. 6, the matrix of the embodiment is illustrated. Assuming that scanning starts at the most significant bits of Y, that is, partial product is shifted with respect to the j-th partial product by 3(=s-1) bits to the right, where i is an integer, ≧1 and ≧m+1. As illustrated in FIG. 6, where the successive partial products 1-19 are shown as rows of the matrix, each row, save the first two, is shifted to the right by 3(=s-1) bits relative to the previous row. Each partial product includes the product of partial multiplication indicated by π signs. In addition, each partial product has appended sign encoding bits. The first partial product has the sign encoding bits appended at its right-hand end, the last partial product has sign encoding bits appended at its left-hand end, all of the middle partial products have sign encoding bits appended at right and left ends.
As FIG. 6 shows, the first partial product has 61 bits, the middle partial products (the second through the eighteenth) have 64 bits, and the last partial product, the nineteenth, has 62 bits. The π sign represents a significant unknown bit of a partial product. The * represents a significant unknown bit which is in a partial product's matrix for sign magnitude and two's complement multiplication, but which is computed differently for the two forms, as described above. The values 1 and 0 represent known significant bits of the partial product rows. Last, the δ sign represents a significant unknown bit of a row specifically for the encoding of a "hot 1" as described above. Out of the 1,211 bits that make up the matrix, only 21 (all indicated by *) are encoded based upon the form of the operands.
The first row of the matrix of FIG. 6 is illustrated in FIG. 7A. This row is produced by scanning the operand X with the first multiplier bit group illustrated in FIG. 7B. As shown, the first row is 61 bits wide, with the three last bits being the right encode of "00δ" where δ, equal to Y3, is the "pseudo-sign" of the next partial product. The bits of the row are labeled -1 through 56, where -1 and 0 are bits resulting from the operand X being multiplied by 2.sup.(s-2) or 22. There are no terms denoted by Y0 Y1 Y2 Y3, the (j+1)th partial product is shifted with respect to the j-th partial product by 3(=s-1) bits to the right, where i is an integer, ≧1 and ≧m+1. As illustrated in FIG. 6, where the successive partial products 1-19 are shown as rows of the matrix, each row, save the first two, is shifted to the right by 3(=s-1) bits relative to the previous row. Each partial product includes the product of partial multiplication indicated by π signs. In addition, each partial product has appended sign encoding bits. The first partial product has the sign encoding bits appended at its right-hand end, the last partial product has sign encoding bits appended at its left-hand end, all of the middle partial products have sign encoding bits appended at right and left ends.
As FIG. 6 shows, the first partial product has 61 bits, the middle partial products (the second through the eighteenth) have 64 bits, and the last partial product, the nineteenth, has 62 bits. The π sign represents a significant unknown bit of a partial product. The * represents a significant unknown bit which is in a partial product's matrix for sign magnitude and two's complement multiplication, but which is computed differently for the two forms, as described above. The values 1 and 0 represent known significant bits of the partial product rows. Last, the δ sign represents a significant unknown bit of a row specifically for the encoding of a "hot 1" as described above. Out of the 1,211 bits that make up the matrix, only 21 (all indicated by *) are encoded based upon the form of the operands.
The first row of the matrix of FIG. 6 is illustrated in FIG. 7A. This row is produced by scanning the operand X with the first multiplier bit group illustrated in FIG. 7B. As shown, the first row is 61 bits wide, with the three last bits being the right encode of "00δ" where δ, equal to Y3, is the "pseudo-sign" of the next partial product. The bits of the row are labeled -1 through 56, where -1 and 0 are bits resulting from the operand X being multiplied by 2.sup.(s-2) or 22. There are no terms denoted by *, implying that this partial product is the same for sign magnitude operands as for two's complement operand.
The equations for determining the bits of the first partial product are given by equations (A1)-(A4):
π(-1)=(X.sub.(1) W[4]+3X.sub.(1) W[3]+X.sub.(0) W[2]+X.sub.(0) W[1]) for i=-1 (A1)
π(0)=(X.sub.(2) W[4]+3X.sub.(2) W[3]+X.sub.(1) W[2]+X.sub.(0) W[1]) for i=0 (A2)
π(i)=(X.sub.(i+2) W[4]+3X.sub.(i+2) W[3]+X.sub.(i+1) W[2]+X.sub.(i) W[1]) for i=1 to 56 (A3)
wherein the coefficients are given by equations (C0)-(C4):
W[0]=(Y.sub.(k-2) Y.sub.(k-1) Y.sub.(k) Y.sub.(k+1))+(→Y.sub.(k-2) →Y.sub.(k-1) →Y.sub.(k) →Y.sub.(k+1))(C0)
W[1]=(Y.sub.(k-2) Y.sub.(k-1) +→Y.sub.(k-2) →Y.sub.(k-1))(Y.sub.(k) →Y.sub.(k+1) +→Y.sub.(k) Y.sub.(k+1)) (C1)
W[2]=(→Y.sub.(k-1) Y.sub.(k) Y.sub.(k+1))+(Y.sub.(k-1) →Y.sub.(k) →Y.sub.(k+1)) (C2)
W[3]=(→Y.sub.(k-2) Y.sub.(k-1) +Y.sub.(k-2) →Y.sub.(k-1))(Y.sub.(k) →Y.sub.(k+1) +→Y.sub.(k) Y.sub.(k+1)) (C3)
W[4]=(→Y.sub.(k-2) Y.sub.(k-1) Y.sub.(k) Y.sub.(k+1))+(Y.sub.(k-2) →Y.sub.(k-1) →Y.sub.(k) →Y.sub.(k+1))(C4)
FIGS. 8A and 8B illustrate the j-th partial product for 2≦j≦18. These rows each have 64 bits, including three sign encoding bits on each end. In FIG. 8A, the left hand bits="11*", where * denotes the bit that is determined differently for signed magnitude operands than for two's complement operands. The three right-hand bits add a "hot 1" to the j+1 partial product when necessary and are labeled "00δ" where δ=Y.sub.(k+1). The bits of jth partial product are labeled -1 to 56, and -4-3-2 for the left-hand encoding. FIG. 8B shows how the multiplier Y is scanned to produce the j-th partial product. In FIG. 8B, four consecutive multiplier bits Y.sub.(k-2) -Y.sub.(k+1) scan the multiplicand X to produce the j-th partial product, with the multiplier bit group for scanning the (j+1th) partial product overlapping the bit group of FIG. 8B by 1 bit, Y.sub.(k+1). The equations for determining the bits of the j-th partial product are given by equations D(1)-D(7):
π(-4)=1 (D1)
π(-3)=1 (D2)
π(-2)=→(Y.sub.(k-2) V (X.sub.(0) →W[0])) (D3)
π(-1)=Y.sub.(k-2) V (X.sub.(1) W[4]+3X.sub.(1) W[3]+X.sub.(0) W[2]+X.sub.(0) W[1]) for i=-1 (D4)
π(0)=Y.sub.(k-2) V (X.sub.(2) W[4 ]+3X.sub.(2) W[3]+X.sub.(1) W[2]+X.sub.(0) W[1]) for i=0 (D5)
π(i)=Y.sub.(k-2) V (X.sub.(i+2) W[4]+3X.sub.(i+2) W[3]+X.sub.(i+1) W[2]+X.sub.(i) W[1]) for i=1 to 56 (D6)
δ=Y.sub.(k+1) (D 7)
It will be observed that determination of bit π(-2) for the j-th row is an exclusive-or (XOR) term. In view of the discussion above regarding Theorem 7, it will be appreciated that, if the FIG. 1 multiplier were limited to sign magnitude operands, the right-hand side of equation (D3) would include only Y.sub.(k-2). However, in order to accommodate both sign magnitude and signed binary operands, this bit is determined according to equation (D3). Thus, sign encoding the jth row depends upon bit Y.sub.(k-2), drawn from the jth multiplier bit group, or upon the sign bit X0 of the multiplicand.
FIG. 9A illustrates 19-th partial product, included in the last row of the matrix. As shown, there is no right encoding, there being no subsequent matrix row, and thus no requirement to possibly encode a "hot 1". The left-side encoding includes four bits, π(-5)-π(-2). The equations for the bits of the 19-th row are given by:
π(-5)=→(Y.sub.(54) V (X.sub.(0) →W[0])) (E1)
π(-4)=(Y.sub.(54) V (X.sub.(0) →W0])) (E2)
π(-3)=(Y.sub.(54) V (X.sub.(0) →W[0])) (E3)
π(-2)=(Y.sub.(54) V (X.sub.(0) →W[0])) (E4)
π(-1)=Y.sub.(54) V (X.sub.(1) W[4]+3X.sub.(1) W[3]+X.sub.(0) W[2]+X.sub.(0) W[1]) for i=-1 (E5)
π(0)=Y.sub.(54) V (X.sub.(2) W[4]+3X.sub.(2) W[3]+X.sub.(1) W[2]+X.sub.(0) W[1] for i=0 (E6)
π(i)=Y.sub.(54) V (X.sub.(i+2) W[4]+3X.sub.(i+2) W[3]+X.sub.(i+1) W[2]+X.sub.(i) W[1]) for i=1 to 56 (E7)
As equations (E1)-(E4) show, the FIG. 1 multiplier accommodates both sign magnitude operands and signed binary operands in complemented form by exclusive-ORing the first bit, Y54, of the 19-th multiplier bit group with an expression including the sign bit X0 of the multiplicand operand.
Thus, the matrix for 4-bit overlapped scanning of a 57-bit multiplicand has been shown in detail. As FIG. 6 illustrates, the middle 17 rows of the matrix are each offset by s-1 bits from the preceding matrix row, except for the second row, which is not offset from the first. The last row is offset from the penultimate row by s-2 bits. It will be evident to those skilled in the art that the equations given above for matrix rows can be generalized to the case of a multiplicand having n-1 bits, not counting the sign bit, in which each partial product includes at most ((n-1)+(s-2)) bits, with the right and left end encodes for the middle partial products being s-1 bits each. Further, the second row through the next to last row are right-offset by s-1 bits.
The entire matrix in the general case is 2(n-1) wide and has m+1 partial products. The first row of the general matrix will contain ((n-1)+(s-2)+(s-1)) bits, the first ((n-1)+(s-2)) bits being the partial product, with s-1 bits appended on the right end. The appended bits consist of s-2 0's followed by a δ which is the "hot 1" for the second partial product, and which is determined by Y.sub.(s-1). In this case, Y0 is the most significant bit, and is also the sign bit, for the sign magnitude multiplier, while Y0 through Ys-1 are all equal to the sign bit for a complemented binary multiplier.
For the j-th row of the general case, where 2≦j≦m, each row is ((n-1)+(s-2)+2(s-1)) bits wide, with ((n-1)+(s-2)) bits representing the partial product, and s-1 sign encoding bits appended on the left- and right-ends of each row to encode sign extension and the possibility of a "hot 1" respectively. Each left-sign encoding consists of s-2 ones, followed by *. These bits are labeled (-(2s-4)) through (-(s-2)). The right encode includes s-2 0's followed by a δ=Yk+1. The partial product has bits at positions (-(s-3)) through (n-1).
Last, the (m+1)th, the last, row of the partial product matrix in the general case has ((n-1)+(s-2)+s) bits. In this row, n-1+s-2 bits are needed to represent the partial product, and s bits are appended on the left end of the partial product. The s encoding bits are all denoted by *.
With the matrix thus explained, provision for generating it can be understood with reference now to FIGS. 10-17, in which an example using 4-bit overlapped scanning will be presented. In FIG. 10, the matrix assembler 26 is shown in greater detail, and includes a partial bit generator 40 and row generation circuitry 42. The partial bit generator 40 can be appreciated with reference to equation (A1)-(A3), (D4)-(D6), and (E5)-(E7). These equations are for generating partial product bits π(-1)-π(i) for the rows of the matrix of FIG. 6. The partial bit generator 40 combines X, 3X and W[1]-W[4] as required for these equations. The row generation circuitry 42 combines the generated terms with Yk-2 to produce the partial product bits for the middle and last rows of the matrix, and also cooperates with the sign encoder to append the sign encoding bits, as required, by combining Yk-2, X0, and W[0]. The row generation circuitry 42 produces the sequence of m+1 shifted partial products with appended sign-encoding bits as illustrated above in FIGS. 6-9B.
Prior to matrix assembly, operands are aligned and extended, if necessary, as illustrated in FIGS. 11 and 12. In FIG. 11, a register 50 includes end storage spaces for storing a sign magnitude multiplier of n bits, Y0 -Yn-1, as described above. Bit Y0 is both the sign bit and MSB of the sign magnitude multiplier, while bit Yn-1 is the LSB of the multiplier. A signed binary multiplier in two's complement form, Ytc, is constrained to include n-(s-1) bits. These bits extend from bit Y0 through bit Yn-s tc, from most to least significant, bit Y0 being the sign bit. In the practice of the invention, in order to ensure that the first partial product magnitude is all zeros, s-1 bits are appended on the front of a signed binary multiplier, the bits being replications of the sign bit Y0. This is accomplished by, for example, placing the signed binary multiplier in the n-(s-1) least significant bit positions of the register 50, and multiplexing Y0 with multiplexer 52 into the first s-1 bit positions of the register 50. In this case, the multiplexer 52 multiplexes the sign bit of a signed complement multiplier into the first s-1 bits of the register 50 only in response to a signal tc indicating, for example, a two's complement multiplier.
Inspection of FIG. 12 will reveal that a signed binary multiplicand Xtc is aligned with a sign magnitude multiplicand by being entered into the least significant bits of a register 60, with the sign bit being multiplexed through a multiplexer 62 into the s-1 most significant bits in response to the tc signal. Otherwise, if X is a sign magnitude operand, it is entered into the register 60 in order from most to least significant bits.
The combining circuit 22 which produces the coefficients W[0]-W[4] is illustrated in detail in FIGS. 13A-13E, which embody equations (C0)-(C4), respectively. As shown, the coefficients are generated in response to the bits of the current multiplier bit group which is scanning the multiplicand to produce the current matrix row.
The partial bit generator is illustrated in FIG. 14. In FIG. 14, 58 circuits are connected in parallel and respond to values of X and to the coefficients W[1]-W[4]. Each of the circuits a generates partial bit which is used to generate one of the 58 partial product bits for each row of the matrix in FIG. 6. Thus, the circuit consisting of AND gates 70-73 and OR gate 74 combines X1, 3X1, X0, and the four coefficients W[1]-W[4] to produce a partial bit for π(-1) in a partial product. Partial bit 0 is generated by four AND gates 80-83 which are connected to the OR gate 84 to combine X0, X1, 3X2, and X2 with the four coefficients. Partial bit π(i) is produced by circuit consisting of the four AND gates 90-93, and the OR gate 94, which are connected to combine the four coefficients with Xi , Xi+1, 3Xi+2, and Xi+2.
Returning to the circuit for partial bit (-1), each of the AND gates 70-73 is a two-input, single-output gate, with each output connected to a respetive input of the OR gate 74. AND gate 70 combines X1 with W[4], the gate 71 combines 3X1 with W[3], the AND gate 72 combines X0 with W[2], while the AND gate 73 combines X0 with W[1]. Inspection of equation (A1) will confirm that the first partial bit circuit indeed produces bit π(-1) for the first partial product. Inspection of equations (D4) and (E5) will confirm that the first partial bit circuit produces the term which is exclusive-ORd with Yk-2. Similarly, the remaining partial bit circuits produce bits π(0) and π(i) for the first partial product as required by equations (A2) and (A3). For the middle and last rows of the matrix of FIG. 6, the remaining partial bit circuits produce a term which is exclusive-ORd with Yk-2. Thus, during the first scan of multiplicand, the partial bit circuit of FIG. 14 produces the partial product forming the first row of the matrix of FIG. 6. For the remaining scans, the partial bit circuit produces values which are exclusive-ORd with one of the bits of the multiplier group currently scanning to produce partial product bits.
FIG. 15 illustrates the portion of the matrix assembler 26 which assembles the first row of the matrix of FIG. 6. The outputs of the partial bits generator 40 are fed directly to a storage location for the first partial product row, the storage location being illustrated by a register 100.sub.(1). The first 58 bits of the register 100.sub.(1) receive directly the bits output by the partial bit generator 40 in their significance sequence. In this regard, their significance sequence is π(-1)π(0) . . . π (i), the sequence given by equation (7.1). The manner in which the sign encoding circuit 24 operates to append boundary bits on the right end of the first partial product term is also shown in FIG. 15. As already described, for the first partial product, S-1 bits are appended to the right end of the partial product term. These bits are all zeros, if the following partial product is positive. If, however, the following partial product is negative, the bits appended to the right of the first partial product are S-2 zeros, followed by a 1. Since the sign of the next row, as proven above, is given by Yk+1, (for the first row, Y3), the sign encoding circuit 24 in FIG. 15 includes bit lines 110, 112, and 114 feeding the last 3 bit locations in storage location 100(1). The bit lines 110 and 112 are hardwired to a logic level "0", while the bit line 114 is responsive to the value of Y3. Thus, when Y3 is at logic level "0", the sign value for the first row will be 0, which indicates that the next row is positive. If, on the other hand, Y3 is 1, the value of delta will be 1, indicating that the sign of the next matrix row is negative.
FIG. 16 illustrates the generation of matrix rows 2 through m according to the invention. In FIG. 16, the partial bit generator 40 is connected to the row generator circuit 42. The row generator circuit consists of exclusive-or (XOR) gates 120-1 -120i. Each of the XOR gates receives as inputs a respective partial bit from the partial bit generator 40 and multiplier bit group bit Yk-2. The outputs of the XOR gates of the row generator circuit are connected to respective bit cells of a register 100.sub.(j) representing a storage location for matrix row j. It will be appreciated that the 58 bits of the partial product in the j-th row of the matrix will be in the significance sequence from π(-1) through π(i). The s-1 bits are appended to the right end of the partial product of the j-th row are generated by the sign encoding circuit 24 as described above in connection with FIG. 15. The s-1 bits appended to the left hand end of the partial product are generated in the sign encoding circuit 24 as illustrated in FIG. 16. In this regard, three sign encoding bits are generated for appending to the left end of the j-th partial product, since s=4. If the partial product term is positive, the encoding is s-1 1's; and if negative, the encoding is s-2 1's followed by a 0. In FIG. 16, lines 115 and 116 are permanently hardwired to a logic "1". Bit line 117 is connected to the output of exclusive-nor (XN) gate 142. The inputs to the XN gate 142 are Yk-2 and the output of the AND gate 140, which combines X0 with →W[0]. Thus, the j-th row of the matrix conforms to the illustration given by equation (7.2).
Formation of the (m+1)-th row of the FIG. 6 matrix is illustrated in FIG. 17. In FIG. 17, a register 100.sub.(m+1) illustrates a storage location where the last row of the matrix is stored. The fifty-eight bits comprising the row's partial product are generated as in FIG. 16 by the partial bit generator 40 and the row generator 42. In the case of the last row, s encoding bits are appended to the left end of the partial product to complete the row. In this regard, s=4, and the four bits are π(-5) through π(-2). For π(-5), the XN gate 152 combines Y54 (which is Yk-2 for the last multiplier bit group), with the output of AND gate 150 combining X0 and →W [0]. The combination of AND gate 150 and XOR gate 154 satisfies each of equations (E2)-(E4). Thus, it will be evident that either "0111" or "1000" will be appended onto the left end of partial product m+1, as provided in the discussion of alternative sign encoding above.
For the case of this embodiment, in which s=4, n-1=56, and m+1=19, the derivation of the matrix of FIG. 6 will be described. Each row of the matrix of FIG. 6 is produced by scanning the multiplicand X with one of a sequence of overlapping bit groups of the multiplier Y. The first partial product is obtained by scanning the multiplicand with bits Y0 through Y3, the second scan entails bits Y3 through Y6, and so on. With this division of the multiplier Y, there are 19 scans, and hence, 19 partial products are produced.
In creation of the matrix, the partial product terms in all rows, except the first and last, are appended with s-1 bits at each end to make them uniform in length and displacement. The appending also "bands" the matrix. Each partial product is represented as 58 bits which is n-1+s-2. Negative partial products are effectively rendered in one's complement, with a "hot 1" added by appending the previous partial product to give the two's complement. Thus, s-1 bits are added to the right of every partial product, save the last, to account for representing the negative products as one's complement numbers, rather than two's complement numbers. If partial product j is negative, its representation is in one's complement. Appending 001 to the right of the one's complemented (j-1)th partial product and aligned with π(n-1) of the jth row will render partial product j in two's complement form when the partial products are added. Of course, 000 is appended to the right of each partial product in a row preceeding a positive partial product.
Last, three bits are appended to the left of every middle partial product. This is done to extend the sign of any negative partial products. These three bits are 111 for positive partial product and 110 for negative. The last partial product has an s-bit encoding appended to the left-hand end which is 0111, denoting that the product is negative or 1000 if the product is positive.
Thus, the overlapped, banded scanning matrix is formed with first row having 61 significant bits, the next 17 rows having 64 significant bits, and the last row having 62 significant bits. Each row of the matrix is shifted 3 bit positions to the right with respect to the preceeding row. Since the partial product in the first row has no 3 bit sign extension on the left, the first and second rows begin in the same column. Because the last row has no bit extension on the right, the last and next to last rows end in the same column. Also, since the last row is extended 4 bits on the left row, the last row begins 2 bit positions to the right of the penultimate row.
This matrix can be reduced to a product using carry save adder tree technology. For example, the carry save adder tree of FIG. 18 includes 17 carry-save adders, CSA1-CSA17. This adder structure requires division of the matrix of FIG. 6 into 6 sets of three rows plus a 7th set having one row. The first 6 sets, for example, rows 1-18 are then processed in the first stages CSA1-CSA6 of the carry save adder tree. In the second stage of the tree, a reduced matrix of partial product terms is combined. The designations C1, S1, C2, S2, C3, S3, C4, S4, C5, S5, C6, and S6 indicate the respective carry and sum outputs from the carry save adders of the first stage of the tree of FIG. 3. There are now 4 sets of 3 rows each, which are added in the second stage of the tree comprising CSA7 -CSA10.
The third stage of the carry save adder tree adds the reduced matrix obtained from the second stage, which now includes three sets of three matrix rows, the last set including the last row of the original matrix which is added in CSA13.
The fourth stage of the carry save adder tree adds a further reduced matrix including two sets of three rows each. The first set is added in CSA14, and the second in CSA15. The fifth stage of the carry save adder, consisting of CSA16, now must add only a single set of three inputs, C14, S14, and C15. An extra row derived from output S15 is saved for the 6th stage of the tree as shown in FIG. 18. The final three rows of partial product terms of the matrix are added in carry save adder CSA17.
Returning to FIG. 1, the register 32, placed at the output of the carry save add circuit 30 and before 2-input adder 34 stores the two reduced matrix rows output by CSA17, which are provided to the adder 34 to produce the product resulting from multiplication of the operands X and Y.
In this description, the following notation is observed:
Xsm : sign magnitude representation of multiplicand X
Ysm : sign magnitude representation of multiplier Y
Xtc : two's complement representation of X
Xtc : two's complement representation of Y
Σ: summation
Y: exclusive --OR of terms
→: complementation of a term or a bit
+: logical OR of terms
the logical AND of terms is denoted by juxtaposition.
Obviously, many modifications and variations of the present invention are possible in light of these teachings, and, it is, therefore, understood that, within the scope of this detailed description, the invention may be practiced other than as specifically taught.
|Cited Patent
|Filing date
|Publication date
|Feb 25, 1970
|Nov 2, 1971
|Collins Radio Co
|Digitalized multiplier
|May 3, 1971
|May 1, 1973
|Honeywell Inf Systems
|Binary two{40 s complement multiplier processing two multiplier bits per cycle
|Jul 18, 1972
|Jun 5, 1973
|A series-parallel multiplication device using modified two{40 s complement arithmetic
|Oct 11, 1972
|Apr 16, 1974
|Bell Telephone Labor Inc
|Serial-parallel binary multiplication using pairwise addition
|Apr 1, 1974
|Feb 11, 1975
|Bell Telephone Labor Inc
|Two{3 s complement parallel array multiplier
|Apr 3, 1978
|Dec 19, 1978
|Motorola, Inc.
|Expandable 4 � 8 array multiplier
|Sep 24, 1982
|Mar 26, 1985
|Tokyo Shibaura Denki Kabushiki Kaisha
|Two's complement multiplier circuit
|Jul 21, 1983
|Jun 10, 1986
|International Business Machines Corporation
|High speed hardware multiplier for fixed floating point operands
|Feb 4, 1985
|Jan 5, 1988
|Nec Corporation
|Multiplying circuit
|Jun 19, 1985
|May 31, 1988
|Advanced Micro Devices, Inc.
|Parallel multiplier array with foreshortened sign extension
|Feb 18, 1987
|Jan 3, 1989
|Nec Corporation
|Arithmetic circuit capable of executing floating point operation and fixed point operation
|Jun 1, 1987
|Jan 3, 1989
|Motorola, Inc.
|Serial two's complement multiplier
|C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Trans. on Electronic Computers, Feb. 1964, pp. 14-17.
|C. S. Wallace, A Suggestion for a Fast Multiplier , IEEE Trans. on Electronic Computers, Feb. 1964, pp. 14 17.
|IEEE Transactions article by Charles R. Baugh et al., vol. C 22, No. 12, pp. 1045 1047, Dec. 1973 entitled A Two s Complement Parallel Array Multiplication Algorithm .
|IEEE Transactions article by Charles R. Baugh et al., vol. C-22, No. 12, pp. 1045-1047, Dec. 1973 entitled "A Two's Complement Parallel Array Multiplication Algorithm".
|IEEE Transactions article by Stylianos D. Pezaris, Apr. 1971, entitled "A 40-NS 17-Bit by 17-Bit Array Multiplier", pp. 442-447.
|IEEE Transactions article by Stylianos D. Pezaris, Apr. 1971, entitled A 40 NS 17 Bit by 17 Bit Array Multiplier , pp. 442 447.
|Citing Patent
|Filing date
|Publication date
|Jul 20, 1992
|Apr 12, 1994
|International Business Machines Corporation
|High performance array multiplier using four-to-two composite counters
|May 25, 1995
|Jul 8, 1997
|Texas Instruments Incorporated
|High radix multiplier architecture
|May 22, 1996
|Feb 9, 1999
|Samsung Electronics Co., Ltd.
|Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication
|Jun 19, 1998
|Jun 6, 2000
|Ati International Srl
|Circuit and method for wrap-around sign extension for signed numbers using replacement of most significant bit
|Jun 19, 1998
|Jun 27, 2000
|Ati International Srl
|Circuit and method for wrap-around sign extension for signed numbers
|Jun 4, 2001
|Jul 5, 2005
|Dsp Group, Inc.
|Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands
|Jun 1, 2001
|Aug 23, 2005
|Microchip Technology Incorporated
|Euclidean distance instructions
|Jun 1, 2001
|Aug 30, 2005
|Microchip Technology Incorporated
|Processor with dual-deadtime pulse width modulation generator
|Jun 1, 2001
|Oct 4, 2005
|Microchip Technology Incorporated
|Maximally negative signed fractional number multiplication
|Jun 1, 2001
|Dec 13, 2005
|Microchip Technology Incorporated
|Configuration fuses for setting PWM options
|Jun 1, 2001
|Dec 13, 2005
|Microchip Technology Incorporated
|Repeat instruction with interrupt
|Jun 1, 2001
|Jan 10, 2006
|Microchip Technology Incorporated
|Variable cycle interrupt disabling
|Jun 1, 2001
|Feb 21, 2006
|Microchip Technology Incorporated
|Sticky z bit
|Jun 1, 2001
|Feb 28, 2006
|Microchip Technology Incorporated
|Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
|Jun 1, 2001
|Mar 28, 2006
|Microchip Technology Incorporated
|Reduced power option
|May 23, 2005
|Jul 10, 2007
|Microchip Technology Incorporated
|Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
|Jun 1, 2001
|Dec 16, 2008
|Microchip Technology Incorporated
|Dual mode arithmetic saturation processing
|Jun 21, 2011
|Microchip Technology Incorporated
|Register pointer trap to prevent errors due to an invalid pointer value in a register
|May 25, 2005
|Jul 31, 2012
|Qualcomm Incorporated
|System and method of performing two's complement operations in a digital signal processor
|Jun 4, 2001
|Nov 1, 2001
|Hong John Suk-Hyun
|Multiplier capable of multiplication of large multiplicands and parallel multiplications small multiplicands
|Jun 1, 2001
|Dec 5, 2002
|Bowling Stephen A.
|Configuration fuses for setting PWM options
|Jun 1, 2001
|Dec 5, 2002
|Catherwood Michael I.
|Maximally negative signed fractional number multiplication
|Jun 1, 2001
|Dec 5, 2002
|Bowling Stephen A.
|Processor with dual-deadtime pulse width modulation generator
|Jun 1, 2001
|Dec 5, 2002
|Michael Catherwood
|Register pointer trap
|Jun 1, 2001
|Dec 12, 2002
|Catherwood Michael I.
|Euclidean distance instructions
|Jun 1, 2001
|Dec 12, 2002
|Catherwood Michael I.
|Dual mode arithmetic saturation processing
|Jun 1, 2001
|Dec 12, 2002
|Brian Boles
|Variable cycle interrupt disabling
|Jun 1, 2001
|Dec 19, 2002
|Michael Catherwood
|Repeat instruction with interrupt
|Jun 1, 2001
|Jan 2, 2003
|John Elliott
|Sticky z bit
|Jun 1, 2001
|Jan 2, 2003
|Michael Catherwood
|Modified harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
|Jun 1, 2001
|Jan 2, 2003
|Catherwood Michael I.
|Find first bit value instruction
|Jun 1, 2001
|Jan 2, 2003
|Conner Joshua M.
|Multi-precision barrel shifting
|Jun 1, 2001
|Jan 30, 2003
|Michael Catherwood
|Shadow register array control instructions
|Jun 1, 2001
|Feb 6, 2003
|Michael Catherwood
|Low overhead interrupt
|Jun 1, 2001
|Jul 3, 2003
|Catherwood Michael I.
|Reduced power option
|Dec 20, 2004
|Aug 4, 2005
|Microchip Technology Incorporated
|Register pointer trap
|May 23, 2005
|Sep 22, 2005
|Microchip Technology Incorporated
|Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
|May 25, 2005
|Dec 14, 2006
|Shankar Krithivasan
|System and method of performing two's complement operations in a digital signal processor
|Dec 11, 1995
|Jun 26, 2002
|Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Dec 28, 1988
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, A COR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:VASSILIADIS, STAMATIS;SCHWARZ, ERIC M.;SUNG, BAIK M.;REEL/FRAME:005014/0862
Effective date: 19881222
|Mar 16, 1993
|Certificate of correction
|Jul 15, 1993
|Fee payment
Year of fee payment: 4
|Feb 14, 1998
|Maintenance fee reminder mailed
|May 17, 1998
|Lapse for failure to pay maintenance fees
|Jul 28, 1998
|Expired due to failure to pay maintenance fee
Effective date: 19980520

subset: commoncrawl


text:
STARmeterSEE RANK
Up 1,338,422 this week
Herbert Stass (1919–1999)
Herbert Stass was born on October 7, 1919 in Oebisfelde, Germany as Herbert Staskiewicz. He was an actor, known for Beate S. (1979), Das ausgefüllte Leben des Alexander Dubronski (1967) and Kandidat Cormoran (1965). He died on November 11, 1999 in Berlin, Germany. See full bio »
Born:in Oebisfelde, Germany
Died:(age 80) in Berlin, Germany


text:
Mount Evans Closed For The SeasonIt's a sure sign that summer is winding down, Mount Evans has closed for the season.
Summit Section Of Mount Evans Highway Will Close TuesdayThe top section of the highway to the summit of Mount Evans is closing for the season after the Labor Day weekend.
Mt. Evans Road Temporarily Closes Due To ConditionsMount Evans Road is currently closed from Summit Lake to the top.
One Of The Best Views In Colorado Open For The SeasonThe 14 mile stretch of Mount Evans Road begins at Echo Lake and climbs through several climate zones before reaching the top.
Road To Mount Evans Summit OpensThe highway leading to the summit of Mount Evans is finally open after more than a month of clearing snow.
Mount Evans Highway To Open June 1The Mount Evans Highway will open to the summit on Wednesday morning.
Mount Evans Road To Remain Closed Through The Holiday WeekendThe popular summer destination of Mount Evans won't be accessible by car until at least Tuesday.
Mount Evans Set To Partially Re-Open On FridayRoad crews working on Mount Evans won't get the holiday weekend off.
Top Scenic Overlooks Near DenverNow that the weather is heating up and traffic conditions in the mountains are less treacherous, it's time to go site seeing. Denver's mountains offer plenty of scenic views, and many are located in areas with other attractions. This weekend, try something different. Pack up the car and head to one of the following places to take in the view.
NWS Boulder Issues First Advisory Of Season Due To Mountain SnowIt seems a little late for this type of headline but this year it's true.
Top Scenic Drives Near DenverOne of the best reasons to live in Colorado is its stunning natural beauty. Here are some of the best scenic drives that you can take near Denver to catch all of Colorado's incredible views.
First Snow Of The Season Visible Along The Front RangeColoradans awoke to dusted peaks and snow-capped mountains along the Front Range on Wednesday for the first time this season.


text:
See All Results
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Gastonia Inpatient Drug and Alcohol Rehab Centers
If you're looking to help yourself or someone you love struggling with substance abuse in Gastonia, NC, Rehabs.com offers a large online database of private exclusive centers, as well as a host of other options. We can help you find drug and alcohol treatment programs for a variety of addictions to cocaine, Xanax or any addictive drug or alcohol. Search for a great rehab center in Gastonia now, and get started on the road to recovery.
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Latest Reviews of Rehab Centers in Gastonia, NC and Nearby
Overall great program....
Helps stop cravings of other drugs. not organized, only consider this if u are highly addicted to op...
30, 60, 90-Day Inpatient Vs. Outpatient Rehabilitation in Gastonia, North Carolina
Getting clean from Fioricet, Palladone, alcohol or any other substance you or your loved one is addicted to takes an individualized treatment plan. Two options of drug or alcohol treatment centers in Gastonia can help you succeed: either Residential or Out-patient Rehab. Residential treatment offers enduring benefits with extended stays in a perfect rehabilitation program. Outpatient programs may be more convenient, but lack the stability and resources of 28-day programs to get clean and sober. Ultimately, the choice is yours, and we are here to help you find the best fit.
Mike Yow began his career in substance abuse treatment in 1988 at the Crawford Center in Greensboro, NC. Mike brings a broad range of experience in inpatient, outpatient, and extended treatment services. He has been certified by the North Carolina Substance Abuse Professional Practice Board since 19...
Fellowship Hall
Philip Cooper is a case manager and relapse prevention guide....
Next Step Recovery Transitional Living for Men
A dual-diagnosis refers to someone who is simultaneously dealing with both a substance abuse issue and a behavioral or mental problem. For instance, an addiction to alcohol or Adderall combined with an eating disorder or ADHD. In these cases, a residential rehab center becomes almost a necessity, incorporating quality inpatient treatment with group support, such as one might find in AA. Luxury drug rehabs in Gastonia, North Carolina will provide state-of-the-art treatment with upscale amenities for anyone requiring the very best drug treatment, just as Gastonia alcohol rehab centers will help those battling alcoholism to achieve sobriety.
Note About Insurance for Addiction Treatment: ComPsych, Healthsmart and Community Health Choice often cover at least a portion of your addiction therapy, and you can find out more about your own provider or benefit status here.
A Look at Gastonia Treatment Facilities With 71,000 residents, Gastonia, NC resembles many small, idyllic towns in the South, but it has a growing problem with drug and alcohol dependency. Gastonia treatment facilities help individuals assess their alcohol and drug use, address underlying personal issues and change addictive behavior. Drug and alcohol dependency is a chronic disease that can be effectively treated if medical and social assistance is sought. There are a number of resources that substance abusers and their families can utilize without even leaving town.
Many of the treatment facilities in Gastonia provide a variety of one-on-one and group therapies that employ the latest rehabilitative techniques.
Questions to Answer Before Entering a Rehab
Many people use drugs without considering themselves dependent, and, admittedly, there can be a fine line between recreational use and actual dependency. Unfortunately, in many cases a drug user can delude themselves into believing their drug use is not interfering with their lives. It may help you to discuss your drug use with your family, and ask yourself if your drug use has damaged the quality of your life. Consider whether your drug use is habitual or if it has led to actions on your part that were regrettable. If your need for the drug has compelled you to steal or commit a crime, seriously consider seeking professional assistance. According to the NationalInstituteonDrugAbuse, only 11.2 percent of addicted drug users sought treatment.
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Our vast online database provides many options in Gastonia, NC to help you get free from drugs. Once you have made the decision to get clean, you've taken the first step to success. Our toll-free helpline advisors can then help you take the next steps to recover from substance addiction and abuse with excellent centers in Gastonia.
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Stud Fasteners
Flush-Head Studs offer quick mating with plastic fasteners.December 4, 2015
Integrating X-Press™ threads, PEM Type FHX™ Studs enable quick mating with push-on plastic nuts, wire tie products, or other plastic fasteners in thin metal assemblies. Self-clinching units install permanently in metal sheets as thin as 1 mm and press into place using any standard press. Available with 5 mm and 6 mm threads in lengths from 10–25 mm, studs are made from hardened carbon steel and finished with zinc plus clear chromate as standard or rust-preventive oil finish as option. Read More
Uniquely Designed Variations of PEM® Self-Clinching Threaded Nuts, Studs, and Standoffs Allow for Close-to-Edge Placement Where Space for Fasteners is LimitedSeptember 25, 2015
Uniquely designed variations of PEM® self-clinching nuts, studs, and standoffs from PennEngineering® allow for close-to-edge placement in thin metal assemblies without compromising host sheet or fastener. Their engineering effectively reduces the standard minimum distance for "hole-centerline-to-edge" required for successful clinching to provide ideal solutions where space for fasteners is... Read More
Self-Clinching Nuts and Studs work with hard sheet materials.December 8, 2014
PEM® self-clinching nuts and studs, which include SH™ hard panel nuts and HFLH™ hard panel studs, are designed for permanent installation into hard sheet materials and suit automotive component attachment applications. Manufactured from hardened alloy steel, products enable close-to-edge mounting without risking panel buckling, eliminate need for embossing operations, and can be installed automatically using standard press or in-die technology. Read More
Heavy-Duty Studs clinch permanently into thin metal sheets.August 29, 2014
Available in lengths up to 2 in., PEM® Type THFE™ Studs feature enlarged head diameter that distributes axial tightening force over wide area to minimize compressive stress on host panel, optimize pull through performance, and develop full thread strength. Self-clinching studs install into steel or aluminum sheets as thin as .031 in. with hardness of HRB 85 or less on Rockwell B scale and HB 165 or less on Hardness Brinell scale. Thread sizes range from ¼-20 through 5/16-18 and M6–M8. Read More
Self-Clinching Studs attach thin metal assemblies.March 13, 2014
Designed to install permanently using standard press, PEM® Self-Clinching Threaded Studs include flush-head models for use in aluminum or stainless steel sheets as thin as .040 in. and stainless versions for corrosion resistance in even thinner stainless steel assemblies. Other types include low-displacement flush head studs for close-to-edge installation; non-flush studs for sheets as thin as .020 in.; and heavy-duty studs whose heads project above sheet to distribute axial tightening force. Read More
Self-Clinching Flush-Head Studs meet corrosion resistance needs.April 26, 2013
For attachment applications requiring corrosion resistance, PEM® Type FHP™ self-clinching flush-head studs are manufactured from A286 stainless steel and install permanently into stainless steel sheets as thin as .040 in. Products mount flush and permanently, becoming integral parts of assembly with only mating nut required for final component attachment. Studs can be supplied in thread sizes No. 4–40 through No. 10–32 and M3–M5 and in range of 10 standard lengths. Read More
ROBNET Is Proud to Announce that PC Construction Awarded ROBNET the Fastener Order for Over 40,000 lbs Type 316 Stainless Steel Nuts, Bolts, and Studs for the CAMBI Process Train PipingJanuary 30, 2013
The District of Columbia Water and Sewer Authority's wastewater treatment plant is going green in a big way. The authority, known as DC Water, is in the early stages of projects that will help meet stringent regulatory requirements for nitrogen as well as make improvements primarily aimed at improving water quality in the Chesapeake Bay. One of the projects is to reduce total nitrogen in the... Read More
System Solution with RIVTEXJune 11, 2012
The RIVTEX system solution from Arnold Umformtechnik and Arnold & Shinjo is a high-quality alternative to conventional welding. It cuts parts assembly costs whilst assuring every quality requirement. <4444>With the RIVTEX system studs and nuts are pressed into the ready-to-assemble sheet metal parts such that they do not fall out and are characterised by high twisting moments and press-out... Read More
Automotive Supplier Hetal-Werke Tests Arnold ATP StudsMay 14, 2012
The automotive division of Hetal-Werke, located in Alpirsbach (Germany), is intensively looking for alternatives to conventional joint technologies. In the future, ATP® TriPress fasteners from Arnold Umformtechnik are expected to be used in place of conventional weld-on studs. These press-in studs match the requirements profile of the company, which specialises in the full scope of kinematic... Read More
Swaging Collar Studs accommodate multiple panels, materials.February 22, 2011
Used for attaching dissimilar panel materials and/or multiple panels, PEM® Type SGPC(TM) studs torque-out resistance and allow for close centerline-to-edge distance to suit limited-space applications. Studs install into sheets as thin as .024 in. and in multiple panels whose total thickness does not exceed max sheet thickness of .047 in. Manufactured from 300 Series stainless steel, products can be used in sheets of any hardness and comes in thread sizes No. 2-56 through ¼-20 and M2.5-M6. Read More
Key Locking Studs target aerospace and military applications.May 5, 2010
Available in range of inch and metric sizes, in lightweight and heavy duty versions, Key Locking Studs feature solid one-piece design to provide high pull-out strength and torque-out capabilities. They can be used on soft materials such as aluminum or magnesium and removed using standard screw extractor without damage to parent material. Produced to NAS and SAE Standards (MS51833 and MS51834), studs come in variety of materials, including 303, A286, 17-4PH CRES and 4140 alloy steel. Read More
Pem® Concealed-Head Studs and Standoffs Install Permanently and Promote Smooth DesignsJanuary 29, 2010
Clinch Fastener Solutions For Thin-Metal Assemblies<4444>PEM® self-clinching concealed-head studs and standoffs install permanently in steel or aluminum sheets as thin as .062" / 1.6mm to provide strong and reusable threads for mating hardware in a wide range of thin-metal assembly applications. Their concealed-head feature contributes particular design benefits by allowing the side of the... Read More
High Tensile Strength Studs are made of carbon alloy steel.December 23, 2009
Available in thread sizes up to 5/16-18 or M8 and in lengths up to 1 in. or 25 mm, PEM® Type HFG8(TM) (unified) and HF109(TM) (metric) heat-treated clinch studs achieve tensile strength up to Grade 8 and Property Class 10.9, respectively. RoHS compliant fasteners can be installed permanently in carbon steel or HSLA steel sheets as thin as .040 in. with hardness up to HRB 89 on Rockwell B scale. Studs are installed without welding, using standard punch and anvil or automated equipment. Read More
Pem® Self-Clinching Studs Introduced in Longer Lengths and Larger Thread SizesSeptember 15, 2009
A new family of PEM® large-sized self-clinching studs introduces ideal solutions for applications demanding high strength and reliable performance. These robust clinch studs in lengths up to 6"/152mm and thread sizes up to ½"/M14 offer a value-added capability allowing users to select from a wide range of variations to tailor fastener to application needs.<4444>The carbon steel or alloy steel... Read More
PEM® Type HFHB Busbar® Clinch Studs Provide Superior Electrical/Mechanical AttachmentFebruary 14, 2008
PEM® Type HFHB BUSBAR® self-clinching studs provide ideal solutions for applications demanding superior electrical/mechanical attachment points in copper. These phosphor bronze externally threaded fasteners offer twice the conductivity of conventional carbon steel studs.<4444> The RoHS-compliant studs install permanently in copper sheets as thin as .050"/1.3mm and have been engineered for... Read More
Self-Clinching Studs provide high-strength attachment.August 31, 2006
Suited for applications demanding optimal electrical/mechanical attachment points in copper, PEM® HFHB BUSBAR® studs install permanently in copper sheets as thin as .050 in. Phosphor bronze fasteners feature external threads and are RoHS-compliant. When properly installed, pushout values up to 560 lb and torque-out values up to 18 lb-ft can be realized. Available in lengths up to 2.00 in., studs come in thread sizes of #10-32 through 3/8-16 and M5-M10. Read More
Mounted Permanently in Thin Metal Sheets: PEM® Concealed-Head Clinch Studs and Standoffs Promote Flush AssembliesApril 28, 2006
PEM® concealed-head self-clinching studs and standoffs can be permanently mounted in steel or aluminum sheets as thin as .062"/1.6mm to provide strong and reliable threads for attachment applications. These fasteners further promote flush assemblies due to their concealed-head capability, which allows the side of the sheet opposite installation to remain smooth and unaffected by the fastening... Read More
Self-Clinching Flush-Head Studs suit stainless assemblies.April 18, 2006
PEM® Type FHP(TM) studs fit attachment applications where requirements for corrosion resistance and thinner, lighter designs must be satisfied. Formed from stainless steel for use in sheet hardness of 92 or less on Rockwell B scale, products mount flush and permanently in stainless sheets as thin as .040 in. and greater; one mating nut is required for final component attachment. RoHS-compliant studs come in 10 lengths and are available in thread sizes No. 4-40 through 10-32 and M3-M5. Read More
Flush-Head Studs mate quickly with plastic nuts and clips.November 23, 2005
PEM® self-clinching flush-head studs feature X-Press(TM) threads to enable mating of plastic nuts and clips without tools. Used to promote secure attachment, products also facilitate removal and re-installation of mating hardware. RoHS-compliant Type FHX steel studs mount flush and permanently in steel or aluminum sheets as thin as .040 in. Thread design, available in 5 x 1.6 sizes and lengths from .394-.689 in., accepts paint, coatings, and under-sealants without affecting performance. Read More
Adjustable Port Stud facilitates field assembly.September 30, 2004
With no exposed threads, Robust Port Stud(TM) eliminates potential for damage to backup washer and O-ring which could lead to leaks. It features locknut that covers threads and provides gripping area for tightening locknut. Interchangeable with current SAE adjustable connectors, port stud features 3-step assembly of thread, align, and tighten, and requires no retrofitting of parts. Read More


text:
Colin Kaepernick is headed to the Super Bowl in just the 10th start of his career. Where does he rank among NFL QBs?
Agree with someone's comment? Vote for it to make the Debate Highlights section. Disagree with a comment? Reply and voice your opinion. Happy Debating!Add Comment
Top 5 easily. He's already outplayed Aaron Rodgers, drew Brees, Matt Ryan, and Tom Brady.Full Comment »
For us Niners fans he ranks Number One. Anywhere else in the league he would most likely rank solidly between the middle to top ten. As far Kaep's p...Full Comment »
Kaepernick has led the 49ers to the Superbowl, and hasn't even had a full seasons experience. In his short time as a starter, he's beaten Brady, Brees...Full Comment »
Remember the Bledsoe-Brady replacement? It's too soon to figure out yet. But I predict something real special in the future for this young QB. In just...Full Comment »
Before CK started a NFL game. I have said CK is the future HoF QB for the 49ers. He has all the tangible and intangible to be great (rocket arm, quic...Full Comment »
I would have to breakdown CK two if fervent ways. First, as a passing threat, he would be top 10 with arguably the strongest arm in the NFL. Second,...Full Comment »


text:
First Blessing Nativity Wood Créche Figurine by Lenox
The First Blessing Wood Créche Figurine is impressive at over 16" in height and rich in tone. This créche is the perfect stable for your Nativity collection.
- Crafted of wood
- Height: 16 1/2"
$200.00 $99.95
Other products we think you'll love.
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*Offer valid on Lenox Exclusive items only. Offer excludes all Donna Karan, Marchesa, Reed & Barton, and kate spade new york merchandise.


text:
DIY decoupage on IKEA Lack table
August 13th, 2014 | by Craftea
Materials: LACK side table We took a plain white IKEA Lack side Table, which cost the grand old total of €
August 13th, 2014 | by Craftea
Materials: LACK side table We took a plain white IKEA Lack side Table, which cost the grand old total of €
August 6th, 2014 | by Crystal Kay
Materials: Galant Tabletop, Kallax 2×2 Shelves and 6″ Capita Legs A new spin on an old hack. I've seen Expedit
April 14th, 2014 | by jozette Martinez
Materials: ALRIK swivel chair, GRUNDTAL shelf, LANSA handles, LINNMON table top, RATIONEL glass shelves, SLATTHULT wall poppies This area was a
April 3rd, 2014 | by Brooke
Materials: NORDEN sideboard You might remember my stacked LACK cutting table from a few years ago. I have once again
March 17th, 2014 | by DMCShaw
Used 2 IKEA Expedit Shelves & 2 IKEA Linnmon Table Tops Bought 2 Expedit Shelves, 6 sets of caster wheels, and
March 10th, 2014 | by Mady
Description: There are a few reasons that prompted me to make this hack; - I live in a tiny (
January 28th, 2014 | by Crystal
1. Assemble the chest as directed, but wait to tack on the back and insert drawers. Paint if desired.
September 11th, 2013 | by Jules Yap
Materials: Laiva desk, Sultan Lade slatted bed-base, saw, nail and hammer Description: My daughter has a Laiva desk but she
June 26th, 2013 | by IH guest
Materials: Acrylic paints, 3D powder, ground coat, paintbrush, sponge roller, masking tape, polisher, varnish Description: First I polished the front
June 11th, 2013 | by IH guest
Materials: 3 (2 x 2) Expedit Shelves, 7 Capita Legs, Wood Screws, Pressed Board 79 x 118 cm, Butcher Block
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On Wednesday, nearly all Colorado television stations will air "Childhelp Crystal Darkness," a documentary that helps fight back against crystal methamphetamine using many Colorado sources.
It showcases testimony from law enforcement and recovery specialists and the stories of recovering meth addicts from Loveland to Denver to Grand Junction.
The documentary will be at 6:30 p.m., and a special Spanish version of it will air at 5:30 p.m. the same day on Latino television stations.
On the evening of the broadcast, United Way 2-1-1's call center will be operating, and calls will be fielded by recovery and prevention experts who are volunteering to assist in the effort. People will be able to reach the center by dialing 211.
Volunteers from North Range Behavioral Health and the Weld County Task Force will be assisting the United Way specialists in answering calls. Calls may also be made to (970) 353-4300 or (866) 485-0211 to get connected.
Jeannine Truswell, executive director of United Way of Weld County, said the agency expects hundreds of calls that night. "The hope is that many of these will be families and individuals seeking help with meth addiction," she said in a press release.
"This is a night for families to block out everything else and watch this together. We believe it will make a difference in many, many lives. Meth is so destructive to our children, our families and our community," Truswell said in the release. "We have to come together to take a stand against this terrible drug."
The Colorado organizing committee is looking for volunteers to assist with the grassroots campaign. To participate, call Jade Thomas at (303) 413-3460.
More information can be found at www.crystaldarkness.com.


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Style events: March through April
tuesday, april 2
Toni&Guy: The hairstyling academy will hold a free educational seminar at 7:30 p.m. at the Costa Mesa academy, 3400 Bristol Street.
wednesday, april 3
Mary Katrantzou: The Greek designer will present her spring line and greet customers from 11 a.m. to 3 p.m. at Nordstrom South Coast Plaza, 3333 Bristol Street, Costa Mesa, 714-549-8300.
thursday, april 4 – sunday april 7
Saks Fifth Avenue: Men's Contemporary Week; gift card giveaway and Diesel beach towel gift at Saks Fifth Avenue South Coast Plaza, 3333 Bristol Street, 714-540-3233, ext 234.
wednesday, april 10
Prada Trunk Show: The Italian design house will showcase its spring handbag line from 11:30 a.m. to 1 p.m. at a lunch and trend presentation, then from 5 to 7 p.m. and again on Thursday, April 11, will host a cocktail reception. The event will take place at Saks Fifth Avenue, South Coast Plaza, 3333 Bristol Street, 714-540-3233, ext. 341.
tuesday, april 23
Paige Geller of Paige Denim: Paige Geller makes a personal appearance to meet and greet customers. She will showcase her Spring 2013 Collection. The event is from 5 to 6:30 p.m. at Bloomingdale's-Fashion Island, 701 Newport Center Drive, Newport Beach. 949-729-6816.
saturday, april 27
Kate Albrecht, aka Mr. Kate: Style blogger Kate Albrecht will host a prom styling event that includes DIY vintage hairstyling and accessorizing tips. Albrecht will be in the store from 2 p.m. to 4 p.m. at Macy's South Coast Plaza, 3333 Bristol Street, 714-556-0611.
sunday, april 28
Sail in Style with Bruno Serato: Help motel families sail out of motel living and into permanent housing. A fashion show follows dinner. The champagne reception is at 5:30 p.m. and dinner is at 6:30 p.m. at the Anaheim White House, 887 S. Anaheim Blvd. For information and tickets: 714-772-1381.
saturday, may 11 – monday, may 13
Stuart Weitzman: The shoe maker will showcase its Fall 2013 line and celebrate the 20th anniversary of its 5050 flat boot at its South Coast Plaza store, 3333 Bristol Street, Costa Mesa. Call store for times, 714-432-8100
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Thai Hot & Sour Soup
Total Time
Prep 20 mins
Cook 30 mins
I don't know where I got this recipe originally, the card is all splattered and dirty. I wanted to post it here before I lose it.
Ingredients Nutrition
- 8 cups chicken stock
- 3 stalks lemongrass, cut in 1 inch lengths
- 4 kaffir lime leaves
- 1 teaspoon lime zest
- 2 green serrano chilies, slivered
- 2 lbs chicken (or mixture) or 2 lbs shrimp (or mixture) or 2 lbs tofu (or mixture)
- 1 tablespoon thick coconut milk
- 2 limes, juice of
- 1 red serrano chilie, slivered
- 2 tablespoons cilantro, chopped
- 3 green onions, chopped
- Heat the chicken stock in a large pot with the lemongrass, lime leaves, lime zest and green chiles. Bring to a boil, then cover, reduce the heat and simmer for 20 minutes.
- Add the meat and/or tofu to the stock and simmer until the meat is done.
- Turn off the heat and add the coconut milk and lime juice. Stir to blend.
- Pour soup into a tureen or ladle into bowls and sprinkle with red chili, cilantro and green onions.
- Adjust individual servings to taste with additional chili, cilantro, green onions, soy sauce. fish sauce or lime juice.
Most Helpful
Made this dish for my family (with 2 under 5). Everyone loved it, but I did make a couple changes. First I added about 1/4 c of coconut milk because we like it and I wanted to add more thickness to the broth. I also added rice noodles to give it more substance, esp for my kids. I can't see making it w/o either next time. The only other thing I'd change for next time is leaving the lemongrass longer to make it easier to remove before eating. It was a bit of a pain to remove them individually from our bowls. I'm passing this recipe on to my dad who has Celiac disease as this is a perfect gluten free meal. Definitely make this again!!
YUMMY! I will make this again. I love the the flavors and textures. This soup made every taste bud in my mouth very happy. Thank you! [made and reviewed for NZ/AUS recipe swap #31, August 2009].
We enjoyed this soup very much Sheynath. I used Collasal shrimp and added fish sauce and a little sugar. (personal preference only). The lemon grass that I used was minced. The spice and tartness in the soup were perfect. I did garnish the soup with shredded thai basil instead of cilantro. My serrano chilie was dried...but worked perfectly in this dish. Thanks so much for sharing. I will make this again.


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The North Texas Regional Advisory Council recently moved into a new office space. Our new address is 2910 Kemp Blvd. Suite 202 Wichita Falls, TX 76308. Give the NTRAC Office a call at (940) 234-0981 if you are in the area and want to stop by.
United Regional Offers Alternate Backboard Washer During ConstructionMay 6, 2016 Due to the heavy construction at United Regional's ED the backboard washer will be temporarily offline. Please see the link under quick docs on the home page for a detailed map illustrating the alternate washing area. >read full article


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Promoted from Diaries - Moe Lane.
Great stuff (you can get to the video on her Facebook page). I don't think I've seen this better said.
Naturally, the Left has started targeting Palin (and targeting is the right word) for her use of the phrase "blood libel", although the phrase is quite appropriate.
Politico was the first to mention it, using the phrase in their headline. The Hill was next. In their piece, they quote Rep. James Clyburn (D-SC), who naturally, decides to go into the gutter [emphasis mine]:
"You know, Sarah Palin just can't seem to get it, on any front. I think she's an attractive person, she is articulate. But I think intellectually, she seems not to be able to understand what's going on here."
It's quite obvious Palin, intellectually, gets it. I'm sure that Clyburn, intellectually, gets it. But Clyburn is so hung up on exploiting this tragedy for his and his party's political advantage that he is compelled and reduced to fling insults at Palin.
This will be added to the Left's "narrative", as was done by Taegan Goddard, just wait and see.
President Obama is set to speak later today in Tuscon. I hope he summons up enough good sense to leave the politics completely out of his speech. Unlike Palin, nobody has accused him of being even partly responsible for the recent tragedy.