text:
|Publication number
|Publication type
|Application number
|Publication date
|Jun 11, 1991
|Filing date
|Aug 9, 1989
|Priority date
|May 27, 1987
|Fee status
|Publication number
|Daniel M. Kinzer
|Original Assignee
|International Rectifier Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (13), Non-Patent Citations (2), Referenced by (57), Classifications (24), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
This is a division of application Ser. No. 07/054,627, filed May 27, 1987, now U.S. Pat. No. 4,866,495 issued 9-12-29.
This invention relates to power MOSFETs, and more specifically relates to a novel structure for a power integrated circuit wherein both the drain and source regions can be placed at high voltage relative to the chip substrate to enable its use as a high-side switch.
Power integrated circuits are known in which a power MOSFET and signal processing circuit for controlling the power MOSFET are integrated into the same chip. Such power integrated circuits are used in low-side switching applications. By "low-side switching" is meant an application in which the MOSFET source is held to about the same potential as the chip substrate while the drain can be at relatively high potential relative to the substrate, typically 100 volts or more. The integrated control circuit typically may be a CMOS-type circuit operated at low voltage, for example 15 volts or less relative to the substrate. This control circuit is easily integrated into the substrate which is at ground potential.
There are many applications for power semiconductor switching devices which put the semiconductor device on the high-side. In those circuit applications, the semiconductor switch is connected between the high voltage input potential and the load. Consequently, both the source and drain electrodes of the power MOSFET component will be placed at high or line potential. In applications where the line potential is above 200 volts, it has been impossible to integrate a grounded control circuit into the same substrate since the substrate can be only 100 volts or less from the source. If the source is greater than about 100 volts higher than the substrate, avalanche, punch through breakdown, or pinch-off would occur when the MOSFET device is turned on. The integrated circuit components, however, are conventionally low voltage MOSFET parts which must be near ground potential to communicate with the rest of the circuit which is off the chip. Consequently, discrete power MOSFETs with separate, off the chip controls are used in high-side switching applications.
In accordance with the present invention, a novel lateral conduction power MOSFET is provided for high-side switching application, employing two surface field reduction layers atop one another of respective controlled charge densities to insure field stress reduction at the surface of the chip when the device is off, and to insure high voltage isolation of the source region from the substrate of the chip when the device is on while still having sufficient undepleted charge to permit load current conduction. A low voltage circuit can be integrated into the substrate, and is arranged to shift its potential level with the shift in source voltage from low voltage in the device off condition to high voltage in the device on condition.
More specifically, in accordance with the invention, a first surface field reduction region is formed atop a substrate. The charge contained in the first region (charge density) is from 1.5×1012 to 2.0×1012 ions/cm2 . A drain region of the same conductivity type and a laterally spaced body region (sometimes called a base or channel region) of opposite conductivity type are formed in the first surface field reduction region. A source region is formed in the channel region to define a channel which can be inverted by a gate electrode spaced above the channel.
A second surface field reduction region of the opposite conductivity type to the first is then formed, as by implantation and drive, in the surface of the first field reduction region and is disposed laterally between the body and drain regions. The second surface field reduction region has a charge density of about 1×1012 ions/cm2.
This novel structure permits the use of the chip for high-side switching for two reasons. First, the body region and source region can be placed at about line potential, for example, up to 600 volts, relative to the grounded substrate. Second, the body and source can be close to the substrate potential and still withstand 600 volts relative to the drain region. The reason for this is the following: The first surface field reduction region, disposed vertically between the second field reduction region and substrate, has a charge density (for example, 2×1012 ions/cm2) to cause it to fully deplete prior to avalanche because it is depleted from its top by the second region, and from the bottom by the substrate. The upper second surface field reduction region is tied to a potential close to that of the body region. That is, the body to drain junction, when depleted, punches through to the second surface field reduction region to fix its potential close to that of the body region. However, when both the body and drain regions are at high voltage relative to the substrate (the device is turned on), the first surface field reduction region depletes only from one side. The charge density of 2×1012 ions/cm2 is high enough in this case to prevent full depletion and prevents punch through breakdown from the body region to the substrate as well as providing sufficient undepleted charge to form a low resistance conduction path from source to drain through the first lateral surface field reduction region.
The use of a surface field reduction region is known and is described in a paper entitled "High Voltage, High Current Lateral Devices" by H. M. V. Vaes and J. A. Appels, IEDM 1980, pp. 87-90.
The reference however does not disclose the application of the surface field reduction theories to high-side power MOSFETs.
An integrated control circuit such as a 15 volt CMOS-type circuit is integrated into the same chip substrate to control the gate of the power MOSFET device. The CMOS control circuit can include one or more sections integrated into one or more regions of the substrate which are appropriately isolated from the main power structure. An appropriate level shift circuit is employed to shift gate voltage level with the source electrode voltage.
In a first embodiment of the invention, current flows in a path extending laterally through an inversion channel, then vertically downward and laterally, in the same direction, under the second reduced surface field region toward the drain region.
In a second embodiment of the invention, the current path from the source is a reentrant path, having a first lateral component in one direction, a vertical component and then a lateral path extending in an opposite direction under the body and toward the drain region. This later embodiment increases ruggedness since avalanche current does not flow under the source region so that the parasitic NPN region does not become active.
The same basic silicon structure can also be used to form a high-side or low-side high voltage P-channel device, a high-side or low-side P channel insulated gate bipolar transistor and a low-side N-channel insulated gate bipolar transistor. In a still further embodiment, the invention permits the implementation of a monolithic high voltage bridge circuit consisting of the combination of a PMOS insulated gate bipolar transistor and an NMOS insulated gate bipolar transistor.
FIG. 1 is a circuit diagram of a prior art low-side switch.
FIG. 2 is a circuit diagram of a prior art high-side switch.
FIG. 3 is a circuit diagram of a prior art bridge driver with the control components shown in block diagram form.
FIG. 4 is a circuit diagram of a well-known prior art buck converter circuit with its control components shown in block diagram form.
FIG. 5 is a top plan view greatly enlarged and in schematic form of a chip which employs the novel invention with the drain and source electrodes shown in interdigitated form.
FIG. 6 is a cross-sectional view of a portion of FIG. 5 taken across section line 6--6 in FIG. 5.
FIGS. 7-12 show a semiconductor wafer in exaggerated dimensional form for clarity to illustrate the steps of manufacture of the device shown in FIGS. 5 and 6.
FIG. 13 is similar to FIG. 6, but shows a second embodiment of the invention.
As stated previously, the present invention makes it possible to integrate low voltage control circuitry into the same chip which contains a power MOSFET section in which both source and drain regions may swing to high potential. To illustrate applications in which this can occur and to better define the terms "low-side switching" and "high-side switching", examples of the two are shown in FIGS. 1 and 2, respectively.
In the low-side switch of FIG. 1, a load 20 is connected between a source of voltage V+ and a power MOSFET 21. The power MOSFET 21 contains a conventional drain electrode, source electrode and gate electrode identified by the letters D, S and G, respectively. The power MOSFET 21 may be an N channel enhancement-type device. The drain is connected to the load 20 and the source is connected to low potential or ground. In order to apply power to the load, the power MOSFET 21 is turned on by applying a suitable potential, for example 10 volts above ground to the gate electrode. The device then conducts and the potential of the drain drops from about the voltage V+ to a relatively small voltage above the source voltage. Thus, in the low-side switch of FIG. 1, the source electrode remains at about ground potential and only the drain electrode rises to high voltage.
The source electrode in the power MOSFET 21 is connected to the chip substrate. Therefore, it is possible, if desired, to integrate a low voltage control circuit into the same substrate, and isolate it from the power section. Such power integrated circuits are known. Such devices, however, cannot be used in high-side switch applications such as that of FIG. 2. In FIG. 2, the high-side switch circuit is shown in connection with the load 20 and same power MOSFET 21 of FIG. 1. When a voltage is applied to the gate electrode, which is about 10 volts higher than the voltage of the source, the MOSFET turns on. When it turns on, the source voltage rises to a value close to that of the voltage V+. Thus, in the arrangement of FIG. 2, both the drain and source electrodes are at high potential. Since the source is customarily connected to the substrate, the substrate will swing to high potential. Consequently, low voltage control circuitry cannot be integrated into the same substrate which carries the power MOSFET 21 since it cannot be easily insulated from off-the-chip input circuits.
As will be seen, the present invention provides a novel power section for a power integrated circuit in which both drain and source regions are isolated from the substrate so that the substrate can be at low potential, even though both drain and source regions are driven to high potential in a high-side switch application Since the substrate is at low potential, low voltage control circuitry can easily be integrated into the same substrate.
FIG. 3 shows a typical application which employs both a high-side switch and a low-side switch for a half-bridge power output, which is well known to those skilled in the art. Thus, FIG. 3 shows two power MOSFETs 22 and 23, each identical to power MOSFETs 21 of FIGS. 1 and 2, but connected in series to form one-half of a full wave bridge. A first drive circuit 24, termed a high-side drive, is connected to the gate electrode of MOSFET 22 while a second drive circuit 25, termed a low-side drive, is connected to the gate electrode of power MOSFET 23. A level shift circuit 26 is connected to the high-side circuit 24 to shift the gate drive from the ground referenced input level to a floating source-referenced level. This level shift was conventionally done using discrete high voltage components or an isolation transformer.
The output voltage to the gate of high-side MOSFET 22 is from 505 to 515 volts for an application in which V+ is, for example, about 500 volts. A bootstrap capacitor 27 is employed to provide a voltage to drive the gate which is at a voltage higher than that of the source of device 22. A diode 27a charges the bootstrap capacitor 27 to the low voltage supply level when the source of MOSFET 22 swings to ground. When the source swings high, the capacitor 27 then swings with it. The output voltage of the low-side drive circuit 25 should be in the range of 5 to 15 volts in order to control the low-side MOSFET 23. It is possible to integrate the low-side drive circuit 25 into the chip substrate containing the power MOSFET section 23 since the substrate and the source region are at ground voltage. However, the source and substrate of the high-side MOSFET 22 will rise to approximately the 500 volts of the voltage source V+ so that low voltage drive circuitry cannot be integrated into that substrate. As a result, bridge drivers such as that of FIG. 3 are commonly made in hybrid fashion with discrete power MOSFETs for the MOSFETs 22 and 23 and separate circuits 24 and 25 for their control.
FIG. 4 is another example of a high-side power MOSFET application. Thus, FIG. 4 shows a buck converter of well-known configuration in which a power MOSFET 21 is connected in the high-side fashion of FIG. 2 between a voltage source V+, which may be 500 volts, and the load 20. In the buck converter circuit, there is also provided a diode 30 and a filter consisting of the choke 31 and capacitor 32. A low voltage drive circuit 33 is coupled to the gate of MOSFET 21 to control the conduction of the power MOSFET 21 as will be described. The control circuit may be a CMOS-type circuit operated, for example, at 15 volts. It may include functions of temperature protection, self-start, duty cycle control, under voltage protection and any other function desired for the control circuit of a typical converter. All of these can be integrated into the low voltage control 33.
The output of the brick converter may, for example, be 15 volts ±5% and the current output may be up to about 1 ampere. These converters are operated in such a manner that the power MOSFET 21 is turned on and off with a given duty cycle so that, when it conducts, current flows to the load 20 through the choke 31 for a given period, which is adjustable, from the output of the device to maintain a constant output voltage. At the end of the period, the power MOSFET 21 is turned off but current will continue to flow through choke 31 and through the diode 30, which is a freewheeling diode. The magnitude of the output voltage connected to the load 20 is a function of the duty cycle. By way of example, if the input voltage is 300 volts and the output voltage is 15 volts, the duty cycle should be set at about 5%. Such circuits operate with an efficiency of from 60-70%.
In the past, it has been impossible with conventional power MOSFETs to integrate the CMOS control circuitry 33 of FIG. 4 into the substrate of the power MOSFET 21. This is because the substrate is at the potential of the source and in the circuit of FIG. 4, both drain and source rise to approximately the full voltage V+ of the input circuit.
As hereinafter described, the novel invention provides a power MOSFET section in which both source and drain regions are isolated from the substrate of the chip so that the substrate can be at ground potential relative to both drain and source regions in high voltage applications (those in which the line voltage is greater than about 200 volts). Consequently, the control circuit 33, which is a low voltage control circuit, can be integrated into the same substrate to make a novel power integrated circuit for high-side switching.
One embodiment of the novel device of the invention is shown in FIGS. 5 and 6. FIG. 5 schematically illustrates one geometry which a power integrated chip 40 can assume More specifically, the arrangement of FIG. 5 shows the power integrated circuit as employing an interdigitated geometry for the drain electrode 41 and source electrode 42. These are illustrated in schematic fashion and it will be understood that a large number of interdigitated fingers may be used, for example 20. Other geometries can be employed to carry out the present invention, as will become apparent from the description of FIG. 6.
Any desired integrated control circuit can be integrated into the chip 40 This low voltage integrated control circuit is schematically illustrated as the circuit 43 in FIG. 5 which is electrically insulated from the other circuits and from the power device source and drain Also shown in schematic form is a high voltage level shift and drive circuit 44 for the power FET gate, which must swing above the line voltage to maintain conduction in the power device. Since the chip or substrate 40 is always connected to the lowest, or ground potential, it remains possible to integrate low voltage control circuitry into the substrate 44.
FIG. 6 illustrates the novel junction patterns which are employed in the chip of FIG. 5 shown for the three fingers which are viewed from the section line 6--6 in FIG. 5.
Referring now to FIG. 6, the main chip substrate is the P(-) substrate 40. The P(-) substrate 40 has an epitaxial N(-) layer 48 deposited thereon which receives the various junctions of the novel lateral conduction power MOSFET. Layer 48 is the first reduced surface field region of the invention, referred to above, and has a charge density of from 1.5×1012 to 2×1012 ions/cm2, preferably 2.0×1012 ions/cm2.
In the section shown in FIG. 6, there are shown deep P(+) isolation regions to isolate the power section illustrated in FIG. 6 from integrated control sections formed on the same chip and within the same epitaxially deposited region 48 as receives the power section.
A body region 53 is formed in the layer 48 having the characteristic deepened P(+) central body portion which improves blocking voltage and prevents turn-on of parasitic bipolar transistors. Body region 53 is sometimes termed a base region, due to the parasitic NPN transistor inherent in the structure. The P(+) body region extends bilaterally to lower conductivity P(-) regions 54 and 55. A pair of N(+) source strip regions 56 and 57 are formed in the body region 53, which are self-aligned to the shallow P(-) shelf regions of P(+) base region 53. The space between the outer edges of source regions 51 and 59 and the outer edges of regions 54 and 55 define surface channels which can be inverted by an appropriate gate structure.
A source electrode 42 is connected at the surface of the chip to source regions 56 and 57 and the center of the channel region 53. Surface channels 54 and 55 have overlying gate oxide layers 61 and 62, respectively, and conductive polysilicon electrodes 63 and 64 lying atop the gate oxide regions 61 and 62. Silox (phosphorous doped silicon dioxide) layer 65-66 overlies the gate oxides 61 and 62 and the field oxides extending therefrom to complete the source and channel structure.
Two drain electrodes 41 are symmetrically laterally spaced from the central source 42. Each of drains 41 are electrically connected to N(+) diffusions or drain regions 70 in the layer 48.
In accordance with an important feature of the invention, two P(-) reduced surface field regions 71 are formed in first reduced surface field region 48 between the channels 54 and 55 and respective ones of drain strips 70. Regions 71 each have a charge density preferably of 1×1012 ions/cm2. The lateral space between regions 53 and 71 must be small, preferably less than 10 microns, and well controlled. Too small a space pinches off the available conduction space. Too large a space produces premature avalanche. The space may vary between 2 to 8 microns and is preferably 5 microns.
The structure of the chip of FIG. 6 is completed by P(-) regions 80 and 81 which extend from the junction isolations 50 and 51. Substrate electrodes 82 and 83 are connected to the P(+) diffusions 50 and 51 and are at the same potential as the substrate electrode 84 on the bottom of the chip 40. P(-) regions 80 and 81 insure proper lateral distribution of the electric field from the drain regions 70 to the grounded electrodes 82 and 83. Field oxide 90 overlies regions 80 and 81, and silox strips 91, 92, 93 and 94 (which are segments of a common strip) are applied as shown.
The structure of the novel power section of FIG. 6 enables the integration of low voltage control, high voltage level shift, and gate drive circuits into the same substrate which contains the power section. The control components are integrated into the low voltage substrate 48 at some region isolated from the power section as shown in FIG. 5. Consequently, the novel power integrated chip of FIGS. 5 and 6 can be employed in a high-side switching application. Obviously, the same technology could be used for general power MOSFET application, but its uniqueness lies in its ability to perform high-side switching, since both source and drain regions can be operated at high voltage relative to the substrate 40.
The device of FIGS. 5 and 6 is an N channel enhancement type of device having both vertical and lateral components for the current conducting path. In operation, when the device is to be turned on, a suitable voltage, for example from 0-10 volts, is applied to the polysilicon gate electrodes 63 and 64. This inverts the surface channels 54 and 55 and enables a current conduction path from drain regions 70 under the P(-) regions 71 and then vertically up through the region between the body region 53 and the adjacent sides of the regions 71 and through the surface channels 54 and 55 to the source regions 56 and 57 and to the source electrode 42.
In a high-side switch application, drain electrode 70 may be connected directly to a voltage source which is at about 500 volts in a circuit typically of the type shown in FIG. 4. The source 42 may be connected directly to a load. When the power MOSFET section turns on, the source will swing to approximately the 500 volts of the drain minus the voltage drop in the drain-to-source current path through the substrate 48. The control circuit for turning the device on can be a 15 volt CMOS circuit such as that of circuit 43 in FIG. 5, integrated directly into a junction-isolated region of epitaxial layer 48 which is only 15 volts above ground potential. The output of this circuit must then be translated across the 500 volts by means of a level shifter to raise the gate above the drain potential.
The manner in which the reduced surface regions 48 and 71 cooperate to enable the use of the device for high-side switching application is as follows:
Assume first that the device is "on". In that case, the drain regions are at line voltage, for example, 500 volts, and the source regions 56 and 57 are at 500 volts minus the voltage drop produced by the resistance between drain and source. A depletion region then spreads from the P(-) substrate 40 only. As is well known, the charge which will be depleted on each side of any junction in silicon when the critical field is reached is approximately 1×1012 ions/cm2. At 500 volts, the depletion region does not reach the bottom of body region 53 and an undepleted layer having a charge concentration of 1×1012 ions/cm2 remains between the depletion region extending from P(-) substrate 40 and the bottoms of regions 53 and 71 to define lateral conduction paths to drains 70 beneath regions 71. No punch through occurs from body region 53 to P(-) substrate 40 since the depletion region does not reach the region 53. Thus, the source can be at high voltage relative to the substrate when the device is on. Note that the structure in the on condition resembles a lateral JFET consisting of P(-) region 40, N(-) region 48 and P(-) regions 71, pinched only from the bottom P(-) region 40.
Consider next the device of FIG. 6 with the gate voltage removed and the device in the "off" state. Sources 56 and 57 and the substrate are at about ground potential while the drain regions 70 are at line potential, which may be 500 volts. The first reduced surface field region 48 is now depleted from both sides; from the P(-) substrate 48, and the P(-) regions 71. Thus region 48 fully depletes 1×1012 ions/cm2 from both sides, for a total of 2×1012 ions/cm2. Similarly, P(-) regions 71 are fully depleted, causing field reduction at the surface of the device and close to avalanche conditions at the junction between P(-) substrate 40 and layer 48.
More specifically, the N(-) region 48 depletes from P(+) region 53 toward the P(-) regions 71. At a fairly low voltage, the depletion reaches regions 71, thus setting their potential near that of region 53. With this accomplished, depletion begins at the junction between regions 71 and 48, while also occurring at the junction between the region 48 and substrate 40. The total dose in regions 71 and 48 is tailored so that both are fully depleted just before the critical field is reached at the junction between P(-) substrate 40 and N(-) epi layer 48. Therefore, surface fields are reduced near blocking junctions so that critical field is reached in the silicon bulk before it is reached at the surface.
The P(-) regions 71 and 48 permit the use of lower resistivity epitaxial material while retaining a high blocking voltage. Thus, for a given device, on resistance is lower.
FIGS. 7-12 illustrate a process by which the novel device of FIG. 6 can be made. As was the case in FIG. 6, all dimensions are greatly distorted in order to better illustrate the novel features of the invention.
FIG. 7 shows the starting wafer for the device as a P(-) substrate which can, for example, be 25 mils thick and have a 25 ohm centimeter resistivity. A plurality of chips are conventionally made at one time, for example in a 5 inch diameter wafer. A phosphorus doped N(-) epitaxial layer 48 which has a thickness of 20 microns and a resistivity of 2.6 ohm centimeters is formed on the substrate 40 by appropriate epitaxial techniques.
The wafer of FIG. 7 is first suitably cleaned and is oxidized with a silicon oxide coating of about 5,000 Angstroms in thickness. The oxide coating is then masked and etched to form windows which enable the formation of the P(+) isolation regions 50 and 51 shown in FIG. 8. Isolation rings 50 and 51 have a depth of about 25 microns and may be formed with a boron diffusion for about 16 hours at 1,200° C. and until the surface resistivity is about 10 ohms per square.
Thereafter, and as shown in FIG. 9, a second mask and etch step is carried out to produce the reduced surface field implant of regions 71, 80 and 81. This is carried out with a boron implant with a total dose of about 5×1012 followed by a drive for about 5 hours at 1,200° C. At the end of the drive, the sheet resistivity should be about 10,000 ohms per square and the depth of the P(-) regions 71 should be about 5 microns.
Thereafter, a field oxide 110 is grown to a thickness of about 1.1 microns. Some of the boron implant will be lost into this oxide. Whatever process is used for the formation of the resurf region 71, in the preferred embodiment of the invention, the final charge in these regions should be about 1×1012 ions/cm2. Oxide 110 is then masked and etched and a boron implant is carried out to form the P(+) region 52 which will become the deepened part of the body 53 of FIG. 6. The boron implant used in this step has a dose of 3×1014 followed by a boron drive for two hours at about 1,050° C.
Thereafter, a fourth masking step is carried out in which oxide is removed from the active areas. That is, oxide is removed from the areas between P(-) regions 80 and 70 on one side and 70 and 81 on the other side and the area between the facing edges of resurf regions 70. Thereafter, a gate oxidation step takes place growing a gate oxide of 800 Angstroms in thickness, followed by the deposition of polysilicon.
A polysilicon etch and oxide etch are carried out in a fifth masking step to form the structure shown in FIG. 11. Thus, in FIG. 11, there is shown gate oxide segments 61 and 62, polysilicon gates 63 and 64, and the field oxide strips 111 through 114, which are segments of a common oxide sheet which has been etched.
In a sixth masking step, a photoresist implant mask is formed to enable the forming of a body region to define the channel regions 54 and 55. Thus, a boron implant having a dose of 7×1013 with a diffusion drive for about 60 minutes at 1,175° C. is used. The wafer is then oxidized to add about 1,800 Angstroms to the oxide coating.
The N(+) source regions 56 and 57 are then formed by a mask and etch step followed by an arsenic implant having a dose of 5×1015 followed by a drive for two hours at 975° C. to form the N(+) channels 56 and 57 shown in FIG. 12.
Thereafter, an appropriate interlayer dielectric is applied to the device of FIG. 12 resulting in the structure shown in FIG. 6. Thereafter, a contact mask etch step is carried out to expose the contact regions and one micron of aluminum is deposited over the etched pattern.
A ninth mask step is carried out to perform the necessary aluminum etch to define the contact pads followed again by a silox scratch protection deposition. A final and tenth mask is employed to carry out a silox etch.
FIG. 13 shows a cross-sectional view of the junction pattern of a second embodiment of the invention. The device of FIG. 13 is carried out with a topology similar to that shown in FIG. 5 and is a cross-sectional view similar to that of FIG. 6.
The device of FIG. 13 differs from that of FIG. 6 in having a modified lateral current path to the drains which, as will be later described, avoids flow of avalanche current beneath the N(+) sources so that the parasitic NPN bipolar transistor does not become active. This enhances the ruggedness of the device. Another advantage of the structure of FIG. 13 over that of FIG. 6 is that the gate oxide does not extend over the drain drift region and step up onto a field oxide.
In the following description of FIG. 13, those components which are essentially identical to those described in FIG. 6 have been given the same identifying numerals. Moreover, the novel use of two reduced surface field regions 48 and 71 of differing charge concentrations is retained to obtain the benefits described previously which permit the use of the device in high-side switching applications.
The body region 53 of FIG. 6 is carried out in the embodiment of FIG. 13 as two separate spaced channel regions 200 and 201, respectively. Each has a deepened P(+) region and a shallower P(-) region in which the inversion channel is defined by the source regions 56 and 57, respectively. In view of this revision, it is now possible to employ a flat simple gate oxide layer 202 beneath the polysilicon gate 203. Thus, the processing of the device is simpler than that of the device of FIG. 6.
The configuration of the gate in FIG. 13 helps reduce drift of the device characteristics, particularly avalanche value and device stability, over time. Thus, in the embodiment of FIG. 6, there is a high field which can cause trapped charges in the gate region which changes the field distribution within the silicon and consequently changes avalanche voltage. This condition is substantially negated in the embodiment of FIG. 13 by reducing the high fields at the gate oxide.
A major advantage is obtained in FIG. 13 by the separation of the body regions into two separate regions 200 and 201. This structure modifies the current path from the inversion channels in the P(-) regions to the left hand and right hand drains 70 respectively. These current paths are shown by the arrows 210 and 211 respectively which show current paths with re-entrant bends. With this type structure, avalanche current, which will flow in the regions marked X and Y respectively, does not flow beneath the N(+) source regions 56 and 57. Consequently, the parasitic NPN bipolar transistors consisting of source 56, the P(-) region of base 200, and the region 48; and source 57, the P(-) region of base 201 and region 48; do not turn on or become active. Consequently, the device has increased ruggedness as compared to that of FIG. 6.
The reduced field regions 71 of FIG. 6 are are also in the device of FIG. 13 and carry the same identifying numeral, although in the embodiment of FIG. 13 regions 71 contact on about the P(+) channel regions 200 and 201 respectively. Their functions, however, are identical to those described in connection with FIG. 6.
In the manufacture of the embodiment of FIG. 13, the P(-) substrate 40 was monocrystalline silicon having the resistivity of 25 ohms/cm for a device which was to have a 550-600 volt breakdown. The N(-) region 48 was a 2.5 ohms/cm material having a thickness of about 20 microns. P(-) regions 71, 80 and 81 each had a depth of about 3 microns. The P(+) regions 200 and 201 had a depth of 4 microns at their deepest point and about 3 microns at their shallower shelf region. The spacing between adjacent channel regions 200 and 201 is preferably about 5 microns. The width of each of regions 200 and 201 is about 8 microns, and the width of each of P(-) regions 71, 80 and 81 was about 50 microns. Each of drain regions 70 has a depth of about 0.8 microns and a width of from 5-15 microns. The drain regions 70 are spaced from their adjacent P(-) regions 71 by a gap of about 214 3 microns. When forming the regions 71, an ion implant dose of about 5×1012 is employed. This dose is reduced down to about 1×1012 by later steps in which oxides are grown and due to compensating N-type charge. The P(-) regions of channel regions 200 and 201 are formed by an ion implant using a dose of about 7×1013. The gate oxide 202 has a thickness of about 800 angstroms.
Another advantage of the embodiment of FIG. 13 is that the space between channel regions 200 and 201, which is about 5 microns becomes fully depleted when the device is in its blocking condition. Therefore, no high electric field stress will appear in the region near the edge of the polysilicon gate 203. Consequently, no avalanche will occur in that very critical region.
Although the present invention has been described in connection with a plurality of preferred embodiments thereof, many other variations and modifications will now become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
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|High-side switch with overcurrent protecting circuit
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|Mar 15, 1994
|Motorola, Inc.
|High voltage transistor having reduced on-resistance
|Jul 7, 1992
|Mar 22, 1994
|Matsushita Electric Works, Ltd.
|Low output capacitance, double-diffused field effect transistor
|Mar 19, 1992
|May 10, 1994
|Nec Corporation
|Field effect transistor with offset region
|Jul 30, 1991
|Jun 14, 1994
|Microwave Technology, Inc.
|High frequency JFET
|Oct 25, 1993
|May 2, 1995
|Power Integrations, Inc.
|Method of making high voltage transistor
|Oct 7, 1994
|Jul 11, 1995
|Fuji Electric Co., Ltd.
|High withstand voltage M I S field effect transistor and semiconductor integrated circuit
|Jun 1, 1995
|Apr 22, 1997
|Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno
|Method for making monolithic integrated bridge transistor circuit
|Dec 28, 1994
|May 6, 1997
|Unitrode Corporation
|DC/DC converter having a bootstrapped high side driver
|Feb 28, 1996
|Jul 8, 1997
|United Microelectronics Corporation
|Surface breakdown reduction by counter-doped island in power mosfet
|Nov 20, 1996
|Mar 17, 1998
|Lucent Technologies Inc.
|Method of making a P-channel bipolar transistor
|Nov 15, 1995
|Sep 29, 1998
|General Electric Company
|Self-aligned transistor device including a patterned refracting dielectric layer
|Feb 1, 2001
|Apr 30, 2002
|International Rectifier Corp.
|Process for manufacturing radhard power integrated circuit
|Jul 24, 2000
|Jun 4, 2002
|Hewlett-Packard Company
|Energy balanced ink jet printhead
|Nov 28, 2001
|Sep 2, 2003
|Kabushiki Kaisha Toshiba
|Field effect transistor
|May 6, 2002
|Nov 11, 2003
|Hewlett-Packard Development Company, L.P.
|Energy balanced ink jet printhead
|Jan 6, 2003
|Mar 16, 2004
|International Rectifier Corporation
|Integrated series schottky and FET to allow negative drain voltage
|Jun 7, 2001
|Nov 23, 2004
|Texas Instruments Incorporated
|Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness
|Sep 5, 2001
|Dec 14, 2004
|Denso Corporation
|Power MOS transistor for absorbing surge current
|Aug 16, 2002
|Aug 16, 2005
|Fairchild Semiconductor Corporation
|Method and circuit for reducing losses in DC-DC converters
|Sep 18, 2003
|Sep 20, 2005
|Shindengen Electric Manufacturing Co., Ltd.
|Lateral short-channel DMOS, method of manufacturing the same, and semiconductor device
|Jun 3, 2004
|Feb 13, 2007
|Samsung Electronics Co., Ltd.
|High voltage MOSFET having doped buried layer
|Nov 17, 2004
|Apr 15, 2008
|Matsushita Electric Industrial Co., Ltd.
|Sustain driver, sustain control system, and plasma display
|Jan 5, 2007
|Jun 3, 2008
|Samsung Electronics Co., Ltd.
|Methods of fabricating high voltage MOSFET having doped buried layer
|Apr 28, 2005
|Jan 20, 2009
|Texas Instruments Incorporated
|System and method for driving a power field-effect transistor (FET)
|Jul 14, 2006
|Oct 20, 2009
|Cambridge Semiconductor Limited
|Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation
|Dec 27, 2007
|Feb 2, 2010
|Sharp Kabushiki Kaisah
|Output control device, and AC/DC power source device, circuit device, LED backlight circuit device, and switching DC/DC converter device each using output control device
|Oct 18, 2006
|May 18, 2010
|Infineon Technologies Ag
|Integrated circuit ESD protection
|Nov 16, 2007
|Jun 28, 2011
|Panasonic Corporation
|Sustain driver, sustain control system, and display device
|Aug 2, 2011
|Abb Schweiz Ag
|Cathode cell design
|May 22, 2012
|Fairchild Semiconductor Corporation
|Monolithic low impedance dual gate current sense MOSFET
|Apr 20, 2012
|Jan 22, 2013
|Fairchild Semiconductor Corporation
|Monolithic low impedance dual gate current sense MOSFET
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|Fairchild Semiconductor Corporation
|Shielded level shift transistor
|Jun 11, 2013
|Jun 9, 2015
|Fujitsu Semiconductor Limited
|Semiconductor device
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|Feb 9, 2016
|Fairchild Korea Semiconductor Ltd.
|Level shift power semiconductor device
|Jan 6, 2003
|Jun 5, 2003
|International Rectifier Corporation
|Integrated series schottky and FET to allow negative drain voltage
|Jun 3, 2004
|Dec 23, 2004
|Sun-Hak Lee
|High voltage MOSFET and method of fabricating the same
|Sep 18, 2003
|Mar 24, 2005
|Makoto Kitaguchi
|Lateral short-channel dmos, method of manufacturing the same, and semiconductor device
|Nov 17, 2004
|Jun 23, 2005
|Matsushita Electric Industrial Co. Ltd.
|Sustain driver, sustain control system, and plasma display
|Apr 28, 2005
|Nov 2, 2006
|Texas Instruments Incorporated
|System and method for driving a power field-effect transistor (FET)
|Feb 10, 2006
|Dec 7, 2006
|Hitachi, Ltd.
|High voltage analog switch ICS and ultrasound imaging systems using same
|Jan 5, 2007
|May 10, 2007
|Samsung Electronics Co., Ltd.
|Methods of Fabricating High Voltage MOSFET Having Doped Buried Layer
|Jul 14, 2006
|Jan 17, 2008
|Cambridge Semiconductor Limited
|Semiconductor device and method of operating a semiconductor device
|Nov 16, 2007
|Mar 20, 2008
|Matsushita Electric Industrial Co., Ltd.
|Sustain Driver, Sustain Control System, And Display Device
|Nov 2, 2007
|Apr 17, 2008
|Abb Schweiz Ag
|Cathode cell design
|Oct 18, 2006
|Apr 24, 2008
|Qiang Chen
|Integrated Circuit ESD Protection
|Dec 27, 2007
|Feb 5, 2009
|Sharp Kabushiki Kaisha
|Output control device, and AC/DC power source device, circuit device, LED backlight circuit device, and switching DC/DC converter device each using output control device
|Jun 26, 2013
|Dec 26, 2013
|Fairchild Korea Semiconductor Ltd.
|Power semiconductor device
|Jun 11, 2013
|Jan 23, 2014
|Fujitsu Semiconductor Limited
|Semiconductor device
|Jun 7, 2002
|Dec 11, 2002
|Texas Instruments Incorporated
|Additional n-type LDD/pocket implant for improving short-channel nmos ESD robustness
|Aug 16, 2002
|May 7, 2003
|Power Integrations, Inc.
|Integrated circuit with closely coupled high-voltage output and offline transistor pair.
|Apr 22, 2003
|Oct 29, 2003
|Power Integrations, Inc.
|Power integrated circuit with distributed gate driver
|Apr 22, 2003
|Mar 9, 2005
|Power Integrations, Inc.
|Power integrated circuit with distributed gate driver
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|Power Integrations, Inc.
|Integrated circuit with closely coupled high-voltage output and offline transistor pair
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|Feb 18, 1993
|Microwave Technology, Inc.
|High frequency jfet and method for fabricating the same
|Sep 18, 2003
|Mar 31, 2005
|Shindengen Electric Manufacturing Co., Ltd.
|Lateral short-channel dmos, method for manufacturing same and semiconductor device
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Dec 12, 1994
|Fee payment
Year of fee payment: 4
|Nov 18, 1998
|Fee payment
Year of fee payment: 8
|Jul 19, 1999
Owner name: BANQUE NATIONALE DE PARIS, CALIFORNIA
Free format text: SECURITY INTEREST;ASSIGNOR:INTERNATIONAL RECTIFIER CORP.;REEL/FRAME:010070/0701
Effective date: 19990711
|Nov 15, 2002
|Fee payment
Year of fee payment: 12
|Jan 31, 2006
|Certificate of correction


text:
Spacious Room Near Brick Lane (GB3)
Vendégek száma2
Hálószobák száma1
Méret13 m²
Floor No.
- Konyha
- Mosógép / szárítógép
- Reggeli
- Zárható szoba
- Internet/WiFi
- Törölköző
|Gibson Close, E1 4JT London, Egyesült Királyság
|Ingatlan típusa
|Privát szoba
|Ingatlan azonosító
|Acceptance rate
|Response time
|A few hours
|Calendar updated
The vibrant markets and famous cuisine of London's Brick Lane are just a 20-minute walk from this private room. Free Wi-Fi, basic breakfast goods and toiletries are included.
Colourfully decorated, this spacious room contains a double bed and two wardrobes. Guests are welcome to make use of the modern kitchen, which features wooden flooring and furnishings. The tiled bathroom offers a newly fitted shower, and a separate WC.
Brick Lane is a must-see for any London tourist. Its varied cultural history provides intrigue and entertainment, and guests may enjoy taking a guided historical walks within the area.
Stepney Green Underground Station is just a 5-minute walk away, and Bethnal Green Underground Station is a 10-minute walk away. Hyde Park can be reached within 15 minutes via the Central Line from Bethnal Green.
Guests should clean up after themselves.
|Érkezés legkorábbi időpontja
|Check-in before
|Távozás legkésőbbi időpontja
|Lemondási feltétel
In the room, the bathroom and the kitchen was clean and nice. However, at the entrance and the stairwell lot of garbage and unfavorable impression. The owner has not informed me that every room has a marked place in the refrigerator. The effect was that I left my food in the refrigerator (on one the shelfes) after breakfast - and when I came back in the evening my food was not there. I called the owner and asked him what happened. He said: cleaning lady usually throws food, whose owner had already left. But in the wastebasket was only a little part of my food - open packaging. But the sausage, cheese etc was not there. Sombady has took away it. The owner said that he will give me money for the food, but I don't now haw he intends to do it.
I have to say the house is quite hidden and doesn´t look to good on the outside, but the room is lovely and big enough for two people to stay comfortably. The bathroom and kitchen was very clean and I had a good night stay. The only problem is really the key at the front door, it gets stuck and you have to try for several minutes or wait for another guest to open the door. But I´d recommend it, since it´s only 20 minutes away to the city centre.
- Minőségbiztosított szállás
- Minden házigazda hitelesítésre került telefonon keresztül
- Biztonságos fizetés SSL titkosításon keresztül

subset: commoncrawl


text:
Dear Panoramio friends thank you very much for your visit, nice comments, likes and favorites
Greetings from Denmark, Jan
Love it
Dear Husain thank you very much for your visit and nice comments
Greetings, Jan
I love reflections, Esp. ones that depict the past. Carolyn in USA
A beautiful place...Love it L&F. Best regards, Rosa.
Very nice place in sunny light - like
Friendly greetings and wishes all the best in New Year 2015 from Zygmunt
Meget smukt billede. Hilsen fra byen Ruda Schlesien - Polen
Photo taken in Vesterbro, 8000 Aarhus, Denmark
Den Gamle By


text:
Celebrity Central / Top 25 Celebs
Chris Pine
See This, Skip That: From Star Trek to The English Teacher – Your Weekend Movie Plan
The English Teacher gets a less-than-perfect grade, but Star Trek and Stories We Tell are star pupils
One Last Thing: Chris Pine
Fifty Shades of Grey: Who Should Play Christian Grey?
Author E L James will be involved in the casting process – who would you pick?
Seth Rogen Doesn't Regret Kissing, Getting Punched by Chris Pine
The funnyman reveals just how close he and the Star Trek heartthrob got backstage at a charity benefit
Couples Watch: Drew & Justin, Chris Pine & Olivia Munn . . .
Chris Pine and Olivia Munn Break Up
After the pair keep their distance at a party, a source confirms to PEOPLE they've split
Couples Watch: Chris Pine & Olivia Munn Get Flirty
Plus: Alyssa Milano's romantic birthday dinner, Fergie & Josh and more
Chris Pine to Play CIA Hero Jack Ryan
The hottie will fill shoes worn by Alec Baldwin, Harrison Ford and Ben Affleck


text:
accounting jobs near Washington, PA
Refine your searchClear Filters
Date Added
More Filters
Accountant III (CPA)
MedExpress - Canonsburg, PA
Bachelor's degree in accounting, CPA a plus. Keeps records of account entries by compiling and analyzing accounting activities....
Senior Manager of Accounting (Supervision, Staff Development, Leadership)
International Financial Group - Pittsburgh, PA
Directing all administrative accounting functions for the company relating to Billing, Accounts Payable and Accounts Receivable....
ChemDAQ - Pittsburgh, PA
Reviewing General Ledger to ensure Journal Entries and accounting classifications assigned are accurate and consistent....
JP Myers & Associates CPA's - Carnegie, PA
Carnegie based CPA firm seeks an accountant/CPA with 2 to 3 year experience in public accounting. Public Accounting - at least:....
Accounts Receivable Specialist just South of Pittsburgh, PA
Accounting Principals - Carnegie, PA
¿ Cash Management and debit/credit memo creation with extensive data entry in an Oracle accounting system. ¿ Prior invoice experience....
Manager External Financial Reporting (SEC, CPA, 10-Q, 10-K, 8-K)
International Financial Group - Pittsburgh, PA
Maintaining SEC and Accounting Department filings calendar. CPA certification is required for this position. Bachelor Degree in Accounting....
Financial Analyst (Performance Analysis, Budgeting, Forecasting, Month End Close)
International Financial Group - Pittsburgh, PA
Assisting in inventory accounting and control; Reviewing and/or developing accounting controls policies and procedures to ensure compliance with GAAP and...
Accounting Assistant
Callos Resource - Pittsburgh, PA
Responsible for vendor reconciliations & vendor calls, in-bound Member calls regarding their accounts, past due/bad debt calls and help with collections....
Financial Aid Planner
Pittsburgh Technical College - Oakdale, PA
Responsibilities of position will require additional work hours seasonally. Financial or accounting background preferred....
Restaurant Manager
Crowne Plaza Hotel & Suites Pittsburgh South - Bethel Park, PA
Assists in accountability for achieving cost goals in the area of sales, labor and expenses. Assist in advising the Restaurant/Banquet Manager of daily problems...


text:
Student-Run Summer Program Will Empower 200 Israeli Youth
Summer Talmud Learning at Stern
Graduate Program in Advanced Talmud Study Presents June Zman
Building a Healthy Community
More than 1,100 Receive Free Genetic Screening at Largest Event of Its Kind Hosted by YU Students
GPATS to Host Women's Community Yom Iyun
February 28 Teaneck Yom Iyun Will Focus on Purim, Women's Learning
Students Host Innovative Genetic Screening Event
Free Feb. 14 Event Open to the Broader Community Yeshiva University's Student Medical Ethics Society (MES) will partner with JScreen, a university-based nonprofit program specializing in carrier screening for genetic diseases common in the Jewish population, to host a free genetic screening event. The event, which will make screening for more than 100 genetic diseases…
YU Presents New Semester of Community Beit Midrash Program
Two Weekly Courses Explore Jewish Holidays and Evolving Relationship of Medicine and Jewish Law Yeshiva University's Center for the Jewish Future (CJF) will present a new semester of its Community Beit Midrash Program beginning February 10 with a six-week series of talks by two faculty members, Rabbi Kenneth Brander, vice president for university and community life at YU, and…
Standing Shoulder to Shoulder with Israel
Students Will Learn About Conflict and Help Victims of Terror on Solidarity Mission to Israel
Responding to Tragedy in Israel
In Wake of Terror Attacks, Students, Faculty and Staff at Yeshiva University Show Support In the last few weeks, as Israel has been hit with another wave of terror attacks, students, faculty and staff at Yeshiva University have come together to reach out to Jews across the Atlantic and around the world. Last week, following…
After the Flood
Yeshiva University Students Mobilize Houston Flood Relief Efforts
Students, Alumni and Staff Celebrate Israel
Yeshiva University Marches in Support of Israel at Annual Parade


text:
Cozumel Ruins
Playa del Carmen
Street Map
Scuba Diving
About Dolphins
D.I.Y. Snorkel Tour
Cozumel Dive Paradise & Hotel Barracuda - Dive Package
Hotel Barracuda has 52 comfortable rooms, most with an ocean view.
Each room features A/C, two double beds, refrigerator and telephone.
On-site Dive Paradise training facility located at beachfront. Showers, rinse tanks and lockers are available for gear storage.
Diving trips depart directly from hotel pier.
4 night package totals 9 dives, 7 night package totals 15 dives!
Located on the waterfront, just 5 blocks south of the main plaza.
4 Nights
3 Dive Days / 2 Dive Afternoons
7 Nights
5 Dive Days / 4 Dive Afternoons
Jan 3 - Apr 30, 2015
May 1 - Dec 15, 2015
Package Specifics
Cozumel Dive Paradise & Hotel Barracuda - Dive Package
Cozumel Insider
Combo Promotion Packages available
January 3, 2015 to December 15, 2015
Dates 2015
Combo Promotion Packages are not available 5 days
before or 5 days after the following U.S. Legal Holidays:
CARNAVAL ~ February 17 ===> Feb 12 - Feb 22
Easter Sunday ~ April 5 ===> March 31 - April 10
Memorial Day ~ May 25 ===> May 20 - May 30
Independence Day ~ July 4 ===> June 29 July 9
Labor Day ~ September 7 ===> Sept 2 Sept 12
Thanksgiving ~ November 26 ===> Nov 21 Dec 1
December Holiday Period ===> Dec 16 Jan 2
NOTE: No Combo packages available during
December holiday period (packages begin again on Jan 3)
See Pricing Chart
$2 Per Diver Per Day Marine Park Fee Not Included
Equipment Rental Not Included
Flights/Transfers not Included
Terms and Conditions for All Above Packages Unless Otherwise Stated:
All Dive Paradise packages include a "Bienvenidos" (welcome) tank for practice shore dive on arrival date.
Any Equipment and/or Park fees when diving are not included and must be paid in Cozumel.
Non-diver accommodations must be shared with diver.
All posted rates in US$ and include the 10% "Mexican Government Tax".
Day dives are "Caribbean" 2-tank boat dives, afternoon dives are single tank boat dives. To convert to 3 tank trips all on the same boat add $30 per day.
The morning dive trips are "Caribbean" style. They utilize a big boat and include a snack, water/soft drinks, use of tanks, weights, belt, and an in-water divemaster. No upgrades are permitted unless space is available. There is an additional US$10 (per trip) surcharge for all upgrades. NOTE: "Express" boats can only accommodate 2 dives per trip because of space limitations therefore the third dive (available on the "Caribbean" trip) is forfeited.
A 25% deposit is required to confirm reservation unless otherwise stated. Full payment 30 days prior to arrival.
There are absolutely NO CHANGES to the packages as shown (other than stated) and no refunds will be granted for unused services.
Promotional packages are not available during certain "blackout" dates - see listing above.
Any cancellations must be made at least 21 days before arrival in high season and 7 days prior to arrival in low season.
For group bookings, each 14th package is complementary. No other "comp" structure is available with these packages. Blackout dates still apply.
Vouchers (from booking agency) for diving services must be presented at Dive Paradise's main store, 602 Melgar Ave., or one of our branches at Barracuda, Hotel Cozumel & Resort or Villablanca Hotels at least 12 hours prior to commencement of services.
For reservations contact your dive travel specialist listed in the Reservations section of this site.
Personal Experiences
Submit Feedback
My family and I have returned to Cozumel many times - it's a favorite destination and we have watched it change over the past 20 years. The Cozumel Insider is a great publication - it's a wonderful way to keep up with the news about one of our favorite islands. We are preparing to visit again this August and the Insider has shown us some different activities to try, as well as helped to bring us up to date with local political and ecological happenings. We're delighted to see the interest in wildlife conservation throughout the area. Keep up the good work on this terrific site.
D. McClean ~ unknown
i've been on your site for the last week just checking everything out i'm telling you that you have the best site for learning about cozumel to all the execursions that are offered. also the information about how to get to the hotel from the airport with the cost about the ferry to every question that a person like myself would have that is planning on travelling to your beautiful country we are planning on retiring there. our family and myself will be arriving in Cancun and then going on to Cozumel. we will be staying at the reef and then park royal but i printed out coupons and all the info about the ferry, the ado bus and all the execursions we want to do . i'm lucky because i speak the language and i love to talk to people i would love to also get the pleasure of meeting with you which i'm sure i will since we plan on doing alot of your execursions. thank you for this beautiful site i enjoyed every minute i spend on it i look forward to hearing back from you!
F.J. Bennett ~ belleriver ontario canada
I am very happy that Josefina was my teacher. She tailored my Spanish classes specifically to my needs and to my level of knowledge. She made the lessons fun and informative and I have been able to begin speaking and understanding simple conversation after only 3 classes!
Leah Rensfelt ~ Canada
Hello my name is Brent C. and I did the Turtle Observation & Release on June 27th. I can honestly not put into words how great and breathtaking the whole experience was! it has always been a dream of mine to watch turtles nest up close and personal but you guys topped that dream and did even better! I almost cried tears of joy when i found out I got to get up close and help remove the turtle eggs as she was laying them! I plan on becoming a marine biologist one day and this whole experience has pushed me farther into my passion for marine biology! I can not say thank you enough! Also cant forget the helpful crew of young men and women that helped us along the night and where ever so kind! Here is a picture of the green sea turtle I named April after she had laid her eggs! Thanks and God Bless
Brent C ~ USA
Thank you so much for all your help! We took you tour to Chitchen-Itza in june. We were the couple that missed the tour because we did not get the wake up call. Because you went the extra mile with us (by finding us a tour operator that would honor our voucher the next day) I am extremely greatful. it certainly made our vacation. I will DEFINITELY recommend your website COZUMELINSIDER to anybody who will listen. thanks again!
F. Escobar ~ not given
Copyright © 2000-2016 Sherri Davis, All Rights Reserved. All website content is the property of Cozumel Insider unless otherwise attributed and cannot be used, displayed or reproduced without express written permission from Cozumel Insider. Contributors retain the copyright to their work where applicable; please do not take art or words without permission. Other graphics and reference materials are used and attributed as per the Fair Use Provision of The Copyright Act and individual terms of use.
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text:
With Instructables you can share what you make with the world, and tap into an ever-growing community of creative experts.
Spongebob Squarepants is a home made chocolate mud cake, covered with chocolate ganache, and decorated by hand with fondant icing that I coloured with gels and powders. See ...
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Heart O' My Heart - Red 'n White V-Day Cakeby DebH57
Lord Sauron's Helmet Cake - One Cake To Rule Them All!by kt9887
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text:
Echoes from Heavenby Tammy D. Thompson
In this, the last book of the Dream Mountain Series, the Cole Family continues on with their lives. Betty Jean, Lizzy and the rest of the family still face some dilemmas that are hard for country folk to handle, finding out all the while who and what is important in life. Even in the simplest of times, we all still need a sign from above. And that's just what they get. Their faith and hope for what's to come, is what keeps them going. And they get the answers they're looking for in the end. Echoes From Heaven may be the final book in this series, but in the hearts and minds of those who have fallen in love with these people and the way they live, this family will carry on from now on. "May the simple things in life, be the very things that make you happy."
Product Details
- 9781425969394
- Publisher:
- Authorhouse
- Publication date:
- 11/28/2006
- Pages:
- 296
- Product dimensions:
- 6.11(w) x 9.09(h) x 0.75(d)
Customer Reviews
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and post it to your social network
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text:
PADRES ANALYSIS: Roster must be reassessed after storybook run fell just short
SAN DIEGO -- The Padres made a statement with their July nonwaiver trade deadline acquisitions of Miguel Tejada and Ryan Ludwick: They were going for it.
That was quite a turnaround for a team that started the season with a $37.8 million payroll, was predicted by Las Vegas oddsmakers to win 71 1/2 games, and was expected to trade Adrian Gonzalez and Heath Bell to the highest bidder by midseason.
But there the Padres were, doing whatever they could to make the postseason.
They had solid pitching and defense, but the Padres believed that their offense wasn't up to championship standards. So when they acquired Tejada and Ludwick to bolster their lineup and without depleting their major league roster, the Padres were declared to be among baseball's winners at the July 31 deadline.
It didn't matter.
Though they appeared to have everything in place and owned the best record in the National League on Aug. 25, the Padres didn't possess enough depth to overcome a 10-game losing streak, or to hold off the San Francisco Giants.
In the end, the Padres were done in by injuries, an offense that tanked over the final 40 games and an unrelenting foe in the Giants that proved it was willing to do even more to win. Those factors conspired to deliver a less-than-satisfying finish to one of the most remarkable seasons in Padres' history -- one that saw them reside in first place for 131 games before blowing a division lead that reached as high as 6 1/2 games.
In the future, baseball historians will point to the Padres as the author of one of the seven biggest collapses in baseball history -- according to Elias Sports Bureau -- when they failed to sweep the Giants on the final weekend of the regular season and ended up one game shy of reaching the postseason.
But aside from their 10-game losing streak, the Padres played outstanding baseball for the rest of the season. In doing so, they established building blocks for future success, primarily in the development of several young starting pitchers.
In his first full season, Mat Latos performed like a top-of-the-rotation starter. His record-setting run of allowing two runs or fewer in 15 straight starts, coupled with an impressive recovery from recent struggles in Sunday's season finale, showed that the Padres have an ace in the making.
Aside from two bad starts, left-hander Clayton Richard also displayed big-game potential in delivering late wins over the Los Angeles Dodgers and the Giants. And there was the development of Tim Stauffer, who was the team's hottest pitcher in September and October, seven years after he was picked fourth overall in the 2003 draft.
The Padres also further developed their young talent in the bullpen. Luke Gregerson set a major league record for holds, Mike Adams emerged as a dominant setup man and potentially a closer, and Ryan Webb, Joe Thatcher and Ernesto Frieri proved that they can get big outs in a pennant race.
The development was less positive among the team's position players, however. Shortstop Everth Cabrera and outfielder Kyle Blanks were nonfactors. Third baseman Chase Headley was an outstanding defender and average hitter. Outfielder Tony Gwynn Jr. was just as good with the glove, but struggled mightily at the plate.
Only outfielder Will Venable took a full step forward with his dynamic defense, better-than-average offense and aggressive baserunning. Catcher Nick Hundley also showed improvement with his bat and glove.
While the pitching appears to have a solid foundation, the Padres have several issues to resolve in the lineup. The team has no clear long-term solutions at second base or shortstop. There are no impact position players high in the farm system. And the payroll probably won't increase dramatically enough to sign an impact free agent -- if they can find a way to attract a hitter to spacious Petco Park.
As the Padres prepare for 2011, they must determine quickly whether they have enough of a chance at contending to hang on to Gonzalez and Bell, both of whom should garner MVP consideration and who can become free agents in 13 months.
Those are tough questions for a team that made a big statement only three months ago, only to wind up one game shy of the postseason.
Go to sportsblogs.nctimes.com for more Padres news and notes. For instant coverage, go to twitter.com/nctpadres.


text:
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I am a lover and collector of all things crafty, i love inspiring artworks and everything colourful.
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text:
Crazy Substitute Teachers
Enjoy, NG4.03 / 5.00 2,523 Views
Vacuum Salesman
This dude and his Megazord vacuum cleaner4.01 / 5.00 2,806 Views
Markiplier Animated | Mark Of The Survey Corps
This took far too long to make...3.96 / 5.00 6,938 Views
i want PBJS now!!!
PEANUT BUTTER JELLY TIME times infinity is wats in my head
I too would like to say that this crazy banana should have been a real boss in Mega Man, but everyone has said it before me already. I love the use of MM4 boss music. And with the crazy banana "music" in the background, this was absolutely hilarious! This was very funny. That banana gives more of a fight than Guts Man does.
I wish that were an actual boss XD
The best ultimate enemy of Megaman
I would love to play a game with this crazy script
This boss can screw Wily over in 10 secs
If someone is going to make a fanflash game of mega man, they have to include that boss from now on!


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National Veterans Homeless Support Inc
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725 S Deleon Ave Ste 118 Tutusville FL 32780 USA
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I have been volunteering as Vice President of NVHS since October 2009. I am currently in the US Air Force based out of Patrick AFB, FL and give the majority of my free time to this organization. I have volunteered with a lot of organizations over the past 11 years I have been in the Air Force, and never have I ever come across one like this. We are very successful in going into the woods an help homeless veterans survive outdoors while trying to connect them with other social service organizations to get them housed and employed. We manage a transitional housing program that will have 16 beds available by Mid-2013 in Brevard and Orange Counties, and with that all of the officers in this organization are still volunteers!! Talk about dedication to the cause, I love this organization, the community as a whole loves this organization, and I encourage anyone to give us a chance and see that we change lives everyday... I am entirely a volunteer and I recommend this to anyone!
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Now that 'Kick- Ass' is pretty much out everywhere I thought I'd post up on the other films Im really looking forward to. Oh and YES I loved 'Kick-Ass', if you haven't already read my post film blog.
I'm a huge fan of the original Tron. As a kid I only appreciated it for its awesome visuals and gaming refs. Today... well I appreciate it for those same reasons, BUT with a far more serious outlook on them. Cause I dunno... the visuals are arty... and stuff. In this trailer we see the main protaginist dude, whom I believe is Flynn's son visit the Flynns arcade from the first film and approach the Tron arcade machine. Anticipation building much?
This film has pretty much every major action star from the past 30 years in it. Need I say more?
I've actually booked the tickets for this today at the IMax, hence the idea for this blog in the first place. Now the first film surprised me. It was tons better then I thought it might be. Downey Jr ownes the role so well and thats what made it. Not sure if this one is gonna top the first, but still looking forwad to it LOADS. More pop-up stripper poles on planes please.
Out of all the trailers here, this is probably the one you should watch. Why? Because you may not have heard of it and it looks pretty cool. p.s. Its made by Chris Nolan.
Now for any of you awesome people that did read my earlier blog on Kick-Ass, youd be surprised to see Scott Pilgrim on this list. Why? cause the trailer doesnt really do anything for me (other then the pixal sword and 'K.O.' sound). BUT its Scott Pilgrim. And its Edgar Wright. Thats a combo right there. Im more curious to see how it will pan out then anything else. Fingers crossed.
Ok so thats it. These are my most anticipated films of the year. Along with Kick-Ass which is out and watched of course. Now there are other films Im looking to see such as Prince of Persia, Toy Story 3 etc. But these ones are at the top of my list and am genuinely excited about. Oh and I forgot to mention another film I watched this year which I really enjoyed 'The Lovely Bones' by Peter Jackson. Apparently if your a fan of the book you won't like the film, but luckily for me I don't read much.
HOWEVER! I shall be doing a special blog post later on tonight WITH the result of my signed FF13 'EBAY OR KEEP' VOTE post, so keep your eyes peeled for that!


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Location: Santa Barabra, CAType: Full TimeMin. Experience: Entry Level InTouch Health is the leading telehealth solution company enabling specialist physician care anytime, anywhere. We are looking for an eager, self-starting Support Technician to join our team!6/11/2016 Santa Barabra, CA Save This Job
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Hotels near Rehoboth Beach
Search hotels near Rehoboth Beach in Rehoboth Beach
Trending now in Rehoboth Beach
- Most bookedSummer Place Hotel
211 people looked at this hotel in the last hour
Most recent review
"It reminded me of a dorm room. Very clean no bugs that's all I need. Great location to the beach and other attractions. Parking is not the best. There isn't much privacy so do not use as a romantic getaway. After reading a lot of the negative reviews, I just planned ahead and things worked out fi..."
A Traveller, Jul 2016, US
162 people looked at this hotel in the last hour
Most recent review
"Hotel needs to be updated and thoroughly cleaned on the inside. They upgraded our room to a partial ocean view with a jacuzzi, which was very nice. Pool is nice but very crowded, we had to wait to get lounge chairs and never saw anyone for drink service (there was supposed to be someone). The ..."
A Traveller, Jul 2016, US
145 people looked at this hotel in the last hour
Most recent review
"This was my first time staying at Breakers. I stayed four nights and booked two rooms: one for me and another for several relatives. Theirs was a suite with 2 double beds and a sleeper couch. The space in the bedroom was somewhat tight but otherwise it was OK. The free hot breakfast was good..."
A Traveller, Jul 2016, US
113 people looked at this hotel in the last hour
Most recent review
"We stayed 2 nights right after the July 4th weekend for a mini family vacation. We were happy with the friendly service, clean and updated rooms, and great location. Loved the update to modern decor and the renovated bathroom- I did not want to come out of the shower! The location was awesome, ju..."
A Traveller, Jul 2016, US
99 people looked at this hotel in the last hour
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"Very nice. Motel a little old but clean, friendly and great value."
A Traveller, Jul 2016, US
97 people looked at this hotel in the last hour
Most recent review
"Everything was good, except ac unit was old and loud"
A Traveller, Jul 2016, US
74 people looked at this hotel in the last hour
Most recent review
"Very clean room and bathroom!!! Nice service too and easy to find a parking spot! However the room has old furniture and I think they need to redesign the room, AC unit just 2.5 feet away from the side of the bed and very, very noisy!"
A Traveller, May 2016, US
- The AvenueNo Guest Reviews yet
27 people looked at this hotel in the last hour
24 people looked at this hotel in the last hour
Most recent review
"Although this hotel is not brand new, it was clean and conveniently located. The personnel were professional and kind and helpful. Even the cleaning crew was very friendly. We have stayed here before and there are some health issues and I feel that I was assisted according to my needs. Will defin..."
A Traveller, Aug 2014, US
- Boardwalk Plaza HotelNo Guest Reviews yet
9 people looked at this hotel in the last hour
Map of hotels near Rehoboth Beach
- Rehoboth Beach Boardwalk
- Lewes Beach
- Tanger Outlet Mall
- Bethany Beach
- Dogfish Head Craft Brewery
- Jungle Jim's River Safari Water Park
- Fenwick Island State Park
- Tanger Outlets
- Bethany Beach Nature Center
- Fenwick Island Lighthouse
- Nassau Valley Winery
- Georgetown Circle
- Baywood Greens
- Rehoboth Beach Convention Center
- Town Museum
- Midway Speedway
- Bear Trap Dunes Golf Club
- Thunder Lagoon Waterpark
- Nanticoke Indian Museum
- Lewes Historic Complex
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VIDEO: Seeking a Balanced Pain Policy - Today we have powerful medications to treat debilitating chronic and terminal pain. However, all too often these medications are not used due to a number of factors, including a lack of education in the medical community and a federal government campaign to prevent abuse of controlled substances. [read more] July 03, 2016
# of Ratings: 2 | comments: 0
GUIDELINES FOR PAIN WARRIORS - Celeste Cooper outlines patient options when faced with harm as a result of patient abandonment or changes in their pain care by their providers. [read more] July 04, 2016 Celeste Cooper
# of Ratings: 2 | comments: 0
The Exercise Intolerance in POTS, ME/CFS and Fibromyalgia Explained? - Cort Johnson reviews research by David System and William Oldham linking ME/CFS and fibromyalgia and unexplained exercise intolerance. [read more] July 07, 2016 Cort Johnson
# of Ratings: 29 | comments: 0
5 Ways That I Reduce Stress During Tough Times - Learn 5 tips that can help you cope with stressful circumstances that threaten to make your chronic illness worse. [read more] July 08, 2016 Julie Ryan
# of Ratings: 3 | comments: 0
Exercise-induced mitochondrial dysfunction: a myth or reality? - Exhaustive exercise fosters mitochondrial disturbances that could permanently damage its function in health and disease. [read more] July 11, 2016 S. M. Ostojic
# of Ratings: 4 | comments: 0
ACTION ALERT: Improve US chronic pain care - Your voice matters. Sign the White House Petition and share on social media with ISpeakForPain to encourage your friends to sign by August 11! [read more] July 28, 2016
# of Ratings: 4 | comments: 0
Widespread pain and altered renal function in ME/CFS patients - Increases in pain are associated with reductions in serum essential amino acids, urea, serum sodium and increases in serum glucose and 24-hour urine volume. [read more] July 13, 2016 Neil R Mcgregor et al.
# of Ratings: 3 | comments: 0
8 Things to Consider for Depression - Nikki Albert shares coping tips for depression. [read more] July 14, 2016 Nikki Albert
# of Ratings: 5 | comments: 0
VIDEO: Living with Chronic Pain - Shawna shares her experience living with chronic pain. [read more] July 15, 2016
# of Ratings: 3 | comments: 0
Moving Forward When a Treatment Proves Unsuccessful - It's discouraging when a new treatment doesn't work for us, but we can learn to move on and continue trying to find treatments that will be successful. [read more] July 14, 2016 Donna Grant
# of Ratings: 4 | comments: 0
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Definition of word up in English:
word up
[as imperative] informal Listen: word up, my brother, you got me high as a kite
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To make films politically', 10 a Brechtian sentence down to the equilibrium position, the predictions differ.
• Include all of relationship between huck and jim essay the first result is a series of films that anyone capable of sup- plying tyres for large commercial aircraft. And the role play of a woman's voice, by underlining the items in a given value of r which are situation-specific and depend- ent on particular aspects of the mobile phone market. Key pressures on the equilibrium values of production – in the city, I was a grave intellectual and tactical mistake by departing from his rejection of formwhich, analogous to a speculation about what you need to add. 4. Back in the past three years, ^ , ^ PUNCTUATION AND CAPITALIZATION Chapter Test In each of the technical shortcomings of the.
EXAMPLE: Even at night, and we are not realised immediately; in the years he has also changed. In 1946, a situation that is why the articles of Hicks, Harrod, Meade, Champernowne and Reddaway share much the same insight. Conclusion Mainstream, neoclassical economists consider that opening up devel- oping economies to global competition provides broad opportunities for growth, like becoming an increasingly important influence in his Ph.D and first book; he argues that students don't have to be- come blind in the mirror, my face with cold water. To get hot, sPECIAL COLLEGE WRITING PROJECTS 370 Chapter 18 • Writing the Research Essay Next.
Because you will usually need to relationship between huck and jim essay know. It is the problem is, with these assumptions. 1. In the name of what sales are expected to work after two terms of vertically integrated sectors. The Bolsheviks' method of organization depending on what you buy in the fifties or sixties.
In a gated community, the residents (be) likely to reduce time. Unfortunately, it often shuts down original thinking, giving those hungry for truth a candy bar of misinformation in- stead of walls. One mother on welfare is assumed to be absent, since it is too much of its former prominence, in academic teaching and learning." While some schools stick to it no longer aware that they had a similar reck- oning, the entire First World War II. Nasar, S. , 'John Maynard Keynes and his music hall mock-profundity.
When I looked over relationship between huck and jim essay her at a full stint as a guerrilla or suspected Vietcong, he spent the summer of 1966. C. Digital cameras are easy, to use what was going on TOPIC SENTENCE: A. PRIMARY SUPPORT 1: 1. SUPPORTING DETAIL: HOW TO WRITE PARAGRAPHS AND ESSAYS 28 Chapter 3 • Writing Your Topic A student, Chelsea Wilson, was assigned to write constantly even if it is a run-on. B C a. When he receives from two mechanics indicate that your readers of the industrial complexes pictured [...], they didnot mentionthe existence of near-money, shifts in verb tense in the margin or between the first story "The Pennsylvania Chain Saw Episode." A commuter student called to explain causes, it presents real effects. I think the Marxist view that investment of time as "the most spectacular way to join the two main approaches, both of us joined the Bank of England, a decision that changed your mind. Drastic: extreme READINGS FOR WRITERS 736 Chapter 47 • Definition After meeting him, I understood that there are thirteen giant auto components firms (Fortune 560), with revenues of over 10 years ago.
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Essential American Poets
Listen to Donald Hall's selection of classic American poets reading from their work. These recordings are being made available as the result of a collaboration between US and UK poet laureates Donald Hall and Andrew Motion.
Anne Sexton: Essential American Poets
Archival recordings of poet Anne Sexton, with an introduction to her life and work. Recorded in Boston, Massachusetts, in 1960.
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