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Build a Fast Low-Frequency Meter
Walsh-Hadamard Encoders/Decoders Know Your Op-Amps Designing for EMC
Double your technical pleasure each month. After you read Circuit Cellar magazine, get a second shot of engineering adrenaline with Circuit Cellar Online, hosted by ChipCenter.
Roaming About
Wireless Connectivity for Mobile PCs Vinit Nijhawan
With all of the advances in wireless technology, it's no wonder that wireless communications is one of the fastest growing industries on the planet. In this article, Vinit takes a look at some of the various public wireless network technologies available today.
Learning the Ropes
Design Downloading and Debugging Ingo Cyliax
Last time, Ingo designed a simple bi-colored LED project. Using CPLDs and FPGAs is much easier when you understand how they work, so this month he gives us some information on flash-memory based CPLDs and SRAM-based FPGAs before explaining how to download and debug your design (even if it is just a blinky LED project) in a Xilinx FPGA environment.
A Well-Lit Sound Check
Build a MIDI Adapter with a LED Indicator Stuart Ball
Is your soundcard MPU401 or MIDI compatible? If you think it is, but aren't sure what that means, then you definitely want to listen up. Stuart explains some of the details of working with and understanding MIDI, and then shows you how to build a MIDI adapter (complete with LEDs) for a soundcard.
Lessons from the Trenches
Embed This PC Part 3: Emulator to Application Testing George Martin
Now that George has explained some of the requirements for embedding a '486, it's time to get things going and start testing. Before he's done with Part 3, you'll have a simple design, some startup code for the emulator, and a project.
87C51 Programmer Adapter
Noel Rios
Programming the 87C51 is easy when you have a dedicated or universal programmer, but such devices certainly aren't free. That's why Noel used an EPROM programmer, crystal, logic IC, and a few other parts to make this simple, inexpensive adapter for programming the 87C51.
Silicon Update Online
Analog PLD Anyone? Tom Cantrell
We're in the middle of the digital revolution, but according to Tom, 1s and 0s will never overthrow the world as we know it. After all, the world as we know it, is analog.
Resource Links
• System Safety • Metglas (Application of Amorphour Metals) Bob Paddock
Test Your EQ
8 Additional Questions
. ARble of Con LL Ta
O M/nts for Mar CO e
INhE2000 NL
Let us help keep your project on track or simplify your design decision. Put your tough technical questions to the ASK US team. The ASK US research staff of engineers has been assembled to share expertise with others. The forum is a place where engineers can congregate to get some tough questions answered, or just browse through the archived Q&A's to broaden their own intelligence base.
Deadline is May 1, 2000
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April 2000
Issue 117
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Getting Your Signals Straight Walsh-Hadamard Encoders and Decoders in MATLAB Kizito Tshilumba Kasengulu Building a RISC System in an FPGA Part 2: Pipeline and Control Unit Design Jan Gray The Shocking Truth about EMC Part 1: Design for Compatibility George Novacek A Quick Meter Made Fast Frequency Meter for Low Frequencies Markus Desgronte All About Correlation Ron Tipton I MicroSeries Op-Amp Specifications Part 1: Served Italian Style Joe DiBartolomeo From the Bench Drop the Incredible Bulk Using Capacitors as Isolation Components Jeff Bachiochi Silicon Update A Winter Timer Tale Tom Cantrell
Task Manager Rob Walker Digital Becomes Analog New Product News edited by Harv Weiner Test Your EQ Advertiser's Index May Preview Priority Interrupt Steve Ciarcia All Things Considered
8 83 95 96
EMBEDDED PC 39 Nouveau PC 42 RPC 46 APC
edited by Harv Weiner
Real-Time PCs POST It Build a Power-On Self Test Card for PC/104 Ingo Cyliax
Issue 117
Applied PCs Under the Covers Part 1: Get Embed(ded) with Windows NT 4.0 Fred Eady
CIRCUIT CELLAR® April 2000
PA 19043-9613 or call (800) 269-6301.95.luster@circuitcellar. Circuit Cellar® makes no claims or warrants that readers have a right to build things based upon these ideas under patent or other relevant intellectual property law in their jurisdiction. P.S. because it gave me an idea of the things we need to work on and improve. or check drawn on U. Holmes. and not everyone who was familiar with us was 100% satisfied with everything we've done. But. It's just like taking a standardized test. Circuit Cellar® makes no warranties and assumes no responsibility or liability of any kind for errors in these programs or schematics or for the consequences of any such errors. Circuit Cellar and Circuit Cellar INK are registered trademarks of Circuit Cellar Inc. with plenty of zeros.com TO SUBSCRIBE: (800) 269-6301 or via our editorial offices: (860) 875-2199 GENERAL INFORMATION: TELEPHONE: (860) 875-2199 FAX: (860) 871-0411 INTERNET: info@circuitcellar. Suite 20. is prohibited. we are living in an increasingly digital era.circuitcellar.com . but I've seen the stats on Circuit Cellar readers and I'd say that 100% of our readers are human." Both sides have their politics and religion. As Joe DiBartolomeo found out when preparing this month's article on op-amp specifications. funds only via VISA. was the issue of digital designers having to find their way through analog design. or that readers have a right to construct or operate any of the devices described herein under the relevant patent or other intellectual property law of the reader's jurisdiction.com EDITORIAL OFFICES: Editor. politics and religion is matter for the trade magazines. you just circle the answer that looks like it might be right and go on. I heard some pretty interesting workarounds that digital designers had come up with. Namely. all other countries $85. You take your time and make sure you ace the questions in your area of expertise.95. All of this emphasis on going digital has brought to attention some interesting issues. when digital designers find themselves faced with analog design issues. MasterCard. 4 Park St. Box 698. Sure. contact Jeannette Ciarcia (860) 875-2199 or e-mail jciarcia@circuitcellar. Circuit Cellar is about quality editorial and practical application articles. Canada/Mexico $55.com 6 Issue 117 April 2000 Entire contents copyright © 2000 by Circuit Cellar Incorporated. you don't spend a lot of time on the questions you don't know or understand. Canada/Mexico $31..walker@circuitcellar. CT 06066 AUTHOR CONTACT: E-MAIL: Author addresses (when available) included at the end of each article. One of the things that came up while I was talking to different people at the show. Until that changes. Tom's on top of this issue. or www. CT and additional offices. All rights reserved. Speaking of humans being analog. That mentality certainly doesn't make them inferior designers. but it certainly won't disappear because humans are analog. Postmaster: Send address changes to Circuit Cellar.95.com. all other countries $49.. One-year (12 issues) subscription rate USA and possessions $21. But. Circuit Cellar. I had a chance to make a bit of a digital-to-analog conversion while at the ESC-Spring in Chicago last month.com. software designers who enjoy the code snippets and software downloads. instead of dashing off digital e-mail replies to readers and authors. P. In January. not form. then there was Stuart Ball's digital sound board project.S. All subscription orders payable in U. and the list goes on. Try voicing your opinion to one of the trade magazines and you'll find out that the only input they want from you is green. editor@circuitcellar. the analog gap may be closing.com ADVERTISING COORDINATOR Valerie Luster (860) 875-2199 ADVERTISING CLERK Fax: (860) 871-0411 E-mail: val. Vernon. Circuit Cellar® disclaims any responsibility for the safe and proper function of reader-assembled projects based upon or from plans. I guess we'll just keep shaking hands and taking your comments.yush@circuitcellar. I also heard analog specialists discussing some of the bubble-gum-and-baling-wire solutions they had run across that were "obviously contrived by digital-oriented designers. Two-year (24 issues) subscription rate USA and possessions $39. as you saw in his March Silicon Update Online article on the latest analog PLDs from Lattice Semiconductor. and instructors who use Circuit Cellar in the classroom. future authors. and plenty of subscribers.O. CIRCUIT CELLAR® www. Direct subscription orders and subscription-related questions to Circuit Cellar Subscriptions. that digital engineers are being asked to fill in more and more analog gaps. I talked to hardware designers who like the schematics.O. rob. That is. not everyone who came by the booth was familiar with Circuit Cellar. descriptions. or information published by Circuit Cellar®. Periodical rates paid at Vernon. Box 698. humans are analog. For information on authorized reprints of articles. bank. international postal money order. I haven't seen any trade magazine demographics. Circulation Dept. t THE MAGAZINE FOR COMPUTER APPLICATIONS EDITORIAL DIRECTOR/PUBLISHER Steve Ciarcia MANAGING EDITOR Rob Walker TECHNICAL EDITORS Jennifer Belmonte Rachel Hill Jennifer Huber WEST COAST EDITOR Tom Cantrell CONTRIBUTING EDITORS Mike Baptiste Ingo Cyliax Fred Eady George Martin Bob Perrin NEW PRODUCTS EDITOR Harv Weiner PROJECT EDITORS Steve Bedford Janice Hughes Elizabeth Laurençot James Soussounis David Tweed ASSOCIATE PUBLISHER Sue Skolnick CIRCULATION MANAGER Rose Mansella CHIEF FINANCIAL OFFICER Jeannette Ciarcia CUSTOMER SERVICE Elaine Johnston ART DIRECTOR KC Zienka GRAPHIC DESIGNER Mary Turek STAFF ENGINEERS Jeff Bachiochi John Gorsky Tak Auyeung QUIZ MASTERS Benjamin Day Bob Perrin EDITORIAL ADVISORY BOARD Ingo Cyliax Norman Jackson David Prutchi Cover photograph Ron Meadows—Meadows Marketing PRINTED IN THE UNITED STATES ADVERTISING ADVERTISING SALES MANAGER Bobbi Yush Fax: (860) 871-0411 (860) 872-3064 E-mail: bobbi. Holmes. because of possible variation in the quality and condition of materials and workmanship of readerassembled projects. THE MAGAZINE FOR COMPUTER APPLICATIONS (ISSN 1528-0608) and Circuit Cellar Online are published monthly by Circuit Cellar Incorporated. The reader assumes any risk of infringement liability for constructing or operating such devices.com. I enjoyed talking to those people too. Reproduction of this publication in whole or in part without written consent from Circuit Cellar Inc.TASK MANAGER Digital Becomes Analog here's no question. CT 06066 (860) 875-2751.circuitcellar. Vernon. PA 19043-9613. Mark Balch finished up his three-part series on high-definition digital television and brought us up to speed on the analog-todigital conversion process. I got to do some analog handshaking and spend some time talking to previous authors. they focus on function.circuitcellar. Like he said. CIRCUIT CELLAR®. that's for sure. After all. The information provided by Circuit Cellar® is for educational purposes. Jeff recently finished a series on digital filters in his From The Bench column.com Sally Collins CONTACTING CIRCUIT CELLAR SUBSCRIPTIONS: INFORMATION: www. 4 Park Street.com or subscribe@circuitcellar. At least that's the impression I got from talking to readers while I was in Chicago. Furthermore.
monitoring options. 8-bit ASCII display interface with onboard.50-mm (0. In QUICK START. converts the image to black and white pixels. Threshold values can be programmed. Applications include bench top. mounting bracket. and compares the designated-color pixel count with user-programmed upper and lower threshold values to render a pass or fail judgment of the target.0 mm (6. and cable. These compact displays offer designers a simple and low-cost way to display icons. Each model features a 5. or teaching bad product. and signature capture touch requirements. masking. and transient voltages. It features an 8wire interface for accuracy. Integral circuitry protects the sensor against overload. displays programming options.020" × . short circuit.apollodisplays. Also available is a transflective.com 8 Issue 117 April 2000 CIRCUIT CELLAR® www. The PresencePLUS sells for under $1700.NEW PRODUCT NEWS Edited by Harv Weiner PIXEL-COUNTING SENSOR The PresencePLUS Pixel-Counting Sensor is a camera-based sensor that consists of a 512 x 384 CMOS pixel array with a programmable microprocessor. and the light source behavior.76") viewing area and outline dimensions of 170.1" × 0. rack or panel mounted instruments.0-V.baneng.020") pitch in a 126. off or strobed.0 x 14.7" × 4. and bit-map graphics with optional user input via an analog resistive touchscreen. and RUN option for applications that do not require defining a specific region of interest. The PRC1 hand-held controller. (612) 544-3164 • Fax: (612) 544-3213 www. The touch screen is designed for finger. The sensor captures a 256-level grayscale image of a specified area. Individual sensors list at $995. passive LCD's with onboard controllers and optional touchscreens.55"). The sensor's three SPST solid-state output contacts may be individually programmed for either NPN (sinking) or PNP (sourcing). and captured images on its LCD screen. the pass and fail values are automatically set to 15% above maximum count and 15% below minimum count.com . industry standard controller T6963C and 64-KB SRAM. User programming designates which pixel color to count. lighting.0 x 105. logos.50 × 0.circuitcellar. mounts directly to the display bezel. stylus. The displays price from $99 and $79 with and without touchscreen. POS terminals. NEMA 1. The display includes 240 × 128 pixels with 0. either manually or automatically. LCD DISPLAY Apollo Display Technologies Inc. and other applications requiring high information content in limited space. sunlight readable version with LED backlighting. respectively. The line includes black and white FSTN transmissive and blue and white STN transmissive models. has introduced a high-contrast line of 240 × 128 pixel monochrome. Inc. multiple fonts. (631) 654-1143 Fax: (631) 654-1496 www. reverse polarity. white or black.0 × 70.com Apollo DisplayTechnologies. The device features an anodized aluminum housing with a painted finish and has an environmental rating of IP20. the auto-exposure time. TEACH. bar charts. and offers 79% transmissivity with integral anti-glare film and hardcoat. used to program and monitor the PresencePLUS. Banner Engineering Corp. both with cold cathode backlighting.96" × 2. using one of the sensor's two TEACH modes.0-mm (4. controller. lens. indexed or motion. QUICK START is a one-step SETUP.
com www. The motion processor outputs commutation signals based on either Hall sensors or the motor's encoder. The chipset is available in two (MC2820) and four axis (MC2840) configurations with prices starting at $69 in OEM quantities. velocity. either in a 16-bit Digital-to-Analog Converter (DAC) or 10-bit.NEW PRODUCT NEWS MULTI-AXIS MOTION PROCESSOR The Navigator MC2800 Series of Multiple Motor Type Motion Processors allows the control of both brushed and brushless servomotors in one chipset. Performance Motion Devices. materials handling. The MC2800 Series has a pre-programmed PID filter with feedforward velocity and acceleration. test and laboratory equipment. and a 32-bit position error. and acceleration from the host. overshoot. trapezoidal. semiconductor manufacturing. By directly outputting commutation signals from the chip. The chipset supports sinusoidal commutation of 2. and generates a corresponding trajectory. and textiles. oscillation.circuitcellar.com CIRCUIT CELLAR® Issue 117 April 2000 9 . User selectable profiling modes supported by the motion processor include Scurve. Users can select any axis to be brushed or brushless (for 2 and 4 axes). Its instruction set supports more than 130 commands to offer flexibility and versatility during application programming. the MC2800 reduces torque ripple. (781) 674-9860 Fax: (781) 674-9861 www.or 3-phase brushless motors. Two or three separate motor signals per axis are sent by the motion processor. and electronic gearing. velocity contouring. The chipset consists of a 132-pin processor and a 100-pin logic and gives users the ability to off-load resource intensive motion control functions from the application's host processor. as well as positioning and velocity control of brushed servomotors. Applications include industrial automation and robotics.pmdcorp. Inc. 20-kHz Pulse Width Modulation (PWM) compatible format. and audible noise level. medical automation. The MC2800 Series accepts input parameters such as position.
and Sun SpARCstations running SunOS or Solaris. a programmable local oscillator. which includes half-band and CIC interpolation filters.995. The VIM modules are daughter cards designed to maximize I/O transfer rates to match the performance and speed of the Pentek 'C6x DSP boards. Both channels use the AD9856 Quadrature Digital Upconverter. Applications include radar test signal generation. transmit functions for advanced software radio and satellite communications systems. a complex mixer. and a 12-bit D/A converter.pentek. electronic countermeasures. It is ideal for radio transmission and can be attached to any VIM-compatibleTMS320C6x digital signal processor (DSP) board and digital receiver to build a complete. Pentek's ReadyFlow Board Support Libraries of C-callable device functions are supplied with all VIM modules. Digital Alphas running D-UNIX.circuitcellar.NEW PRODUCT NEWS SIGNAL PROCESSING SYSTEM The Model 6229 is the industry's first digital upconverter and D/A VIM-2 (Velocity Interface Mezzanine) module. Inc. Third-party and Pentek software development tools are available for a variety of platforms including PC's running Windows 95/98/NT. The digital upconverter and D/A module contain two complete upconverter channels. HP workstations running HP-UX. and synthesized signal generation for test and measurement. (201) 818-5900 Fax: (201) 818-5904 www. low-cost transmit and receive software radio system.com 10 Issue 117 April 2000 CIRCUIT CELLAR® www. VIM modules are offered in several different sizes and formats with an extensive array of functionality. Pricing for the Model 6229 starts at $3.com . Pentek.
allowing the compiler to carry out cross-module optimizations. with peaks up to 40 A off a single 4. a state of the art source level simulator. The debug monitor turns the Virtual Workshop into a full source level remote debugger. The debug monitor consumes less than 2 KB of program space and easily fits beneath the 0800h address partition of the Dallas DS5000. The CMI-50I5-12. but a 120° factory option is available. Coupled with a unique low loss current sensing circuit and internal bus capacitors.circuitcellar.NEW PRODUCT NEWS MOTOR CONTROL MODULE The CMI-5015-12 Motor Control Module is specifically designed for operating both fractional and integral horsepower three-phase motors. which can be used to develop and fully debug 8051 programs both with and without target hardware. The Virtual Workshop communicates with it via a PC serial port and controls execution of the user's program breakpoints. The CMI-5015-12 is designed with 60° electrical sensor phasing. allows full source level debugging without any hardware. fans. It also features customizable common code merging. the Embedded Development Studio is able to drive the parallel compilation of all of the source files in a program. also known as the 8051 Virtual Workshop. it will check the integrity of the entire program ensuring that variables. It supports memory banking with up to 256 banks of code and 256 banks of RAM.com www. It can be rapidly extended to simulate additional devices allowing the simulation of complete target systems. batteryoperated motors. The C compiler features smart pointers that free the programmer from the task of telling the compiler where variables are located. single stepping. hermetically sealed module. All of these integrate into Crossware's Embedded Development Studio environment to create a single vendor tool set.com Crossware + 44 (0)1763 853500 Fax: + 44 (0)1763 853330 www. plug and play module contains the latest ASIC technology for commutation. is supplied together with tools and instructions that allow it to be modified and debugged without hardware. The CMI-50I5-12 sells for $375 per 1. making it ideally suited for high performance battery operated three-phase Brushless Motor Control applications. vibration. 8051 DEVELOPMENT SUITE The 8051 Development Suite includes a full-featured ANSI C compiler. an advanced overlay linker. an so on. and operates over the full military temperature range of -55°C to 125°C. and blower motors.to 12-V power supply. positioning systems. using the Virtual Workshop. a relocatable cross-assembler. and extreme temperature are present.cmodules. Its high-efficient power stage is made up of high and low side drivers for driving the gates of low resistance N Channel power MOSFETS. cross conduction protection. The simulator.crossware. The linker also is cross-module aware. swapping itself to external ram while the users program is active. the need for large external components is eliminated. electromechanical valve assemblies. The module is ideally suited for harsh environments where shock. Composite Modules (508) 226-6969 Fax: (508) 226-0938 www.com CIRCUIT CELLAR® Issue 117 April 2000 11 . such as robotics. It consumes no internal ram resources. functions. temperature compensated reference. and other objects are used consistently across modules. and a debug monitor. and cycle-by-cycle current limiting. The module delivers currents of 30 A. It is packaged in a miniature. under voltage lock out protection. allowing the programmer to adjust the size of the program to fit the memory available. An internal DC/DC converter provides logic voltages allowing the module to operate off a single supply as low as 4 V while supplying maximum current to the output stage. braking. Full C source code.000. In addition. As well as performing an overlay analysis to minimize memory usage.
0) (0. or a multiple of 4. 4. in most applications only linear codes are used.0.1.0. which is why they are used in DSP for communications.0. how do we construct a matrix of a certain order (n) in agreement with the above theorem? The answer to the first question is. yes.[2] Because linear codes are used in this article.0. image processing. 12 Issue 117 April 2000 CIRCUIT CELLAR® www.0. and so forth. Hadamard codes belong to the category of block codes.1. it's important to say that the Sylvester construction technique for a matrix of order n = 2m (m being a positive integer) always leads to a linear code. Despite the fact that they can be linear (i.1.0. Hn is in natural order if its rows are not ordered with respect to the number of sign changes in each row. Kizito was kind enough to give us some Hadamard code background before explaining how to implement these helpful encoders and decoders in MATLAB.e. Does the arrangement of rows or columns (because it changes nothing.1..1) (0.0) (0.0. where the encoder takes the original stream of bits.1.e. They are easy to generate and provide simple properties that can be expressed through the algebra of matrix and Hadamard Transforms.0) (0.1) Table 1—The encoder maps the message into a code word according to the Reed-Muller Algorithm. in this article I chose a widely used arrangement called natural order (H8 is naturally ordered). the response to the second question will concern naturally ordered matrix. Using this DEFINING A HADAMARD MATRIX A mathematical definition is provided in this section (a demonstration of the theorem can be found in [2]).0.Getting Your Signals Straight FEATURE ARTICLE Kizito Tshilumba Kasengulu order n exists. Many arrangements are possible [3]. You can verify that any pair of rows or columns is orthogonal. n Two questions must now be answered.[1] They have interesting properties. the inner product is zero). 2.1.circuitcellar.0.1.1. while the Paley technique for n > 8 always leads to a nonlinear code. the theorem: if a Hadamard matrix of Message (1. such that any pair of distinct rows or columns is orthogonal (i.1. +1 +1 +1 +1 +1 +1 +1 +1 +1 – +1 – +1 – +1 – +1 +1 – – +1 +1 – – +1 – – +1 +1 – – +1 H8 = +1 +1 +1 +1 – – – – +1 – +1 – – +1 – +1 +1 +1 – – – – +1 +1 +1 – – +1 – +1 +1 – [1] Walsh-Hadamard Encoders and Decoders in MATLAB Not up to speed on Walsh-Hadamard encoders and decoders? No problem.1.1) (0. we will work only with rows for simplicity) make a difference in applications? And. First.1. and outputs code words with a content and a length defined by the properties of the code. then n is 1. Therefore.1.1.com .0.1.1) (1. The most used algorithms that allow the construction of a naturally ordered Hadamard matrix are named after Sylvester and Paley. The order of rows leads to different matrices having different behaviors in applications. divides it in short sequences of a certain length.0.1.1. The matrix H8 is a Hadamard matrix of order 8 (the character "–" for "–1"). the definition: a Hadamard matrix of order n is a n × n matrix of 1s and –1s. And now.0) Code word (0. the Sylvester technique of order n = 2m is chosen. amed after the French mathematician Jacques Hadamard.0. At this stage.. each component of the code word is a linear combination of the ones in the message) or non-linear.
5 1 W3 0 0 -1 0 1 0. Haar functions. note that MATLAB software provides the function hadamard(n) that allows the creation of a naturally ordered Hadamard matrix of order n. you have linear binary block codes of length n. F_8_2=kron(kron(eye(2). f(n) being a sequence containing M = 2m real numbers. Naturally ordered WalshHadamard matrices of order n have an index from 0 for the first row to n – 1 for the last. the integral can be replaced by a summation.5 Time 1 -1 0 0. among the possible codes you can derive from them. a Walsh-Hadamard matrix is a Hadamard matrix where its rows describe samples of Walsh functions. this leading to linear binary block codes of length n = 2m and to their decoding with Fast Hadamard Transforms.5 Time 1 Figure 1—Here are the eight Walsh functions over 0 to 1. 1 -1 . observe that the Walsh-Hadamard Transform makes only sums and substractions (they will be taken as sums) of the elements of the inputted vector. function FWHT_Vector = FWHT_8 ( Input_Vector _8 ) %-----------------------------------------------------% function : FWHT_8 % Description : This function executes a Fast Walsh-Hadamard Transform with a natural order.5 1 -1 0 1 0. as are the Walsh functions.1). now called Walsh-Hadamard matrix. its second the sample of W1. arranged in natural order from W0 to W7 .circuitcellar. WALSH FUNCTIONS In the mathematical literature.5 1 -1 0 1 0. in accordance with the Sylvester construction technique and the earlier-mentioned theorem.H_2).5 1 0 0 -1 0 1 0.5 W7 0 0 -1 0 0. If the Hadamard matrix is in natural order. For an input Issue 117 April 2000 www. …WHT 2 m – 1 = ƒ n WH 2 m [5] From equation 4. its first row is the sample of W0. [2] -1 0 1 0. and so on. the naturally ordered Hadamard matrix of order n = 2m is obtained through: 1 1 0 H1 = 1 H2 = 1 1 1 –1 Hn Hn H2n = Hn –H n This article will deal with the naturally ordered Hadamard matrix of order n = 2m. and M–1 and WH is the naturally ordered WalshHadamard matrix of order M. We also can write (equasion 4) in the general matrix form: WHT = WHT0. its naturally ordered Walsh-Hadamard Transform WHT is defined as: M –1 Listing 1—This is the code for the implementation of equations 6 and 7. %-. F_8_3=kron(kron(eye(1).eye(2)). this for vectors of length 8. two continuous functions S1(t) and S2(t) are said to be orthogonal over t2-t1 if: t2 t1 ∫ S1 t S2 t =0 [3] If we have discrete functions or sequences. Note that the matrix of equation 1 is a naturally ordered Walsh-Hadamard matrix. W4 W2 W6 W5 FAST WALSH-HADAMARD TRANSFORMS Just like a Fourier Transform is an expanded summation of the orthogonal functions sin() and cos(). a Walsh-Hadamard Transform also is a summation of the Walsh functions of a Hadamard matrix. Walsh functions were first published in 1924 by J. Walsh functions.eye(4)).…. Walsh. ]. In closing this section. and so on.H_2).H_2). n n=0 [4] where k = 0.2. All of this is of course in agreement with the above theorem. Figure 1 shows eight Walsh functions over 0 to 1. WHT1. and the orthogonality expresses that the inner product (scalar product) is zero. and its rows are noted by index starting from 0 for the first row to 7 = 8 – 1 for the eighth row.5 1 -1 0 1 0. The Walsh functions in Figure 1 can be related to the rows of a Hadamard matrix of order 8 (see equation 1) because if you take eight samples (from 1/16 with interval 1/8) of each of the continuous Walsh func- tions. In other words.1. Among orthogonal continuous func- tions. As it will be seen later.W0 0 W1 Sylvester construction technique. we can mention the wellknown sin() and cos(). FHT_Vector_8=Input_Vector_8*F_8_1* F_8_2*F_8_3 % performing the FWHT end WHT k = Σ ƒ n WH k.L.The three stages in FWHT_8 F_8_1=kron(kron(eye(4). %-----------------------------------------------------H_2=[ 1 1 .[4] They are obtained by using square waveforms to produce the number of desired functions.com CIRCUIT CELLAR® 13 . Remember that in this article n = 2m (m positive integer). the resulting sequences are simply rows of the Hadamard matrix.
that is. end WH2 m = F 1 2 mF 2 2 m…F m 2 m where: [6] F i2 m = I 2 m – i ⊗ WH2 ⊗ I 2 i – i [7] this code is said to be non-cyclic because every code word does not have a shifted version inside the code.…m. keep in mind that the Hamming distance (d) between two sequences of equal length is the number of coordinates in which they differ. Therefore. floor_function d min – 1 2 [9] This correction capability must be taken as minimal because it can be proven that some block codes have a higher capability. Because the Hamming distance between a code word and its complement always has a value of n.e. saying that the linear codes studied in this article are noncyclic codes means that. You can verify that this Walsh-Hadamard code of length n = 2m (2n codes words of length n) has a minimum distance of: IN THE WORLD OF BITS After defining the real matrix. M(M–1) operations.vector of length M you have M – 1 additions in M steps. a maximum likelihood hard decision decoder (MLHDD) outputs the code word closest in Hamming distance to the received sequence. Also. function Vector = Conv( Binary_Sequence ) %-----------------------------------------------------% function : Conv % Description : This function converts a Binary Sequence into a Vector containing +1s or -1s %-----------------------------------------------------Vector=[]. This function is used to cross from the binary world to the real world. end . The code definition here is commonly used and is sufficient for a good understanding of the subject. The MLHDD will output a code word having a minimal Hamming distance of dx to the received sequence and n + dx between the complement of the code word and the received sequence.Converting 1 into -1 Vector=[ Vector -1 ]. Despite the fact that there are many Walsh-Hadamard code definitions. In other words. 3. end. a WalshHadamard code has a length of n and comprises 2n code words. A code with dmin can detect all error patterns of weight (the number of nonzero coordinates in a sequence) less than or equal to. M log2 M operations). dmin – 1. in this article. This method uses a factorisation of the matrix WH so the application has fewer steps compared to the ordinary case. It can correct all error patterns of weight less than or equal to: CIRCUIT CELLAR® and i = 1. for every code word. which allow you to convert a binary sequence into a real vector. Fast Walsh-Hadamard Transforms allow a gain in time by having M additions in log2 M steps (i.. [8] Listings 2 and 3 contain the functions Conv(Binary_Sequence)and BinHM(Hadamard_ Matrix). respectively. 2. here the code has a length of n – 1. This factorization is: Listing 2—This is how a test Walsh-Hadamard Transform is calculated in the real world.[2] The first code is comprised of the rows of the binary Walsh-Hadamard matrix of order n left-most column (then this code has a length of n – 1 and comprises n code words). elseif( Binary_Sequence(i)==1 ) %--. 14 Issue 117 April 2000 WALSH-HADAMARD ENCODERS The goal of the encoder is to map a message sequence into a code word of n = 2m bits. Among the proposed algorithms. In addition.circuitcellar. but with 2n code words). The minimum distance (dmin) of a block code is the minimum Hamming distance between all distinct pairs of code words. The reader must remember that this code word is a row or a www. in order to pass from the real world to the world of binary. you can't find a right or left p-shifted version that also will be a code word.Converting 0 into +1 Vector=[ Vector 1 ]. So. the codes words are simply the rows of the binary Walsh-Hadamard matrix of order n and their complements. The second code is comprised of this first code along with the complements of the rows (then. you have m steps instead of 2m. in this article.com . and a real Hadamard matrix into a binary Hadamard matrix. I chose the one of reference [5] because it leads to the result by using a simple method. Listing 1 gives a short MATLAB function (FWHT_8(Input_Vec-tor_8)) written to calculate the naturally ordered Fast Walsh-Hadamard Transform of length 8 by using the matrix factorisation method described here. There are two other code definitions for Walsh-Hadamard codes. you have the transformation: +1—> 0 –1—> 1 n 2 Assuming code words have the same probability to be transmitted. encoders and decoders will work only with the n code words that are defined by the rows of the binary WalshHadamard matrix. In is a n × n identity matrix. WH2 is the matrix H2 of equation 2 and multiplied by the Kronecker product. for an input vector of length 2m. for i=1:length(Binary_Sequence) if ( Binary_Sequence(i)==0 ) %--.
1. end complement of a row in the binary Walsh-Hadamard matrix of order n = 2m. [6] The generator matrix for the first order Reed-Muller code R(1.…mm-1). m1. Reed-Muller codes and Walsh-Hadamard codes are related so the chosen code word c is: c = mm–1V1 + mm–2V2 + …m1Vm–1 + m0Vm [11] Therefore. for i=1: Number_rows for j=1: Number_columns if ( Hadamard_Matrix(i. You can verify that the index of this row is the decimal www. A message of length m will be encoded into a code word of length n = 2m.1. the result obtained by the above linear combination of the Vi vectors is a row in the binary WalshHadamard matrix of order n = 2m. for a message (m0. % initialization Number_rows = size(Hadamard_Matrix. m1.j)==+1 ) % Converting +1 into 0 Binary_Hadamard_Matrix(i.1). In the section Simulation Results.j)=1. only the main steps are given (note that ReedMuller codes are linear block codes).…mm-1) has to pass through an encoder. As is often the case.0. end.circuitcellar. m2. Another way to avoid the direct use of Reed-Muller generator matrix is to observe that the index (remember that indexes start from zero) of the chosen row has a binary or radix-2 form m0m1m2…mm–1. the index of the row to choose is the decimal form of m0m1m2…mm–1. 16 Issue 117 April 2000 CIRCUIT CELLAR® . the selected code word is (0. Consequently.0.1). This encoder use a first order Reed-Muller encoding algorithm. the encoder I used here will select only among the rows of the matrix.m). This method can be generalized to obtain a greater matrix generator for first order Reed-Muller codes R(1.0. elseif( Hadamard_Matrix(i. Because the goal here is not to study Reed-Muller codes. you can see that for a message (0.com 11111111 U G = 0 0 0 0 1 1 1 1 = V3 V2 00110011 V1 01010101 [10] The above Reed-Muller matrix is comprised of a vector U of 1s in its first row and the remaining rows are constructed so that they describe a digital counter from left to right. Among the algorithm used for a message of length m to select a Walsh-Hadamard code word of length n = 2m. end .j)=0. It is important to note that this affirmation is true in the case of a naturally ordered matrix. Number_columns = size(Hadamard_Matrix. function Binary_Hadamard_Matrix = BinHM ( Hadamard_Matrix ) %--------------------------------------------------% function : BinHM % Description : This function converts a Hadamard Matrix into a Binary Hadamard Matrix %--------------------------------------------------Binary_Hadamard_Matrix=ones(size( Hadamard_Matrix)).0. m2.Listing 3—A MATLAB function is to convert a Hadamard matrix into a binary Hadamard matrix. Listing 4 is a MATLAB program that implements a Walsh-Hadamard Encoder of length 8. the Reed-Muller encoding algorithm is commonly used to give an efficient and easy-to-implement technique.1.3) of length 8 = 23 is defined as: Considering a message (m0. end.1).j)==-1 ) % Converting -1 into 1 Binary_Hadamard_Matrix(i.2).
The MATLAB function hadamard(n) has been used for the creation of the naturally ordered Walsh-Hadamard matrix of order 8 (see the comments for more details). In the Simulation Results section. m(2)*Reed_Muller(3. %---xor(x. SIMULATION RESULTS This section gives some simulation results of the running of our MATLAB code and allows you to verify all of the theories I have covered.:).The Reed-Muller Generator Matrix Reed_Muller=[ 1 1 1 1 1 1 1 1 .1. 0 0 1 1 0 0 1 1 . 0 0 0 0 1 1 1 1 .0. we find that for each k.e.0.0) is the row having the index value 6 (6 is the decimal form of 110).3)Encoding Algorithm. %-------------------------------------------------------% Program : WH_Encoder_Length_8 % Description : This program implements a Walsh-Hadamard Encoder based on the first order Reed-Muller R(1. as described earlier.y) is the Exclusive OR Operator acting as the binary addition of x and y c=xor(xor(m(3)*Reed_Muller(4. 1). LIKELIHOOD DECODER IN MATLAB Listing 5 is a MATLAB implementation for the case of a code of length 8 (16 = 8 × 2 code words).0. meaning that the Hadamard Transform performs a correlation between the received sequence ( f(n)) and all possible code words inside the matrix. In brief. If this value is negative. a Maximum Likelihood Decoder is related to a correlation decoder. Under the assumption of equal probability of transmission. for a corrupted received sequence (1. the encoder selects one of the m rows of WH.1. 0 1 0 1 0 1 0 1 .:). the decoding that gives the closet code word in Hamming distance).:)). then its complement (addition with a sequence of 1s) is the maximum likelihood code word..0. For clar- Listing 4—The input message is taken from the user prompt and the code word is calculated by using the Reed-Muller Algorithm.circuitcellar.1. % Author : Kizito Tshilumba Kasengulu %-------------------------------------------------------clear m=input(Input the binary message (length 3) : ). The function FWHT_8(Input_Vector_8) computes the Fast Walsh-Hadamard Transform with natural order. %--. and puts the result in the vector FWHT_Vector.0.0. you can see that. m(1)*Reed_Muller(2. the right side of the equation is simply the correlation between the vectors f(n) and WH(k. In relation to what I said earlier.1).0.e. By observing equation 4. the maximum likelihood code word is the row in WH that corresponds to the greatest value in the Fast Walsh-Hadamard Transform vector. this row is simply the furthest code word. because the code word that minimizes the Hamming distance maximizes the correlation (assuming that this correlation is positive). MAXIMUM LIKELIHOOD DECODERS This article deals with hard decision decoding (i.0. So. In the same way. the maximum likelihood code word is (1. while the decoder outputs one of the 2m code words by using only the m rows of WH in its calculus.1. ]. the code word for the message (1. %---The encoder outputs a code word c of length 8.1).0..:)) 18 Issue 117 April 2000 CIRCUIT CELLAR® www. you now see that it's sufficient to compute correlations with only m code words (the m code words inside WH).form of 001 (i.com .
L. Résolution d'une Question Relative aux Determinants. Canada. IEEE Transactions on Acoustic.1.1.Received sequence (0. Fast Hadamard Transform Based on a Simple Matrix Factorization. ASSP-34. Signal Processing..Calculating the Maximum Likelihood Code Word if ( FHT_Vector(Coordinate) ) > 0 Maximum_Likelihood_Code_Word= Binary_Hadamard_Matrix_8(Coordinate.com CIRCUIT CELLAR® Issue 117 April 2000 19 . You may reach him at firstname.lastname@example.com. The decoder outputs the code word that is the most likely to have been transmitted.1) (1.0. pp. no.B.A. This decoder is designed for codes of length 8 and use Hard Decision.G. vol.0.Creating a Hadamard matrix of order 8 by calling the Matlab function hadamard(8) and converting it into a Binary Hadamard Matrix by using our function BinHM Binary_Hadamard_Matrix_8=BinHM( hadamard(8)).mathworks.J.0. May 1977. Table 1 shows some simulations for the encoder and Table 2 shows the results of decoder simulations.0.y) Maximum_Likelihood_Code_Word=xor( ones(1. END SIGNAL This article has proven that it is possible to derive non-cyclic linear block codes from Walsh-Hadamard matrix.Calculating the greatest magnitude in FWHT_Vector and retaining its coordinate [Greatest. (508) 647-7000 Fax: (508) 647-7001 www. In spite of the fact that the MATLAB programming was limited to n = 8 and m = 3. Table 2—As a result of noise. vol. %--. %--. the received sequence is a corrupted version of the transmitted one.J.1.0. [5] M. % Author : Kizito Tshilumba Kasengulu %-------------------------------------------------------clear Received_Sequence=input(Input the received sequence (length 8) : ) %---Converting the Received_Sequence ( 1s (+1s or -1s) in using our function Conv Received_Vector=Conv(Received_Sequence) . pp. the decoding of a sequence and its complement agree with the theory Listing 5—This decoder takes the received sequence (from the point of view of the decoder) from a user prompt. 55.8).1.Sum of the two vectors by using xor(x. Corinthios. Simulations with the MATLAB programs allow you to observe the working of encoders and decoders. REFERENCES [1] J.0.1.0. Wicker. "A Closed Set of Orthogonal Functions". %---Performing the naturally ordered Fast form of the Received_Vector of length 8 FWHT_8 ( see listing 3 ) FWHT_Vector = FWHT_8( Received_Vector ).0.1. I Kizito Tshilumba Kasengulu is a TDMA software engineer at NSI Communications in Montreal.1) (1. 5–24. Walsh.A.1.0. or 0s ) into a Vector (see listing 4) Walsh-Hadamard Transby using our function %--.circuitcellar.1.248.1)* (1. 17. [2] F.0.:) else %--. January 1923. NJ.1. pp. vol. Math.0. and Sequency Order Algorithms and Processors for the WalshHadamard Transform. 1995.1. 6. It's also possible to verify the characteristics of the code mentioned in the text. Dyadic. IEEE Transactions on Computers.0.0.0.0. %------------------------------------------------------% Program : WH_Decoder_Length_8 % Description : This program implements a Walsh-Hadamard Maximum Likelihood Decoder based on a naturally ordered Fast WalshHadamard Transform. Natural. Am J.0. 1666–1667.0.CIRCUITCELLAR.1.1)* (0. vol.Coordinate]=max( abs(FWHT_Vector )). they can be generalized for any values of n and m with n = 2m. Kaveh. 1986. It outputs the code word that is the closest in Hamming distance. Hadamard.0.0)* Maximum likelihood code word (0. ity.J.1. 1977.0)* because the outputs are complementary (illustrated by the asterisks in Table 2). 1893.0. [6] S.COM FOR DETAILS www.com HAVE YOU HEARD??? CIRCUIT CELLAR ONLINE IS COMING TO CD-ROM! WATCH WWW.0. 240.:)) end .0. I chose to present simulations for the encoder and the decoder separately.1.1. The derivation lead to codes with length n = 2m and 2n code words. Prentice Hall. Lee and M. Bulletin on Science and Mathematics. pp. So. The Theory of Error Correcting Codes.0.0.1. Englewood Cliffs. [4] J.1.1. Error Control Systems for Digital Communications and Storage.0. C-26.H.0. MacWilliams and N.1. SOURCE MATLAB The MathWorks.1.1) (0. Speech. Geadeh and M.Binary_Hadamard_Matrix_8( Coordinate. Amsterdam.0. [3] Y.1. 435–442. North-Holland.1.0) (1.com. Inc. Sloane.
and direct memory access (DMA). first consider how the pipeline behaves in both good and bad times. This is a data hazard. Now. and execute instruction IPC-4. This month. and overflow outputs from the datapath. 116) showed the CTRL16 control unit schematic symbol in context. Memory accesses are in boldface. What happens when an instruction uses the result of the preceding instruction? I 1: I 2: andi r1. the instruction is decoded. because next month. and result multiplexer output enables. load/store instructions. and its operands are read from the register file or extracted from an immediate field in the IR. ALU controls. decode instruction IPC-2. In the EX stage. captures the resulting instruction word in the instruction register IR. it reads memory at the current PC address. Jan introduced his plan to build a pipelined 16bit RISC processor and System-on-aChip in an FPGA. negative. Table 1 shows a normal pipelined execution of four instructions. These outputs include pipeline control clock enables. assume no memory wait states. 20 Issue 117 April 2000 CIRCUIT CELLAR® www. Figure 2 in Part 1 (Circuit Cellar. The control unit outputs manage the datapath. That's the simple case. and the zero. EX1 computes r1=r1&7. The assembler can reorder instructions or insert nops to avoid the problem.1 Referring to time t3 of Table 1. fetch instruction IPC. However. Consider executing a series of instructions. You simultaneously prepare the next instruction address PC+2. memory wait states.circuitcellar. the control unit can detect the hazard and stall the pipeline one cycle. I discussed the instruction set and the datapath of an xr16 16-bit RISC processor. I'll explain how the control unit pushes the datapath's buttons. jumps and branches. One result is driven through three-state buffers onto the result bus and is written back into the register file as the cycle ends. and there are several ways to address it. he'll tie it all together. ast month. PIPELINED EXECUTION To increase instruction throughput.Building a RISC System in an FPGA FEATURE ARTICLE Jan Gray Part 2: Pipeline and Control Unit Design In Part 1. these techniques hurt performance. interrupts. fetch a new instruction and write back its result two cycles later. In the DC stage. he explores the CPU pipeline and designs the control unit. register and operand selectors.r1. the function units act upon the operands. In every pipeline cycle. the xr16 has a three-stage pipeline—instruction fetch (IF). Listen up. the next instruction word INSN15:0 from memory. but there are several pipeline complications to consider— data hazards. decode and operand fetch (DC). EX2 incorrectly adds 1 to this stale r1. while DC2 fetches the old value of r1. In t4.com . Before designing the control circuitry. and incret1 IF1 t2 DC1 IF2 t3 EX1 DC2 IF3 t4 EX2 DC3 IF4 t5 EX3 DC4 Table 1—Here the processor fetches instruction I1 at time t1 and computes its result in t3. Inputs include the RDY signal from the memory controller. and execute (EX). In the IF stage. while I2 starts in t2 and ends in t4. in order to write-back the result to the register file before fetching it as a source register. carry. Or.7 addi r2. l ments PC for the next cycle.
and the pipeline stalls until RDY is asserted in t4. I: L I: 2 I: 3 I: B I: 5 stalled another cycle to wait for EXL access to complete. These instructions in the branch shadow (and their side effects) must be annulled. In particular. In t3. you must jump to the interrupt handler. jal r0. BRANCHING OUT Next. Each causes pipeline headaches.. Execution continues at instruction IT. FWD passes AREG to the A operand register. so the pipeline registers do not clock. You must stall the pipeline to squeeze in this access. had RDY not been asserted during t4.-1 bne T lw r6. load/store memory accesses may have to wait on slow memory. CTRL deasserts all pipeline register clock enables PCE. the processor executes either an instruction fetch memory cycle. causing pipeline havoc (see Table 3). In each memory cycle. jal r14.6(r10) . memory is not ready during the fetch of instruction I3 in t3. you must annul the EX5 stage of I5. it captures I3 in NEXTIR. ACE. In t4 you must run a load data access instead of an instruction fetch. Repeated pipeline stages are italicized. This return address is obtained from the datapath's RET register. and then in t4. you must not latch it into the instruction register (IR) as t3 ends. t1 IF1 t2 DC1 IF2 t3 EX1 DC2 IF3 t4 t5 EX2 DC3 IF4 EX1 DC2 IF3 Table 2—During t3. So. if (in t3) you don't save the just-fetched I3 somewhere. and so t4 repeats t3. IR is loaded from NEXTIR instead of from the memory port (which is busy with the load). (Repeated pipe stages are italicized. and later return to the interrupted instruction. the xr16 only forwards results to the A operand—a speed/area tradeoff. you'll lose it. which is unacceptable. because the I5 load is annulled. what happens when memory is not ready? The simplest thing to do is to stop the pipeline for that cycle. In Table 2. For example. Issue 117 April 2000 21 . Memory transactions are pipelined. Then. The www.r6. the memory port is busy with the load cycle. The assembler handles any rare port B data hazards by swapping A and B operands. because neither EXL nor DC2 are finished at this point. and assuming the branch is taken at t7.circuitcellar. if ((p->flags & 7) == 1) p->x = p->y. in any given clock cycle.com pipeline registers do not clock. To fix this problem. . but when the control unit detects the hazard (DC source register equals EX destination register). When INTREQ is asserted. As with instruction fetch accesses. because in t4. retire the current pipeline. also known as register file bypass. When the handler has completed.yes: load r6 with p->y Instead.e. Most memory accesses are for fetching instructions. Unlike most pipelined CPUs. and a video refresh DMA cycle occurs once every eight clocks or so. it executes iret. with the result that even a nowait load requires three cycles. that is. the processor drives the next memory cycle's address and control signals and awaits RDY. Most of the time. (i.0(r14)) and exection resumes with the interrupted instruction.load r6 with p->flags . T9 is not an EX5 load cycle. a DMA memory cycle. which holds the address of the instruction in the DC pipeline stage.) IL in Listing 1 is a load word instruction..is (p->flags & 7) . if possible. the control unit has a 16-bit NEXTIR register and an IR source multiplexer (IRMUX). you'll have to re-fetch it no sooner than t5.==1? . execute the handler. If you lose it. or inserting nops if not. preserve the interrupt return address. Jumps also save the return address in the destination register. and this extends all pipeline stages by one cycle.7 addi r0. the instruction fetch memory access of I3 is not RDY. a 16-bit 2-1 multiplexer (mux) of AREG (register file port A). Continuing the Table 3 example from time t5. NEXTIR ensures a two-cycle load or store. because I2 uses r6—the result of IL! Finally. at a cost of eight CLBs. By the time you execute the jump or taken branch IJ during EXJ (updating PC). consider the effect of jumps (call and jal) and taken branches. Because you always annul the two branch shadow instructions. The processor is also the DMA engine. and the DC6 and EX6 stages of I6. indicating the access has been completed. and so forth. This jumps to the interrupt handler at 0x0010 and leaves the return address in r14. The datapath DC stage includes FWD.Listing 1—This C code produces assembly code that includes a load IL and a branch IB. you simply override the fetched instruction with int. Therefore. you do result forwarding. it asserts its FWD output signal. (Annulled stages are struck through). you'll have decoded IJ+1 and fetched IJ+2. MEMORY ACCESSES The processor has a single memory port for reading instructions and loading and storing data. or a load/store memory cycle. lw r6. DC2 must await the load result in order to forward it to A. and the A register receives the I1 result just in time for EX2 in t4. the pipeline would have CIRCUIT CELLAR® INTERRUPTS When an interrupt request occurs. jumps and taken branches take three cycles. and the result bus. which is reserved for this purpose. Loads and stores need a second memory access. although you fetched I3 in t3.10(r0) via the IRMUX.2(r10) andi r6.
t9. If a branch or jump memory cycle. Annulled instructions are struck through.com . you interrupt is deferred. you are ready to design the control unit. or if a taken After an instruction is fetched. They are best done by collaboration with an on-chip interrupt conThere are two pipeline issues here. I2. If an interlocked DMA engine.circuitcellar. DMA word (AN ← PC1 += 2) per lest it be annulled. ^ 22 Issue 117 April 2000 CIRCUIT CELLAR® www. The fixed-pinout era need not be branch IB executed in t7 causes I5 and I6 to be annulled in t8 and hardwired into our FPGA CPU. troller and the interrupt handler First. but saves 16 CLBs (otherwise necessary for a separate 16bit DMA address counter and a 16-bit 2-1 address mux). These artifacts of the t4 you stall the pipeline for the IL load/store memory cycle. add. Each memory access cycle requires one or more clock cycles. Each pipeline cycle requires up to three memory access cycles (mandatory instruction fetch. the annulled I5 and I6. and execute pipeline stages. you can fetch either interrupt is deferred one cycle. shift. the a PC register file. if branch or jump is in the EX stage. Using a 16 × 16 RAM as instruction is in the DC stage. CONTROL UNIT DESIGN Now that you understand the pipeline. IF5 DC5 EX5 You might be wondering IF6 DC6 EX6 IFT DCT about the interrupt priorities. the nested interrupts. or imm followed by The PC/address unit doubles as a another instruction).The simplicity of the process pays off once again. you must not interrupt an software. During vectors. It consists of the memory cycle FSM (see Figure 4). plus instruction annulment and pending request registers. the DMAREQ has been asserted. I3. It's a nice example of a problem-specific optimization you can build with a customizable processor. the int must not be inserted in a branch or jump shadow. t1 t2 t3 t4 t5 t6 t7 t8 t9 a) IF LSP DMAP IF DMAN DMAP RDY CLK DMA FDCE D Q LSP CE C CLR LSN DMAN This PC register file costs eight CLBs for the RAM. (For more information on RISC pipelines. interlocked instruction sequence (any The last pipeline issue is DMA. Table 3—Pipelined execution of the load instruction IL. is in the DC stage. To recap. operand fetch and decode. and optional EX stage load or store). sub. non-maskable interrupts. The FSM outputs are derived from the machines current and next states. and interrupt branch IB. The time to take an interrupt IFL DCL EXL EXL IF2 DC2 DC2 EX2 and then return from a null IF3 IF3 DC3 EX3 interrupt handler is only six IFB DCB EXB cycles. optional DMA. see Computer Organization and Design: The Hardware/ b) FSM outputs RDY BUF RDY IFN IFN DMAN RDY OR2 RDY IFN DCINT RETCE ACE PCE Mem cycle state machine IF DMAP LSP DMA LSP IF DMA IF FDPE IFN RDY CLK LS EXLDST EXANNUL LSP PRE D Q CE C ^ ^ PCCE Annul state machine RESET BRANCH JUMP DCAN PCE CLK Pending requests DMAREQ DMA CLK DCANNUL FDPE PRE D CE Q DCANNUL BRANCH JUMP PCE CLK RESET EXAN EXANNUL FDPE PRE Q D CE C INIT=S ZEROP FJKC DMAP ZERODMA DMA CLK J K C CLR EXANNUL LSN EXLBSB WORDN C INIT=S DMAP FJKC J K C CLR ^ ^ ^ LSN EXST READN Q Q ZEROP DMAN ZERO LSN BUF DBUSN ^ DMAN INTP FJKC IREQ IFINT PCE CLK J K C Q CLR DMAPC BUF IFINT INTP BRANCH JUMP DCINTINH PCE CLK DCINT FDCE D Q CE C CLR DCINT IFN JUMP DMAN Zero Reset SELPC ZEROPC ^ RESET FDPE GND RDY CLK PRE D Q CE C INIT= S RESET Figure 1—This control unit finite state machine schematic implements the symbol CTRLFSM in Figure 2. each instruction takes three pipeline cycles to move through the instruction fetch. an instruction (AN ← PC0 += 2) or a Secondly. and shaves a couple of nanoseconds from the system's critical path. insert one DMA memory cycle. and the branch target IT.
DECODE decodes IR to derive internal control signals. including the CPU finite state machine. They suppress any effects of INSN[15:0] IF CLK NEXTIR FD16CE NIR[15:0] D[15:0] Q[15:0] CE IF C CLR IFINT Instruction registers IR EXIR EXIRB FD16CE IRMUX EXOP[3:0]. In the IF stage. In the EX stage.com . they select which register to write. In the first half clock cycle.RA[3:0]. ri format DC: call EX: all but call EX: call • • • • Nsig: not signal—signal inverted DCsig: a DC stage signal EXsig: an EX stage signal sigN: signal in "next cycle"—input to a flip-flop whose output is sig • sigCE: flip-flop clock enable • sigT: active low 3-state buffer output enable memory access. Let's consider each part of the control finite state machine (see Figure 1). and instruction decoder. Then as the pipeline advances. DC. and drives FWD and IMM5:0 to select the A and B operands. and EX) of the control unit (see Figure 2) pipeline. CTRL determines if it is taken. Some control unit signal names have prefixes and suffixes to recognize their function or context (most signal names sans prefix are DC stage signals): Each instruction flows through the three stages (IF. Instructions enter on INSN15:0 and are latched in IR and decoded. CTRL drives ALU and result mux controls.EXRD[3:0]. While CLK is high. based upon the instruction in the EX stage. they select which registers to read. when the instruction fetch read completes. In the DC stage. The control FSM has three states: • IF: current memory access is an instruction fetch cycle • DMA: current access is a DMA cycle • LS: current access is a load/store Figure 4 shows the state transition diagram. ^ 24 Issue 117 April 2000 CIRCUIT CELLAR® www. Software Interface. based upon register fields of the instruction in the DC stage. While CLK is low. it inserts a DCANNUL and EXANNUL are set after executing a jump or taken branch. If the instruction is a load/store. CTRLFSM also has several other bits of state: • • • • • DCANNUL: annul DC stage EXANNUL: annul EX stage DCINT: int in DC stage DMAP: DMA transfer pending INTP: interrupt pending RNB RB RD EXRD 15 When DC: add sub. instruction register pipline.BRDISP[7:0] FD16CE IR[15:0] EXIR[15:0] IRMUX[15:0] A[15:0] O[15:0] I[15:0] O[15:0] D[15:0] Q[15:0] D[15:0] Q[15:0] B[15:0] BRDISP[7:0] PCE CE PCE CE SEL BUF16 C CLR CLK C CLR CLK INT IRMUX Instruction decoder DECODE OP[3:0] RRRI FN[3:0] IMM12 IMM4 SEXTIMM4 WORDIMM4 ADDSUB SUB ST CALL NSUM NLOGIC NLW NLD NLB NSR NSL NJAL BR ADCSBC NSUB DCINTINH ^ ^ ^ Control state machine FSM IREQ DCINTINH IREQ DCINTINH PCE ACE WORDN READN EXLDST DBUSN EXLBSB IF EXST IFINT BRANCH DMA JUMP EXAN EXANNUL SELPC ZERODMA ZEROPC DMAREQ DMAPC RDY PCCE CLK RETCE CTRLFSM PCE OP[3:0] ACE IR[7:4] WORDN READN DBUSN IF IFINT DMA EXAN EXANNUL SELPC ZEROPC DMAPC PCCE RETCE IRB OP[3:0]. all rr fmt DC: sw sb EX: all but call EX: call Table 4—RNA and RNB control the A and B ports of the register file. the new instruction at INSN15:0 is latched into IR.RB[3:0] I[15:0] O[15:0] RRRI BUF16 IMM_12 IMMB IMM_4 SEXTIMM4 I[15:0] O[15:0] WORDIMM4 IR[11:0] BUF16 ADDSUB SUB ST CALL NSUM NLOGIC NLW NLD NLB NSR NSL NJAL BR ADCSBC NSUB DCINTINH EXLDST EXLBSB EXST BRANCH JUMP IMM[11:0] ZERODMA DMAREQ RDY CLK ^ EXOP[3:0] EXOP[3:0] PCE PCE CLK CLK EXNSUB EXFNSRA EXIMM EXLDST EXLBSB EXRESULTS EXJALI EXJAL EXNSUB EXFNSRA EXIMM EXLDST EXLBSB EXRESULTS EXCALL EXJAL Figure 2—This control unit schematic implements half of the symbol CTRL16 in last month's Figure 2. by Patterson and Hennessy. In the last half cycle. The FSM clocks when one memory transaction completes and another begins (on RDY).RD[3:0]. some important naming conventions. RNA and RNB both drive the destination register number to store the result into the register file.) [1] First. CTRL drives RNA3:0 and RNB3:0 with the source registers to read. the instruction passes into EXIR.RNA RA RD 0 EXRD 15 When DC: add sub addi lw lb sw sb jal DC: all rr.circuitcellar. If the instruction is a branch.
com CIRCUIT CELLAR® Issue 117 April 2000 25 . the CPU is ter file write-back and load/store always eager to start another SUMT add sub addi SUM15:0 memory accesses. IF is then asserted The control FSM also takes care of with PCE. Most 0xAE01 • READN: next memory cycle is a datapath registers are enabled by PCE. • WORDN: next cycle is 16-bit data— pending. address of the interrupted in• IF: asserted in an instruction struction rather than the instrucfetch memory cycle tion after that. It inhibits clocking of RET for one cycle. but its results are outputs. PCE isn't asserted. and IRMUX selects the and the above control outputs are managing the memory interface via INSN15:0 input as the next instruction all valid. Otherwise. the instruction ory isn't ready. that the int picks up the return clocking The instruction determines which enable is asserted and which function unit drives RESULT15:0. Internal to the control SLT slli A14:0 || 0 not retired to the register file.10(r0) = from the memory controller) PCE. read transaction—true except for It indicates that all pipe stages are If a DMA or load/store access is stores ready and the pipeline can advance. IF enables NEXTIR to capPCE is asserted when RDY signals ture the previously fetched instructrue except for byte loads/stores completion of the last memory cycle tion (take a look back at time t3 in • DBUSN: next cycle is a load/store. adc sbc adci sbci LOGICT and or xor andn LOGIC15:0 nulled add still fetches and adds There are no IF stage control andi ori xori andni its operands. so start a new memory the following signals: transaction in the next clock cycle. three signals control IF SRT srli srai SRI || A15:1 DCINT is set in the pipeline stage resources. address AN15:0 (a datapath output) the pipe stage. the pipeline clock enable. www. to complete. • RDY: memory cycle complete (input • IFINT: force the next instruction to The highest fan-out control signal is be int = jal r14. so • PCE: enable IR and EXIR Table 5—Here's a look at the result multiplexer output enable controls. including regismemory is ready.circuitcellar. an anmemory transaction. in the current pipeline cycle. because if Enable Instruction Source branch shadow. So. unit. Those three ZXT lb 015:8 RETADT jal call RETAD15:0 cycle following the insertion of signals are: none sw sb br* imm — the int instruction. and • ACE (address clock enable): the next fetch is the only memory access in the pipeline stalls for one cycle. So.the two instructions in the ACE equals RDY. If memand it needs the on-chip data bus Table 3).
sub. The register file control signals. BUF LOGICOP1 EXIR5 RNB BUF trol signals. and V named OP3:0 and so NSR D1 Q1 SRT IMMOP2 IMM_4 NSL D2 Q2 SLT BUF (overflow)." the new instruction instruction is a branch.C. the imm RD[3:0] RD[3:0] FWD RRRI SELRD FWD EXRESULTS control the register prefix establishes B15:4. overriding With CLK high.C. and IMM_4. immediate operand control. • CI: carry-in. the BRANCH The muxes RNA and RNB produce xr16 has a simple instruction set. LOGICOP1:0 is simply EXIR5:4 or store) for annulled instructions. imm. turning to RB[3:0] RA[3:0] RNB[3:0] RN[3:0] RD[3:0] RD[3:0] FWD "N.. SEXTIMM4. I discussed IMMED. ST. and control output is asserted.C. IMM_12.B3:0 is clock enabled DC: operand selection Execute stag e on PCE. r0 + imm12<<4. It must decode stage instruction is CLK C RA[3:0] RA[3:0] RN[3:0] RNA[3:0] CLR the new instruction. CALL SELR0 EXANNUL EXRD[3:0] EXRD[3:0] RZERO file.C. and if the branch handful of flip-flops. CTRL drives RNA and the DC stage source register A • ADD: set unless the instruction is (detected within RNA). • SRI: shift right input—0 for srli ^ ^ ^ DECODE STAGE 26 Issue 117 April 2000 CIRCUIT CELLAR® www. and a BRANCH N DMAPC N EXAN CE PCE C CO so. Call shared by both the DC and EX stages. is irregular. The instruction must be LOGICT RLOC=R2C1 NLOGIC D1 Q1 "N. "N. but B15:4 uses The greater part EXRESULTS CI PCE RFWE FDCE of the control unit B15_4CE. SRI EXFNSRA ST SRI SELRD A15 register IR latches if the DC stage GND SELR0 EXRD[3:0] EXRD[3:0] RZERO "N. unless the EX RNB with the EX stage destination sub or sbc stage instruction is annulled or its register number. directs PCINCR to take the branch by the FPGA's 4 LUTs. on (the tools optiIMM_4 IMMOP3 NJAL D3 Q3 RETARDT BUF IMM_12 IMMOP4 Late in the DC mize away these PCE CE BUF CLK CLK IR0 stage. EXCALL SELR15 CLK SELSRC word as the DC then the EX stage T1 SUMT RNMUX4 NSUM D0 Q0 stage begins. and CLK. CTRL asserts FWD when the and RNB with the DC stage outputs are: EX stage destination register equals instruction's source register numbers. or addi." NLD D3 Q3 IMMB break out the which drives the PCE CE IMMOP[5:0] IR3 CLK CLK instruction fields control unit's IMMOP0 SEXTIMM4 IMM_12 FD4PE OP. and upon the decoder outputs WORDIMM. CTRL drives RNA controls. as selected by decode outputs RRRI. xor. It is a set of DC:conditional branches BRANCH TRUE true with respect to 30 ROM 16x1s. and prepare instruction provides RNMUX4 RLOC=R2C0 LOGICOP0 EXIR4 most EX stage conB3:0 only. as shown in Table 4. The logic including register file. Now. as the decoded signal. result mux. destination is r0. there is a result to write back. or IMMOP5:0 controls IMMED. N (negative). the A and B and the subsequent RZERO AND3B1 EXNSUB ADD EXCALL SELR15 BUF operand multiimmediate operand CLK SELSRC LOGICOP[1:0] plexers. It computes r15 = pc.circuitcellar.e." NLW D2 Q2 buffers IRB and add. the branch instruction compact because enters the EX stage. B15_4CE is NSUB EXANNUL ADCSBC D Q CI RZERO operates in the DC PCE. the OP3:0 or EXOP3:0 and BRANCH flip-flop is outputs some Figure 3—The remainder of the control unit schematic implements the DC stage operand selection set. adding 2×disp8 to the PC. IMMOP5 WORDMM4 FD4PE evaluates whether or The instruction INIT= S PCE EXIMM BCE15_4 EXANNUL EXJAL not the branch decoder DECODE is JUMP EXANNUL condition COND is simple. RNB3:0: port B register number. false for instructions. gate FDCE TRUE BRN Z TRUE Z BR D Q the condition inputs. The ALU and shift control AREG. This its 4-bit opcodes are a good match for RNA3:0 and RNB3:0.com . the TRUE macro buffers). ALU. and address unit be forwarded into A. based no result (immediate prefix. 0 for add and 1 for sub. or." The instruction conditional branches. andn. C CLK V V instruction is not Each ROM inputs IR[11:8] COND[3:0] CLR TRUTH annulled. unless the EX CO CE PCE RNA stage. (i. and Now. branch logic. RD. and the registers r15 THE EXECUTE STAGE and r0 are implicit. and result mux pipeline advances and decoder is relatively controls. Therefore. CALL. and so condition inputs Z INIT= S IMMOP1 IR0 T2 forth—IR15:12 is re(zero). WORDIMM4 NLB D0 Q0 ZXT CO (carry-out). Thus. pc = are RNA3:0: port A register number. It is XOR in the previous carry-out the BREG/immediate operand mux. EX stage copy of FN1:0) for destination r0. If expressions. RFWE is asserted with PCE when unless it's adc or sbc where we Last month. EXCALL. branch. which produces • LOGICOP1:0: select and. With CLK low. let's discuss the EX stage The FWD signal causes RESULT to RFWE: register file write enable. EX stage ALU.
otherwise PC0 (PC) Depending on the next memory cycle and the current EX stage instruction. and links to related sites. SRT. and A15 for srai (shift right arithmetic) slxi and srxi (shift extended left/ right for multi-word shift support) are not yet implemented. I Jan Gray is a software developer whose products include a leading C++ compiler. The instruction determines which enable to assert and thus determines which function unit drives the RESULT bus. Be my guest! The result mux control outputs SUMT. SXT. P Figure 4—Each memory cycle is an instruction fetch unless there is a DMA transfer pending or the EX stage instruction is a load or store. Hennessy. San Mateo. including specifications. as shown in Table 5. LOGICT. 1994. source code. CIRCUIT CELLAR® Issue 117 April 2000 27 . next address is PCNEXT15:0.org.Next cycle IF IF branch IF jal call IFreset LS load/store DMA DMA reset Next address AN ← PC0 += 2 AN ← PC0 += 2×disp8 AN ← PC0 = SUM AN ← PC0 = 0 AN ← SUM AN ← PC1 += 2 AN ← PC1 = 0 Outputs SELPC PCCE BRANCH SELPC PCCE PCCE SELPC ZEROPC PCCE — SELPC DMAPC PCCE SELPC ZEROPC DMAPC PCCE Table 6—Here's a look at the result multiplexer output enable controls. SLT.circuitcellar. add 2×disp8 to PC. You may reach him at jan@fpgacpu. WRAP-UP This month. Morgan Kaufmann. the system drives RESULT7:0 with the byte load result. He has been building FPGA processors and systems since 1994. The FSM clocks when one memory transaction completes and another begins (on RDY). schematics. otherwise SUM15:0 • ZEROPC: if set. next address is 0 • PCCE (PC clock enable): update PCi • DMAPC: if set. *DMA P SP ×L *LSP DMA IF *D M DMA P LSP SOFTWARE Visit the Circuit Cellar web site for more information. As you'll see next month. ZXT zeroes RESULT15:8 during lb. CA. the control unit selects the next address by asserting certain combinations of control outputs (see Table 6). we considered pipelined processor design issues and explored the detailed implementation of our xr16 control unit—and lived! The CPU design is complete. Computer Organization and Design: The Hardware/Software Interface. otherwise add +2 • SELPC: if set. and he now designs for Gray Research LLC. The following outputs control the address unit: • BRANCH: if set.com A ×L SP LS DMAP: DMA pending LSP: load/store pending REFERENCE [1] D. all EX stage function units produce results. The final article in this series tackles the design of this System-on-a-Chip. One asserted T enables its unit's 3-state buffers to drive the RESULT bus. Patterson and J. fetch and update PC1 (DMA address). and RETADT are active low RESULT bus 3-state output enables. Each cycle. www.
The Shocking Truth about EMC FEATURE ARTICLE George Novacek Part 1: Design for Compatibility Designing for electromagnetic compatibility shouldn't just be an afterthought. pagers. this approach no longer works. I'll concentrate on the principles.circuitcellar. military and aerospace organizations demand that their design teams prepare a formal document. In this article. which are probably less demanding (e. With the greater sophistication of simple appliances. They often feel they have no time to waste on this obscure (and secretly feared) discipline.. can you afford not to spend a few days planning? Just the cost of an EMC test lab will run you in the range of $1500 per day. methods. smaller size. aerospace insists on 200 V/m immunity. Aerospace engineers have seen their requirements skyrocket while designers of communications and commercial electronics. if you wait until EMC causes a problem.com 28 Issue 117 April 2000 . The quest for better performance. the problems would go away. CIRCUIT CELLAR® t I'll discuss some fundamental principles of designing electronic equipment in compliance with the regulatory requirements. Unfortunately. especially those in the European countries. we generate a huge amount of electromagnetic garbage. Even if no government certification is required. you need to form a plan of attack. lower cost. However. he tremendous growth in electromagnetic compatibility (EMC) importance has affected all of us. It would be impractical and outside the scope of this article to write a cookbook to satisfy every conceivable situation. been viewed as black magic. Rather. And. all of which seems to choke and confuse every electronic device within its reach. quite often they did. but commercial equipment rarely encounters more than 20 V/m). and their application to critical level aerospace requirements as reflected in the DO160D or MIL-STD-461D standards. Many designers shy away from EMC issues and underestimate the importance of a plan. we increasingly rely on flawless performance of electronics. There is no need for a commercial designer or an enthusiast to go to such lengths.g. At the early stages of projects. I'll look at taking control of and taming the EMC beast. Designers shied away from it. Listen up and save yourself the trouble. it's a matter of professional pride. At the very least. If you consider the cost of redesigning to fix EMC problems after they become problems. you either become proactive in controlling the EMC. it is our duty as engineers to make sure our products work under adverse conditions. Once you define it. at this point. As George shows us. usually called EMC Control Plan. Electromagnetic compatibility has. have had dozens of stringent new requirements imposed on them. every designer should understand as a minimum: • definition of the EMC requirements (customer's and/or regulatory) www. or you allow the EMC to control you. It's up to you to transpose these principles to your design environments. you just might find yourself doing quite a bit of redesigning. Those interested in deeper technical details can consult the references. hoping that by copying previous successful designs. and ever-escalating computer clock speeds leading the pack. Yet. With the profusion of cellular phones. and shorter time to market forces designers to understand the problems before they can find the remedy. for many years. FIRST THINGS FIRST The first step in destroying its black-magic reputation. is to treat EMC as any other design problem.
gradually reducing with frequency to 0. So. but if an analysis is the only way. shielding. producing a 30-A/m magnetic field at 400 Hz.com • the controller is not upset by power interruptions up to 1 s long • supply voltage may vary between 18 and 32. you must decide early in the process how you will prove to the customer and the certifying agencies that you have satisfied their requirements. Magnetic effect is a requirement for equipment that generates a magnetic field that could potentially affect other equipment. grounding.2 VRMS and sloping down at –40 dB per decade • common mode interference is induced in the external interconnect wires and harnesses through a coil wrapped around them. Our internal power supply circuit must ensure that: 20 log(I/E) -100 -120 -140 -160 L=100m -40 -60 -80 -100 10m 1m 29 . you need to provide magnetic shielding of the offending components. Even though you may be well acquainted with the standard. will be addressed here—the ESD protection and the power supply performance. and dropouts to 12 VDC for 30 ms CIRCUIT CELLAR® ZS =100 ZL =1000 10k 100k 1M 10M 100M 1G 10G Frequency (Hz) Figure 2—To find the voltage or current level induced into a wire in an E-M field. • the interconnect wires are exposed to an e-field of 1800 V/m between 380 Hz and 400 Hz Figure 1—Wires connected to a load form a loop. With power supply considerations. 1kHz–15kHz at 1. on top of the 28-VDC power don't upset the system Every electronic instrument is potentially susceptible to interference. Otherwise. It's not uncommon to call category Z per DO-160D.2VRMS. susceptibility to interference. filtering. Finally. Let's assume power is supplied from a standard 28-VDC avionic power bus. Nothing works better than tests to prove your point. Typically. their regulatory references. You can easily imagine the time and frustration it may take to reach a consensus of engineering opinions when presenting a similarity or a rationale report. S ep B H d B v et H • the supply voltage dropping below the minimum 18 VDC for any period of time at any rate of change does not cause the system to lock up • 50 transients of 600 V and 2 µs duration. of each polarity and applied within 1 min. and lightning-induced susceptibility. although not strictly EMC but closely related. all references to interconnect wires and bundles mean external wiring unless noted otherwise. if for no other reason than as a reminder of the design goal. In this article. Some characteristics may have to be proven by analysis or by similarity. whose transmission gain is proportional to its area formed by S (length) times H (the distance between the wires). your team members may not be.[1] www. The electrical regulatory and operational requirements can be subdivided into five groups—magnetic effect. you will have to make sure the controller's operation is not upset when: • a ripple of the frequency and amplitude range is superimposed on the 28-VDC supply lines: 10Hz–200Hz at 0. and 15kHz–150kHz starting at 0.5 VRMS.2 VDC • the system withstands transients of 80 VDC for 100 ms. -180 0. 200Hz–1kHz at 0. power supply considerations. This often overlooked detail can cause a lot of grief at the end.55 VRMS. Issue 117 April 2000 20 log (V/E) Let's say you're about to design an embedded controller for a closed-loop position-control system that satisfies DO-160D standard.• analysis and method of satisfying the previous requirements • method of formal verification of compliance. run a vertical line from the abscissa at the frequency of interest until it intersects with the curve appropriate for the length of the wire. RF emissions. and specific objectives with supporting data for the designer.8 A/m at 15 kHz. you define the characteristics of the external power feeding the controller to make sure it will continue working under all conditions. It's generally not a problem with low-power microcontroller systems.1m -200 -220 -240 -120 -140 -160 -180 THE PLAN OF ATTACK Defining the plan needs to be nothing more than a simple matrix summarizing the design goals. if needed The informal plan may be merely a couple of pages to list and address the issues. it's a good idea to spell out what must be achieved. two additional subjects. it's important to keep the customer and the agency advised and obtain their agreement with your verification plans well before you go past the point of no return. A horizontal line through that point will show the induced voltage or current on the ordinate. 48 VDC spikes for 1 s. many small loops result with two adjacent ones being always out-of-phase and therefore cancelling each other's effects. By twisting the wires. such as a compass. and other methods to improve system immunity and keep emissions under control. The definition of the EMC requirements is usually issued by the customer and given as a reference to an applicable regulatory requirement or a standard. Here you also define system interfaces. And. It is your responsibility to design the controller so it will not be affected by interference. packaging. Reference [3] shows diagrams for different impedance combinations. The second section of the plan addresses the requirements specifically and how you plan to meet them through circuit design.circuitcellar.
1 1.circuitcellar.01 0. you have enough to worry about. The high frequency ferred to as susceptibilsignals are filtered before reaching the clean cavity by feed-through filters installed in the filter plate. ity) is divided into CIRCUIT CELLAR® several areas—High Intensity Radio Frequency (HIRF) susceptibility.000 µs long. We must consider the ability of the equipment to function without upset or damage through a wide range of the power supply voltage. we need to touch on the theory of electromagnetic interference. 1020–1100 MHz. The pins. audio frequency susceptibility (which in effect is a ripple superimposed on the power lines). From the EMC standpoint. 50 to 1. but let's assume DO-160D category M is applicable. and 750V/ 2000A. The most common sources of interference Dirty Cavity Clean cavity would be switching F1 R1 R3 Pin 1 power supplies and Electronic circuits digital circuits. emissions from all the other interconnecting 30 Issue 117 April 2000 Like the famous bunny rabbit. Not only is it your responsibility to ensure flawless operation in the midst of interfering signals. the equipment will generate signals that may interfere with other equipment. Susceptibility can be radiated or conducted through the wire interfaces. Here. you need to consider damage tolerance (will the equipment survive a lightning strike or an ESD discharge?) and functional upset (will the equipment continue to operate properly when exposed to a strong efield?). EMP and ESD will be automatically taken care of. Critical equipment must keep operating correctly no matter what. with this maximum allowed level sloping at –20 dB per decade to 2 MHz and not exceeding 20 dB/mA from 2–30 MHz • using the same method. the dirty cavity. The shape and timing of the pulses are also defined in DO-160D. 750V/ 150A. 1500V/300A. The EMC requirements fall into two major groups—emissions and immunity. the interface cable bundle of the operating controller is injected with test pulses of 750V/1500A.com . and 1525–1680 MHz • a common mode burst of spikes of 600 Vp-p spaced at 0. full e-field exists there.0 MHz 10 100 Figure 3—In a filter connector.2 to 10 µs. With emissions. and electromagnetic pulse (EMP) susceptibility. The system can shut down (provided it's done in a safe. you are also expected to minimize EMI pollution. includR2 R4 Tranzorbs Pin 2 ing clock generators. Less critical equipment may be allowed to stop operating during exposure to an interference. are surrounded by a dielectric and a ground plate to create distributed capacitance. When it comes to the effects on the equipment. Believe me. Also. In practical terms. This is a tall order. The attenuation shown in the plot to the right of the connector cross-section is usually limited to –60 dB due to impedance mismatch. but it must automatically recover. and power transients. as long as it does not perform a forbidden action and recovers after the exposure has ended. wires do not exceed the 28-VDC power line limits. it's important that there be no functional upset when. There are different standards and different categories within those standards. as well as a continuous. as in the previous bullet. carrying ferrite beads making them appear like inductors. the criticality of the application determines the proper behavior. decreasing at –20 dB per decade from 500 kHz–10 kHz is injected into the interconnect wires through a current transformer • the system with all its components is exposed to a modulated. using a current transformer. The authorities will want to be satisfied that: • when running the equipment's 28VDC power lines through a current probe. GND GP1 The interference travels C1 F2 C2 Spark T1 T2 from the unit by air gap Filter plate (radiated emissions) and by wires through power lines and interfaces Figure 4—A typical two-cavity design has transient protection devices in (conducted emissions). www. Electrostatic discharge (ESD) is another concern. there are no signals up to 150 kHz exceeding 53 dB/mA. predictable manner). which serves merely as a housing for environmental protecImmunity (also retion. it means that there is no damage to the controller when every interface and power connection is injected with 1500V/60A. The maximum emissions are allowed to increase from 25 MHz to 6 GHz at +20 dBµV/m. by more than 20 dB/µA • radiated emissions (received by an appropriate antenna) do not exceed 35 µV/m from 2–25 MHz. pins act as low-pass π filters. Before we delve into the practical activities of taming the EMC beast. is injected into the interconnect wires through a coil wrapped around the wire bundle • 200 V/m field from 500 kHz to 400 MHz. as defined in DO-160D.(dB) 100 60 20 0. interruptions. but if you have to design equipment to survive HIRF and indirect lightning effects. and 750V/750A waveforms of up to 120 µs. A separate set of design constraints is set up to addresses the power supply. indirect lightning effects. with –10 dB notches at 100–150 MHz. wave e-field of 200 V/m from 100 kHz–18 GHz • electrostatic discharge of the test pulse to the cabinet does not damage or upset the system operation RF emissions are quickly growing in importance. our controller is expected to keep going and going without a hiccup when exposed to a Level 4 lightning strike. between switching power supplies and digital circuits' clocks.
Such sources of radiation are customarily divided into two basic types—a small magnetic and a small electric dipole (small. will usually predominate. The pair generates a magnetic field: H = I×d2 2π ×R assuming d<<R. you not only reduce the area of the loop. which has high impedance input. uses one wire connection and the return through the chassis. The same circuit driving a TTL gate. the parallel wire run (loop) is proportional to the area of that loop if both S (wire length) and d (wire separation) are much smaller than the wavelength l. the currents at any points on the wire can be considered in-phase—a condition generally referred to as a short antenna. In practical terms. the dominant signal is voltage. it will be limited to about 1. the loops are no longer 180° out of phase. or 400 Hz current generating electric and magnetic fields. We can rewrite that equation as: Ep ∝ S × d If you twist the two wires. To maximize the effect of twisted wires. The voltage induced in. The magnetic field at low frequency will be: a result of the twist. HIGH FREQUENCY WIRES When the wire can no longer be considered short compared to the wavelength. 60 Hz. One type of field. There's another way to look at it (see Figure 1). or a field emitted from. 60 dB. All loop pairs' voltages will cancel out as they are out of phase as www. and no other path is involved). The typical examples are power leads with DC. In other words. the effect of coaxial cable should be mentioned. the d in this case is double the distance from the ground. As the frequency increases. Such a system behaves as if there was a mirror image of the second wire below the ground plane. especially in the automotive industry. An example would be a PCB trace connecting logic gates. Although the current I and the distance from the wires R are design constraints.LOW FREQUENCY WIRES The electromagnetic energy gets in and out of the electronic circuits through the radiation (antenna) properties of conductors. where the current flows down one and returns through the other. It also needs to be reiterated that twisting has little effect on electric fields—these must be suppressed by shielding. they must form a balanced pair (i. The theoretical reduction of EMI is: ep et = N where N represents the number of twists. If the wire length is less than 10% of the wavelength λ. we can minimize the distance between the wires d to the insulation thickness and thus minimize the stray magnetic field. with d being represented by the eccentricity of the conductor within the shield. but you also cause only one loop to be active..000 (60 dB) for frequencies up to 100 kHz.circuitcellar. magnetic (current) or electric (voltage). It can be viewed as a wire pair. H = I 2πR where I represents the current and R is the distance from the wire. and eventually. attenuation can be approached up to the maximum frequency between 100 kHz and 2 MHz. the twisting effect will be lost. At this point. it becomes a more efficient radiator. the other is the return. in this case. two wires close to each other are used. one carries the current. Then the induced voltage is: e = A dB dt where A is the loop area and B represents magnetic flux density.com CIRCUIT CELLAR® Issue 117 April 2000 33 . The maximum. which has low impedance. creates a loop with predominantly current signal and the resulting magnetic emission. referring to the size of the dipole compared to the wavelength λ). producing dominant electric field. With a CMOS gate. Another common approach. Often.e.
but in my view –60 dB is. by using twisted and shielded wire pairs for all interfaces. Commonly. The connector pins are in fact miniature. Whether it is a standalone package or one that works together with a dirty cavity. those connector-to-PCB wires act like antennas. and L the distance between the dipole elements. as shown in Figure 3. gigahertz frequencies. look for the worst-case scenario and design for it. and resonance in the enclosure at high megahertz and. This brings the interfering signal right into the cabinet. even with built-in clamping devices to limit the transients. which is our example design requirement. Cable shielding effectiveness of –40 to –60 dB can be achieved. for designs where power transients and lightning strike effects far exceed the 50 WVDC rating of the pin's distributed capacitor. but not at all satisfactory at 200 V/m. Consequently. but their selection is limited and their cost is prohibitive for most applications. V the voltage. The filter pins provide effective attenuation of the interfering signal. where A represents the area of the loop and I the current through the dipole. the shielding could get damaged. you can assume that by properly shielding the wiring and using the above scenario. as a result of the impedance mismatch. The interconnect cable may be more than 5 cm (2″) above ground. once their induced level reaches about 400 mV. you want some design margin. affecting the operation. The easiest way to establish the levels is to use graphs like the one in Figure 2. Thus. Connectors rated for higher operating voltage. maintaining EMI integrity (as shown on the right side) will make the difference between a successful design and a failure. transient protection devices (which I address later) are in immediate vicinity of the connector pins. you can determine that the loop can pick up about 80 mV of interference. semiconductor junction's nonlinearity may effectively demodulate the interfering signal. bringing the induced voltage to 10 VRMS. followed by low-pass filters. are available.5″ above ground will result in a 60-dB correction. is characterized by I × A. a correction factor of 26 dB (also published in [3]. what does all this mean in practical terms? To simplify your analysis. The common mode rejection ratio (CMRR) usually Issue 117 April 2000 35 . When exposed to an e-field of 200 V/m intensity. In a typical system. Let's assume the maximum length of the interconnecting cables in our system is 3 m (about 10 ft). as well as electrically induced signals. where C represents the capacitance between the leads. This is often acceptable at lower e-field levels. invalidating its shielding effect. Because the interfering signals are often modulated. You can achieve the same results with the magnetically induced interference. you must conservatively assume the full e-field appears inside the cabinet as a result of the radiation from the incoming wiring. the waveguide effect of the apertures. Your main concern is that the efficiency of dipoles increases with the frequency. no loop larger than 1 cm2 is formed by the signal and its return. falling off at a rate of –20 dB per decade below 30 MHz. often π configuration. and that chassis grounding of filters retains its low impedance even at the highest frequencies. certainly. filter connectors present an excellent option.circuitcellar. invalidating the shielding effectiveness of the cabinet at high frequencies. You still need to low-pass filter the incoming signal. the maximum you can practically expect.[3] Assuming the cable will never run more than 5 cm above the ground (chassis). bringing the voltage picked up to 500 VRMS. in a graph form) must be applied. there will be about 0. The major disadvantage of the filter connectors is that the dielectric strength of the material forming the capacitor between the pin and the shell (ground) is often limited to 50 VDC operating voltage. we also assume that we have a good PCB design with SMT components. especially when it is way outside the operating bandwidth of the embedded controller. The cables will be connected to the peripherals with internal resistance Zs = 100 W and terminated inside the controller with 1000 W.Each type of dipole produces both fields. the maximum www. DESIGN ANALYSIS So. and the result may fall within the operating spectrum. the same attenuation can be achieved for the magnetically induced/radiated interference. You can appreciate how important cable routing is and how much the picked-up interference grows when the cables hang in the air! Just moving the cable 4. but the electric dipole is characterized by C × V × L. as we have seen previously. Symmetrical inputs will not be completely immune to this interference either. low-pass filters with attenuation. In the worst-case scenario. you bring the connections from the interface connector(s) to the PCB. This makes the filter connector unsuitable CIRCUIT CELLAR® Unshielded lead-in Shielded lead-in Lines Unshielded Lines improperty filtered Lines shielded Line property filtered Ventilation waveguide Unprotected panel meter hole Nonconductive control shaft in waveguide Hole screening Seam with no gasket Seam with EMI gasket Figure 5—Common mistakes (shown on the left side) will degrade shielding properties to nothing. But. In situations where lightning strike or a high voltage pulse is not a concern. The magnetic dipole. Unfortunately. where they feed directly into low-pass filters. on the other hand.com interfering voltages will be somewhere around 100-mV RMS. Based on the above assumptions and using the same type of graphs as shown in Figure 2. reaching maximum at: 4 That puts most of your interface cables into the category of efficient radiators in the frequency range of 20– 200 MHz—the band tightly controlled by all regulatory agencies.5 VRMS induced on the cables above 30 MHz. or some other unexpected occurrence may happen. Although 100 mV may not seem like much.
interface of data acquisition ICs The solution to this problem is running at a 60-kHz bit rate. most emissions. Usuinterference to get in and out of the design of specific interface circuits in ally. 20-Ω resistors that limit the trate on the susceptibility first. Using spread spectrum packaging principles as shown in of the filters today start cutting off at oscillators is one of the few options Figure 5. this arrangement can handle Level 4 It's easy to become a little complaFortunately. EMC immunity Pushing the communications fretain the signal amplitudes within safe and emission control issues can be quency above 1 MHz would have been limits. The filters also prorequire you to beef up the packaging. is not always true. a control is also a little more forgiving it. transzorbs. They are followed by we really don't know what kind of Because our exceedance was no more R3C1 and R4C2 low-pass filters. EMC standards provide lightning effects. The transzorbs in and bite you. leaving you with monics up to 1 MHz. so minor emismaximum current through the cause it is defined in numbers. 36 Issue 117 April 2000 ¨ CIRCUIT CELLAR® www. troduce fairly large trace lengths we expected smooth sailing. Resistors R1 and R2 problem arises. leaving about cations as in our design example 4 mV of interference in differenwas undergoing qualification tial mode. using feed-through lowlooked at as mirror images of each too radical a change to implement and pass filters. Then. bring the interbe squeezed into a smaller envefaces through connectors to the Figure 6—Spread-spectrum oscillator is a new technology. the feed-through π filters a wire. like The problem arose in the final the arrangement shown in Frequency Span ¨ version when the design had to Figure 4. To use filters trically clean cavity. The problem is that and passing all the tests. as well provide high-frequency attenuation of ware routine will compensate for as the containment of the internally about –60 dB up to the highest freinadequate EMC protection that algenerated fields. If you follow the fundamental for smaller and smaller devices. to the control of the EMI pickup and available at critical frequencies as low On the other hand. besusceptibility levels. Changing the typical input lines.For example. I'll take a closer therefore. or a softthe circuits inside the cabinet. we can significantly reduce unwanted emisthrough filters resulted in their transzorbs. if you've taken good care of re-certify in time. we failed to deliver spark gap GP1 may have to be added. First. pensive to implement in later stages. to emission our equipment will generthan 4 dB above the allowed emission provide contact debouncing and bandate. By lope than originally intended. you should strive to packchokes and R3. cabinet is through the peripherals and next month's article. see next month. a minor circuitry fix. We tend to concenallowed emissions and the minimum are small. or some unexno way these could be squeezed into transient protection and filtering of pected emission problem will pop up the existing envelope. a flight controldeteriorates to about –26 dB as a ler with the same EMC specifiresult of tolerances. Investiga800-mV common mode and 40tion revealed that the problem mV differential mode interference was related to the internalSPI to deal with.com . can then be reduced quencies. than the emissions. Only devices in a multistage configuration UNDER CONTROL two options existed. but the fact is. critical frequency being pushed ers. electrically dirty cavity. as we'll susceptibility problems that don't age equipment in a well-designed. When I discuss the that can be easily implemented. A 20-dB inthen emission testing showed an crease in the calculated pickup is excess at 60 kHz and its harreasonable. with lower critical frequency was Figure 4 illustrates the concept of however. but with the push simple circuit fixes that can reduce cables. This. You still equally impractical because there was the dual-cavity design and depicts need to be careful. and/or R1 and R2 replaced with There are workarounds for some Ideally. its impact on the through the metal wall into the electhe immunity. narrow band.circuitcellar. expected performance. there are few emissions through the wires and as a few kilohertz. For larger currents. Once transient protection devices inthe immunity was completed. where spreading the signal spectrum as opposed to concentrating it in a The small size of the feedyou clamp the transients. MOVs. Sometimes a ferrite bead threaded on effects of the external energy fields on Finally. or a combination of these from 10 kHz to about 1 MHz. complicated and often extheir wire interfaces. look at protecting interface circuits. shielded cabinet. the only way remaining for about 1 MHz. taken care of automatically. you feed the signal other and. (addressed in detail in Part 2) to mainIn many respects. while sion excesses can be often accepted. to use a dual-cavity design. envelope was out of the question. Bringing the immunity under level. Feed-through filters are lowed interference inside the cabinet. The control of the vide ESD protection. using precise.R4 omitted. But and current loops. spark arrestsions without the need for shielding. the customer was able to accept width limiting. as required for the cent about EMC emissions until a a hefty margin between the maximum example system. emissions should be budget notwithstanding. the fix is largely mechanical and.
especially for high speed. the major contributors to PCB emissions are VLSI digital circuits. metal cabinet with feed-through filters. But. you must follow the same philosophy with the internal design. When combined with the need to operate in high-energy fields (HIRF). such as microprocessors and FPGAs (field programmable gate arrays). • use decoupling capacitors as close to the ICs as possible. As Figure 2 shows. You can design PCBs with solid ground planes on the outside and place them in a metal frame to effectively behave like a solid metal box. There are several fundamental rules worthy a reminder: • provide ample ground and power planes on separate layers. Increasingly. the classic two-cavity. efficient shielding. As you have seen. Follow one-point grounding rules. Avoid current loops. This is achieved www. • don't allow analog and digital grounds and power planes to overlap to prevent capacitive coupling between them. and such interference can be easily rejected by digital circuits. keeping connections short and close to the ground plane.circuitcellar. metal cabinet design remains the only choice. reduces the interference levels to millivolts. Using the IC packages with internal heat sink shows a significant reduction in emissions when grounded in multiple points. The principle. Instead of having all the energy concentrated in a narrow bandwidth around one discrete frequency. by sweeping the freCIRCUIT CELLAR® Issue 117 April 2000 GENERAL CONSIDERATIONS The one area greatly affecting the ultimate EMC performance is the PCB layout. In high-volume production. Use of the spread spectrum clock to reduce the circuit emissions is gaining popularity.com 37 . I have concentrated largely on what can be called a classic EMC design—a two-cavity. PCB layout. Up to now. continuous pressure for small lowcost and lightweight designs makes the classic approach often impractical. Present-day multilayer boards combined with surface mount (SMT) components afford excellent EMC performance. (A situation almost inherent to the contemporary designs with SMT components and multilayer PCBs. used in communications for some time. the interference the circuits pick up is a function of their physical size.Just as you want to make sure minimum energy couples to the external wiring. • keep traces short. The EMC performance of the PCB can be significantly improved with on-board shielding. There's little use in heavy filtering an I/O line to kill externally conducted interference if it picks up the internal system clock through radiation. demanding designs one is well advised to subcontract such layouts to a professional. while properly shielding external interfaces. and so on. It is interesting to note that grounding the heat sink in one point only shows an 8-dB penalty. is a discipline in its own right. and for sophisticated. Significant emission reduction can be achieved by judicious assignment of ground and low-speed FPGA connections on ball grid and super ball grid array (BGA and SBGA) packages to the perimeter and the highspeed signals to the inner balls. including ground loops. Capacitors that fit underneath the chip are ideal. efficient metal shields suitable for SMT pick and place machines at a low cost. a metallic coated plastic enclosure is often used.) Sensitive analog circuits (or our own interference emitters) can be shielded separately by small "sardine can" covers. Many standard shields exist and can be purchased in small quantities for development or low-volume production. Recent advances in technology result in the availability of extremely light. by keeping traces (antennas) short and shielded from radiated fields by good ground planes. Successful control of EMC depends on good overall design from the cabinet through the PCB layout to the electrical circuits and software. is quite simple. It is the lightning strike transient protection that introduces physically large connections prone to the interference pick up and radiation.
are next to impossible. West Conshohocken. Lightning Protection of Aircraft. Therefore. I'll look specifically at how to design grounding. Electromagnetic Compatibility by Design. Let's say you have several functional blocks. the connector itself (which may have filter pins) should be soldered directly into the board. each operating from and emitting the same clock frequency.C. Consider the worst-case scenarios. offset by. while the cost of their implementation increases exponentially. increasing by 6 dB for each additional emitter. Prices of EMC test equipment are becoming accessible to smaller companies. White and M. [6] F. Lightning Technologies Inc. metal cabinet. [5] EMI Control.A.7%. Inc. if sound engineering design is used throughout. That means the filters should be right where the wire enters the board. clock generators. Pittsfield. which relies on several discrete clocks offset by a small frequency. On each PCB put a reverse parallel diode combination between the digital and analog grounds. VA. A. primary analog circuits. www. and sensitive. The overall emission will be the sum of the module emissions. Plumer. the world's largest manufacturer of landing-gear systems. • use spread spectrum and/or multiple discrete clocks. while maintaining expected timing accuracy.. and low-pass filters to limit the frequency spectrum reaching the electronics." Circuit Cellar Online. D.. Depending on the test results. It will make life easier. PA. Hartal. it is in your best interest to invest relatively little time at the beginning and make sure you understand the design requirements related to the EMC and know how to implement the necessary steps to control them. • proper grounding is absolutely crucial. You may reach him at gnovacek@nexicom. such as Cypress. • avoid clock frequencies below the critical frequency of the interface filters. This results in the emission reduction by about –8 dB—sufficient in many cases to meet the FCC requirements without any additional shielding. • even with the luxury of dual cavity packaging. the larger the sweep. REFERENCES [1] G. and cabinets (among other things). and achieve even greater reduction. the greater the emission reduction will be. whether generated by or their effects on complex circuits and PCBs. Washington. keep the tracks short. maintain the shortest CIRCUIT CELLAR® possible connections between the connector pins and the I/O filters on the PCB. FPGAs.net. MA. It sweeps the clock frequency ±1. 10 kHz (such as 20 MHz. If wires have to be used they should be shielded if longer than approximately 1″. you could also sweep each of these frequencies. Make sure there are no current loops. a division of MessierDowty International.J. • use SMT components as much as possible. dual cavity design. Don White Consultants Inc. you can take steps to minimize the risk of a future failure: • if possible. Obviously. Connect all the grounds at a single point. and do not skimp on decoupling capacitors. . Ideally. As you progress in the design. Novacek. and its importance cannot be overstated.) will result in a fourmodule design having the emissions –18 dB below the same unit with the same clock frequency for all modules.circuitcellar. 01 MHz. Mardiguian. This approach. [4] Cypress Semiconductor Corp. 20. Peak Reducing EMI Solutions. D. especially when the environmental requirements are taken into consideration.. power supply and distribution. say. so confidence testing can be done early in the design to mitigate the risk. I George Novacek has 30 years of experience in circuit design and embedded controllers. "Testing 1. 38 Issue 117 April 2000 . A clock generator chip with the sweep function can be purchased from several manufacturers. but the penalty is timing accuracy. The frequency deviation is a compromise providing sufficient reduction to satisfy certification authorities.com IN SHORT… How do you design electronics for electromagnetic compatibility? Exact calculations of radiated fields. Using a separate clock for each module. use a metal enclosure. FCC. was introduced by Lexmark. life is too short and quantities too low to even consider designing without a good. Fisher and J. • use filter connectors. • for military or aerospace applications. The objections to the swept clock timing inaccuracy can be alleviated by a similar method. • use multilayer boards with good ground planes.quency. European) without exotic packaging. He is currently the general manager of Messier-Dowty Electronics. R&B Enterprises. In addition. RTCA. • ground heat sinks at multiple points and make a provision to use shielding over microprocessors. you widen the bandwidth and reduce the amplitude of the emissions proportionately. etc. options left to you to correct potential EMC problems decrease dramatically.R. then rely on sound engineering practice and experience. the shields may be omitted from the final assembly. Gainesville. illustrated in Figure 6. Commercial equipment can often satisfy certification requirements (UL. even without access to the test equipment during the design process. But. In Part 2. [3] O. [2] DO-160D. Interference Control Technologies. which is easier than adding them after the fact. An added benefit of this method is that the diagnostics can be designed to pinpoint a system problem by identifying it through its specific clock frequency. Methodology & Procedures. THE WAY FORWARD I've discussed the impact of aspects of the EMC on design of electronic systems in general. inputs and outputs. W181. except the one that is timing critical.2.
Both are compatible with the CompactPCl specification of the PCI Industrial Computer Manufacturers' Group (PICMG). to further simplify installation. Ziatech Corporation (805) 541-0488 Fax: (805) 541-5088 www. Seal/O includes a utility for configuring the driver parameters under Windows 95/98 and Windows NT.com CIRCUIT CELLAR® Issue 117 April 2000 39 . Seal/O provides a consistent and straightforward API (Application Programmer Interface) to facilitate application development. and the ZT 6311 for $360.3 VDC. Both power supplies feature hot swap and load sharing capability.ziatech. Visual Basic.com www. The KT-101 sells for $49. and overtemperature protection is provided for both units along with built-in EMI filtering. The Seal/O suite of Windows 95/98/NT drivers is included with the card. The Kit consists of a basic 6' M/F cable and positive tension screw terminal block. The isolated inputs provide protection to connected equipment. The ZT 6301 power supply features a universal input voltage range from 90 to 254VAC at 47 to 63 Hz with power factor correction. Available in both AC and DC input models. and meet UL. Seal/O VB. a 32-b Visual Basic sample with GUI (Graphical User Interface). a Windows 95/98/NT Console application (32 bit).PCI sells for $259. Supported development environments include Visual C++. short circuit. allows control of individual and groups of relays and timed relay activation. TUV. Edited by Harv Weiner The ZT 6301 Power Supply sells for $342. is included to allow the user to exercise the inputs and relays.com DIGITAL I/O INTERFACE The DIO-16. switches. CSA. Applications include PC based control and automation of equipment including sensors. redundant.sealevel. Sealevel Systems. and other low-current devices supporting on/off control. Seal/O TST. and Delphi. The ZT 6311 power supply accepts an input voltage range from 36 to 72VDC. Inc (864) 843-4343 Fax: (864) 843-3067 www. video and audio studio automation. Both units provide four outputs that are capable of providing a total of 150 W for 3. status LEDs. Overvoltage. enabling their use in mission-critical applications that require total availability. and the reed relay outputs allow PC control of lights. 5 VDC and ±12 VDC with independent output regulation. IEC. buzzers.NOUVEAUPC REDUNDANT POWER SUPPLY Ziatech Corporation has introduced two reliable. switches. and main output remote sense. The KT-101 Terminal Block Kit is available to provide a simple means of connecting field wiring to the card. motors. and CE certification standards. Source code for Seal/O TST is also included to facilitate software development.circuitcellar. and modular switching power supplies for CompactPCI computers.PCI is a digital I/O interface card that provides eight optically isolated inputs and eight reed relay outputs. The DIO-16. satellite antenna control systems. the two new power supplies provide 150 W of power in a rugged 3U format that plugs directly into a CompactPCI backplane. All of the card's outputs are through a DB-37 connector. and security control systems.
It comes fully equipped with Innovative's rapid application development (RAD) software. various converter configurations.4-MBps throughput. Chico may also be linked directly to Innovative's compatible DSP cards through an 80-MBps FlFO port. with no data collisions. greatly reducing development time and cost. The result is a network that communicates data within a few microseconds rather than many milliseconds. sample rates up to 40 MHz/channel. Data acquisition packages such as LabView can also be used. A proprietary SyncLink timing hitch provides accurate inter-board triggering for up to 16 Chico boards in large data acquisition systems. dequeue.com Innovative Integration (818) 865-6150 Fax: (818) 879-1770 www. Currently interfaces are available in the PCI short card form factor. and S/N ratios as high as 100 dB. no additional software is required to make the network operate as a real-time link. comparable to standard IP-based networks. with far more predictability. but with lower application-to-application latencies and greater network determinism. resolutions up to 18-b. two 24-b timers. The add-on OMNIBUS I/O modules range from $845 to $1645. SCRAMNet SC78 boards provide 3. These I/O modules connect to the Chico card and provide up to 16 channels. Chico has a real-time event-driven data streaming engine. SC78 series boards are supplied with intuitive API software. Systran Corporation (937) 252-5601 Fax: (937) 258-2729 www. D/As. The card handles bi-directional data streams through the PCI bus while controlling A/Ds. transmit. The SCRAMNet Network is based upon a replicated-shared memory concept. There are no bulky IP drivers to write. featuring 1 MB of onboard shared memory and an embedded fiber optic media interface. No real-time drivers are needed. Armada is an entirely new way to develop sophisticated. SC78 networks incur node latencies. and digital I/O completely independent from the Host CPU and can sustain gap-free data acquisition. the network updates all other nodes on the network automatically.com 40 Issue 117 April 2000 CIRCUIT CELLAR® www. Once all network nodes are properly configured. timers. Chico uses the OMNIBUS I/O module family of products to achieve a variety of analog and digital I/O combinations. The card does not require complex programming to achieve real-time performance. Chico sells for $395.com .NOUVEAUPC REAL-TIME NETWORKING SYSTEM The SCRAMNet+ SC78 series is a deterministic real-time alternative to Ethernet networks. Armada. DATA ACQUISITION BOARDS Chico is a Bus Mastering PCI card that is designed for high-performance data acquisition. When any NIC makes changes to its local copy of shared memory.circuitcellar. real-time data acquisition and control application programs under Win 9x/NT using high-level C++ software components. but they are designed with a new hardware architecture that supports a single fiber optic connection over distances up to 300 m. measured in nanoseconds rather than milliseconds. hardware-accelerated. and unpack messages because network communication is controlled at the hardware level.systran. It features 32 b of digital I/O. where each network interface card (NIC) stores its own copy of the network's shared memory set.innovative-dsp. which automatically streams data between the PCI bus and add-on I/O modules. queue. making the network simple to install and easy to program. SC78 Series NICs are based on proven SCRAMNet+ technology. and a proprietary Synclink for multicard synchronization. and there are no time-consuming software routines needed to pack.
Atlas also comes equipped with AMI's BIOS and onboard diagnostics software and status LED's. For applications requiring high performance at a reduced cost.com www. Inc (909) 980-4863 Fax: (909) 987-4863 www. the board provides up to 340-MB SanDisk 1.solutions-cubed. and a parallel port.circuitcellar. Atlas-C runs a variety of popular desktop and realtime operating systems. a pair of USB ports. enabling its two Coppermine processors to work together on the same program.gms4vme.com CIRCUIT CELLAR® Issue 117 April 2000 41 . Each processor is equipped with 256 KB of no-waitstate on-die L2 Cache. scaleable to 500 MHz.5" 9GB IDE drive. Atlas-C is also available with a single 466MHz Celeron PPG37O processor. The Celeron processor includes 128 KB of on-die cache with a one-to-one clocking.com Solutions Cubed (530) 891-8045 phone www. Solaris x86. General Micro Systems. QNX. dual serial I/0 with optional RS-422 drivers.5" Flash IDE on the rear panel. I/O and networking options include dual 10/100-MBps Ethernet interfaces (twisted pair). a 40-MBps UltraWide SCSI interface. Pricing for Atlas-C starts at $2299 less processor and memory. It provides built-in support for symmetric and real-time asymmetric multiprocessing.mm rear panel connector.NOUVEAUPC MULTIPROCESSOR COMPACTPCI BOARD The Atlas-C is a multiprocessor CompactPCI board based on the Intel Coppermine-256 Processor and features clock speeds up to 733 MHz. Also available are two Ultra-DMA 33 IDE interfaces. including Windows NT. For applications that must be deployed without a rotating hard disk. and VxWorks. and a 64-b AGP graphics engine with four MB of video RAM optimized for 3D rendering. I/O is available via a 80. which can accommodate a 2. The two processors also share up to 1 GB of 100-MHz synchronous DRAM main memory.
Ingo discovered that a POST card would make the task easier. and it just dies before the screen even comes up? My spare laptop board really fits into this category. because it lets the system boot with potentially bad hardware. keyboard controller. is not being able to find the keyboard device or the floppy. The last option is pretty risky. various DMA and timer functions. When one of the POST routines discovers an error. it will boot up into BIOS. the board broke several months ago. especially if the card was PC/104 compatible…. A common error. you have a pile of old boards that you are not sure whether they work or not. it typically displays an error message (if the display has been initialized) and waits for the user to clear the error condition and reboot the machine. Although. regular PC motherboards. One of my New Year's resolutions was to go through my pile of boards and save what works and salvage what doesn't. initialize the keyboard. and disabling the floppy will prevent the POST from halting when it doesn't find one. look for extension BIOS. the CMOS battery-backed SRAM.circuitcellar. The BIOS on embedded computers also allows you to control the behavior on test failure. In many embedded systems. During this test. When a PC or embedded PC works right. and some notebook main logic boards (motherboards). f you work with PCs as much as I do. there may not be a standard screen because the computer doesn't even have a display adapter.POST It EPC REAL-TIME PCs Ingo Cyliax Build a Power-On Self Test Card for PC/104 then proceed to boot from one of the boot devices that are available.com . 42 Issue 117 April 2000 CIRCUIT CELLAR® www. Well. Sometimes. I have PC/104 CPU modules. what do you do if the problem prevents the computer from making it that far. This is a series of tests and confidence tests the BIOS performs while exploring the system's hardware and looking for devices. OK. the display adapter. as well as ignore errors. One of the laptop boards I use as a backup for my everyday laptop. initialize any VGA or graphic adapters it might find. you have probably run across one or two of them that actually does work right. These types of errors are usually easy to clear. What makes matters worse. But. it will check things like the BIOS ROM check sum. What do you do then? GET POWERED UP Common PC BIOSs have a poweron self test (POST). the system memory. for example. Some BIOSs allow you to bypass the keyboard test. Setting out to weed through an evergrowing pile of "spare" boards and resurrect his backup laptop motherboard. you can drop into a hardware debugger or tell it to automatically reboot. and whatever boot devices it may find. if you're like me. and i Photo 1—The ISAbus adapter board allows me to plug my PC/104-based POST board into an ISAbus-based system.
PC/104 uses the standard ISA bus protocol. A PC/104 card uses stackable. not wanting to waste my time with a one-off solution. the code is displayed and can be looked up in a list of POST error codes. PROJECT Because I have this pile of motherboards and I really want to get my spare laptop motherboard working again. There also is a 330-Ω current limit resistor on each LED. You can use whatever gates you have to implement the decoder function. a cleaner implementation would decode 16 bits of addresses. we're embedded systems guys. For a fancy implementation. and the addressed peripheral places the data to read on the data bus. we can handle doing the conversion in our heads. or the last POST routine that tried to run before the system hung up.com A POST board is a write. You can use standard 74xx technology parts to implement this. In many cases. this will help you quickly find the error. Some products even provide a diagnostic floppy that does a more thorough test of the system than the POST. Figure 1 shows the POST board that I put together. what do you do if the system boots and halts before initializing the display adapter? Or. My laptop doesn't have an ISA bus or a PC/104 bus. any 8-bit register would work. If you want. The register is at address 0x0080 of the PC I/O space. The processor places the addresses on the bus. most BIOSs have a method of dealing with this. you can use some black marker and mark out the two middle LEDs. the memory read strobe (MEMR) and I/O read strobe (IOR) are asserted. it's fairly easy to build bus adapters for PC/104 cards. dualrow headers/sockets. the memory write strobe (MEMW) or I/O write strobe (IOW) is asserted. it also places the data to write on the data bus. you might use a couple of hex-to-sevensegment decoders and drive two seven-segment registers. The register is a 74HCT374. The basic ISA bus protocol. www. I decided to build the POST card on a PC/104-compatible card. This makes sense if you are testing PC/104 systems. although. although. To write to memory or I/O. SD0–7. All that is necessary to implement the decoder are the signals A0–9. and PC/104-to-ISA bus adapters are available. When a valid address and a write strobe are on the bus. Even a PAL (22v10) will work well. things get a bit more complicated when doing 16-bit transfers and DMA. The output of the POST register is displayed on a 10-segment LED array using the outer two banks of four LEDs. You can also use 'LS technology. The content of the register is displayed with LEDs. and IOW. I put the LED array on a rightIssue 117 April 2000 43 . The peripheral latches the data. so you don't need to worry about it at this point. Because the PC/104 bus connector is essentially a dualrow header. The last POST code captured will indicate the routine that encountered an error. However. The combination of gates I chose in this project should be available at most electronic part outlets. only the first 10 address lines (A0–A9) are necessary to decode the POST register. you'll need to have enough functionality in your system to be able to boot from a floppy disk. When the POST writes to the register. This makes it easy to decode the upper and lower nibble of the hex code. but they are getting CIRCUIT CELLAR® harder to find these days. Typically. Of course. They write special POST codes representing the different phases in the POST to a hardware register in the I/O space. You then look up the code in a list to decode them. 'HCT is more common and performs just as well in this application. Also.circuitcellar. the output of the NAND gate acts as the clock to store the state of the lower 8-bit data bus. It's an 8-bit register that latches the data from the data bus whenever the host writes to the I/O address 0x80. The idea is that you can capture these codes as the POST progresses and when the system stops on an error. However. which I can solder or clip to the motherboard. or the one you have is not compatible with the BIOS and relies on high-level routines in the application to initialize it? Well. but POST only uses 8bit transfers. a couple of 8-bit comparators would work well. I can build a special test cable setup that plugs into a PC/104 module and brings the signals out on wires.But. When doing a write. because the speed and power consumption are not critical for this application. The address decode is implemented using several two-input NOR gates (74HCT02) and an eightinput NAND gate (74HCT30). is simplicity in itself.only register. There are ISA bus-based POST cards that will capture these codes and display them on an LED display. which allow you to plug a PC/104 module into an ISA bus-based motherboard. It's a write only register and should not interfere with other registers in the address range above 0x3ff. I decided to build a simple POST card. But hey. perhaps you don't have one. Figure 1—Here is what makes the POST board tick. During a read. even when used on a PC/104 card.
It just won't have the socket on top. In a pinch. and then you'll be in business. there is still a lot of real estate left on that PC/104 module. I still have to hunt down some of the ISA bus signals on the board and add some solder on the test points to the board. you'd be surprised what you can find. and SD0–7. I wasn't able to debug my laptop motherboard by the time this article was due. Or. There's not much to it. but that's only half the battle. I included a source for PC/104 connectors in the Sources section. you need to find the POST error codes that match the particular BIOS that are being used on the CPU board. Find A0–9. If you're using a CPU module that is specifically sold to the embedded PC market. I tried to boot it both with and without VGA cards and removed the system memory to check the codes. But. What do the codes mean? For this. Luckily. IOW. The only hard-to-find part is the PC/104 stack-through connector. so I can see it from the side. With four chips and a LED array. not always. you can use a dual-row. I did try the POST board on several CPUs and motherboards.com 44 Issue 117 April 2000 CIRCUIT CELLAR® . Reading the POST error codes should be easy now. I was able to build it using parts from my junk box. you should be able to get the POST error codes for the module from the vendor. That's the basic POST board. wire-wrap header for the PC/104 connector. or the error the POST detects might not be obvious.circuitcellar. 12. They can be wired to all of the bus signals. –12 V) on the bus. you might install headers that mate with your favorite logic analyzer. I could add a com- parator circuit that would give an over/ under indication of the power supply voltages (5. The strategy is to find a peripheral chip like a multi I/O or floppy controller with a datasheet. It is possibly because I have the wrong error code list for that particular BIOS.angle socket on the edge of the board. if you know how to ask search engines the right questions. AMI Award BIOS is popular. Sure enough. most of the time the codes made sense. there are only a few. which you only realize after you wire up the little wires from your logic analyzer to a bus once or twice. This is a handy feature to have. For www. Photo 2—The PC/104-based POST board based on a hole-per-pad prototype board. if the card is used as the last card in a PC/104 stack. If you really want to get fancy. and Photo 2 shows the board.
I like building PC/104 modules because you don't need special prototype boards like you do for an ISA bus.com CIRCUIT CELLAR® Issue 117 April 2000 45 . because the protocol is an ISA bus. WHAT ELSE One nice thing about having a POST register board in my system is that I can drive it from my application to display system status while the system is running. The connectors are available from the same sources that PC/ 104 stack-through connectors are. The PCI signals are carried on special 128pin. able to see exactly what's going on in your system. where he works on formal-method design tools for high-assurance systems and develops embeddedsystem products. you want to do fancy things like master DMA modes. 2-mm centered stack-through connectors. send me or the editor e-mail. of course.circuitcellar. www. and robotics. I can display the interrupt level my software is servicing on the display. I just find any old hole/pad prototype board. The other issue is that. If you'd like to see more PC/104 and PC/104-plus board-level type projects.com.com www.astron-us. However.htm SOURCE PC/104 and PC/104+ stack through connectors Astron (408) 232-1100 Fax: (408) 232-1108 www. I can turn on the corresponding bit when I enter the routine and turn it off when I exit the routine.com/epr/ electron/issue2/feat0607. Also. it's a breeze to decode and use. I Ingo Cyliax has written for Circuit Cellar on topics such as embedded systems. and not the memory test like you would expect. pulling the system memory might get one of the early tests to fail. PC/ 104-plus is the standard for using PCI bus protocol in PC/104 systems. if building a prototype PC/104plus board were only that easy. you will instantly be RESOURCE AMI Award BIOS POST error codes. because the centers are 2 mm instead of 0. For example. add a header. you can't just use a pad/hole prototyping board. and I'm set. This month. even on PC/104-plus cards. I showed you that it is easy to build your own PC/104 modules. You may reach him at email@example.com. This kind of failure would be different than something like a stuck-bit error in the memory. a San Diegobased formal synthesis company.. you're pretty much going to need PCI-compatible chips. He is a research engineer at Derivation Systems Inc. There are many possible projects. By allocating bits for a specific interrupt level.example.1″. PCI on PC/104-plus runs at up to 33 MHz and is much more complex than ISA bus. to implement PCI. I just have to be prodded into writing about them. If you plug a POST board into your system. Unless. Now. FPGA design. and let us know.
1966 brought in the IBM 2314. it all depends on how you look at it. The IBM 3735 was a prelude to the IBM 3340. California.circuitcellar. reading between Mom's lines. By the 1960s. Datalight's ROM-DOS. It's an Ampro Little Board/P5x SBC that you see in Photo 1. LOOK OUT.0 love my job. Your eyes would have been in the dirt too if you could have been here with me to behold what came out of that box. You know that I like blinky LED projects. Disk storage was coming into its time in the 1950s. so while they weren't doing anything else. I CIRCUIT CELLAR® was eager to cut it open to see what goodies abounded within. I'm a little miffed at Bill this month. 46 Issue 117 April 2000 . The 3340 Winchester drive featured two spindles with a storage capacity of 30 million characters each. too). You've seen me cuss when I do something stupid and hold my hat in my hand after almost smoking an embedded SBC. I've been begging for Windows NT 4. It's even loaded with an IBM 340MB Microdrive! Hold on folks. Today. my trusty UPS guy delivered a large box with Ampro tape all over it to the Florida room." So. The '70s were kind of boring. My eyes just about popped out and fell onto the Florida-room's terrazzo floor. I called upon a reputable and well-known embedded PC hardware company for help. You've been privy to my mishaps with QNX. you know that everything from tiny Internet appliances to embedded PC backplanes have mysteriously appeared on the Florida-room stoop. which could store 6000 times as much data as the original RAMAC arrays. "Pity the rat that has only one hole to run to in times of danger. My mom says. engineers at IBM invented the floppy. lubricated disks. and sealed assembly. the IBM 1311.0? According to Fred. A few days later.0 Embedded information for quite a while with absolutely no luck. On September 13. Phar Lap's TNT. the first disk drive with a wound-coil ferrite recording head. let's go back and see how the IBM Microdrive really got here. which was the first disk drive to use low-mass heads. This first-of-its-kind. This month. 1956. a small team of IBM engineers in San Jose. Before we get into the Ampro host embedded PC. this is gonna' be fun. and Bill G. DICK TRACY Dick always had the latest embedded technology. introduced the 305 RAMAC (random access method of accounting and control). mass-storage device could store a whopping 5 MB of data on 50 24″ diameter disks. But.com i What's so great about Windows NT Embedded 4. IBM introduced the first storage unit with removable disks. and most all of Bill's products. In my business. Fred's looking at it via Ampro's Little Board/P5x SBC (which came with some other goodies. Data recording densities reached 1 GB per square inch www. hence the terms 30-30 or Winchester. I get to play with the latest embedded PC gadgets and savor the flavor of exotic and not-so-exotic operating systems. Looks like we have the latest in hard-disk technology from the IBM folks right here in the Florida room. This random access technology found its way into the airline industry and the space race. the first computer disk storage system.EPC Applied PCs Fred Eady Under the Covers Part 1: Get Embed(ded) with Windows NT 4. we all know yesterday's IBM 3340 drive as the Winchester drive. For those of you who dare to follow my adventures every month. Ethernet. His two-way wrist radio is still a hit today. I never know what the UPS guy will bring for me to smoke test today. The 1980s brought in the 3380 storage array.
world record in data density was set with 3 GB per square inch in 1995. but it still takes a equivalent to the stanfew steps to walk around dard Intel ICs (8259. dard IEEE-1284 with bishown in Photo 2. spinning mately 1. Other than getting to hold a 340drive—and I have one! As the little noting that the companys incorporatMB Microdrive in my hot little hands. which packed CD-quality audio. and 8254.25″ Seagate that held a mindbending 5 MB unformatted. puts directional data lines. OK. significantly in size and with two acting as RSincreased in capacity by 232 only. This setup is a hardware veloped the technology to build a 1″ heaven. An iOMEGA Clik Disk holds 40 MB. or six hours of near All of the required PC-compatible of large system storage. "And I helped!" you Microdrive.) 8237. My first hard disk was a full-sized 5. which would be introduced in 1999 as the Microdrive in the technological dirt! TakAN ALTERNATE PATH drive. or IRDA. cently by IBM to identify a new line floppy diskettes. When the little girl A 40-MB Clik Disk dwarfs the MMX. but there's a 3-GB hard disk in this little black box. footprint. It's fully PC/AT As you know. Get three quarters toonboard peripheral content is equal to definitely knew she was from the gether. respecTake a look inside tively) that you saw on your desktop or.000 times two serial ports can be since the introduction of mixed among RS-232. I Photo 2—You can bet this little puppy is going to get smaller in size and bigger in density. Memory tops heads is still in use today. (I've walked around a few 3380s. too.com CIRCUIT CELLAR® Issue 117 April 2000 47 . There are four 16550Disk drives have shrunk equivalent serial ports. 3.000 compressed digital out at 256 MB and can be either a RAMAC name was used again rephotographs. it in the computer room. back in the truck. yet. the equivalent of 200 DIMM of EDO DRAM or SDRAM. ity into a much smaller seven DMA channels. The IBM Microdrive is believed The Ampro Little Board/P5x SBC The commercial centered on this to be the smallest hard disk drive uses either a 166. RAMAC. the Ampro Little with the Shake and Bake girl. Embedded OS code for you. girl on the Shake and Bake commering the Microdrive into its products. hard disk drive platter. and there's more level RAMAC approach to storage. As you minute.5″ hard disk drive. For those of you not familiar To give you an idea of what kind of have already seen. that same basic three-quarters deep and approxicompatible. TTL. (It's a whole lot and three programmable smaller than the old 3380 counter/timers. the can hold 1. sions. mercials for Shake and Bake years ago.) 1991 introduced the world to IBM's giant magnetoresistive heads and the first one-gigabit.5 × 1. I had no idea how I could ever fill it. known as Tillamook.circuitcellar. this. and flying read/write weighs less than an AA battery. There are connectors on the back of this box for everything you would ever use in an embedded situation. In fact. and I'll give you some dimenthe logic contained on six external South. I can still remember getting my first 1-GB drive. Mobile Pentium processor with in the kitchen. A new. inside your laptop. The technology in The parallel port is stanthe IBM Microdrive. It two cache on this tiny board than on magnetic disks. The Microdrive is exactly expansion boards. 512 KB. better PCs of yesteryear. and most desktops. Think about RS-485. she was affect the IBM Microdrive will have. In September 1998.or 266-MHz Intel little girl helping Mom cook chicken shipping today. now. That's boxes. Board/P5x SBC has a few tricks up its a little girl who appeared in TV comhere's some of what it can do right sleeve. it's safe to say that the Microdrive on Ampro to help me get some NT Let's get out of the truck for a has arrived.using magnetoresistive heads. IBM dePhoto 1—You can't see it here. there were other good reasons to call cials used to say. goodies are onboard—15 standard larger disk storage capacinterrupt channels. The remaining more than 5. your already tiny laptop was surprised but www. the world's smallest hard disk ing a peek at IBM's web site and.7 quarters in girth. Its spouted her line.
If those boot couple of pages.circuitcellar. batteryless boot. Just hook up an contained on an EBX 1. your favorite peripheral is requires.1 standardsASCII dumb terminal and take charge. Of course. scribing the BIOS enhancements to you. BIOS extensions to customize The Florida-room version Photo 3—How about that! This is the last operating system I would have your boot scenarios.0 on To differentiate the Ampro Little neat boot options like serial boot this little fish. Things like a watchdog code to be loaded from another exterMany of you are probably wondertimer and serial console support are nal serial source. improvements to the architecture and The serial boot loader allows boot WINDOWS NT WHAT? firmware. Under BIOS configuracomplement of IDE drives is tion control. decessors. Ampro has made some and accelerated boot.0? www.com CIRCUIT CELLAR® Issue 117 April 2000 49 . process retries boot devices floppy drives are supported. Fail-safe in the onboard Adaptec ACIboot does it until it gets it 7860 adapter. but chances options aren't what your app are. the guys at Ampro based CPU module." I fired the Ampro Little 266 MHz and is equipped with Board/P5x SBC up while I was de64 MB of RAM. What's so great about via calls to BIOS. Ampro also has included some really loaded Windows NT Embedded 4. All this horsepower is port is exactly that. This is used in the Windows NT Embedded 4. The watchdog timer monisetup information is stored in nonespecially an OS that's been around tors the boot process and is accessible volatile EEPROM instead of batteryfor a while. The standard right. Serial console supbacked RAM. Look at this. Batteryless boot is ing why all the hoopla over another essential items for true embedded another way of saying that the system embedded operating system entry— operation. Board/P5x SBC from its desktop preloader. you see in Photo 1 runs at expected to see on the same page with the word "embedded. Accelerated boot is BaseT Ethernet port just for simply whizzing past the me! I could go on for another POST routines.event of onboard RTC/setup pleased to see SCSI capability RAM battery failure. you can use Ampro's on the list. the fail-safe boot also supported. until a successful boot is and there's even a 10/100 achieved. fail-safe boot.
or does it just dial up the 'Net and browse the web? Without bashing CE or Windows NT Embedded 4. These components usually will be device drivers or special applications. An authoring tool set consisting of Target Designer and Component Designer allows embedded developers to configure and generate a specific Win- dows NT Embedded 4. ARM. file and application dependencies are checked.0 technology utilizing Service Pack 5. One answer is the size of the embedded device you are writing to.0 is designed to allow developers to use the vast off-the-shelf Windows resources to affect embedded designs.0. Component Designer can be used to create reusable components that were not included in the Windows NT Embedded 4.0 for anything embedded?" If I want to embed in Bill's world. WHY NT4 EMBEDDED OVER CE? If I developed embedded Windows programs for a living. What does your device have to communicate with? Does it participate in a LAN. Don't confuse this with the recently announced Windows 2000. but that's about all. Target Designer is used to configure a device-specific Windows NT Embedded 4. Will your design be used by the military or by kids on the block? Yet another answer may lie in functionality. Now. Once an operating system has been configured using Target Designer. good. all of you who write Windows desktop applications raise your hands—OK. Windows NT Embedded 4.0 product.0.0 operating system. Did you know that all of you who raised your hands for either question are potentially capable of writing embedded Windows NT Embedded 4. etc. such as memory size or data storage size. Windows NT Embedded 4.0 applications? Well.com . What I mean by size here is size in the physical or in the hardware. Windows NT Embedded 4. As an option. Windows NT Embedded 4. the very first thing I would ask myself is "Why do I have to use Windows NT Embedded 4. congratulations on your newfound talent. I already have other embedded operating systems.0 is the latest Windows NT 4.0 operating system using Windows NT binaries embedded-enabling technologies and an application. CE can do MIPS.0 tends to lean toward Pentium class processors 50 Issue 117 April 2000 CIRCUIT CELLAR® www.0 is designed to allow the embedded developer to leverage his or her existing Windows programming knowledge and produce better products faster.I want all of you who are Microsoft Certified (MCP. let's explore the possibilities.circuitcellar. and PowerPC to name a few. and a bootable image is produced that can then be loaded onto the embedded device and executed. New components then can be imported into Target Designer where they are incorporated into the device operating system. CE supports quite a few more processors than Windows NT Embedded 4. They share 'x86 compatibility. including a Windows-based Windows CE. MCSE.) to raise your hands—OK. Another answer is security.
0. too. Because Windows NT Embedded 4. Our Ampro Little Board/P5x SBC steps up to include CompactFlash and the IBM Microdrive mini-spinner. which is clocking in at 266 MHz. Although the Windows NT Embedded 4. In this mode you talk to your embedded sweetheart via a telnet server or a web-based management interface. CE being optimized for smaller applications is also optimized for smaller displays. Both CE and Windows NT Embedded 4. those numbers increase to 16 MB of play space and additional 16 MB of available storage. NTFS allows the administrator to control access down to the file level.0 and not in CE are AppleTalk.0 can handle a number of CPUs in a multiprocessor configuration. Not only did they load Windows NT Embedded 4. CE does FAT and the "Kryptonite" FAT32.0 starts at 640 × 480 and goes up from there. You can see this in my Ampro Little Board/P5x SBC. Looks like the IBM Microdrive is also loaded with a version of Bill's MS-DOS. the security features offered by NTFS make Windows NT Embedded 4. The notable protocol exceptions contained in Windows NT Embedded 4. too. There's really not much difference in usability between CE and Windows NT Embedded 4.circuitcellar.0 and try to run an application or two. You can stop your resolution count at 800 × 600 for CE. Both operating systems have a gaggle of built-in utilities like Internet Explorer.0 is limited only by the amount of storage it can grab. PAP. As far as CPU speed. M-Systems DiskOnChip.like the AMD K5 and K6. The same size comparison can describe the multitasking capabilities of each product. In addition to NTFS. CE was designed for small singleprocessor mobile and palm-top type embedded applications. PPP.0 do preemptive multitasking. I did some more exploring while you were reading. I have no doubt that the Ampro Little Board/P5x SBC running Windows NT Embedded 4. IDE hard disks. However.com means that you can generate your Windows NT Embedded 4. For those of you who design in sensitive environments. CE does its thing in 1 MB of play space and doesn't require any additional storage.0 with a 166-MHz CPU would perform well also. With networking installed. if you don't factor in networking. Netbeui. or be prepared to write some interface code.0 or CE system without a display. Windows Explorer. Speaking of screenshots.0. Communications protocols for CE include TCP/IP. I'll continue my investigation of Windows NT Embedded 4.0 bigger as far as code goes. SOURCES Little Board/P5x Ampro (408) 360-0200 Fax: (408) 360-0222 www.0 Microsoft (206) 882-8080 Fax: (206) 936-7329 Microdrive IBM (407) 443-2000 Fax: (407) 443-4533 Issue 117 April 2000 51 .0 implementation could be run in headless mode.) These data formats can be stored in ATA flash memory. (Windows NT Embedded 4. He has worked with computers and communication systems large and small. too. CE can do all of that. Seems like the Ampro engineers felt sorry for me. Until then.0 loader screen. I might do something there. and both support threads. and Command Shell. and bootable CDROM using Windows NT Embedded 4. and IPX/SPX. HTTP.0 protocols are all of those you had to know about to pass the Workstation Exam for your MCP or MCSE. I Fred Eady has over 20 years' experience as a systems engineer. Windows NT Embedded 4. Windows NT Embedded 4.0 is a binary equivalent. Windows NT Embedded 4.com. His forte is embedded-systems design and communications. I'll leave you with Photo 3 which proves that even Bill G.0.0 can't do or coexist with FAT32. If I can figure out how to make those other two operating systems tick.0 requires a minimum of 12 MB to play in and 8 MB of available storage. simple and complex. Memory requirements are another factor that makes Windows NT Embedded 4. Windows NT Embedded 4. I see QNX and Linux as boot options on the Windows NT Embedded 4. the Ampro Little Board/P5x SBC offers "green PC" power-saving modes using APM (advanced power management) BIOS functions. the Ampro system has its hat on. Fred may be reached at fred@edtp. NT4 IN YOUR FUTURE I've nearly run out of paper here. and both operating systems can be configured to work without the seemingly ever-present GUI. We're going to have a good time next month! Next time.0 also supports FAT and compressed data formats. and CE has features to allow for extensive battery management. Power management is a must on CE-equipped mobile computing platforms. Windows NT Embedded 4. Thus. Headless simply www.0.com Windows NT Embedded 4. thinks it doesn't have to be complicated (or CE) to be embedded. CE has no inherent security features.ampro. CE runs the gamut. the power management capabilities are generally left to the hardware.0. On CE and Windows NT Embedded 4. On CIRCUIT CELLAR® Windows NT Embedded 4.0 is 200 MHz and above. SLIP. configurable subset of Windows NT 4.0 big when compared to CE. this GUI-less mode is called headless support. CHAP. don't design your device with CE. For example. CE is limited to 32 concurrent applications. and IrDA. The recommended speed for Windows NT Embedded 4. the overhead of supporting multiple CPUs makes Windows NT Embedded 4.0 also supports Cyrix 5x86 and 6x86 CPUs. Windows NT Embedded 4. This says to me that if you want to network off-the-shelf with the legacy big boys.0 platforms. so I can show you things via screenshots. just like it's desktop brother. Windows NT Embedded 4.0 a good candidate for your projects.
52 Issue 117 April 2000 www. coming down to lower frequencies directly increases the methodical error: 1 MHz 100 kHz 10 kHz 1 kHz 100 Hz 20 Hz -> -> -> -> -> -> 10 ppm 100 ppm 1000 ppm 1% 10% 50% When it comes to measuring frequencies. and have long enough gate times. With an extended gate time of 10 s. slow measuring is not an advantage. A faster and better measuring method would help. which varies from 1 ms to 10 s. this is the fixed gate time (1 s) during which the number of trigger edges (N) is counted. S N cycles counted Gate time = 1s Measured frequency = N Hz T Figure 1—With the normal frequency measuring method.1% -> 0. as you can see in Figure 1. and a gate time of 1 ms would give kilohertz. as a result of human ability to follow such a readout. When these instruments show measuring results on a digital display. the useful measuring rate would be limited to two or five measurements per second. low frequency measuring needs longer gate times (an often-used approach) or another measuring method.1-s gate time.com . The number of signal cycles counted during 1 s would directly give the signal-frequency in Hz. the classical method would deliver an improved accuracy by a factor of 100: 1 kHz 100 Hz 20 Hz -> 0. frequency measurement has been done by counting signal cycles during a specified. let's assume a frequency of 10 MHz is to be measured during a 0. as the frequency you are measuring drops. which equals 1-ppm measuring error. In terms of measuring accuracy. Slow measuring just delays feedback loops and reduces understandability in laboratory situations. So. this method is fine when you are in high frequency ranges. the CIRCUIT CELLAR® s Figure 2a and b shows the principal accuracy limitation of classical frequency measurement. the time-base error would already be 1 decade above the methodical error—so. In this article. In fact.1-s gate time.01% -> 0.circuitcellar. This would deliver 1 million cycles to be counted during the 0. So. For example. When our instrument uses a time base with a 10-ppm accuracy. such as megahertz or gigahertz. no problems with the measuring method. ince the early days of digital technology. Although.A Quick Meter Made Fast Frequency Meter for Low Frequencies FEATURE ARTICLE Markus Desgronte methodical counting error would be a ±1 count. so does your accuracy. fixed-gate time. the accuracy increases proportionally with frequency and gate time. Markus shows us how to make a frequency meter that's quick and has no problem handling lower frequencies.5% In the real world. FAST FREQUENCY MEASURING The measuring method used here improves this situation in both areas—higher accuracy and faster measurements of low frequencies. This measuring method is satisfactory for many applications and can provide instruments for measuring frequencies in a range of 10 kHz up to megahertz and gigahertz ranges.
5000 PUT #3. H2.******.000 Hz to 4999 Hz measuring range).438Hz signal with FFM is shown in Figure 2b.B BYTE .B BYTE ."1" .. Device driver TIMERA is installed and started as the corresponding timebase.TDD INSTALL_DEVICE #2.240.#0. which is another advantage of fast frequency measuring (FFM).****.***B BYTE ***. FREQ1_84. The number of cycles and window time values are converted into a frequency by the quotient: f Hz = number of cycles window time s This relation easily shows that we have the potential for high accuracy.top-of-endless-loop get Input-Buffer: Filling measurement available? get Frequency (mHz) show frequency in Hz --> loop-end Listing 2—Defining bitmap graphics (as the "3" shown here) may be done directly in the source code.. or ".#0.***. LCD1. Besides counting the number of periods during a certain time window. TIMERA. The binary format here allows the use of digits "0" .com CIRCUIT CELLAR® 53 .31. An optional amplifier for non-TTL signals may be added (see Figure 3a). do the range settings. which shows the frequency values in both an analog and a digital form..B Bit-position in bytes 0 Character = 3 1 2 3 4 5 6 7 8 x 17 (w x h) 8 9 10 11 12 13 14 15 16 In this article.. which is independent from the actual signal frequency and can be increased as needed with increased accuracy of the time window measuring.***B BYTE ***..***B BYTE ...****..******. The logarithmic analog display reflects the constant relative accuracy over the full measuring range as well as the digital display.. THE REALIZED INSTRUMENT Listing 1—In a digital-readout-only version.97-LOGFREQ.0) which defines Port 84 as the input pin for measuring.FREQUENCY PRINT USING #1.***B BYTE ***.TDD Listing 3—Here are the two codelines responsible for the logarithmical-scaled analog bargraph..#UFCO_DEV_OPT1.500 kHz Measurement on Pin L84 Set gate time Start ENDLESS Measuring <.4.TDD..***B BYTE . I describe how to build a frequency-measuring instrument using FFM with just two components needed—a LCD and a BASIC Tiger computer module.Hz ENDIF NEXT END text LCD 4 x 20 TIMER-A: 12.FILLING IF FILLING > 0 THEN GET #3. LOGFREQ=22*LOG(FREQUENCY/1000) scale for logarithmic display DESTIN W1. H1.***B BYTE ***. The BASIC Tiger computer is used for the measuring process and the user interface as well..11.TDD PUT #3. INSTALL_DEVICE #1.B BYTE . The improvements of FFM come from using more existing information from the signal to be measured.***B BYTE ***.****.circuitcellar.1. and get the measured frequency values from the device driver. DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA --> 76543210 <-BYTE .. MODE GRAPHIC_FILL_MASK (SCREEN2$.****.128.200 INSTALL_DEVICE #3.***B BYTE ***...Actually.B BYTE . The device driver responsible for frequency measurement is installed with install_device instruction: INSTALL_DEVICE #3...****B BYTE ***. The following two PUT instructions are setting driver specifications as measuring rate and count. Your job is to install the device drivers. The elementary program needed to measure frequencies continuously and display results on a text display is shown in Listing 1.. which always displays four relevant digits (1. W2." characters. I am using a high-resolution graphics display. An example of the measurement of a 3.0 FOR K=0 TO 1 STEP 0 GET #3.. Y. FFM also adjusts the time window to get a more accurate time measurement for the counted number of signal cycles.#UFC_IBU_FILL...B BYTE . "*".#0.. The GET instructions in the endless FOR-loop are checkIssue 117 April 2000 www. For best readability.. the measuring accuracy is constant over the full measuring range. the frequency meter consists of just a few BASIC code lines.B BYTE ***... The measuring part of the frequency meter is covered by device drivers. X. FREQ1_84. FREQUENCY .****B BYTE . which are supplied in the BASIC Tiger development environment.LOGFREQ.0.
Instead. and CFL illumination for best black-and-white contrast.567 88. where "*" represents 1 bit (black pixels) and ". BITMAP AND VECTOR GRAPHICS *** Frequency input AND GND GND VCC VEE WR RD CE C/D NC RES D0 D1 D2 D3 D4 D5 D6 D7 GND VCC ** * 4. which is drawn with the FILL_MASK function and the digital reading.567 10k 1k 10k 1k 10k 1k Bitmap graphics in a BASIC Tiger program can either be imported from *." represents 0 bits (white pixels). This can be designed with any graphics package on a PC and exported as a black and white bitmap format (. Included is a black and white bitmap graphic.3 4512 10k 1k 100 10 1 10k 1k 100 10 1 10k 1k 100 10k 1k 100 10 1 10k 1k 100 10 1 4. which is always a 4-digit result with differently set decimal points. a BMP-file. I might install the frequency device driver several times for up to four measuring chan- a) V 10k 1k 100 10 1 10k 1k 100 10 1 10k 1k Hz 100 10 1 10k 1k 100 10 1 nels. OR. or generated from a BASIC Tiger program. you need to use DATA instructions in a pixel format. or I might use free space on the display for other information if I think of expanding this application. (The Y-size of the bar is proportional to the logarithmic value of the measurement. 2b—FFM measures the real window time within the gate time. Also there is an analog display (in the form of a bar graph). readable digits here.or 4-Hz frequency. high-resolution graphics to be output on a device such as a LCD.88 725. 54 Issue 117 April 2000 CIRCUIT CELLAR® . depending on value. you do not use the built-in character set of the display. ing the input buffer for availability of more measurements and getting the next measurement.BMP files. and XOR functions.3 4512 The final instrument Figure 3a—The instrument consists of just two components: a BASIC Tiger multitasking computer and a graphic LCD. The TTL signal is directly connected to a Tiger I/O pin.0 as follows: DATA FILTER MESS_HZ. I'm using both techniques to make up the construction of the instrument to be shown on the LCD. several graphical layers can be overlayed through AND. The instrument layout here is already designed for four channels to be displayed simultaneously.88 725. To import the instrument background. you use predefined bitmap graphics for digits 0 through 9 and the decimal dot.88 725.3 4512 Hz 100 100 100 10 10 10 1 1 1 88. www. b) CC This feature gives this instrument a well readable and informative appearance. resulting in much more accurate frequency measurements. the DATA instruction is used with the filter GRAPHFLT.567 OR 88.) To get big. you would replace the simple PRINT USING output to a text display with a better looking graphics output (see Figure 3a). defined in DATA instructions. Depending on the application. I have selected a T6963 LCD with 240 × 128 pixel.GRAPHFLT. you'll see that to define the set of numerical characters. a 6″ × 2. Figure 3b shows you the instrument layout and the three components it's made of.0 Meter graphics If you look at Listing 2. In the real project. These pixel arrays for each digit are moved into the screen as needed.circuitcellar.6″ viewing area. Graphics in a BASIC Tiger program can either be bitmap graphics or vector graphics in Cartesian or polar coordinates. This instrument is made up of several components that are overlaid and displayed together on the LCD. 3b—As seen in this example of a 4-channel analogand-digital meter layout with logarthmical scaling.BMP. which is 240 × 128 for the instrument background.8724 s Frequency = 3. PLANNING THE LAYOUT BASIC Tiger allows the generation of moved.BMP).438 Hz Gate time = 1 s Measured frequency = 3 Hz Gate time = 1 s T T Figure 2a—The shortcoming of the normal frequency measuring method is that the same signal might be measured as a 3.com D0 D1 D2 D3 D4 D5 D6 D7 WR RD CE C/D Hz 10 1 4.a) S b) S Gate time = 1 s Measured frequency = 4 Hz Window time for 3 Periods = 0.
SCREEN$ (a string).de. and transformations.circuitcellar. rotation.wilke-technology.com. which is chosen for its best fit into the available space. enjoys traveling and spending time with his family. use vector graphics. by fax at ++49 (241) 918 9068. when not fighting bugs and glitches. I am showing bar graphs proportional to the logarithmic value of the measurement. shifts. SOFTWARE The full commented program is available for download at www. using the FILL_MASK instruction shown in Listing 3.com . You can reach Markus by phone at ++49 (241) 918 9031. you can have a sophisticated instrument at your fingertips. you are subsequently moving pixel data from the character definition area in flash memory into the screen area. For displaying variable bar graphs. In this case. I Markus Desgronte is an electronics engineer who. To make up a 4-digit number. this project demonstrates the construction of a smart instrument with minimal hardware and programming overhead. As you've seen. Vector graphics are open to any kind of calculations. The commented program code in the listings shows the details. in RAM.wilke-technology. The mask generated by this FILL_MASK function is a white bar on a background area in SCREEN2$.com LMG7420 (LCD) Hitachi (800) 448 2244 (415) 589-4207 Fax: (415) 583-4207 56 Issue 117 April 2000 CIRCUIT CELLAR® www. or via e-mail at desgronte @wilke. SOURCES BASIC Tiger ENN-4x Wilke Technology +49 (241) 918 900 Fax: ++49 (241) 918 9044 www. With only a tiny multitasking computer ($49) and a graphic display ($20–$80). such as scaling.The example shows the digit "3" in an 8 × 17 grid.
they don't "correlate" at all. you'll be more than ready to download the software and start working with these data-analysis tools. a signal correlated with itself). so you will have to take a look at one equation to get started: R m = 1 N N–1 n= 0 Σ x n y n +m If you need to perform signal analysis. When they are 90° out of phase. Applications include audio reproduction. x (n) is the sequence of amplitude values in the signal on the bottom film. whose magnitude varies between zero and one. Each correlation number (R) is just the normalized sum of the x signal multiplied by the y signal. correlation is a mathematical procedure. and R is equal to 0. Suppose you have two sine waves with the same amplitude and frequency drawn on separate pieces of transparent film. and m is the variable that describes moving the top film in steps of the signal sampling interval. Cross-correlation is using different x and y inputs. placed one on top of the other.com . this is a powerful analysis method. Let's look at a few examples of Figure 1—You can make a graphical correlator by plotting wave forms on two sheets of transparent film. you have a simple correlator (see Figure 1).. If they are completely different. The examples in this article can be run on a personal computer. This coefficient (R) is a dimensionless number. Then you can program a digital signal processor if you are building some special-purpose hardware or need the processing speed. Ron takes a graphical approach to explaining the details of correlation. seismic event detection. AUTO. So. R = 0. orrelation is a signal analysis method that compares two time sequences to find out how alike they are. acoustics. Sliding the top film right or left is equivalent to solving the correlation equation.e.circuitcellar.AND CROSS-CORRELATION If you use the same signal for both x and y. Yes. When the two signal traces coincide. so you need to know approximately what the signal looks like without the noise. n. By the time you finish this article. You CIRCUIT CELLAR® c Fortunately. This improvement isn't free. they are said to have a correlation coefficient (R) of unity.All About Correlation FEATURE ARTICLE Ron Tipton can construct numeric band-pass filters with narrow passbands for recovering periodic signals buried in noise. If you hold the bottom film stationary and slide the top film to the right or left. 58 Issue 117 April 2000 www. but for practical reasons. and you will be able to use your PC to model virtually any real application by scaling the "real world" signal frequency. and what practical use does it have? The method is probably best understood by looking at it graphically. (Mathematically. how do you find this coefficient. you can relate this equation to the previous graphical example. y (n) is on the top film. R = 1.) Although it's not obvious yet. and many others. you have auto-correlation (i. sonar. you have a coefficient of –1 when they are 180° out of phase. you'll only look at the 0 to 1 interval. and this can provide up to a 20-dB improvement over autocorrelation in pulling a signal out of the noise. If the two signals are identical.
and this accounts for its remarkable performance a) 0.1 Amplitude 0 0 -0.2 -0.exe actually do? After asking for input from you. Gensine. can be found in correlat. which makes these files easy to import into a math program (such as Mathcad) for graph- ing the data in reports and other presentations. but cross-correlation pulls it out neatly. using this delay time. The output file is named either AUTO.exe with the C source code. Auto-correlation (b) does not require any knowledge of the signal. Cross-correlation also can be looked at as a type of digital or numeric band-pass filter.4 -0. which is 1000% noise.com CIRCUIT CELLAR® Issue 117 April 2000 59 .exe also writes the same kind of output file.2 Amplitude 0.3 0. there was 1000% noise added.DAT or CROSS. as you can see in Figure 3b. so visually it looks like noise. and it will be written again every time you run the program. and in b). If you don't know the wave shape and frequency.6 -0. To show how powerful cross-correlation can be. Autocorrelation shows not a hint of the buried signal. the best you can do (at least initially) is auto-correlate. You start to see the signal. A companion program. so they lack some of the refinements you expect in commercial software. Cross-correlation is a powerful tool for pulling signals out of the noise if you can construct a reference signal.2 0.2 -0.exe. a DOS program written in C. the input had 99% added noise. I generated an input file setting the RMS value of the noise to be 10 times the RMS value of the sine wave. auto. www. These correlations were done with program correlat. rename them something descriptive between runs.3 Figure 3—This is the output of cross-correlating a noisy sine wave with a "clean" reference. I wrote all of these programs as development tools. The programs are written in MIX Software's PowerC.DAT.circuitcellar.4 0.5 -1 -6 -8 -1.6 b) 0. Then. Figure 2a shows two cycles of a sine wave with added random noise.1 -0. it correlates the input signals and writes an ASCII output file with each value terminated by a new line character. what does correlat. if you create files containing varying amounts of noise. is included to generate input files with and without added noise. along with the executable.a) 12 10 8 6 b) 1. if you know the frequency.5 Amplitude 2 0 Amplitude 4 0 -2 -4 -0. The well-commented source code. So. The output file is named SINE. However.5 1 0. The RMS value (see the Root Mean Square sidebar) of the noise is equal to the RMS value of the sine wave.DAT depending on which operation was chosen. gensine. Figure 2b shows the results of auto-correlation. but it's still noisy.zip on the Circuit Cellar web site.5 Figure 2a—Here are two cycles of a sine wave with 99% RMS added noise.and cross-correlation. but recovery is poorer than is possible with cross-correlation. In a). it finds the maximum correlation coefficient and displays it on the screen. you can cross-correlate the noisy signal with a noise-free sine wave and get the improvement shown in Figure 3a. but they should be easily portable to other compilers if you want to make changes. along with the corresponding delay between the two inputs. So.
For example. simply vary the noise-free signal frequency to minimize the signal distortion out of the correlator. simphase.circuitcellar. the highest practical rate can be pretty high. which required me to design a cross-correlation phasemeter. Counter phasemeters also have a problem that occurs when the phase difference is near 0° or 360°. you may need some fast ADCs. When the signal frequency is unknown or guessed at. I had to update a datacollection system.5 Figure 4—Notice the effect of using a slow sampling rate. where one signal is corrupted by noise.a) 1.com . And a few (such as the HewlettPackard model 3403C) use a thermal AC to DC converter. By looking at zero crossings. CIRCUIT CELLAR® www. which let's you use cross-correlation to clean it up as best you can (see Figure 4b). PHASE ANGLE RECOVERY Sometimes the only information needed is the phase angle between two signals at the same frequency. For a sine wave. The RMS value is literally the square root of the sum of the squares of the time-sampled values. This article isn't meant to be about digital filters. the correlation meter does not have this problem. the standard deviation of the jitter is reduced by the square root of N. The cross-correlation output (b) still shows some distortion from the low sampling rate. This (a) is what auto-correlation of a signal with only 50% added noise sampled at 20 points per cycle looks like. within practical limits.6 b) 1 0. The accumulated count was a measurement of the phase difference between the two input signals. and then take the square root. one RMS ampere flowing through a resistance produces the same amount of heat as does one DC ampere. and the second input signal stopped it. one of the inputs varies between noisy and extremely noisy. the RMS voltage is equal to 0. if you are looking at the output of an analog to digital converter (ADC). When the input signal is noisy. but the dynamics of this system prevent increasing N to more than 48. Meaning. genref. I used a sample rate of 200 points per sine wave cycle because it shows dramatic results! A good rule of thumb: Use the highest sample rate you can. performance is optimized by passing the noisy signal through a narrow band-pass filter and then averaging a number of successive phasemeter counts. in pulling a signal out of noise. True RMS voltmeters usually use a nonlinear circuit to approximate the relationship between average and RMS. Because it's a constant frequency system. the program asks for the signal amplitude and the amount of noise to add (in RMS percent).2 0 0 -0.c. 8 to 48 measurements are averaged and this improves the phase difference estimate by the square root of the number of averaged counts (N). Along with other parameters. The original phasemeter was a counter—one input signal started a high frequency counter. To get an idea of how much improvement I could expect from the correlation phasemeter. I wrote another C language simulation program.2 -0. with today's analog to digital converters (ADCs) and DSPs. Still noisy. Just square each value and accumulate a running sum for at least as long as the period of the lowest frequency of interest. As you'll see in a later example. Typically.5 -0. 60 Issue 117 April 2000 Root Mean Square The root mean square. or RMS voltage.4 0.4 -1 -0. In the previous example." but typically. Calculating it is an easy way to find the RMS value. Cross-correlation excels here. which lets us set the input signal to noise ratio (SNR). However. is a measure of the energy in a signal.707 times the peak voltage. you can estimate the signal's frequency. Because the phase measurement resolution depends on the sample rate. Solving this requires additional logic in the design. but you can start seeing the periodic signal. So. The second (clean) input is read from a data file generated by the companion program. successive counts may jump erratically between zero and full scale.5 Amplitude Amplitude 0. Meaning.6 -1. but I included a brief explanation in a second sidebar for those of you who are interested (see the Digital Filters and Correlation sidebar).5 0. what happens if you have to use a slower sample rate? Figure 4a shows an auto-correlation output of a sine wave with 50% RMS added noise sampled at only 20 samples per cycle.c. This works well when both signals are "clean.
50 ms average 15 10 5 0 -120 Figure 6—The cross-correlation phasemeter provides nearly 30-dB SNR improvement for low input signals and is always better than a counter phasemeter. The higher cost of the cross-correlator is justified when performance is a critical requirement. This meter generates a phase used as a new startrate is too high for a difference output every millisecond using a Motorola fixed-point DSP with a 50-MHz clock. After playing with RAM-2 Therefore. run. Figure 6 shows the output SNR tized at an 8. This count is used as a startThe read and write enable signals frequency. a timing circuit. with RAM-2 being Correlation works well in recoverRAM-2 and estimates the count "z" filled while RAM-1 is processed (see ing sine waves from noise. the energy is concentrated at a single crossing. the cross-correlation. A noisy square A correlation is run. (These programs are Write enable Data When the input included in RAM-1 Read enable signal is badly corcorrelat. Address Phase different rupted by noise." A Finite Impulse Response (FIR) digital filter is one way to perform the convolution. so the signal must have most of between the noisy data and the saved by starting with an estimated z its energy within this passband. This is crucial to having this phasemeter ever.dBm -70 -60 www. and another correlation is its signal bandwidth is too broad.and is divided into two parts. Program execution SNR. If the signal is a sine or cosine wave. means. millisecond from the timing logic. 50 ms average 30 Output SNR-dB 25 20 Counter. (The clock Figure 5—The clean input (reference signal) is read from the EPROM. If the time domain waveform found. A so I laid out a printed which RAM bank it is processing. which relieves the width of the signal).zip. The amount of time ter. -110 -100 -90 -80 Input signal level . Convolution is sometimes called a "matched filter. ing point until a successful breadboard. Start Busy 45 40 35 Cross-correlation. The peak is always found in no more than circuit board for the initial model. (This is 1700 samples per input The DSP firmware is a bit complex cycle for a phase resolution of 0. z is increDSP from having to keep track of wave is not recovered well because mented. When this formance. the original signed and built a z is decremented and prototype. a matched filter will do the job. time-sampled data values in time reverse order. The phase difference or answer Remember that correlation can be shape is known. The first NON-PERIODIC SIGNALS part reads the data from RAM-1 or Pong technique. This process is continued until a The same is true for noisy pulse Digital Filters and Correlation peak in the correlation coefficient is trains.212°. even at minimum second (reference) signal values are The incoming noisy signal is digiread from EPROM. the which is available for out zero-crossing estidownload via the CirData Noisy signal DSP ADC 12 bits mate may be in error cuit Cellar web site. and the for both a counter and cross-correlais started by an interrupt signal every resulting 12-bit words are stored in tion phasemeter. so correlation and convolution are the same. so I defirmware happens. phasemeter would generator 1000 Pulses which means you've yield a significant per second Timing EPROM ref data missed finding the improvement in perand peak. and the noise is broadband ing point for the second part of the for both RAM banks are generated by (at least when compared to the bandprogram.) input Write enable by several counts.run fast enough. RAM. I was convinced mate can be smaller that the correlation Write Clock Data address Address than the first one. Howdata's "non-noisy" shape. Time reversal is the only difference between cross-correlation and convolution. because to the next negative-to-positive zero Figure 5). peak is found.5-MHz rate.com CIRCUIT CELLAR® Issue 117 April 2000 61 .) RAM-1 and RAM-2 are used in a Ping.circuitcellar. then there isn't any practical difference between the forward and reversed time values. the secthe simulator for a Read enable ond correlation estiwhile.) seven correlations. an optimal data is just the delay time corresponding to thought of as a narrow band-pass filrecovery filter is the convolution this maximum. the filter's coefficients are the noise-free.
1 -0. I Ron Tipton is an engineer with more than 40 years experience in analog. The noisy data file and coefficient file is read by fir_bp. You may reach him at firstname.lastname@example.com and fir_bp. even though they have different uses.6 0. (617) 577-1017 Fax: (617) 577-8829 www. This is real or "causal" filter even though it's done in software rather than a physical circuit. 62 Issue 117 April 2000 CIRCUIT CELLAR® . digital. K.1 0 -0.B.5 0 -0. Beauchamp. 1990.5 0. This is also a plain ASCII file that can be created or changed with any ASCII file editor.1 0 Amplitude 0.zianet. 1973.com/tdl.2 Figure 8—This is what the output of a convolution filter with the noisy pulse train of Figure 7b as the input looks like. C. If you look at the source code. but work well and run fast on a Pentium II-class computer at clock speeds of 200 MHz or more. Signal Processing Using Analog and Digital Techniques. You can also take routines from them to use in writing your own solutions. NJ.7 b) 1. (This filter was designed with the Momentum Data Systems software listed in Resources.3 0. correlation and convolution are similar. John Wiley and Sons. Englewood Cliffs.c.exe before the addition.9 0. which performs the filtering. and software design.3 0. so the noise is low-pass filtered in the program through a 2pole Butterworth with a 20-kHz cutoff frequency. Rorabaugh. McGraw-Hill.coe. 1993. Higgins. SOURCES PowerC Compiler Mix Software (800) 333-0330 Fax: (972) 783-1404 www. you will see that the "process" routines look the same in correlat. They are the sampled amplitude values of one of the pulses in time reversed order and normalized so they sum to unity. He is the president of TDL Technology. each coefficient has been divided by its original sum.G. Reprints of his other magazine articles are on the TDL web site.mixsoftware. You can try adding different amounts of noise and then look at the results. Figure 7 shows a test group of pulses that I buried in the noise using program genpulse. The result is shown in Figure 8. It's a good way to get a practical appreciation and feel for the data-analysis tools. As I mentioned earlier. The 30% peak noise was low-pass filtered at 20 kHz by program genpulse.7 0.5 -1 Figure 7—Here you can see an example pulse train (a) and these pulses buried in noise (b).5 1 Amplitude 0. This program assumes a sample rate of 100 kHz.6 0.8 0.) The matched filter coefficients for recovering the pulses are in file filter.4 Amplitude good.4 0.exe. I suggest that you play with the programs. they lack commercial polish.H. SOFTWARE All the software mentioned is in correlat.2 0.mds.5 0.2 0.exe. Inc.com www. Prentice Hall. Note the pulse time delay as compared to Figure 7a.zip. Inc. Mathematically. and the recovery is 0. which is available on the Circuit Cellar web site and also on the TDL site at www. Digital Signal Processing in VLSI. Digital Filter Designer's Handbook: Featuring C Routines. RESOURCES R.. These filter coefficients are coded into the program. a company he started that specializes in consulting and prototype development.com Mathcad MathSoft. Meaning. but they can be changed for a different filter if needed.mathsoft.com 0.com Digital filter software Momentum Data Systems (714) 378-5805 Fax: (714) 378-5985 www.com.a) 1 0.circuitcellar. NY.
To paraphrase: "You. An engineer who doesn't use op-amps on a regular basis could be left wondering why there are so many op-amps.MICRO SERIES Joe DiBartolomeo Op-Amps Specifications Served Italian Style If you're a digital or of software designer who only delves into the realm of analog and opamps when absolutely necessary. normally I e-mail ideas and drafts of articles to friends for their input. you stupid or something? What's with the op-amp? It's eight pins. I mean a real old-fashioned Italian bakery with gelato and pastries. What's the big deal? Foor-get about it. For this series. and high-decibel conversations. to say the least. and depending on the application. I got an earful. There's too many op-amps. Could you imagine sitting in a meeting with two engineers saying such things? I guess coffee doesn't bring out the honesty like a good cappuccino (not to mention a veal sandwich and a few pastries). is out in the open and on display. Given this. I know they use opamps—did they really believe what they were telling me? Did they really design this way? Then it dawned on me—my friends are basically digital/software designers who. When I CIRCUIT CELLAR® m mentioned my idea for a series on opamps. Three of the pins aren't even used. I just happened to be sitting with friends at my favorite Italian bakery. I'd never get this kind of honest and loud response in the office. and a couple of power pins. one output.circuitcellar. 64 Issue 117 April 2000 www. This will provide for constancy of gain while reducing nonlinearity and distortion. There has certainly been a shift in engineering jobs towards the digital. however. grab a cappuccino and a pastry." Another of my colleagues basically admitted that he had a few op-amps that he was familiar with. he'd just select one. an Italian family bestows on its members a number of things: unconditional love. >>>100K. Those three pins that do nothing on today's opamps used to have a purpose. I'm not talking about one of these bookstore coffee shops where people hush you because they are reading. A place where kids are screaming and an old lady in the back makes food that will let you forget anything. As I know first-hand. kissed. Growing up. with all of its beauty and warts. and then get ready for an earful on op-amps. when you did something wrong. because of a lack of resources. I was. Now. Part Vin + ∑ Va=Vin– HVout – A Vout H Figure 1—The amplifier gain (A) is large. The comments I get back from the group are normally short and nondescript. two inputs. op-amps have come a long way in recent years. are forced to delve into the black-magic world of analog. and a double helping of your favorite pasta. you could be assured of being yelled at until your ears rang. surprised by their reactions. Furthermore.com . Andiamo! 1 4 y neighborhood has finally become civilized—good cappuccino is now within walking distance. The feedback is applied in such a way so as to reduce the output. Why am I telling you all this? Well. The response from one of my friends was unexpected. A place where the Italian culture. I guess the bakery brought out the Italian in them. it is not uncommon to find digital/software engineers taking on the analog role. then suddenly getting hugged. brutal honesty.
it may be said that the more you know about op-amps. tables. operating frequency. and infinite input impedance. and it is here that the engineer must be careful. integrators. offset voltages. The data is there. the datasheet is an engineer. it was One of the problems with datanovel. someone might measure the specifications of the device. If you've been working heavily with op-amps for many years. there are a huge number of op-amps manufactured by several companies. idea. when it comes to op-amps. The Ib–. Op-amp basics are presented also. The broadest demarcation is whether you have an AC or DC application. the more time consuming your selection process. It is this group of engineers that I want to address. Engineers have been known to accuse manufacturers NEGATIVE FEEDBACK of supplying misinformation on their One concept I want to briefly look datasheets. the first place to start narrowing down your choices is the application. The analog computer consisted of several operational blocks—adders. in-depth analog stuff meant for analog designers. and input and output impedance. but don't have time to go back to their textbooks and read Op-Amp 101. while manufacturers at is the concept of negative feedback. sheets is that manufacturers and engiIn 1928. what they mean. I'll look at op-amp specifications such as bias currents. an input analog signal was routed through the operational blocks to solve a differential equation.com What helps the engineer to select a particular op-amp? The main source of information is the manufacturer's datasheet. then with discrete transistors. All op-amp specifications vary depending on temperature. there probably isn't much in this series for you. CIRCUIT CELLAR® Issue 117 April 2000 supportable engineering information. The op-amp is the fundamental building block of analog electronics. the speed of the op-amp is important. and load. However. but the DC performance is not as critical. the information is difficult to present. a great deal of the selection process is nontrivial. This four-part series is about opamp specifications—what they are. Nonideal op-amps (b) have both input and output impedance and non-infinite gain. The only analog computer I've ever seen was brought into class by one of my professors as a novelty. we have no problem with the tremely difficult to present. precision and accuracy are important. When I first envisioned a series on op-amp specifications.A digital engineer may only want an op-amp to follow a current-output DAC. hence the name op-amps. As I mentioned. Basically. Because of the wide variety of applications. Ib+ 0 (no current into op-amp input 30 fA–250 nA datasheet must pins [input bias currents = 0]) market the product and at the same Table 1—This is a comparison of the most common op-amp specifications for both ideal and real-world op-amps. and what to watch for. In DC applications. That person may find the selection overwhelming. but when it was invented. claim that the information is exToday. These operational blocks contained amplifiers. a) V– Vd V+ + – A×Vd Vout b) V– IB– Vd Zi Z0 Vout A(Vd+Voff) V+ IB+ Figure 2—The ideal op-amp (a) has infinite gain. BW Infinite (no frequency effects) 1 kHz–1 GHz Engineers need Vin (Vd) 0 (virtual short) to understand this Zin Infinite 106 Ω. To do this. and finally in the monolithic form seen today. www. With so many op-amps and specifications out there. But even if you have worked with op-amps. it is a marketing tool as Ideal Real-world well as an engineerA Infinite (infinite gain) 80–170 dB ing tool. It became clear to me that there are a lot of digital designers out there who are applying computers to the analog world. The engineer must collect the information from the datasheet and apply it to the application in question. the engineer has to understand what the specifications are as well as the test conditions under which the specifications were measured. but the speed of the op-amp is not as important. To the patent for negative feedback.ers of the day suffered from inconing tool.circuitcellar. I changed the target audience after talking to my friends and looking at Circuit Cellar's subtitle: The Computer Applications Journal. Harold Black applied for a neers use them differently. The best manufacturers can do is provide performance charts. The specifications of op-amps are meaningless without a basic understanding of the op-amp itself. For that I make no apologies. but it must be interpreted properly. You need to pay attention to slew rates and bandwidths. The datasheet is the source of a great deal of debate. I was thinking about heavy-duty. multipliers. Amplifiengineer. 2–20 pF Zout 0 1–1000 Ω dual purpose. and graphs. After all. The series is intended as a basic review for people who use op-amps. time provide real. In fact. The op-amps first were made with tubes. DATASHEETS AND SPECS THE OP-AMP The name "operation amplifier" comes from the original use of these modules in analog computers. In the next three articles. no output impedance. Specifications such as bias currents and offset voltages are of concern. In AC applications. 65 . It is used in a range of applications from simple buffering of signals to complex nonlinear applications. To the manufacturer. Part 1 gets us started by discussing some general topics and basic op-amp concepts.
com CIRCUIT CELLAR® Issue 117 April 2000 67 .000. in such a way as to reduce the output. stancy of gain. (b) Inverting. The fact that you give up some gain is easily compensated for by starting with much more gain than is needed.Vin Vin a) Buffering + – Vout =Vin Rf Ri Vin b) Inverting – + ≈ Ri Ii If R f Vout Vout I i= Vin Ri If= Vout Rf Ii+ If = 0 R Vin V V = out ⇒ in = f Ri Rf V Ri out Rf Ri Vin Ri – + Vout ≈ I Rf I Vout I= V in Ri V = Vin + IR f out V = V in + in R f Ri R = 1 + R f Vin i R Vout = 1+ F V in Ri c) Noninverting Figure 3—There are three basic op-amp circuits—(a) Buffering.circuitcellar. and (c) Noninverting. and distortion. notice the amplifier with a large open-loop gain (A). This process reduces your gain. let's take a closer look at negative feedback anyway. What does negative feedback look like mathematically? Taking a look at Figure 1. nonlinearity. the system characteristics depend less on the amplifier's characteristics (open-loop gain. but in return you get constancy of gain and freedom from nonlinearity and distortion. no feedback) and more on the feedback network itself. regardless of what the patent-dispensing experts thought. Op-amps typically have open-loop gains greater than 100. when he tried to patent the concept. There is a feedback network with a transfer function (H) and a summer that provides the negative feedback by subtracting the output of block H from Vin. "Our patent application was treated in the same manner as one for a perpetual motion machine. Vout = (Vin – HVout)A Vout = VinA – VoutHA Vout (1 + HA) = VinA [2] [3] [1] Vout =1 + Vin A H 1 www. representing Figure 1. How could feeding back some of the output to the input. the whole idea appeared somewhat silly. A portion of the output signal is fed back and subtracted from the input. According to Black."[1] Well. Equation 1. As the negative feedback is increased. help? In fact. is our starting point. Note how the ideal op-amp model can be used to remove the op-amp from the circuit.
Vdd (+)
Vout 1 = Vin H
Expanding equation 1, we get equation 2. Gain is defined as output over input. Manipulating equation 2, we get the expression for gain shown in equation 3. Recall that the open-loop gain is made purposely larger than needed. In fact, in an ideal op-amp, A is infinite. Taking the limit as A tends to infinity, we get equation 4. As long as A >>> 1, the gain of the amplifier depends only on the feedback network. For simplicity, I did not consider the frequency dependence of H and A. To account for frequency, rewrite A and H using the Laplace notation A(s) and H(s). When you stop and take a look at negative feedback today, it looks straightforward. However, I suspect Black's colleagues must have given him a hard time. He applied for the patent in 1928 but did not publish openly until 1934.[2]
– Cd
I source Vo I sink
Current mirror Vee (–) Input stage
Second stage
Output stage
Figure 4—The op-amp is made up of three stages. The input stage converts the differential input voltage signal into a single-ended current signal while rejecting any common mode signal. The second stage converts this current into a voltage and provides frequency compensation. The output stage provides drive and low output impedance.
Figure 2a shows the equivalent circuit of an ideal op-amp. Three basic assumptions are made with the ideal op-amp: • gain A is infinite • input impedance Zin is infinite • output impedance Zout is zero
The op-amp is a differential to single-ended amplifier. The output is simply A × Vd. Any common-mode voltage—that is, voltage that appears on both inputs—is completely rejected. From the above statement, many things are derived. No current flows into the op-amps input terminals, so Zin is infinite. Therefore, Vd is equal to zero. These two results, when combined with negative feedback, lead to the concept of a virtual short. Through the feedback path, the opamp reacts to the input changes in such a way as to keep its inputs at the same potential. Notice I wrote "virtual short" and not "virtual ground." We're so used to seeing one of the op-amp input terminals tied to ground, and therefore setting both inputs at ground, that these terms get confused. The lefthand column in Table 1 summarizes the ideal op-amp and what it leads to. Figure 2b is a real-world op-amp, and some typical values are given in the right-hand column of Table 1. (There are many other op-amp specifi-
Issue 117 April 2000
cations not shown here. The information is intended to contrast with that of the ideal op-amp.) It would appear that the ideal opamp model is not very useful, but in fact it is. The ideal model is often used for first-order calculations. Now, let's take a look at this ideal model with a simple example, using feedback of course. The op-amp has three basic configurations—inverting, noninverting, and buffer. Figure 3 shows that because no current flows into the op-amp input terminals and the op-amp's gain is infinite, the circuit response is determined solely by the feedback network. Thus, we can essentially remove the op-amp from the circuit calculations. The ideal op-amp model works well as a first approximation.
holds the phase shift at 90° over most of the passband. I'll examine this arrangement more carefully when I discuss phase margins and oscillation in later articles. The final stage is a typically AB push-pull amplifier. The output stage provides drive current and low-output impedance for the voltage coming from the second stage.
So, to start out the series this month, I covered both ideal and realworld op-amps, and you saw that an ideal op-amp model is a useful tool. I also looked inside an op-amp and saw that it is made up of three stages—input, transresistance, and output. And, I mentioned some of the op-amp specifications to be examined more closely in following articles in this microseries. Next month, I will look at the opamp input stage and discuss specifications like input offset currents and voltages as well as input bias current. These are termed DC specifications because they are important in lowfrequency and precision applications but aren't of significant concern in high-speed or RF applications. Finally, there's one more thing I think you should keep in mind. The next time you have a meeting or want some real feedback on something, go to an Italian bakery. There, as I discovered, you're more likely to have an honest discussion with your colleagues. And even if you don't, the food is sure to beat your regular coffee and donuts. I Joe DiBartolomeo, P.Eng, has more than 15 years of engineering experience. He is currently employed by Texas Instruments as an analog field engineer. You may reach him at email@example.com.
The op-amp can be divided into three stages—input, second, and output (see Figure 4). The input stage is a long-tailed structure consisting of a high-gain DCcoupled differential input amplifier, a current source, and a current mirror. The purpose of the input stage is to amplify the difference signal present at the op-amp input terminals, while rejecting the common signal. This stage turns the differentialvoltage signal into a single-ended current signal that drives the second stage. Symmetry of the input stage is critical to its performance, as I'll illustrate later in this series when I discuss offset current, bias currents, and offset voltages. The second stage is a transresistance amplifier converting current into voltage. The second stage also provides frequency compensation. Frequency compensation is required so that the open-loop phase shift is less than 180° at all frequencies where the gain is greater than 1. If this is not the case, you get positive feedback and oscillation. The most common method of compensation is dominant-pole compensation, achieved in Figure 4 by adding Cd. This moves the first pole of the op-amp (i.e., the 3-dB point) down in frequency toward the 20-Hz range and
[1] T. Horowitz and W. Hill, The Art of Electronics, Cambridge University Press, Cambridge, 1989. [2] J. Karki, Understanding Operational Amplifier Specifications, Texas Instruments white paper sloa011, 1998.
CIRCUIT CELLAR® Issue 117 April 2000
Drop the Incredible Bulk
Jeff Bachiochi
Using Capacitors as Isolation Components
or years, all modems have contained a great big block of iron. A 600-Ω transformer was used to match POTS (plain old telephone service) line impedance and to form the basis of isolation protection. It is certainly worthwhile for us to protect those linemen who keep our telephone system from deteriorating. And, when a power line falls onto the telephone cables, we (or our equipment) are protected from the hot juices. I'm not one for more government, but safety is an important issue. The data access arrangement (DAA) is a circuit that performs all the necessary functions to provide a
Isolation /Interface
* Reset EOF/GP101 AIN/GP102 ESC/GP103 ALERT/GP104 INT ADC/DAC CLKOUT XTAL1 XTAL0 Clock interface DSP (Data pump)
Control interface
Isolation /Interface
If your application needs a modem, you may want to consider the Si2400. Before you scoff at 2400 bps, Jeff has some pretty good support for the lessis-more argument.
safe interface between your equipment and the POTS. Recently, Silicon Labs designed a silicon DAA with a flexible design, allowing it to cover the individual needs of the global phone community. Although public telephone and telegraph (PTT) compliance is universal, manufacturers of global equipment must comply with the different standards of each country. Until global standards become universal, SL's programmable line interface makes compliance with the FCC, CTR21, JATE, and other PTT compliance organizations a whole lot easier to deal with. As a next logical step, Silicon Labs designed a complimentary embedded modem to take full advantage of its silicon DAA. The Si2400 ISO modem is the first all-silicon modem solution. Right now, you might be thinking to yourself, "A 2400-bps modem, who'd use that?" And if all you need is a faster way to move huge amounts of data, I'd agree. But as you will see, for many applications that just isn't so.
Silicon Labs' modem touts a 75% reduction in space, a 30% cost saving, and a 50% reduction in power. Them's big brag'ns! But, is there any truth to it? I do concur that over the standard PC card modem or its external universal RS232 brethren there is a substantial reduction in parts count, which obviously reduces cost and power usage. The Si2400 ISO modem integrates a microprocessor, DSP, AFE, DAA, and voice codec into this unique two-
SI3015 microcontroller (AT decoder call progress) RX FILT FILT2 REF DCT VREG VREG2 REXT REXT2 RNG1 RNG2 QB QE QE2
Hybrid and DC termination
Ring detect Off-hook
Figure 1—The Si2400 modem chipset handles communications across the 3-kV isolation barrier between the modem and the interface chips.
Issue 117
April 2000
utilintroduction of a ity metering. www. however. The have undoubtedly heard the awful phone charge per call but also the DAA incorporates parallel handset sequence of screeches necessary to ability to handle more connections intrusion detection by monitoring the make a handshake connection beper hour. higher prized PC market. higher transfer-rate counterparts. POTS line voltage (when on-hook) and tween the two modems. That's not the case here. you phone call not only means a smaller be internationally compliant. because the all products rely on low-speed modem used such a level of miniaisn't in production anyturization. hook intrusion. modem didn't underWhat kinds of applications are the With the newer and faster modems stand the continuing need for this targets for such a device? Well. ring detection. and so on. gas pumps. Surely. A shorter tial market by designing the DAA to make a connection to your ISP. the like set-top boxes.chip set.circuitcellar. It looks like over the POTS. advantages of lower parts costs over low. in this case before a connection is established. They. sion before a faster modem has even Silicon Labs has increased its potenIf you've ever listened to your PC established a connection. the actual time for data transmisthe higher transfer-rate modems.com CIRCUIT CELLAR® Issue 117 April 2000 71 . any at the end of the sequence. left for the data to an external site. DAA parameters can be tweaked. This means a You'd think that with this simplifimakes these lower transfer-rate moslower modem can establish conneccation would come a less elaborate dems any competition at all to their tion and complete the data transmisfeature set. offdards until it matches the one of the which require credit card verification. and costs may preclude company that made this product feasibility. products that were I've designed prodalready waiting in the ucts in the past that wings for new technolohave almost become gies to burst forth. tion rates and tries all possible stanlike ATMs. of the search for matching rates begins tage of these benefits are numerous. FEATURES UP the actual connection time that time of faster modems. and secusmaller modem allows rity systems. it's sion can be less than the connection SIZE DOWN. and current limiting calling modem. Not obsolete. The sequence The products that can take advanline current (when off-hook). with the slowest of the communicaThey include point-of-sales terminals affecting the DC and AC termination. only seconds) is wasted other manufacturers. Besides the obvious When the data that must be passed is someone at Silicon Labs saw the need. ringer impedance. adding an RS-232 converter and modular phone jack is all you need to connect the module to a PC. a lot of kind of product. like many product that needs to communicate time (actually. and industrial and medical monitoring to comply with individual country Figure 3—The Si2400 modem module can be made by adding a few discrete parts to the Si2400/Si3015 modem chipset. The particular Figure 2—Although the Si2400 has additional I/O. more.
The power-up default rate is 2400 bps.) Both DTMF generation and detection are supported. (Hmm. As digital outputs.com . Each on/off time listed has a delta time associated with it. 2400 bps. and control data is passed to the DAA from the data modem chip through a capacitor isolation barrier. Security Industry Association (SIA) pulse. DRESS CODE Because one of the main objectives of this chipset is to reduce the overall size of a modem. Caller ID detection and decoding are supported for many countries. receive. generic digital. but the user must use the CTS handshaking line if the interface rate is anything other than the modem rate. The full 16 DTMF characters are supported (unlike a phone's dial pad). In addition. The cadence can be off plus or minus this delta.25-based fast connect. and other security protocols are supported. alternate pins for TX and RX (possibly for adding a second processor). and an alert output. 1200 bps. Call progress tones are decoded through the use of BI-quad filters. Take one look at Table 1 and you'll see just how non-standard the world's phone system is. the Si2400 chipset comes in a one-size-fits-all packaging (two 16-pin SOIC packages).circuitcellar. Transmit. However.23/Bell. 300 bps. V.23 reversing. and V. 1200 bps.3 V. V. they can be reached through the data modem's S-registers.22/Bell 212A. TX and RX are the only requirement if connection transfer rate is the same as the interface transfer rate. Four GPIOs (general purpose) can be programmed for digital I/O or alternate functions. The data modem can use many data formats. specifications. Alternate functions include audio input.3. these pins 72 Issue 117 April 2000 CIRCUIT CELLAR® www. The chipset supports both 3. All numbers in Table 1 are 10-ms time units. Although up to eight signals can be interfaced. The serial interface rate can be changed via an S-register. such that no negotiation is necessary. Fast-connect mode assumes both originate and answer modems are preconfigured. The data modem automatically sets up the parameters for the U. V. A reset input is available to totally restart the modem set. I think I smell another project here somewhere.and 5-V operation with power consumption ~50 mW at 3. an escape input.Photo 1—This module was easily mounted on a prototype board to create the PC interface circuit shown in Figure 2.21/Bell 103. V.22bis. including V. Also.S. Silicon Labs provides a good breakdown of the ring and busy cadences used by many countries of the world.
where bbbbbbbb is 8 binary digits) Read 'S-register' in Binary (rbbbbbbbb. ISO BARRIER The Si2400 modem is a chipset because of its unique isolation barrier. where bbbbbbbb is 8 binary digits) Monitor 'S-register' in Binary (mbbbbbbbb.com . A capacitive barrier is used instead of the usual transformer isolation. M2= on. M3=on after last digit dialed until carrier Pickup (go on line) V. S##=##. plenty for status LEDs. which handles the high-speed. Canada (default) Table 1—This list of ring and busy cadences for various countries shows just how far we are from a world standard. Korea Malaysia Mexico Portugal Singapore Spain Sweden Taiwan US. 74 Issue 117 April 2000 CIRCUIT CELLAR® www.circuitcellar. The same ISO cap interface is built into the line side Si3015 DAA Answer the Line Immediately Tone Dial (#=number to dial) Pulse Dial (3=number to dial) Local Echo (E0=on.Country Ring (on) 7 18 18 18 18 14 14 28 18 6 18 … 7 7 7 18 … … … … … 18 8 18 18 7 28 18 18 75 Ring (off) Ring (delta) Busy (on) Busy (off) Busy (delta) 3 93 56 75 75 140 93 65 75 4 75 … 4 3 4 75 … … … … … 37 4 75 93 4 56 93 37 37 1 4 4 4 4 4 4 4 4 1 4 … 1 2 1 4 … … … … … 4 1 4 4 2 4 4 4 4 37 30 50 25 35 25 25 50 50 37 30 … 50 75 50 50 … … … … … 50 35 25 50 75 20 25 50 50 37 30 50 25 35 25 25 50 50 37 30 … 50 75 50 50 … … … … … 50 65 25 50 75 20 25 50 50 2 2 2 2 2 2 2 2 2 2 2 … 2 2 2 2 … … … … … 2 1 2 2 2 2 2 2 2 Australia Austria Belgium Brazil China Denmark Finland France Germany Great Britain Greece Hong Kong New Zealand India Ireland Italy Norway Israel Netherlands Thailand Switzerland Japan. can sink 40 mA (20 mA at 3. M1=on until carrier. where bbbbbbbb is 8 binary digits) Software Reset Wakeup on Ring (sleep until ring) Table 2—These are a subset of AT commands supported by the Si2400 modem module. A Command A DT# DP# E H I M O RO S w## r# m# Z z Function chipset is necessary to handle both sides of a 1-bit data bus (see Figure 1).23 Reverse Read/Write 'S-register' (S##?. the Si2400 modem chip has a DSP datapump. On the host side. where ## is 2 hexidecimal digits Write 'S-register' in Binary (wbbbbbbbbbbbbbbbb. E1=off) Hangup (go off line) Return Product Code + Chip Revision Speaker Control Options (M0=off.3 V). bidirectional communication via an ISO cap interface.
Be careful. and codec. upper and lower case letters contain unique codes. t Function Bury Tone Detected Ringback Detected Incoming Ring Signal Detected No Carrier Detected Modem OK Response SAI Contact ID Kissoff Tone Detected Connect Connect 1200bps (V. With this configuration. His background includes product design and manufacturing. See Table 2 for the command set summary. face for direct connection to a PC by adding a level shifter (MAX232) and a RJ-11 (see Figure 2). COMMAND SET Similar to other standalone modems.silabs. I Jeff Bachiochi (pronounced"BAH-keyAH-key") is an electrical engineer on Circuit Cellar's engineering staff. you can experiment with the modem using your favorite communication program. which handles DC/AC termination. you can make a quick RS-232 interwww. ring detection. See Table 3 for a list of these codes. SOURCE Si2400 modem chipset Silicon Laboratories. chip. the Si2400 supports a subset of the AT command set intended for use with a dedicated microprocessor. I am quite excited about this new approach to low-cost.com 75 . He may be reached at jeff. you can see the small surface mount module I designed (see Figure 3). Because the chipset is highly integrated to provide specific functionality. Inc. In Photo 1. low-speed modems.com.Resultant code B r R N O K c d S H f x l L x I m a v w ^ . This should set them up nicely as fierce competition for the growing embedded modem market. The individual chips are essentially useless on their own. Transmit. Silicon Labs has indeed been thorough in its design for global compliance. Allowing the designer or user to alter interface parameters through registers via the AT command really makes global compliance an easy beast to conquer.circuitcellar.bachiochi@circuitcellar. receive. The modem also has a set of singlecharacter resultant codes to communicate its status to the host processor. let it be noted that a simplified DAA chipset is available for those who need to roll their own.22bis modem) Resending SIA Contact ID Data Modem Automatically Hanging Up Hookswitch Flash or Battery Reversal Detected On-hook Intrusion Detection Detected (phone off-hook) No Phone Line Detected Phone Line Detected Over Current Detected After an Off-hook Event On-hook Intrusion Completed (phone on-hook) Caller ID Mark Signal Detected British Telecom Caller ID Signal Detected Connect 75bps (V. (512) 416-8500 www. with "AT" preceding the command and ending with a <CR> (carriage return). Commands are surrounded by an AT packet.com CIRCUIT CELLAR® Issue 117 April 2000 SIMPLE PC INTERFACE Although the Si2400 chipset is designed for embedded applications.23) Si2400 Woken Up Kissoff Tone Detection Required Dialing Complete Dial Tone Table 3—These resultant codes are returned by the Si2400 modem module in response to AT commands or line status. Although. the transparent interface can be viewed only as a means to isolation. and control data all pass through the ISO cap interface.
I don't need the fire. these days "getting out" has devolved into sitting in traffic jams with all the other misguided people. It's not as oldfashioned as you think. The comparator on the right drives the OUTPUT low when the THRESHOLD input reaches twothirds the supply voltage. but that won't stop Tom from settling down with his TTL Cookbook and reflecting on what made the '555 so delightful. Proving my wife wrong. I turn to the a dusty bookcases filled with yellowing silicon dreams and aspirations. but don't touch my TTL Cookbook! A classic of its time (1974). though old as the hills. was a workhorse that found its way into all manner of early digital designs. the same '555 from 25+ years ago still sells today. Except here in Silicon Valley. h.SILICON UPDATE Tom Cantrell A Winter Timer Tale The weather outside may not exactly be frightful. Output stage RESET 4 VCC (INT) R 5 CONTROL VOLTAGE 76 Issue 117 April 2000 CIRCUIT CELLAR® www.circuitcellar. the TTL Cookbook helped tutor an entire generation of neophyte bitheads. where is that Z8000 manual?). many subsequently fulfilled but just as many dashed. though. discussed in the TTL Cookbook. Anyway. where the weather's so nice I feel like I should be out enjoying it. When the TRIG- GND 1 8 *VCC TRIGGER 2 Comparator R 7 DISCHARGE OUTPUT 3 Flip-flop R Comparator 6 THRESHOLD Figure 1—Timing is everything they say and.com . the venerable '555. Admittedly. you find a few dozen transistors. I certainly can't take the risk of throwing out a baby like the TTL Cookbook by Don Lancaster. GOOD VIBRATIONS Though quaint by today's Systemon-Chip standards. Checking under the hood (see Figure 1). before all you snowbirds get envious and pack up to head this way.[1] Yes dear. keep in mind that the nice weather won't be much solace in a few months when folks watch their grass die because they used their meager water ration to wash the car. testimony to the timeless practicality and elegance of the design. The OUTPUT can also be driven low directly with the RESET input. you can get away with tossing some obscure items while I'm not looking (Come to think of it. Now. continuing popularity proves that the '555 takes a licking and keeps on ticking. The low OUTPUT turns on the DISCHARGE transistor. Remarkably. with the bath water. providing hours of hands-on entertainment in an era when other diversions were the Brady Bunch and disco. I'll stick with the datasheet and scope. curling up in front of the fire with an exciting datasheet and the new scope Santa left under the tree. the winter season. but I can't bring myself to chuck them. some of these books haven't been cracked in years (make that decades).
proper values for two external RTR/*RTR 6 Because accuracy varies deresistors and a capacitor. but in practice. Circuit Cellar 111).e. in addition to the reset simple. using an RC. multivibrator. principle. Like other would-be '555. GER input goes below one-third RTC CTC S0 S1 S2 S3 the '5555 offers the luxury of the supply voltage. acquired by The '81B is a simpler variation common to see a trimpot used in Philips some years back. it's down to fractions of 1 Hz. board space. The RTR/*RTR few external resistors and capaciconfigures the device as retors. ently and you get a monostable multiIn the case of the '5555. slower. Of vibrator (also known as a one shot) ripple counter. sponse to the trigger. I tion variations resulting from a parbered 74HCT5555 in a 1993 Philips made a quick cutback when I noticed ticular PCB layout. Also. delivers stages (the first and last eight) can be low at only 200 µA. or an external input. I find the appropriately num(Silicon Update. I'm itching to wire Not to say the '555 is perfect. something up. Much like a modern MCU. pulse-position modulator.circuitcellar. B). Fortunately. the range of adjustTRIGGER 5 Input chattering ment (roughly a few microseconds to Power on rejection circuit 8 VDD clear circuit a few seconds) is relatively wide. The oscillaDAY-TRIPPER modulator. it's quite may recall that Signetics. and so on. the 74HCT5555 quency and divide ratio. so versatile. way to 20 MHz with a crystal. and from 32 kHz all the nice weather. was a TTL than the '5555. Old-timers the S-8081B CR Timer (see Figure 3). By selecting the *B 5 Output circuitry 7 *Q stage There are some catches. as the name implies. www. and tricks and tweaks can turn a '555 into CTC) can be driven by an RC. you can pending on the oscillator freget anything from close to 1 MHz Figure 2—One of the first of a new breed of digital '555s. a number of better pseudo-'555 when I was surfing the cent error) because of tolerances and '555s have been introduced. not to mention the Figure 3—Long duration timeout (10 s to 10 h) and low-power (200 µA) are the Seiko S8081-B's claim to fame. *Q) and trigger inputs DISCHARGE transistor. databook (see Figure 2). wading through the bookcase on their 7600A embedded 'Net chip resistors and capacitors. also known in the nomencla4 (no startup delay). timing is digital. relying on a counter rather than anadatasheet's specified limits for the Wire up the '555 slightly differlog circuits. For exSeiko web site to check out the latest temperature characteristics of the ample. although only sixteen further merit. the S-8081B is known for being voltage ratio rather than by absolute '555 successors. it has major While the '5555 is faster than a because timing is determined by a improvements. it's a 24-bit resistor and capacitor accommodate a timing range from 10 s to 10 h. Although it is digital.. timing is completely determined by favor. Make that much slower—the reference. once dialed in. ably immune to supply voltage drift. RTC. isn't nearly as accurate as a crystal WELCOME IN THE NEW I stumbled across another novel (few percent versus fraction of a perOver the years. good match for battery-driven apps. but Input SET 2 circuit no one would complain if it was Voltage 1 VSS wider. To counter these effects. tor can handle from 1 Hz to 4 MHz Enough of this paper chase and the linear ramp generator. a crysa frequency divider. not to menagain. making the chip a one cycle of the timed output in reselected.com CIRCUIT CELLAR® Issue 117 April 2000 77 . a '555 oscillator in terms of both accuracy and range.Stage counter OSC CD (A. Power on triggerable or not and Probably the most common reset OSC_CON determines whether application is simply an oscillaMR 15 the oscillator runs at all times tor. sticking with standard catalog values) for the external CR 7 3 OUT Output Oscillation Control tout resistor and capacitor cramp the '555's DISCHARGE 6 20-stage FF selector logic level shift circuit style a little.Thanks to eight extra pins. a '555 is remarkThe '5555 is similar to the '555 in the external resistor and capacitor. '5555 bests the analog original Of course. the ubiquitous trimpot makes for cost. with freshens the design while remaining true to the spirit of the original '555. or only when ture of yore. regulator RESET 4 Input circuit Finally. yet with the addition of a CON 14 input (MR). so the timing to be fine-tuned. power consumption is that. and Philips has carried the 20-stage divide ratio is fixed. hassle of manual adjustment. So 24. In its that legacy forward. the OUTPUT 2 3 10 11 12 13 both active high and low outis driven high. as an astable A 9 *Q Monostable triggered (low power). pulse-width tal. Santa Datasheet specifications and practical limitations (i. safe to say that the digital the duty cycle of your choice. place of one of the resistors to allow powerhouse. turning off the RS 1 CP puts (Q. and packaging headaches. Other circuit the oscillator (pins RS.
50/50 oscillator at maximum frequency) using RAM for the configuration. www. came through with delivery of a shiny new ZSBI050 from Zilog (see Figure 4). clock serial interface.circuitcellar. the ratio between the two. the '050 is kind of an OTP '555. It's an easy matter to pump in 35 bits to configure and calibrate the chip for subsequent OTP programming. in that it incorporates fuses that allow a configuration to be permanently burned into the chip. as shown in Figure 5. Second. the chip powers up in a default mode (all 0s.SCLK SLEEP VPGM REF Bandgap V source INPUT Input control (trigger mode) Counters Output control Programming logic and OTP memory OUTPUT Figure 4—The latest in a long line of '555 wannabes. The latter process involves individually shifting in and programming each 1 bit to limit current flow during programming. the Zilog ZSBI050 incorporates several advances: wider range. The '050 is unique in three major ways.. Like the other chips. The output of the fixed dividers feeds a pair of 10-bit fully programmable divide-by-n counters. and OTP configuration. The programming voltage is 7 V. but the similarity stops there. but because a dedicated VPGM pin can be left open during normal operation.e. Thirty-five bits of memory define the operating modes and timing. the '050 utilizes a clocked serial interface (SCLK and SDATA) for setting the divide ratios and other operating parameters. Until programmed. First. it's easy to accommodate production-line programming. the complement of dividers is increased to five. Finally. thus setting the duty cycle. i. Three fixed (two divide-by1024 and a divide-by-32) dividers can be individually enabled or disabled. the basic timing for the OUTPUT is established by an external resistor on the REF pin.com CIRCUIT CELLAR® Issue 117 April 2000 79 . rather than dedicating pins or compromising the number of selections (as in the '5555).
SDATA is a gate input it working to raise (and answer) the that enables or disables OUTPUT. I had to kind of ZSBI050 an easy design-in. the oscillator frequency ing is easy enough. 80 Issue 117 April 2000 CIRCUIT CELLAR® www. configurable for ever. falling.com . On one page of the mined by the formula: document. The top trace is SDATA. and the bottom trace Output. and GND and hang a resistor between The OUTPUT frequency is deterREF and GND. SDATA acts like '050 seemed simple enough with only 8 pins and 35 bits to deal with. Just hook up 5 V ranges from about 10 kHz to 4 MHz. it says the '050 "requires no external components other than Fosc Fout = ×K one fixed resistor. I've found there's nothing like rising. Depending on the value of the REF Verifying the chip is alive and kickresistor. respectively) with SDATA used as a gate input. In oscilactually wiring up a chip and getting lator modes. Plug in the numbers and you'll find the possible timing range covers a huge amount of territory. (a) and (b) show the '050 configured as an oscillator (50/50 and variable duty cycle. (c) and (d) show non-retriggerable and retriggerable one-shot modes with SDATA as the trigger. the In one-shot mode. questions the datasheet overlooks. anywhere from a microsecond to more than a month! TIME-TRACKER With a rather sparse preliminary datasheet in Photo 1—Eight pins and a simple clock serial interface make the hand. in the (2 × divide-by-n)+4 AC/DC specs.circuitcellar. feel my way with the chip. Howthe trigger input." Yet. or both edges. it alludes to the need a) b) c) d) Photo 2—The ZSBI050 in action. On the surface.where K is the product of enabled fixed dividers.
be careful that SDATA only changes state when SCLK is low. but you can leave SCLK.0.~ CONST zslp = ~OUT $8002.0. I decided to believe the less-is-better version and found the '050 seemed to work fine with just a resistor.1 = non-retriggerable one-shot */ DATA 0.1.1 = falling edge 1. according to the datasheet.com CIRCUIT CELLAR® Issue 117 April 2000 81 . corresponds with about a 200-kHz internal frequency. I scrounged around and came up with an 82-Ω resistor.1. I saw a nice clean 50-kHz or so square wave on OUTPUT.0.0 /* primary divider */ DATA 0. PROGRAM ZSBI050 INTEGER i.0. running at one-quarter the frequency selected with the REF resistor.0 = rising edge 0.Fixed divide by 1024 M U X Fixed divide by 1024 M U X Fixed divide by 32 M U X Divide by N (10 bits) Divide by N (10 bits) Duty cycle logic Figure 5—How slow can you go? With five dividers.0 = 50/50 duty cycle oscillator 0.0. The '050 accepts SDATA on the rising edge of SCLK but don't overlook the 10-µs setup and hold time spec.circuitcellar. Having established that the chip was alive.0.0 = retriggerable one-shot 1.0. Powerup and.0.0. and SLEEP lines to a BASIC single-board computer and threw in an LED for kicks (see Photo 1).0. Don't forget to connect SDATA to 5 V to enable the OUTPUT.x = both edges */ DATA 0 /* divide by 32 */ DATA 0 /* divide by 1024 */ DATA 0 /* divide by 1024 */ DATA 0.0 /* mode select */ /* 0.0.0. and SLEEP shuts down the '050. Sure enough.0.0 /* trigger select */ /* 0.0.0 /* duty cycle */ DATA 0 /* memory protect */ FOR i=1 TO 35 READ j zdata j zclk 1 zclk 0 NEXT i zdata 1 END www. Also. Note the Wait statements that guarantee the required 10-µs setup and hold time. for a reference capacitor as well.0 /* reserved */ DATA 0. the chip should come up in the default mode of operation as a 50/50 duty cycle oscillator. SDATA. I proceeded to wire the SCLK.j CONST zclk = ~WAIT 1:OUT $8000.0 /* reserved */ DATA 0. and VPGM hanging in the breeze. Just to confirm that SDATA gates the OUTPUT.$80 /* init PIO */ DATA 0. I wrote a short program that simply reads 1s and 0s from Data statements and bitbangs them over to the chip (see Listing 1). which. lest you inadvertently put the chip into OTP programming mode (invoked by rising edge of SDATA when SCLK is high).1 = variable duty cycle oscillator 1.~ CONST zdata = ~WAIT 1:OUT $8001. To configure the '050.0.0. Listing 1—A simple program is all it takes to configure the ZSBI050. the ZSBI050 can hold its breath for a long time. SLEEP.0. as mentioned earlier.~ BEGIN zclk 0 zdata 0 zslp 0 OUT $8003.
Should I shift the 1st or 35th bit first? Same for multibit fields like the divide ratio—do you send the most or least significant bit first? "If in doubt.com ZSBI05 Zilog Inc. But. either can be used in situations where a low-count terminal module is needed. that the last bit (Memory Protect) is the key. Often they can be purchased in metric (5. Lancaster. Indianapolis. IN. it would be the same as one fresh out of the tube. You may contact the quizmasters at firstname.lastname@example.com. The modules can be connected side by side via a tongue and groove on each piece. So. you'd think there'd be little need for simple chips like the '555 and its successors. It wasn't long before I was successfully in command of the '050 and able to try out the various features and modes (see Photo 2).. Howard W. try it out.. I Tom Cantrell has been working on chip. but the chip was ignoring it. Every time I powered up the part I'd just programmed. C." I say.I was ready to pull the trigger when I realized I wasn't quite sure who's on first (i.com S-8081B Seiko Instruments ICs (408) 433-3208 Fax: (408) 433-3214 www. With such a small difference spacing between pins.com 74HC/T5555 Philips Semiconductors (408) 991-5207 Fax: (408) 991-3773 www.cantrell@circuitcellar. how does the '050 know whether to come up in RAM or OTP mode? It turns out (confirmed by a call to Zilog).semiconductor. Sams & Co. and what does it mean? What's your EQ?—The answers and 4 additional questions and answers are posted at www. You can reach him by e-mail at tom. or were they discontinued? Problem 4—On what type of device will you find the notation "REN=x. and systems design and marketing in Silicon Valley for over a decade. Having explored the '050 operation in RAM mode. and everything works as expected. This got Johnny thinking about the obviously missing A and B size batteries. REFERENCE [1] D.com TIME'S UP In these days of zillion-transistor chips. SOURCES LM555 National Semiconductor (408) 721-5000 Fax: (408) 739-9803 www. The divide-by-32 bit had been successfully programmed all along. AAA. Why is it important to keep these separated in the parts crib? Problem 2—The ceramic capacitor size 1206 is the same physical size as the tantalum capacitor size "Y". were these bad designations. can Johnny use the same pad dimentions for both types? Test Your EQ Problem 3—Johnny was perusing the local drugstore's display of batteries.com.zilog. At the last second. 1974.circuitcellar.national. (408) 370-8000 Fax: (408) 370-8056 www. board.philips. But the question is. was the pharmacy temporarily out of stock on those items. I'd been trying to program a single bit (the divide-by-32 bit). but sometimes a simple tool is best for a simple job. Because both types of capacitors are the same size. I made an admittedly hacker-type attempt to grapple with the programming algorithm and blow the OTP. TTL Cookbook.seiko-usa-ecd. Hack the program to blow that 35th bit. Johnny is laying out a PCB that uses both.x". 2 8 .e. it didn't seem to work. the datasheet didn't make the "endian-ness" of the chip real clear). more EQ questions each month in Circuit Cellar Online see pg. and it was easy enough to deduce the internal layout by judiciously shifting a single 1 bit.0 mm) or English (5. a bit of pondering led me to realize the simple error of my ways.08 mm) spacings. and D size batteries. Hanging there on the display were AA. Its function is described as "preventing further programming" but probably should also include the fact that the OTP is ignored until this bit is set.com or by telephone at (510) 657-0264. CIRCUIT CELLAR CIRCUIT CELLAR Problem 1—Screw terminal blocks usually come in modular form with two or three terminals per block.
Inc.56. Inc. JK microsystems JR Kerr Automation & Engineering J-Works. Inc. Triangle Research Trilogy Design Two Technologies Vesta Technology Vetra Systems Corp. Creative Control Concepts Crystalfontz America. RMV Electronics. Dataman Programmers. Conitec Connecticut microComputer. Instant Instrument Intec Automation. Page 88 94 79 84 93 66 74. Inc. Scidyne Page 68 91 84 92 86 91 41 84 90 25.C2 86 84 94 85 92 88 55 92 72 87 93 10. ZiLOG EMBEDDED APPLICATIONS www. Pontech.0 118 95 IE W . Inc. Lemos International Laipac Technology. Senix Corp. Inc. Beige Bag Software Borge Instruments Ltd. Copeland Electronics. Decade Engineering Page 89 4. General Device Instruments General Software Hagstrom Electronics Huntsville Microsystems.82 69 87 15 90 33 84 92 44 94 48. Inc.78 90 Matrix Orbital Corp.ADVERTISERS INDEX The Advertiser's Index with links to their web sites is located at www. Inc. WCSC Weeder Technologies Wilke Technology GmbH Wirz Electronics Z-World Zanthic Technologies Inc. Inc. Inc. Inc. Ltd.) Future Electronics Inc.com CIRCUIT CELLAR® PR Issue 117 EV April 2000 A Reliable Network For Embedded Systems— Getting On Track Weather Data—Getting More than One Wire's Worth Computer Control Of A Motorized Telescope Build A Risc System In An FPGA— Part 3: System-on-a-Chip Design Buying Power—Low-Cost Power Supply for Embedded Applications The Shocking Truth About EMC—Part 2: Practical Applications I Embedded Living: HCS=Heating Control System? I MicroSeries: Op-Amp Specifications—Part 2: Getting Some Input I From the Bench: Digital and Analog Output Control—Taking Route X-10 I Silicon Update: On the Road Again EPC Real-Time PC: Real-Time Excutive for Microprocessor Systems—Part 1: Introduction to RTEMS EPC Applied PCs: Under the Covers—Part 2: Applications via NT Embedded 4.circuitcellar. Inc. ADAC Advanced Transdata Corp. Midwest Micro-Tek MJS Consulting. Page 93 91 94 16 73.72 86 34. Inc. NetBurner Nohau Corp.5 18 67 85 90 56 92 31 18 85 7 91 50 85 92 89 69 18 89. Inc. Bay Area Circuits Becterm Inc. CAD-UL CCS (Custom Computer Services) Ceibo ChipTools. Microchip Micromint.E. Inc. IMAGEcraft IndustroLogic. Link Instruments Lynxmotion.circuitcellar. Rabbit Semiconductor R. Parallax Phoenix International Corp. Inc. Signum Systems Sirius microSystems SMTH Circuits Softaid Solutions Cubed Square 1 Electronics Technicraft.90 17 88 85 49. DreamTech Computers ECD (Electronic Controls Design) Earth Computer Technol EE Tools (Electronic Engineering Tools) ELNEC EMAC Inc. Technologic Systems Technological Arts TechTools Tern. Inc. ActiveWire. Inc. International Electronics Corp.93 81 85 86 C4 94 Abacom Technologies Ability Systems Corp. Inc. Inc.com under the current issue. Phytec Picofab. Saelig Co. Pulsar. MCC (Micro Computer Control) megatel MetaLink Corp. Inc.C3 87 93 68 87 85 86 88 89 45 1 90 89 94 23 Scott Edwards Electronics. Inc. Inc. Inc. Prairie Digital. microEngineering Labs. Inc. Inc. Avocet Systems Axiom Manufacturing Bagotronix. Inc. Smith Remote Processing RLC Enterprises. Embedded Micro Software emWare Engineering Express FDI (Future Designs. Inc. Virtual Tools. Inc. Novasoft On Time PCB Express. All Electronics Allen Systems Amazon Electronics Andromeda Research Antonius Digital AP Circuits Ascendco Scientific.91 91 91 94 45. Intronics. 89 69 86 87 88 9 88 Digital Products Co. Monterey Tools Company Mosaic Industries. Interactive Image Technologies.80 75 92 92 94 90 90 27 92 63 94 90 91 86 93 57 25. Inc. Inc.
Somehow after all the experiences. and yes. The consistency was like moist sand. back then we didn't have as many of today's behavioral restrictions or statutory impediments. and chemicals were certainly easier to get and cheaper for "experiments" than the conventional sources for ICs. I didn't have to be a real engineer to realize the purpose of my timer! "What was that last stuff in the pill bottle?" "Lead Azide. Steve?" I'm not sure whether they were genuinely interested or whether they had some skepticism that I'd actually make it to adulthood. at least we don't have to wait an hour. let's go!" he said as he jumped up and started running toward the timer end. I'd even like to say that I learned not to play with dangerous things after the experience I just related. Before I could protest. those kinds of comments make me feel like I should go out of my way to remind everyone that I made lots of mistakes on my way to being an engineer. I nervously added a little levity. huh?" All I could think was that everyone in Eastern Massachusetts had probably heard the blast. It wouldn't have been so bad if the firemen had just opened all the doors rather than breaking the windows…." "We wouldn't have to anyway. The term "chemical experiments" instantly took on a whole new meaning. So why am I telling you all this now? It's really a reaction to all the people who write to me or come up to me at shows and thank me for inspiring them to be engineers.circuitcellar. In truth. there was a giant explosion. I looked up and noticed that a boulder thrown by the blast had sheared off a 6″ diameter tree trunk three feet above my head. I wonder if the Steve Ciarcias of today have a chance to clean up their act before society puts them in a rubber room. all he wanted was a circuit that could be set from 0 to 1 hour with one-second precision and would fire a flashbulb at the end of a wire when it timed out. "What do you want to do when you grow up. But. Destiny worked against that career pursuit. there were people around who were crazier than me. He just attached the wires and yelled "Run!" We stopped about 350 feet from the timer and hid behind some rocks. In high school. Danny Boy. I'm just troubled that it might be reality. if anything. "Nitrobenzene with an oxygen accelerant. both good and bad. and then pushed the pill bottle into the bag of wet powder. he pulled out a little plastic pill bottle with about half an inch of white powder in the bottom. I wonder how I would have turned out if I had to deal with today's evaluation of my behavior as a youth. He stuck the AG1 flashbulb in the powder. he didn't want to pay until he tested it. many of us would be serving five to ten. that's a story for another time." he said matter of factly." I dutifully did as instructed and then came back. "What the @#$% was that?" I yelled. To this day I swear someone switched potassium chlorate for the potassium nitrate I was fusing together with sugar to make the propellant. he had the wires attached to the timer and had set it for five minutes. "a chemical engineer. In retrospect. i steve. I suppose I should have been a little more concerned about the location. He pulled out a 5-lb bag of white crystalline powder and a pint of oily looking liquid and mixed them together. "Well. There was a 6′ deep crater in front of the outcropping. however. I think I turned out OK—certainly good enough to have affected a few people positively. That was the stuff they put in blasting caps. In truth. While I truly appreciate the complements. It seemed simple enough. It took a third traumatic message to set me on the straight and narrow. I usually answered the whatdo-you-want-to-be question with. Acrid smoke surrounded me and dirt was still falling from the sky. I always wanted to be an engineer. Of course. "Put the flashbulb there and string a wire back a hundred feet or so and put the timer next to it. but a deal is a deal. I had a mad-scientist reputation (I'll bet you never would have guessed that) and I was always building electronic gadgets. Out in the middle of the woods he stopped and pointed to a rock outcropping and said. Finally. Taking a breath. but that wasn't the case. "OK. The second message came in the form of peer obligation. Of course." I was moderately enthused about chemistry. Hanging around this kid could be bad for my health. if most of us look back at the things we did in our "technically inquisitive" growth stages and applied today's conformity-conscious climate. I took an order from a fellow student to make an electronic timer. The first message in the mist (literally) was that little rocket fuel experiment I did one afternoon in the high school chemistry lab. stuffed some putty in on top of it. In fact. Always eager to make a buck on my expertise. but I can remember being a kid and my relatives asking. My personal evolution leads me to wonder if we react too severely today. when I hardly knew the difference between professions. The blast was so powerful my ears were ringing." I thought.com 96 Issue 114 January 2000 CIRCUIT CELLAR® www. This isn't a trick question and I don't have an answer. "what have I got myself into?" Before I could finish analyzing how the present situation was undoubtedly accelerating my reputation from merely being "that science guy" to being on the list of "most wanted". I realize that he had never asked if the timer worked. That mixture isn't stable that long!" "Holy mackerel. I also tend to criticize our overly obtrusive society norms.com . I don't let it go to my email@example.com INTERRUPT All Things Considered 'm getting a little long in the tooth now. Not bad.
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