text:
Share with your friends:
Performing Artists (Click on Artist for Reviews and Previews)
Show Details
- Ticket Price: $25.00 - $115.00
- Door Time: 9:30 PM
- Show Type: Comedy
18 & over
2 Beverage Minimum Per Person
Non-Refundable & Non-Transferable
Robert Kelly's comedy is deeply rooted his own life and relationships which makes it honest, abrasively funny, yet refreshingly vulnerable. He has been winning over audiences for years touring clubs, colleges and theaters, including repeat performances at Montreal's Just For Laughs Festival.
His new hour special Robert Kelly: Live at the Village Underground debuted on Comedy Central and is now available on Netflix. Besides being a fixture on Comedy Central, Robert plays Bam Bam in Denis Leary's FX show Sex&Drugs&Rock&Roll, which will air again this summer. He can also be seen as Louie CK's brother Robbie on the hit series Louie. His other acting credits include roles in Trainwreck, Maron, Benders, Nurse Jackie and Inside Amy Schumer. Robert currently hosts the top rated podcast "You Know What Dude?" that can be found on iTunes. Robert is also the co-founder of the RiotCast podcasting Network.
Tweet Feed
- 2nite @ 8p #wellRED Comedy w/ @traecrowder @averagedrew @coreyfcomedy! Only a few tix left bit.ly/2999GCT pic.twitter.com/stUBd77yOb 23 h
- @BenningtonShow @RichVos Purchase Tix @ bit.ly/295D288 23 h
- Ready 4 #TuesdayMotivation? 2FOR1 Tix 2nite @ 7p w/ @aaronbergcomedy & more! Use Code: 24TUE bit.ly/28ZSSwI pic.twitter.com/hnuZYZKMDo Jun 28
- RT @traecrowder: NYC we will be at @GothamComedy on June 30 and need your help spreading the word! @averagedrew @coreyfcomedy Tix: https:… Jun 22
- #NYC! This Thurs 6/23 is the last episode of the season #axsgotham @AXSTV w/ @chrisdelia hosting! Get tix NOW bit.ly/28R9ry9 Jun 22


text:
You're in Computer Keyboards
Narrow Search Results
Price Range
By Seller
By Keyword
Related Searches
Adesso ACK-730PW Industrial Keyboard - White
PS/2 - 109 Keys more
|compare prices
Roccat Ryos MK - Keyboard - USB - US Qwerty - black - ROC-12-601-BK
The most advanced, most customizable mechanical keyboard ever - NOBODY comes close! Introducing the ROCCAT Ryos MK - advanced mechanical gaming keyboard. With an eye-watering number of configuration options and high-quality CHERRY MX key switches, you... more
$99.99 $89.99
FREE shippinggo to store
Interlink Electronics SMK-Link Electronics Wireless Ultra-Mini Touchpad Keyboard - Keyboard - wireless - 2.4 GHz - Qwerty - VP6364
The Wireless Ultra-Mini Touchpad Keyboard is the ideal companion for text entry and pointing up to 33 feet away. The game controller-like shape is comfortable and instantly familiar in the hand. The integrated touchpad provides accurate and quick... more
FREE shippinggo to store
Roccat Ryos MK Glow - Keyboard - USB - US Qwerty - ROC-12-751-BK
Thanks to a high-powered LED underneath each key, the illuminated Ryos MK Glow glows like no other - so you can hunt for your prey instead of your keys. And since you can choose the illumination level that suits every lighting environment, you can... more
$139.99 $109.99
FREE shippinggo to store
AGS Laser Projection Bluetooth Virtual Keyboard & Mouse with Build in Display Screen
- Easliy pair laser projection keyboard & mouse for your Iphone, Ipad, Smartphone, laptop or tablets- For devices with bluetooth, operation systems: Windows, iOS, Android, Mac OS- English QWERTY keyboard layout- With Mouse Funtion,Input method can be... more
|go to store
Arabic and English Computer Keyboard (USB Wired Black Keyboard with White Letters - Standard QWERTY Key Layout) - SimplyPlugo by Solidtech (Black Color Keyboard with White Arabic and English Letters) - Algeria, Bahrain, Comoros, Djibouti, Egypt, Iraq,...
Arabic - English USB SimplyPlugo Brand Keyboard Black. New Keyboard. This Keyboard provides superior comfort without forcing you to relearn how to type; it also maintains the key locations in the standard layout so you don't have to relearn how to... more
|go to store
Fosmon® Portable Lightweight Mini Wireless Bluetooth Keyboard Controller (QWERTY keypad) with Built-In Touchpad for Apple iOS / Android / Windows Smartphones, Tablets, PS3 / PS4, Laptop, Notebook and others (Black & Orange)
Connect to all of your favorite devices via Bluetooth with this wireless touch-pad controller from Fosmon. This controller gives you everything you need right in the palm of your hand. Navigate your mouse or cursor easily with your thumb without having... more
|go to store
USB more
|compare prices
Standard Keyboard - 104 Keys more
|compare prices
Kinesis Advantage KB500USBQD Keyboard
Qwerty/Dvorak Switchable more
|compare prices
Cherry Corporation Compact Keyboard
104 Key, Black more
|compare prices
Cherry Corporation G8011900LUMEU0 Keyboard
Advance Performance Line Keyboard more
|compare prices
Cherry Corporation G86-71411 Keyboard
17 in. - USB - 3 Track MSR more
|compare prices
Cherry Corportation G86-61410 Keyboard
14 in Keyboard - USB more
|compare prices
U.S. Robotics USR5500 Bluetooth QWERTY Keyboard w/ iDevice Hotkey Shortcuts, Volume Control, Music Control, Unlock Device Function, 32' Range & Full Size Keys
The USRobotics Wireless Bluetooth Keyboard is the ideal accessory for home and business users with tablets or tricky typing systems. The keyboard supports most tablets including the iPad, Xoom, Galaxy Tab, and Playbook but also works with all major... more
$29.99 $22.59go to store
U.S. Robotics USR5502 Bluetooth QWERTY Mini Keyboard w/ 48 Keys, Rechargable Li-Ion Battery, Multimedia Control Keys, Volume Control & Compact Design
The USRobotics Mini Bluetooth Keyboard is the ideal accessory for home and business users with tablets or tricky typing systems. The keyboard supports most tablets including the iPad, Xoom, Galaxy Tab, and Playbook but also works with all major systems... more
$27.99 $22.39go to store
Siig JK-WR0512-S1 Wireless Slim Mini Keyboard
SIIG�s Wireless Ultra Slim Mini Keyboard is an ultra-thin mini keyboard designed to offer the comfort and convenience of wireless connectivity. This ultra slim, space-saving mini keyboard is only 0.3" (8mm) thick and supports up to 33 ft (10 meters)... more
|compare prices
Standard Keyboard - QWERTY - 89 Keys - Language: English more
|compare prices
Micro Innovations Rapid Access Keyboard
QWERTY - 104 Keys - Language: English more
|compare prices
Language: English more
|compare prices
Micro Innovations 09N5540 Keyboard
Micro Innovations Keyboards are built to last a lifetime - in the office and at home. They offer the reliability you need under all working conditions. The keyboards combine innovative-patented technology with advanced electronic circuitry.Spill resistant more
|compare prices
Standard Keyboard - QWERTY - 104 Keys - Language: English more
|compare prices
Enhanced 104 Key Layout - High Quality Membrane Switch - PS/2 - Beige more
|compare prices
Matias Half-QWERTY 508 Keyboard for One-Handed Typing FK101-508
Touch-type with just one hand on the Half-QWERTY 508 Keyboard from Matias. Designed for one-handed individuals or those suffering from hemiplegia carpal tunnel syndrome or other hand-related injuries the Half-QWERTY is compliant with Section 508 of the... more
|go to store
Siig Inc Wireless Slim Keyboard Mouse
SIIG's Wireless Slim Multimedia Keyboard Mouse offers exceptional performance and reliability with the convenience of wireless connectivity at an affordable price. more
|compare prices
Cherry Corporation G86-61401 Keyboard
USB - 14 in - Black more
|compare prices
4xem Xstreamview Air Mouse With Gyroscope,qwerty Keyboard For Andriod, Ios, Windows - Wireless Connectivity - Compatible With Computer, Smart Tv - Qwerty Keys Layout (xsvc120)
Xstreamview XSVC120 is a remote controller with the multi-function of Air Mouse, keyboard, Multimedia Android Control and Motion Sense Support. It has an Elegant ID design, with an air mouse keyboard on one side, remote-control on the other side. It... more
|go to store
Solidtek KB-700BU POS/Rack Mount Keyboard
SolidTek compact keyboard perfect for rack mounts solution and cash register systemSoft-Touch and silent, tactile feedback more
|compare prices
Ergoguys Goldtouch Ergonomic Adjustable Keyboard Putty Pc Usb By Ergoguys
Key Ovation Goldtouch Ergonomic Adjustable Keyboard USB QWERTY White more
|go to store
Flexible - PS/2 - White more
|compare prices
Adesso ACK-730PB-MRP Rackmount Keyboard with Touchpad - Black
USB - QWERTY - 104 Keys more
|compare prices
Verbatim 96983 Verbatim Wireless Slim Keyboard and Optical Mouse - Black - USB Wireless RF Keyboard - 80 Key - Black - USB Wireless RF Mouse - Scroll Wheel - QWERTY - Black -
Verbatim 96983 Brand New Includes 1 Year Warranty Wireless keyboard and mouse offer 2.4 Ghz wireless communication for no delays in what you type and what you see on-screen and no cord clutter. Ultra-slim keyboard features low-profile keys and a media... more
FREE shippinggo to store
Microsoft Wired Desktop 400 Keyboard and Mouse - USB Wired Keyboard - 104 Key - English (North America) - USB Wired Mouse - Optical - 800 dpi - 3 Button - Scroll Wheel - QWERTY
Combines Sleek Design with Exceptional Value This desktop set combines a spill-resistant keyboard and optical mouse to deliver all the features you need - and more - with Microsoft quality and reliability. Enjoy plug and play setup, Windows 7 features,... more
$23.27 $18.66go to store
Gear Head Wireless Bluetooth Keyboard For Ipad 2
Wireless Bluetooth Tablet Cellular Phone On/Off Switch Hot Key s QWERTY Marketing Information Bluetooth Connectivity Our state of the art design incorporates the latest Bluetooth Technology to easily connect to your iPad 2 iPhone or iPod Touch.... more
|go to store
SIIG's USB Mini Multimedia Keyboard is a space-saving ultra-slim designed mini keyboard. This compact mini keyboard is only 0.875 thick and water-resistant to prevent short circuit due to liquid spills. It also features 86-key QWERTY keyboard layout... more
|go to store
Cherry SPOS Biometric Keyboard , Touchpad
Integrates UPEK TCS2 TouchChip biometric sensor. Save precious space incorporating a biometric reader, touch pad, and MSR into one compact keyboard utilizing one USB connection. Full QWERTY key layout in compact 14" form factor combines maximal space... more
FREE shippinggo to store
Standard Keyboard - QWERTY - 105 Keys more
|compare prices
Solidtek KB-5010BU Mini Keyboard with Track Ball - Black
USB Interface - Compatible with PC - Type A more
|compare prices
Ads related to ibm qwerty keyboards

subset: commoncrawl


text:
V.20 No.2 |
The Daily Word: 1.14.11: It hits the fan in Tunisia
By John Bear [ Fri Jan 14 2011 9:20 AM ]
Tunisia's president dissolves government.
Autopsy reveals police shot man seven times.
Martha Stewart splits lip, gets nine stitches. Not a good thing.
FDA won't ban Vicodin.
More than 500 people die in Brazil floods.
I watched a really depressing nature show about eagles last night. There is no link. I just thought you should know.
Mentally disabled man pardoned for murder (73 years after he was executed).
Young girl killed in Arizona shootings laid to rest.
Happy birthday, LL Cool J.
David Nelson of 'Ozzie and Harriet' dies.
Used needles found all over abandoned apartment complex.
Lawmakers greet calls for gun control with silence.
Today's Events
I Never Sang For My Father at Teatro Paraguas
Dramatic reading of Robert Anderson's classic play, directed by Maura Studi.
Java Bike at Albuquerque Tourism & Sightseeing Factory
Geeks Who Drink • Quiz for a Cause at O'Niell's PubMore Recommended Events ››
Kombat Kitty @ Barley Rm • 7.1.2016
home | feature | news | film | music | art | food | classifieds | personals | staff | lo-fi | search
© 1996-2016 Weekly Alibi email@example.com
View mobile version


text:
Coming up in the next {{countdown}} {{countdownlbl}}
Coming up next:
Skip to this video now
Now Playing:
Play Video
This transcript has been automatically generated and may not be 100% accurate.
When Will Iceland Volcano Stop Spewing Ash?
Iceland's leading volcano scientist says activity will calm in a few days.
Now Playing: When Will Iceland Volcano Stop Spewing Ash?
Now Playing: U.K. Warships Rescue Stranded Travelers
Now Playing: President Obama Defends Policies Against Donald Trump Attacks
Now Playing: New Details in EgyptAir Crash Mystery
Now Playing: Tornadoes Tear Through the Midwest
Now Playing: ISIS Militants Killed in US Airstrikes
Now Playing: Istanbul Bombing: Who Were the Attackers?
Now Playing: Man Calls 911 in Ambien-Induced Hallucination
Now Playing: Pepsi Bringing Back Aspartame in Diet Drink
Now Playing: Stephanie March's Dangerous Breast Implant Surgery
Now Playing: Exclusive: Jason Pierre-Paul in Fireworks Safety PSA
Now Playing: Kelsea Ballerini, Arsenio Hall Talk 'Greatest Hits'
Now Playing: Frank Grillo Talks 'The Purge: Election Year'
Now Playing: St. Lucia Performs 'Dancing On Glass' on 'GMA'
Now Playing: Deals and Steals: Made in America
Now Playing: Donald Trump Attacks Hillary Clinton on ISIS, Benghazi
Now Playing: Maks Chmerkovskiy, Peta Murgatroyd Announce Pregnancy
Now Playing: July 4th Cook-off: Grillmaster Dads Throw Down
Now Playing: Mother Acquitted in Distracted Driving Case that Resulted in Fatal Crash
Now Playing: Academy Announces New Class of Diverse Members
Now Playing: {{itm.title}}


text:
Temporary invincibility for Armored Core 2Home / Playstation 2 /
This page contains Armored Core 2 Codes for Playstation 2 called "Temporary invincibility" and has been posted or updated on Dec 7, 2006 by luthfanfachri.
- Developer: From Software
- Publisher: Agetec Inc.
- Genre: Simulation Sci-Fi
- Release: Oct 24, 2000
- ESRB: Teen
Temporary invincibility
While playing a game, press L2 + R2 + R3. If you entered the code correctly, a "Limiter Released" system error message will appear, and you will have infinite energy during this time. After approximately one minute, the "OB Down" system error will appear. It will last as long as the previous error, but you will not have any energy. After "OB Down" is completed, your AC will recharge and return to normal. Make sure you finish off your enemy before you become vulnerable.
Please Submit a Problem for any incomplete, non-working or fake cheat listed above.
If you know other secrets, hints, glitches or level guides, then please Submit your Cheats and share your insights with other gamers.
Stuck in this game? Set a specific, clearly defined question and let other gamers answer your question or view answers to previously asked questions. If you think you are an expert then please try to help others with their questions.
Toy Story 3 - Gameplay Video
- Apr 16, 2015, Views: 200
Romancing SaGa - Trailer
- Aug 18, 2014, Views: 507
The Shadow Of Zorro - Walkthrough Part 1
- Jun 27, 2014, Views: 295
Shinobido Takumi - Demo 1
- Jun 27, 2014, Views: 338
- The Journey: Bob's Story, (PC)
- Deus Ex: Mankind Divided, (PS4)
- Skylanders Battlecast Cards To Life, (AND)
- Mafia 3, (PS4)
- Forestry 2017 - The Simulation, (XONE)
- Tayutama 2: You're The Only One, (PC)
- Call Of Duty: Infinite Warfare, (PS4)
- Ginger: Beyond The Crystal, (PS4)
- God Eater Resurrection, (PC)
- Hero Siege: Pocket Edition, (iOS)
- Get 'Em, (iOS)
- Quest To Aztlan, (iOS)
- Paranormal Minis, (iOS)
- Station Manager, (iOS)
- Iron Mission - Classic Arcade Shoot'em Up, (iOS)
- Epic Flail (Noxus Ltd), (iOS)
- 2-bit Cowboy Rides Again, (iOS)
- Dungeons Of Chaos Unity Edition, (iOS)
- Rule With An Iron Fish, (iOS)
- Heroes Of Loot 2, (iOS)
- Fi, Chris And The Apocalypse, (iOS)


text:
Strong Volume Gainers (MTX,UNFI,MTOX,FXR,CRED)
What's a Strong Volume Gainer?
A strong volume gainer is when volume is four times greater than the 20-day SMA and is above yesterday's close.
Higher volume many times offers profits from mathematical correlation speculating, arbitraging takeover attempts or mean reversion trading.Looking to trade strong volume gainers? Look no further, the Masters have you covered. Out of a multitude of stocks, here are our top 5 picks.
Minerals Technologies Inc (MTX) is currently trading at $62.4 on volume of 388868. Its 52 week range is between $46.17 and $69.54.
United Natural Foods Inc (UNFI) is currently trading at $51.2 on volume of 1190893. Its 52 week range is between $32.83 and $51.92.
MEDTOX Scientific Inc (MTOX) is currently trading at $26.71 on volume of 800933. Its 52 week range is between $11.64 and $26.88.
First Trust Indust/Producer Dur AlphaDEX (FXR) is currently trading at $17.06.on volume of 550128. Its 52 week range is $13.81 and $19.98.
Credo Petroleum Corp (CRED) is currently trading at $14.38.on volume of 815814. Its 52 week range is between $7.14 and $14.38.
MASTERY Bottom line:
A stock moving up in price on higher than normal volume indicates strong buying conviction that could carry the stock even higher. A stock headed lower on big volume increases could signal strong selling pressure and an emerging downward trend. However, while it is easy to find a system that has worked well in the past, there's no guarantee that it will work in the future..
Best of the Blogs
BlogDroid 600
Scanning and identifying the best blog entries every hour
- ObamaScare Looms - Health Insurers Are Looking For A Taxpayer Bailout | ZeroHedge
- What's Driving This Ramp? The Biggest Short Squeeze In 5 Years | ZeroHedge
- The Real 'Fear' Index Just Went To '11' | ZeroHedge
- The Accusations Begin: David Cameron Blames Brexit On Merkel And EU "Immigration Failure" | ZeroHedge
- Imports Collapse At East Coast Ports | ZeroHedge
- Rent Affordability In Just One Chart | ZeroHedge
- Is This Where All Those Companies "Leaving England" Will Go | ZeroHedge
Latest Headlines
Newsbot 3000
The most relevant financial news and articles from the Internets
- Airbnb looks to keep employees happy by allowing them to sell stock... | Business Insider
- One of the most senior women in the hedge fund industry has made... | Business Insider
- Butter doesn't increase risk of heart disease after all | Business Insider
- The best thing you can do for your productivity over a long... | Business Insider
- Samsung has a wild idea to reinvent notifications on your phone | Business Insider
- Book Review: Thinking, Fast and Slow by Daniel Kahneman | BusinessWeek
- These are all the Fourth of July sales you should know about | Business Insider


text:
Let us know what you think: Email email@example.com.
Safe Kids Midlands
Buckle Buddies provides education and community outreach on Child Passenger Safety. Learn how you can protect your child.
Cassell Brothers Heating and Cooling
For affordable, reliable heating and air service look no further than Cassell Brothers. Click here to learn more about our products and services.
Planet Fitness - Tanning Season is Here
Vote for Us for Best Fitness Club. Come and see why we were voted one of the best gyms in Columbia. Locations on Two Notch, Garner's Ferry and Dutch Square. Click here for locations and more info.
Ole Timey Meats July Special For Two
2 ribeye, 1lb beef stew, 2 salmon fillets and much more! Fresh cut and packaged for the freezer. Only $71.90. Click here!
Get Your Gear On is Keeping the Outdoors Affordable
Great gifts from the great outdoors! Offering a wide variety of products to suite your camping, canoeing, and kayaking needs. Click here!
Welcome to Sandy's Famous Hot Dogs
All our hot dogs are custom made, "our recipe", with Black Angus beef. Click here and print coupons for great food at a great price.
Crescent Construction
We specialize in roofing and can help any homeowner with their home repair needs. Give us a call (803-781-1900) or click here to learn more.
Modern Exterminating Company
We are the longest standing family-owned, local, independent pest control company in Columbia. Give us a call at 803-765-2315 or visit us online.


text:
Declining e-commerce sales hurt Barnes & Noble in fiscal 2016
Last year's website redesign produces mixed results.
Declining e-commerce sales hurt Barnes & Noble in fiscal 2016
Last year's website redesign produces mixed results.
Chinese web retailer JD.com books 100 million orders in 1 day
Foreign brands like Adidas and Puma contributed to the 60% growth compared with last year's June 18 event.
Sign up for IRNewsLink and get daily reports delivery to your inbox. Sign Up Now
Sponsored by 2013 Social Media 300
1 - 5 of 5 Results
Sybase 365, a subsidiary of Sybase, Inc., an SAP company and the global leader in mobile messaging and mobile commerce services today announced thelaunch of its new Sybase Push 365 messaging service, a mobile app-based push messaging service which offers enterprises the opportunity to grow and sustain customer engagement.
Posted 04/25/2012
In Rapidly Evolving mCommerce Space, Platform Provides Rich Services; Ability to Scale to Hundreds of Millions of Customers, Thousands of Transactions Per Second. Enables largest Financial Institutions and Operator Groups to Offer mCommerce Services.
Posted 02/28/2012
If the price is right, consumers are ready to shop via mobile devices.
Posted 11/30/2011Bill SiwickiPost a comment
And many mobile consumers would research products, new survey shows.
Posted 11/11/2011Bill SiwickiPost a comment
The drugstore chain's new program lets customers know when prescriptions are ready, and more.
Posted 09/21/2010Bill SiwickiPost a comment


text:
A good day for unusual lawsuits
News of a wide range of unusual lawsuits — among the topics: schools, religion, post 9/11 security issues and flammable aftershave — showed up in this morning's papers, along with the a sweeping set of plans for the Milwaukee Police Department's future.
This is our daily summary of Wisconsin court-related news in the Journal Sentinel and elsewhere. Check this space each weekday morning for a quick digest of the state's legal happenings, and send your news tips here.
- In a federal lawsuit, Milwaukee Public Schools were found to fail at providing special education services. It's not clear yet what consequences the suit will have for MPS, but the story says there's about $1.8 million in legal fees somebody's going to have to pay.
- It's another fraud lawsuit against the Catholic Archdiocese of Milwaukee over sex-abuse allegations. Track this and see if there's a consolidation of cases at some point.
- Brut used to advertise in Britain under the slogan "splash it all over." A federal lawsuit by a Milwaukee man, however, alleges that you don't want to do that anywhere near a campfire.
- Milwaukee fed court also has a new civil-rights lawsuit by an Iranian man over a 2001 detention.
- These are interesting times to be tracking the Milwaukee Police Department. There's an alderman calling for a halt on all internal promotions, a proposal to shift police-district boundaries (when was the last time this happened?) expanding the area the downtown district covers (at a time downtown's population appears to be growing with new condos and such), and a couple outside consultants being called in to help pick a new chief.
- Vote fraud in Racine County? Four felons still on paper allegedly went to the polls.
- Your daily Zapata trial update from Madison: prosecutors brought out Eugene Zapata's "stalking diary" of his wife's activities before her 1976 disappearance Tuesday and might get done with their side of the homicide case today.
- Finally: we have disorderly conduct charges, of the misdemeanor variety, being filed in Outagamie County against the Packers' Nick Barnett. They haven't hit the court yet and hence aren't on CCAP.
Latest Proof and Hearsay Posts
- Tiny school district feels big financial pain from Woznicki records requests
- Marcia Clark, O.J. Simpson prosecutor and author, coming to Pabst Theater
- Milwaukee Bar Association names new executive director
- A dozen Wisconsin DAs calling it quits this year
- Gov. Walker appoints 2 lawyers with Milwaukee ties to Sheboygan judicial seats
- Milwaukee lawyer explains his night in Scottish jail after soccer championship
- Law grad's first case a winner, before WI Supreme Court
- Ex-lawyer allowed to skip prison to concentrate on restitution still owes big
- Milwaukee man among 58 federal prisoners President Obama orders released early
- $400,000 in lemon law awards over large commercial truck upheld
Supreme Court Tracker


text:
AUBURN, N.Y. - The Auburn Doubledays open the 2013 season at Falcon Park tonight against the Batavia Muckdogs.
This marks the first time since 2010 that the Doubledays open the season at home. Auburn is looking for its fourth straight opening day victory over Batavia. The two teams squared off 12 times last season with the Doubledays getting the upper hand 7-5.
Three familiar faces are back to lead the Doubledays. Gary Cathcart returns for his third season as Auburn's manager. Cathcart has led the Doubledays to two straight division titles. Sam Narron returns for his second season as the pitching coach and Luis Ordaz enters his third season as hitting coach.
The Doubledays are aiming to win the Pinckney Division for the third year in a row. Auburn has won the division eight times since 2002. First pitch is set for 7:05 with fireworks after the game!
For more information, please contact the Auburn Doubledays by email email@example.com or call us at (315) 255-2489.
Today on MiLB.com
Top Stories on MiLB.com
- Rockies' Freeland one step closer to home
- Twins slugger Walker not 'trying to change'
- Roth flirts with first no-hitter in Express history
- Yanks' Higashioka plates seven on two-homer day
- Fulmer finally busts loose in Barons' shutout
- Padres' Hedges goes yard in fifth straight game
- Astros sending Bregman, Hernandez to Grizzlies
- Nationals' Turner tallies another three-hit game


text:
Tix For Ft. Bragg MLB Game Are Nontransferable ESPN Viewership Slightly Lower In Q2 Pistons Flagship Dumps Sports Format ESPN Didn't Have Much Say On CWS Finale Start USOC Revokes Media Credentials For FloSports Braves To Open SunTrust On April 13 NBC Plans Record Amount Of Olympic TV Padres HOF Opens Friday Without Selig Name Spurrier Could Land SEC Net Role Shapiro Addresses Rogers Centre Concerns
Upcoming Conferences and Events
SBD/October 8, 2012/Media
Fox Sports San Diego Inks Deal With AT&T U-Verse; Talks Ongoing With Dish
Published October 8, 2012
TAKERS FOR THE LAKERS? In L.A., Bill Plaschke wrote of TWC SportsNet holding the Lakers' TV rights, "As of now, the majority of the games played this season by the new-look, buzz-soaring, championship-or-bust Lakers will not be seen in the majority of Los Angeles households." TWC has been "unable to convince the area's other giant television providers to run their two channels." Providers such as DirecTV, Charter, Dish, Cox, Verizon and AT&T U-Verse are "holding out for a better deal." Even the Lakers "can't watch the Lakers," as the TV provider "for their El Segundo headquarters building is DirecTV." Lakers Exec VP/Business Operations Jeanie Buss said, "I've been a DirecTV customer for years, so I understand what everyone is going through. The providers have to decide whether they want to take our channel, and it's the customers who have to be vocal in letting their provider know they want it." Plaschke: "I've also been a DirecTV customer for years. It was sold to me as the cornerstone for sports channels. ... For them to waste this much time haggling over the hottest sports property among their 1.7 million Los Angeles households is insulting" (L.A. TIMES, 10/7).


text:
|Horny son fucks his momma�s tasty pussy until she explodes in an orgasm!
Having sex with your own mom is an extremely rewarding experience I should say. If you are a real incest porn buff, you sure will love this scene showing a tender act of love between a mother and a son. Incest is so common among animals and why should we people be deprived of it? Break the rules, watch this young boy fuck his mother�s pussy like there is no tomorrow. She is not young and she knows exactly what her boy wants and is ready to give it to him in exchange for hard pussy pounding by a young, throbbing cock of her son! Son�s love for his mother goes deep, a lot deeper that you�d normally think!
Related random videos. virgana first sexporno porn ks
Language: japanese | spanish | italian | french | german | dutch
Random pages: 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10
Random friendly site pages: 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10
Rape sex porno tube links: Rape video | Sex video rape | Rape videos | Rape sex videos: | Rape sex porn
Rape Portal - the best rape video sex site on the net! Raped teens, daughters embedded on rape videos and photo galleries.�Mega full violence collection of real rapes you can found on this extreme rape video site and it's all for�FREE
Incest Portal - You can see incest sex video here. | Rape porno - You can see rape porno video here. | Raped Moms | BDSM Rape | Rape Anal | Rape Asian | GangBang Rape | Country Rape | Defloration Rape | Femdom Rape | Rape Incest | Perfect Rape | extreme-rape | amazing-rape | crazy-rape | boundrape | facialrape | videofantasyrape | humiliationrape | gapingrape | screamingrape | rough-rape | punishedrape | tiedrape | longislandcity imoc | Friendly Sites |
real homemade xxx hardcore incest videos porn from the 1970 s | rapa sex porn for couples | rough forcedsex incest porn galleries video | teen age girls fuke defloration with big cocke porn film downloads
real incest xxc porn from the 50 s | incest sex brutalsex incest porn games avatar | tamil incest bad sex storys incest porn from bleach big boobs | sexvideo moms boy porn for blackberry
sexy porn japnes incest porn sharing | tamil voilent virgin fuck sex videos porn from 1970 | incestd forced hanging sex video download porn games and hentai | incest sex litel boys fucking teen incest porn for q


text:
|COOKIES: By using this website you agree that we can place Google Analytics Cookies on your device for performance monitoring.
University of Cambridge > Talks.cam > Isaac Newton Institute Seminar Series > When shapes collide: finding order in disorder
When shapes collide: finding order in disorder
Add to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact Mustapha Amrani.
The Mathematics of Liquid Crystals
This talk is part of the Isaac Newton Institute Seminar Series series.
This talk is included in these lists:
Note that ex-directory lists are not shown.
Other listsThinking Society: Is our university a place of free thinking? Computer Laboratory Opera Group Seminars Cambridge International Forum for Development
Other talksAerobic Oxidation Reactions for Organic Chemical Synthesis Metabolomics 2016 Probabilistic anonymisation of microdatasets and models for analysis Nuclear fusion Ignite 2016 - Fast-tracking innovation to commercial reality FORTHCOMING SPEAKERS DATES NOT ARRANGED..


text:
A major horse arena is planned at McDonald, TN., at Exit 20 of I-75 near Cleveland.
Mack Hess, facilities manager of the Tri-State Exhibition Center, said it "is a dream come true for the equestrian people in this area. It will be a premier facility in the Southeast."
Bids are out on the 70,000-square-facility under plans drawn up by Tune Design of Chattanooga.
Mr. Hess said the group was organized in 2000 and held its first horse show in November 2001.
"We doubled the number of events this year that we had last year," he said.
Current facilities include an 80-stall barn, three outdoor arenas and a pavilion 210 x 70 feet.
The new arena will be 320 x 240 feet. It will have a roof, but initially not have sides. Those are to be added later, Mr. Hess said.
He said the 92-acre site is just a quarter mile from the freeway. "It is an absolutely gorgeous setting with pastures and the mountains in the background," he stated.
Going north from Chattanooga, you turn left onto Highway 64.
Mr. Hess said the late Bill Hawk operated a horse arena at Ooltewah, but that has been closed for a number of years.
"After that, the people who show horses had to go out of town," he said.
Mr. Hess said the Tri-State Exhibition Center benefits Hamilton County as well as Bradley County. It is in Bradley, but is only a short distance from the Hamilton line. He said some of the events last more than one day. He said many visitors go into Chattanooga to see the attractions there.
He said the new facility will not just host horse shows, but be big enough for camping and RV shows and other similar events.
Max Everhart is chairman of the board of the Tri-State Exhibition Center.
The Hamilton County Commission looked into building a horse arena, but that project never got off the ground.
Curtis Adams, the current commission chairman, said, "We never could get the support for it. But we missed a golden opportunity, and now Bradley County is going to reap the benefits."
June 26, 2016
June 25, 2016
Here is the latest jail booking report from Hamilton County: AARON, MICHELLE RENEE 1906 APPLING STREET CHATTANOOGA, 37406 Age at Arrest: 47 years old Arresting Agency: Chattanooga ... (click for more)
One person died in a crash on I-75 in Whitfield County on Saturday. The wreck happened near exit 348 in the southbound lane. Traffic was backed up for miles after the accident. (click for more)
Cleveland Police said over $30,000 worth of high-end men's clothing was stolen from Hardwick & Co on Oak Street. The burglary happened sometime Friday night. Items stolen included ... (click for more)
Here is the latest jail booking report from Hamilton County: AARON, MICHELLE RENEE 1906 APPLING STREET CHATTANOOGA, 37406 Age at Arrest: 47 years old Arresting Agency: Chattanooga DOMESTIC ASSAULT --- ADAMS, WILLIAM JACKSON 621 MEMORIAL DR APT 903 CHATTANOOGA, 37415 Age at Arrest: 19 years old Arresting Agency: Chattanooga POSSESSION ... (click for more)
I am writing this letter to bring to your attention to a city traffic issue that needs to be addressed immediately, the sooner the better. I can see no large cost factor. Recently, while as a concerned citizen, removing trash and litter from the entry/exit area of the Wilcox Tunnel on the side that runs into Chamberlain Avenue, I fully realized that this area could ... (click for more)
Coeur d'Alene, Idaho, is a really cool place. I tried to buy a huge mounted buffalo head in an antique store there one time until I found out the shipping charges were four times what the head was worth. But suddenly my rapt attention is riveted on Coeur d'Alene again because a dazzling social experiment is taking place this very moment at a plush resort in north Idaho. Several ... (click for more)
Sunday was a hot, hot day, but that didn't keep nearly a thousand local and regional triathletes from around the Southeast from putting their best foot forward in the annual Waterfront Triathlon in downtown Chattanooga. Chris Douglas and Sara Gibson were the overall winners in the International distance race, which started with a 1.5K (.93 mile) swim, followed by a 42K (26 ... (click for more)
For just the fourth time this season, the Jackson Generals have lost a series with Sunday's 6-2 loss to the Chattanooga Lookouts at AT&T Field in Chattanooga, Tennessee. The Lookouts have won three of the first four in the five-game series in their quest to make it to the Southern League playoffs again. Aaron Slegers started for Chattanooga and picked up the win after eight ... (click for more)


text:
Good News Mountaineer Garage
10 - 19
1 - 2.5 Million
SIC Code:
8999 - Services, Nec
Full company description is available with the free trial.
Additional Info:
The company profile also contains facebook info, phone numbers, linkedin accounts, cfo contacts, and Good News Mountaineer Garage email format addresses with the domain of @goodnewsmountaineergarage.com. Good News Mountaineer Garage, a Non-profit company has its main office in Alum Creek, WV. If you sign up for our free trial you will see our email@example.com addresses.
Company Background:
Full company description is available with the free trial.
Similar Companies:
Appalachian Outreach Inc
Looking for company data regarding Appalachian Outreach Inc's CEO or CFO? Appalachian Outreach Inc is part of the Non-profit field and are located in the area of Moundsville, WV. Some of the helpful data that can be found on their Lead411 profile include Appalachian Outreach Inc email addresses marked by the domain format @appalachianoutreaching.org. Other contact information could contain cfo names, phone numbers, linkedin profiles, corporate contacts, and facebook profiles. If you sign up for our free trial you will see our firstname.lastname@example.com addresses.
Appalachian Trail Conservancy
Appalachian Trail Conservancy is a Harpers Ferry, WV-based company working within the Non-profit industry. You can find Appalachian Trail Conservancy email format addresses here with the domain @appalachiantrail.org. If you sign up for our free trial you will see our firstname.lastname@example.com addresses.
Arthurdale Heritage Inc
Arthurdale Heritage Inc, a company that works within the Non-profit industry. Their profile on Lead411 presents significant contact information such as cfo contacts, phone numbers, linkedin data, and Arthurdale Heritage Inc email addresses with the @arthurdaleheritage.orgdomain format. They have their head office in Arthurdale, WV. If you sign up for our free trial you will see our email@example.com addresses.
Company Directory > Good News Mountaineer Garage


text:
No uploads yetBut you can browse tons of interesting content on our featured content page.
View all Likes
- LiveJournal's Backend: A hist... by vishnu 9 years ago
- Mobile UX Overview by designtaylor 5 years ago
- Android UI Design Patterns & ... by mswolfson 5 years ago
- [Android] Multiple Background... by thelinh299 3 years ago
- Mobile Design. Strategic Solu... by theresaneil 3 years ago
- The Best Android Apps 2012: A... by theresaneil 4 years ago
- Loading
- Follow Following


text:
The trajectory was never known.Still isn't.Somehow the lines crossedand the circles wound tighterand the orbits moved closerand the buzzing overlapsare the sweetest giftsI've ever known.
12.11.12 clt
cynthia lund torroll orbis
Merry Christmas
Why thank you cm ~ and right back at'cha…
I'd kill to be a fly on your cortex ;-P
Steve! You're back! And leaving me with a smile that can only be You induced! x
… wonderful thought Cia…William Tell couldn't do better….:)
Ha ~ love that. Thank you Rich!
oh Damn Girl!!! That is SOO good!!! said one Queeenie Bee to another!! xxx
Ha! buzzzzzzzzzzzz. THANK YOU sweet Yvo! xxx
All right no wrong what's left? Intrigued "-))
Life is like that. xxx
wonderful write
Merci, dear Boo!
Ahhh… "The buzzing overlaps…." How powerfully evocative Cynthia. And how much of life captured in three words.
That's so kind of you Ted. Thank you very much. You've touched me with your visit and wonderful notes.
10% off
for joining the Redbubble mailing list
Receive exclusive deals and awesome artist news and content right to your inbox.
Free for your convenience.


text:
Shorts amateur teensTeen amateurs get sexual experience fucking hard in various positions
Blowjob brunettes coupleBlack dude squeezes black butt of Porshe Carrera and fucks her twat
Bathroom blowjob brunetteShe Teases Him Until He Gives In And Takes A Blowjob
Asian threesome skinnySlammage X two While I'm Grounded
Voyeur sleeping spyingCreeping up on a sleeping camper and wake her up with a nut sack
Amateur black and ebony cuckoldHe Watch His Wife With A Black Bull
Teen pussy youngChubby bbw ex girlfriend sleeping
Japanese lingerie stockingsAsian Girl Fucks Guy In Ass While He Fucks Other Girl
Deepthroat blowjob blondeCan she do finer than her daughter pleasuring her son-in-law?
Drunk swingers fuckDrunk swingers fuck while friend videotapes
Romantic sensual teen (18/19)The most gorgeous pornography movie with anal penetration episodes
Amateur brunette milfI Know What She Did Last Summer
Blonde titty fuck uniformNurse & Doctor Play While Patient's Away
Brunettes high heels glamourShe plays chess with her BF ad then rides him hard
Blonde facial milfShe Maid Me nail Her booty
Kinky babes sleepingSleeping babe fucked
Amateur homemadeShe Sucks Him Until He Simply Needs To Explode On Her Face
Car outdoor publicRedhead in assfuck pick up fuck-fest movie
Ass fucking hotFuck him till he cum, fuck ya
Amateur cuckold interracialShe Fucks While Hubby Films
Close up interracial pantyhoseCouple Let A Black Guy Fuck His Wife While He Films
Blowjob brunette doggystyleShe Never Thought He'd Get The Message And Fuck Her
Twink teen soloJared has some company while he jerks part6
Asian handjob hardcoreWoman Jerks Guy Off From Behind While Hes On His Knees
Small tits lingerieErika cums while watching an online movie
Blonde lingerie milfPilots Wife Fucks While He Is Away And So Does He
High heels brunettes long hairHot porn movie of a crazy brunette cowgirl in a steaming sex action
Anal brunette skinnySuper-fucking-hot dark haired porn movie with wicked culo cramming
Mom mother cougarWhile mom sleeps brat and boyfriend play
Blowjob licking ridingShe Smiles While She Watches Him Stroke His Dick
Blowjob cheating oralWhile he sleeps
Anal double penetration squirtingShe spray on him while he sodomzes her and she takes 2dicks
Fullvideo blowjob oralShe blows him while he rubbs her pussy
Amateur voyeur webcamsNaughty Nerdy Girl wanks to Porn Movie
Blowjobs handjobs pornstarsClassic Porn Movie part two
Hardcore interracial masturbationShe Masturbates While She Waits
Blondes hardcore missionaryShort-haired blonde chick Julia Laube fucked in a porn movie
Car realityAwesome fresh pickup porn movie
Amateur homemade teen (18/19)Uber-sexy naked gf movie
Amateur close-ups maturesShe cums on hes cock then he creampies her hot
Anal milfs pornstarsShe's Baaaack!!!! The Insatiable Debbie Diamond - MILF star She was the craziest, horniest p
Amateur hidden cams homemadeHidden Cam Catches Girlfriend Fucking While Hes Away
Fat mature granny matureFat Granny Sucks His Dick While He Plays With Her Pussy
Big tits blowjob pov (point of view)She Screams As He Enters Her Wet Little Cunt
Blowjob brunette doggystyleShe Sucks And Fucks Him Until He Can't Hold It In
Amateur casting interviewCollege Dropout Auditions For A Porn Movie
Ebony hardcore big titsWhorey dark-hued cop hunts fellow down then porks him till he ends off.
Blowjob long hair pov (point of view)She Moans While She Masturbates Her Hairy British Twat
Pornstar squirting blowjobSee For Riley's gash! She spunks While riding Peter's dude meat!
Bbw big ass blowjobSucking Her Mans Big Cock While He Grabs Her Fat Ass
Amateur homemadeGirl Squats Over A Guy While He Tongues Her Twat
Amateur home stockingsBrunette Amateur Blows Him Until He Explodes
Lesbian lingerie teensWhile He Is Away The Cats Will Play Lesbian Porn
WebcamWebchat With Big Titted Teen Playin With Tits While He Jerks
Anal bbc (big black cock) big titsDirty Minded Housewife Cheats On Husband While He Watches
European amateur homemadeGirlfriend fucked while friend checks porn online
Amateur big tits matureMature Blonde Fucks Him Till He Busts On Her Chest
Hardcore interracial lingerieShe Moans As He Drills Her Harder And Harder
Sclip homemade amateurFunny amateurs filming a real porn movie
Nun retro ridingClassic Porn Movie With Very Hot Scenes
Brunette classic short hairVintage Classsical Porn Movie With Great Sex Scenes
Anal bdsm hardcoreShe loves when he puts objects inside her
Blonde pussy masturbationBig tit blonde rides him till he comes in her face
Big tits blowjob ebonyShe Loves What He Does To Her Tight Black Shaved Pussy
Pussy licking blowjob 69Asa deep-throats Marco's boner while he slurps her saucy raw cunt
Interacial busty bigGorgeous pakistani girl fucked in porn movie
Umemaro 3d hentaiUmemaro 3d- pizza takeout obscenity movie edition subbed
Anal blowjob brunetteAnal foray porno movie with sheer pleasure gel pouring out culo
Teen china girlLaura filipino amateur bar girl makes her first porn movie
Amateur webcamsOlder movies
Masturbation sex toysShe loves her toys
Amateur close-ups hidden camsWhile GF was sleeping
Bathroom blonde lickingShe Sucks Him Off Until He Shoots On Her Peaches


text:
The Derby City Jazz Festival
The Derby City Jazz Festival is coming to Fourth Street Live July 1-2. The festival will focus on the popular smooth jazz genre and will be headlined by Marion Meadows, a Top 10 fixture of the contemporary jazz charts. "We are excited to have the opportunity to host the Derby City Jazz Festival on Fourth Street Live," said Ed Heartless, executive director Fourth Street Live. "We think it will be a tremendous event for the city." In addition to Meadows,veteran jazzers Jeff Lorber and Brian Bromberg will team. Others performing are Althea Rene, Marcus Johnson, Fo Mo Deep, Cindy Bradley, Urban Jazz Coalition, Everett Harpp , Mike Phillips, Cindy Bradley and Chris Standring,


text:
Relevant offers
Samoa have been the big movers on the IRB world rankings as the cutoff point approaches for the Rugby World Cup pool allocation draw.
The high-flying Samoans have surged into eighth spot on the IRB's officials rankings list, meaning they will now be part of the second band (fifth to eighth-ranked sides) when the World Cup pools are drawn on December 3 in London.
And Tonga's fabulous upset of Scotland at the weekend has seen the island side surge past the Scots into 11th on the IRB rankings list. The 10th-placed Italians are now in their sights.
This weekend's final two matches in the north (England v NZ and Wales v Australia) will be the official cutoff point for the World Cup draw bands, though the top four cannot be hauled in regardless of what happens.
That means fourth-ranked France will join southern superpowers New Zealand, South Africa and Australia in the top band, with each to be distributed in separate pools for the RWC.
The next four now includes Samoa, who have surged to eighth on the back of a big win over Canada, an upset against Wales in Cardiff and a resolute 22-14 defeat to France at the weekend.
However seventh-ranked Wales, who are hovering dangerously near the cusp of the top eight, still have plenty to play for as they look to halt a six-test losing skid when they host the Wallabies this weekend.
A seventh straight Welsh defeat would see Warren Gatland's side drop outside the top eight and face landing in a potential group of death for 2015,
If Wales avoid defeat against Australia, they will take one of the other two spots in the second band along with Samoa, with Argentina in the third band.
However, if Australia defeat Wales, then Samoa and Argentina will fill these two spots in the second band, with Wales joining Italy, Tonga and Scotland in the third band of seeds for the pool allocation draw.
England and Ireland are guaranteed to be in the second band of seeds.
Provisional IRB world rankings
1 New Zealand - 92.91
2 South Africa - 86.94
3 Australia - 86.31
4 France - 85.07
5 England - 81.07
6 Ireland - 80.22
7 Wales - 78.95
8 Samoa - 78.71
9 Argentina - 78.71
10 Italy - 76.24
11 Tonga - 76.10
12 Scotland - 75.83
Results from weekend matches for the 12 seeded teams for RWC 2015:
Ireland 46 Argentina 24
England 15 South Africa 16
Italy 19 Australia 22
Scotland 15 Tonga 21
France 22 Samoa 14
Wales 10 New Zealand 33
- Fairfax Media
Sponsored links
All Blacks crush Wales to sweep series with six-try win in Dunedin
All Blacks player ratings: Great night for Barrett, Dagg, Retallick as Welsh swept
England complete 3-0 series sweep of Wallabies in Sydney try-fest
NZ Warriors accuse NRL refs of changing penalty try rules mid-season
All Blacks send Wales packing - now bring on the Aussies in Sydney
Draw v US means no Champions Trophy hockey medals for women's Black Sticks
Springboks hold off Ireland 19-13 in third test to clinch series victory
Euro 2016: Northern Ireland own goal sends Wales into last eight
Georgina Robinson: Wallabies' World Cup hangover continues with series sweep
Euro 2016: Poland advance past Switzerland on penalties to reach quarters
Greig Laidlaw boots Scotland to 21-16 second test win over Japan in Tokyo
Brett Morris stars as Canterbury Bulldogs thrash Brisbane Broncos
New-look Israel Dagg all smiles as All Black comeback gathers pace
Gunmen take guests hostage after car blast at Mogadishu hotel
All Blacks crush Wales to sweep series with six-try win in Dunedin
Two dead, many hurt in US shooting at Texas dance studio
Moko: Hit, kicked, thrown, bitten, stomped and smothered – but prosecutors can't prove couple murdered the boy
Models used in adverts for homeless charity a 'kick in the guts'
Lotto punters strike it lucky - but Powerball still up for grabs
Weird laws still exist in New Zealand - and you could get punished if you break them
Brexit: Newspaper front pages after Britain votes to leave the EU
Fast-moving 'ferocious' California wildfire kills two, destroys homes and vehicles
Two dead, many hurt in US shooting at Texas dance studio
Gunmen take guests hostage after car blast at Mogadishu hotel
Powerful NZ dame: UK ties to become deeper, stronger and more significant
Why corporates are splashing out on lavish reward trips down under
5 things to do if you don't like skiing or snowboarding
All Blacks crush Wales to sweep series with six-try win in Dunedin
Recap: Wallabies v England - third test in Sydney
82-year-old grandmother rejects $27 million offer so she can stay in her home
All Blacks player ratings: Great night for Barrett, Dagg, Retallick as Welsh swept
High-speed crash kills four near Hamilton, witnesses report 'racing' before impact
England complete 3-0 series sweep of Wallabies in Sydney try-fest
Phil Gifford: All Blacks selections pay off for Steve Hansen and co
Julian 'The Bus' Savea struggles to hit top gear against Wales
All Blacks send Wales packing - now bring on the Aussies in Sydney
Protesters take to the streets to show support for Scotland remaining in the EU
Who was the better Springboks lock?


text: + Filter ART Beauty Campaigns Celebrity Commissioned Fashion Men Personal Portrait Production Video CREATION&PRODUCTION Małgorzata Sulima / Twój Styl Mateusz Stankiewicz / Radzimir Dębski, Fashion Magazine Małgorzata Sulima / Shy Albatros Sonia Szóstak / Birdy for Rolling Stone Mateusz Stankiewicz / La Mania AW'16 Małgorzata Sulima / Reni Jusis, K MAG Justyna Dudek / Spring & Paint Load more Stay in touch To receive news updates leave your email address Your address has been successfully signed up. We have send You a confirmation email. Add


text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 4, 2003
|Filing date
|Sep 26, 2001
|Priority date
|Sep 29, 2000
|Fee status
|Publication number
|Partha P. Data Ray, Mikhail I. Grinchuk, Pedja Raspopovic
|Original Assignee
|Lsi Logic Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (4), Non-Patent Citations (1), Referenced by (26), Classifications (5), Legal Events (9)
|External Links: USPTO, USPTO Assignment, Espacenet
This application claims the benefits of U.S. Provisional Application No. 60/236,953, filed Sep. 29, 2000, and entitled "VIRTUAL TREE-BASED NETLIST MODEL AND METHOD OF DELAY ESTIMATION FOR AN INTEGRATED CIRCUIT DESIGN."
Cross-reference is also made to U.S. application Ser. No. 09/964,030, filed on even date herewith, and entitled "METHOD AND APPARATUS FOR ADAPTIVE TIMING OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN."
The present invention relates to the design of semiconductor integrated circuits, and more specifically to an analytical model for estimating delays of logic gates in a netlist before mapping the netlist to any particular technology library and prior to placing and routing the netlist.
Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library.
Each cell corresponds to a logical functions unit, which is implemented by one or more transistors that are optimized for the cell. The logic designer selects the cells according to the number of loads that are attached to the cell, as well as an estimated interconnection required for routing. The cells in the cell library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The cell layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell's transistors and cell routing data. The cell characteristics include a cell propagation delay and a model of the cell's function. The propagation delay is a function of the internal delay and the output loading (or "fan-out") of the cell.
A series of computer-aided design tools generate a netlist from the schematic diagram or HDL specification of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell, the placement of each cell and the routed interconnections.
A timing analysis tool is then used to identify timing violations within the circuit. The time it takes for a signal to travel along a particular path or "net" from one sequential element to another depends on the number of cells in the path, the internal cell delay, the number of loads attached to the cells in the path, the length of the routed interconnections in the path and the drive strengths of the transistors in the path.
A timing violation may be caused by a number of factors. For example, a particular cell may not have a large enough drive strength to drive the number of loads that are attached to that cell. Also, exceptionally long routing paths may cause timing violations. Timing violations are eliminated by making adjustments at each stage in the layout process. For example, an under-driven cell may be fixed by changing the logic diagram to include a cell having a larger drive strength. Alternatively, the logic diagram can be changed to divide the loads between one or more redundant cells or buffer cells. An exceptionally long routing path can be corrected by adjusting the placement of the cells.
Once the timing violations have been corrected, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which can be used to fabricate the integrated circuit.
Few attempts have been made to estimate delay before a netlist has been mapped to a particular technology library and subsequently placed and routed. Unavailability of any wire length information as well as absence of exact load-delay behavior of generic (unmapped) logic elements makes delay estimation an open problem.
All estimations of wire lengths (and hence the wire loads) before placing the cells and routing their interconnections are significantly inaccurate and mislead the design tool using them. Mapping the netlist into specific cells of a particular technology library is therefore done without any delay information or with grossly inaccurate (statistical) delay information. Also, the transformation of large function blocks, such as multiple-input and multiple-output elements, into smaller logical functions or cells is also done with limited delay information. The technology mapping and transformations are subsequently improved upon iteratively with delay information obtained from placement and routing. As a result, the initial placement and routing is not timing driven since little or no timing information is available at this stage in the fabrication process.
In the past, delay models for unmapped netlists rely on an approximate calculation of the number of logic levels in each gate or cell. Thus, the gate delay estimation is based only on the type of gate. Other models have placed a restriction on the fan-out of each gate output to limit error in the gate delay estimation as the load increases. These two models are easy to use, but are not very accurate.
In another model, each gate model is described by estimated capacitances of its inputs, and delay (for a specific output pin of the gate) depends on the type of gate as well as the total capacitance of all input pins of other gates driven by this output pin. This model is quite accurate, but is not local enough. For example, delay along a particular path can depend on the input capacitances of gates that do not belong to the path if an output pin on that path drives input pins of gates that are not on the path.
Improved methods and analytical delay models are desired for estimating delays of cells in a netlist before mapping the netlist to a particular technology library and prior to placing and routing the netlist.
One aspect of the present invention relates to a pre-placement delay model for a logical function block of an integrated circuit design, which includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.
Another aspect of the present invention relates to a method of modeling delay through a logical function block within an integrated circuit design prior to placement and routing. The method includes (a) identifying a fan-in count indicative of a number of inputs to the logical function block; (b) identifying a fan-out count indicative of a number of inputs to other logical function blocks in the integrated circuit design that are driven by an output of the logical function block; and (c) producing a propagation delay estimate for the logical function block as a function of the binary logarithm of the fan-in count and the binary logarithm of the fan-out count.
Yet another aspect of the present invention relates to a semiconductor cell library which, for each cell in the library, includes a functional model and a propagation delay model. The propagation delay model models propagation delay through the cell as a function of only two design variables, a fan-in count variable and a fan-out count variable. The fan-in count variable indicates a number of inputs to the cell, and the fan-out count variable indicates a number of inputs of other cells that are driven by an output of that cell.
FIG. 1 is a flowchart of a layout process in which delay estimation models of the present invention can be used according to one embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a 2-level logic tree that uses basic actual technology gates to implement a Boolean function, F.
FIG. 3 is a graph illustrating the typical behavior of delay(F, load) dependencies for ten different classes of Boolean functions, F.
FIG. 4 is a diagram illustrating an example of an algorithm for calculating an array of delay(F, load) values for each function, F, of each of the classes shown in FIG. 3.
FIG. 1 is a flowchart of a layout process in which delay estimation models can be used according to one embodiment of the present invention. The first step in the layout process is to prepare a schematic diagram or HDL specification in which functional elements are interconnected to perform a particular logical function, at step 100. At step 112, the schematic diagram or HDL specification is synthesized into cells of a cell library. Each cell library has an associated cell definition having physical data and timing characteristics associated with that cell. In one embodiment, the diagram is synthesized into a generic cell library that can be mapped into a specific cell library for a particular manufacturer or technology in subsequent process steps. In another embodiment, the diagram is synthesized directly into a specific cell library.
As described in more detail below, the cell characteristics include a virtual tree-based analytical delay model, which estimates typical cell propagation delays, and a generic model of the cell's function. The cell layout definition includes an estimated layout pattern of the transistors in the cell, estimated geometry data for the cell's transistors and estimated cell routing data.
The virtual tree-based analytical delay model estimates the delay dependence on the number of inputs to the cell (or "fan-in" count) and the load driven by the cell (or "fan-out" count"). The delay model is generalized so that a few general parameters can be used to model the delay behavior of various multi-input and multi-fanout elements in an unmapped netlist. For each basic cell, different technology libraries provide tables of delay as function of output load, as well as tables of input capacitances. This information is used to arrive at values for these generalized parameters so that fairly accurate delay models can be obtained for the unmapped netlist elements. The delay models are fully local. The estimated delay along a particular path depends only on a sum of the gate delay estimates of the gates in that path, not the input capacitances of other gates not in the path. The result is a delay model is easy to calculate given the "fan-in" count and the "fan-out" count and has convenient mathematical properties that can be used by subsequent process steps.
At step 114, the design tools generate a netlist of the selected cells and the interconnections between the cells. In a typical logic diagram or HDL specification, the netlist would include one or more blocks of large, multiple-input or multiple-output logic structures that can be expanded later into tree-like structures of smaller logic functions or cells. Two common variants of these structures include multiple-input logic functions such as large trees of AND, OR, and XOR gates, and any inversions thereof at their inputs or outputs, and large buffer trees, which are often inserted into a netlist to distribute signals from cells having outputs pins with large fanouts (i.e. large output loading). Each of these structures can be implemented with a variety of internal circuit configurations, with each configuration resulting in a potentially different propagation delay from a particular input to a particular output. Therefore, one of these configurations may be more beneficial than another, depending on the arrival times of signals on each pin of the logic block, the required arrival times for each pin and the timing of surrounding circuitry that interfaces with the block.
At step 116, an optimization algorithm optimizes the entire netlist by expanding each of these multiple-input and multiple-output blocks into an optimal one of its respective circuit configurations and providing resulting delay estimates for each structure to subsequent steps in the layout process. This optimization is performed using the virtual tree-based delay models of each cell in the netlist. Since these models provide fairly accurate timing information, the optimization algorithm can optimize gate trees and fan-out buffer trees into circuit configurations that are timing-based. The placement and routing steps 118 and 120 can therefore be timing-driven, resulting in a more effective initial placement and route.
At step 118, the cells in the optimized netlist are placed by arranging the cells in particular locations to form a layout pattern for the integrated circuit. Once the cells have been placed, the interconnections between the cells are routed, at step 120, along predetermined routing layers.
A timing analysis tool is used, at step 122, to generate timing data for the electrical signal paths and to identify any timing violations. The timing analysis tool first determines the output loading of each cell based on the routed interconnections of that cell and the input loading of the driven cells. Based on the output loading of each cell, the timing analysis tool generates timing data and identifies any timing violations. A timing violation occurs when a signal does not reach a particular pin in the netlist at within an appropriate time window. The use of virtual tree-based delay models allows the optimization algorithm performed at step 116 to optimize large, multiple-input and multiple-output blocks to reduce or eliminate timing violations that would otherwise occur after placement and routing in steps 118 and 120. This reduces the number of design iterations required to provide an integrated circuit that has no timing violations. If there are any remaining timing violations, at step 124, the logic designer and/or design tools can return to prior process steps, as indicated by dashed line 123, to correct these timing violations. However, since placement and routing steps were timing-driven, the number of design iterations through these process steps are significantly reduced or eliminated.
Once all of the timing violations have been corrected, an integrated circuit layout definition is prepared, at step 126, which includes a netlist of the selected cells and the interconnections between the cells. The definition further includes placement data for the cells, routing data for the interconnections between the cells and cell layout definitions. The cell layout definitions include layout patterns of the interconnected transistors, local cell routing data and geometry data for the interconnected transistors. The integrated circuit layout definition is then used to fabric the integrated circuit at step 128.
1. Model Description
The virtual-tree-based analytical delay model has two basic constants, Δ1 and Δ2. Constant Δ1 is considered to be the gate delay of binary gates of the simplest form like NAND, NOR, AND and OR for a minimal load (i.e., if these gates have a fan-out count of 1). Constant Δ2 represents delay growth for each additional count of fan-out. The delay, Δ, of a binary gate can thus be estimated as:
This linear dependence of delay on the fan-out count is, however, too pessimistic. It has been found that in almost all circumstances the delay dependence estimation can be improved by using a logarithmic dependence. The delay growth for each additional input or output load is logarithmic for symmetric types of gates.
For example, a gate having an output with a large fan-out can be implemented by a balanced binary tree of buffers. Each binary signal branch (an output pin that is coupled to two input pins) is driven by a buffer. The delay for a fan-out count of 2n is equal to Δ1+nΔ2, where Δ1 is the basic gate delay, Δ2 is the buffer delay, and n=log2(fanoutcount). Making the substitutions into Equation 1, we have,
Equations 1 and 2 are equal for fan-out counts of 1 and 2. But for larger fan-outs, Equation 2 gives less delay. Equation 2 is therefore a generalization of Equation 1 dealing with not only individual gates, but also a combination of gates and buffer trees.
Another generalization is delay estimation for multi-input gates (for associative functions like AND, OR, XOR, and inversions of these functions). Again, these functions can be implemented with balanced binary trees, which leads to the following analytical delay estimation model:
Equation 3 reflects properties of real delay behavior for individual gates. Analysis of actual technology data shows that this equation can be applied to gates having a small fan-in and fan-out, and the same values of Δ1 and Δ2 can be used for different types of gates. The delay information from an entire technology library or set of different technology libraries can be reduced to values of Δ1 (for binary gates having non-linear logical functions such as AND, OR, NAND and NOR), Δ1 (for binary gates having linear logical functions such as XOR and XNOR) and Δ2.
In a particular technology library, there are gates of different functionalities, and even gates with the same functionality, but with different load/delay dependencies. The values for Δ1 and Δ2 can be computed by investigating delay behaviors of different technology library cells and all possible variants of the same cells and by combining these cells in various configurations to achieve a minimum possible delay estimation for a set of Boolean functions. These estimated delay values are then used in a best-fit fashion to extract the values for the constants Δ1 and Δ2 that are used in the delay model shown in Equation 3. Using these values for the coefficients, a reasonably good basis for delay optimization of complex multi-input and large fan-out netlist elements can be obtained before mapping and placement.
Equation 3 gives the delay behavior for virtual models of Boolean functions that can be implemented with the set of gates listed in Table 1.
Number of
Number of
n > 1
Δ2 log2 n
n > 1
Δ1 log2 n
n > 1
Δ1 log2 n
This delay model is more accurate than traditional models (like models based on the number of logic levels in the cell), because it has no "free" fan-ins or fan-outs. Every additional count of fan-in or fan-out has a corresponding delay penalty. The delay along a particular path in a logic design is easy to calculate because the path delay is the sum of the individual gate delays in that path, and all the gate delays depend only on the delay estimate for that gate. In more "technical" delay models, neighboring gates must also be considered in order to calculate the delay of a gate.
2. Analysis of Technology Data
The model can be verified using actual technology gates to implement a variety of different Boolean functions. For this purpose, numerous possible implementations of various Boolean functions are considered, with each implementation using logic trees of actual gates of the technology, such as buffer, NOT, AND, NAND, OR, NOR, XOR and XNOR gates. Also, parallel-connected gates are also used. In these gates, a parallel connection of N copies of the same technology gate is considered to be "more powerful" since it is capable of driving N more loads with the same delay and the same functionality. Each individual gate in the parallel connection drives 1/N times the original load. However, these "parallelized" gates have N times more input capacitance than a single technology gate. For each of the Boolean functions considered above, the minimum possible delay that can be obtained is calculated for different load values.
Table 2 provides a list of sample Boolean functions that can be considered when verifying the delay model.
Functions Implemented
X NAND Y, i.e., NOT (X AND Y)
X NOR Y, i.e., NOT (X OR Y)
In Table 2, functions 1.1 and 1.2 (1.X, where "X" is an integer variable) are considered to have zero levels of binary logic. Functions 2.1 through 2.4 (2.X) have one level of binary logic. Functions 3.1 through 3.8 (3.X) have two levels of binary logic. In one embodiment, delay tables were also formed for 16 additional functions that have three levels of binary logic (4.X), as well as for functions with more complicated structures of one level, where XOR and/or XNOR gates were used in addition to AND and OR gates.
For a given technology library, each of the basic gate elements has a specified input capacitance for each input of the gate and has delays for each output as a function of load. To simplify calculations, an average value can be used for the input capacitance of a cell instead of a separate value for each input of the cell. Also, in one embodiment, a single delay(load) function, which is an average of all delay functions from different inputs, is used. That is, a gate G is considered a black box specified by a logical function parameter (such as buffer NOT, AND, NAND, OR, NOR, XOR and XNOR), an input capacitance parameter "C" and a delay function parameter, delay=f(load).
When adding parallel-connected gates to the list of basic gate elements, "G", that are used to implement the Boolean functions listed above, a new gate object, "NG", can be defined, where "N" is a positive integer representing the number of individual gates that are connected in parallel with one another. The parameters for each gate can then be generalized to:
1) function (NG)=function (G);
2) capacitance (NG)=N capacitance (G); and
3) delay (NG, load)=delay (G, load/N).
When considering numerous possible implementations of each Boolean function listed above, logic trees of the type shown in FIG. 2 are used. FIG. 2 is a diagram illustrating an example of a 2-level logic tree that uses basic actual technology gates to implement one of the Boolean functions listed above. Tree 200 includes inputs 201, output 202 and gates 203-208. Gates 203 are labeled "X" and include gates of a fixed type, such as a basic inverter in the library. To avoid "free" branching of primary inputs 201, all trees are defined such that their primary inputs drive only one unit of "standard load" without extra delay. In this example, the standard load is the input capacitance of one basic inverter.
Gates 204 are labeled "A1" and include any sequence of "parallelized" buffers or inverters. The sequence may be empty so as to include zero buffers or inverters. Gates 206 and 208 are labeled "A2" and A3", respectively, and also include any sequence of "parallelized" buffers or inverters. Gates 205 are labeled "B1" and include any "parallelized" symmetric binary gate. Gate 207 is labeled "B2" and includes another "parallelized" symmetric binary gate.
Then, depending on the actual implementation of gates 204-208, tree 200, represented by the variable "T", has a logical function "f(T)", a standard input capacitance (because of added gates 203) and a delay dependence, "delay(T, load)".
For each logical function F (such that it can be implemented by the trees T) the best possible delay for each load value is calculated according to the relation:
where the minimum is taken for all trees T such that f(T)=F.
Equation 4 gives one delay(F, load) function per Boolean function F, where the delay at each load is the minimum delay for all trees T of function F. The delay(F, load) values are calculated using all possible trees T having 0, 1, 2, . . . , NLMAX levels of binary gates, and for loads equal to 1, 2, . . . , LMAX times the "standard load", where NLMAX is the maximum number of binary logic levels, such as 3, and LMAX is a maximum load, such as 1000.
From the results of Equation 4, several observations can be made. First, functions 1.1 and 1.2 in Table 2 have similar delays, especially for larger load values. Second, all functions 2.1 through 2.4 (i.e., "2.X" where X is an integer variable) have similar delays, especially for larger load. Third, all functions 3.1 through 3.8 (i.e., "3.X") have similar delays, especially for larger load values. Fourth, all 16 functions of "4.X" (with 3 levels of logic) have similar delays, especially for larger load values. Thus, the delay(F, load) function depends largely on the number of logic levels in the function F. The number of logic levels can therefore be used to group the various Boolean functions together.
For small loads, there was a bit more delay than a log-linear dependence of the form
can predict, where C1 and C2 are coefficients corresponding to basic gate delay and fan-out delay, respectively. This mismatch for small loads can be corrected by taking into consideration the effect of internal output capacitance of gates, such that Equation 5 becomes,
where Cp is a parameter modeling the effect of parasitic capacitance.
Each of the delay(F, load) functions can therefore be approximated by a formula of the form:
where the value of Cp can vary between 1 and 10 standard loads, depending on the function F.
Let the parameter "NL(F)" be the number of binary logical levels in tree T, where F is the logical function implemented by tree T. Let "NLL(F)" be the number of binary logical levels that include XOR or XNOR gates in tree T. The values of delta(F, load) will therefore depend mostly on the values NL(F) and NLL(F). Different functions F1, F2 with NL(F1)=NL(F2) and NLL(F1)=NLL(F2) are such that:
Moreover, it was found that coefficients C2 in Equation 7 are approximately equal for all functions F. Coefficients C1 are different from one another for different functions F, but
where C1A, C1B, C1C are constants. The constant C1A has no practical significance since it reflects the input capacitance normalization provided by gates 203 in FIG. 2. However, constants C1B, C1C, C2 can be interpreted meaningfully.
For binary gates having non-linear logical functions (such as AND, NAND, OR and NOR gates),
For binary gates having linear logical functions (such as XOR and XNOR gates),
Finally, C2 can be interpreted as,
Thus, once the values for C1B, C1C and C2 are calculated for a particular technology library, or set of libraries, these values can be used to select parameters Δ1 and Δ2 for tree-like functional blocks that are implemented with actual technology gates. Then, the delay behavior of a tree-like functional block that is unmapped to actual technology gates would be the same if the parameters Δ1 and Δ2 were used to model the delay behavior.
3. Calculating Constants Δ1 and Δ2
The input capacitance and output loading data for basic gates in an actual technology cell library are used to find generic values for Δ1 and Δ2, which can be applied to predict the delay behavior of all multi-input and multi-output functional blocks that can be implemented by these basic gates. When finding the best values for constants Δ1 and Δ2, a variety of different Boolean functions "F" that can be implemented with these basic gates are considered.
A. Distribution of Logical Functions into Different Classes
First, the different logical functions F are distributed into classes, such that all functions in a particular class have the same combination of logic levels NL(F) and NLL(F). In one example, Boolean functions having up to three binary logic levels are divided into ten classes or groups.
FIG. 3 is a graph illustrating the typical behavior of the delay(F, load) dependency for the ten different classes of Boolean functions F. X-axis 300 represents the number of standard loads on a log scale. Y-axis 301 represents delay in nanoseconds (ns). Each curve in FIG. 3 represents the delay(F, load) dependency for a respective one of the classes and is labeled with a unique notation (i,j), where "i" equals the number of binary logic levels in the corresponding class of functions F and "j" equals the number of binary XOR or XNOR levels in the total number of logic levels "i".
The functions in the classes shown in FIG. 3 are divided in the following manner:
1) 1-input functions having 0 levels:
group (0,0) (where i=0 and j=0) includes the functions:
x; and
NOT x
(These two functions are referred to as "elements of the set A").
2) 2-input functions having 1 level:
group (1,0) includes the functions:
x AND y;
x OR y;
NOT(x AND y); and
NOT(x OR y)
(The first two functions in group
(1,0) are referred to as
"elements of the set B").
group (1,1) includes the functions:
x XOR y; and
NOT(x XOR y)
(The first function in group
(1,1) is referred to as the only
element of the set C).
3) 4-input functions having 2 levels (which have the form n(p(q(x1,x2), q(x3,x4))), where n ε A, p and q are members of specific sets of 2-input functions):
group (2,0) has 8 functions:
p, q ε B
group (2,1) has 12 functions:
p ε B, q ε C, or p ε C, q ε B
group (2,2) has 2 functions:
x1 XOR x2 XOR x3 XOR x4; and
NOT(x1 XOR x2 XOR x3 XOR x4)
(or, p, q ε C)
4) 8-input functions having 3 levels (which have form n(p(q(r(x1, x2), r(x3, x4)), q(r(x5, x6), r(x7, x8)))), where n ε A, p, q, r are members of specific sets of 2-input functions):
group (3,0) has 16 functions:
p, q, r ε B
group (3,1) has 24 functions:
one of p, q, r belongs to C; and
remaining two belong to B.
group (3,2) has 12 functions:
one of p, q, r belongs to B; and
remaining two belong to C.
group (3,3) has 2 functions:
x1 XOR . . . XOR x8; and
NOT(x1 XOR . . . XOR x8)
(or, all three p, q, r ε C)
The above-defined groups (as well as their generalization to any number of binary logic levels) have the following properties:
(a) if f is element of group (i,j), then NOT(f) is also element of (i,j);
(b) if f is element of group (i,j), then all four functions of the form:
g(f(x1, . . . ,xN), f(y1, . . . ,yN))
where N equals the fan-in of f (i.e. 2 in the i-th power), g is any of: x AND y, x OR y, NOT(x AND y), NOT(x OR y), belong to group (i+1,j); and
(c) if f is element of group (i,j), then both functions of the form:
where N equals the fan-in of f (i.e. 2 in the i-th power), g is any of: x XOR y, NOT(x XOR y), belong to group (i+1,j+1).
This provides an example of a constructive definition of each group. All that is needed is an "initialization" to define group (0,0).
B. Calculation of Tables of Delay Values, delay(F, load), for Different Boolean Functions F
Tables of the delay values, delay(F, load), are formed for different Boolean functions F. These are calculated using Equation 4 above. For each load value, the corresponding delay values for the various functions F in the class are averaged, for example, to arrive at a common delay(class, load) dependency for all functions F in the class. Each curve in FIG. 3 represents one of these common delay(class, load) dependencies, which reflects the approximation given in Equation 8.
For each group (i,j), where 0≦j≦i≦NLMAX, and for each function F from this group, an array of delay values, delay(F, load), are calculated, where load=0, 1, 2, . . . , LMAX "standard loads".
To do this, delay values for actual technology gates are used. In the analysis, all buffers, inverters, and 2-input gates (AND, NAND, OR, NOR, XOR, XNOR) are considered. Let the name of this set of gates be "S". All delay-related information for each gate G is reduced to:
1) input capacitance (or average of 2 input capacitances for 2-input gates), which are given the notation, "C(G)"; and
2) values of delay (or average of 2 delays for 2-input gates), if load=0,1, . . . ,LMAX standard loads, which are given the notation, "D(G,load)".
FIG. 4 is a diagram illustrating an example of an algorithm 400 for calculating an array of delay(F, load) values for each function F of each group (i,j) using the delay-related information given above, according to one embodiment of the present invention. In algorithm 400, the constant LMAX defines the maximum number of standard loads used in the calculations, such as LMAX=1000, the constant NMAX defines the maximum possible number of gates that can be coupled in parallel to one another for "parallelized" gates (the maximum value of N in "NG" used above), such as NMAX=500, and the constant NLMAX defines the maximum available number of binary logic levels, such as NLMAX=3.
At 401, algorithm 400 begins an initialization routine, "Step 1", which initializes the data arrays, delay(F, load), for each function F. If F is NOT(x), then algorithm 400 lets delay(F, load)=D(G, load), for each load=0,1, . . . ,LMAX, where G is the "most standard" inverter of the given technology library. For all remaining functions F, algorithm 400 lets all values delay(F, load) be +infinity (or some other large number).
At 402, the main loop "Step 2" begins. Step 2 is repeated to find, for each logical function F (such that it can be implemented by the trees T), for each group (i,j), the best possible delay, according to Equation 4 above. The delay(F, load) values are calculated using all possible trees T having 0, 1, 2, . . . , NLMAX levels of binary gates, and for loads equal to 0, 1, 2, . . . , LMAX times the "standard load". Each run of Step 2 tries to add more gates to the trees having the best known delays (in a previous iteration). If the result is faster than the previously best known result for the same function, then the corresponding delay is updated in the respective array. Step 2 is repeated until there are no more updates to the arrays delay(F, load). The result is one array of delay(F, load) values for each function F in each class (i,j).
C. Approximating Each Group (i,j) of functions F by a Formula
Once all of the arrays of delay(F, load) values have been calculated, a common delay(class, load) dependency is approximated for each class by a formula like that given in Equation 7, with respective coefficients C1, C2 and Cp.
1. Calculation of C1, C2 and Cp
Best-fit values for the coefficients C1, C2 and Cp of Equation 7 are calculated for each group (i,j) based on the delay values for loads 1, 2, . . . , LMAX, calculated above. A best-fit is obtained by considering all possible values of Cp with some small step (such as from 0 to 10 with step 0.1). Then, corresponding values of C1=C1(Cp) and C2=C2(Cp) can be found using a standard least-square method for linear approximation. Let the variable err(Cp) be the mean square error of this approximation. Then, a value Cp is chosen so as to minimize err(Cp). Given the value of Cp, the values of C1 and C2 can be calculated from C1=C1(Cp) and C2=C2(Cp). The values for C1, C2 and Cp for all classes are now known. In one example, C2 is calculated to be 0.45 ns.
2. Calculation of C1A, C1B and C1C
Finally, given the coefficients C1, C2 and Cp for each group (i,j), one set of values C1A, C 1B, and C 1C can be calculated for all functions F. The simplest method takes three values of C1: for example, the values of C1 for the classes of Boolean functions having (NL,NLL) equal to (0,0), (1,0), and (1,1). In this case, given Equation 9 and the number of logic levels NL and NLL in each class, the following relationship can be defined:
Solving for C1A, C1B and C1C,
A more accurate approach is to use all available values of C1 from all classes of functions and to compute C1A, C1B and C1C as a solution of the following minimization problem:
Given values C1(i,j) for different i, j (for example, for all i and j, such that 0≦j≦i≦NLMAX), the coefficients C1A, C1B and C1C can be found that minimize the sum,
That is, the C1Xs are parameters of the best linear approximation of a 2-variable function. They can be found using standard methods.
In yet another alternative embodiment, the parameters can be estimated directly from the curves shown in FIG. 3. Looking at FIG. 3, when the load grows, all curves approach parallel straight lines. The slope of these lines gives a value for C1A. To measure the slope, line 303 is drawn "parallel" to the curves, through the origin of FIG. 3, at point (1.0, 0.0). C1A is the second coordinate of point (2.0, C1A) on the same straight line 303. Looking at Y-axis 301, C1A˜0.045 ns.
The value of C1B is the average difference of delays for the same load in each pair of curves in FIG. 3 with parameters (i,j) and (i+1, j) . In other words, C1B is the delay penalty for adding one more logic level to the Boolean function. For larger loads, all six such pairs give more or less equal differences: approximately 0.035 ns.
Similarly, the value of C1C is the average difference of delays for the same load in each pair of curves with parameters (i,j) and (i, j+1). In other words, C1C is the additional delay penalty for a logic level being an XOR or XNOR type. For larger loads, all six such pairs give more or less equal differences: approximately 0.12 ns.
3. Calculating Δ1 and Δ2
Given these values for C1B, C1C and C2 and Equations 10-12,
Δ2 =C 2˜0.045 ns EQ. 22
Thus, by using data for actual technology gates, generic values for Δ1 and Δ2 can be obtained for estimating the delay through multi-input and multi-output blocks with Equation 3 as a function of only the fan-in count and the fan-out count. The particular value used for Δ1 depends on whether the logical function of the block would contain linear binary gates or non-linear binary gates. Therefore, based on the logical function of the block, the delay behavior can be modeled prior to mapping the block into actual technology gates since all gates have approximately the same values of Δ2, all non-linear gates have approximately the same values of Δ1, and all linear gates have approximately the same values of Δ1.
The virtual tree-based delay model given in Equation 3 provides delay predictions for multi-input and multi-output functional blocks in a netlist, which are really different configurations of basic logic functions enumerated in Table 2. Given values of Δ1 and Δ2, Equation 3 is simple and quick to calculate. These predictions have been found to approximate actual delay values reasonably well and also gives important observations of the common delay behavior of different classes of functions, which can be important initial assumptions for delay optimization of netlists.
Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.
|Cited Patent
|Filing date
|Publication date
|Apr 19, 1994
|Feb 27, 1996
|Lsi Logic Corporation
|Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
|Mar 23, 1995
|Mar 19, 1996
|Synopsys, Inc.
|Apparatus and method for estimating time delays using unmapped combinational logic networks
|Nov 20, 1995
|Jun 1, 1999
|Lsi Logic Corporation
|Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles"
|Feb 11, 1998
|Aug 8, 2000
|Monterey Design Systems, Inc.
|Method for providing performance-driven logic optimization in an integrated circuit layout design
|Wu et al., Accurate Speed Improvement Techniques for RC line and tree interconnections in CMOS VLSI, IEEE International Symposium on Circuits and Systems, pp. 1648-1651, May 1990.
|Citing Patent
|Filing date
|Publication date
|Dec 31, 2002
|Apr 26, 2005
|Lsi Logic Corporation
|Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpoints
|Sep 26, 2001
|Mar 28, 2006
|Lsi Logic Corporation
|Method and apparatus for adaptive timing optimization of an integrated circuit design
|Jun 23, 2004
|Jun 19, 2007
|Altera Corporation
|Timing analysis for programmable logic
|Feb 10, 2005
|Nov 27, 2007
|International Business Machines Corporation
|System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
|Feb 23, 2006
|Nov 4, 2008
|International Business Machines Corporation
|Modeling asynchronous behavior from primary inputs and latches
|Jul 17, 2006
|Feb 10, 2009
|International Business Machines Corporation
|Method for driving values to DC adjusted/untimed nets to identify timing problems
|Mar 9, 2010
|International Business Machines Corporation
|Logic block timing estimation using conesize
|Mar 7, 2005
|Jun 15, 2010
|Fujitsu Limited
|Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence
|Feb 1, 2011
|International Business Machines Corporation
|Sequential equivalence checking for asynchronous verification
|Jul 7, 2008
|Feb 8, 2011
|International Business Machines Corporation
|Modeling asynchronous behavior from primary inputs and latches
|Nov 14, 2008
|Feb 8, 2011
|International Business Machines Corporation
|Driving values to DC adjusted/untimed nets to identify timing problems
|Nov 5, 2008
|Feb 21, 2012
|International Business Machines Corporation
|Specifying and validating untimed nets
|Aug 27, 2008
|Jun 17, 2014
|Altera Corporation
|Method and apparatus for extracted synthesis gate characteristics model
|Mar 28, 2012
|Jun 24, 2014
|Synopsys, Inc.
|Optimizing logic synthesis for environmental insensitivity
|Oct 15, 2012
|Oct 7, 2014
|Albeado Inc.
|Pervasive, domain and situational-aware, adaptive, automated, and coordinated analysis and control of enterprise-wide computers, networks, and applications for mitigation of business and operational risks and enhancement of cyber security
|Dec 31, 2002
|Jul 1, 2004
|Johnson Gregory A.
|Method, system, and product for achieving optimal timing in a data path that includes variable delay lines and coupled endpoints
|Mar 7, 2005
|Jul 14, 2005
|Fujitsu Limited
|Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium
|Apr 9, 2004
|Oct 13, 2005
|Zenasis Technologies, Inc.
|System and method for automated accurate pre-layout estimation of standard cell characteristics
|Feb 10, 2005
|Aug 24, 2006
|Yee Ja
|System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
|Jul 17, 2006
|Jan 17, 2008
|Gass Robert B
|System and Method for Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems
|Jul 7, 2008
|Nov 27, 2008
|Hidvegi Zoltan T
|Modeling asynchronous behavior from primary inputs and latches
|Sep 11, 2007
|Mar 12, 2009
|International Business Machines Corporation
|System to Identify Timing Differences from Logic Block Changes and Associated Methods
|Nov 14, 2008
|May 21, 2009
|International Business Machines Corporation
|Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems
|Nov 27, 2007
|May 28, 2009
|Baumgartner Jason R
|System and Method for Sequential Equivalence Checking for Asynchronous Verification
|Nov 5, 2008
|May 6, 2010
|Dilullo Jack
|Method for Specifying and Validating Untimed Nets
|Oct 28, 2010
|Du Nguyen
|Clock Approximation for Hardware Simulation
|U.S. Classification
|716/108, 703/15
|International Classification
|Cooperative Classification
|European Classification
|Sep 26, 2001
Owner name: LSI LOGIC CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAY, PARTHA P. DATTA;GRINCHUK, MIKHAIL I.;RASPOPOVIC, PEDJA;REEL/FRAME:012212/0892;SIGNING DATES FROM 20010922 TO 20010924
|Apr 19, 2007
|Fee payment
Year of fee payment: 4
|May 3, 2011
|Fee payment
Year of fee payment: 8
|May 8, 2014
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG
Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031
Effective date: 20140506
|Jun 6, 2014
Owner name: LSI CORPORATION, CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270
Effective date: 20070406
|Apr 3, 2015
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388
Effective date: 20140814
|Apr 28, 2015
|Fee payment
Year of fee payment: 12
|Feb 2, 2016
Owner name: LSI CORPORATION, CALIFORNIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039
Effective date: 20160201
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039
Effective date: 20160201
|Feb 11, 2016
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001
Effective date: 20160201


text:
Hearing aids in 45373, Troy, OH
We found 10 hearing clinics with 81 reviews within 75.2 miles of 45373, Troy, OH.
Featured hearing professionals near you
Jolene Fogt, BC-HIS
Hearing Instrument Specialist Jolene Fogt has two children who are hearing impaired and both began (read more)
Peg Meiring, Au.D., FAAA
Dr. Peg Meiring and Dr. Ellen Hunter are the founders of Family Audiology Associates, Inc. Dr (read more)
Terri Shive, AuD
Dr. Terri Shive holds a Master of Arts in Audiology from the Univeristy of Akron and a Doctorate in (read more)
Cindy Whitehurst, Au.D., FAAA
Dr. Whitehurst has been working in the field for 25 years. Her experience includes hospitals, (read more)
Tim Cross, BC-HIS
Timothy A Cross has been board certified in Hearing Instrument Sciences since 1992 and received his (read more)
Patricia Lambert, M.A., FAAA
Patricia Lambert has been a dispensing audiologist in the greater Cincinnati area since 1982. She (read more)
Additional professionals near you
Upper Valley Hearing and Balance Inc.
View Clinic Details
Earzlink Hearing Care - Tipp City
View Clinic Details
Hearing Professionals - Sidney
View Clinic Details
Earzlink Hearing Care - Washington C…
View Clinic Details


text:
Terry discusses work with families at summit
At her keynote address at the Community Summit on Children, Professor Nicole Terry discusses how communities can ensure "all children enter school ready to learn and ready to succeed."
At her keynote address at the Community Summit on Children, Professor Nicole Terry discusses how communities can ensure "all children enter school ready to learn and ready to succeed."
After-School All-Stars Atlanta has received an Atlanta Falcons Youth Foundation grant to support after-school and summer programs aimed at increasing young girls' aerobic fitness levels.
The National Academy of Education selected College of Education & Human Development Assistant Professor Chenyi Zhang as a 2016 Spencer Postdoctoral Fellow.
At a State Capitol announcement on June 1, Georgia Gov. Nathan Deal and Arthur Levine celebrated the state of Georgia's class of Woodrow Wilson Georgia Teaching Fellows.
First-year principals from across Georgia had the opportunity to network and celebrate their achievements at the Principals Center's annual New Principals Celebration.
The College of Education & Human Development's Collaboration and Resources for Encouraging and Supporting Transformations in Education (CREST-Ed) program will host its Summer Institute on July 14.
Four doctoral students have been selected to receive College of Education & Human Development Doctoral Dissertation Awards.
African-American girls in low-income, high-risk neighborhoods report encounters with aggression and sexual objectification, according to Georgia State University researchers.
The program committee for the 11th Annual Sources of Urban Educational Excellence Conference is accepting proposals for conference sessions through June 3, 2016.
The city of Atlanta was ranked the 14th healthiest metropolitan area in the U.S. for the second year in a row, according to the American College of Sports Medicine's 2016 American Fitness Index.


text:
Jun 21, 2016
WASHINGTON [MENL] -- An Israeli defense subsidiary has won a contract tosupply the U.S. Navy.
TEL AVIV [MENL] -- Israel has sought to deter Hamas from sparking anotherwar from the Gaza Strip.
Jun 17, 2016
WASHINGTON [MENL] -- A U.S. contractor has provided details of an aircraftproject for the Royal Saudi Naval Forces.
Jun 09, 2016
TEL AVIV [MENL] -- Israel's business capital has been struck by a majorPalestinian attack.