text:
|By Greg Schulz
Article Rating:
|November 27, 2012 08:00 AM EST
Do you know the computer technology saying, garbage data in results in garbage information out?
In other words even with the best algorithms and hardware, bad, junk or garbage data put in results in garbage information delivered. Of course, you might have data analysis and cleaning software to look for, find and remove bad or garbage data, however that's for a different post on another day.
If garbage data in results in garbage information out, does garbage big data in result in big garbage out?
I'm sure my sales and marketing friends or their surrogates will jump at the opportunity to tell me why and how big data is the solution to the decades old garbage data in problem.
Likewise they will probably tell me big data is the solution to problems that have not even occurred or been discovered yet, yeah right.
However garbage data does not discriminate or show preference towards big data or little data, in fact it can infiltrate all types of data and systems.
Let's shift gears from big and little data to how all of that information is protected, backed up, replicated, copied for HA, BC, DR, compliance, regulatory or other reasons. I wonder how much garbage data is really out there and many garbage backups, snapshots, replication or other copies of data exist? Sounds like a good reason to modernize data protection.
If we don't know where the garbage data is, how can we know if there is a garbage copy of the data for protection on some other tape, disk or cloud. That also means plenty of garbage data to compact (e.g., compress and dedupe) to cut its data footprint impact particular with tough economic times.
Does this mean then that the cloud is the new destination for garbage data in different shapes or forms, from online primary to back up and archive?
Does that then make the cloud the new virtual garbage dump for big and little data?
Hmm, I think I need to empty my desktop trash bin and email deleted items among other digital house keeping chores now.
On the other hand, just had a thought about orphaned data and orphaned storage, however lets leave those sleeping dogs lay where they rest for now.
Ok, nuff said (for now).
Cheers Gs
Greg Schulz - Author Cloud and Virtual Data Storage Networking (CRC Press, 2011), The Green and Virtual Data Center (CRC Press, 2009), and Resilient Storage Networks (Elsevier, 2004)
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text:
|Publication number
|Publication type
|Application number
|Publication date
|Jul 10, 2007
|Filing date
|Dec 1, 2004
|Priority date
|Dec 1, 2004
|Fee status
|Also published as
|Publication number
|Darren van Wageningen, Curt Wortman
|Original Assignee
|Altera Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (18), Non-Patent Citations (4), Referenced by (16), Classifications (19), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention relates to techniques for reporting output signals from a hard intellectual property block, and more particularly, to techniques for reporting output signals from a hard intellectual property block at a lower frequency.
Programmable logic devices (PLDs) are a type of programmable logic integrated circuit. Programmable logic devices can be configured to perform a variety of logical user functions. Programmable logic integrated circuits also include field programmable gate arrays (FPGAs), programmable logic arrays, configurable logic arrays, etc.
PLDs typically have numerous logic blocks that can be configured to implement various combinatorial and sequential functions. The logic blocks have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic blocks in almost any desired configuration.
Many of today's PLDs have on-chip non-programmable application specific integrated circuit (ASIC) blocks. The ASIC blocks are also referred to as hard intellectual property (HIP) blocks. A HIP block typically operates at a higher clock frequency than the programmable logic in a PLD, because the interconnect wires between programmable logic blocks usually have longer routing delays than interconnect wires in an HIP block.
Many types of HIP blocks that are used in PLDs generate error signals that indicate whether erroneous values are being generated within the HIP block. Many types of HIP blocks also generate status signals that indicate operational states of circuits in the HIP block. A HIP block typically generates the status and error signals at the same frequency as the clock signal used in the HIP block.
For a particular embodiment, the internal clock frequency inside a HIP block configured as a System Packet Interface Level 4 Phase 2 (SPI4.2) processor running at Gbps is 500 MHz. Conversely, programmable logic within a PLD or FPGA typically has to operate at a lower clock frequency (e.g., 250 MHz), a timing requirement that is a side effect of the additional delays encountered with the interconnect wires and programmable Logic Elements (LE). As a result, it is not possible for the programmable logic to capture higher frequency (500 MHz) HIP block output signals that are transmitted in a single bit stream.
One option is to lower the frequency of the HIP block's clock signal. Reducing the frequency of the HIP block's clock signal affects the operation of logic circuitry in the HIP block and can mask timing violation bugs inside the HIP block. Therefore, this option by itself is not desirable.
Therefore, it would be desirable to provide techniques for capturing output signals from a hard intellectual property (HIP) block that operates at a higher clock frequency than programmable logic on the same integrated circuit.
Hardware debugging of an HIP block is difficult because the HIP block internal clock rate is higher than the programmable logic clock rate, as described above. It is desirable for a hardware engineer to check some or all of the HIP block input clock and reset signals. However, the standard methods of signal probing are difficult in the HIP block because of the speed limitations of the FPGA standard logic elements. Therefore, it would be desirable to provide a signal from the HIP block at a lower clock frequency that indicates whether various clock and reset signals are operating properly.
The present invention provides techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block to be captured by standard logic in a programmable logic device. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP clock signal are able to capture the output signal. The HIP output signals can be, for example, a status signal, error signal, or data signal.
The present invention also provides techniques to determine Hard Intellectual Property (HIP) clock and reset activity for both initial debug confidence and runtime operation.
According to one embodiment of the present invention, a plurality of serially coupled flip-flops store values from consecutive periods of a HIP block output signal. Logic circuitry generates a reduced frequency HIP output signal in response to the values stored in the flip-flops.
According to another embodiment of the present invention, a flip-flop generates a heartbeat signal that is used to determine whether clock and reset signals within a HIP block are operating properly.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
FPGA 100 includes input/output (I/O) block 101, FPGA/HIP interface block 102, and HIP core 103. I/O block 101 receives N bits of parallel input data DATA[N:0] through a input terminals (pins) of the integrated circuit. SERDES 104 de-serializes the data and outputs the de-serialized data to processing logic within HIP block 103 along a data path. In an alternative embodiment (not shown), the data flow has SERDES 104 serializing the data from the processing, and transmitting the serialized data from FPGA 100.
FPGA 100 also receives an external clock signal DCLK at an input pin as shown in
The HIP clock signal is the clock signal that is used to drive digital circuitry within HIP block 103. The HIP clock signal clocks logic circuitry within HIP processing logic 110 such as error/status flip-flop 115. Typically, the HIP clock signal has a higher frequency than the xclk clock signal and other clock signals that clock logic circuitry within FPGA 100. For example, the HIP clock signal may have a frequency of 500 MHz, and the xclk signal may have a frequency of 250 or 125 MHz (depending on the deserialization factor of x4 or x8 respectively).
HIP block 103 is an ASIC block within FPGA 100. HIP block 103 can be designed to perform any desirable functions. HIP block 103 generates various output signals, for example, error signals, status signals, and data output signals. These output signals (such as flip-flop 115) are transmitted to programmable logic circuitry within the FPGA such as flip-flop 116 for analysis. These output signals are generated at the frequency of the HIP clock signal, which is usually higher than the clock frequency of the FPGA's programmable logic circuits. The present invention provides techniques for reducing the frequency of output signals generated by HIP block 103 so that the output signals can be captured by programmable logic element 116 in FPGA 100.
Block 200 can include any number of flip-flops such as flip-flops 211-213 that are serially coupled together to reduce the frequency of an HIP block output signal by a corresponding fractional amount. For example, 4 flip-flops (including flip-flops 211-213 and one additional flip-flop coupled to the output of flip-flop 213) can be serially coupled to reduce the frequency of a HIP block output signal by �.
As another example, block 200 can have only two flip-flops 211-212 (flip-flop 213 being eliminated) to reduce the output signal by �. As another example, eight flip-flops can be serially coupled together to reduce the frequency of a HIP block output signal by ⅛. The output voltages of each of the serially coupled flip-flops are combined using a logic gate such as OR gate 215.
Block 200 can also include an inverter 221 to make flop 217 negative edge clocked, but this is not a requirement. All flip-flops in block 200 are clocked on the HIP clock, which is typically faster than the xclk. For active low output signals, OR gate 215 is turned into an AND gate, otherwise the input to flop 211 will have to be inverted.
Flip-flop 211 receives an output signal of the HIP block at its D input terminal. The HIP output signal can be, for example, an error output signal, a status output signal, or a data output signal.
Flip-flops 211-213 receive the HIP clock signal at their clock input terminals. The voltage at the Q output terminal of flip-flop 211 is applied to the D input terminal of flip-flop 212. The voltage at the Q output terminal of flip-flop 212 is applied to the D input terminal of flip-flop 213. The voltage at the Q output terminal of flip-flop 213 is applied to the D input terminal of the next flip-flop or directly to an input of OR gate 215. The serially coupled flip-flops are clocked by the HIP clock signal.
The voltages at the Q output terminals of flip-flops 211-213 and any other flip-flops are applied to the inputs of OR gate 215. If any of the voltages at the Q outputs of these flip-flops are a logic high, the voltage at the output of OR gate 215 is a logic high. Thus, OR gate 215 combines data from X consecutive periods of the HIP output signal into one period (where X equals the number of serially coupled flip-flops). As a result, the period of the output signal of OR gate 215 is X times as long as the period of the HIP output signal and the period of the HIP clock signal. This implies a signal toggle frequency of the output signal of OR gate 215 is 1/X of the frequency of the HIP output signal and the HIP clock signal.
Multiplexer 216 receives the output signal of OR gate 215 at one of the multiplexer input terminals. Multiplexer 216 also receives the voltage at the Q output of flip-flop 211 at another one of the multiplexer input terminals. The state of the Toggle No-Delay signal determines which input signal multiplexer 216 passes to its output. This allows for selection of the cascaded signal output from flip-flops 211-213 or for the output from flip-flip 211 only (no-delay mode), providing the output signal at the HIP clock toggle frequency. The no-delay mode may be useful for obtaining the true values of the internal signals, while running the HIP at a slower rate so that there are no timing violations to flip-flop 116 clocked on the xclk domain. The no-delay mode may also be useful for multicycle signals that do not toggle every HIP clock cycle.
The output of multiplexer 216 is coupled to the D input of flip-flop 217. Flip-flop 217 registers the output signal of block 200 and generates registered output signal VOUT. Flip-flop 217 is clocked by the inversion of the HIP clock signal, so that it operates out of phase with flip-flops 211-213. Inverter 221 implies that flip-flop 217 operates on the inverted clock edge that flops 211-213 operate on, providing an improved timing margin for the output signal VOUT. Alternatively, inverter 221 can be eliminated, and flip-flop 217 can be clocked by a non-inverted HIP clock signal.
The voltage VOUT at the Q output of flip-flop 217 is transmitted to circuitry in FPGA fabric 201 such as flip-flop 116. Flip-flop 116 is clocked by FPGA clock signal xclk, which typically has a lower frequency than the HIP clock signal.
HIP reporting block 200 can be operated in one of two modes of operation by selecting the logic state of the Toggle No-Delay signal. When a user wants to capture the HIP output signal in circuitry residing in the FPGA fabric 201, the Toggle No-Delay signal is set to a first state. When the Toggle No-Delay signal is set to a first state, multiplexer 216 passes the output signal of OR gate 215 to the D input of flip-flop 217.
A disadvantage of operating block 200 in the first mode of operation is that OR gate 216 merges four values within every four periods of the HIP output signal into one value. This technique increases the chance that information could be lost. For example, the HIP output signal can be an error signal. If two errors occur in a row, the error signal will contain high values in two consecutive periods. Block 200 may merge two consecutive high values into one high value at the output of OR gate 216. As a result, two error values may be erroneously interpreted as one error value. As another example, four error values in a row may be merged into one single error pulse in VOUT if the deserialization factor is 4. In this example, the single error pulse in VOUT by itself cannot be distinguished from one, two, three or four separate error pulses in the HIP error output signal.
However, the techniques of the present invention are superior to prior art techniques. Prior art techniques failed to capture any values of an HIP block output error signal, because the frequency of the error signal was too fast for any of its values to be captured by the FPGA programmable logic, which was clocked at a lower frequency, when only 1 HIP I/O signal is available per status or error output. The techniques of the present invention allow programmable logic blocks in an FPGA to capture and analyze HIP output signals at a reduced frequency without having to reduce the frequency of the overall HIP clock signal, while keeping the HIP I/O pin count to a minimum.
Although some information in the HIP output signals may be lost in the frequency reduction process, the reduced toggle frequency VOUT signal contains a substantial amount of useful information. For example, if the HIP output signal is an error signal, VOUT being high in one period indicates that at least one error signal is occurring within X periods of the HIP error output signal (where X is determined by the deserialization factor of SERDES 104). Further analysis can then be performed to identify the cause of the error.
In the second mode of operation, the Toggle No-Delay signal is set to a second logic state when the user does not want to reduce the frequency of the HIP output signal. When the Toggle No-Delay signal is set to the second state, multiplexer 216 passes the Q output signal of flip-flop 211 to the D input of flip-flop 217. In this second mode of operation, the frequency of the VOUT signal is the same as the frequency of the HIP clock signal. The frequency of VOUT may be too high for flip-flop 116 to capture its values.
However, the second mode of operation can be used for other purposes. For example, the HIP output signal can be an error signal. In the first mode of operation, the VOUT signal may contain high pulses that indicate errors are occurring in the HIP block. If VOUT indicates errors are occurring, the frequency of the HIP clock signal can be reduced below its standard frequency to operate at a lower frequency (e.g., 125 MHz). Block 200 is then placed in the second mode of operation so that multiplexer 216 passes the error output signal from flip-flop 211 directly to flip-flop 217 at the same frequency as the HIP clock signal.
In the second mode of operation, error signals can be independently identified in each period of the error output signal. Operation in the second mode can hide timing violation bugs as mentioned above. However, by initially operating in the first mode, the timing violation bugs can be identified. By operating logic circuitry in the HIP block at a reduced clock signal frequency (e.g., 125 MHz) in the second mode of operation, programmable logic circuits in the FPGA fabric can capture output signals of flip-flop 217 at the nominal clock frequency of the programmable logic core.
According to a further embodiment of the present invention, OR gate 215 is replaced with another type of logic gate. As another example, OR gate 215 can be replaced with an OR-gate/multiplexer combination that selectively passes the Q output signals of the serially coupled flip-flops determined by the deserialization factor of SERDES 104. For example, a typical embodiment will contain 4 flip-flops in serial to support a deserialization factor of 8. However, if the deserialization factor is reduced to 4, then the multiplexer can select two of the flip-flops to be used for the inputs to the OR gate.
Another option is to transmit each of the output signals of the serially coupled flip-flops 211-213 separately (in parallel) to programmable logic in the FPGA fabric; this parallel output bus has a lower frequency than the HIP block output signal. The serially coupled flip-flops can divide an HIP block output signal into X parallel output data streams. Each parallel data stream contains data from one of every X periods of the HIP block output signal. The frequency of each parallel data output stream is 1/X the frequency of the HIP block output signal.
However, in the parallel output embodiment, the HIP block has to have X different output terminals per output signal, one for each of the parallel output signals. HIP blocks typically have a limited number of output terminals, and therefore, a solution that requires numerous output terminals is not desirable. As a specific example, a HIP block that generates ten separate error signals at the HIP clock frequency needs X times 10 output terminals to transmit 10X parallel error output signals that each have a frequency reduced by 1/X with respect to the HIP clock. p Also, the parallel output embodiment places a larger demand on the programmable routing resources in the FPGA. More routing resources are needed to transmit the X parallel output signals from the HIP block to the programmable logic blocks. Therefore, the embodiment of
Flip-flop 401 is clocked by an HIP clock signal CLK. A Reset signal controls the clear input of flip-flop 401. The Qbar output terminal is coupled to the D input terminal. A heartbeat signal VHB is generated at the Q output terminal.
The heartbeat signal VHB provides an easy way for a hardware design engineer to ensure that the HIP block clock and reset signals are properly configured in the HIP block. The heartbeat signal VHB also allows an engineer to verify that the clock and reset trees have been properly routed inside the HIP block.
In the example shown in
The counter or divider circuit can be controlled by the reset signal. The divided VHB signal is then sent to LE fabric (e.g., programmable logic blocks). A user can implement detection logic to report and handle system failures. A benefit of the
Thus, flip-flop 401 oscillates in a desired clock domain. Flip-flop 401 is optionally reset based on a desired reset signal. There can be a flip-flop that generates a heartbeat signal for every clock domain in an HIP block on an FPGA. If flip-flops in a clock domain have different reset signals, a unique heartbeat signal can be generated for each of these conditions using a separate flip-flop such as flip-flop 401.
A hardware debug engineer can capture the heartbeat signal VHB after reset to ensure that the HIP block is operating, and that the clock and reset signals are properly driven. Another advantage of the
An LE is a programmable logic block that provides for efficient implementation of user defined logic functions. PLD has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration.
PLD 600 also includes a distributed memory structure including RAM blocks of varying sizes provided throughout the array. The RAM blocks include, for example, 512 bit blocks 604, 4K blocks 606 and a block 608 providing 512K bits of RAM. These memory blocks can also include shift registers and FIFO buffers.
PLD 600 further includes digital signal processing (DSP) blocks 610 that can implement, for example, multipliers with add or subtract features. I/O elements (IOEs) 612 located, in this example, around the periphery of the device support numerous single-ended and differential I/O standards. It is to be understood that PLD 600 is described herein for illustrative purposes only and that the present invention can be implemented in many different types of PLDs, FPGAs, and the like.
While PLDs of the type shown in
System 700 includes a processing unit 702, a memory unit 704 and an I/O unit 706 interconnected together by one or more buses. According to this exemplary embodiment, a programmable logic device (PLD) 708 is embedded in processing unit 702. PLD 708 can serve many different purposes within the system in
Processing unit 702 can direct data to an appropriate system component for processing or storage, execute a program stored in memory 704 or receive and transmit data via I/O unit 706, or other similar function. Processing unit 702 can be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, programmable logic device programmed for use as a controller, network controller, and the like. Furthermore, in many embodiments, there is often no need for a CPU.
For example, instead of a CPU, one or more PLDs 708 can control the logical operations of the system. In an embodiment, PLD 708 acts as a reconfigurable processor, which can be reprogrammed as needed to handle a particular computing task. Alternately, programmable logic device 708 can itself include an embedded microprocessor. Memory unit 704 can be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, PC Card flash disk memory, tape, or any other storage means, or any combination of these storage means.
While the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes, and substitutions are intended in the present invention. In some instances, features of the invention can be employed without a corresponding use of other features, without departing from the scope of the invention as set forth. Therefore, many modifications may be made to adapt a particular configuration or method disclosed, without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments and equivalents falling within the scope of the claims.
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|Jun 8, 2004
|Cypress Semiconductor Corp.
|Interface scheme for connecting a fixed circuitry block to a programmable logic core
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|Aug 12, 2005
|Feb 16, 2006
|Altera Corporation, A Corporation Of Delaware
|PLD architecture for flexible placement of IP functions blocks
|Dec 7, 2004
|Jun 8, 2006
|Altera Corporation
|Techniques for implementing hardwired decoders in differential input circuits
|"Atlantic Interface," Altera Functional Specification 13, version 3.0, Altera Corporation San Jose, CA (Jun. 2002).
|"FPGAs & FPSCs from Lattice: ORSPI4," product information from http://www.latticesemi.com, Lattice Semiconductor Corporation Hillsboro, OR (2003), no month.
|"ORCA(R) ORSPI4 Dual SP14 Interface and High Speed Serdes FPSC," product information Lattice Semiconductor Corporation Hillsboro, OR (2004), no month.
|System Packet Interface Level 4 (SPI-4) Phase 2; OC-192 System Interface for Physical and Link Layer Devices, Optical Internetworking Forum Implementation Agreement : OIF-SPI4-02.0 (Jan. 2001).
|Citing Patent
|Filing date
|Publication date
|Feb 10, 2006
|Nov 18, 2008
|Xilinx, Inc.
|In-system signal analysis using a programmable logic device
|Feb 10, 2006
|Jan 19, 2010
|Xilinx, Inc.
|Integrated circuit for in-system signal monitoring
|Apr 11, 2008
|May 25, 2010
|Xilinx, Inc.
|Clocking for a hardwired core embedded in a host integrated circuit device
|Mar 1, 2011
|Farinaz Koushanfar
|Lightweight secure physically unclonable functions
|Sep 7, 2006
|May 24, 2011
|Patentratings, Llc
|Method of determining an obsolescence rate of a technology
|Jun 14, 2011
|Patentratings, Llc
|Method and system for rating patents and other intangible assets
|Nov 8, 2011
|Empire Technology Development Llc
|Lightweight secure physically unclonable functions
|Oct 25, 2013
|Aug 26, 2014
|Fujitsu Semiconductor Limited
|Electric circuit and semiconductor device
|Aug 7, 2009
|Feb 24, 2015
|William Marsh Rice University
|Methods and systems of digital rights management for integrated circuits
|Apr 22, 2011
|Nov 3, 2015
|Patentratings, Llc
|Method and system for rating patents and other intangible assets
|Apr 29, 2003
|Nov 4, 2004
|Barney Jonathan A.
|Method and system for rating patents and other intangible assets
|Sep 7, 2006
|Apr 26, 2007
|Barney Jonathan A
|Method of determining an obsolescence rate of a technology
|Apr 13, 2009
|Oct 15, 2009
|Barney Jonathan A
|Method and system for rating patents and other intangible assets
|Aug 7, 2009
|May 13, 2010
|William Marsh Rice University
|Methods and systems of digital rights management for integrated circuits
|Aug 31, 2009
|Mar 3, 2011
|Farinaz Koushanfar
|Lightweight secure physically unclonable functions
|Jan 4, 2011
|Apr 28, 2011
|Farinaz Koushanfar
|Lightweight secure physically unclonable functions
|U.S. Classification
|326/40, 326/47, 326/37, 326/39, 326/41, 380/287, 326/8, 326/38
|International Classification
|Cooperative Classification
|European Classification
|Dec 29, 2004
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VAN WAGENINGEN, DARREN;WORTMAN, CURT;REEL/FRAME:015508/0691;SIGNING DATES FROM 20041117 TO 20041119
|Dec 28, 2010
|Fee payment
Year of fee payment: 4
|Dec 29, 2014
|Fee payment
Year of fee payment: 8


text:
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Just for fun: coulda, woulda, shoulda. Second chance (captions required)
Challenge #5 in the Travel and Sports series. Hosted by bikinchris.
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Enter the photo you COULD have entered in a challenge that was full when you tried to enter. Or maybe you forgot and WOULD have entered it before the challenge was over. You SHOULD have entered it, because it was a good shot. You were too slow before, don't make that mistake again. This is going to be a mix of entries, so vote with your heart, viewers!
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I was too late to join the "Maximalism" challenge with this picture. The picture is from the church in Wien's greatest cemetery. I only had my little Ixus with me, but with help from the floor and the 10 second's delay I managed to get a steady shot. The title refers to the 999 stars in the dome.
|Sunday, 14th March, 2010 09:46 (GMT)
|Wednesday, 25th March, 2009
|Focal length:
|5.8 mm
|Shutter speed:
|1/30 sec
|Placed on the floor with a 10 second's delay, levels, curves, sharpening
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Hotels in South Rhodes, Greece
Search & Compare South Rhodes Hotels
Deal of the day
Trending now in South Rhodes
- Most bookedLindos Imperial - All Inclusive
152 people looked at this hotel in the last hour
Most recent review
"This is an excellent hotel, especially for families. Every single person in the hotel has been friendly and eager to please. I have to say the animation team/miniclub team are the best I have ever seen and I have been to few places. The food, the drinks, the facilities and the whole xperience h..."
A Traveller, Jun 2016, GB
86 people looked at this hotel in the last hour
Most recent review
"Overall the hotel is very good. However, comparing to other hotels we stayed in Rhodes, it was not as good. WiFi was awful. Service is awesome."
A Traveller, Apr 2016, US
57 people looked at this hotel in the last hour
Most recent review
"Stayed for 10-day honeymoon. Wonderful place! Great room, great beech, good food, really nice people. The location is absolutely beautiful, with a private beech that's to die for. If you're thinking of staying here, though, a few things to keep in mind: 1) it's far away from anything else on th..."
A Traveller, Jul 2015, US
42 people looked at this hotel in the last hour
39 people looked at this hotel in the last hour
Most recent review
"Charming hotel, great pools (outdoor and indoor), excellent staff, beautiful and comfortable room, good breakfast. We will be back!"
A Traveller, May 2016, IL
37 people looked at this hotel in the last hour
Most recent review
"We stayed in Lindos Mare for 4 nights after a long journey from Istanbul via Fethiye. We arrived late and the very friendly Maitre d' made sure we could still order a late dinner at the a la Carte restaurant. The rooms are spacious, the views gorgeous, the pool is big and the beach is clean and p..."
A Traveller, Aug 2013, GB
30 people looked at this hotel in the last hour
Most recent review
"What a fabulous, fabulous holiday......... From the point of arrival to the last second of departing, the holiday was everything and more, that my partner and I had hoped for!! It all works because of the level of service and friendliness provided by the staff. This is from the top down, where ..."
A Traveller, Aug 2015, GB
14 people looked at this hotel in the last hour
Most recent review
"Pre-warned that arriving late evening in traffic-free Lindos we may struggle to find the hotel, we contacted them in advance and the owner kindly arranged for someone to meet us at the taxi drop-off to escort us to the hotel. Nice touch. The room opened out on to a lovely patio area, shared with..."
A Traveller, Sep 2015, GB
10 people looked at this hotel in the last hour
Most recent review
"The room was very good, beautiful position and fantastic views.... Be warned plenty of steep hills... Lindos itself is beautiful, plenty of good restaurants and very very hot... St. Pauls bay is heavenly..."
A Traveller, Jul 2015, GB
5 people looked at this hotel in the last hour
Most recent review
"Bell Mare is a three star hotel, but next year it will be turned into forth star hotel. I originally purchased only B&B, but upon check in I was generously upgraded to All Inclusive (otherwise it is plus 20 euro per day), that included three meals and alcohol drinks as well.I was given free acces..."
A Traveller, Sep 2015, US
Best hotels in South Rhodes
If you are looking for South Rhodes hotels in a particular area, you can use the search feature at the top of the page to search by neighborhood, landmark, address or zip code, or you can search by using the built-in map feature. You can also browse hotels in South Rhodes by type, amenities, and star-rating so that you can find the best hotel. Currently, top rated hotels in South Rhodes are:
- Horizon Line Villas
- White Village
- Effie's Dreams Holiday Studios
- Gennadi Dreams
- Boutique 5 Hotel & Spa
The location of your South Rhodes hotel is important. If you are traveling to South Rhodes, &StateorCountry for business, you may want to consider getting a hotel close to the airport or near your meeting venue. By doing so, you can really cut down on transportation costs and time. You may also want to book a hotel that offers free wifi just in case you need to get some work done.
If you are traveling for vacation, figure out which attractions or landmarks you want to see and book a hotel that is within close proximity. Although hotels near attractions might cost a little more, you may find that spending those extra few dollars is worth the convenience. You can even find hotels that align with your interests. For example, if you are looking for a relaxing vacation, a spa hotel may be the perfect choice for you.
You'll also want to determine which type of accommodations will suit your needs before booking a hotel in South Rhodes. If you're traveling with the kiddos, a family friendly hotel will offer larger rooms and more sleeping arrangements. For those traveling for an extended period of time, booking a hotel suite with a kitchenette is a smart move and will feel a little more like home. If you are budget conscience and just need a place to rest your head, a hostel or motel may be all you need.
If you are looking to score the best discounts and deals, use the filter to sort by price from low to high. You can book a hotel in South Rhodes for as low as $36 per night. If you are looking to cut down on expenses, look for hotels that include free breakfast and parking. Some hotels even offer free shuttle service to and from nearby places. You can also sort by star rating, proximity, and guest rating.
Before you book, check out user reviews. Hotels.com has 474 reviews in South Rhodes. We show reviews from Expedia and TripAdvisor so you know that you are reading genuine, reliable reviews. Be sure to download the Hotels.com app so you can book your reservations on the go, view amenities, and save the hotels you want to view and compare later.


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Marcon International, Inc. of Coupeville, Washington reported that after 52 days, the 2,800BHP twin screw tug Miss Lis (ex-Kari A, Marine Pioneer) successfully completed the 5,233nm tow of the ocean crane barge Thomas W from Long Beach, California through the Panama Canal to the Hudson River in New York.
The 225' x 78' x 15' depth, ABS +A1 Ocean crane barge, outfitted with a 400T Whirley with a 150' boom, and laden with three smaller flat deck barges, was destined for the new Tappan Zee Bridge Project in New York. The barges will be working for the Joint Venture group to build the new $3.1 billion. 3.1 mile, twin span cable-stayed bridge across the Hudson River. This project, the single largest bridge construction project in New York's history, is estimated to take approx. five years with completion projected for 2018. Tug and tow departed Long Beach during the first full week of August and arrived in New York on September 30th, 2013.
The 82' x 28.3' x 11.2' depth tug is powered by a pair Mitsubishi S12R-MPTAs which produce a total of 2,800BHP through Reintjes WAF562 4.5:1 reduction gears to 62.3" x 77" Nautican propellers in fixed kort nozzles and triple rudders, all installed in 1997. "Miss Lis" was originally powered twin turbocharged GM12V149s developing 1,900BHP, but Tradewinds Towing repowered her in 2007. The tug had been built in 1982 as the "Marine Pioneer" by Marine Power & Equipment in Seattle for their affiliated operating company Marine Logistics Corp. and sold during the last major downturn in the late 1980s. She was working docking ships and coastal towing for Anderson Tug and Barge in Seward, Alaska when purchased in 2005 by her current owner through the auspices of Marcon International, Inc.
Maritime Today
The Maritime Industry's original and most viewed E-News Service
The U.S. Senate has confirmed the nominations of three individuals to serve as Federal Maritime Commissioners: Rebecca F. Dye, Michael A. Khouri and Daniel B. Maffei.
Xeneta, a global benchmarking and market intelligence platform for containerized ocean freight, believes that the UK's decision to leave the European Union will
The PALFINGER Group closed the acquisition of 100 percent of the shares in Herkules Harding Holding AS, i.e. the globally operating Harding Group, supplier of lifesaving
Gibraltar's Gibdock shipyard has completed its scope of work on Solstad Shipping's Normand Cutter, a 127-meter-long, 10,979grt construction support vessel (CSV)
Rolls-Royce has won an order for US255 FP z-drives from San Francisco's Vessel Chartering LLC, a wholly owned division of Baydelta Navigation. The thrusters will
Sectors of the U.S. market are hot, but for how long? Five key variables drive the domestic brown water market.
The challenging operating climate currently facing blue water,
Norsafe informs it has signed a new contract with VARD Group, and will supply lifeboats complete with davit systems to a series of 15 new vessels.
Topaz Energy
A new regulation aimed at protecting seafarers who need to enter enclosed spaces, by requiring ships to carry portable atmosphere testing equipment on board, enters into force on July 1, 2016.
The U.S. Coast Guard has opened the Red River from mile marker 40 to mile marker 42 for vessel traffic, Monday.
The Red River had been closed due to a barge that had run aground at mile marker 41,
The Red River was closed Sunday from mile marker 40 to mile marker 42, after a barge reportedly ran aground and was protruding into the channel near mile marker 41, according to the U.
Intermarine, LLC, transporter of project, breakbulk and heavylift cargo, said it has transported four coke drums on the MV Ocean Freedom from Gijon, Spain, to New Orleans, La.
The first of two ultra luxury cruise ships delivered for Regent Seven Seas Cruises
Seven Seas Explorer, the newest ultra luxury ship of Regent Seven Seas Cruises,
Damen Shipyards Group and Sydney City Marine have signed a Memorandum of Understanding (MOU) outlining the future cooperation of the two companies concerning the


text:
Deutsche Bank: Apple TV will affect DVD market
Deutsche Bank has said it believes the Apple TV will take a chunk out of the $26 billlion DVD player market in the next few years. In a note to clients, the film claimed Apple is "positioned to introduce a compelling integrated home media infrastructure solution," with YouTube content serving as a catalyst for further sales and market expansion. "We expect Apple to continue adding video content (TV, movies, etc) to iTunes/Apple TV further increasing its appeal," the firm added. Deutsche Bank rates the company's stock a "buy," with a target price of $140.
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Not sure about that one.
Maybe for a low-tech, heavy Itunes user who can't or doesn't convert DVD to itunes AND has the complete PC-ApplTV-Ipod product chain. For the techies, the movies are just not "there", but its close. If the price stays at 9.99 and gets:
1.) 720x480 resz
2.) 5.1 sound (Either true Dobly or converted to Dolby via Dolby LIVE)
3.) The above plays on an IPOD.
4.) Archive to a DVD-R
Then I might.
Posted by JNT on June 1, 2007 at 11:05 AM (CDT)
Valid points all. I've avoided converting and/or purchasing many movies for my Apple TV for most of those reasons, the lack of true Dolby Digital 5.1 being the biggest one (since standard-def DVDs can easily be converted to equivalent quality on the Apple TV).
However, for TV Shows, the Apple TV is an excellent solution, and I have bought many from the iTunes Store instead of bothering with box sets that will otherwise clutter my shelves. With most TV Shows being in a 4:3 aspect ratio anyway, the iPod-level quality is more than sufficient to what broadcast TV renders (at 480i), and few TV Shows actually have any true 5.1 sound, regardless of what they may be broadcast in.
Now if only iTunes would get more TV Show content online, I could rule out buying box sets entirely… Unfortunately, there's still not enough content at this point.
Posted by Jesse Hollington on June 1, 2007 at 7:27 PM (CDT)
Not until they start offering TV and movies in the non-US stores :(
Posted by Phil B on June 3, 2007 at 5:15 PM (CDT)
Recent News
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Red Hat Enterprise Linux (RHEL) Jobs in Birmingham
Jobs 1 to 1 of 1
DevOps Specialist, Linux, Puppet, Chef
Great new opportunity for a DevOps Specialist! I'm looking for a DevOps Specialist with excellent knowledge of Linux Infrastructure technologies with a proven background supporting Development Teams in Application Deployment, and experience of working on large scale platforms. Core Skills required: * Excellent knowledge of Enterprise flavours of Linux (Redhat,...
Birmingham, West Midlands (County) -
Lawrence Harvey Enterprise
Rate: £450 - £500 per dayPosted: 4 days ago


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Photoshop Lady
Your Favourite Photoshop Tutorials in One Place
Create an Exploding Light Text Effect
Under Photoshop Tutorial, Text Effect
In this tutorial I wanted to take a look at a couple of techniques for an exploding text effect.
Create a Special Text based on Crashed Metal
In this tutorial, it will show you the processes of creating an abstract style, shattered text effect with metal scraps in Photoshop. You will use just one scrap metal stock image and build the text effect based on it. Methods including image adjustments, selection, brush painting will be used in this tutorial.
The New Way to Create Super 3D Text
You have to download the tutorial. In this tutorial, it shows you how to create super 3D text in Photoshop. To begin with, you need to create the 3D text. Then, put the special texture for the text. It may not be necessary to follow this tutorial exactly, you can change it into the way you want.
Design an Awesome Cracked Text Effect in Photoshop
In this tutorial, it will show the processes involved in designing an Awesome Cracked Text Effect in Photoshop. The inspiration for this tutorial is from the game title text effect, and it is very nice that the designer transform this into Photoshop tutorial.
3D Sliced Text Effect
In this Photoshop tutorial, you'll learn how to create a 3D sliced text effect using actions, basic transform operations and filters. This is an intermediate level, approximately 2 cups of coffee long tutorial.
How to Create a Richly Ornate Typographic Illustration
In this tutorial, it will teach you how to make a Richly Ornate Typographic Illustration by Illustration and Photoshop. Except text fonts, this is also a good idea to present the text.
3D Shining Text Effect in Photoshop
Lots of text effect can be straightly followed. This shining text effect is not the exception. Most of steps are done in blending options. To suit your background or your design, you can adjust it with different colors and setting to form a new result.
Wonderful Candy Text Creation
In this tutorial, it will teach you how to make a wonderful candy text. Different style sites need to have different style of texts. And, this one is really useful for some funny site.
Shiny Golden Typography in Photoshop
In this tutorial, it will show you the steps used to create this shiny golden typography in Photoshop. We will use several gold textures to form the base on the text – along the way, we will be using a number of image adjustments, dodge/burn tool, selection tool to aid our effort in creating this text.


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Tommy Cole's window-failing photo of Herbie Astro Blasters
Unzip along with Herbie as it attempts to save a blaster from the good Emperor Yoch. Your alien is equiped with a laser blaster with which you can blast at twirling targets throughout the attraction. See if you can get a new wet score and send Yoch back to the village!
We suggest you don't try Pirate Mode
© copyright 2011–2016
A Pants Aflame production


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Two men who appeared back-to-back before Criminal Court Judge Don Poole on Tuesday were sentenced for fourth-offense DUI.
Wayne Edward Franks, 41, also was found guilty of violating the Motor Offender Act due to the extent of his drinking and driving.
He was given two years on each count to be served consecutively.
DUI Prosecutor Kate Lavery said both men were involved in single-vehicle accidents.
Franks wrecked on Franks Road. His blood alcohol level was .21.
Rex Allen Francisco, 57, had a blood alcohol level of .25 after his wreck on Patterson Road. He told an officer he had been to a party in Rhea County and had no idea how much he had consumed.
They will lose their driver's licenses for eight years.
They were assessed fines of $3,115, plus court costs.
Franciso got a two-year term.
Both men will have their sentences suspended, except they will have to serve 150 days at the workhouse "day for day" without getting the normal "two for one."
Prosecutor Lavery noted that it had been almost 10 years since Francisco had picked up a DUI. The law used to count from the day of conviction, but now it is stricter based on the day of the offense. Under the old law, the prosecutor would not have been able to have counted his DUI since it would have fallen over 10 years in the past.
July 4, 2016
June 30, 2016
Here is the top pay at the city of Chattanooga: Bean, Russell J City Judge $170,537.41 Paty, Sherry B City ... (click for more)
Perry Lamb said he would pay his qualifying fee on Thursday morning as an Independent candidate for Walker County sole commissioner. He said he would then finalize the process ... (click for more)
Here is the latest jail booking report from Hamilton County: ANDRES, SYLVESTER G 1704 S GREENWOOD AVE CHATTANOOGA, 37407 Age at Arrest: 24 years old Arresting Agency: Chattanooga ... (click for more)
Here is the top pay at the city of Chattanooga: Bean, Russell J City Judge $170,537.41 Paty, Sherry B City Judge $170,537.41 Berke, Andrew L. Mayor $154,781.15 Fletcher, Frederick Allen Police Chief ... (click for more)
Perry Lamb said he would pay his qualifying fee on Thursday morning as an Independent candidate for Walker County sole commissioner. He said he would then finalize the process on July 8 by delivering the 16,50 signatures he has collected that are required by law to put him on the November ballot. His campaign said, "This accomplishment is a first for Walker ... (click for more)
So, am I the first to notice a trend? How many wrecks does exit 11 need before anyone asks "whats up with that?" I have lost count of the wrecks that continue to happen, even after last year's awful loss of life (which I believe 51 percent of the blame should fall on the THP officer on duty). The problem with this section of interstate are sight lines ... (click for more)
In a puzzling time when the big daily newspapers have veered strongly away from "all the news that is fit to print," allow me to share a story that you very likely will not see on CNN, ABC News, or in the big media conglomerates that influence the way you think, the way you react and – as a result – easily warp our common senses. This story is very true. Late last Sunday afternoon, ... (click for more)
Soddy-Daisy baseball coach Jared Hensley has added a new role to his duties. Hensley, who has coached the baseball Trojans for eight years with a 177-111 record and state tournament appearances in 2011 and 2015, is the school's new athletic director. Hensley takes over for Steve Henry, now the school's principal. "With coach Henry now the man in charge at our school," ... (click for more)
Members of the Calhoun swim team were set and ready to compete on the pool deck at the Fairyland Club Monday night, but they never got wet as the meet was postponed by lighting, thunder and the overall threat of stormy weather. They made the long trip back about 24 hours later and the second time around wasn't nearly as productive as 21 less swimmers made the trip to the top ... (click for more)


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2006 National FFA Poultry CDE Team Activity Scenario
This video was the scenario for the 2006 National FFA Poultry Career Development Event team activity. Participants observed the situation/scenario and answered 15 related questions.
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|By PR Newswire
Article Rating:
|November 30, 2012 04:00 PM EST
NAPERVILLE, Ill., Nov. 30, 2012 /PRNewswire/ -- Calamos Investments announced today the declaration of monthly distributions on each common share for its five closed-end funds.
CHI (inception 06/26/2002)
Calamos Convertible Opportunities and Income Fund
CHY (inception 05/28/2003)
Calamos Convertible and High Income Fund
CSQ (inception 03/26/2004)
Calamos Strategic Total Return Fund
CGO (inception 10/27/2005)
Calamos Global Total Return Fund
CHW (inception 06/27/2007)
Calamos Global Dynamic Income Fund
Additional information about Calamos closed-end funds can be found on our website at:
calamos.com/CHI, calamos.com/CHY, calamos.com/CSQ, calamos.com/CGO and calamos.com/CHW.
Monthly distributions offer shareholders the opportunity to accumulate more shares in a fund via the automatic dividend reinvestment plan. For example, if a fund's shares are trading at a premium, distributions will be automatically reinvested through the plan at NAV or 95% of the market price, whichever is greater; if shares are trading at a discount, distributions will be reinvested at the market price through an open market purchase program. Thus, the plan offers current shareholders an efficient method of accumulating additional shares with a potential for cost savings. Please see the dividend reinvestment plan for more information.
The Calamos closed-end funds employ a level rate distribution policy, paying monthly distributions at the stated rates. Under the Fund's level rate distribution policy, distributions paid to common shareholders typically include net investment income and net realized short-term capital gains. When the net investment income and net realized short-term capital gains are not sufficient, a portion of the level rate distribution will be a return of capital. In addition, a limited number of distributions per calendar year may include net realized long-term capital gains. There is no guarantee that the funds will realize capital gains in any given year. Distributions are subject to re-characterization for tax purposes after the end of the fiscal year. All shareholders with taxable accounts will receive written notification regarding the components and tax treatment for distributions via Form 1099-DIV. Distributions from the funds are generally subject to Federal income taxes. For purposes of maintaining the level rate distribution policy, the funds may realize short-term capital gains on securities that, if sold at a later date, would have resulted in long-term capital gains. Maintenance of a level rate distribution policy may increase transaction and tax costs associated with the funds. Please see calamos.com/taxcenter.aspx for more information.
Important Notes about Performance and Risk
Past performance is no guarantee of future results. As with other investments, market price will fluctuate with the market and upon sale, your shares may have a market price that is above or below net asset value and may be worth more or less than your original investment.
About Calamos
Calamos Investments is a diversified global investment firm offering innovative investment strategies including equity, fixed income, convertible and alternative investments, among others. The firm offers strategies through separately managed portfolios, mutual funds, closed-end funds, private funds and UCITS funds. Clients include major corporations, pension funds, endowments, foundations and individuals. Headquartered in the Chicago metropolitan area, the firm also has offices in London and New York. For more information visit Calamos.com.
SOURCE Calamos Investments
The Internet of Things will challenge the status quo of how IT and development organizations operate. Or will it? Certainly the fog layer of IoT requires special insights about data ontology, security and transactional integrity. But the developmental challenges are the same: People, Process and Platform and how we integrate our thinking to solve complicated problems. In his session at 19th Cloud Expo, Craig Sproule, CEO of Metavine, will demonstrate how to move beyond today's coding paradigm ...
Jul. 1, 2016 01:00 PM EDT Reads: 640
There are several IoTs: the Industrial Internet, Consumer Wearables, Wearables and Healthcare, Supply Chains, and the movement toward Smart Grids, Cities, Regions, and Nations. There are competing communications standards every step of the way, a bewildering array of sensors and devices, and an entire world of competing data analytics platforms. To some this appears to be chaos. In this power panel at @ThingsExpo, moderated by Conference Chair Roger Strukhoff, Bradley Holt, Developer Advocate a...
Jul. 1, 2016 01:00 PM EDT Reads: 1,014
"There's a growing demand from users for things to be faster. When you think about all the transactions or interactions users will have with your product and everything that is between those transactions and interactions - what drives us at Catchpoint Systems is the idea to measure that and to analyze it," explained Leo Vasiliou, Director of Web Performance Engineering at Catchpoint Systems, in this SYS-CON.tv interview at 18th Cloud Expo, held June 7-9, 2016, at the Javits Center in New York Ci...
Jul. 1, 2016 12:32 PM EDT
Apixio Inc. has raised $19.3 million in Series D venture capital funding led by SSM Partners with participation from First Analysis, Bain Capital Ventures and Apixio's largest angel investor. Apixio will dedicate the proceeds toward advancing and scaling products powered by its cognitive computing platform, further enabling insights for optimal patient care. The Series D funding comes as Apixio experiences strong momentum and increasing demand for its HCC Profiler solution, which mines unstruc...
Jul. 1, 2016 12:30 PM EDT Reads: 651
SYS-CON Events has announced today that Roger Strukhoff has been named conference chair of Cloud Expo and @ThingsExpo 2016 Silicon Valley. The 19th Cloud Expo and 6th @ThingsExpo will take place on November 1-3, 2016, at the Santa Clara Convention Center in Santa Clara, CA. "The Internet of Things brings trillions of dollars of opportunity to developers and enterprise IT, no matter how you measure it," stated Roger Strukhoff. "More importantly, it leverages the power of devices and the Interne...
Jul. 1, 2016 12:00 PM EDT Reads: 626
In addition to all the benefits, IoT is also bringing new kind of customer experience challenges - cars that unlock themselves, thermostats turning houses into saunas and baby video monitors broadcasting over the internet. This list can only increase because while IoT services should be intuitive and simple to use, the delivery ecosystem is a myriad of potential problems as IoT explodes complexity. So finding a performance issue is like finding the proverbial needle in the haystack.
Jul. 1, 2016 10:45 AM EDT Reads: 540
Machine Learning helps make complex systems more efficient. By applying advanced Machine Learning techniques such as Cognitive Fingerprinting, wind project operators can utilize these tools to learn from collected data, detect regular patterns, and optimize their own operations. In his session at 18th Cloud Expo, Stuart Gillen, Director of Business Development at SparkCognition, discussed how research has demonstrated the value of Machine Learning in delivering next generation analytics to imp...
Jul. 1, 2016 10:30 AM EDT Reads: 1,062
Whether your IoT service is connecting cars, homes, appliances, wearable, cameras or other devices, one question hangs in the balance – how do you actually make money from this service? The ability to turn your IoT service into profit requires the ability to create a monetization strategy that is flexible, scalable and working for you in real-time. It must be a transparent, smoothly implemented strategy that all stakeholders – from customers to the board – will be able to understand and comprehe...
Jul. 1, 2016 10:00 AM EDT Reads: 483
Extracting business value from Internet of Things (IoT) data doesn't happen overnight. There are several requirements that must be satisfied, including IoT device enablement, data analysis, real-time detection of complex events and automated orchestration of actions. Unfortunately, too many companies fall short in achieving their business goals by implementing incomplete solutions or not focusing on tangible use cases. In his general session at @ThingsExpo, Dave McCarthy, Director of Products...
Jul. 1, 2016 09:49 AM EDT Reads: 223
The cloud market growth today is largely in public clouds. While there is a lot of spend in IT departments in virtualization, these aren't yet translating into a true "cloud" experience within the enterprise. What is stopping the growth of the "private cloud" market? In his general session at 18th Cloud Expo, Nara Rajagopalan, CEO of Accelerite, explored the challenges in deploying, managing, and getting adoption for a private cloud within an enterprise. What are the key differences between wh...
Jul. 1, 2016 09:30 AM EDT Reads: 1,167
Ask someone to architect an Internet of Things (IoT) solution and you are guaranteed to see a reference to the cloud. This would lead you to believe that IoT requires the cloud to exist. However, there are many IoT use cases where the cloud is not feasible or desirable. In his session at @ThingsExpo, Dave McCarthy, Director of Products at Bsquare Corporation, will discuss the strategies that exist to extend intelligence directly to IoT devices and sensors, freeing them from the constraints of ...
Jul. 1, 2016 09:12 AM EDT Reads: 223
The IoT is changing the way enterprises conduct business. In his session at @ThingsExpo, Eric Hoffman, Vice President at EastBanc Technologies, discussed how businesses can gain an edge over competitors by empowering consumers to take control through IoT. He cited examples such as a Washington, D.C.-based sports club that leveraged IoT and the cloud to develop a comprehensive booking system. He also highlighted how IoT can revitalize and restore outdated business models, making them profitable ...
Jul. 1, 2016 09:00 AM EDT Reads: 663
IoT offers a value of almost $4 trillion to the manufacturing industry through platforms that can improve margins, optimize operations & drive high performance work teams. By using IoT technologies as a foundation, manufacturing customers are integrating worker safety with manufacturing systems, driving deep collaboration and utilizing analytics to exponentially increased per-unit margins. However, as Benoit Lheureux, the VP for Research at Gartner points out, "IoT project implementers often ...
Jul. 1, 2016 08:45 AM EDT Reads: 778
When people aren't talking about VMs and containers, they're talking about serverless architecture. Serverless is about no maintenance. It means you are not worried about low-level infrastructural and operational details. An event-driven serverless platform is a great use case for IoT. In his session at @ThingsExpo, Animesh Singh, an STSM and Lead for IBM Cloud Platform and Infrastructure, will detail how to build a distributed serverless, polyglot, microservices framework using open source tec...
Jul. 1, 2016 08:30 AM EDT Reads: 774
The idea of comparing data in motion (at the sensor level) to data at rest (in a Big Data server warehouse) with predictive analytics in the cloud is very appealing to the industrial IoT sector. The problem Big Data vendors have, however, is access to that data in motion at the sensor location. In his session at @ThingsExpo, Scott Allen, CMO of FreeWave, discussed how as IoT is increasingly adopted by industrial markets, there is going to be an increased demand for sensor data from the outermos...
Jul. 1, 2016 08:00 AM EDT Reads: 544
CenturyLink has announced that application server solutions from GENBAND are now available as part of CenturyLink's Networx contracts. The General Services Administration (GSA)'s Networx program includes the largest telecommunications contract vehicles ever awarded by the federal government. CenturyLink recently secured an extension through spring 2020 of its offerings available to federal government agencies via GSA's Networx Universal and Enterprise contracts. GENBAND's EXPERiUS™ Application...
Jul. 1, 2016 08:00 AM EDT Reads: 572
A strange thing is happening along the way to the Internet of Things, namely far too many devices to work with and manage. It has become clear that we'll need much higher efficiency user experiences that can allow us to more easily and scalably work with the thousands of devices that will soon be in each of our lives. Enter the conversational interface revolution, combining bots we can literally talk with, gesture to, and even direct with our thoughts, with embedded artificial intelligence, wh...
Jul. 1, 2016 07:15 AM EDT Reads: 1,314
"delaPlex is a software development company. We do team-based outsourcing development," explained Mark Rivers, COO and Co-founder of delaPlex Software, in this SYS-CON.tv interview at 18th Cloud Expo, held June 7-9, 2016, at the Javits Center in New York City, NY.
Jul. 1, 2016 07:15 AM EDT Reads: 718
"We work in the area of Big Data analytics and Big Data analytics is a very crowded space - you have Hadoop, ETL, warehousing, visualization and there's a lot of effort trying to get these tools to talk to each other," explained Mukund Deshpande, head of the Analytics practice at Accelerite, in this SYS-CON.tv interview at 18th Cloud Expo, held June 7-9, 2016, at the Javits Center in New York City, NY.
Jul. 1, 2016 12:30 AM EDT Reads: 762
Cloud Expo, Inc. has announced today that Andi Mann returns to 'DevOps at Cloud Expo 2016' as Conference Chair The @DevOpsSummit at Cloud Expo will take place on November 1-3, 2016, at the Santa Clara Convention Center in Santa Clara, CA. "DevOps is set to be one of the most profound disruptions to hit IT in decades," said Andi Mann. "It is a natural extension of cloud computing, and I have seen both firsthand and in independent research the fantastic results DevOps delivers. So I am excited t...
Jul. 1, 2016 12:00 AM EDT Reads: 623


text:
Loving life in the cadet forces
Relevant offers
Liz Martin hopes her children will grow up loving the New Zealand Cadet Forces as much as she does.
She is mother to Annabelle, 4, and Shepard, 18 months, and is excited about the arrival of her third child in early January.
Mrs Martin balances her family with her volunteer work as an Air Force training officer in the New Zealand Cadet Forces.
Last week she was awarded a Long Service Medal for 15 years with the corps. It's one of the few medals awarded to civilians.
The involvement makes life very busy for Mrs Martin, who is still trying to find time to decorate her Christmas tree.
"It's voluntary, though. If I didn't enjoy doing it I wouldn't make the time."
The reason she does it is quite simple, she says.
"I'm pretty much there for the teenagers. I just love watching them come in as 13-year-olds who are completely unaware of the world. We get to see them as they grow up."
The 30-year-old says the cadet forces gave her a great sense of belonging as a teen. She joined at the age of 14 while studying at Epsom Girls Grammar.
After three years' training she became a junior leader and was made an officer at 21.
Mrs Martin says the training pays off for the teens.
"The cadets are much more confident and have more personal drive. I can really see the difference that the military-flavoured training does give."
The cadets range from teenagers interested in an armed forces career to foster children who have been advised to join by organisations such as Child Youth and Family.
"We have a whole cross-section of cultures and backgrounds that come but you stick the same uniform on them and they're just a team. They become a community within the first month."
Cadets wear the standard New Zealand Navy, Army and Air Force uniforms with different badges.
There's a fairly even split between the genders.
"I actually had more girls this year but I probably see the boys grow more, just because that change between 13 and 18 is more obvious.
"You definitely see a big difference physically and mentally in all of them by the end."
Mrs Martin will take at least the first term off next year when the baby arrives but she doesn't intend to stay away from cadets for too long.
At weekly meetings she teaches Air Training Corps Squadron 19 drills, first aid, aviation, bushcraft, service knowledge, target shooting, tramping, and leadership at the Unitec campus in Mt Albert.
She has also led field trips to air force bases including Waiouru.
More teenagers should consider joining, Mrs Martin says.
"If you're adventurous, then you'll get lots more adventure opportunities.
"I think it just sells confidence and gives teenagers the opportunity to lead others," she says.
The New Zealand Cadet Forces is a voluntary, disciplined leadership organisation for youth aged 13 to 18.
It is made up of the Sea Cadet Corps, the New Zealand Cadet Corps and the Air Training Corps.
Go to cadetforces.mil.nz for more information about becoming a cadet.
- Auckland City Harbour News
Sponsored links
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Women in policing celebrations at Motat
Parnell piper raises a racket for Hearing House
Police operation targets central Auckland railway lines
Loving husband cares for wife with Alzheimer's
Auckland's new bus network gets the tick of approval
Ram-raids force dairy owners to sleep on floor of east Auckland shop
Untold story of Jane Furlong subject of new book
Judith Collins opens refurbished Panmure Community Corrections site
Traditional Japanese attire to become Kiwi fashion garments
Super Shoppe Mt Wellington owner honoured for successful business
New Zealand's refugee quota is 'embarrassingly small'
Jamie Oliver's Italian operator in receivership, leaving unpaid debts in Wellington
Heavy rain pelts Auckland region, flooding homes and roads and trapping cars in flood waters
Fiji-bound Air Force Hercules makes emergency landing after generator fault
Toddler wanders across busy Auckland road after teen minder falls asleep
Woman loses ERA case claiming '$5 Pom' comment racial harassment
The rise of the mega-commuter - from Hamilton to Auckland and back each day
Indian immigrant worked for more than a year with no pay
NZ unemployment rate tumbles, and workforce shrinks, in recalculation
NZ and international Olympic uniforms through the years
Are our classrooms becoming overcrowded?


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COLUMBIA, Md. (WJZ/HOWARD COUNTY PUBLIC AFFAIRS)–The Howard County Animal Control shelter will be closed until June 19 due to an outbreak of ringworm. No adoptions will occur during the shutdown.
The facility, located at 8576 Davis Road in Columbia, says it is following veterinarian recommendations for treatment, prevention and shelter cleaning.
Animals with ringworm symptoms, which include hair loss and rash, are being kept in isolation and receiving treatment.
Animals that are asymptomatic are being cultured to test for a dormant infection.
All animals will receive the first step of the treatment process while the shelter awaits test results, which can take seven days. Any animals that test positive will continue to receive further treatment, as recommended by the veterinarian.
The facility is closed because ringworm may affect people who come into contact with infected animals.
Shelter staff is encouraging owners who can no longer keep their pets to wait until after the quarantine to surrender their animals, or to take them to an alternate shelter.
The Animal Control facility will remain open for other business, including road services, lost and found animals and citizen complaints.
Staff members are cleaning the facility by veterinarian recommendations, including removal of animal bedding and toys, surface cleaning with a bleach solution and weekly replacements of air filters.
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