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Issue date: Monday, October 1, 2001
Pages available: 78
Previous edition: Sunday, September 30, 2001
Next edition: Tuesday, October 2, 2001
Publication name: Altoona Mirror
Location: Altoona, Pennsylvania
Pages available: 2,271,029
Years available: 1876 - 2014Learn more about this publication
Altoona Mirror (Newspaper) - October 1, 2001, Altoona, Pennsylvania INSIDE TODAY SPORTS: Steelers record first win of season Bl LIFE: Christian artists to perform at Jaffa Copyright 2001 MONDAY, OCTOBER 1, 2001 Coping with a tragedy Area students raise rnipney and write letters to come to terms with the Sept. 11 terrorist attacks. BY JAY YOUNG StaffWriter CW. Longer Elementary School fourth-grader Domenic Cuzzolina feels better these days, a lot better than three weeks ago. lot of children are smiling again as things slowly return to normal. Normalcy, or as close as they can get after the Sept. 11 terrorist attacks, has been accomplished in schools by teachers setting aside portions of regular plans to allow time to cope. .It was a need that became apparent early in the school day Sept. 12. Younger students may not have a com- plete understanding of what has happened, but they have a sense that something is wrong. "They Eire dealing with some really strong emotions thai they aren't used to dealing Ixiiiger counselor Irish Gray said. "They are little sponges for picking up on the emotional tone in the community, in school and at home. They look to us to sec if they're OK, and when they look at us and we're not OK, then they know they're not OK, either." The motions were so strong for Cuzzolina the day after the attacks that classroom work noarl was impossible. During a visit to the office that day, the boy shared an idea he and his 12-year-old brother discussed. "We came up with this, and it was a real- ly good Cuzzolina said, sitting in front of a desk covered with pennies, nick- els, dimes and quartos. In the background, other students counted change, while fourth-graders Anahi Meneses Bucio and Kaitlyn Felty spread out a pile of crumpled dollar bills. The more than raised so far will go to the Salvation Army to assist in their relief efforts. But first, it must be counted. Gray thought about finding an automatic com counter, hut she realized that might defeat tlie purpose. "I think the actual physical act of count- ing is more memorable for she said. Please see A6 WAR ON TERRORISM COVERAGE: PAGES A6, A7, C1, C3 500 newsstand Mmoi pholos by Jay Young Above: C.W. Longer Elementary School fourth- grader AnaM Meneses Bucio counts a portion of the money she and her classmates collected for a relief fluid to help those touched by the Sept. 11 terrorist attacks. School staff bad the students count the money by hand to help them cope with the strong feelings sparked by the tragedy. At right: Longer fourth-grader Domenic Cuzzolina was one of about 20 students who helped count money raised by the school. The hoy shared his idea to collect the funds with school staff shortly after the attacks on New York City and Washington, D.C. BELLWOOD-ANTIS SCHOOLS Residents opposing proposed upgrades One critic says million to improve district's athletic facilities and parking availability has nothing to do with enhancing education. Hv WALT FIIANK Staff Writer BELLWOOD JlellwoDd-Antis School District offi- cials face opposition to a million proposal to improve the district's athletic facilities and to create additional parking. Superintendent Rod Kuhns hosted two feedback ses- sions with government officials, business people and residents Tuesday to gain public input before school board members decide whether to proceed with the project. District residents also can comment on the project at p.m. Oct. 9 before the monthly school board ineeting- Meanwhile, opposition to the project is growing. Resident Clyde Flaugh has placed more than 300 letters at various locations expressing bis objections. A petition also is circulating in the communi- ty and is expected to bo pre- sented to board members. "I am definitely against Flaugh said. "Look at the economy in the area. Look what is going to happen to Tyrone [Westvaco plant clos- a number of jobs have been lost in Altoona." "My biggest concern is, what does this do for educa- tion? It docs almost nothing. If it were for education, I wouldn't complain." But extracurricular activities are an important part of the school's curriculum, Kuhns said. "Every school knows how important it is to have an athletic he said. "It is very important here at Bellwood-Antis." Leo Matuszewski, vice chairman of Antis Township supervisors and chairman of the Northern Blair County Regional Sewer Authority, said the time is not right to proceed with the project. "1 think that as a taxpayer and an elected official, it is a very worthwhile Matuszewski said. "But in light of the past few weeks, it is not the time to do it. "We need to see more stability before we undertake a project of that magnitude. The land acquisition is a good move." In August, board members reached sales agreements with Hank to purchase about 10 acres for and with CRH Catering Co. Inc. for about one acre of land for District residents can comment on Hie proposed project at p.m. Oct. 9 before the monthly board meeting in the high school cafeteria. Please see A4 'Slight murmurs of change' Census data show population up in Pennsylvania's rural areas BY JEANETTE KSEBS capitolwire.com HARRISBURG In the heartland of Pennsylvania, more children are living in two-parent families, minor- ity residents are growing and homcownership is increasing. At (he same time, rural workers earn far less than the national average and have access to fewer doc- tors; and teens are not as likely to go to college as their urban counterparts. Pennsylvania has the largest rural population of any state in the nation, although that may change when the final census numbers are released. .While much of the conversation generated by the cen- sus has focused on population changes in urban and suburban areas, the once-a-decade snapshot of rural Pennsylvania shows the landscape of many small towns also is changing. Nationally, Pennsylvania ranks 40th among the 50 states in percentage of population change. Please see A8 PENN STATE ALTOONA Students' off-campus behavior will reflect standing at college BY MARK LEBKHFINGEII StaffWriter The behavior of Penn State Altoona students who live off campus will affect their on-campus standing. "Most of our students are making wonderful deci- said David Shields, I'enn State Altoona's director of student affairs. For students who don't make wonderful decisions, Penn State .University has implemented a new code Spokeswoman: Niltany Pointe Apartmenls tries to help PAOE A4 of conduct covering off-campus misconduct. Previously, off-campus offenses such as underage drinking, public drunkenness, retail theft and crim- inal mischief wouldn't have registered on the uni- versity's judicial radar. Rut that changes with the new code of conduct. Please see A4 Subscription or home delivery questions: 946-7480 or (800) 287-4-180 Altnnna Mtrrnr THE GREAT COMBINATION Mostly sunny, Forecast, A2 Call us today...Make money today. Ask for THE GREAT COMBINATION of MIRROR CLASSIFIEDS and HOT-ADS Phone (814) 946-7422 or fax us at (814) 946-7547 fci 1 nT-iiiJfWkr j ll Xr.L_ i ALt J Business____ AS Movies___ A5 Obituaries A9 Opinion A7 NFL____________B2 Scoreboard BS Classifieds C3-10 Comics ____ D5 Community news D2 Puzzles ______ ___D4 Television D4 ;


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COLLEGE PLACE, Wash. (AP) — Steal a pickup truck in Oregon. Check.
Drive it across the border into Washington. Check.
Park it across the street from the College Place, Wash., police department. Oops.
College Place Police Chief Dennis Lepiane tells the Walla Walla Union-Bulletin it was only about a half hour after police received word that a pickup stolen in Umatilla County, Ore., might be headed for Washington when one of his officers saw a vehicle matching that description. It was parked across the street from City Hall, home of the police department.
Officers confirmed it was the right vehicle, then confronted an 18-year-old woman and a 15-year-old boy, who fled through an apartment complex. Both were arrested Thursday after a foot chase. The 18-year-old was taken to jail and the younger teen was placed in juvenile detention.
Information from: Walla Walla Union-Bulletin, http://www.union-bulletin.com


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Predators Edge Ducks, 2-1, In Game 7, Advance To Second RoundFor the fourth consecutive season, the Ducks blew a 3-2 series lead and lost a Game 7 at home.
Predators Force Franchise's First Game 7, Beating Ducks, 3-1Ryan Kesler scored a power-play goal for the Ducks, who now are 8-6 in Game 6s.
Ducks Defeat Predators In Game 5, Take 3-2 Series LeadThe Anaheim Ducks have defeated the Nashville Predators 5-2 on Saturday to take a 3-2 series lead.
Ducks Beat Predators, 4-1, To Tie Up SeriesRyan Getzlaf and Andrew Cogliano also scored as the road team stayed perfect in the best-of-seven series.
Ducks Bounce Back, Beat Predators 3-0 To Pull Within 2-1The Ducks have not lost three straight to open a postseason series since the 2006 Western Conference finals, and they didn't come close to dropping a third straight this year.
Smith, Rinne Lead Predators To 3-2 Win Over Ducks In Game 2Craig Smith had a goal and an assist, Pekka Rinne made 27 saves and the Nashville Predators confidently claimed their second straight road victory to open their first-round series, 3-2 over the Anaheim Ducks in Game 2 on Sunday night.
Forsberg Goes To Bank In Predators' 3-2 Win Over DucksFilip Forsberg got credit for the tiebreaking goal with 9:35 to play, and the Nashville Predators opened their first-round playoff series with a 3-2 victory over the Anaheim Ducks on Friday night.
Ducks Beat Capitals, Clinch Pacific Division TitleCorey Perry and Nick Ritchie scored, Frederik Andersen stopped all 24 shots he faced, and the Anaheim Ducks clinched the Pacific Division on the final day of the regular season by beating the Washington Capitals 2-0 on Sunday night.
Silfverberg Scores Twice As Ducks Beat Avalanche 5-3Jakob Silfverberg scored twice, Corey Perry had three assists and the playoff-bound Anaheim Ducks beat the Colorado Avalanche 5-3 on Saturday.
Kings Hold Off Rival Ducks, 2-1, Close In On Division TitleJonathan Quick made 19 saves for the Kings, who opened a two-point lead on the Ducks atop the Pacific Division by snapping their three-game losing streak in the Freeway Faceoff rivalry series.
Ducks Beat Stars 3-1 To Take Over 1st Place In Pacific Nate Thompson and Ryan Kesler each scored a short-handed goal, John Gibson made 25 saves and the Anaheim Ducks defeated the Dallas Stars 3-1 to return to the top of the Pacific Division on Sunday night.
Etem Burns Ducks In Canucks' Third-Period Rally For 3-2 VictoryJohn Gibson made 25 saves and Josh Manson scored in the opening minute for the injury-depleted Ducks, who had won three straight.


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OKC Thunder hires Florida assistant Mark Daigneault to be D-League head coach
Oklahoma City's newest professional team has its first head coach.
On Friday afternoon, Sam Presti and the Thunder hired Florida assistant Mark Daigneault to lead its D-League affiliate – the team formerly known as the Tulsa 66ers which is relocating to Oklahoma City this season and has yet to determine its name.
"Mark has placed a high value on development throughout his career and we feel that he is well aligned with the goals of our organization," Presti said in a press release.
Daignealt is replacing Darko Rajakovic, who was promoted to the Thunder's coaching staff this offseason.
At 29, Daigneault is extremely young for the profession. But he has plenty of experience. Daigneault attended the University of Connecticut and, as a freshman, began performing various tasks for the nationally renowned basketball program as a team manager. By his senior year, he had earned extra duties and, upon graduation, was hired as an assistant coach at Holy Cross.
Daigneault worked at Holy Cross for three seasons before moving to the University of Florida in 2010, where he has been the last four years working as an assistant to Billy Donovan. Daigneault has also assisted Donovan during his time coaching Team USA.
"His experience at Florida under Coach Donovan has provided him the platform to apply his intelligence and relationship skills to help strengthen the program," Presti said through the release. "We are excited about Mark joining the organization and continuing his professional growth."
"Mark has been a valuable member of our staff the past four seasons, and I'm very happy to see him get this opportunity with a great organization," Donovan said through the release. "We all wish him the best of luck and know he'll do a tremendous job."
The Thunder also recently hired Weber State assistant Phil Beckner to be part of Daigneault's staff. Beckner has been at Weber State for the seven years and developed a strong bond with Blazers star Damian Lillard when he played there.
"No one has been more dedicated, loyal or invested in our program than Phil has been for the last seven years," Weber State coach Randy Rahe said in a press release. "He has been a huge part of the success we've had. We are truly going to miss him."
But Daigneault is the head man. And this season, for the first time, his team will play its home games at the Cox Convention Center and hold practices at the Thunder's old facility in Edmond, linking the D-League team to its parent club more than ever before.
"I have had a great deal of respect for the Thunder organization throughout my career, and I'm excited to immerse myself in the culture there, and focus on the continued development of the program," Daigneault said in a release.


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'The Progressive Agenda to Combat Income Inequality.' …Wait, the acronym is PAtCII?
As in, 'patsy?' Talk about truth in advertising…Read More »
As in, 'patsy?' Talk about truth in advertising…Read More »
Teachers unions constantly demand more pay and more benefits. They say that it's "for the children". There is a valid connection between quality work and pay. Good teachers that can make better money elsewhere can do so without compromising the notion of "for the children", if that's even the slightest bit true. They are doing it for different children, that's all. There is nothing wrong | Read More »
or promote any other political agenda, I don't care who you are. We need to be praying for the families of those involved and getting to the bottom of the shooter's plot.
By Andrew Cray At the end of President Bush's last year in office, the unemployment rate was 7.2%. This was during the so-called worst recession since the Great Depression. For most of 2010 the unemployment rate was teetering near 10 percent with the government constant readjusting employment figures after each release. With last weeks disappointing job numbers and a minimal drop from 9.8 percent to | Read More »
According to the Progressives for America Facebook Page, Obama has clearly attained sainthood…no, that's not right. Obama has clearly attained God-status. Yeah, that's the ticket. He is the only president in history who has fixed everyone's problems without even trying. So, let's take a look at Obama's many failures and see if the Progressives have a clue, or if they are clearly intoxicated on the | Read More »
The President, not too surprisingly, said a lot last night in the State of the Union – and by that, I mean he used a lot of words. But what did the President actually propose? In short – it was the same thing we've been hearing from him since his campaign – the government creates jobs, the government needs to control healthcare, and the government | Read More »
As the tentacles of the neoliberal agenda extend further into the most precious areas of our free society, small farms comprise part of the last remaining opposition to tyranny. If our country is to stay a free republic, we cannot place the right for families to grow food under the thumb of a government bureaucrat. Earlier this year, H.R. 875, The Food Safety Modernization Act, | Read More »
When he won the election last November with 53% of the vote and an Electoral count of 365, Barack Obama seemed to have a mandate for his campaign mantra of, "hope and change." He entered the White House in January with an approval rating of 69%, the highest of any President since John F. Kennedy. Then he started working and in a short nine months | Read More »
This US citizen really wants to know the answer to the above question. I just happen to be in first hand position to be able to report on the effects of this ban, as well provide links for further reading below.)Here's my first impression of flourescent bulbs from personal experience. My wife and oldest daughter hate them. I hate them because I can't find the | Read More »
Barack Obama made sure to express many conservative views during his campaign. If he had not, he would not have been elected. He expressed the following ideas in big public forums at least once: That he favored offshore oil drilling, nuclear power, clean-coal technology, the 2nd amendment, FISA anti-terror legislation, keeping troops in Iraq until the job is done, keeping the military strong, tax cuts | Read More »
From the diaries by Jeff Let me be the first to congratulate Representative Paul Broun to be the first to fire a shot at the Obama Agenda! Damn proud to be a Georgian! Congressman Broun points to the "civilian security force" as examples of his agenda and how it follows Marxist principles. He even takes it a step farther to remind people of how Hitler | Read More »
I want common-sense conservatism. I want a Republican who understands that cutting federal spending and not raising taxes is key – like McCain. Earmarks as they are should be a thing of the past – if a Senator or Representative wants a project for his state or district, then it should be its own legislation, let it succeed or fail on its merits. I want | Read More »
Barack Obama has been elected as the next President of the United States. I wish him well, his road will not be easy. It is now our job to help him execute his duties for the betterment of the American People. Personally, I oppose many of his established positions, and I am suspect of what is to come. However, he will be my President and | Read More »
For some time now Republicans have assumed that the key to winning over the blue states is to sell them on conservative economic policies and to run away from a conservative social and ethical agenda. Clearly that plan isn't working. The success of Proposition 8 in massive Blue State California should finally indicate to Republicans that the key to success in Blue States is not | Read More »
For months I have been concerned with Obama's view of Government's role in citizens' lives. I have always thought of him as being Socialist, and that worries me. But what worries me more is "why" he has socialist views. I have waited to hear someone, anyone in the media mention this, but our world today is so politically correct, that the mere whisper of an | Read More »


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Those looking for an exciting escape away from the western world will find that holidays in Philippines represent a most alluring destination, showcasing alluring activities, cultural peculiarities and oasis-like views of tree-clad hills and stunning crystal clear waters, which offset gorgeous white sandy beaches and mountainous ranges. Set off of Vietnam and China's coast, the Philippines is a tantalising prospect for anyone wanting to experience a different side of life, a laid-back atmosphere accompanying an inspiring array of attractions and activities – the Philippines is a buzzing hub of captivating culture.
Eclectic festivals have been born out of the various influences and heritages that the Philippines have been subject to, ranging from Japanese to Bornean, you'll be able to try something new and unique as soon as you step off the plane on your Philippines holidays. As you arrive you'll be greeted by a welcoming and warm atmosphere, Filipinos being naturally upbeat and friendly people, never faltering in their proud traditions.
Amazingly, the Philippines are made up of over 7000 exotic islands, each one being slightly different to the last and suiting a whole manner of tastes, whether you're looking to unwind on the paradisiacal sun-soaked sands of Boracay, experience the mountains with a jeepney drive through North Luzon or get involved with water and extreme sports in Laguna – you'll be well served on your holidays in the Philippines. Although there's plenty to do, there's also plenty to see, and with incredible sights around every corner, this natural haven will tantalise and amaze with its varied landscapes and vivacious settings, the UNESCO World Heritage Site, Banaue Rice Terraces being a particular highlight of historical importance.
If you're hoping to immerse yourself in Philippine life, then there's no better city in which to do so than in the bustling capital of Manila. Nowhere else will you find a more intense version of the urban sprawl, but staying just a day in the chaos will reward you with rare finds, a humming vibe and the ultimate selection of sites. San Agustin Museum is a tranquil setting amid the swarm of locals who keep the city brimming with vitality on Philippines holidays, while Rizal Park is hailed as the largest urban park in Asia. You'll also find an assemblage of cathedrals and churches, but as the sun goes down you'll be treated to the vibrant and tropical nightlife found in East Asia; the Philippines, Malaysia and Thailand capturing the aura like no other.
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Desert planet by ScoobyltWatch
©2013-2016 Scoobylt
This looks so cool!
It kinda makes me think of Star Wars
It kinda makes me think of Star Wars
Dis rulez.
This is really neat. Never seen anything like it, so thumbs up for the uniqueness. Great concept. Now I'm just wondering what makes these people need to build their buildings up high on the cliffs? Must be something wandering around on the ground they are afraid of . . .
thanks. yes you a re absolutely right. I was thinking about dangerous animals living on the ground plus they build their houses in the "ravine" so they could avoid sand storms. Also the water collection could be more efficient higher. I'm no an expert on these thing but that's what I was thinking about at that time.
It's good to see you thinking over your designs and making them practical, rather than doing what I see a lot of artists do-draw something that looks cool but is completely implausible. Keep up the good work!
Great work!!
Fantastic artwork.
reminds me of Thousand Needles in World of Warcraft
great work
Thank you Deviantart for helping me discover such amazing stuff.
amazing! [inlove]
Wow this is like totally amazing! O.O


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June 10, 2014 The preseason football magazine's are showing up and Emporia State's trip to the NCAA Playoffs last year is being recognized. The Hornets are ranked #22 in the Sporting News NCAA Division II Preseason Top 25.
Emporia State returns nine starters from an offense that ranked 15th in the nation in scoring offense and 20th in total offense. Quarterback Brent Wilson was sixth in the nation in passing efficiency and ranked seventh in the nation touchdown passes. Austin Willis was 23rd in the nation in receiving yards per game at 101.2 yards per game. Five of his ten touchdown receptions went for over 50 yards. Emporia State is set to return four of their five starters on the offensive line, including honorable mention All-American Jarrett Statsny.
Defensively the Hornets have seven starters returning on defense. Emporia State led the MIAA in interceptions last season with 22 and have have the players responsible for half of them returning. Four of the top five tacklers from a year ago return led by linebacker Deshawn Dinwiddie.
Emporia State is one of three MIAA teams and eight teams from Super Region-3 in the top 25. The Hornets have gone 19-4 over the last two seasons and have not lost to an unranked team since a 22-16 loss to a then unranked Missouri Western on Oct. 15, 2011. Emporia State is 8-2 over their last ten games on Jones Field at Welch Stadium with both losses coming to teams ranked in the top 15 at the time.
The Hornets will have five home games during the 2014 season, starting with a Thursday night game against Missouri Southern on September 6 at 7:00 p.m. Central Oklahoma will be the opponent on Saturday, September 20 before the annual Football Traditions event. October will start with a visit from Lindenwood on October 4. Homecoming will take place on October 18 against Ft. Hays State. Senior Day will be against defending national champion Northwest Missouri on November 8. All of the Saturday games are set for a 2:00 p.m. kick-off.
Season tickets are on sale now through the Athletic Ticket Office in the Emporia State Memorial Union. Reserved season tickets are just $66, a $10 savings over purchasing the tickets on a game by game basis. Adult general admission season tickets are $41 with season tickets for children and people over 65 years old can be picked up for just $26.
Sporting News NCAA Division II Preseason Top 25
1. Northwest Missouri 15-0
2. Grand Valley State 12-3
3. CSU-Pueblo 11-1
4. Minn. State-Mankato 11-1
5. Lenoir-Rhyne 13-2
6. West Chester 13-2
7. North Alabama 10-3
8. Minn.-Duluth 11-2
9. West Texas A&M 11-3
10. Henderson State 11-1
11. Shepherd 11-1
12. Winston-Salem State 10-2
13. Ohio Dominican 10-1
14. Pittsburg State 10-2
15. St. Cloud State 12-2
16. Indianapolis 10-2
17. Bloomsburg 10-2
18. Carson-Newman 10-3
19. Delta State 7-3
20. American International 9-3
21. Tuskegee 8-3
22. Emporia State 9-2
23. Newberry 9-3
24. East Stroudsburg 7-4
25. Azusa Pacific 10-2


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Officials from North American Stainless and Acerinox, its parent company, delivered a clear message Thursday: The company is strong, healthy and well-positioned for the future. "We are a good customer and a good supplier," CEO Bernardo Velazquez said during the first Acerinox Investor and Analyst's Day held at the NAS plant in Ghent. Velazquez told more than 50 investor
The Trimble Banner The race for the Milton mayor's office has heated up, with Commissioner Steve Brierly throwing his hat into the ring with current Mayor Denny Jackson. Jackson was voted in as mayor by the commissioners after Donnie Oakley died while in office. Oakley died in September 2009 after a long battle with cancer. Jackson to
Downtown Bedford again will be the host of the Trimble County Apple Festival. This is the 20th year for the event, which is 9 a.m. to 6 p.m. Saturday and 11 a.m. to 5 p.m. Sunday, Sept. 11-12, on the Courthouse Square. The Jelly Bean Run, a motorcycle ride to raise money for several local charities, joins the festival this year. Registration is 9:30-11:30 a.m. Saturday. The t
The Trimble Banner Fiscal Court has released one-half of the 2010-11 funds it had committed to the Milton Volunteer Fire and Rescue Department. Trimble County Judge-Executive Randy Stevens said Monday that he hand-delivered the check for $15,000 to the department's treasurer last week. The county has budgeted $30,000 for each depart
Milton VFD hosts fish fry; updates website The Milton Volunteer Fire Department will host it's annual Labor Day Weekend Fish Fry from 10:30 a.m. to 8 p.m. Friday and Saturday, Sept. 3-4, at Station 1 on the hilltop. The menu features fish, hot dogs, baked beans, cole slaw, desserts and soft drinks. Funds raised will benefit the
The Trimble Banner Emergency responders from Milton, Bedford, Westside and La Grange fire departments responded to a house fire Wednesday morning, Aug. 25, on Richmond Road in Milton. The two-story, A-frame house is owned by Steve and Amy Renfro. No one was home at the time of the fire, and there were no injuries. The fire was first report
On Nov. 2, incumbents Sheriff Ben Smith and Constable Glenn Chatham will attempt to do the statistically impossible: Win back their seats in the general election as write-in candidates. Smith lost his seat in the May Democratic primary to Carrollton Police Officer Jamie Kinman by a vote of 1,191 to 837, while Chatham lost to former Carroll County Jailer David Miles by a vote of 385 to 289. Co
An article in the Sept. 1 edition of The News-Democrat on the proposal by Nam V.Do to move the Moore/Washburn cemetery on Gilgal Road is not connected with a nearby monastery. Nam confirmed Tuesday that his project at 1171 Gigal Road is not connected to the Bodhidharma Zen Monastery property, which is located at 1711 Gilgal Road. Luu Hong Ha, president of the Bodhidharma Zen Monastery, also co
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15079 South U.S. Highway 231
Midland City, AL 36350
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Spalletti was MISQUOTED as saying Park was the difference.What he really said was that Park's attitude showed the difference between the two teams! United had a never-say-die attitude.Don't get me wrong, I would love to see Park succeed. As I said already, I think he does have the skill but unfortunately never gets a chance to use it due to the fact that he can't hold the ball. No upper body strength.


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The Leonardo Inn Hotel Hamburg Airport (ex Leonardo Hotel Hamburg Airport) as the closest 3* hotel to the international airport of Hamburg (500 m) is located in a peaceful and quiet greenbelt area. The Hamburg hotel welcomes its guests with a completely modernized reception and lobby area in a beautiful contemporary design and guest sense the warm and welcoming atmosphere as soon as they arrive.
The Leonardo Inn Hotel Hamburg Airport offers 37 newly renovated rooms, free Wi-Fi and convinces thanks to sound-insulated windows with comfortable sleep. The renewed breakfast restaurant is the perfect place to start your exciting day and spoils you with a rich and tasteful breakfast.
Both business and leisure travellers benefit from the hotel's free airport shuttle service (available on request), which takes you to the Hamburg airport as well as to companies in the vicinity of the hotel.
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Park, Sleep & Fly
A worry-free touch down for your car, a relaxed take-off for you! You don't feel like standing at the check-in counter all tired out and wrinkled? Then you should book the Park, Sleep & Fly offer at the Leonardo Inn Hotel Hamburg Airport, which is in walking distance to the airport.
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Ivy Press specialises in producing books that take innovative approaches to the subjects that you want to read about. The books are written by experts in their fields and designed to the very highest standards. Ivy has three imprints: Ivy Press, Ivy Kids and Leaping Hare Press.
Ivy Press produces titles that will inspire you, books that will show you how to make things, books that will make your mouth water, books that will inform you, books that will make you laugh out loud, books that will expand your mind, and books that will stimulate you, however much you already know.
Ivy Kids produces beautiful books that will get kids making, creating, thinking, playing and dreaming. Covering all sorts of areas including cool, contemporary kids' crafts, awesome art activities, and fresh nonfiction topics, our books will get kids of all ages imagining, innovating, and above all, having fun!
Leaping Hare Press from mindfully walking along a noisy street or swapping seeds, our books embrace community spirit and ecological principles to share empowering steps (or hops) that make a real, positive difference – and deliver the feel-good factor too! Conscious living; meaningful, positive and practical life choices; heart and head; empowerment and engagement – we feel it is possible to create change by being that change (thank you Gandhi!) and that true wellbeing is not just about the individual but each other as well as the natural world.
Ivy is a member of the Quarto International Co-Editions Group. Quarto International Co-editions Group creates illustrated books that are licensed and printed for third party publishers for publication under their own imprints in over 30 languages around the world. The division includes seventeen separate businesses.


text:
For one day, Leicester market will be taken over by local community organisations, clubs, societies and voluntary groups. They will be promoting their organisations to the people of Leicester and Leicestershire. It will be a showcase of what goes on, in and around your neighbourhood. A real diversity of activities, cultures and interests, will be on display, together with street performers, musicians and the talents that make Leicester the OUR place to be.
Promote your organisation to:
Visit to see:
Thanks to all who promoted and attended in 2014.
We'll be bigger and better than before!


text:
Anyone from the esteemed Fifty Plus crowd riding in Tour de Palm Springs February 8th? I'm interested in riding my first century and looking for others that perhaps would be interested in joining me. I'm not a racer, but do enjoy long rides at a relaxed 15mph pace (flats and hills combined) and average about 80-100 miles/week.
Although there will be thousands of other riders I do believe it would be more fun to buddy up with one or more Fifty Plus folks, particularly if this is your first time as well. I live in Rancho Mirage so I'm very familiar with the route.
If interested let me know. Thanks!


text:
|Numéro de publication
|Type de publication
|Numéro de demande
|Date de publication
|22 juin 1999
|Date de dépôt
|9 janv. 1997
|Date de priorité
|9 janv. 1997
|État de paiement des frais
|Numéro de publication
|Steven C. Miller
|Cessionnaire d'origine
|Silicon Graphics, Inc.
|Exporter la citation
|BiBTeX, EndNote, RefMan
|Citations de brevets (6), Référencé par (99), Classifications (5), Événements juridiques (11)
|Liens externes: USPTO, Cession USPTO, Espacenet
The present invention pertains to a high bandwidth bridge mechanism which minimizes memory latencies for optimal performance.
In the past, computers were primarily applied to processing rather mundane, repetitive numerical and/or textual tasks involving number-crunching, spread sheeting, and word processing. These simple tasks merely entailed entering data from a keyboard, processing the data according to some computer program, and then displaying the resulting text or numbers on a computer monitor and perhaps later storing these results in a magnetic disk drive. However, today's computer systems are much more advanced, versatile, and sophisticated. Especially since the advent of multimedia applications and the Internet, computers are now commonly called upon to accept and process data from a wide variety of different formats ranging from audio to video and even realistic computer-generated three-dimensional graphic images. A partial list of applications involving these multimedia applications include the generation of special effects for movies, computer animation, real-time simulations, video teleconferencing, Internet-related applications, computer games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diagnostic imaging, etc.
The reason behind the proliferation of multimedia applications is due to the fact that much more information can be conveyed and readily comprehended with pictures and sounds rather than with text or numbers. Video, audio, and three-dimensional graphics render a computer system more user friendly, dynamic, and realistic. However, the added degree of complexity for the design of new generations of computer systems necessary for processing these multimedia applications is tremendous. The ability of handling digitized audio, video, and graphics requires that vast amounts of data be processed at extremely fast speeds. An incredible amount of data must be processed every second in order to produce smooth, fluid, and realistic full-motion displays on a computer screen. Additional speed and processing power is needed in order to provide the computer system with high-fidelity stereo, real-time, and interactive capabilities. Hence, speed is of the essence in designing modern, state-of-the-art computer systems.
One of the major bottlenecks in attaining faster, greater bandwidth computer systems pertains to the current bus architecture. The standard bus architecture found in most personal computers today is the Peripheral Component Interconnect (PCI) bus. A PCI bus is comprised of a set of wires that is used to electrically interconnect the various semiconductor chips and input/output devices of the computer system. Electric signals are conducted over the bus so that the various components can communicate with each other. This type of bus architecture offers a simple, efficient, and cost-effective method of transmitting data. For a time, it was also sufficient to handle the amount of data flowing between the various devices residing within the computer system. However, as the demand for increased amounts of data skyrocket, the PCI bus is rapidly becoming inadequate to handle the increase in data transmissions.
In light of the shortcomings inherent to the PCI bus architecture, designers have to find ways to improve the speed at which bits of data can be conveyed. For example, one such solution is to implement a switched router as described in the patent application entitled "Packet Switched Router Architecture For Providing Multiple Simultaneous Communications," Ser. No. 08/717580, filed on Sep. 23, 1996, and assigned to the assignees of the present invention. Rather than having a shared bus arrangement, a central "switchboard" arrangement is used to select and establish temporary links between multiple devices. Packets of data are then sent over the links. By selecting and establishing multiple links, the central switchboard allows multiple packets to be simultaneously sent to various destinations. This results in significantly greater bandwidth. There exist many different, improved bus architectures to meet the high bandwidth requirements.
However, a common problem with any new bus architecture is that various peripheral devices designed specifically for connection to a PCI bus are now rendered incompatible. Existing PCI devices (e.g., modems, disk drives, network controllers, printers, etc.) are designed specifically for a PCI type bus scheme. As such, they are incompatible with and cannot be connected to any non-PCI based bus design. Of course, the computer industry could establish a new, faster bus standard. However, this is a lengthy, complicated, highly contentious, and extremely expensive process. The entire computer industry would have to make a wholesale switch over to the new bus standard. And until a new bus standard is adopted, computer manufacturers are hobbled by the outdated PCI bus architecture.
An alternative option is to implement a PCI bus in conjunction with a new, faster bus architecture (e.g., a packet switched router architecture). A bridge device is interposed between the two different bus schemes and acts as an interface. This approach works fine, except that an extra delay is incurred when data is routed through the bridge. In particular, the main memory and CPU are coupled to the new bus structure on one side of the bridge to take advantage of its higher bandwidth, whereas the PCI devices are coupled to the PCI bus on the other side of the bridge. Consequently, read/write operations involving PCI devices require that data be routed to/from a PCI device via the PCI bus, through the bridge, to the new bus, and to/from the main memory. These memory accesses through the bridge result in added memory latencies. The extra memory latencies associated with the bridge may exceed the tolerances of some PCI devices. Thus, there is a need for some mechanism to hide or minimize this memory latency so that high speed PCI devices may be serviced. The present invention provides a novel, effective solution for minimizing latencies in a way that allows standard PCI devices to operate and yet keeps up with higher data rates. The present invention accomplishes this feat by implementing a combination of special write gathering/buffering, read prefetching/buffering, flushing, interrupt, and virtual device operations.
The present invention pertains to a mechanism in a computer system for minimizing memory latencies. An improved, high-speed packet switched router is used to route packets quickly and efficiently between the microprocessor and the main memory. The computer system also supports PCI devices by implementing a bridge which acts as an interface between a PCI bus and the packet switched router. In order to minimize the memory latencies for PCI based memory accesses through the bridge, a plurality of read and write buffers are implemented. Write gathering is used to gather multiple write transactions on the PCI bus into the write buffers and sent by the bridge as one cache line sized transfer to the routing mechanism. This write gathering technique is performed on a per device basis rather than on a bus basis. Consequently, the bridge may select particular devices to perform write gathering, while exempting other devices.
For PCI based read operations, data is pre-fetched from the main memory and stored in the read buffers. Thereby, PCI devices can access the read buffers multiple times to retrieve the requested data. Furthermore, there are three different types of read operations: precise reads, non-precise reads, and pre-fetched reads. Other features of the present invention include a virtual device, whereby one or more specific bits are used to differentiate between multiple streams running on a single PCI controller. Buffers are allocated according to these bits. Thereby, multiple streams will not interfere with each other while data integrity is preserved. Another aspect of the present invention pertains to a novel use of interrupts. Specific buffers may be flushed under the control of an interrupt signal. These and other features of the present invention are claimed and described in detail below.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
FIG. 1 shows an exemplary computer system upon which the present invention may be practiced.
FIG. 2 shows a detailed block diagram of the currently preferred design for the bridge.
FIG. 3 shows a flowchart describing the steps for performing read operations with pre-fetching.
FIG. 4 shows a flowchart describing the steps for performing write gathering.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the present invention. It should further be noted that there exists many different computer system configurations to which the present invention may be applied. One such exemplary computer system is shown in FIG. 1. Switched packet router 101 has a pair of direct point-to-point connection to memory controller 102. Memory controller 102 facilitates the transfer of data between one or more microprocessors 103 and main memory 104, which is comprised of DRAM SIMMs. A high-speed (e.g., 1 GBytes/sec) memory bus 105 is used to couple memory controller 102 with the actual main memory 104. To improve performance, the microprocessors 103 can temporarily cache data in the SRAMs 106. Other "widgets" or devices which may be connected to switched packet router 101 include one or more graphics subsystems 107-108. The graphics subsystems 107-108 perform functions such as scan conversion, texturing, anti-aliasing, etc. Furthermore, a video board 109 having compression/decompression capabilities can be connected to switched packet router 101. Additional devices may also be connected to the switched router 101. Each of the devices connected to switched router 101 has its own dedicated transceiver for transmitting and receiving digital data. Each device also has two links: one for transmit (source link) and one to receive (destination link). A link is defined as the physical connection from the switched router 101 to any of the connected devices. A link may be uni-directional or bi-directional.
The currently preferred bus architecture employs a high-speed, packet-switched protocol. A packet of data refers to a minimum unit of data transfer over one of the links. Packets can be one of several fixed sizes ranging from a double word (i.e., 8 bytes) to a full cache line (i.e., 128 bytes) plus a header. Packets are comprised of a 32-bit command word and some or all of the following: a 48-bit address, 16-bit remote map field, data field, and a data enable word. The command word contains destination and source identification numbers, packet type, transaction number, data size, arbitration and control bits. The packets can be grouped into two functional types: request packets and response packets. A request packet initiates an operation, whereas response packets are those which reply to a request packet. One or more packets of data are transmitted from one or more source devices over the established links through the switched router 101 to one or more destination devices. Afterwards, switched router 101 can be commanded to establish different links between different devices. Thereupon, packets of data may be transmitted from any of the interconnect devices. With this new routing architecture, bandwidth is increased to the desired degree merely by establishing additional links. The switched router is described in detail in the patent application entitled "Packet Switched Router Architecture For Providing Multiple Simultaneous Communications," Ser. No. 08/717580, filed on Sep. 23, 1996, and assigned to the assignees of the present invention.
A bridge device 110 may also be connected to switched router 101. The bridge 110 acts as an interface so that various off-the-shelf PCI devices (e.g., printers, monitors, modems, disk drives, etc.) may be coupled to the computer system via standard SCSI 111, IOC 112 and audio 113 ports. A second bridge 114 may be added to provide expansion PCI slots 115-117. Ports 118 and 119 are used to provide future growth and upgradeability for the computer system.
FIG. 2 shows a detailed block diagram of the currently preferred design for the bridge. The bridge is implemented as an ASIC chip for providing communications with the system through an 8-bit interconnect link to the packet switched router and a standard PCI bus.
The PCI Local Bus 201 is a 32-bit or 64-bit bus with multiplexed address and data lines. The synchronous bus can operate at a speed up to 33 MHz in burst mode which provides a very high host/memory to peripheral transfer rate. The bus is processor independent and devices are configurable by the host. PCI devices can act as a bus master to transfer data to and from the host or they can access other local PCI devices or devices on another side of the packet switched router. Supporting PCI Bus allows the user to have a large number of third party high performance, low cost peripheral devices to choose from to provide most functionalities and best I/O throughput. GIO Bus is very similar to PCI Bus. They both have multiplexed address/data buses, device dedicated bus request/grant lines, and both support burst transfer mode. The Bridge supports a 64-bit pipelined GIO Bus. The Bridge functions as both master 202 and slave 203 to the GIO Bus.
The request dispatcher 204 decodes and distributes all incoming requests to the different functional units. It is also responsible for returning the response from those requests, providing any address translation, and error checking. Packet switched router to PCI/GIO bus translation mechanism consists of generating a PCI/GIO bus address from the packet switched router address. This translation occurs using fixed regions defined in device slot space and auxiliary I/O space. The request generator 205 is responsible for request packet generation, address translation, and response buffer management. The request generator translation mechanism uses two mapping techniques, a direct map scheme for a portion of system memory and a page mapped scheme for the rest. The direct map scheme uses internal registers and predefined areas to perform mapping. The page map scheme uses a Page Mapping Unit (PMU) to perform address translation on a page basis. To speed up the read access performed by the PCI/GIO devices to data residing across the packet switched router Bus, the Prefetcher circuit 206 decides whether to prefetch more data following current address. This enables faster read response time when sequential reads are performed by the PCI/GIO I/O devices.
Data Buffers 207 provide speed and data buffering between packet switched router Interconnect and PCI/GIO circuit. It off loads read/write packets from high speed, non-stallable Switched packet router Bus to the lower performance, two-way handshaking PCI/GIO buses 201. When the command is from PCI/GIO to Switched packet router, address and data are first gathered at Data Buffers 207 before they are read by the PCI/GIO PMU. The SSRAM/FLASH controller 208 supports local SSRAM used by the PMU for storage of address translation entries and FLASH for boot support. The internal registers 209 in the Bridge reside in a Switched packet router address region known as "widget space". Every widget has a 16 MByte widget space located in system address space based on widget id number. The Bridge ASIC can occupy any widget id number from 0×2 through 0×f. All registers in the Bridge are 32-bits or less in size and are aligned to a double-word boundary. The registers are located on data bits 31:0 of the double word. The registers can be accessed by Switched packet router double-word packet type with 4 data enables only (32-bit load/store only). Access by other packet type results in an address error exception. There are two device registers 210 for each of the eight devices on the PCI/GIO bus, one register for read response buffer allocation and the other for general control and mapping.
The Bridge ASIC also contains special buffering for two different data paths. The one path is used for operations generated from a widget as a master (pio mode). An example of those operations are such things as load/store operations from the processor. The other path is for operations initiated by a bus master from the PCI/GIO bus (dma mode). An example of these operation would be a SCSI DMA. The buffering in the Bridge ASIC allows peak performance on both the PCI/GIO buses and the Switched packet router Interconnect. The next few sections define the operational flushing policies, programming and use of the buffers in the ASIC. The widget master buffers consist of a request fifo (in the request dispatcher 204), a request ping-pong (in the PCI master 211), and a response ping-pong buffer (in the request dispatcher 204). These buffers allow smooth flow of request operations through the bridge. The request fifo holds initial requests until the request dispatcher 204 can route the request to the proper section of the Bridge ASIC. This fifo can hold three cache line or quarter cache line write requests or up to fifteen, read or double word write requests. The Bridge automatically handles the packing and proper credit management of smaller packets. If the operation is to the PCI/GIO bus, the ping-pong buffer provides an additional two operation buffer. If the operation requires a response, the PCI/GIO bus and the SSRAM/FLASH share the ping-pong response buffer.
There are two types of PCI master buffers used in the Bridge ASIC, read response buffers and write buffers. Read response buffers are used to hold the data returned from a read request made by the PCI master or the prefetcher. Write buffers are used to hold the data from a PCI master write operation until it can be sent on the Switched packet router interconnect.
The bridge ASIC contains sixteen read response buffers, split into two groups: the even device group and the odd device group. The read response buffers are hard allocated to a PCI master device by using the even/odd device response buffer registers. The PCI device number is based on which physical bus request/grant pair is used. The Bridge ASIC PCI bus supports eight bus request/grant pairs. To allocate a buffer to a given device, the buffer must have its enable bit and the two most significant bits of the device number set. The LSB of the device number is implied by the use of even or odd read response register. The reason for the even/odd buffer is to reduce the compare logic required. This does limit the maximum number of buffers which can be used with any single bus request/grant pair to eight. In addition, each device can have two virtual request/grant pairs within a single bus request/grant pair. The Bridge ASIC provides three kinds of PCI to Switched packet router request mapping which effect read response buffer operations: precise, non-precise, and prefetched. All read operations require at least one buffer to be allocated to that bus request/grant pair. Those devices which can use multiple buffers, a buffer must be ready to be assigned to the current transaction. If all the buffers for a given device are in use, then the transaction is retried and no information is stored. Since all PCI operations which are retried with no data transfer will be repeated there is no data loss problems.
A precise PCI read operation causes the Bridge ASIC to issue a retry on the PCI bus and generate a double word Switched packet router operation requesting only those bytes selected by the PCI byte enables. The PCI device continues to request the bus and perform the read operation. The Bridge ASIC will continue to issue retries until the response arrives and then the next read operation will provide the requested data. The Bridge ASIC compares exact address and byte enables in this mode. After the read is complete, the buffer is ready for another transaction.
FIG. 3 shows a flowchart describing the steps for performing read operations with pre-fetching. Initially, the computer system performs its routine operations until a read transaction generated from a PCI device is detected, steps 301-302. Thereupon, a determination is made as to whether this particular read request is the first one issued by the PCI device, step 303. If it is not the first read request, then the requested data is retrieved from the read buffers, step 310. Otherwise, for a first read request, a request is made to retrieve an entire cache line from the memory, step 304. A determination is made as to whether the prefetch attribute was set for this particular PCI device, step 305. If the pre-fetch attribute was not selected, the data is retrieved from the read buffers, step 310. Otherwise, sequential cache lines from the memory are loaded into the read buffers, step 306. This process continues until either the read buffers become full (step 308), a page boundary is encountered (step 309), or the buffers are caused to be flushed (step 309). Next, the buffers are read, step 310. Subsequent read transactions can access the same buffers because data had been subsequently prefetched. Subsequent buffer accesses can continue until either the last word has been retrieved (step 311), the buffers are caused to be flushed (step 312), or the end of the page is encountered (step 313). Thereupon, the read buffers can be reused, step 314.
Read response buffers filled by a precise operation are flushed based on the following rules: 1) When a write from the same master and an address match occurs; 2) When an interrupt occurs from a interrupt pin assigned to the device associated with the buffer; 3) Single access to the buffer (normal completion); 4) PCI master write access to 0×3fff-- 0000 through 0×3fff-- ffff; and 5) PIO flush.
A non-precise PCI read operation behaves like the precise transaction except that the Bridge ASIC generates a Switched packet router cache line address bits are used for the compare. Accessing the buffer at any address within the cache line provides a response and will continue (bursting) until either the end of the cache line is reached or the PCI cycle is terminated by the master. At this point, the buffer is ready for reuse. Read response buffers filled by a non-precise operation are flushed based on the same rules given above for precise operations.
A prefetched PCI read operation starts similar to the previous operation. First, a retry is issued on the PCI bus; a Switched packet router cache line request is issued, and the prefetcher 206 is enabled for this transaction. The prefetcher 206 stores the next cache line address and looks for addition free buffers currently assigned to the requesting device. If additional assigned buffers are free, then the prefetcher 206 will launch incremental cache line read requests until all the buffers are in use. The prefetcher 206 can be enabled to stop at either a 4K or 16K page boundary. The prefetcher 206 will continue to search for free buffers and posting read request until either a page crossing or a flush condition is reached. The prefetcher 206 can only increment linearly on physical addresses. Prefetched reads also effect when a buffer is available for the next transaction. Both the precise and non-precise operation only allow a single bus tenure to access the buffer then the buffer free for use in the next transaction. The prefetched buffer allows multiple bus tenures to access the buffer until the last (most significant word) single/double word is accessed (32-bit/64-bit bus). With the last access, the buffer is ready for another transaction. In the currently preferred embodiment, the Bridge is optimized for a burst length of 128 byte boundary. The cache line size on this machine is 128 bytes. By doing transfers that are exactly one cache line the cache coherency operations are much more efficient. The memory system is also optimized for blocks of this size and alignment. Other size transfers will work, but they will not be as efficient.
Read response buffers filled by a prefetch operation are flushed based on the following rules: 1) When any non-sequential read is performed by the PCI master (breaking stream); 2) When a write from the same master occurs; 3) When an interrupt occurs from a interrupt pin assigned to the device associated with the buffer; 4) Access to the last word of data in the buffer (normal completion); 5) PCI master write access to 0×3fff-- 0000 through O×3fff-- ffff; and 6) PIO flush.
Now, the PIO(Processor) Flush operation is discussed. The read response buffers can be cleared with a PIO by setting the corresponding enable bit in the even/odd read response buffer registers 212 to zero, then checking the read response buffer status register. If the RRB-- INUSE bit is set then, one must wait until the RRB-- VALID bit is set and the RRB-- INUSE bit is clear. A PIO to the corresponding RRB-- CLEAR bit clears the buffer. If both the RRB-- VALID and RRB-- INUSE are dear then the buffer is cleared. This is also the mechanism used to reassign buffers "on the fly" to other devices. When a buffer is clear and disabled, it can be reassigned to another device.
From the above rules of operation for the read response buffers, a single PCI master device could have either a single prefetch stream, or multiple random precise/non-precise requests equaling the number of buffers allocated. This functions well for some devices, but others (e.g., scsi controllers) may have a large data stream which uses the prefetch feature and an occasional dma descriptor read to an unrelated address. Using the above rules, the data stream is flushed on every descriptor read. This will negativity impact performance. It is for cases like these, that the virtual request feature solves. To use this feature, the PCI master must be able to generate 64-bit PCI addresses. The Bridge uses PCI address bit 57 to differentiate between the virtual read streams. The even/odd read response buffer registers have a bit for each buffer to select virtual buffer. This bit is compared against address bit 57 in selecting or clearing the buffers.
Unlike the read response buffers, the seven write buffers residing within the PCI slave datapath 213, are dynamically allocated by the PCI slave logic. This allows the maximum performance for the minimum amount of buffer ram. The Bridge ASIC supports a dual ring arbitration scheme, allowing PCI devices to be either real-time or not. Any non-real time device must leave two write buffers free at all times. If a write occurs and only two buffers are free, then the write is retried until more buffers are free. Any real time device cannot use more than five buffers at a time, and must leave at least one free if it already has write buffers in use.
These rules apply to all cache line aligned transfers. Non-aligned transfers must be broken up into quarter cache transfers (on the Switched packet router interconnect) or write gathered. PCI devices which are not able to burst an entire 128 byte cache might use write gathering mode on the write buffers. By setting the write gather bits in the device (x) registers, when a write occurs, the data is gathered into larger units to be sent on Switched packet router. A PCI device can only have a single write gather buffer in use at one time.
FIG. 4 shows a flowchart describing the steps for performing write gathering. Initially, the computer system performs its routine operations until a write transaction generated from a PCI device is detected, steps 402. Thereupon, a determination is made as to whether that particular PCI device has been designated for write gathering, step 403. If it has not been selected to be write gathered, the data is written to the main memory via the bridge, step 406. Otherwise, the data to be written is stored in the write buffers, step 404. At that point, step 405 determines whether a cache line has been filled. If an entire cache line is full of data, a single write transaction to the main memory from the bridge is executed, step 407. Normal operations continue, step 401.
Flushing of the write buffers is done when the following occurs: 1) A read from the device corresponding to the gather buffer; 2) A non-contiguous write; 3) An interrupt from the interrupt pins associated with the device; 4) A PIO access to the write request buffer flush register; or 5) PCI master write access to 0×3fff-- 0000 through 0×3fff-- ffff. In the currently preferred embodiment, the interrupt controller 214 can also influence the buffer flush management for a device. When a device finishes transferring data to or from the Bridge, there may be partially filled data in the write gathering buffer or unused prefetched data in the read buffer. The device can initiate an interrupt or do a memory write to specified address to flush the buffer and invalidate all the data in those buffers which are assigned to the device. If the device uses an interrupt pin to flush/invalidate data buffers, the interrupt packet will be sent after the data. The interrupt pins must be assigned to each device using the interrupt device register. Multiple pins can be assigned to a single device.
The memory latency issue is now described in further detail. As described above, the Bridge ASIC connects the PCI bus to the system bus. The system bus then connects to main memory. This means that the latency to main memory is longer than in a computer whereby the PCI bus is directly connects to main memory. By not connecting the PCI bus directly to the main memory, a computer can have multiple PCI buses, and the total I/O bandwidth of the system is not limited to the bandwidth of a single PCI bus.
To mitigate this longer memory latency, the Bridge can prefetch data from memory. When a PCI device first issues a read the Bridge will retry the read since it does not have any data for the read. Then the Bridge will send a request for a cache line, 128 bytes, to the destination. If the prefetch attribute is set then the Bridge will continue sending read requests for sequential cache lines. If the device is accessing data sequentially, the Bridge will have the data the device is requesting for the next transaction. The Bridge will stop sending requests for more cache lines when it runs out of read buffers assigned to that device, gets to a page boundary, or a condition has occurred that causes the read buffers to be flushed. Conditions that cause the prefetch buffers for a device to be flushed are: a non-sequential read is issued, the device issues a write, software invalidates the prefetch buffers, or the device generates an interrupt. Once the PCI device has read the last word in a data buffer the buffer is reused and the Bridge will send out another read request unless the read buffers have been flushed for some reason or the prefetcher has reached the end of the page.
The Bridge also supports write gathering to make main memory writes more efficient. The write gatherer holds 128 bytes. Each coherent memory write needs to send an invalidate or intervention to the processor. Writes that are less than a quarter cache line boundary will require a read-modify-write sequence to write the data into main memory. For these reasons, the write gatherer tries to convert partial cache line writes into cache line writes to main memory so that they can be handled much more efficiently. The write buffer is flushed when the PCI device issues a read, writes to a non-contiguous address, generates an interrupt, or is flushed by software.
For the first access to a region in main memory, the latency will be very long. If prefetching is used however, sequential accesses should be much faster since the data should be in the Bridge most of the time before the PCI device requests the data. The latency for the first access to a region depends on many factors, such as the priority of the device on the PCI bus, the number of PCI cards installed in the system at the same PCI priority; and the number and priority of devices connected to the system bus.
To maximize performance and efficiency of the whole computer, PCI devices should transfer 128 byte blocks that are aligned to a 128 byte boundary. Because the Bridge is optimized for this size transfer, it disconnects when it is the target of a read and gets to a 128 byte boundary even if it has prefetched the next cache line. This also limits a device's time on the bus to approximately 1 us (i.e., the time to transfer one cache line for a 32 bit device assuming neither device stalls during the transfer).
During write transactions where the Bridge is the target, the Bridge disconnects at 128 byte boundaries or whenever a PCI device writes only part of a 32 byte aligned block. For example if a PCI device wants to write 67 bytes starting at address 32 with no data being transferred at bytes starting at address 32 with no data being transferred at byte address 68 (using the byte enables), the Bridge accepts the first 32 bytes from byte address 32 to 63 and it will accept the next 31 bytes from address 64 to 95, but then it will disconnect because the second 32 bytes were not contiguous. Only 63 bytes will be transferred even though the master wanted to transfer 67 bytes because the second block of 32 bytes was not contiguous.
It is therefore important that whenever possible a PCI device transfer 128 byte blocks that are aligned to 128 byte boundaries. This is very important when designing the buffering on a PCI device. The loss in efficiency will not only be in the memory system but also in arbitration, getting on and off the bus, and the address cycle to data overhead. Also, because the PCI arbiter is a round robin arbiter, a device in a busy system will have to wait its turn if a transfer takes multiple transactions.
It is also important to understand some of the address attributes that are used by the Bridge. These attributes are used to make transfers more efficient. If the prefetch attribute is set, then the Bridge holds on to data it reads from main memory until the PCI device that requested the data reads a byte or more of the last double word of the cache line, 128 bytes, or it is flushed for some reason. This attribute bit also causes the Bridge to read sequential data before the PCI device requests it. Prefetching is required to achieve any reasonable bandwidth on the PCI bus.
There are two basic types of reads: prefetched and not prefetched. The reads that are not prefetched are used when a small amount of data from sequential addresses is to be read. Prefetched reads are used when a lot of sequential data will be accessed. Read prefetching is required for reads from a PCI device to main memory in order to maintain reasonable read memory bandwidth. When a PCI device tries to read data from main memory which has not already been read by the Bridge, it will terminate the read with a retry. The Bridge will then issue one or more cache line reads to main memory if the prefetch attribute is set. The number of cache lines it will request depends on the number of read buffers software has assigned to that PCI device. There are 16 read buffers that have to be shared by all of the PCI devices. A PCI device can have a maximum of 8 read buffers assigned to it. Some time after the device was issued a retry, it will request the PCI bus again and try the read request again. The Bridge will continue issuing retries until it has the data from memory. Once it has the data, it will transfer the data until the initiator terminates the transfer or when a cache line boundary is crossed, the Bridge will issue a disconnect. The Bridge always disconnects on reads that cross cache line boundaries even if it has prefetched the next cache line of data.
The Bridge will continue issuing read requests to main memory reusing the buffers that the device has read to the end of, until it reaches a page boundary, or an event occurs that causes all of the buffers for that PCI device to be flushed. The page boundary can be programmed to be 4 K or 16 K bytes long.
For write gathering, the Bridge contains seven write buffers that are dynamically allocated. The write gatherer's function is to combine multiple write transactions on the PCI bus into one cache line sized transfer on the system bus. Four of the buffers can be used as write gatherers. Write gathering improves the system efficiency because it reduces the number of cache coherency operations to the processor since one is done for each system bus transaction if the coherency attribute is set and the memory system is optimized for cache line size operations. A PCI device can enable the write gatherer by setting the write gathering by setting the write gathering attribute in the device register. This enables write gathering for all writes that the device does using direct mapped space. A PCI device can only have one write gathering operation in progress at a time. When a PCI device writes to the end of a cache line, the buffer will always be written to memory.
A write buffer gets written to main memory when: 1) The PCI device that owns the write buffer issues a read; 2) The write data is not contiguous in address or the byte enables are not all asserted for each data transfer; 3) An interrupt occurs for the PCI device that owns the write buffer; 4) The processor accesses the write request buffer flush register; or 5) The PCI device writes anything to the region 0×3fff 0000 to 0×3fff ffff. The data on the write to this region is dropped by the Bridge.
Another attribute, known as the virtual request attribute, is for PCI devices that wish to have two outstanding prefetched read streams at the same time. Because of the rules of when the prefetch buffers get flushed, two outstanding streams would just thrash each other without the virtual request attribute. This attribute decouples the two streams so that requests for one stream do not affect the prefetch buffers for the other stream. Hence, the virtual request attribute is for PCI devices that need to have two concurrent prefetched read streams. Because of the rules of when the prefetch buffers get flushed, two outstanding streams would just thrash each other without the virtual request attribute. This attribute decouples the two streams so that requests for one stream do not affect the prefetch buffers for the other stream.
Hence, the virtual request attribute is for PCI devices that need to have two concurrent prefetched read streams. Because of the rules of when the prefetch buffers get flushed, two outstanding streams would just thrash each other. Hence, in light of this shortcoming, the virtual request attribute was implemented. This attribute effectively decouples the two streams so that requests for one stream do not affect the prefetch buffers for the other stream.
The virtual attribute can also support having one read stream and one write stream. Normally, a write will cause all of the prefetch read buffers for that PCI device to be invalidated, but if the read stream and the write stream have different virtual request attributes then the write will not invalidate any of the read buffers with the opposite virtual request attribute unless the cache line address of the read and write are the same. When the write occurs all of the read buffers with the same virtual request attribute will be invalidated. When a PCI device issues a write, the address is compared to the addresses of all of the read buffers owned by that PCI device, including ones with the opposite virtual request attribute and if there are any matches that read buffer is invalidated.
The virtual request attribute is only available for PCI devices that issue dual address cycles. This attribute is not present in the page map or in direct mapped space. This feature can be very useful for any PCI device that requires two unrelated concurrent transfers. When read buffers are assigned to a device the virtual request attribute is also assigned to the buffer.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
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