text:
- Detail Images
For a feature-rich professional-grade navigation tool, look no further than the Kasper & Richter Meridian Pro Luminous Compass. A built-in clinometer measures slope and elevation while the bubble level and 1/4-inch thread allows you to fix the compass to a tripod for exceptionally precise readings. Plus, the luminous compass card can be quickly charged by a light source, allowing night-time readings for up to 20 minutes.
- Aluminum body is lightweight and durable
- Luminous compass card can be quickly charged with a flashlight, which allows you take night-time readings for up to 20 minutes
- Fluid-filled dampening reduces wobble for improved readability
- Thermo-elastic capsule provides durable bubble-free performance
- Integrated clinometer allows you to measure slope and elevation
- Bubble level helps ensure an accurate read
- 1/4-inch thread allows you to attach the compass to a tripod
- Flip-up sighting prism allows you to take bearings on distant objects and landmarks
- Cordura carry case with belt loop keeps the compass safely stowed and close at hand
- Luminescent bezel and north points allow you to take readings in low light conditions
- Inch and millimeter scales aid in map reading
- Metal bezel has a 0-360 azimuth scale with 5-degree resolution
- Internal compass card has 0-360 azimuth scale and a reciprocal scale with 1-degree resolution
- Reviews
What do you think about this product?
Have questions about this product?
An Excellent Compass
This is a great compass that is tough, accurate and reliable. The case is tough and the replaceable capsule has never developed a bubble. I've gone from just above sea level to about 2300 meters and back, from a warm house to -25*C for a few days at a time, bumping dropping and just hard use and never developed a bubble. I have had this compass for a few years now and use it for hunting, hiking, rough surveying property and mining claims, and it's accuracy is excellent. For hunting in the mountains the inclinometer helps get angles for shooting up/down hills for shot ranging. If you are just going to hike trails, it's overkill, but for anything like off map hiking mountaineering or more it is a high end option.


text:
Pokemon Cobalt
View Single Post
July 1st, 2011 (4:02 AM).
Is Waldo
Join Date: Jun 2011
Location: among the elekids
Gender: Male
Nature: Adamant
Posts: 181
Originally Posted by
Rai Rai
That map needs serious work done to it, it doesn't look appealing to people who see it. You need to add more trees make the map bigger give a better path with alternate options for the player. There also appears to be errors with the rocks, which on that subject you might want to try place them a bit better, it seems odd just seeing them in a such a linear way. Hopefully that will help you.
Thank you for this advice Rai Rai. This was only to prove I can Map on a grid and such and such. This is not going into any game. This being said, the map was only a sketch at that. It took approximately an hour. Real good maps can take much longer than that. The tiles I used also didn't supply all the supplies needed. But I did also make an edited version of it, though all the things I said above still apply (except that it took about 30 mins more). But I will probably not change it beyond this point.
Attached Images
(864.6 KB, 9 views)
(Save to Dropbox)
View Public Profile
Send a private message to Beegu
Find all posts by Beegu
Find threads started by Beegu

subset: commoncrawl


text:
On this day in history...14th July
A look back at this day in history, and what was happening with Pompey courtesy of our sister site PompeyRama.
No games on this day previously...
Another feature, again courtesy of our sister site PompeyRama, sees us look at those Pompey personalities - past or present - who have a birthday on this day...
14/7/1972: Andy Awford
Win FREE pizza with Vital Football!
Select your team and get 50% off if they score twice.


text:
State Street woman denies growing potSeptember 19,2013By Josh O'Gorman
Staff Writer
A Rutland woman denied charges she was growing marijuana in her State Street home.
Tammy Duquette, 50, pleaded innocent in Rutland criminal court Monday to a felony charge of cultivating three or more pot plants, which carries a maximum penalty of three years in prison and a $10,000 fine.
According to an affidavit filed with the court, in late July, state police received a tip of a grow operation at 182 State St. When police arrived, they met Duquette outside, who reportedly told police she had three pot plants inside, records state.
Affidavits state Duquette allowed police to search her residence, and the search revealed a grow operation – including lights, timers, plant food and fertilizer – with 17 plants.
"While inside this room Duquette advised me that she was responsible for growing the marijuana plants and that she was not very good at it," Sate Police Detective Cpl. David LaChance wrote in his affidavit. "She advised she had been growing the marijuana plants for her own used (sic) and was not selling any of the marijuana."MORE IN This Just InBENNINGTON For the first time, all the choral students of the Southwest Vermont Supervisory... Full StoryKILLINGTON A Rutland woman was injured Sunday after she crashed her car while trying to avoid... Full StoryPOULTNEY Six times a member from the American Legion Auxiliary laid a wreath. Full Story
- Most Popular
- Most Emailed


text:
Appointments & Offices
Check insurance plans, locations and make an appointment
Is Dr. Isaacson Jr. accepting new patients?
If you are a new patient, please check with Dr. Isaacson Jr. before scheduling an appointment.
What insurance does he accept?*
- Capital District Physician's Health Plan (CDPHP)
- EmblemHealth
- Fidelis Care
- Government Employees Health Association (GEHA)
- Medicaid
- POMCO Group
- UnitedHealthCare


text:
Sunday Worship
8:00 AM Holy Eucharist, Rite I (Traditional)
9:00 AM Hospitality in St. John's Commons
9:00-11:45 AM Nursery Care Available
9:15 AM Godly Play Children's Formation &
Adult Education
9:15 AM Choir Rehearsal
10:15 AM Sung Holy Eucharist, Rite II
9:00-11:45 AM Nursery Care Available
11:30 AM Hospitality in St. John's Commons
Beginning Sunday, June 5th through Sunday, August 28th
9:00 AM - Holy Eucharist, Rite II
*Nursery Care Available
Weekday Worship & Prayer
Monday, Wednesday, & Friday Evening Prayer at 5:30 PM
Tuesday Healing Prayer & Holy Eucharist at Noon
Thursday Holy Eucharist at Noon
The Chapel of the Resurrection is open for prayer
Monday-Friday from 8:30 AM - 4:00 PM.
Weekday services are held in the Chapel of the Resurrection.
Please enter through the Memorial Garden on Ferry Street.
Click HERE for the Weekly Prayers & Announcements
Worship Ministry Schedule
St. John's Office
The St. John's Office is open
Monday-Friday from 8:30 AM - 4:00 PM
Click HERE for the complete St. John's Calendar
The St. John's/LUM Food Pantry
Monday 9:00 AM-11:30 AM
Tuesday 9:00 AM-11:30 AM
Wednesday CLOSED
Thursday 9:00 AM-11:30 AM
Friday 9:00 AM-11:30 AM
Saturday 1:00 PM-3:00 PM with the Veggie Drop
during Summer hours
The St. John's\LUM Food Pantry is located at the corner of Ferry and 6th Streets. Look for the green awning.


text:
No products in shopping cart.
Go and choose one!
|bookmark |
|Login register | 繁 | 简 | En | help | contact us | delivery country : USA
(9 reviews)
|product name: SKIN79 HOTPINK COLLECTION
Sun Protect Beblesh Pact SPF30 PA++ (15g)
|item no.: 104062102001
|brand: SKIN79
|ative from: 2009-10-09 00:00:00
|product size: 15 g
|category: Compact Foundation
Skin 79 Hotpink Collection Sun Protect Beblesh Pact SPF30 PA++ features the following benefits:
Suggested skin care routine: cleanser>toner>lotion>Sun Protect Beblesh Pact
Apply a proper amount. Blend it evenly to entire face with the puff provided. For areas with enlarged pores or blemish, tip the cream on troubled points for better concealing effect. Afterwards, you may apply loose powder or foundation for a long-lasting nude makeup look.


text:
Join or Sign In
All Wrapped Up in ...
Cake Decorating
D-3 Baby Shower
LoveBug Is One!
70th Birthday Cupcakes
It's A Girl
Lavender Butterflies
Sponge Bob's House
Zebra and Pink
She's Having Twins!
Purple Butterfly
It's A Boy!
Baby Blocks
Orchids and Bling
Stacked Birthday Cake
Cars Birthday Cake
Purse Cake
Masquerade Cake
Christmas Calla Lilies
Modern Roses
Strawberries & Cream
Super Mario Brothers
Birthday Cake
Buttercream and Roses
Champagne & Chocolate ...
Cascading Callas
Teal Magnolia Wedding ...
Angry Birds
Cupcake Tower Topper
Wedding Cupcake Tower ...
Wedding Cake
Take Craftsy with you!
Craftsy Apps for iOS and Android. Read more »


text:
Academics . Ceramics . Courses
Art + Design History II: 18th Century-1945
Course No. ACD 104 Credits: 3.0
Faculty Andrew Dolan | David Hart | Gary D. Sampson | Lane Cooper | Michael Weil | Rita Goodman
Prerequisite(s) Art + Design History I: Ancient-18th Century
Covers major movements and ideas in European and American art and design history to the mid-20th century. Students are provided with a firm grounding in the debates and theories of modernity and modernism in art. Prerequisite ACD 103. Offered spring.
Get started here.
Amy Sinbondit
Technical Specialist/Adjunct Faculty
Amy Krusinski Sinbondit is a ceramic artist currently working at the Cleveland Institute of Art as the Technic...more
While at CIA, you'll learn from the masters through our rigorous, world-class curriculum and connect with working professionals to begin your career.


text:
THANK YOU!!! Thank you to everyone who supported CCMGA by stopping by and shopping at the 2015 Bulb & Perennial Mart. Proceeds from the sale benefit community outreach programs, as well as horticultural and water conservation education throughout Collin County.
Watch this page for details about the Next Annual ccmga Bulb & Perennial Mart in October 2016.
CCMGA will be selling some of the beautiful, yet hardy perennials that do so well in the international award winning Earth-KInd® Research and Demonstration Gardens at Myers Park, as well as researched and proven spring, summer, and fall blooming bulbs suitable for our climate and soil extremes. The Texas-tough plants offered at The Mart will add a splash of color to your garden throughout the year. Purchase these proven winners by cash, check, or credit card (Visa or Mastercard only).
The Bulb and Perennial Mart is an indoor event, so come rain or shine! Join us for a day filled with fun, education, and the joy of gardening! We've done the homework and testing for you so that you can purchase with confidence! Our bulb varieties are top performers for North Texas gardens and include daffodils, tulips, lilies and more. This year we will again have a wonderful assortment of crinums. Crinums are truly heirlooms, the kind of plants great-grandma would have grown! Master Gardeners will be on hand to help you make the perfect selections, answer questions and give tips for successful planting, as well as give tours of the Research and Demonstration Gardens.
Event Activities:
8:30 a.m. — Early Bird Seminar
9:00 a.m.-1:00 p.m.
For directions to Myers Park & Event Center, click here.
Need Help Before Digging In?
For tips on preparing garden beds or planting bulbs, check out the information below:
How to Incorporate Bulbs in Your Landscape
Bulb Planting Guide
Bulb Planting Video
Proceeds from the sale benefit community outreach programs, and horticultural and water conservation education throughout Collin County.


text:
The Grossest Criminal Ever Punks Cops
This Cats vs Zombies Short Film Will Make Your Day
What Were These People Thinking? 16 Hilarious Tattoo Fails
25 Photos That Will Restore Your Faith In Humanity
Woman Spent Thousands To Transform Into Disney Princesses
AHHH! 13 Bone Chilling Pictures of Horrifying Hell Beasts
You Won't Believe What This Shadow in the Sea Is!
Apparently Gravity Has A Weird Effect On Girls
25 Most Unbelievable Coincidences
17 Rare Animals You Had No Idea Existed
Palmer Johnson Building The Bugatti Of Boats
12 Real People Who Look Just like Cartoon Characters
Top 10 "Useless" Organs
More Proof Drugs Will Ruin You Forever
17 of the Ugliest Celebrities
10 of the Craziest Foods You May Want to Try (or Not!)
10 Of The Most Fascinating Snake Facts
It's Crazy What Photoshop Can Do
Russia Proposes Superhighway Linking New York And London
What You Do When Your Crush Is Coming
10 Most Gorgeous Airline Flight Attendants
Kahn Design's Defender-Based 6x6 Can Be Yours For $310k
Born Fighters: the 25 Most Aggressive Dog Breeds
The Largest Ship On the Planet Will Amaze You
Prepare to Have Your Mind Blown
What Happens When Your Dog Is Over Protective
15 Place On Earth Where The Laws of Physics Don't Apply
The True Wonders of Plastic Surgery
When You Know You're Really Defeated
10 Animals That Don't Realize They're Animals


text:
Not all of the students can afford buying a Physics book to use as their reference material while studying physics, and because we think that I.T can be about Physics in some ways, our group decided to create and design a website that contains stuffs about College Physics which is composed of the following: * History of Physics
* Branches of Physics (Branches of Classical Physics and Modern Physics) * Significance of Physics.
* Tribute to the greatest Physicians and their contributions to advancement of Physics * Deeper explanation and recapitulation on Scientific Method, Significant Digits, Scientific Notation and the four types of variable relationship * Measurement
* Conversion Table
* Definition and examples of Scalar Quantity including the steps to solve it. * Definition and examples Vector Quantity including the steps to solve it. * All about Motion
* Random trivia about Sciences (Social, Natural, and Applied) * Quizzes, exercises, and activities ON EACH of the lessons to test if the students had absorbed and understand the lessons clearly *Further lessons would be added after the group provide a Physics book that would be the reference of this website if the investigatory project would be approved.
The lessons mentioned above would come from a book that we will provide if the project will be approved. We honestly state that the contents of the lessons that would be put on the website can be found somehow on other reference material but the thing that would make our work unique and original is, we would put our own assessment about a certain lesson and add some personal understanding about the topic to spice it up. We aim to make students more interested in Physics, encourage them to like it, and finally diminish their misconception that Physics is a hard subject by making it entertaining to study at the web. This investigatory project will surely satisfy the needs of thrifty students and lessen their...


text:
Newegg.com - A great place to buy computers, computer parts, electronics, software, accessories, and DVDs online. With great prices, fast shipping, and top-rated customer service - once you know, you Newegg.
If you are reading this message, Please click this link to reload this page.(Do not use your browser's "Refresh" button). Please email us if you're running the latest version of your browser and you still see this message.
Newegg.com - Computer Parts, Laptops, Electronics, HDTVs, Digital Cameras and More!
Sold and Shipped by Newegg
Filter Results
Fantastic Game!
This review is from: Encore Software Caillou Ready To Read Jewel Case
Pros: Very fantastic game! My mom has benefited from it alot! Goes great with my Little Bill Season 2 Blu™Ray disks!
Cons: Does not overclock and runs pretty hot in my VCR
Other Thoughts: Great for your parents!
0 out of 1 people found this review helpful. Did you?
This item is eligible for Newegg Premier benefits. Are you a Newegg Premier Member? If not, sign up today and get:
Your request will be processed within the next 24 hours.
Please add "email@example.com" to your address book to ensure delivery.See Today's E-Blast Promo


text:
IBM develops switch-based virtualization
By - Source: Tom's Hardware | 0 comment
IBM is developing a smart-switch based storage virtualization tool that will rival both EMC Corp's forthcoming Invista product and its own SVC software, according to multiple sources. Based on technology OEM'ed from start-up Incipient, the tool will not ship for some while, and according to one source will only begin beta testing in the first quarter next year, running on smart SAN switches made by Cisco Systems.
Ask a Category Expert
Create a new thread in the UK News comments forum about this subject
This thread is closed for comments
0 comment


text:
Rocky the Squirrel (from Rocky & Bullwinkle) plush dog toy with a plastic squeaker.
What a great way to remind yourself of your childhood and let your dog play with the toy you used to watch on TV growing up.
For medium breed dogs 25-50lbs
Size: 10 Inches
Designs are assorted as shown in the photo
Sold individually
© 2016 DogSupplies.com - Visit Our 3 Locations: DogSupplies.com - 11136 Sam Furr Road, Huntersville NC 28078 (704-875-7800)
Dog Supplies Outlet - 2960 St Rose Pkwy Ste 170, Henderson, NV 89052 (702-901-7557) OR 8450 W Sahara Ste 102, Las Vegas NV 89117 (702-869-8690)


text:
Library Chairs
Fashionable Library Chairs
Leveraging upon sound infrastructure and diligent personnel, we are able to supply and trade premium array of Fashionable Library Chairs. These fashionable library chairs are very smooth, soft and long lasting made from high quality fabric materials with designs inspired from traditional furniture items. Our fashionable library chairs are very comfortable and have excellent colours perfect for libraries, homes and many others. We are offering our fashionable library chairs to our clients at economical range of prices.
- Premium quality
- Sturdy
- Very durable
- Cost efficient
We are looking queries from Pune.
Designer Library Chairs
Serving our clients in the past long years, we are able to supply and trade high quality range of Designer Library Chairs. These designer library chairs are very stylish and fashionable with contemporary designs that are very lovely and eye pleasing. Our designer library chairs are very comfy and colourful made from high quality materials sourced from trusted manufacturers in the industry. These designer library chairs are very efficient to use and easy to maintain for that long lasting applications. Avail from us our range of designer library chairs at competitive prices.
- Excellent quality
- Flawless fabrication
- Very eye pleasing designs
- Economical
We are looking queries from Pune.
Comfortable Library Chairs
We are also offering our clients excellent range of Comfortable Library Chairs which we supply and trade in wide range. Our comfortable library chairs are highly appreciated for its excellent strength, durability and adorable designs. These comfortable library chairs are very comfy and offer relaxing designs that are perfect for everyday use. Our comfortable library chairs are designed to withstand pressure and weight from the users. We offer various colours and designs of these adorable comfortable library chairs at reasonable prices.
- High quality
- Very elegant
- Long lasting
- Sturdy
We are looking queries from Pune.
To,Memorex Systems


text:
Pinewood Derby® Speed Secrets$12.95This book helps you build a stronger relationship with your child as you work side-by-side to build the ultimate winning car! From author David Meade, who got his start as a boy in the PWD, the book is filled with extremely useful information as well as tried and true techniques, to take you step-by-step with instructions, photos, and diagrams. Paperback, 128 pages. Learn More
Boy Scout™ Songbook$7.99Includes lyrics to all of the songs on the new Boy Scout Songbook CD. Great for singing songs at campfires, meetings and roundtables. Learn More
Okpik: Cold Weather Camping$9.99BSA's guide to cold-weather camping. Learn More
Woodworking with KidsOriginal Price:$18.95 Current Price: $4.99This is the book for youngsters, parents, and grandparents who want to fashion things from wood and having fun doing it together. Whether it's building an easel or crafting a birdhouse, this book will guide you as you work, learning the best and safest ways to complete your projects. Book contains more than 20 fun projects, with color photos and easy-to-follow, step-by-step instructions. Each project has detailed drawings with measurements and cutaways that eliminate guesswork. Learn More


text:
|Publication number
|Publication type
|Application number
|Publication date
|Nov 15, 2011
|Filing date
|Feb 23, 2010
|Priority date
|Aug 31, 2005
|Fee status
|Also published as
|Publication number
|Jun Ye, Moshe E. Preil, Xun Chen, Shauh-Teh Juang, James Wiley
|Original Assignee
|Asml Netherlands B.V.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (14), Non-Patent Citations (6), Referenced by (32), Classifications (17), Legal Events (2)
|External Links: USPTO, USPTO Assignment, Espacenet
This application is a divisional of U.S. patent application Ser. No. 11/466,978 filed on Aug. 24, 2006, issued as U.S. Pat. No. 7,695,876, on Apr. 13, 2010, which claims priority from U.S. Provisional Patent Application No. 60/713,123, filed Aug. 31, 2005, the contents of both applications being hereby incorporated by reference.
This invention relates generally to lithography processes and relates more particularly to a method for identifying process window signature patterns for lithography process control.
In the semiconductor industry, microlithography (or simply lithography) is the process of printing the circuit patterns on a semiconductor wafer (for example, a silicon or gallium arsenide wafer). Currently, optical lithography is the predominant technology used in volume semiconductor manufacturing. Optical lithography employs light in the visible to deep ultraviolet spectrum range to expose the resist on a wafer. In the future, extreme ultraviolet (EUV) and soft x-rays may be employed. Following exposure, the resist is developed to yield a relief image.
In optical lithography, a photomask (often called a mask or a reticle) is first written using electron-beam or laser-beam direct-write tools. A typical mask for optical lithography consists of a glass (or quartz) plate of six to eight inches on a side, with one surface coated with a thin metal layer (for example, chrome) of a thickness of about 100 nm. The chip pattern is etched into the metal layer, hence allowing light to transmit through. The area where the metal layer is not etched away blocks light transmission. In this way, a pattern may be projected onto a semiconductor wafer.
The mask contains certain patterns and features that are used to create desired circuit patterns on a wafer. The tool used in projecting the mask image onto a wafer is called a stepper or scanner (hereinafter collectively called "exposure tool").
Illumination source 12 may be laser source operated, for example, at UV (ultra-violet) or DUV (deep ultra-violet) wavelengths. The light beam is expanded and scrambled before it is incident on illumination pupil 14. Illumination pupil 14 may be a simple round aperture, or have specifically designed shapes for off-axis illumination. Off-axis illumination may include, for example, annular illumination (i.e., the pupil is a ring with a designed inner and outer radius), quadruple illumination (i.e., the pupil has four openings in the four quadrant of the pupil plane), and other shapes like dipole illumination.
After illumination pupil 14, the light passes through the illumination optics (for example, lens subsystem 16 a) and is incident on mask 18. Mask 18 contains the circuit pattern to be imaged on wafer 22 by the projection optics. As the desired pattern size on wafer 22 becomes smaller and smaller, and those patterns becomes closer and closer to each other, the lithography process becomes more challenging. In an effort to improve imaging quality, current processing techniques employ resolution enhancement technologies ("RET"), such as, for example, optical proximity correction ("OPC"), phase shift masks ("PSM"), off-axis illumination ("OAI"), condenser and exit pupil filters, and so on.
Many of the RET technologies are applied on or directly to mask 18. For example, OPC and PSM, which modify the light wave to (1) compensate for the imperfection of the imaging property of the projection optics, for example, the OPC technology is used to compensate the optical proximity effect due to light interference, and/or (2) take advantage of designed light interferences to enhance the imaging quality, for example, the phase shift mask technology is used to create phase shifting between neighboring patterns to enhance resolution.
Notably, mask 18 may not be "perfect" due to its own manufacturing process. For example, corners on mask 18 may not be sharp but may be rounded and/or the linewidth may have a bias from design value where the bias may also depend on the designed linewidth value and neighboring patterns. These imperfections on mask 18 may affect the final imaging quality.
The projection optics (for example, lens subsystems 16 b and 16 c, and projection pupil filter 20) images mask 18 onto wafer 22. In this regard, the projection optics includes a projection pupil filter 20. Projection pupil filter 20 limits the maximum spatial frequency of the mask pattern that can be passed through the projection optics. A number called "numerical aperture" or NA often characterizes projection pupil filter 20. There are also proposed RET techniques that modify projection pupil filter 20, which is generally called pupil filtering. Pupil filtering may include modulation for both the amplitude and the phase on the passing light beams.
Due to the wavelength of light being finite, and current techniques employing wavelengths that are larger than the minimum linewidth that is printed on wafer 22, there are typically significant light interference and diffractions during the imaging process. The imaging process is not a perfect replication of the pattern on mask 18. Current techniques employ physical theory to model this imaging process. Further, due to the high NA value of current exposure tools, different polarizations of the light provide different imaging properties. To more accurately model the lithography process, a vector-based model may be used.
The projection optics may be diffraction-limited. However, lens subsystem 16 b and 16 c in the projection optics are most often not completely "perfect." These imperfections may be modeled as aberrations, which are often abstracted as some undesired phase modulation at the plane of projection pupil filter 20, and are often represented by a set of Zernike coefficients. After the light finally reaches the surface of wafer 22, they will further interact with the coatings on wafer 22 (for example, the photo-resist). In this regard, different resist thickness, different optical properties of the resist (for example, its refractive index), and different material stack under the resist (for example, bottom-anti-reflection-coating or BARC), may further affect the imaging characteristics. Some of these effects may also be abstracted by a modulation at the pupil plane.
When the resist is exposed by the aerial image and thereafter baked and developed, the resist tends to undergo complex chemical and physical changes. First principle and empirical models have been developed to simulate these processes.
When wafers are printed using an exposure tool, ideally, wafer 22 should be placed exactly at the focal plane of the projection optics, or a designated location away from the focal plane. However, due to the imperfect mechanical control of exposure tools, there is always a small deviation between the designated plane and the actual wafer plane. That deviation is called defocus, or sometimes just called "focus," and represented by a distance unit, e.g., 50 nm. The defocus introduces additional imperfections in the imaging path, and can also be characterized by a phase modulation at the pupil plane.
Furthermore, all wafers, and dice on the wafers, are ideally exposed by a designated amount of exposure dose, e.g., 20 mJ/cm2. However, due to the imperfections in the illumination control and changes in the reflectivity and uniformity of the film stacks on the wafers being patterned, there is always a small deviation between the ideal exposure dose and the actual exposure dose deposited on a die. That deviation is called exposure dose variation, or sometimes just called "exposure," and is represented by a percentage deviation from the ideal exposure dose, e.g., 10%.
The combination of focus and exposure errors means that the dimensions of the wafer features that are patterned may not match exactly with the dimensions required by the design. Since every structure responds differently to focus and exposure errors in different ways depending on the width, shape, and local environment of the specific structure, it is not possible to describe the response of every individual structure in a circuit pattern with a limited set of figures of merit.
In practice, the most common metric used to characterize a lithography process is the width of the smallest features being patterned on a given process layer for a given technology. This minimum dimension is referred to as the "critical dimension" or CD. While critical dimensions are actually intended to represent the three dimensional resist profile, the term CD is usually associated with a one-dimensional slice through the resist line, also referred to as the linewidth. In a looser definition, the term CD is often used to refer to any linewidth measurement even if it is not the minimum dimension on the device.
Under a certain lithographic setting (e.g., exposure tool, wavelength, NA, and so on), the amount of defocus and exposure dose variations that a circuit design can tolerate, while still producing functional chips, is called the design's "process window." The process window is often characterized as an area or region in the two-dimensional F-E plot, where "F" is defocus, and "E" is exposure dose variation. Such a plot may also be referred to as an "ED tree", so-called because of the tree-shaped process window which results when exposure (E) is plotted on the x-axis and defocus (D) is plotted on the y-axis. Some RET techniques (e.g., PSM, scattering bars in OPC, OAI) can enhance the process window for a certain circuit design. The settings of the exposure tool (e.g., NA) also have a big impact on the process window.
A process window for a lithography process is further limited because different patterns within a circuit design have different process windows. These differences may include shifts in the best focal plane position, shifts in the best exposure, and changes in the allowed range of focus and exposure. Different patterns also have different criteria for successful printing. While CD variation of up to +/−15% may be tolerable for some non-critical features, the tolerance for the most critical structures may be only half as much. The failure modes of different patterns may also be very different. Some patterns may be considered unacceptable due to excessive CD variation, others due to excessive changes in their sidewall profiles, and others may suffer from excessive line end pullback or corner rounding. Catastrophic pattern failures are also possible due to the interaction of neighboring structures. A CD variation that may be acceptable if a given feature were being printed as an isolated structure might cause bridging, necking, or other unacceptable pattern variations in a different local environment.
The ultimate goal of the lithography process is to deliver a robust and well maintained "common process window," that is, a process window in which every feature prints within specifications. An example of the overlapping of multiple process windows for individual structures leading to a common process window is shown in
OPC is one of a number of techniques available to lithography process designers to optimize the process window overlap between all critical features by adjusting the mask level pattern so that, in principle, all patterns are reproduced at the desired wafer dimensions and shapes under a common set of focus and exposure conditions. However, due to the complex non-linear nature of the pattern transfer process, OPC remains a difficult technique to implement, test, and insert into production with the assurance that all features of interest are correctly transferred from mask to wafer in a manufacturing fab. It is particularly difficult to determine which limited set of structures should be measured and tracked on a regular basis to guarantee that all of the structures in the circuit design are printed correctly.
The definition of common process window used to this point has been phrased in terms of CD performance as the sole metric of process capability. In fact, the common process window for a viable process must be such that the entire three-dimensional pattern is replicated faithfully, including the sidewall profile and height of the remaining resist pattern after development. A complete, common process window would insure that the CD, sidewall angle (SWA), and resist loss (RL) during development are all within specifications for all structures in the circuit layer being patterned. In practice, the process window is often defined only in terms of the CD. A typical process window may be defined as the region of the F-E plane over which the critical dimensions are patterned within specified tolerances, such as +1-10% of the nominal target dimension.
In addition to focus and exposure, many other parameters can have an adverse impact on the common process window, including, but not limited to, lens aberrations (Zernike aberrations, scattered light, and other mid- to long-range spatial frequency errors), imperfections in the exposure tool illumination system (uniformity, localized partial coherence, and localized variations in pupil filling), and less than optimal optical proximity corrections. (See Wong, "Resolution Enhancement Techniques in Optical Lithography," SPIE Press, Bellingham, Wash., Volume TT47, ISBN 0-8194-3995-9 (2001), and Mahajan, "Aberration Theory Made Simple," SPIE Press, Bellingham, Wash., Volume TT06, ISBN 0-8194-0536-1 (1991)).
A typical integrated circuit device contains between 100 million to several billion structures, and there are typically several hundred devices or chips on a typical silicon substrate with a diameter of 200 or 300 mm. It is clearly impossible to measure the dimensions of every structure on a single device, and even more so to measure every device on every production wafer. In practice, a limited set of structures is defined, either within the device areas or placed in the scribe lines between device areas, for in-process monitoring and control.
One of the most difficult challenges in implementing complex OPC into production, such as leading edge model-based OPC, is the difficulty in determining which limited set of structures should be measured and tracked on a regular basis to guarantee that all of the structures in the circuit design are printed correctly. Since all patterns respond differently to changes in focus, exposure, and other process variables, a test structure that is sensitive to one parameter that must be monitored and controlled may be insensitive to other critical parameters. Thus, even if the process monitors seems to indicate that the process is in control, other patterns which are critical to the proper operation of the device may drift without being detected by the metrology plan of record. Insuring that all of the critical parameters are adequately monitored and controlled is a growing challenge in integrated circuit manufacturing.
In today's wafer fabs, exposure tool related optical conditions such as focus, exposure, illumination and aberration may be monitored using test masks and test wafers using specially designed test patterns, or by an exposure tool's self-metrology while undergoing maintenance checks. The optical analysis in these approaches is not in-situ, i.e., the extracted optical conditions are not present when product wafers are printed. Therefore the use of these data is limited.
It is also possible to use test patterns in the product mask's scribe lines, i.e., the spaces between the device areas, to print test patterns, and analyze the test patterns in the scribe lines to extract the optical conditions when the wafer is printed. This approach will take up the valuable space in the scribe lines, where many other patterns are needed, for example alignment patterns. Furthermore, this approach cannot analyze the optical conditions inside the device design itself.
In practice, a limited set of test structures is defined, either within the device areas or placed in the scribe lines between the device areas, for in-process metrology and process control. The dimensions of these test structures are usually chosen to be at or near the minimum feature size that will be patterned within the device, and are referred to as "the CD" of the layer being patterned regardless of whether the width of the structures being measured is actually the minimum or most critical dimension in the device.
The CD is intended to be measured as near as possible to the base of the three-dimensional resist structure, that is, at the resist-substrate interface, to assure the optimum feature size for subsequent process steps such as etch, film deposition, polishing, and ion implantation. This is often difficult due to the top-down viewing angle of scanning electron microscopes used for CD metrology (CD-SEMs) and the high aspect ratio of the three-dimensional profiles, which typically approach 3:1 (3 units depth in the z-direction for every one unit of width in the x-y plane). Scatterometry (SCD) and tilt-SEMs are intended to help resolve this problem and may be used to determine metrics of resist profile and resist loss in addition to CD, but they suffer from other sources of error and uncertainty as well. While it is possible to obtain a reasonable approximation of the CD at the resist-substrate interface for the specified test structures when the process is very close to optimal, the uncertainty in the true CD increases as the process drifts away from the optimal settings.
CD data from multiple test structures with different geometries may be collected in an effort to more closely monitor the common process window of the entire pattern transfer process. While this comes closer to monitoring the full process than simply measuring a single type of test structure, it falls far short of the ultimate goal of representing the performance of all patterns and structures within the device, including the effects of the local environment on the dimensional stability of each pattern. In addition, a full characterization of the common process window would need to take into account the full three-dimensional shape of the metrology patterns, including sidewall angle, sidewall curvature, or other deviations from an idealized trapezoidal shape, and the height of the pattern indicating resist loss from the top of the three-dimensional structure.
The non-linear manner in which each different structure responds to its own local environment and to the global changes in optical and other process conditions throughout the pattern transfer process from mask to wafer creates a complex manufacturing environment where it is difficult to determine, from a limited number of measurements, whether or not all of the desired features within the device are printed within specification, and whether or not all of the variable process condition parameters are being maintained at or near their optimum operating points. This leads to several related problems:
(1) The limited amount of metrology data and test structures cannot adequately ensure that the CDs across the device are within specifications and that the entire device will operate as intended. Since typical manufacturing cycle times can take several months, it is extremely disruptive to the entire business when a large number of wafers turn out to have unacceptably low yield of devices that work properly, requiring new lots to be started and deliveries to be substantially more expensive and behind schedule.
(2) Even when a variation in CD performance is detected, the proper corrective action to take is often unclear due to the confounding influences of focus, exposure, and other process conditions. Historically the easiest adjustment to make has been the exposure dose (See Levinson, "Lithography Process Control," SPIE press, Bellingham, Wash., Vol. TT28, ISBN 0-8194-3052-8 (1999)). However, this blind correction, that is, using only a single adjustable parameter to force a desired output on a limited set of data regardless of which of many parameters actually caused the process to deviate in the first place, often means that the root cause of the CD variation remains undetected and incorrectly compensated.
(3) If the process variation of the test structures was caused by a drift or shift in other parameters besides exposure, a simple exposure compensation or other blind adjustment may be adequate to correct the CD of the test structures, but not of all structures within the device, which could result in the final devices having reduced functionality and yield.
(4) Although crude correction such as a blind exposure dose adjustment may bring the metrology target CDs back into specification, if the error was in fact caused by a focus drift or other optical error instead of an exposure drift, the resulting resist profiles will not have the correct sidewalls intended for the process. Thus, when the wafers are etched, the final profile of the resulting etched structure may be incorrect, leading to improper circuit operation and device failure.
(5) Even if the wafers in question are adequately corrected by a simple dose or other blind correction, other wafers that are to be patterned with other device layouts may be patterned incorrectly with the same relative correction. Thus, by changing the only one parameter to compensate for drifts in other parameters, the process control algorithms for the entire production line may become unstable.
(6) Even if the process can be adequately corrected with a global adjustment of the exposure dose or some other blind correction, if the underlying source of the process variation is not correctly identified and corrected, it may continue to drift further until no amount of compensation of a single parameter can recover the desired process outputs. At that point, the orderly flow of wafers through the entire process line may be disrupted as CDs begin to fall outside the specification limits and the root cause analysis of the true source of the variation must be initiated at great cost and disruption to the manufacturing environment.
Many different approaches have been developed to try to improve CD monitoring and control systems. In particular, a number of techniques have been disclosed to try to separate out the influences of focus and exposure to solve some of the problems listed above. While some of these methods are partially successful, they all suffer from drawbacks in terms of metrology calibration and/or requirements for extensive test structures that do not adequately represent the circuit features. In addition, they are limited to focus and exposure only and do not include other optical parameters of interest. Many of these techniques require extensive metrology and test structure calibration and cannot be easily adapted to changes in circuit design and/or process targets.
U.S. Pat. No. 6,414,326 to Nguyen discloses a simple method to deconvolve focus and exposure errors by measuring two different test structures, one with an isolated pitch and the other with a dense pitch. Since these pitches respond differently to focus and exposure, a given combination of CD errors for the respective patterns should correspond to a unique set of focus and exposure errors. Like many similar efforts, this approach still suffers from an ambiguity in the sign of the focus error: a given combination of isolated and dense CD errors could be due to a focus shift of a given magnitude but in either the positive or negative direction. Nguyen teaches a possible solution using astigmatism of the lens to differentiate between the two focus directions for vertically vs. horizontally oriented features, but this requires extensive characterization of lens astigmatism across the field which may also be convolved with other lens parameters.
U.S. Pat. No. 6,673,638 to Bendik et al. discloses a system for creating line end test structures that are modified to print in a deliberately defocused state even when the exposure tool is at best focus. A comparison between differently modified structures can uniquely determine dose and focus errors; the sign ambiguity of the focus can be solved by printing features of opposite polarity (lines and spaces). This approach is restricted to special targets in the scribe line, not actual device geometries, and depends on line end metrology, which is less precise and more susceptible to convolution with other optical aberrations than line width (CD) measurements.
U.S. Pat. No. 6,929,892 to Shishido et al. discloses the use of an SEM with tilt capability or scatterometry to determine the sidewall profile of a highly isolated feature, which is known to be more susceptible to focus-induced variations than dense structures. The ambiguity in the sign of the focus error is said to be resolved by measuring isolated structures of opposite polarity. Like U.S. Pat. No. 6,673,638, this approach is limited to scribe line test structures, not actual device geometries, and the focus sensitive isolated structures are also sensitive to other aberrations.
U.S. Pat. No. 6,803,995 to Ausschnitt discloses a focus control system using special scribe line patterns wherein line end shortening of the segments of a long pattern ("schnitzl") can be imaged as line width changes in an optical measuring system. The effects of focus and exposure can be deconvolved using targets of opposite polarity, but the sign ambiguity of the best focus position can only be resolved by exposing some fields on the wafer at deliberately defocused conditions, resulting in potential lost chips and complicated exposure and metrology schemes. U.S. Pat. No. 6,643,596 to Firth et al. also discloses a system of deliberately inducing focus perturbations on a lot-by-lot basis to update a focus model. This results in better focus metrology at the expense of negatively impacting the CD control of each lot processed at less than optimal focus.
Various applications of scatterometry have been described as alternative approaches to separating the effects of focus and exposure while also providing CD metrology data. U.S. Patent Application Publication No. 2004/0190008 to Mieher et al. discloses the use of CD, SWA, and RL values derived from SCD spectra to determine a unique combination of focus and exposure conditions. U.S. Pat. No. 6,429,930 to Littau et al. discloses the use of SCD spectra to uniquely determine focus and exposure by comparison to a library of stored spectra and U.S. Patent Application Publication No. 2004/0223137 to Littau et al. discloses extracting an SCD-derived cross section and comparing it to simulated or measured cross sections as a function of F-E conditions. All SCD approaches are limited to arrayed test structures placed in the scribe lines, not device geometries, and are typically limited to one-dimensional line space patterns or at best regular arrays of two-dimensional features such as contact holes. It should also be kept in mind that while SCD does provide highly repeatable measurements, the CD values extracted from SCD curves are all modeled results based on regression, simulation, or lookup tables and do not represent direct measurements of the actual CD or sidewall angle.
Several approaches have been described using signal analysis of the SEM profiles or images to determine the sidewall profile by comparison to stored reference signals. U.S. Patent Application Publication No. 2002/0051567 to Ganz et al. discloses collecting images of assorted structures and comparing them to a library of the same patterns printed at different focus and exposure settings. This technique does not describe how an adequate set of patterns is determined to insure predictability over a range of F-E conditions, or to separate F-E effects from other imaging errors, nor does it result in CD metrology data of sufficient quantitative precision to insure that the process is operating within specifications. U.S. Pat. No. 6,909,930 to Shishido et al. discloses collecting CD-SEM data and analyzing the shape of the SEM line scan profiles or images to determine whether the CD errors are due to focus or exposure. This approach requires extensive calibration, therefore it can only be applied to specific structures which are carefully characterized beforehand and stored in a library. This technique is also sensitive to slight changes in the SEM line scan profile which may be induced by changes in the SEM conditions rather than the exposure tool conditions. U.S. Pat. No. 6,913,861 to Shishido et al. discloses creating special scribe line test structures such as diamond or other highly tapered patterns where the exposure dose is effectively varied along the structure. SEM line scan analysis is performed on these special structures to deconvolve the effects of focus and exposure. U.S. Pat. No. 6,791,082 to Komuro et al. discloses a similar approach using scribe line patterns of opposite polarity to separate the impact of focus and exposure and to resolve the ambiguity in the sign of any focal plane error. Both of these approaches depend on special scribe line targets, not actual device geometries, and rely on extensive look up tables and the stability of the SEM line scan to extract the condition of the exposure tool.
All of the above approaches aim to separate the contributions of focus and exposure on pattern CDs under the tacit assumption that all other optical parameters can be effectively ignored. U.S. Pat. No. 6,795,163 to Finders et al. shows that these other parameters can be as important, if not more so, in determining the patterned CD errors of a given line width as a function of pitch. Finders et al. disclose that the partial coherence, sigma, of the exposure tool can be adjusted to tilt the CD vs. pitch curve to suffer less CD variation across a range of pitches. This illustrates that even in a system that can adequately separate focus and exposure contributions under ideal conditions, the addition of a small illumination error can drastically impact the measured CD performance and so lead to incorrect determination of the computed focus and exposure adjustments.
It is therefore highly desirable to have a system and technique to effectively monitor or observe the lithography process's F-E condition inside the device with actual circuit design patterns, on any selected wafers and at any selected dice on that wafer. This need can be realized by a system and technique that can extract the F-E conditions of the lithographic process directly from printed patterns on product wafers, on any selected wafers and at any selected dice on that wafer.
It is further desired that this system and technique be able to insure the correct patterning of all structures within the device, not just the structure being measured. This need can be realized by a system and technique that can optimize the selection of the optimum set of measured patterns from actual device design patterns that forms a complete characteristic set such that the correct patterning of this set of patterns serves as measurable proof that all patterns within the device are reproduced within specifications.
Beyond the traditional F-E process window, other optical conditions, e.g., NA, illumination conditions, and aberrations, will also drift over time and impact the patterning of the device structures. It is also highly desirable that these other drifts can be extracted directly from the observations of the printed circuit patterns on wafers.
It is further desirable that this system and technique should be capable of quickly and effectively identifying specific patterns within the device that, when measured, will provide precise and specific feedback to the lithography control system indicating not just the CD values, but also the specific corrections that need to be applied to the system to bring the CDs back within specifications and to maintain the exposure tool and the lithography process at their optimum operating conditions. These needs can be realized by the system and technique to locate a complete characteristic set of patterns within the circuit whose collective response to the multivariate optical and process variations provides a unique monitoring and control solution.
A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.
In one embodiment, a method for identifying process window signature patterns comprises performing simulations of a lithography process, using a representation of a device area of a mask, at two or more non-nominal locations and at nominal condition in a process window to produce simulation results, determining a simulated value for each metric in the pattern-metric pairs from the simulation results, determining simulated values from the simulation results for at least one metric at the two or more non-nominal locations and at nominal condition in the process window, wherein the simulated values for the at least one metric are determined at a plurality of locations with the device area. The method further comprises, for each of the plurality of locations within the device area determining a difference between simulated values for the at least one metric at the two or more non-nominal locations in the process window and the simulated value for the at least one metric at nominal condition, identifying a number of locations within the device area where the difference for the at least one metric is above a threshold, if the number of identified locations is greater than a predetermined number, modifying the threshold and identifying the locations within the device area where the difference for the at least one metric is above the threshold until the number of identified locations within the device area is less than the predetermined number, and assigning patterns associated with the number of identified locations within the device area that is less than the predetermined number to be signature patterns.
In one embodiment, a method for using the signature patterns for lithography process control comprises receiving measured values of the at least one metric associated with the signature patterns, the measured values having been obtained from measurements of the signature patterns on a wafer processed by the lithography process using the mask, finding a location in the process window where a total difference measure between the measured values of the at least one metric associated with all of the signature patterns and the simulated values of the at least one metric associated with all of the signature patterns at the location in the process window is minimized, and determining a change between the location in the process window where the total difference measure is minimized and nominal condition to determine a change in the lithography process. The change in the lithography process is then fed back to the lithography process for process control or fed forward to another process, for example an etching process.
The method of the invention enables direct process window extraction from device patterns on production wafers by determining a set of process window signature patterns (also referred to herein as "signature patterns") within a device design that, when monitored as part of a lithography process control system, provide clear feedback to the control system on how the lithography process is performing, whether the CDs for all features within the device, not just the measured features, are within specification, and which process condition parameters should be adjusted and by how much in order to maintain the lithography process and exposure tool at the optimum operating condition.
It is well known that device patterns, depending on their environment, respond differently to changes in focus, exposure dose, and other process condition parameters. The collective response of the signature patterns to the entire range of process condition parameters can be decomposed and analyzed to determine the exact process condition parameters that have drifted and by exactly how much. The signature patterns can be selected for any given device layout. The signature patterns are the minimum subset of patterns in the design area of a mask that allow for the required level of process control with the minimum amount of metrology effort and expense. The metrology data from the signature patterns is used to extract the conditions of all process condition parameters that caused drift in the imaging process. The method of the invention includes simulating the impact of these process drifts on every signature pattern within the circuit across the full field of the exposure tool and determining what corrections should be applied to the lithography process to optimize the pattern transfer for the specific devices being patterned, as well as what corrections to process condition into the fab-wide process control system to be applied at later steps in the process and/or to other products which would be subsequently patterned using the same process equipment.
As used herein, the term "process condition parameters" refers to any of the exposure tool parameters and/or the lithographic process parameters that can be modeled and whose impact on the pattern transfer process can be simulated, whether or not that parameter can be adjusted and corrected. The process condition parameters may also be called "input parameters" to the lithography process. The process condition parameters can be subdivided into adjustable and non-adjustable parameters, and the adjustable parameters may be further sub-divided into those that are adjustable by the end user and those that require more extensive service procedures to adjust. The user response to changes in the process condition parameters may differ depending on whether or not the particular parameter is user-adjustable. These distinctions will impact the user response to observed changes in the process condition parameters, but it does not restrict which process condition parameters may be monitored.
While no useful set of patterns can be found within a device design such that each pattern would be sensitive to the variation of one and only one process condition parameter, there does exist a set of signature patterns such that the combined response of the signature patterns uniquely identifies the combination of all process condition parameter variations that contributed to the printing of the circuit design. That is, while no specific individual pattern can be used in isolation to detect variations in focus and only variations in focus while another pattern monitors exposure, another monitors spherical aberration, another monitors partial coherence of the illumination system, and so on, there does exist a set of signature patterns whose response can be uniquely decomposed to identify any deviations from nominal in any of the above-mentioned process condition parameters and to determine the specific corrections to apply to each of the process condition parameters. Even though no single signature pattern acts as a unique probe of one and only one process condition parameter, the set of signature patterns acts collectively as if it were a complete set of probes, each of which responds to one and only one of the process condition parameters of interest.
The full chip simulation system disclosed in U.S. Pat. No. 7,003,758, the subject matter of which is hereby incorporated by reference in its entirety, can be used to automatically simulate the response of a full chip design to each of the process condition parameters of interest. The simulation system may also be used to determine the optimum set of signature patterns that have the highest sensitivity to the process condition parameters of interest with the minimum number of measurements required, create a metrology recipe to collect the required images and/or CD data from printed wafers, extract metrics of interest (image contours, CD values, or other metrics of pattern quality) from the measured data, and analyze these metrics to uniquely identify all variations in the process condition parameters. The extracted process condition parameters can be fed back into the simulation system to predict the quality of the printed patterns across the chip and across the full wafer, determine if the quality is acceptable or not, and pass back a go/no go decision flag and correction parameters to the manufacturing control system.
In a simple example for positive photoresist, as the exposure dose is reduced, the CD of all line patterns (chrome patterns on the mask) will increase and the CD of all space patterns will decrease. However, when focus changes, some spaces and line patterns will grow and others will shrink, depending on the exact pattern environment, such as the pitch and OPC correction patterns in the vicinity, and the exact exposure dose. In this example, a full chip simulation is performed to find those isolated lines, and line-space pairs with the right pitch, that behave differently due to focus and exposure changes. Using the measured relative change in linewidth for these patterns, the location in the focus-exposure process window can be identified. This example is provided only as the simplest representation of the more general case.
In step 414, locations in a process window are selected including nominal condition. The locations in the process window are defined by values of process condition parameters to the lithography process. The process condition parameters may include focus, exposure dose, film stacks, lens aberrations, illumination shifts, coherence, and/or any other process condition parameters to the lithography process, whether user-correctable or not. In the following discussion, the process window is in a two-dimensional focus-exposure space for ease of illustration. The locations in the process window are selected so as to include multiple values of each process condition parameter, i.e., varying values of focus and exposure dose, and the nominal condition of each process condition parameter. In a preferred embodiment, the selected locations in the process window include two or more non-nominal conditions and nominal condition. The distance between the varying values of the process condition parameters is preferably the minimum adjustable step size of the process condition parameter.
In step 416, the lithography process is simulated using data representative of the device area of a mask at each of the selected locations in the process window, producing simulation results for each value of the process condition parameters. The lithography process is simulated using a lithography simulation system, one embodiment of which is described below in conjunction with
In step 418, the CDs of the patterns in the simulation results are measured to produce simulated CD values. The CDs are measured at the locations selected in optional step 412 or at other regularly-spaced locations within the device area. Then, in step 420, for each CD measurement location, the distance between the simulated CD values at the selected locations in the process window and the simulated CD value at nominal condition is determined. In one embodiment, the minimum distance can be determined in a root-mean-square sense. For example,
where j=(1, 2, . . . , M), M is the total number of the selected locations throughout the entire device area of a mask where CD measurements are to be taken, Dnom(j) is the difference between the simulated CD values at the selected locations in the process window and the simulated CD value at nominal condition for the j-th CD measurement location, N is the number of selected locations in the process window, Wi, is a weighting factor, CD(Ei,Fi) is the simulated CD value at location (Ei,Fi) in the process window, and CD(Eo,Fo) is the simulated CD value at nominal condition. In step 422, the CD measurement locations for which the distance Dnom(j) is greater than a threshold are identified. The value of the threshold is preferably based on the noise of the lithography simulation system used to produce the simulated results.
If, in step 424, it is determined that the number of CD measurement locations for which the distance Dnom(j) is greater than the threshold is greater than 30, then in step 426 the threshold is increased and the method returns to step 422. If, in step 424, it is determined that the number of CD measurement locations for which the distance Dnom is greater than the threshold is less than 30, then the method continues in step 428. In step 428, the patterns associated with the 30 or fewer CD measurement locations are assigned to be the process window signature patterns. In another embodiment, if the number of CD measurement locations for which Dnom(j) is greater than the threshold is much fewer than 30, then the threshold will be decreased until a sufficient number of locations are identified.
Next, in step 514, wafers are processed using the lithography process and the mask to produce printed patterns on the wafer. In step 516, the metrics of the printed signature patterns on the wafer are measured according to the metrology recipe. In step 518, the location in the process window where a total difference measure between the simulated value for each metric and the measured value for each metric is minimized for all signature patterns is identified. In one embodiment, the total difference measure between the simulated and measured value for each metric is calculated as follows:
where G(F,E) is the difference measure as a function of the location in the process window (here values of focus, F, and exposure dose, E), N is the number of the signature patterns, where there is one metric measured for each signature pattern, Wi is a weighting factor, Mwafer (i) is a measured value of metric M of the i-th signature pattern, and Msim (i)(F,E) is a simulated value of metric M of the i-th signature pattern at a location (F,E) in the process window. The location in the process window, i.e., the values of focus and exposure dose (F,E), that results in the minimum value for G(F,E) is identified. In one example, determining the minimum value of G(F,E) may be performed by selecting an arbitrary location in the process window, solving for G(F,E) for that location, and iterating these steps until the minimum value of G(F,E) is determined. Any appropriate techniques for determining the minimum value of G(F,E) are within the scope of the invention, for example using a steepest decent algorithm or using a look-up table.
In step 520, the distance between the identified location in the process window and nominal condition of the lithography process is determined. This distance identifies a change in the process condition parameters (in this example, focus and exposure dose) of the lithography process. This change in the process condition parameters can then be fed back to a control system for the lithography process or fed forward to a control system for other processes, for example an etch process.
In step 618, for each pattern-metric pair, differences between the metrics of the simulation results are determined and the sensitivity of each metric to each of the process condition parameters is determined. The sensitivity can be expressed as an average rate of change in a metric across the full range of values for the process condition parameters, as a derivative (instantaneous rate of change at specific values of the process condition parameters), as a total range of deviation, or some similar, normalized indication of relative sensitivity with respect to a specific process condition parameter of interest.
Next, in step 620, a matrix of the sensitivities of the metrics to the process condition parameters is created. In one embodiment, the matrix has one column for each process condition parameter and one row for each pattern-metric pair. This matrix is referred to herein as the pattern matrix.
In a slightly more realistic but still idealized example,
In step 622, a subset of the pattern-metric pairs that have the most linearly separable sensitivities to changes in the values of the process condition parameters is selected. In one embodiment, the pattern matrix is analyzed to find the pattern-metric pairs where a limited number of process condition parameters have the most dominant effect on the metric relative to all of the other process condition parameters. These pattern-metric pairs form an initial subset of pattern-metric pairs. A requirement for the initial subset of pattern-metric pairs is that for each process condition parameter, at least one pattern-metric pair with high sensitivity to that process condition parameter is included. In another embodiment, the pattern matrix is analyzed to determine the minimum number of pattern-metric pairs required to satisfactorily monitor the lithography process. This determination can be based on sample testing of a submatrix of the sensitivities to determine a set of pattern-metric pairs with the most easily deconvolved sensitivities, i.e., where the sensitivities of the pattern-metric pairs to a range of different process condition parameter variations can be used to most accurately solve for the correct values of variations of the process condition parameters. This sample testing can be performed using the lithography simulation system described below in conjunction with
In another embodiment, the full pattern matrix is analyzed using other means, such as algebraic testing. In this case, the matrix can be analyzed and the initial subset of pattern-metric pairs that have the most nearly orthogonal set of sensitivities, that is, the set where the sensitivities to the full set of process condition parameters are as different as possible, are identified. Various statistical metrics can be employed to identify the optimum subset of pattern-metric pairs and select the minimum number of pattern-metric pairs needed for reliable process monitoring and control, including, but not limited to, metrics of the respective cross-correlation between the various pattern-metric pairs and process condition parameters and metrics of the orthogonality of the sensitivities of the pattern-metric pairs.
In step 624, the initial subset of pattern-metric pairs is evaluated. The initial subset of pattern-metric pairs may be evaluated based on how dominant one or more process condition parameters is compared to the other process condition parameters, on the sensitivity of the pattern-metric pair to changes in the process condition parameters, and on other factors, such as ease of measurement of the specific metric using the metrology tools available. A satisfactory subset of pattern-metric pairs must have at least a number of pattern-metric pairs equal to the number of process condition parameters and must respond strongly to multiple different process condition parameters, but with linearly independent sensitivities.
If the initial set of pattern-metric pairs is not satisfactory for reliable monitoring of the lithography process, then in step 626 a further subset of pattern-metric pairs is selected. Any of the techniques described above for selecting the initial subset of pattern-metric pairs may also be used to select the further subset of pattern-metric pairs. Then the method returns to step 624 where the further subset of pattern-metric pairs is evaluated. Steps 626 and 624 are repeated until a satisfactory subset of pattern-metric pairs is selected. In step 628, the patterns of the final subset of pattern-metric pairs are assigned to be the signature patterns, and a matrix of the sensitivities of the signature patterns and their associated metrics to the process condition parameters is defined as the signature pattern matrix (SP matrix).
In another embodiment, the pattern matrix has more than one column per process condition parameter. For example, if derivatives of the sensitivities are computed, the pattern matrix may include one column for each process condition parameter at each specific value of the process condition parameter to distinguish which pattern-metric pairs are most sensitive to that process condition parameter across the range of values assumed for that process condition parameter. The final subset of pattern-metric pairs are then constructed to insure that changes in the metrics of the final set of pattern-metric pairs can be well resolved to determine the specific process condition parameter changes. This is especially useful if one of the patterns has a good response to a process condition parameter as its value changes in one direction, but not in the other. In this case, it would be valuable to include complementary patterns, one of which responds clearly to changes of either sign in the process condition parameter, thereby insuring complete process coverage over the full range of process condition parameters. Focus is a typical example of an process condition parameter where numerous patterns show a clearly one-sided response.
In step 914, wafers are processed using the lithography process and the mask to produce printed patterns on the wafer. In step 916, the metrics of the printed signature patterns on the wafer are measured according to the metrology recipe. In step 918, differences between the measured values of the metrics associated with the signature patterns and nominal values of the metrics are calculated to determine changes in the metrics. Optionally, previously-measured values of the metrics from previously-printed wafers may be used instead of the nominal values. The measured values of the metrics associated with the signature patterns may also be used to determine the critical dimension distribution across the exposure field of the exposure tool or across the entire wafer.
Then, in step 920, the equation A{right arrow over (M)}=SP*Δ{right arrow over (PC)} is solved to determine changes in the values of the process condition parameters that resulted in changes to the metrics, where Δ{right arrow over (M)} is a vector that includes the changes in the values of the metrics associated with the signature patterns, SP is the SP matrix, and Δ{right arrow over (PC)} is a vector that includes the changes in the values of the process condition parameters. Since the SP matrix is known, any changes in the values of the process condition parameters can be determined for any measured changes in the metrics associated with the signature patterns. There are many numerical methods in the literature to solve a matrix inversion problem, and any such numerical method is within the scope of the invention. In step 922, the changes in the values of the process condition parameters are provided to a lithography process control system. The
A distribution of the changes in the process condition parameters across a wafer can be correlated with wafer chip yield maps. Statistical analysis (e.g., ANOVA, i.e., ANalysis Of VAriations) can be used to extract information on, for example, which process condition parameter is the critical yield limiting factor or which drift or variation in certain process condition parameters are most highly correlated with certain signatures of yield fluctuation or excursions. These could become critical information in fab yield management and yield improvements.
The calculated changes in the values of the process condition parameter can also be used to adaptively adjust the metrology recipe. As changes in the process condition parameters are detected, additional measurements of the metrics associated with the signature patterns can be incorporated into the metrology recipe, either to measure the metrics at more locations across the field and/or across the wafer, or to measure additional signature patterns for added sensitivity to the process condition parameters that are beginning to show unacceptable drift. As additional data and/or corrective action are taken to improve the process control of the lithography process, the metrology recipe may be adaptively relaxed back to the minimum possible metrology burden.
The calculated changes in the values of the process condition parameters can also be used to enable model-based advanced process control (MBAPC) of the lithography process. In conventional control schemes for a wafer fab running multiple different products and processes, critical dimension drift is usually monitored and corrected on a product-by-product and layer-by-layer basis.
In the simplest scheme one can simply assume that all CD measurement drifts are due to exposure dose variation and change the exposure dose for all other layer/product combinations on exposure tool No. 1. Such schemes have been implemented, but if the true source of the CD measurement drift was not an exposure dose change, but rather focus, aberration, or other process condition parameter, the net result may be incorrect compensation and a degradation, rather than an improvement, in the CD performance of all product/layer combinations.
Using the signature patterns to determine changes in the process condition parameters can improve the effectiveness of advanced process control (APC) by correctly identifying the root cause of any observed CD measurement drift, thereby enabling the optimum exposure tool correction not just of the lot being measured, but of all subsequent lots of any product/layer combination processed on the same tool, as well as all subsequent lots of the same product/layer on other exposure tools. As shown in
Using the signature patterns to determine changes in the process condition parameters also allows for routine comparison between the process condition parameter changes on multiple exposure tools by identifying which tools are most prone to drift and in need of maintenance, which tools are closest to their optimum operating conditions and should be given priority for processing the most critical lots, which tools are most closely matched to one another to facilitate processing similar product layers on the most closely matched tools, and which tools are operating most closely to the conditions used in establishing the OPC and RET models used to create the layouts for the different products, thereby facilitating the orderly flow of production lots to the tools that will pattern those lots as closely as possible to the design intent.
Using the signature patterns to determine changes in the process condition parameters is also useful in implementing an improved MBAPC control system by removing or eliminating the effects of reticle manufacturing variations from the lithography process control system. In a conventional APC or statistical process control (SPC) system, it is often observed that certain masks produce better CD distributions and/or a higher yield of high value chips when exposed on one particular exposure tool, while another mask may produce higher yield and/or value when exposed on a different exposure tool. Given the limited amount of data available on CD distributions on the mask, the limited data available on the full pattern transfer process across the exposure field, and the difficulty in determining exactly which patterns vary on the chips to make the chips produced by one tool perform better than those produced by another tool, it is usually not possible to determine why one mask/tool combination should perform better than another.
The lithography process simulation and metrology method using the signature patterns described herein can enable a better understanding of the contribution of mask variations to CD and yield performance, and thereby facilitate improved MBAPC control. By determining the variations not just in the CD distribution of the metrology targets but of the process condition parameters, using the signature patterns to determine changes in the process condition parameters allows for faster identification of specific masks where the performance of the mask in terms of CD distributions, CD behavior of specific features, or specific metrics of pattern transfer does not meet expectations. As an example, and by illustration only, assume that a series of masks is exposed on the same exposure tool in succession and the metrology results collected on a set of signature patterns which may or may not be common to the different masks, but signature patterns produce the same calculated changes in process condition parameters. If the changes in process condition parameters for one of the masks is noticeably different than the changes in process condition parameters for the other masks, given that there was little time for the exposure tool to drift between the exposures, this would serve as a quick and effective identification of a problem with the quality of the one mask with different changes in process condition parameters. More information could then be collected for that mask to determine if it should be used in production or not, and, if it is to be used, a full chip simulation could help identify mask specific offsets in the process condition parameters to be applied to the exposures using that mask to produce the optimum CD and pattern transfer performance at the wafer level.
Using the signature patterns to determine changes in the process condition parameters is especially useful for products that are processed on an infrequent basis. In a conventional process control system, these infrequent lots would be exposed using a time weighted average of the previous exposure doses used for the same product/layer on a given exposure tool, even though there may have been extensive changes to the tool since the last time a lot of that product/layer was processed. In more advanced approaches, the exposure dose may be adjusted based on the average change of all other recently processed lots of similar product/layers on the same tool. However, the choice of what constitutes a "similar" layer is often based on empirical results (a limited history showing similar CDs at similar times in the past), or a subjective sense on the part of the person directing the production flow or writing the rules for an automated flow control system. Often the creation of groups of "similar" product layers is determined based on the design rules or technology used for the particular design with no knowledge of how the mask manufacturing errors differ from mask to mask.
Using the signature patterns to determine changes in the process condition parameters can improve these process control approaches in a number of ways. First, the question of what constitutes a "similar" product/layer can be answered rigorously, not subjectively. Using the full chip simulation system and the signature patterns, incoming circuit designs could be analyzed and automatically rated on their sensitivity to variations of the different process condition parameters. Designs whose simulated metrics have similar sensitivities to the process condition parameters could be grouped together and SPC or APC control algorithms could be used to treat them as a group. In this manner, even if a particular mask that belongs to such a group is not used for a period of time, the optimum process conditions to use for that mask would still be known from the performance of the other members of the group. In addition, above and beyond the improvement obtained by better classification into similar groups, the corrections to be applied to the exposure tool would be greatly improved because the user could determine not just a time averaged exposure dose offset, but an exposure dose offset appropriate to the known changes in the full range of process condition parameters determined from all other products that had been processed since the last time the particular mask in question had been used. Thus, if a particular aberration of the projection lens or illumination system had been known to have drifted, a full chip simulation or a critical portion thereof could be quickly recomputed and new optimum settings of the adjustable process condition parameters can be determined based on the complete configuration of all of the process condition parameters.
The process condition parameters computed from measured changes in metrics associated with the signature patterns can also be used to feed forward corrections to an etch process or other subsequent process steps. For example, even if the measured and/or simulated CDs are within specification, if the slope of the resist features is incorrect due to focus offsets or other aberrations, the final width of the etched structure will be incorrect as well. Although an out-of-specification resist pattern on a wafer can be cleaned (stripped) and reworked, once the pattern is etched into the underlying layer, no further correction is possible, and the entire wafer, possibly even the entire wafer lot, may have lower than acceptable yield and may even need to be scrapped. For this reason, feed forward corrections to the etch process are very valuable.
The process condition parameters computed from measured changes in metrics associated with the signature patterns allow the lithography process control system to comprehend not just the resist CDs, but also how those CDs will transfer through the etch process. The correlation between focus and resist sidewall angle, and the correlation between resist sidewall angle and the final etched CD, is well known, and can be predicted by empirical lookup tables or models of the etch process that are well documented in the literature. The full chip simulation system disclosed in U.S. Pat. No. 7,003,758 and described below in conjunction with
Front-end processing system 1314 b includes a front-end processing device 1340 which is suitably programmed to handle or perform direct interaction with the user or operator (i.e., the "outside world") via, for example, client computer(s) (not illustrated) that provide operator or user access to system 1300 for job setup and/or results review/analysis. A front-end SCSI RAID hard-disk array 1338 b, associated with front-end processing device 1340 should be a high capacity storage device, since front-end. SCSI RAID 1338 b is used to store results and images of many simulation jobs. Front-end processing system 1314 b also communicates with application processing system 1314 a, to provide or retrieve data to or from application SCSI RAID 1338 a (for example, the design database), and instructs application processing system 1314 a to start a job, as instructed by the user or operator.
Application processing system 1314 a and front-end processing system 1314 b connect with accelerator system 1316, for example, through high speed switches (for example, gigabit-Ethernet switches 1342 a and 1342 b). Switches 1342 a and 1342 b may be Dell 5224 Power Connect, manufactured and provided by Dell Computer (Austin, Tex., USA). The implementation and operation of the Dell 5224 Power Connect are described in detail in application notes, technical/journal articles and data sheets, all of which are incorporated by reference herein.
In one embodiment, all or substantially all of the actual computationally intensive tasks of lithography simulation may be conducted by accelerator system 1316, and, in particular, one or more accelerator components 1316 a-n. This architecture allows scalable computation capacity, by changing the number of accelerator hardware components 1316 a-n. Moreover, this architecture also enables or enhances overall fault-tolerance of system 1300. For example, should a given accelerator hardware component 1316 a-n fail, its jobs may be re-assigned to the other accelerator hardware components 1316 a-n, and, in this way, system 1300 maintains its operational condition/state.
In particular, accelerator system 1316 may include one or more accelerator components 1316 a-n, each having one of microprocessor subsystem 1344 a-n (including one or more microprocessors), one or more accelerator subsystems 1346 a-n, and local or resident memory storage 1348 a-n coupled to an associated microprocessor subsystem 1344 a-n. The extent or amount of hardware acceleration capability may be balanced with microprocessor subsystems 1344 a-n, depending on the extent or amount of computation to be performed.
In one embodiment, microprocessor subsystems 1344 a-n each includes two Xeon microprocessors manufactured by Intel (Santa Clara, Calif., USA). The accelerator subsystems 1346 a-n each includes a plurality of Application-Specific Integrated Circuit (ASIC), special-purpose DSP integrated circuits, and/or programmable gate arrays (for example, field-programmable gate arrays ("FPGAs")). In fact, each of accelerator subsystems 1346 a-n may include multiple accelerator subsystems, for example, accelerator subsystem 1346 a may include all the accelerator subsystems 1346 a 1-6 ax, as illustrated in
A bus 1350 a-n facilitates high-speed communication between microprocessor subsystem 1344 a-n and associated accelerator subsystem(s) 1346 a-n. The communication protocols and techniques on bus 1350 a-n may be PCI, PCIX, or other high-speed communication protocols and techniques. Indeed, any high-speed technique, whether now known or later developed, may be implemented over bus 1350 a-n. Notably, in one embodiment, the bus interface may be implemented using a 21P100BGC PCI-X bridge (64 bit/133 MHz) from International Business Machines Corporation (Armonk, N.Y., USA). The implementation and operation of the 21 P100BGC are described in detail in application notes, technical/journal articles and data sheets, all of which are incorporated by reference herein.
In one embodiment, computations that are performed by be accelerator subsystems 1346 a-n include, for example, anti-aliasing filtering and down-sampling, Fast Fourier Transforms for aerial image computation, image filtering and/or thresholding operations in resist modeling. The computations that are performed by microprocessor subsystems 1344 a-n include, for example, polygon-to-binary bitmap conversion and application programs or processes (e.g., RET verification). The partitioning of computing tasks between microprocessor subsystem 1344 a-n and accelerator subsystems 1346 a-n is application-dependent and may vary from application to application or job to job.
The invention has been described above with reference to specific embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
|Cited Patent
|Filing date
|Publication date
|Aug 31, 1999
|Jul 2, 2002
|Advanced Micro Devices, Inc.
|Technique to separate dose-induced vs. focus-induced CD or linewidth variation
|Sep 4, 2001
|Aug 6, 2002
|Accent Optical Technologies, Inc.
|Determination of center of focus by diffraction signature analysis
|Dec 13, 2001
|Nov 4, 2003
|Yield Dynamics, Inc.
|System and method for controlling critical dimension in a semiconductor manufacturing process
|Jan 28, 2002
|Jan 6, 2004
|Kla-Tencor Corporation
|Method and apparatus for the production of process sensitive lithographic features
|Jan 22, 2003
|Sep 14, 2004
|Hitachi, Ltd.
|Process conditions change monitoring systems that use electron beams, and related monitoring methods
|Apr 3, 2002
|Sep 21, 2004
|Asml Netherlands B.V.
|Lithographic manufacturing process, lithographic projection apparatus, and device manufactured thereby
|Jan 17, 2001
|Oct 12, 2004
|International Business Machines Corporation
|Focus control system
|Apr 18, 2002
|Jun 21, 2005
|Hitachi, Ltd.
|Method and system for monitoring a semiconductor device manufacturing process
|Feb 18, 2003
|Jul 5, 2005
|Hitachi High-Technologies Corporation
|Method of observing exposure condition for exposing semiconductor device and its apparatus and method of manufacturing semiconductor device
|Jul 20, 2004
|Aug 16, 2005
|Hitachi High-Technologies Corporation
|Method of monitoring an exposure process
|Apr 1, 2004
|Feb 21, 2006
|Brion Technologies, Inc.
|System and method for lithography simulation
|Sep 4, 2001
|May 2, 2002
|Dietmar Ganz
|Method of adjusting a lithographic tool
|Jan 17, 2004
|Sep 30, 2004
|Kla-Tencor Corporation
|Method for process optimization and control by comparison between 2 or more measured scatterometry signals
|Oct 10, 2002
|Nov 11, 2004
|Littau Michael E.
|Determination of center of focus by cross-section analysis
|A.K.K. Wong "Resolution Enhancement Techniques in Optical Lithography" SPIE Press, Bellingham, WA, vol. TT47, ISBN 0-8194-3995-9 (2001).
|Allgair et al. "Characterization of Optical Proximity Correction Features" Proc. SPIE vol. 4344, pp. 200-207 (2001).
|H.J. Levinson "Lithography Process Contol" SPIE Optical Engineering Press, Bellingham, WA, vol. TT28, ISBN 0-8194-3052-8 (1999).
|T. Brunner et al. "Impact of Resist Blur on MEF, OPC, and CD Control" Proc. SPIE vol. 5377, pp. 141-149 (2004).
|V. Wiaux "Assessment of OPC Effectiveness Using Two-Dimensional Metrics," Proc. SPIE, vol. 4691, pp. 395-406 (2002).
|V.N. Mahajan "Aberration Theory Made Simple" SPIE Optical Engineering Press, Bellingham, WA, vol. TT06, ISBN 0-8194-0536-1 (1991).
|Citing Patent
|Filing date
|Publication date
|Jun 12, 2012
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|Jun 19, 2012
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|May 29, 2009
|Jun 26, 2012
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|May 29, 2009
|Sep 4, 2012
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|May 29, 2009
|Oct 2, 2012
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|Sep 23, 2011
|Nov 27, 2012
|Asml Netherlands B.V.
|Process window signature patterns for lithography process control
|Dec 11, 2012
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|Nov 29, 2010
|Feb 26, 2013
|Luminescent Technologies, Inc.
|Virtual photo-mask critical-dimension measurement
|Jun 4, 2013
|Luminescent Technologies, Inc.
|Photo-mask acceptance technique
|Jun 11, 2013
|Luminescent Technologies, Inc.
|Extending the field of view of a mask-inspection image
|Jan 26, 2011
|Jul 30, 2013
|International Business Machines Corporation
|Optical proximity correction verification accounting for mask deviations
|Feb 4, 2011
|Oct 8, 2013
|Luminescent Technologies, Inc.
|Technique for analyzing a reflective photo-mask
|Jan 26, 2011
|Nov 5, 2013
|International Business Machines Corporation
|Diagnosing in-line critical dimension control adjustments using optical proximity correction verification
|May 27, 2011
|Nov 19, 2013
|Nikon Corporation
|Method or matching high-numerical aperture scanners
|Feb 9, 2011
|Dec 17, 2013
|Luminescent Technologies, Inc.
|Technique for repairing a reflective photo-mask
|Nov 24, 2010
|Dec 31, 2013
|International Business Machines Corporation
|Determining lithographic set point using optical proximity correction verification simulation
|Sep 19, 2007
|Feb 4, 2014
|Luminescent Technologies, Inc.
|Photo-mask and wafer image reconstruction
|Jul 13, 2011
|Feb 18, 2014
|Luminescent Technologies, Inc.
|Electron-beam image reconstruction
|Apr 1, 2013
|Sep 9, 2014
|Asml Netherlands B.V.
|Method for process window optimized optical proximity correction
|Feb 11, 2013
|Apr 14, 2015
|Dino Technology Acquisition Llc
|Technique for repairing a reflective photo-mask
|Mar 11, 2013
|Jul 28, 2015
|Kla-Tencor Corporation
|Multistage extreme ultra-violet mask qualification
|Feb 23, 2011
|Sep 15, 2015
|Carl Zeiss Sms Ltd.
|Critical dimension uniformity correction by scanner signature control
|May 29, 2009
|Jan 28, 2010
|Preil Moshe E
|Photo-Mask and Wafer Image Reconstruction
|May 29, 2009
|Jan 28, 2010
|Preil Moshe E
|Photo-Mask and Wafer Image Reconstruction
|May 29, 2009
|Jan 28, 2010
|Preil Moshe E
|Photo-Mask and Wafer Image Reconstruction
|May 29, 2009
|Apr 8, 2010
|Preil Moshe E
|Photo-Mask and Wafer Image Reconstruction
|May 29, 2009
|May 13, 2010
|Preil Moshe E
|Photo-Mask and Wafer Image Reconstruction
|Aug 11, 2011
|Linyong Pang
|Extending the Field of View of a Mask-Inspection Image
|Jan 26, 2012
|Asml Netherlands B.V.
|Process Window Signature Patterns for Lithography Process Control
|May 27, 2011
|Feb 16, 2012
|Nikon Corporation
|Method for matching high-numerical aperture scanners
|Jul 26, 2012
|International Business Machines Corporation
|Optical proximity correction verification accounting for mask deviations
|Feb 23, 2011
|Mar 28, 2013
|Ofir Sharoni
|Critical dimension uniformity correction by scanner signature control
|U.S. Classification
|430/5, 382/145, 257/48, 382/149, 382/147, 430/30
|International Classification
|Cooperative Classification
|European Classification
|Apr 23, 2010
Owner name: ASML NETHERLANDS B.V.,NETHERLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRION TECHNOLOGIES, INC.;REEL/FRAME:024278/0346
Effective date: 20100416
Owner name: ASML NETHERLANDS B.V., NETHERLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRION TECHNOLOGIES, INC.;REEL/FRAME:024278/0346
Effective date: 20100416
|May 7, 2015
|Fee payment
Year of fee payment: 4


text:
Affluent Lifestyle Guide
You might like Best Runway Models >
Check out this fantastic brick-for-brick remake of the third trailer from Christopher Nolan's The Dark Knight Rises. The clip above was made by the very talented people over at ParanickFilmz, Jedimastersoda and Adviceversas. Job well done. Which trailer would you like to see remade with…
Watch 'The Dark Knight Rises' Trailer 3 in LEGO is a post by Brian Farmer on Highsnobiety.