text:
|Numéro de publication
|Type de publication
|Numéro de demande
|Date de publication
|16 mars 2004
|Date de dépôt
|14 juin 2001
|Date de priorité
|14 juin 2001
|État de paiement des frais
|Numéro de publication
|Kenneth H. Potter, Trevor Garner
|Cessionnaire d'origine
|Cisco Technology, Inc.
|Exporter la citation
|BiBTeX, EndNote, RefMan
|Citations de brevets (8), Référencé par (13), Classifications (9), Événements juridiques (4)
|Liens externes: USPTO, Cession USPTO, Espacenet
This invention relates generally to nodes of computer networks and, more specifically, to improving the efficiency of storing packets in the nodes' computer memories by eliminating the need for additional read-modify-write (RMW) operations.
A computer network is a geographically distributed collection of interconnected subnetworks for transporting data between nodes, such as intermediate nodes and end nodes. A local area network (LAN) is an example of such a subnetwork; a plurality of LANs may be further interconnected by an intermediate network node, such as a router or switch, to extend the effective "size" of the computer network and increase the number of communicating nodes. Examples of the end nodes may include servers and personal computers. The nodes typically communicate by exchanging discrete frames or packets of data according to predefined protocols. In this context, a protocol consists of a set of rules defining how the nodes interact with each other.
Each node typically comprises a number of basic subsystems including a processor, a main memory and an input/output (I/O) subsystem. Data is transferred between the main memory ("system memory") and processor subsystem over a memory bus, and between the processor and I/O subsystems over a system bus. Examples of the system bus may include the conventional lightning data transport (or hyper transport) bus and the conventional peripheral component [computer] interconnect (PCI) bus. The processor subsystem may comprise a single-chip processor and system controller device that incorporates a set of functions including a system memory controller, support for one or more system buses and direct memory access (DMA) engines. In general, the single-chip device is designed for general-purpose use and is not heavily optimized for networking applications.
In a typical networking application developed using the single-chip device, packets are received from a framer, such as an Ethernet media access control (MAC) controller, of the I/O subsystem attached to the system bus. A DMA engine in the MAC controller is provided a list of addresses (e.g., in the form of a descriptor ring in a system memory) for buffers it may access in the system memory. As each packet is received at the MAC controller, the DMA engine obtains ownership of ("masters") the system bus to access a next descriptor ring to obtain a next buffer address in the system memory at which it may, e.g., store ("write") data contained in the packet. The DMA engine may need to issue many write operations over the system bus to transfer all of the packet data.
For example, assume the system memory comprises double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices and that a portion of the memory is organized into packet buffers at system initialization. These buffers are defined to start on certain binary boundaries (e.g., 32 bytes) in order to take advantage of the system bus burst size, bus alignment and cache line size. Assume also that the system (PCI) bus has a width of 32 (or 64) bits and system memory accessed over the bus is also 32 (or 64, respectively) bits wide thereby matching the bus. Moreover, each access (transfer) of data over the system bus to the memory comprises two cycles (or four half cycles). Therefore, at 32 (64) bits per half cycle, the minimum transfer size of packet data over the system bus is 16 (32) bytes (that is 4 bytes per half cycle times 4 half cycles equals 16 bytes).
Continuing the same example, in order to write 40 bytes of data to an address, e.g., 0x100038 in system memory, 10 half cycles are needed over a 32-bit (4 byte wide) system bus. However, to write 40 data bytes to system memory address 0x100037, 11 half cycles would be required (i.e., the first half cycle with 1 byte of data, 9 half cycles with 4 bytes and the last half cycle with 3 bytes). By aligning the buffer start address with the width of the system bus, efficient use of that bus is ensured. This same efficiency carries over to the actual system memory interface, where the data can be written into the system memory using the fewest cycles if the start of the buffer matches the granularity of accesses to the system memory. From a simplistic point of view with respect to the system memory, if a memory line is 32 bits or 4 bytes wide (herein a memory "line" includes the typical data storage word and any error correcting code extension to that word, if any), usually the entire line must be fetched in order to over write only one byte while preserving the other three bytes. So, in the above example [the system] , to store the 40 bytes, the system will write to 10 full width lines when starting at address 0x100038 because the memory line width and the message length match 10 complete, full memory lines exactly. However, if the starting address is 0x100037, the first byte of the 40 will be stored in the last byte of a 4 byte wide first line, and the last three bytes of the 40 being stored will be stored in the first three bytes of the 4 byte wide eleventh line. Now if the last three bytes were modified, the entire four bytes must be fetched and the first three bytes modified while keeping the last byte intact (assuming it is part of another message, etc.); that is, a read-modify-write (RMW) operation must be used for changing the last three bytes. A similar operation must be used to modify the first byte of the stored 40-byte message. In this case the inefficiencies of the non-aligned memory are seen in the need to access eleven, rather than ten bytes, and the need for read/modify/write operations, rather than simple write operations.
The present invention becomes even more important for large packet memories incorporating error correction codes (ECC). In these memories, it is not feasible to provide byte-write capability since the ECC covers the entire widths of the memories. For example, assume the system memory, including a system memory bus interface, is arranged to accommodate a 64-bit memory "line" width. Eight (8) additional bits are needed for ECC computation by the system memory controller such that the memory and memory bus interface are organized and aligned on 72-bit line widths. Therefore, a non-aligned start address not only could cause an extra write cycle but also the inefficient RMW operation discussed herein.
By starting the packet buffers on appropriate binary boundaries, the inefficiencies of writing packet data to the beginning of the buffers are avoided. However, there is no equivalent "work around" in conventional systems when writing the end of the packet buffers in system memory. For example, if the effective memory width is 8 bytes and the length of a packet is 63 bytes, the last transfer of the packet over the system bus requires that only 7 bytes be written to the appropriate packet buffer. As noted, the processor and system controller device is general-purpose and, accordingly, does not "know" that the portion of memory is reserved solely for packet buffers. Therefore, the processor and system controller device strictly interpret the system bus operation using a RMW operation to preserve the one byte location of the buffer that was not written with the packet data, rather than "padding out" (e.g., writing null values) to that location. This represents an inefficient use of system resources and the present invention is directed to a technique that improves the efficiency of such resources
As noted, the RMW operation is quite expensive and consumes substantial over-head with respect to "turning around" the memory bus when writing data into an allocated buffer. That is, not only does the RMW operation double the traffic over the memory bus (by both reading and writing the data block), it also consumes overhead with respect to gaining access/ownership of the memory bus in order to avoid collisions over that bus. Therefore, not only is the operation expensive in terms of resource consumption, but it also adversely (and substantially) impacts throughput over the bus. Accordingly, the present invention is directed to improving the efficiency of memory write operations to buffers within a packet memory of an intermediate network node.
The present invention comprises a mechanism for instructing a memory controller with respect to the performance of a write operation directed to a system memory of an intermediate network node. The memory controller is preferably embodied within a single-chip processor and system controller device having bus interface logic coupled to a system bus of the node. The bus interface logic includes conventional base address registers configured to decode addresses from system bus requests initiated by a media access control (MAC) controller coupled to a system bus. The base address registers are then used to determine those resources (e.g., lines of the system memory) targeted by the requests, such as the write operation.
According to the present invention, the mechanism comprises a novel attribute, e.g., a bit, added to each base address register. Depending upon an application executing on the processor, the attribute bit may be configured to one of two states, each of which specifies a mode of operation. In a first state, the bit may be configured to indicate that a partial write operation to a memory line within the system memory should be enforced exactly as specified by the system bus request, thereby resulting in a read-modified-write (RMW) operation described before. Alternatively, a second state of the bit may be configured to indicate that the partial write data be "padded out" to thereby overwrite, e.g., the entire memory line.
For example, assume the MAC controller issues a 7-byte write operation to the memory controller that is directed to an address 0x100030 in the system memory. If the bit is configured to specify overwriting of the memory line, the memory controller pads the data by one additional byte (at the end of the data), computes an error correction code for the entire 8 bytes and issues a single direct write operation to the 8-byte wide memory line. Similarly, assume the MAC controller issues a 6-byte external bus (write) request to the memory controller that is directed to address 0x100032. If the attribute is configured to specify overwriting of the memory line, the memory controller pads the data by 2 additional bytes starting at address 0x100030 (at the beginning of the data), computes an error correction code for the entire 8 bytes and issues a direct write operation to the 8-byte wide memory line. Although these operations destroy the previous contents of the byte at address 0x100037 (and of the bytes at addresses 0x100030-0x100031) within the packet buffer, the application did not intend to use those bytes anyway. The tradeoff is between using more memory than needed to store messages, as in the present invention, but providing the advantage of not requiring RMW operations.
In certain cases, it may desirable to allow a particular memory region (buffer) to be operated on in both modes. Here, the MAC controller may pad out a system bus request to fill a packet buffer with original packet data to thereby avoid a RMW operation. However, the application executing on the processor may require manipulation of a packet header and, thus, not want to destroy any packet data. To accomplish these objectives, the memory can be "dual-mapped" to a virtual address space using two sets of base address registers. Both sets of registers may reference the same memory address, but one set has the novel bit configured in the first state and the other has the novel bit configured in the second state. Alternatively, the novel bit can come directly from a high order bit of the address specified in the write operation. As a result, the present invention advantageously increases the efficiency of writing packet data to system memory, particularly for small packet sizes.
The above and further advantages of the invention may be better understood by referring to the following description in conjunction with the accompanying drawings in which like reference numbers indicate identical or functionally similar elements:
FIG. 1 is a block diagram of a computer network comprising a collection of inter-connected subnetworks and nodes, including an intermediate network node;
FIG. 2 is a schematic block diagram of an illustrative intermediate network node having a packet memory that may be advantageously used with the present invention;
FIG. 3 is a schematic block diagram illustrating the organization of the packet memory; and
FIG. 4 is an illustration of the format of a base address register including a novel attribute in accordance with the present invention.
FIG. 1 is a block diagram of a computer network 100 comprising a collection of interconnected subnetworks and nodes. The nodes may comprise computers including end nodes 105, such as a sending end node 102 and a receiving end node 106, and an intermediate network node 200, the latter of which may be a switch or router. The subnetworks 104, 108 included within network 100 are preferably local area networks (LANs) interconnected by the intermediate node 200, although the networks may comprise other communication links, such as wide area networks. Communication among the nodes coupled to the LANs is typically effected by exchanging discrete packets 110 among the nodes.
For example, the sending node 102 generates a data packet 110 by encapsulating "payload" data within headers, such as conventional data link and network layer headers, as the data passes through different layers of a protocol stack. The packet is then transmitted over the network to the intermediate node 200, which facilitates the flow of the data packet through the network by routing it to the proper receiving node 106. Specifically, the node 200 receives the packet from an input interface, parses the data link and network layer headers, renders a forwarding decision for the packet, appends a new data link header to the packet and then transmits the packet to an output interface.
The present invention is directed to efficiently moving packet data from interfaces of a node to a system memory coupled to a processor subsystem of the node. Although the present invention is described herein using an illustrative intermediate network node, it will be apparent to those skilled in the art that the invention may apply to any node, including an end node. General-purpose processor subsystems are typically not optimized for networking application environments. The invention adds functionality to a general-purpose processor subsystem that increases the efficiency of the node when executing network applications. The general-purpose processor subsystem is typically configured to perform more than just networking applications, i.e., more than "pushing" packets in and out of system memory. Consequently, when the general-purpose processor subsystem performs such networking applications, the performance of the node may suffer.
FIG. 2 is a schematic block diagram illustrating an intermediate network node 200 that may be advantageously used with the present invention. The intermediate network node comprises a main memory subsystem ("system memory 210") coupled to a processor subsystem 230. In the illustrative embodiment, the processor subsystem 230 comprises a processor 232 and system controller 234 integrated onto a single "chip" device. The single-chip device further includes a memory controller 236 coupled to the system memory 210 via a memory bus 220.
The system controller 234 is connected to a system bus 240, such as the conventional peripheral component [computer] interconnect (PCI) bus which, in turn, [couples] to communication devices, such as media access control (MAC) controllers 250. Examples of the MAC controllers include Ethernet, High level Data Link Control (HLDC) or other similar communications controllers, known in the art, that are adapted to transmit and receive packet data to and from computer networks. For example, packet data may be received at a physical interface 252 of the controller that is attached to a computer subnetwork 104 in FIG. 1. The controller then moves that received data over the system bus 240 to the memory controller 236, where the data is forwarded over the memory bus 220 and onto a portion of the system memory 210 organized as a packet memory 300.
The system memory 210 comprises storage locations addressable by the processor for storing software programs and data structures associated with the invention described herein. An operating system, portions of which are typically resident in memory and executed by the processors, functionally organizes the intermediate node by, inter alia [inter alia,] invoking network operations in support of software processes executing on the node. It will be apparent to those skilled in the art that other memory means, including various computer readable media, may be used for storing and executing program instructions pertaining to the described mechanism and technique.
FIG. 3 is a schematic block diagram illustrating the organization of the packet memory 300. The packet memory may be apportioned into a plurality of fixed sized buffers 310, e.g., 512-byte packet buffers. These fixed sized buffers are generally aligned on binary boundaries (e.g., 32-bytes) in order to take advantage of burst sizes over the system and memory buses, bus alignments and, e.g., cache lines. It should be noted, however, that the size of the buffers may be arranged to accommodate [, e.g.,] a worst-case packet size.
Often, a beginning portion of the buffer is reserved as a "header expansion" portion 302 in the event additional information may be added to the packet data moved into that buffer 310. For example, software executing on the processor processes the packet data by, e.g., removing an original header associated with the packet and inserting a new modified header onto the packet. In the event the new modified header expands ("grows") with respect to the original header, the header expansion portion 302 of the buffer is available to accommodate the expanded packet header. Another example of the use of the header expansion portion 302 that applies to an end node is for packet header decompression, which causes the header to grow. Thus, when a packet initially arrives at the buffer 310 of the packet memory 300, the packet is loaded ("written") into a main portion 306 of the buffer adjacent to the header expansion portion 302. The size of the buffer portion 302 is usually determined by the processor subsystem; however, if that size is not aligned on a binary boundary, then performance issues may arise as discussed herein.
In the illustrative embodiment, the memory bus 220 coupling the memory controller 236 to the packet memory 300 is preferably a 64-bit data bus that provides a standard memory interface width. For every 64-bits of data presented over this interface, an 8-bit error correction code (ECC) is computed by the memory controller and stored with the data. Therefore, the (buffer) memory is typically organized into 72-bit wide memory "lines." If it is desired to modify only a portion of a memory line data, a read-modify-write (RMW) operation must be executed. Broadly stated, execution of the RMW operation results in (i) retrieving (reading) the entire memory line data, (ii) modifying the portion of the data, (iii) computing a new ECC value for the entire modified data and (iv) storing (writing) the modified data back into the memory line.
Instead of accessing a single memory line in the packet memory 300, the subsystems are typically configured to enable access: to multiple lines within the memory. For example)to efficiently operate a memory controller, data is transferred over the memory bus in multiple cycle "bursts." Bursts are memory cycles that are used exclusively to write data to or read data from a number of usually contiguous memory locations without allowing other processes to access the memory at all. This is particularly true for double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices, where transfers (accesses) of data to and from these devices generally comprise 2 cycles (or 4 half cycles). That is, data is accessed at the memory devices on both the rising and trailing edges of a clock signal. Therefore 4 half cycles, each comprising 64 bits, result in a 32-byte burst transfer over the memory interface. (Note that each half-cycle transfer of data includes an 8-bit ECC such that, for a 64-bit memory interface data path, a 72-bit wide interface is required.) Accordingly, a general-purpose packet controller is typically configured with a minimum transfer size of 32 bytes.
As noted, the RMW operation may be used to modify only a portion (e.g., a 64-bit or 8-byte portion) of the 32-byte burst. Yet, the RMW operation is expensive in terms of the resources, e.g., time and memory bandwidth, needed to execute that operation. Therefore, it is generally desirable to avoid performing byte-oriented operations on packet data. However, when a MAC controller "pushes" packets received at its physical interface to an allocated buffer in the packet memory, the memory controller may need to utilize a RMW operation. For example, if the header expansion portion 302 at the beginning of the buffer 310 does not end on a 32-byte boundary, the beginning of the main portion 306 of the buffer will reside in the same 32-byte area as the end of the header expansion portion. As a result, the memory controller must read the 32-byte "block," modify the portion where the packet is to be written, and then write the modified block back into the buffer.
Since the header expansion portion of the buffer does not yet contain any useful information, this represents an unnecessary use of the expensive RMW operation. To alleviate this situation, most subsystems allocate the main portion to an aligned (e.g., 32-byte) boundary in memory. However, this approach cannot be applied to the end of the packet transfer, primarily because the memory controller is part of a general-purpose processor subsystem. That is, in response to a request to write only a beginning portion of a 32-byte block to complete the packet transfer, the controller strictly interprets the request and performs a RMW operation, even though the remaining trailing portion 304 of the buffer is currently unused and does not contain any useful information that needs to be preserved.
FIG. 4 is an illustration of the format of a base address register 400, including an attribute portion, often one bit in size. Each base address register 400 includes an address field 410 and a mask field 420 that cooperate to specify the defined address range. For example, if the address is "1EA000" and the mask is "FFF0000", then the defined address range is anywhere between address 1EA0000 and 1EAFFFF. This defined address range is the area of the packet memory that is decoded by the registers. The base address register provides an offset or base address that is enabled by the mask. The lower order bits of the physical packet memory being addressed are appended to the base address. This and other equivalent operations and manipulations using base addresses and/or masks servicing as offsets to specific memory addresses are well known in the art. The present invention adds a field to the base address register containing the novel attribute 450 that is configurable by the processor. The attribute 450 represents the status information that specifies whether the RMW operation is enforced on the specified address range that, in the illustrative embodiment, is essentially the packet memory portion of system memory "carved out" with the allocated buffers. Within that specified address range of allocated buffers, the processor may configure the attribute to a state that indicates, e.g., "no RMW."
In the illustrative embodiment, there is a plurality of base address registers that specify different address ranges, wherein each register may specify a different attribute state. The base address register maps an address as viewed on the system bus into an address within the system (packet) memory. Whereas one base address register may specify an address range with the attribute asserted to indicate "no RMW," another base address register may specify an address range with the attribute de-asserted to "enable RMW" operations to that range. Therefore, the novel attribute 450 may be configured to a first state denoting that a partial write operation to a memory line within a specified address range should be enforced exactly as specified by a bus request from a MAC controller, thereby resulting in the RMW operation. Alternatively, the attribute may be configured to a second state to denote that partial write data may be "padded out" to thereby overwrite, e.g., the entire memory line. This aspect of the inventive mechanism provides control by the processor over the mode of operation issued by the memory controller to the packet memory.
For example, assume the MAC controller issues a 7-byte external bus request (e.g., a write operation) to the memory controller that is directed to an address 0x00030 in the system memory. If the novel attribute bit 450 is configured to specify overwriting of the memory line, the memory controller pads the data by one additional byte (at the end of the data), computes an error correction code for the entire 8 bytes and issues a direct write operation to the 8-byte wide memory line. Similarly, assume the MAC controller issues a 5-byte external bus (write) request to the memory controller that is directed to address 0x100033. If the attribute 450 is configured to specify overwriting of the memory line, the memory controller pads the data by 3 additional bytes (at the beginning of the data) starting at address 0x100030, computes an error correction code for the entire 8 bytes and issues a direct write operation to the 8-byte wide memory line. Although these operations destroy the previous contents of the byte at address 0x100037 (and of the bytes at addresses 0x100030-0x100032) within the packet buffer, the application executing on the processor did not intend to use those bytes anyway, and the bytes cannot be directly used to store bytes from another packet.
Referring again to FIG. 2, a data structure or table, such as a descriptor ring 212, is present in another portion of system memory 210 to instruct the MAC controller 250 as to the address of an available buffer in the packet memory. The descriptor ring includes a plurality of entries 215, each of which includes a pointer 214 (buffer address) and, possibly, a length of the buffer along with an ownership bit 216. The ownership bit 216 is asserted to indicate ownership of the buffer address by either the processor or the controller. The MAC controller typically "walks" the entries 215 of the descriptor ring 212 searching for buffer addresses having the ownership bit that indicates ownership by the controller. Thus, the descriptor ring is used to pass an available buffer address to the controller.
In accordance with an aspect of the present invention, the address loaded into the entry of the descriptor ring having the ownership bit asserted to indicate ownership by the MAC controller is contained within the address range specified in a base address register. The controller thus accesses the descriptor ring to retrieve the address of a buffer at which it may transfer data of a specified length, while the system (memory) controller accesses the base address register to determine the state of the novel attribute. Depending upon that state, the memory controller is instructed to enable or suppress the RMW operation for that external bus request.
Advantageously, the invention improves the efficiency of the node because it enables use of commercially available communication [(MAC)] controllers (MAC controllers) in a manner that reduces the overhead associated with partial write operations to packet memory without having to modify those controllers. For example, the invention allows the communications controller to optimize transfers over the system bus such that a 32-byte data burst is performed over the bus even though only 27 bytes is actually required by the request. Here, the processor provides the communications controller with the address of the allocated buffers within the packet memory utilizing the base address register having the novel attribute configured to indicate no RMW operations. Use of the "no RMW" attribute state in this instance allows the additional 5 bytes of information to be written into the targeted packet buffer locations because the integrity of the data stored at those locations is not at issue. Notably, the attribute is configured by the processor and interpreted only by the system (memory) controller, and thus it does not impact the system beyond the intermediate node processor and its packet memory.
In certain cases, it may desirable to allow a particular memory region (buffer) to be operated on in both modes. Here, the MAC controller may pad out a system bus request to fill a packet buffer with original packet data to thereby avoid a RMW operation. However, the application executing on the processor may require manipulation of a packet header and, thus, not want to destroy any packet data. To accomplish these objectives, the memory can be "dual-mapped" to a virtual address space using two sets of base address registers. Both sets of registers may reference the same memory address, but one set has the novel bit configured in the first state and the other has the novel bit configured in the second state.
For example, assume an entry of the descriptor ring 212 is updated to indicate ownership by the processor. In this case, the descriptor ring is in the same address range as the allocated buffers of the system memory. However, the entry may not be 32 bytes in length and, as such, the RMW operation is required with respect to this entry. Accordingly, the processor provides the actual address of the entry of the descriptor ring to the communications controller utilizing the base address register having the novel attribute configured to enable RMW operations to that address. If the attribute was configured to specify no RMW operation, then a 32-byte write operation to the descriptor ring would destroy entries beyond the particular entry targeted for update, thereby adversely affecting system performance. Thus, the invention enables selective suppression of RMW operations to the system memory.
While there has been shown and described an illustrative embodiment for instructing a memory controller with respect ;to the performance of a write operation directed to a system memory using the novel attribute within a base address register configured to provide mapping of addresses to the memory, it is to be understood that various other adaptations and modifications may be made within the spirit and scope of the invention. For example, the novel attribute may be embodied within other entities such as a memory management unit. In another specific embodiment, the attribute could simply be defined as a high order address bit that is not needed to select locations within the real memory. That is, the attribute may be provided as a high order address bit that is not part of the address decode indicating the mode to be used when writing memory. This latter embodiment must be implemented with care. As a result, the present invention advantageously increases the efficiency of writing packet data to system memory, particularly for small packet sizes.
The foregoing description has been directed to specific embodiments of this invention. It will be apparent, however, that other variations and modifications may be made to the described embodiments, with the attainment of some or all of their advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.
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Owner name: CISCO TECHNOLOGY, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:POTTER, KENNETH H.;GARNER, TREVOR;REEL/FRAME:011905/0158
Effective date: 20010613
|20 aoűt 2007
|Fee payment
Year of fee payment: 4
|16 sept. 2011
|Fee payment
Year of fee payment: 8
|16 sept. 2015
|Fee payment
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text:
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The Court of Appeal has confirmed that if a secured creditor votes its secured debt in a liquidation meeting, the vote is invalid - and the security
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Liquidators must seek a court order to recover an insolvent transaction - even where the creditor has not objected in time to a notice under section
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It's now official
Making a payment to a creditor (in this case, the IRD) will in and of itself give that creditor priority over competing creditors

subset: commoncrawl


text:
Posted by Crowls2424
Not at all. I used this thread before I saw it on my other post trying to prove my point that Chimera is not dirty. This thread showed when a player has his back turned he doesn't crush the guys face into the boards, he wraps his arms around him (bear hug) while playing the body for a lesser impact.
Tonight McQuaid turned last minute before Chimera hold up or do the bear hug.


text:
After only being back in the saddle for a short while, Jo not only shed the pounds but is now a budding rider ready to buy her own stead!
We all know that getting in shape requires commitment, but by taking up a sport that is also fun and mentally stimulating, you are benefiting from the best of both worlds. Horse riding is an excellent way to exercise and get fit. It strengthens all your core body muscles, tones the all-important tum and bum areas and provides a relaxing cardiovascular workout.
Horse riding benefits everyone – men and women, old and young, able-bodied and disabled.
Riding will help you improve your fitness, build muscle tone, promote muscle strength and burn calories.
Riding is highly social, fun and mentally stimulating.
Did you know...
horse riding improves your sense of well being? It has the same antidepressant effects, similar to a "runner's high", associated with a drop in stress hormones!
some people with long standing illnesses or disabilities indicated an improved physical/mental condition, after going horse riding?
horse riding is a natural stimulator of the hormone serotonin? Serotonin is a natural mood enhancer which leads to a feeling of well being during and after exercise!
you can burn as many calories trotting on horseback as you can by heading down to the gym for a lunchtime workout?


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Ivana Baquero
Actor Ivana Baquero Movies / Films:"The Shannara Chronicles" (2016) El laberinto del fauno (2006) aka Pan's Labyrinth (2006) Frágiles (2005) Romasanta (2004) aka Werewolf Hunter, Werewolf Hunter: The Legend of Romasanta (2004)
Reviewed Movies Starring Ivana Baquero
Pan's Labyrinth (2006)
Following a bloody civil war, young Ofelia enters a world of unimaginable cruelty when she moves in with her new stepfather, a tyrannical military officer. Armed with only her imagination, Ofelia discovers…
Eyes of the Werewolf (2004)
A laboratory accident leaves Rich blind and at the mercy of an unscrupulous surgeon who performs an accidental eye transplant. Unknown to everyone, the eyes were stolen from a werewolf. All hell breaks…


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Try using black tea as a natural and safe alternative to dish soap or hand soap! Or even a metal scouring pad! It really does work and in our tests, we pitted tea against brillo steel pads, treated with oxyclean, regular dish soap, and just warm water.
Black tea worked better than a steel pad every time!
It even cleans floors safely!
And if you like to drink tea, too, try growing your own! Black and green tea come from a species of plant native to Asia, but which is readily available from several sources including Territorial Seed Company in Oregon (territorialseed.com). Tea plants require warm temperatures, and do well in greenhouses or as house plants. Besides tasting good, they also have pretty flowers!


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People Laugh at My Plan A Lot!
My 3 Sons: J (2/6/12), M (3/5/14), & R (1/16/16)
Experience in: being Catholic, NFP, HB, BF, CD, EC, & having opinions :)
I chose to have natural births because I didn't want myself or my babies to have exposure to the drugs and because I'm seriously terrrified of needles. I was more scared of getting a needle in my back or an IV then I was of dealing with contractions. Why you choose to have a natural birth doesn't mean that you won't be able to do it. You can do it as long as you stay focused and relaxed. It's not as awful and traumatizing as everyone likes to make it out to be. I loved my three natural births. My only bad experience was my one medicated birth.
My best advice is do your research. Get up, move around. Try and find a Doula. Use a birthing ball or a focal point or both. You can totally do it and your plan A is great! Laying down in a hospital bed was like torture to me, so I would recommend doing everything I could to not do that. Ask for a nurse that is open to natural birth, when you get to the hospital. It makes for a happier experience. Doctors don't spend too much time with you in the hospital. They check on you here and there but that's about it. The nurses are more important. Good Luck! Sounds like a great start!
Leo + Sagittarius = Gemini 2009, Virgo 2011 & Scorpio 2014
I am an FTM, and my doctor yesterday told me: it's all mental. You have to prepare, read, take NUCB classes. Animals don't think about it, they just do it. It's all mental.
My biggest fear with epidural is the loss of control (and the needle in my back). I cannot imagine not feeling my legs, listening to people to find out when a contraction happens, and birthing on my back -may the worst possible position!
If my mother did it, then I can do it. I've been through crazy things that were no where near as natural and expected as birthing a baby, so I figure I can handle a natural expected process (even if it goes an unexpected way).
As a mom, I'm doing everything I can to give my baby what s/he needs for a great start in the world. That includes a drug free birth with plenty of happy bonding hormones all around.
Like PP have said, it's all in the mind (and fear is the mind killer). Take a deep breath and remind yourself you're not the first and you won't be the last woman to give birth naturally. Watch some natural births (not the crazy stuff on TV but maybe some homebirths). You'll feel a lot better.
I found it fascinating that these hippie midwives have delivered thousands of babies and none have autism and neither to any Amish births either.......coincidence? I think not. Good luck! You can do it!
DH | Eric (5.5.07) :: DS | Seth (2.9.10) :: #2 COMING SOON!
iPhotograph | iBlog | iTweet


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The independent/specialty-film business bottomed out last weekend with its weakest performance of 2006, based on the results of the indieWIRE Box Office Tracking Report (iWBOT), as 60 titles took in just $3.076 million. Things should pick up, however, as that traditionally slow weekend passes and new movies like Miramax Films' "Venus" and Warner Independent Pictures' "The Painted Veil" start to arrive for the holidays this week. Still, there were two encouraging performances last weekend as David Lynch's "Inland Empire" came in first again on the iWBOT by venturing into Los Angeles and jumping to four engagements from its previous two.
The iWBOT is based on per-theater averages reported by Rentrak Theatrical, the complete indieWIRE BOT weekly chart is available here at indieWIRE.com
"Inland Empire" averaged $11,223 and reached $100,000 in total gross - impressive for an art film that is, essentially, three hours of weirdness. It is being distributed by Lynch's own Absurda company, which has hired 518 Media to handle North American theatrical bookings. Meanwhile "Live and Become" - a "stealth film" whose distributor, Menemsha Films, has yet to start aggressively booking it nationally - opened at Washington's Avalon Theatre to a smashing $10,368. And it has been playing at Boston's West Newton Cinema for 12 weeks, recently splitting a screen with "Stranger than Fiction."
"It was the best art-house run in Washington, D.C., by far," said Andrew Mencher, Avalon's director of programming, of "Live and Become's" performance, in an E-mail. "'History Boys' did $7,606 at Bethesda Row. Considering we did this well on a traditionally soft week before Christmas, we're pretty excited. It's yet another example of a distributor investing time in a specific market and working hard to energize specific segments of the population base. Lead-actor Sirak Sabahat graciously came to D.C. and appeared at several events over the weekend and he turned out to be a terrific draw."
Mencher said "Live and Become's" Boston gross was a much smaller $1,100 for the weekend.
Menemsha has a history of releasing art films and documentaries, especially with a Jewish theme, that build slowly but play remarkably well in key cities. Its "Gloomy Sunday," a German-Hungarian thriller set in 1930s Budapest, played at L.A.'s Laemmle Music Hall Theatre for 55 weeks and at Boston's West Newton for 70 weeks. The distributor hopes to make "Live and Become" its biggest release to date.
"Sometimes we don't get out of the box with big numbers," explained Menemsha's Neil Friedman. "But we go north, unlike a lot of other films, and increase our gross from week to week. It was like that with 'Gloomy Sunday' and we're going to try to do it with 'Live and Become.'"
The drama, a French-Israeli production directed and co-written by Radu Mihaileanu, concerns an Ethiopian Christian boy whose mother pretends he's Jewish to get him airlifted to Israel and out of a Sudanese refugee camp in 1984. (At the time, in an evacuation called Operation Moses, Israel was airlifting Ethiopia's Falasha Jews out of the troubled, chaotic and uncooperative nation if they could get to Sudan first.) Once in Israel, the boy must pretend to be Jewish.
"It's a twist on the idea that it's not good to be a Jew when there's trouble," Friedman said. "In this case, it helps you survive."
In another twist, the actor who plays the Ethiopian Christian youth passing as Jewish, Sirak Sabahat, is in fact an Ethiopian Falasha Jew who came to Israel during another evacuation, 1991's Operation Solomon.
Friedman said "Live and Become" will be going into a wider release in 2007.
"Inland Empire" did best at Manhattan's IFC Center, where it was in its second weekend and grossed $17,057. At the Brattle Theatre in Cambridge, it brought in $5,924. In Los Angeles, it brought in about $14,000 at Laemmle's Sunset 5 in West Los Angeles and $7,500 at Laemmle's Pasadena Playhouse.
"I wouldn't say those are through the roof, but I'm cautiously optimistic," Greg Laemmle said of the L.A. numbers. "The feedback by and large has been positive. There were not masses of people fleeing to the exits that we know of. But we're dealing still with a fan base that goes for it."
Peter Langs, 518 Media's CEO, said more prints are being made to get to a total of 16 and that January, 2007, dates are set for Hartford and Palm Springs. "We're trying to time it with David's appearances," he said.
No word yet, by the way, on whether the film's apartment-dwelling hares, whose every enigmatic statement is met by a laugh track, will get their own sitcom.
Because of last weekend's low overall gross of $3.076 million, the 60 films at 2,078 theaters had a per-site average of but $1,480. But because of the drop in theaters from the previous weekend's 3,358, as well as the drop in titles from the previous weekend's 73, that average actually represented at increase of approximately 20% over the previous $1,217. Because so few indie/specialty films have broken out this fall, some upscale houses are playing "prestige" studio films like "Stranger than Fiction," "The Departed," "Running with Scissors," "Blood Diamond" and even "Apocalypto." Those aren't reflected in the iWBOT numbers.
ABOUT THE WRITER: Steven Rosen is a Los Angeles-based film writer and former movie critic at the Denver Post.
indieWIRE:BOT tracks independent/specialty releases compiled from Rentrak Theatrical, which collects studio reported data as well as box-office figures from North American theatre locations. To submit information about your film to Rentrak, please email email@example.com


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how is the CVR to be paid? My shares are in a discount brokerage firm account. What if, between now and 2017, I close the account or move to another address. How would I receive the CVR? A lot of things can change in four years.
If you hold on and take the CVRs, they will appear in your account under some sort of numeric code with the appropriate number of "shares" and zero value. It can be transferred to another account. If you were to close all your broker accounts it might well be a paper nightmare, but should still be tracked.
As others have said though, it is your call if you want to hang on to these. Your can sell your shares on the open market prior to the closing and get something over $13.50 that is the market value of that CVR.
Right now you would get 0.23 for the CVRs. But it would not surprise me to see the price drift up in the next couple months, for 2 reasons. One is that there is a real cost in tying up that $13.50. That could be .10 or so. But also there are many who are cashing out simply because they do want to be bothered. Personally, I will not sell the CVRs for less than .50, and have even bought more twice under 13.70 though did sell earlier when they hit $14+).
OK, some of this price stuff is speculation of course. But you can always hold on up until shortly before the closing and decide then. If you do this, do NOT tender your shares as that will limit your options. If you hold on and have turned down the offer, you still end up with the same deal as those whe tendered their shares, so it really matters little, Also, you might not want to wait until the last day to sell as the market might get distorted then.
You will not need to hold your shares that long. You will receive an opportunity sell agree to the terms offered by cubist, and when you sell to cubist, you will be the shareholder of record, and if Ted hits the agreed to sales targets in the time frame agreed to, you will be paid at the appropriate time. Be sure to keep your trading account open, though I don't think it will matter.
This assumes the deal will close as agreed by both BODs.
The easiest solution is to keep your account open, and give the company a change of address.


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HTG Peer Groups Blog
The HTG peer group experience is a unique forum for technology industry resellers who are serious about implementing a model for success in their own businesses through sharing and collaboration of best practices.
CRN Power100 Women in IT
A month or so ago, HTG hosted our second CEO Forum in Denver and had Colleen Abdullah who is CEO of WOW as our speaker. She was dynamic and extremly engaging. One thing she said I have not forgotten was this: "If you want to succeed in the business world today, you need to have some strong women on the management team". May be paraphrased a bit, but the message was clear. The days are over of male dominance in the board room. It is time to leverage the current generation of female leaders and leverage their skills as part of a successful management team. I can validate that statement completely.
Connie Arentson has worked at HTS for some 15 years now. She began as a field engineer, quickly moved up to become service manager and held that role until June 2009 when she was elevated to the position of president at HTS. That is one of the best decisions I have ever made in running the company. Her passion to succeed and attention to detail has propelled us to growth even when the economy was down. We had to make some tough decisions last year, but it was done with grace and consideration for all our team, and no one lost their job as we consolidated some offices. I can honestly say that had a guy been sitting in that seat it probably would have looked different. Connie is a humble, steady leader who just gets it done but never forgets about the people and relationships that make HTS a success.
Jane Cage is the ultimate partner. She came to HTS as part of a merger back in late 2002 when her Connecting Point store joined SCCI to form HTS. There is no person I know on this planet who can do magic with data like she can. Our back office has been revolutionized by her ability to make numbers talk and sing together. She is the cautious part of our leadership team, and always asks the pesky questions like "why are we doing that"? But over the years (and I am not really saying this out loud) I have come to appreciate her caution and discipline even when it slows things down some. Jane has a heart of gold and knows most of the known world, and her experience and relationships have been a blessing to our company over the years.
Christy Sacco came to HTG to help us get events right. It didn't take long with me trying to manage details that I knew we had to have help and fast. (For some reason her picture is not in the slide show, but if you go to the entire list she shows up on the list on page 15). Christy is like a never ending bundle of energy. She makes me tired just watching her, and I am usually considered the maniac of getting things done. There isn't a detail she hasn't conquered and no problem that causes her to lose too much sleep. But her biggest attribute is she is an event planner extrordinaire because she understand the channel and partners very well. She is a relationship person who knows that first and foremost it is about people. Her experience and expertise have caused HTG to have awesome events ever since she came to us. And the real challenge is how to make it better in the future when she has already produced near perfection. Of course that is me speaking - she has a whole list of details to take us to the next level.
Bottom line is that HTS/HTG has three of the Power100 women in this industry. We are in pretty good company when you look at the list for other companies that can say that. Am I proud of these women? You bet I am, and blessed to work beside them every day. It takes fantastic people in the seats on the bus if you want to really hit it out of the park. We are blessed with these three, and a whole lot more on our team. You can only expect bigger and better things from HTS and HTG as we experience the power of teamwork. The best is yet to come because our management team (which also has some amazing men) is hitting on all cylinders.
Thanks to all who allow us to serve you or call you friends. It has been a great ride for the first 25 years, and we are just getting started. Connie, Jane and Christy - I am proud of all three of you and look forward to being kept in line for some time to come. When my bride enters this mix I am surrounded on every side with no where to run or hide. Guess I will just get back to work......
- Peer Power - So What? - Peer Power Apr 07
- MSPU Boot Camp Coming to Atlanta - Peer Power Apr 06
- The HTG SWOT process in action - Peer Power Apr 01
- Risk....Care....Dream....Expect - Peer Power Mar 21
- An Upcoming Live Meeting Opportunity - Peer Power Mar 11
Arlin Sorensen serves as the CEO and Founder of the Heartland Companies which includes HTG Peer Groups. When he is not traveling to speak and consult, Arlin is home on his farm in Iowa with his wife Nancy. He is a proud "Pop" to four precocious grandchildren who serve as daily reminders of why he is intentionally living to leave a strong legacy of faith and integrity. He loves making a difference in the lives and companies of small to mid-market business owners. You can reach him at firstname.lastname@example.com or on Twitter @asorensen
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This is the second post in a series on making sure your legacy is in place financially. Part of planning and preparation means being ready for the unexpected. There are four D's that can drastic


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Something shiny and glossy is what this fiftieth birthday shindig calls for and they also have to be swirly and hang from the ceiling so everyone can see them. There aren't many things out there like what was described, but we always come to the rescue and we offer The Party Continues 50th Birthday Swirl Decorations just for you.
Not yet rated. Be the first to Write a Review


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I totally ripped this off from a very cool and funny site called Savage Chickens. And you totally have to go check them out, it's worth the trip. Guaranteed to make you smile! (Well, only if you think chickens are kind of funny.)
I'm happily married, and have Nick and Nora, our two cats.


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Brad Wollack
BEST BETDATE: July 26 2013, 8:15 PM to July 27 2013, 10:45 PMCost:$22.CATEGORY: Performing ArtsVENUE INFORMATION:Comedy Works South at the Landmark5345 Landmark Pl.Englewood, CO 80111
With a full head of curly red hair, comedian Brad Wollack has been the butt of nearly every redhead joke out there. As co-producer, co-creator, and co-star of the E! comedy series After Lately, Wollack can pack a laugh-filled punch of his own. Fri-Sat 7:15 p.m., 9:45 p.m.
More Information:
Visit www.bradwollack.com.


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Similar to this Known Issue, the Blackberry handheld device will attempt to open the new 'notified' request via a new browser instance, and in doing so, will fail to present the appropriate notify cookie. As a result, the device will display a blank page rather than the expected destination URL that triggered the notify action.
At present, the only known workaround is to negate any 'notify' actions for BES IP addresses or Blackberry user-agent strings.


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Dahlan: Bush speech strengthened Arafat popularity
Mohammed Dahlan, the man widely regarded as the US and Israel's preferred successor to Yasser Arafat, Tuesday accused U.S. President Bush of demanding a "coup d'état" against the Palestinian leader and declared that he would not stand against Arafat.
While conceding "reservations" about some of Arafat's decisions, Dahlan, former head of Palestinian security in Gaza Strip, said Bush's intervention had backfired and would keep Arafat in place, rather than encouraging reform and a new generation of leaders.
Writing in the British daily Guardian, Dahlan said maintained one result of Bush's intervention is that the latest polls show nine out of 10 Palestinians would vote for Arafat. "As long as the Israelis are against Arafat, I'm with him - whatever reservations I have about some of the decisions that have been made."
Dahlan - who remains a close security adviser to Arafat - ridiculed what he called the "lies and false allegations" that he was somehow favored by Israel, recalling an incident last year when his car was shot at by Israeli soldiers. (Albawaba.com)
© 2002 Al Bawaba (www.albawaba.com)
Top Headlines
- New crisis between Arafat, Abu Mazen over appointment of new interior minister could result in Dahlan's removal
- Israel, Palestinians Pleased with Bush's Anti-Terror Speech
- U.S. officials: Bush decided to seek Arafat removal after latest bombing attacks in Israel
- Iran spiritual leader accuses Bush of "unimaginable injustice"
- Dahlan resigns; Arafat wants him as security adviser


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Orlando Sansón Castro is a Cuban cartoonist. He is the artist of the comic strip 'Simplicio' together with writer José Luis Vitón, that was published in the small format comics paper La Tira in the 1990s.
Artwork © 2016 Orlando Sansón Castro
Website © 1994-2016 Lambiek
Laatste update: 2016-02-20
Series en boeken door Orlando Sansón Castro op voorraad in de Lambiek Webshop:
If you want to help us continue and improve our ever- expanding database, we would appreciate your donation through Paypal.


text:
More New and Used
from Private Sellers
Note: Supplemental materials are not guaranteed with Rental or Used book purchases.
Best Bike Rides Minneapolis and St. Paul : Great Recreational Rides in the Twin Cities Area
ISBN13:by Steve Johnson
Trade Paper
Questions About This Book?
What version or edition is this?
This is the edition with a publication date of 5/21/2013.
What is included with this book?
- The New copy of this book will include any supplemental materials advertised. Please check the title of the book to determine if it should include any CDs, lab manuals, study guides, etc.
- The eBook copy of this book is not guaranteed to include any supplemental materials. Typically only the book itself is included.
Written for cyclists of all stripes, Best Bike Rides books offer a diverse array of scenic tours in and around some of Americas largest urban destinations. Road rides, rail trails, bike paths, and single-track mountain bike rides all get included. Most rides are in the 5 to 30 mile range, allowing for great afternoon outings and family adventures. Each book features 35-40 rides with color photos, maps, point-by-point miles and directions, and GPS coordinates of starting and finishing points.
Author Biography
Steve Johnson is a self-propelled recreation junkie and fan of all things outdoors. A regular contributor to Backpacker and regional magazines across the country, some of Steve\u2019s other work include Minnesota Waterfalls, Loop Hikes Colorado, and Bicycling Wisconsin. Steve lives with his family at a country place in southeastern Minnesota.


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|Número de publicación
|Tipo de publicación
|Número de solicitud
|Fecha de publicación
|22 Ene 1991
|Fecha de presentación
|12 Dic 1989
|Fecha de prioridad
|15 Dic 1988
|También publicado como
|Número de publicación
|Vivian C. Watts
|Cesionario original
|Bath Scientific Limited
|Exportar cita
|BiBTeX, EndNote, RefMan
|Citas de patentes (9), Citada por (8), Clasificaciones (7), Eventos legales (6)
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet
The present invention relates to an electrical testing probe, for example for use in testing printed circuit boards.
In the field of testing printed circuit boards, for example such boards before they have components added, a method of testing requires more than one moving electrical testing probe. A requirement of such a probe is that it has a small area of contact such that it does not make a short circuit between closely spaced electrical pads that may be present on the printed circuit board. Additionally, it is often a requirement that probes come into close proximity with each other; and further that a probe can provide when necessary a purely vertical motion with no horizontal motion when making contact with the printed circuit board so that no scrubbing action takes place between the probe and the probed surface which could damage the surface being tested.
Current designs of probes have probe bodies with very small diameters and are able to cater for the above requirements. FIG. 1 shows schematically such a probe, in which reference numeral 1 denotes the probe, this comprising a probe body 2 held springloaded in a sleeve 3 of a stand-off member 4. FIG. 2 shows two such probes with a typical minimum probe separation A in one horizontal direction.
However, such a probe as is shown in FIG. 1 may not adequately meet the requirement that it can probe both an electrical pad with a small geometry and also a pad which has a large geometry with a hole in the centre of the pad. Although such a probe will adequately contact the former, in the case of the latter it could travel down the centre of the pad and through the hole without making electrical contact (see FIG. 3 in which reference numeral 5 denotes a pad with a small geometry and FIG. 4 in which reference numeral 6 denotes a pad with a large geometry).
According to the present invention, there is provided an electrical testing probe comprising: a probe body which is generally laminar and which tapers downwardly to provide a contact portion; and a carrying member which carries said probe body.
The present invention will now be described, by way of example, with reference to FIGS. 5 to 10 of the accompanying drawings, in which:
FIG. 5 shows from one side a probe according to an example of the invention;
FIG. 6 shows a view from above of the probe;
FIG. 7 shows from one side two such probes near each other and with a typical minimum separation in one horizontal direction;
FIG. 8 shows a view from above of two such probes near each other and with a typical minimum separation in an orthogonal horizontal direction; and
FIGS. 9 and 10 show the probe body of such a probe contacting an electrical pad with a small geometry and an electrical pad with a large geometry respectively.
Referring first to FIG. 5, a probe 7 according to an example of the invention comprises a stand-off member 8 which carries sleeves 9 and 10, reference numeral 11 denoting a laminar probe body in the form of a thin blade of electrically conductive material. The probe body 11 is carried by a rod-shaped member 12 which is held by virtue of a spring 19 in a springloaded manner in sleeve 9 and a rod-shaped member 13 which slides in sleeve 10 and serves to prevent rotation of the probe body 11.
The probe body 11 has a straight upper side 14 which is horizontal; a first, straight lateral side 15 which is vertical; a second, straight lateral side 16 which is raked backwards from a tip 17 of the probe body; and a lower side 18 whereby the probe body tapers downwardly towards tip 17. As shown, side 18 is formed to have a stepped or staircase pattern, although it could, if desired, be a straight side.
Such a probe may be used in a system comprising a further such probe for testing automatically printed circuit boards. Each of the probes would be movable automatically in two orthogonal (X and Y) horizontal directions and in the vertical (Z) direction. The probes would be moved to contact specific points on the printed circuit board for the purpose of automatically making resistive and/or capacitive checks under the control of a computer. For example, two such probes may be used in apparatus as described in U.S. patent application Ser. No. 397,612 filed on Aug. 22, 1989 and entitled TESTING ELECTRICAL CIRCUITS (which is a Continuation-in-Part of U.S. patent application Ser. No. 326,697 filed on Mar. 21, 1989), now copending.
By virtue of the side 16 of the probe body 11 raking back at an angle to the vertical from the tip 17, if this side is out of parallel with the vertical, it will not cause two such probe bodies to make contact with each other when they come in close proximity.
The horizontal dimension of tip 17 determines the minimum size of electrical pad with which contact can safely be made without shorting out an adjacent pad. In conjunction with the thickness of the probe body 11, it determines the surface area contact that is made with a surface being tested.
By virtue of sides 16 and 18 of the probe body 11 whereby the latter tapers downwardly towards its tip 17, the probe body 11 can contact both an electrical pad with a small geometry and an electrical pad with a large geometry (without merely passing through the centre of the hole of the latter without making electrical contact with the pad). This is shown by way of FIGS. 9 and 10 respectively.
Although, as mentioned, the side 18 could be a straight edge, if it has a staircase shape as shown, this means that when making contact with a pad of large geometry, the probe body 11 is likely to catch on the edge of the hole via one of the steps of the staircase shape and not have a sideways bias which might occur with a straight edge in a similar circumstance.
As well as side 16 being raked back at an angle to the vertical from tip 17, also side 18 is raked back at an angle to the vertical from the tip 17. This is so that the probe body 11 does not make contact outside the tip 17 on a flat surface.
It is to be noted that the tip 17 is forward of the spring-loaded member 12 so that two such probes can come as close together as is practical at their probe body tips 17 in one horizontal direction - see FIG. 7.
The thickness of the probe body 11 determines how close two such probes can come together in an orthogonal horizontal direction when they are adjacent each other - see FIG. 8.
In the light of the foregoing, it will be appreciated that: at least two such probes 7 can coexist together and can be moved in both the X and Y directions such that their tips 17 can come into close proximity with each other in either the X or Y direction; a motion of the tip 17 of the probe can be effected in purely the Z direction with minimum scrubbing action in the X and Y directions; and such a probe can adequately make contact with electrical pads with both small and large geometries without the requirement to offset mechanically the centre of action of the probe tip.
|Patente citada
|Fecha de presentación
|Fecha de publicación
|4 Jun 1973
|26 Nov 1974
|Electroglass Inc
|Microcircuit test device with multi-axes probe control and probe stop means
|22 Dic 1975
|30 Ago 1977
|Charles Wheeler Coberly
|Integrated circuit probe
|14 Jun 1979
|13 Ene 1981
|Upa Technology, Inc.
|Probe assembly for measuring conductivity of plated through holes
|26 Dic 1978
|17 Feb 1981
|Pacific Western Systems Inc.
|Probe head for an automatic semiconductive wafer prober
|30 Abr 1984
|29 Sep 1987
|Cascade Microtech, Inc.
|Wafer probe
|10 Nov 1986
|16 Ago 1988
|Cascade Microtech, Inc.
|Wafer probe
|17 Ago 1987
|27 Sep 1988
|Feinmetall Gmbh
|Contactor for an electronic tester
|2 Dic 1987
|21 Feb 1989
|Northern Telecom Limited
|Adjustable quick-mount test probe assembly
|19 Jul 1983
|19 Dic 1989
|Texas Instruments Incorporated
|Intelligent multiprobe tip
|Patente citante
|Fecha de presentación
|Fecha de publicación
|24 Oct 1991
|20 Abr 1993
|Interconnect Devices, Inc.
|Module attachment for printed circuit board test fixtures
|23 Nov 1994
|2 Ene 1996
|At&T Corp.
|Temporary connections for fast electrical access to electronic devices
|10 Feb 2003
|18 Nov 2003
|Lecroy Corporation
|Electrical test probe wedge tip
|21 Nov 2002
|26 Abr 2005
|Pemstar, Inc.
|Micro connector to facilitate testing of micro electronic component and subassemblies
|3 Jul 2002
|6 Mar 2003
|Schhuster Philip J.
|Micro connector to facilitate testing of micro electronic component and subassemblies
|21 Nov 2002
|3 Abr 2003
|Daniel Johns
|Micro connector to facilitate testing of micro electronic component and subassemblies
|10 Feb 2003
|9 Oct 2003
|Lecroy Corporation
|Electrical test probe wedge tip
|10 Jul 2002
|13 Feb 2003
|Pemstar, Inc.
|Micro connector to facilitate testing of micro electronic component and subassemblies
|Clasificación de EE.UU.
|324/755.01, 439/482, 324/756.01, 324/763.01
|Clasificación internacional
|Clasificación cooperativa
|Clasificación europea
|12 Dic 1989
Owner name: BATH SCIENTIFIC LIMITED, LYSANDER ROAD, BOWERHILL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WATTS, VIVIAN C.;REEL/FRAME:005200/0874
Effective date: 19891123
|18 Jul 1994
|Fee payment
Year of fee payment: 4
|15 Dic 1997
Owner name: EVERETT CHARLES TECHNOLOGIES, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BATH SCIENTIFIC LIMITED;REEL/FRAME:008861/0739
Effective date: 19971204
|18 Ago 1998
|Maintenance fee reminder mailed
|24 Ene 1999
|Lapse for failure to pay maintenance fees
|6 Abr 1999
|Expired due to failure to pay maintenance fee
Effective date: 19990122


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There comes a time in every makeup obsessed girl's life when she finally realises that despite having 40 lippies and 13 mascaras.....she actually has a favourite mascara and a favourite lip gloss. Shocking I know and shhhhhhh please don't tell my boxes and drawers full of other makeup as they might get jealous and I wouldn't want that. L'oreal Voluminous in Carbon Black and Soap and Glory Sexy Mother pucker Lip Plumper are two products that I make sure I repurchase as soon as the previous ones look like they might run out, funnily enough they both tend to run out around the same time which is quite handy for trips to Boots in Bluewater.
L'oreal Voluminous is probably the most boringly packaged L'oreal mascara but it is by a country mile their best, I wish they did a tube of their white primer that they use for their double ended mascaras as I would love a big fat tube of that to use with this. When I want massive lashes I put on the primer, put on a layer of this, put on a layer of the fibres from ModelCo's fibre mascara then put on another coat of voluminous (really spilling my weirdo mascara layering secrets now) then sometimes I stick on a few individual lashes if it's for a night out. Being high maintenance sure does take up some time!
Soap and Glory Sexy Motherpucker gloss (£9) is hardcore, I kissed the back of my hand once and the ingredients that make youR lips swell are so strong that I got a rash on the back of my hand! Keep this just to lips please otherwise you will look a bit weird, and don't get this on the skin around your mouth or that will go bright red. Exercise some caution, take care and you will have one big fat kisser that often causes people to ask who did my lips as they want them.
And if you wondered what a 'Bitch Fit' looks like? I can't say for sure as each one is different, but it certainly isn't pretty.


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2 posts tagged with guardian by hoder.
Displaying 1 through 2 of 2.
Iran has shown the British what kind of people we really are: without honour and without shame, writes David Cox in The Guardian.
Our shameless culture, by David Cox (The Guardian): Iran has shown the British what kind of people we really are: without honour and without shame. The Sun, the now officially approved disseminator of British military information, notes that navigator Arthur Batchelor was "tormented" by being called "Mr Bean". Understandably, he had to cry himself to sleep. Perhaps President Ahmadinejad feared that the goody bags might just prove a step too far. But no, they were gratefully received, in a response that aptly captures the infantilisation of a people that once ruled much of the world. Navigator Batchelor has however since complained that the quality of his own bag's contents was not what he had hoped.
Iran is not on the verge of revolution
Iran expelled me, but its press restrictions play into the hands of the west's fantasies about Islamism: "Contrary to the fantasies of neo-conservatives, Iran is not on the verge of revolutionand, if it was, the US wouldn't be able to orchestrate it. There is no coherent political opposition or leader able to harness public discontent. A significant number of Iranians are profiting from an economic boom and are not ready to risk their livelihood for democracy protests," writes Dan De Luce, the Guardian's reporter in Tehran who has recently been expelled by the Iranian goverment.
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Inauguration Day
I flew the American colors on Inauguration Day, at half-mass in memory of all the American liberties and dreams this president has slaughtered in the past four years.
TalkBack readers
A few of my friends get together every morning drinking coffee and looking at the TalkBack. Some of them mentioned that they've called in to TalkBack several times about banning gun magazines and clips and so forth, and we pick up the paper and you've got an article printed in there called "full protection." Well, someone stated that it would be fine to allow the sale of grenades, tanks and chemical weapons because the government is coming to take our wives and kill our chickens. I think you ought to have a little more responsibility to the public than printing such crazy stuff as this. You need to select better posts rather than putting such idiotic statements in your paper.
Some churches are cleverly used by the devil to worship evil, because people go to church searching for our God. A variety of religious doctrine is waved in front of audiences like a sword or assault weapon. A plethora of religious television solicits the troubled, the meek, the destitute and the impoverished for their last dollars in the name of our Lord. My God has a sense of humor, my favorite animals are cats. They have nine lives right? I have used up a few so far, the worst situation most recently. You are blessed if you read this, so share, in the name of our lord, amen.
Washington, D.C.
I believe with all my heart that, if we could get rid of Mitch McConnell and let John Boehner handle the things in Washington, D.C., there would be cooperation, there would be more people working together and there would be more peace than we've been seeing.


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Destination Maternity relaunching site with a mobile focus
More than half of the maternity apparel retailer's online traffic comes from mobile shoppers.
Destination Maternity relaunching site with a mobile focus
More than half of the maternity apparel retailer's online traffic comes from mobile shoppers.
Twitter pivots away from Buy buttons
While the social network isn't doing away with its direct-sale initiative, it is focusing its attention on ads that drive consumers to retailers' sites.
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When it comes to mobile average order value, tablets beat smartphones, Apple tops Android, and men spend more than women, according to the Internet Retailer-exclusive, 5,500-retailer Shopgate Mobile Commerce Index.
Posted 06/26/2014Bill SiwickiPost a comment
Related Content:Online Jewelry Sales Statistics
Version 4.0 of mShopper's mobile commerce platform features responsive design techniques that retailers can use to serve sites to consumers on mobile devices of varying shapes and sizes. In tests, conversion rates are up 50%.
Posted 06/26/2014Amy DustoPost a comment
75% of contacts from users of the Amazon Fire HDX tablet now come through the device's unique Mayday button, which quickly connects the tablet user with Amazon support agents via onscreen video.
Posted 06/16/2014Bill SiwickiPost a comment
New features improve quality and speed time-to-market for mobile apps. Higher level of re-usability of testing scripts delivers better coverage of cross-platform requirements.
Posted 06/12/2014
Mobile book buyers often have a title or author in mind, and searchers convert at a far higher rate, Alibris says, hence the prominence of search. 10% of the e-retailer's traffic stems from tablets; the bookseller expects tablet visits to grow 5-10 times in the next two years.
Posted 05/29/2014Bill SiwickiPost a comment
Nearly 70% of consumers go online before they shop in stores, and 36% connect to the web while in stores.
Posted 04/28/2014Allison EnrightPost a comment
Related Content:Web Influenced Retail Sales
As shopping on smartphones and tablets becomes routine for consumers and the importance of home desktop computers fades, retailers will need to focus more on a consumer's location and context and less on the type of device a consumer is using, experts predict. Mobility, both outside and inside the home, will remain key, experts say. But what about 'the Internet of Things'?
Posted 04/28/2014Bill SiwickiPost a comment
Related Content:Forrester Retail Forecast | Us Ecommerce Forecast | Iot
TV, an American institution, has met its match—the smartphone. TV viewers watch 2 hours and 27 minutes of television every day while smartphone owners now use their devices for 2 hours and 31 minutes every day, Millward Brown Digital finds. Tablet owners rack up only 43 minutes a day.
Posted 04/24/2014Bill SiwickiPost a comment
U.S. m-commerce sales on tablets are soaring while the influence of smartphones on purchases grows, new data from research firm eMarketer show. By 2018, purchases on tablets and mobile phones will account for 27% of all online sales, or $133 billion.
Posted 04/21/2014Bill SiwickiPost a comment
Big Bazaar Direct already is one of India's largest retailers. But it wants to be bigger, and rather than open more bricks-and-mortar stores, it's arming small Indian merchants with tablets pre-loaded with a special Big Bazaar app that enables shopkeepers to place online orders on behalf of their customers, most of whom do not have Internet access.
Posted 04/17/2014Bill SiwickiPost a comment


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"Square of 23rd February and Gernika bridge" Top 5 Page for this destination Pforzheim Things to Do Tip by Kathrin_E
Pforzheim Things to Do: 23 reviews and 70 photos
The square behind the modern city hall has been named "Platz des 23. Februar 1945" to commemorate the date of the city's destruction. It is for pedestrians only, with benches and flower beds and a modern fountain. However, the visitors it attracts are not necessarily people you'd like to meet after dark...
Next to the square a pedestrian bridge crosses the adjacent six-lane street and leads to the congress centre and the theatre, and from there down to the river. The bridge is named Gernikabrücke . Gernika, the holy town in the Basque country, Guernica in Spanish, is twinned with Pforzheim. Both towns share the same sad fate: Gernika was bombed by German aircrafts in the Spanish Civil War in 1937 (remember Picasso's painting).
Directions: Behind the city hall
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KPD Recruitment Info
City of Kyle info
Head Lifeguard
Kyle, TX
Salary Range:
Minimum 9.50 per Hour
Employment Type:
Seasonal - Full Time
Under the direction of the Pool Manager, assist with administrative, supervisory, and professional work in the day to day operation and maintenance of the City pool and in coordinating various aquatics programs. Accomplishes specialized work in protecting life, preventing accidents, enforcing safety regulations and providing instructions; and performs related work as required.
Pool Dates run from May-2013 through September-2013
Assist the Pool Manager in training and supervising lifeguards, cashiers and other related personnel.
Assist staff in general performance of duties.
Direct the patrolling of the pool and the enforcement of safety rules and regulations.
Supervises and assists in cleaning the pool and related facilities and equipment.
Coordinates schedules and maintains related records and statistics for programs and personnel at the swimming pool; prepares attendance and accident reports.
Supervises classes, workshops and activities for persons engaged in aquatics programs and co-sponsored programs when needed.
Assist the Pool Manager in the maintenance of the swimming pool; monitor and maintain pool filtration system; monitor pool water chemistry through testing of water samples; adjust chemistry as needed to maintain standards.
Responds to public inquiries about aquatics programs made by person, telephone, or any other type of correspondence.
Assume full management responsibilities of City Pool facilities in absence of Pool Manager and/or Assistant Pool Manager.
Maintains desired working relationship with Parks & Recreation Director, Recreation Manager, Program Coordinator, and City Manager.
Performs a variety of miscellaneous duties such as answering phones, typing correspondence, running errands, picking up supplies needed for activities, conducting classes, collecting fees; making arrangements for rental and use of pool, helping set up for classes, events, etc.
Performs all other duties as duly assigned by the Parks and Recreation Director.
American Red Cross Standard First Aid, CPR for the Professional Rescuer and Lifeguard Training are all required.
Water Safety Instructor certification is preferred.
Work may routinely require the employee to push, pull, lift, and/or carry up to 50 pounds.
Work includes walking, talking, hearing, using hands to handle, feel or operate objects, tools, or controls, and reaching with hands and arms. Vision abilities required by this job include close vision and the ability to adjust focus.
Work may routinely require the employee to climb, balance, bend, stoop, kneel, crouch, and/or crawl.
Swim with proficiency and endurance for possible rescues.
Work outdoors in a variety of environmental conditions, including high temperatures, humidity and moisture and distracting noises.
Ability to remain calm and act resourcefully in an emergency and in stressful situations.
Ability to communicate effectively, verbally and in writing.
Working knowledge of basic opening, closing, and cash on hand statements.
Ability to establish and maintain effective working relationships with employees, supervisors, other agencies, and the public.
Must have a minimum of six (6) months professional experience in instructing or supervising water recreational activities. Must possess or be able to obtain a valid Texas Drivers License or Texas Identification Card.
An individual who poses a direct threat to the health and safety of himself/herself or others in the workplace will be deemed not qualified for this position.
This position description has been prepared to assist in defining job responsibilities, physical demands, and skills needed. It is not intended as a complete list of job duties, responsibilities, and/or essential functions. This description is not intended to limit or modify the right of any supervisor to assign, direct, and control the work of employees under supervision. The City of Kyle retains and reserves any or all rights to change, modify, amend, add to or delete, from any section of this document as it deems, in its judgment, to be proper.
The City of Kyle is an Equal Opportunity Employer
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Posted by Newfiebullet
At the start of the season, I was focussing on Seguin and Caron. However, I see Marchand taking advantage of every shift, as opposed to every game. WIthout a doubt, his improvement(s) required to be productive at the NHL-level will come very quickly using this approach. Good on him!
Yeah, I'd like to see him play with some of teh others, but that is just a matter of time.


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Twenty-five years later: Still laughing at Seinfeld
Twenty-five years ago this month, The Seinfeld Chronicles made its debut and four borderline sociopaths living in existential desperation made their way into our lives for the next nine years.
The "show about nothing," which NBC execs initially didn't believe would click with audiences while calling its premise "too New York, too Jewish," was given just four episodes to justify its existence before being taken off the air for a year. Had it not been for the tireless efforts of one executive who saw the show's potential, the series would have never made it past the pilot, in which we find Jerry and George having an inane argument about placement of shirt buttons in a bustling coffee shop. It was fair to call the initial four episodes a work in progress.
Oh, but did it ever make a glorious return, going on to redefine the sitcom genre and transcend television as we know it, celebrating the excruciating minutiae and annoyingness of everyday existence, whether it be waiting for a table at a Chinese restaurant or being annoyed with people who double dip, people who eat their peas one at a time or being annoyed at, well, just about anything. Seinfeld was a massive success, serving as appointment viewing for more than 76 million Americans at the height of its popularity in the '90s, and becoming one of the most successful shows in U.S. television history, kvetching and kvelling its way to the top of Arthur Nielsen Media Research Ratings every year from 1994 to 1998.
Seinfeld, which still airs in syndication on more than 250 stations across the country on prime real estate, provided laser-sharp observations about our culture while dealing with an array of Jewish issues, whether that be difficulties finding a mohel, coping with blabby rabbis, falling for women for their "shiksappeal," being mildly outraged with people who convert to Judaism for the wrong reasons or shopping for the perfect chocolate babka. Seinfeld was a sitcom like no other, in which the characters never learned a lesson in morality and the error of their ways or subsequently grew more mature as a result of their actions. Most episodes painted two bleak worldviews: Most people are inherently bad (and not very bright), or caring about other people's feelings is absurd (and not very practical, either).
Much of the show's observational and innocuous brand of humor and coffee-shop banter was based on surviving daily in a world of small but humiliating situations, and discussing them all with your self-pitying and neurotic friends afterward — a group of people sitting around and doing, famously, nothing. But besides the phrases it gave us — "sponge-worthy," "shrinkage" and "yada yada," its quotability and its perpetuation in syndicated reruns, the themes Seinfeld was built around are so very universal.
Who, at one point, hasn't thought about arguing with a clerk after getting wrong change, or confronting someone for taking credit for something they didn't do? This stuff isn't just shtick—it's a masterful rendering of the absurd and the all-too-true.
Our society's appreciation for the show has even spawned various "Seinfeld to go" Twitter accounts such as @Seinfeldtoday and @Seinfeld2000, which imagine what the show would be like if it were still on the air, perfectly capture the mocking "no hugging, no learning" philosophy that formed Seinfeld's core in 140 characters or less while racking up a whopping 1.2 million followers.
Twenty-five years later, it is not hyperbolic to say that Seinfeld is one of the most culturally important comedic works of its generation, painting an honest picture of the inextricable frustrations of modern life. The show's work is still felt in more contemporary shows like How I Met Your Mother, Arrested Development and It's Always Sunny in Philadelphia (and previously, The Office). It's best legacy, however, is Seinfeld writer Larry David's cringe-inducing HBO comedy Curb Your Enthusiasm, which takes the everyday comic absurdity and selfishness of Seinfeld to a new level as Larry David fumbles through his vain life offending absolutely everyone.
The show that was supposedly about "nothing" was, in fact, about everything. "Look around, life is full of characters," its creators seemed to be telling us. "There are more Georges, Kramers, Elaines and Newmans around you than you know, and the world itself is much, much stranger than you give it credit for."


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Have a client that's claiming complied C is harder to reverse engineer than sudo "compiled" Perl byte-code, or the like. Anyone have a way to prove, or disprove this?
I don't know too much about perl, but I'll give some examples why reversing code compiled to assembly is so ugly.
The ugliest thing about reverse engineering c code is that the compilation removes all type information. This total lack of names and types is very the worst part IMO.
There is plenty of other ugly stuff. Such as whole program optimization using different registers to pass parameters every time. Functions being inlined so what was one a simple function appears in many places, often in slightly different form due to optimizations.
The same registers and bytes on the stack get reused by different content inside a function. Gets especially ugly with arrays on the stack. Since you have no way to know how big the array is and where it ends.
Then there are micro-optimizations which can get annoying. For example I once spend >15 minutes to reverse a simple function that once was similar to
Perl is really easy to reverse engineer. The tool of choice is vi, vim, emacs or notepad.
That does raise the question about why they're worried about reverse engineering. It is more difficult to turn machine code back to something resembling the original source code than it is byte-code normally but for most nefarious activities that's irrelevant. If someone wants to copy your secrets or break your security they can do enough without turning it back into a perfect representation of your original source code.
Reverse engineering code for a virtual machine is usually easier. A virtual machine is typically designed to be an easy target for the language. That means it typically represents the constructs of that language reasonably easily and directly.
If, however, you're dealing with a VM that wasn't designed for that particular language (e.g., Perl compiled to the JVM) that would frequently put you back much closer to working with code generated for real hardware -- i.e., you have to do whatever's necessary to target a pre-defined architecture instead of designing the target to fit the source.
Ok, there has been suficient debate on this over the years; and mostly the results are never conclusive ... mainly because it doesn't matter.
For a motivated reverse engineer, both will be the same.
If you are using pseudo exe makers like perl2exe then that will be easier to "decompile" than compiled C, as perl2exe does not compile the perl at all, it's just a bit "hidden" (see http://www.net-security.org/vuln.php?id=2464 ; this is really old, but concept is probably still the same (I haven't researched so don't know for sure, but I hope you get my point) )
I would advise look at the language which is best for the job so maintenance and development of the actual product can be done sensibly and sustainably.
Remember you _can_not_ stop a motivated adversary, you need to make it more expensive to reverse than to write it themselves.
These 4 should make it difficult (but again not impossible)...
[1] Insert noise code (random places, random code) which does pointless maths and complex data structure interaction (if done properly this will be a great headache if the purpose is to reverse the code rather than the functionality).
[2] Chain a few (different) code obfuscators on the source code as part of build process.
[3] Apply a Software protection dongle which will prevent code execution if the h/w is not present, this will mean physical access to the dongle's data is required before rest of the reversing can take place : http://en.wikipedia.org/wiki/Software_protection_dongle
[4] There are always protectors (e.g. Themida http://www.oreans.com/themida.php) you can get which will be able to protect a .exe after it has been built (regardless of how it was compiled).
... That should give the reverser enough headache.
But remember that all this will also cost money, so you should always weigh up what is it that you are trying to achieve and then look at your options.
In short: Both methods are equally insecure. Unless you are using a non-compiling perl-to-exe maker in which case native compiled EXE wins.
I hope this helps.
C is harder to decompile than byte-compiled Perl code. Any Perl code that's been byte-compiled can be decompiled. Byte-compiled code is not machine code like in compiled C programs. Some others suggested using code obfuscation techniques. Those are just tricks to make code harder to read and won't effect the difficulty in decompiling the Perl source. The decompiled source may be harder to read but there are many Perl de-obfuscation tools available and even a Perl module:
Perl packing programs like Par, PerlAPP or Perl2exe won't offer source code protection either. At some point the source has to be extracted so Perl can execute the script. Even packers like PerlAPP and Perl2exe, which attempt some encryption techniques on the source, can be defeated with a debugger:
It'll stop someone from casually browsing your Perl code but even the packer has to unpack the script before it can be run. Anyone who's determined can get the source code.
Decompiling C is a different beast altogether. Once it's compiled it's now machine code. You either end up with Assembly code with most C decompilers or some of the commercial C decompilers will take the Assembly code and try to generate equivalent C code but, unless it's a really simple program, seldom are able to recreate the original code.