text:
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What should I be doing instead of this?
by Nick Swartsell
Posted In:
at 09:35 AM |
Morning News and Stuff
Cincinnati-Chicago high speed rail gets more boosters; VLT auction under investigation; Kasich says part of the ACA helped people... but we should repeal the ACA
Good morning y'all! Here's a quicker than usual rundown of the day's news before I jet for an interview. There is yet another version of the Union Terminal restoration deal being passed around. The deal, which Hamilton County Commissioners are expected to vote on soon, doesn't make many changes to the sales tax hike on the November ballot, but would hold the Cincinnati Museum Center responsible for any cost overruns the project might incur while allowing its leaders to seek financing for the project. Voters will still have to approve the .25 percent sales tax increase before that deal would go into effect.• VLT Academy might be gone, but there's at least one more bit of turbulence related to the troubled former charter school. VLT closed in August after losing its sponsoring organization, required by Ohio law, and falling behind on its rent. It seems computers sold at an auction to pay off the school's debts may not have been scrubbed of private personal information. The Ohio Department of Education says it has launched an investigation to make sure that information was erased properly and didn't fall into the wrong hands.• The push for a high-speed rail route between Chicago and Cincinnati has gained more supporters. The mayor and city manager of Hamilton recently sent a letter to OKI, the region's planning office asking for the office to fund a feasibility study for the potential project. They join Hamilton County Commissioners, who voted in September to request that study. The rail line could have big economic benefits, but would also be a huge, long-term undertaking. • Speaking of transit, you can tell the Ohio Department of Transportation what you'd like to see in the future at a public discussion from 10 a.m. to 12 p.m. on Oct. 31. Yes, that's in the middle of a workday. It's also in Lebanon for some reason, which you can't really get to by public transit. That has some people kind of miffed. The meeting is for the entire Southwestern Ohio region, ODOT says, and that's why it has to be held in a central location. Come on, guys, you couldn't have two meetings in Dayton and Cincinnati on a couple Saturdays? I'll bring the donuts and coffee. Anyway, the event is part of a statewide outreach effort by ODOT to get input about transit options in the state. Meetings have also been conducted in Columbus, Cleveland, Athens and Findlay.• An Ohio man arrested in North Korea in May finally returned home today. Officials in the isolated country detained Jeffery Fowle after leaving a bible in a nightclub there. He was held until recently on charges of Christian evangelism, a crime in North Korea. His release might have been hastened by repeated appeals by President Obama to North Korean leader Kim Jong Un. • We've reported a bit about Common Core in the past. Controversy continues over the new federal academic standards, and the fight is coming to the state board of education elections. Seven candidates are running for election to the 19 member board, and several of them have made repealing the standards a key point in their campaigns. Mary Prichard, who is running to represent Butler, Preble, Montgomery and Miami Counties on the board, has made the issue the centerpiece of her candidacy. She calls the standards "a government takeover." Zac Haines, running to represent Hamilton and Warren Counties, has promised to work to repeal them in the state. His opponent, Pat Bruns of Price Hill, supports the standards. Ohio is one of 40 states to implement Common Core.• Wait. Did Gov. John Kasich really say that? He did, and he didn't. The Associated Press reports that in a speech Monday, Kasich said a repeal of President Obama's Affordable Care Act is "not gonna happen." Then Kasich, either backtracking or clarifying, ran them down and asked the AP to make a correction. He was only referring to the Medicaid expansion of the ACA, he said. That's been a controversial issue all its own, with many conservative governors refusing to take the federal dollars to increase eligibility for residents of their states. Kasich did take the money, though, which has helped hundreds of thousands of Ohioans get medical coverage. Kasich's correction is a bit of a small distinction, since most conservatives roll the ACA up in one big, evil ball. Rejecting the Medicaid expansion has been something of a litmus test for conservative governors. But Kasich has not only taken it, he's praised the program. Opposition to expanding Medicaid, which governors like Texas' Rick Perry have worn like a badge of honor, "was really either political or ideological," Kasich said in the same speech. "I don't think that holds water against real flesh and blood and real improvements in people's lives." That alone is a noteworthy thing for a conservative governor to say. But have no fear, Kasich still hates the program, saying in his clarification that it "can and should be repealed." Wait, even the part you said helps people?
by Jac Kern
Posted In:
at 12:15 PM |
I Just Can't Get Enough
The remaking and re-imagining of classic films and TV shows is often met with high expectations and harsh reviews. Despite this, I was really looking forward to A&E's new horror-drama, Bates Motel. Something of a warped prequel to Psycho, the thriller places a young Norman Bates and his mother Norma in charge of a previously foreclosed motel in a contemporary setting. With the swoon-worthy Vera Farmiga (big sis to American Horror Story's Violet, Taissa Farmiga) starring as the mother to the future sociopath (who is portrayed by creepy-yet-cute Freddie Highmore), I really thought it was going to be awesome. It wasn't. Check out my full reaction in this week's TV column. I know I should have lowered my expectations — prequels generally suck — but I was really pulling for this one. Sadly, I've felt more suspense in an episode of A&E's Intervention that in this show where multiple people were murdered in the premiere. Dammit, Bates Motel, I was rooting for you! Popular restaurant recommendation site Urbanspoon recently listed the most buzzed about bar-n-grills across America and Cincinnati topped the list with seven restaurant-bar mentions — matched only by Chicago, New Orleans and St. Louis. The restaurants include A Tavola, Adriatico's Pizza, Bakersfield OTR, Nada, Senate, Taste of Belgium Bistro and Terry's Turf Club. With Covington's Wunderbar bringing the local count up to eight, it looks like Greater Cincinnati is the place to go for beers and bites! Usually when my mom shares with me something she found on the Internet, it's either a pug photo shoot on YouTube or an MSN slideshow of inappropriate advertisements, but recently she sent me something even better. Check out this informational North Korean documentary footage of American life: Ah, America: Where there aren't any birds, except for the ones we all ate yesterday. Just a reminder, next time you order your snow coffee, make sure to ask if it's local. Thanks for the cake, North Korea! So the Catholics got a new pope last week. Remember: There's always money in the Vatican! Usually when I hear "Satan" and "Obama" in the sentence, I quickly tune out whichever Fox News zombie or disgruntled family member is ranting, but this week the two were compared for a new reason. The History Channel's incredibly factual miniseries The Bible obviously features the devil, an important supporting character from the original masterpiece, but some people are upset about the resemblance to our president. Check it out for yourself here. The Princess Bride is a classic, but what if little Fred Savage's grandpa gave him another book instead? If the kid hated all that kissing in PB, I can only imagine what he'd think of GOT's uh, adult scenes.Hey remember my American Horror Story Season Three guesses? AHS: Coven = confirmed. Witches! Squee!
by Steven Rosen
Posted In:
Music News
at 09:13 AM |
Come Hear Your Favorite North Korean Folk Songs at the Library
Under Steve Kemple, music reference librarian in the Popular Library, downtown's Main Library has begun doing some fascinating free programming to highlight the depth of its music collection — and just music in general. It already has an Experimental Music at the Library series, featuring live events such as a band from Oakland (Horaflora) that plays grapefruit, electric toothbrushes and balloons. At 7 p.m. on March 20, Hadron Collider will pair psychedelic light projections with feedback and drone noises. But coming up first, the spotlight is on another of Kemple's ongoing music programs at the Main Library — Listen to This! — for which an audience is invited to listen to and discuss albums from the Library's collection. Past sessions have been devoted to Iranian music and Marvin Gaye. Next Wednesday from 7-8:30 p.m., Listen to This! features the traditional music of North Korea. So far, Kemple has only found one relevant album in the collection — North Korean Folk Songs — but it's a good one. And the hunt is on for more. No word if Dennis Rodman will attend with or without his new best friend, but you're sure to have a good time — and become well-versed on North Korean music — if you do. The program will be held in the first-floor Popular Music Lounge. Kemple's creative programming was just written up in the Library Journal.Go here for more information.
by Kevin Osborne
Posted In:
State Legislature
LGBT Issues
Foreign Relations
at 08:01 AM |
Morning News and Stuff
A major roundup of people suspected of committing violent crimes in Cincinnati continues today. On Thursday, police announced they had arrested 30 people and confiscated more than 200 guns in raids in neighborhoods including Avondale, Madisonville, Price Hill, Walnut Hills and elsewhere. Cincinnati police are being assisted in the effort by the Bureau of Alcohol, Tobacco and Firearms, and Police Chief James Craig said the sweep would be ongoing for the next few days. About 100 additional suspects are being sought.A 52-year-old woman who hasn't been able to speak for her entire adult life has now found her voice. Jan Christian recently completed a series of seven operations on her larynx to restore her speech at University Hospital. When she was 17, Christian was in a severe automobile accident in which she was thrown forward and hit her throat on the dashboard. She also broke her neck in four places.Kentucky has changed a law so Amish people can drive their horse-drawn buggies without committing a crime. Gov. Steve Beshear signed a bill into law Wednesday that allows the Amish to use reflective silver or white tape on their buggies rather than the traditional fluorescent orange signs that makes the buggies more visible to approaching motorists. Some Amish farmers in western Kentucky had served jail time for refusing to use the emblems. They said the triangular shape represents the Trinity, which they are not allowed to display, and that the fluorescent orange calls undue attention to them against the norms of their religion.In celebration of National Hug Day (yes, that's a real thing), several students from Xavier University will give free hugs on downtown's Fountain Square today. About 20 students will flock to the square between 11 a.m. and 2 p.m., holding up signs that read, "free hugs." Oddly, National Hug Day actually is celebrated on Jan. 21. Well, people always say Cincinnati is a little bit behind the times.Two Kentucky men have been charged with a federal hate crime in an attack against a gay man last year, marking the first time the law has been applied in a case involving a victim's sexual orientation. The U.S. Attorney's Office in Lexington announced the charges against two Harlan County men on Thursday. A statement said David Jason Jenkins and Anthony Ray Jenkins were indicted in an April 2011 attack on a gay man in an eastern Kentucky park.In news elsewhere, U.S. and Asian leaders are worried that North Korea's failure to launch a rocket into orbit Thursday will prompt the nation to take some sort of aggressive action in an attempt to restore its honor. The most common fear is that the secretive, authoritarian regime will conduct a nuclear test, which could heighten tensions with South Korea and Japan. The botched launch was supposed to carry a satellite into orbit for weather observation, as the centerpiece of a national holiday weekend to honor the birth of the nation's founder, Kim Il Sung.As if that's not troubling enough, the Russian military anticipates an attack will occur on Iran by summer and has developed a plan to move Russian troops through neighboring Georgia to stage in Armenia, which borders on the Islamic republic. Dmitry Rogozin, who recently was the Russian ambassador to NATO, warned against an attack on Iran. "Iran is our neighbor," Rogozin said. "If Iran is involved in any military action, it's a direct threat to our security."A United Nations team of military observers is ready to deploy to Syria to begin a monitoring mission as soon as the Security Council approves its mission, which could be later today. The team is standing by to begin overseeing a tenuous but apparently stable ceasefire, which is now in its second day. Protests in the wake of that ceasefire have broken out across the nation, and government forces have responded by firing into the air, reportedly killing one protester, activists alleged.Apple Inc. is rejecting the U.S. Justice Department's allegations that it colluded with publishers over electronic book pricing, calling the charges "simply not true." The U.S. government this week sued Apple and five publishers, saying they conspired to fix the prices of electronic books. It has reached a settlement with three of the publishers that could lead to cheaper e-books for consumers.The mayor of Newark, N.J., was taken to a hospital Thursday night for treatment of smoke inhalation he suffered trying to rescue his next-door neighbors from their burning house. Cory Booker arrived home when he saw flames and smoke from the second floor of the building next to his home, and no residents outside. Booker rushed in and his security detail followed. Guards rescued two people on the first floor, while Booker rescued a woman on the second floor. No serious injuries were reported. (Mark Mallory, you need to step up your game.)
Worst Week Ever!
May 19-25: Worst Week Ever!
Danny Cross
0 Comments · Wednesday, May 26, 2010
We at WWE! are admittedly afraid of many things: Rollercoasters, angry PR representatives and our fathers after Bengals games are all pretty high on our lists of things to avoid. But there is one entity that scares us so badly even the mention of its name strikes fear into the most brave part of our hearts: North Korea.
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text:
a place for zinesters - writers and readers
a group for all the horror zinesters out there.....xo
Members: 115
Latest Activity: Apr 8
Started by Aspire Feb 12, 2013.
Started by Hannah Neurotica Dec 5, 2010.
Started by Jeani Rector Dec 2, 2010.
Issue 18 of Necronomicon fanzine is out now on Etsy http://www.etsy.com/shop/NecroNeil plus all the back issues of the last ten years have been reprinted.
Again, manic ramblings about mostly retro horror films in an old skool cut and paste fashoin. Always looking for contributions, anything personal relating to horror is perfect!
Hello there!
Le Stoner's Digest finally got its first issue! You can get it right there in my Etsy shop : http://www.etsy.com/shop/inoxid
In a few words, it's a fiction zine with 5 greasy stories of stabwounds and psychotic maniacs.
Not licking your fingers yet? Well here's the whole drill :
"Le Stoner's Digest is a new fiction zine written by two french dudes ( with some help from Displaced Snail's very own J. Carlough!). It is sleazy, violent, fun, what can i say, it's PULP as FUCK.
First issue is about big knives and psycho killers, and you should not let your kids read it. I mean, seriously, why would you give them some cheap-ass zine when they could be entertaining themselves with Cosmopolitan or some cool mag with high-end cars and big boobs?
Contains 5 profanity-littered original stories, and plenty of illustrations. 32 A5 pages of gorgeous 120g paper, with a manly 200g cover, and the supplement is a short story by Phillibert Mossberg printed on that awesome but weirdly formatted paper i once found in the street in Paris. True story!"
Necronomicon issue 17 is now out at Etsy http://www.etsy.com/listing/68183145/necronomicon-issue-17-uk-horro...
Its my manic diary through watching horror films, mostly ones from the 80s and 90s, ones I grew up on, films from a review book my parents kept in the 80s...Always looking for reviewers, anything horror related. Enthusiastic, nice sense of humour, informal...Give me message if you want to write something!
I'm looking to table at a show next month and I was going to see if any of you are interested in having me distro your zines. I'm looking for, well, 3-5 copies of... whatever projects you're working on (that are horror/gore related). I'm fine with paying you, or you can just donate a few if you're just wanting to get your zines out there. Or if you have any fliers/ads for your zine that you'd like me to put up, that'd be great too! My e-mail is crochetsrebellion(at)gmail.com. Please get in touch!!! I really appreciate it!

subset: commoncrawl


text:
The prophets of doom have been insisting that America's youth are so caught up in their tech toys that they have no interest in the important issues of the day, know little about our political system, and care even less.
Those doomsayers should have been at Burlington Township High School last week when more than 40 young women proved otherwise.
A special event, called "Running and Winning," and sponsored by the League of Women Voters of Burlington County, gave the group of female students a look at the political process, with visits from many women leaders in the morning, then set them loose to do a bit of campaigning and debating on a hot issue in the afternoon.
The event also was co-sponsored by the American Association of University Women (Medford Branch) , Alice Paul Institute, South Jersey NOW (Alice Paul Chapter) and The Links, Inc. (Rancocas Valley Chapter).
Morning speakers included Burlington County Freeholder Aimee Belgard, a Democratic candidate for the Third District Congressional seat; Burlington County Sheriff Jean Stanfield; Cinnaminson Committeewoman Kathy Fitzpatrick; Westampton Mayor Carolyn Chang; and Rovena Overton, an Eastampton Councilwoman, among many others.
"I wasn't sure what it would be like, but it's been amazing," said Jasmine Knight, 17, one of the participants. Knight, a senior who serves as vice president of the school's Student Council, already has experienced an enrichment program at Stanford University in a program called "Lead America," and will be attending the University of Alabama next year.
"I know that some men think women's opinions are not very valuable," said Jasmine, who finds that attitude troubling. "Frankly, I think the country would be in good hands with a woman president who has the skill and perspective to lead us to some important changes."
And does Jasmine believe that she will see a woman president in her lifetime? "Definitely!"
That attitude was clear as the young women students expressed thoughts about their reaction to the notion of women in leadership roles.
"Right now, being in politics is not in my future plans," said Jessica Hlay, 18, who has her heart set on animal sciences. "But a lot could change, and I found the issue of wage equity especially important when it comes to women. That really came out in today's discussions."
Indeed, it was a day for looking at womens' lives through the job and wage equity issue (equal pay for equal work) and thinking more about politics than just about running for office.
For Marcy Rosner of Moorestown, a member of the League of Women Voters of Burlington County and chair of its Running and Winning Committee, it was a day of excitement and satisfaction as the young women proved their mettle by working in groups on a issue to which they had just been oriented: Should possession of small amounts of marijuana by decriminalized, legalized, or neither in New Jersey?
That matter is actually under consideration in the state Legislature.
While their real counterparts in the Legislature are given plenty of time for research and preparation, these young women had less than a day to frame their arguments.
Remarkably, the small groups were able to formulate and present cogent arguments for all three positions. As it turned out, leaving things as they trailed well behind decriminalization or legalization of marijuana in the final analysis.
"These young women learned to work in teams to process ideas and arguments and to do the kind of public speaking that often terrifies adults," said Rosner, as the teams, armed with colorful and inventive posters containing slogans, presented their points of view.
Senior Alexis Arnell, who is off to American University to study combined communication, law, economics and government, felt that the Running and Winning event was an example of how hard work can get the job done.
"Obstacles are part of life, and maybe women do have to work harder, and smarter. But that makes us stronger in the end," said Alexis, who also is the Burlington County Farm Fair Queen, and president of Student Council.
Perhaps the most important lessons of the day were reviewed by Kris Myers, director of programming at Alice Paul Institute, who did a wrap-up with the participants.
"I think you saw today that every issue can be complex, and that public speaking can be so hard. But you also learned something about your own skill sets and also about how politics doesn't mean just running for office," said Myers, reminding the young women that artists and publicists and speechwriters can all be on the political horizon, and help to change the world.
The workbook of the day reminded the female students that "It's been 90 years since the long, persistent and difficult efforts of the suffragists won the vote for women. But women are still not fully involved in politics."
Days like this one may very well change that landscape.


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Customer Reviews
3 of 6 people found the following review helpfulMarch 15, 2008Reviewer: A customer in CaliforniaSeems like it is as low carb as regular flour. We have tried this "low carb" flour 3 times in 3 different recipes. My mom is diabetic, her blood glucose is the same after using products w/Carbalose and products with the "regular" flour. What is the point of paying 5x for this flour? Absolutely no benefits had been noticed for the people on LC or w/diabetes. Will not order again.
2 of 7 people found the following review helpfulJanuary 27, 2007Reviewer: Lloyd in ArkansasI made drop biscuits,for the first time. Not good. Perhaps I did not mix properly. mixed by hand. Taste no way close to biscuit.
0 of 1 people found the following review helpfulMarch 10, 2010Reviewer: Doug in MichiganI have been low-carbing for 5 years and I have no tolerance (taste wise) for this flour. It seems different people have different thresh-holds for "that taste" but even 25% of this flour in a recipe causes it to be inedible for me.
Very, very disappointing.


text:
|Número de publicación
|Tipo de publicación
|Número de solicitud
|Fecha de publicación
|31 Mar 1998
|Fecha de presentación
|12 Dic 1995
|Fecha de prioridad
|12 Dic 1995
|También publicado como
|Número de publicación
|Allan Robert Bertolet, Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser, III, Timothy Shawn Reny, Terrance John Zittritsch
|Cesionario original
|International Business Machines Corporation
|Exportar cita
|BiBTeX, EndNote, RefMan
|Citas de patentes (14), Citada por (17), Clasificaciones (5), Eventos legales (8)
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet
This application relates to commonly-owned previously filed U.S. patent applications:
1. Ser. No.: 08/460,481, filed Jun. 2, 1995, entitled "PROGRAMMABLE LOGIC CELL;" now U.S. Pat. No. 5,646,546, Jul. 8, 1997.
2. Ser. No.: 08/459,156, filed Jun. 2, 1995, entitled "PROGRAMMABLE ARRAY CLOCK/RESET RESOURCE;" now U.S. Pat. No. 5,652,529, Jul. 29, 1997.
3. Ser. No.: 08/460,420, filed Jun. 2, 1995, entitled "PROGRAMMABLE ARRAY I/O-ROUTING RESOURCE;"
4. Ser. No.: 08/459,579, filed Jun. 2, 1995, entitled "PROGRAMMABLE ARRAY INTERCONNECT NETWORK;" now U.S. Pat. No. 5,631,578, May 20, 1997.
5. Ser. No.: 08/488,314, filed Jun. 7, 1995, entitled "CONTINUOUS ADDRESS STRUCTURE WITH FOLDING;" and
6. Ser. No.: 08/528,177, filed Sep. 14, 1995, entitled "METHODS AND SYSTEMS FOR IMPROVING MEMORY COMPONENT SIZE AND ACCESS SPEED, INCLUDING SPLITTING BIT LINES AND ALTERNATE PRE-CHARGE/ACCESS CYCLES."
The section entitled "Description of the Preferred Embodiment(s)," and the drawings, from each of the above-referenced related U.S. patent applications are hereby expressly incorporated herein by reference.
This invention relates in general to integrated circuit design and fabrication, and more particularly to automated placement and routing for layout and schematic generation for a family of integrated circuits having varying sizes.
Integrated circuit ("IC") design and fabrication often involves a transfer of digital information from a circuit designer to fabrication facilities or foundries. The circuit designer must prepare a digital representation of circuit layout information in a format suitable for use by the foundry. Circuit designers also often use such digital circuit representations internally for automated schematic generation for verification and/or test of proposed circuit designs.
However, the current process by which circuit designers generate such digital representations from customer specifications is primarily manual in nature. The circuit designer must first manually design an appropriate circuit to meet a customer's functional and timing specifications. A designer must then manually lay out, or place and wire, the requisite components of a proposed circuit in an area and location of silicon which is commensurate with the customer's specifications. Computer-aided-design tools are currently available which facilitate this design process, however, the majority of the task is still very much a manual undertaking.
The customer specifications may also include fabrication of scaleable integrated circuit architectures. Field programmable gate arrays ("FPGAs") are an example of an architecture which may be considered scaleable or growable. At the device level, FPGAs are heterogeneous in nature, i.e., they are not comprised of a pure repetition of a single type of circuit. FPGAs rather comprise a multitude of different circuit types, which when viewed at higher levels of circuit type grouping, may be considered repetitive or scaleable. For example, a sector of FPGA logic cells may be defined as an M×N grouping of logic cells. A customer may require a family of ICs having 3×3, 5×5, 7×7, 9×9 . . . sectors. A customer may therefore specify that the same basic building blocks of an FPGA (e.g., a sector) be provided, but that multiple ICs be made available having a range of sizes measured in sectors. Multiple FPGA sizes may comprise an IC "family" which is often a useful way to market FPGAs to a user base.
However, from the standpoint of a circuit designer, an FPGA must be considered a collection of generally disparate circuit types (logic cells, interconnect, repeaters, etc.), because of the complexity and wiring requirements of each of these circuit types. To support fabrication of an FPGA family, multiple transfers of digital information to the foundry are required, one such transfer for each IC size. Using the known circuit design techniques discussed above, a primarily manual layout or place and wire procedure is necessary for each IC size. Thus, despite the apparent repetitive nature of FPGA circuits when viewed at higher levels, a designer must perform manual place and wire techniques for each IC size.
A method and system are thus required which automate the process by which a family of heterogeneous ICs can be designed and fabricated without unduly burdensome repetition of manual design and place and wire procedures.
The shortcomings of the prior art are overcome and additional advantages provided by the present invention, which in one aspect is a method for heterogeneous array design including defining a plurality of column circuit types, each column circuit type having associated therewith a column width, at least two of the column widths being different, and defining a plurality of row circuit types, each row circuit type having associated therewith a row height, at least two of the row heights being different. The pluralities of row and column circuit types are allocated to respective row and column regions in the array. The allocated pluralities of row and circuit types thereby form a plurality of intersecting regions across the array. Circuits are arranged into kernels corresponding to respective intersecting regions, according to the width of the column circuit type and the height of the row circuit type which form the respective intersecting regions.
The method may further include placing each respective arranged kernel in the array according to a two-dimensional coordinate system having an origin. A first coordinate is determined as a function of the widths of the allocated column types between the origin and the respective intersecting region. A second coordinate is determined as a function of the heights of the allocated row types between the origin and the respective intersecting region.
The step of placing the arranged kernels may be repeated for each member of a family of heterogeneous arrays, each member being generally characterized by the number and types of row and column circuit types allocated thereto. In this respect, the present invention provides an automated place and route, and layout and schematic generation technique, for designing differently sized members of an array family.
In another aspect of the invention, a method and system are provided for placing a plurality of kernels in a heterogeneous array, the array being characterized by a plurality of columns, each column having a column circuit type, and a plurality of rows, each row having a row circuit type. The method and system include describing a plurality of kernel types, the plurality of kernels being grouped within the kernel types of the plurality of kernel types. At least one kernel type is generally defined by the intersection of a column having a given column circuit type and a row having a given row circuit type. At least one kernel placement position is calculated for a kernel of the at least one kernel type. The placement position is calculated as a function of the location in the array of the column having the given column circuit type and the row having the given row circuit type.
Kernel positions for all remaining kernels of the at least one kernel type may be calculated, the number of remaining kernels of the at least one kernel type being determined as a function of the number in the array of each row and column circuit type by which the at least one kernel type is defined. Further, kernel positions for the kernels of the remaining kernel types may be calculated, the number of kernels of each remaining kernel type being determined as a function of the number in the array of each row and column circuit type by which the respective kernel type is defined.
A first coordinate of the calculated placement position and a second coordinate of the calculated placement position may correspond to distances from an origin in a two-dimensional coordinate system used to lay out the array. In this case, the calculating includes determining, for the first coordinate, the number, type and width of any columns between the column and the origin; and determining, for the second coordinate, the number, type and height of any row between the row and the origin.
The heterogeneous array may comprise a plurality of logic cells partitioned into sectors, each sector being defined by the intersection of a plurality of adjacent columns and a plurality of adjacent rows, the plurality of adjacent columns having a given sequence of column circuit types and the plurality of adjacent rows having a given sequence of row circuit types. In this case, the providing and calculating placement positions are repeated for each member of a family of heterogeneous circuit arrays, each member of the family being generally characterized by the number of sectors therein.
In yet another aspect of the invention, an architecture for a family of differently sized programmable arrays is provided. Each member of the family has a plurality of logic cells and support circuitry therein. The logic cells are arranged in four sections, and the support circuitry is generally distributed throughout a cruciform-shaped region generally centered in the array and which defines the four sections of logic cells. The length of the arms of the cruciform and the sizes of the sections can be together varied to produce the differently sized members of the family of programmable arrays.
By employing the methods and systems of the present invention, a family of heterogeneous ICs can be designed and fabricated without repetition of manual design and place and wire procedures. Layout and schematic generation is automated for each member of the IC family.
The subject matter regarded as the present invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the following detailed description of preferred embodiment(s) and the accompanying drawings in which:
FIG. 1 depicts a 7×7 sector member of an FPGA family designed and fabricated according to the principles of the present invention;
FIG. 2 depicts the row and column types for a 3×3 sector FPGA defined in accordance with the principles of the present invention;
FIG. 3 is a flow diagram of the procedure employed to produce layout and schematics for a single member of an IC family in accordance with the principles of the present invention;
FIG. 4 is a flow diagram of the procedure employed to place the kernels within each kernel type according to the principles of the present invention; and
FIG. 5 depicts an exemplary workstation environment within which the principles of the present invention can be implemented.
Layout and schematic generation has been a primarily manual task for each member of a family of ICs. The present invention provides a technique which automates this task. Row and column circuit types are defined and allocated across an array. Circuits are arranged into kernels in the regions formed by row and column intersections. The number and sequence of row and column circuit types is used to automatically locate each kernel. Using these techniques, layout and schematic generation can be automatically performed for an arbitrarily sized IC. FPGAs are disclosed herein as an exemplary type of IC for which these techniques can be used.
FIG. 1 depicts an FPGA 10 designed and fabricated in accordance with the principles of the present invention. Array 10 represents one member of a family of FPGAs to be made available to customers or users. Array 10 is a 7×7 sector member of a family which may include a 3×3 sector member, a 5×5 sector member, etc.
The array can be generally characterized as a symmetrical array of logic or core cells 18 which are grouped into sectors 20. Therefore, at this high level, it is apparent that the family of arrays can be described in terms of the number of sectors in each linear dimension. However, as discussed above, and as disclosed in detail in the commonly-owned related applications above, the array is in fact a heterogeneous array comprising a variety of subsystems including the logic cells, clock/reset resources, interconnect resources, etc., most of which are not discernable upon examination of FIG. 1. The term "array" denotes either the entirety of the circuits on a single IC chip, multiple IC chips, or could denote merely a portion of circuits of a larger circuit.
FIG. 1 also depicts a central region 12 within which support circuitry is contained for the array. The horizontal region 12 can be complemented with a similar vertical region (not shown) which together form a cruciform imposed on the array. Around the perimeter of the chip are placed I/O regions 14 and 16. The circuits forming these I/O regions are disclosed in the above-referenced related application entitled "PROGRAMMABLE ARRAY I/O-ROUTING RESOURCE."
Members of an FPGA IC family are designed in accordance with the principles of the present invention using layout and schematic building blocks or kernels. The kernels are placed and wired using procedures (discussed below) to produce the completed IC. The kernels are generally common to all ICs of the family. Multiple IC sizes can be created using the procedures discussed below in connection with FIGS. 3 and 4. The place and wire procedures automate the process of producing multiple members of a family of IC chip sizes based on the same set of kernels by taking as an input parameter the chip size and placing and wiring the appropriate kernels to produce the desired IC size. The output of the place and wire procedure is completed layout and schematic IC data, for subsequent use by the fabrication facility and the designer for verification/test.
With reference to FIG. 2, shown therein is an exemplary 3×3 sector member of a family of arrays provided in accordance with the principles of the present invention. The circuits comprising the array 40 are shown generally grouped into column or row types. Thus, the IC is divided into column and row regions within which are allocated column and row types of circuits. Column widths are not the same across columns but are constant for the entire height of any one column. Row heights are not the same across rows but are constant for the width of any one row.
The array 40 depicted in FIG. 2 is designed with five column/row types defined in accordance with the invention. The column/row types are:
CoreCellQuad: CoreCellQuad columns and rows contain data for a 4×4 array of core cells. This is referred to as a four cell quadrant. The number of CoreCellQuad type columns/rows varies with IC size requirements.
Repeater: Repeater columns and rows contain repeater data. Repeaters are structures in the interconnect resource which buffer, re-direct, and re-drive interconnect signal data. The number of repeater type columns/rows varies with IC size requirements.
Jumper: Jumper columns contain jumper data and jumper rows contain jumper data and sector clock circuitry. Jumpers are also part of the interconnect network and effect connection between interconnect wires. Sector clock circuitry includes circuitry employed to distribute reset and clock signals to core cells. The number of jumper type columns/rows varies with IC size requirements.
IO area: IO area columns and rows contain input/output blocks, input/output routing and outermost repeater data. All IC sizes likely have two IO area columns (left and right perimeter edges) and two IO area rows (top and bottom perimeter edges).
Cruciform: There is one cruciform column and one cruciform row for each IC. The cruciform column contains word line drivers, dedicated IO and configuration logic. The cruciform row contains bit line drivers, global clock circuitry and dedicated IO.
The sequence of column types from left to right for the array shown corresponds to the sequence of row types shown from top to bottom, although this not a requirement of the invention for other arrays.
IO area rows 42 and 44 are depicted in FIG. 2. IO area columns 46 and 48 are also depicted in FIG. 2. Cruciform areas 50 and 52 are depicted, and intersect in region 54. The remaining types of columns or rows are depicted and labeled as they occur throughout the embodiment of this particular array. Sector 60 is formed from intersections of the sequence of rows 56 and the sequence of columns 58.
One aspect of the present invention is evident upon an examination of FIGS. 1 and 2. The cruciform region contains four "arms" which extend from the center of the array. The support circuity disposed in this region can support a scaleable architecture because the length of each arm (e.g., the number of bit line or word line drivers) can be expanded outward. The expansion of these arms does not interfere with the outward expansion of the sectors. Thus, the expansion of the four sector regions defined by the cruciform, and the cruciform itself, contribute to the overall scaleability of the architecture.
The IC layout and schematic information is generated in accordance with the present invention by placing kernels at the intersections of the columns and rows. Columns and rows can thus be considered as segmented by the type of kernel being placed therein. For example, a column where the kernel placed is a repeater, is a repeater column, or if the kernel is a jumper, it is a jumper column. Kernel 64 represents the intersection between a CoreCellQuad column and a jumper row. Similarly, kernel 62 represents the intersection between a CoreCellQuad column and a CoreCellQuad row. Thus, the overall number of kernels in the IC is simply a multiplication of the number of rows times the number of columns. However, many of the kernels can be grouped into kernel types based upon the intersection of common types of columns and rows. As an example, since there are five column types and five row types in this exemplary embodiment, there are twenty-five different kernel types with twenty-five distinctive shapes. Thus, kernels 64, 66 and 68 can be grouped into a common kernel type because they all represent the intersection of a CoreCellQuad column with a jumper row. The placement procedure, discussed below, cycles through all column and row intersections for a given kernel type and processes, i.e., places and wires, the appropriate kernel for that intersection. As the IC sizes change, columns and rows are simply added and subtracted from the chip in a known sequence. However, the place and wire procedure remains automated.
The IC's logical architecture is designed to allow logical elements to be grouped into physical blocks. These blocks are located in repeatable patterns around the chip. The repeatable patterns are based on the kernel columns and rows. The physical size of each kernel type is determined by the width of the column where it will be placed and the height of the row where it will be placed. As an example, at the intersection of a CoreCellQuad column and a repeater row, the kernel 70 placed there must have the width of four core cells and height of one repeater. This is a design constraint in force when the kernel types are developed.
Kernels are designed using industry standard techniques. Manual entry is the primary method utilized. A few kernels are designed using high level descriptions and automatic place and route tools. Kernels types may have multiple versions therein. An additional version of a kernel type is required if small changes are required to be made to a kernel within the kernel type based on its particular placement location. Examples of changes prompting the requirement of multiple versions are device sizes, internal pin connections, and via placement. Device sizes are changed in kernels containing clock drivers. Internal pin connections are varied in IO kernels. Via placement is changed in the kernels connecting the IO power ring to power pads. The procedure recognizes what version should be placed and chooses the correct one.
The size and location of the columns and rows are critical design characteristics in the physical architecture of the chips, and are defined primarily by user or customer requirements. Once known, the location of any column and row intersection can be calculated knowing the sequence of column/row types between that intersection and an origin. Also, the names of the nets that are connected to kernel pins can be calculated. This is the underlying calculation the procedure, discussed below, uses to place and wire the kernels.
The procedure accepts as an input parameter the number of sectors in the desired IC and the procedure cycles through all column and row intersections processing the appropriate kernel for each intersection. The X,Y placement location (relative to an arbitrarily placed origin) is calculated and the kernel layout and schematic instances at the X,Y location are placed. Net names are calculated for each kernel pin and the pins are appropriately labeled with the calculated net names.
The column and row sizes (i.e., widths and heights) can also be linked to packaging requirements. As columns and rows are added to the IC, more wirebond pads and solder bumps must also be added. Since the chips grow by adding sector columns and rows, and each sector may require, for example, thirteen wirebond pads, the width of a sector must equal at least the pitch of the thirteen wirebond pads. (The metal bumps for each sector require less space than the wirebond pads so they are not the critical dimension.) These are all design constraints when the column and row sizes are initially chosen. In the exemplary embodiment of FIG. 2, the width of one repeater column plus one jumper column plus two CoreCellQuad columns represents the width of a sector and therefore the pitch of thirteen wirebond pads.
Thus, the primary characteristics of the physical architecture of a desired IC are:
Column and row partitions or regions covering the entire IC;
Kernel placement and wiring at column and row intersections;
Kernel width and height matching column width and row height;
Column and row sizes linked to packaging requirements; and
Logical architecture represented as repeatable blocks that are placed in patterns around the chip.
Using these characteristics, the place and wire procedure can generate multiple sizes from the same layout and schematic building blocks (i.e., kernels).
With reference to FIGS. 3 and 4, shown therein are exemplary embodiments of the procedures for automatically producing layout and schematic data for each IC size within a family of IC sizes, according to the present invention. These procedures place and wire repeatable layout and schematic building blocks (kernels) to form the completed IC. This process can be referred to as "tiling" and the procedures can be referred to as the "tiler."
The output of the tiler procedures is layout and schematic data. Layout data is most commonly transferred to, and used by, the fabrication facility for actually fabricating the chip. Schematic data is often used by the designers for additional design tasks, including verification and/or test. Most layout connections are formed by abutments. When kernels are placed next to each other, tabs on the edges of each kernel touch and form connections. In a few cases, the tiler procedure draws wires and/or vias to form connections. For all layout connections, the tiler labels the pin net with its chip level net name. Schematic connections are formed by labelling. All pins on a kernel schematic instance are labelled with its chip level net name. Connections are formed when pins are assigned to the same chip level net name.
Those skilled in the art will recognize that the terms "place" and/or "route" encompass steps in the design process wherein a circuit is assigned a location and wiring, possibly in a software tool which produces digital dam to be provided to a fabrication facility. These terms thus are not limited to the actual fabrication process when an actual physical circuit is placed and routed in silicon.
An exemplary embodiment of a main tiler procedure is depicted in the flow diagram of FIG. 3. In step 100 "LOAD KERNEL TYPE CODE FILES," each kernel type's code file is loaded which drives a kernel type's placement and wiring. At this point, the number and physical make-up of row and column types, and therefore kernel types, has been determined by the circuit designers as set forth above. These files represent this information and are provided to the tiler for the automated place and wire step for each family member. These files are loaded each time the main procedure is loaded.
Step 102 "START TILER"0 begins the tiler procedure. Step 104 "OPEN LIBRARY" opens the library where the IC layout data is to be deposited. Its name can be the first parameter of the tiler function call. Step 106 "OPEN CHIP LAYOUT AND SCHEMATIC CELL VIEWS" opens the chip layout and schematic views wherein which the placed and wired IC data is to be deposited. The cell name may be the second parameter of the tiler function call. In step 108, "INITIALIZE GLOBAL VARIABLES," five exemplary primary layout dimensions and five exemplary primary symbol dimensions are initialized based on the exemplary five column and row types discussed above. The five primary layout dimensions are used for chip layout data, and the five primary symbol dimensions are used for chip schematic data. These values are thereafter stored in global variables for access by the following routines. Step 110, "CREATE CHIP EDGE POLYGON," simply writes some introductory information to the chip layout cell view. Those skilled in the art will recognize that steps 100-110 are exemplary only, and are merely introductory steps in the particular embodiment disclosed for preparing the processing environment for the subsequent place and route procedure.
Step 112 "FOR LOOP FOR KERNEL TYPE 1 TO END" begins a loop within which a place and wire procedure is performed for each kernel type. As discussed above, five distinct column and row types are defined for the exemplary FPGA IC disclosed herein. One can thus expect to process twenty-five different kernel types. Each kernel within the kernel type is similarly formed and represents an intersection between a given type of column with a given type of row.
Step 114, "PLACE AND WIRE KERNEL TYPE" is a procedure, discussed below with reference to FIG. 4, within which each kernel within the current kernel type is placed and wired based on the number of sectors desired for the family member being processed. This parameter may be specified in a third parameter of the tiler procedure call.
Step 116, "NEXT KERNEL TYPE" simply checks to determine whether all the kernel types have been placed and wired, and if not, returns processing to steps 112 and 114 for placement and wiring of the next kernel type.
Step 118 "SAVE AND CLOSE CELL VIEWS" and step 120 "END TILER" are conventional steps which follow completion of the place and route procedure for all kernel types.
With reference to FIG. 4, shown therein is a detailed flow diagram for step 114 "PLACE AND WIRE KERNEL TYPE" of FIG. 3. Step 200 "START" initiates this procedure. Step 202 "INITIALIZE KERNEL TYPES PIN LIST" initializes kernel version pin lists for the kernel versions within each kernel type. As discussed above, multiple kernels are usually expected to be placed while processing a kernel type, unless only one row and one column of the given type are present in the array. However, each kernel type may also have a variable number of versions based upon particular wiring requirements in a chip.
Step 204 "FOR LOOP FROM COLUMN START TO COLUMN END" initiates a loop within which columns relevant to the kernel type are processed for placement and routing of each kernel in the kernel type. If the kernel type is defined by a column type of which there is only a single occurrence in the array, this loop would merely occur only one time. Step 206 "CALCULATE KERNEL LAYOUT AND SYMBOL X LOCATIONS" calculates the X coordinates based on the current column information and primary kernel heights and widths. Thus, for each column processed in the loop, a different X location results based on the location of that column and the types of columns located between an origin defined in the chip and the current column. Thus, while only the column types relevant to the current kernel type are processed within the loop, the procedure nevertheless requires information on the overall sequence of column types between the origin and the current column in order to correctly calculate the X location.
In step 208 "FOR LOOP FROM ROW START TO ROW END" initiates a loop within which all of the rows relevant to the particular kernel type are processed. Again, if only one row is relevant, this loop only occurs one time.
Step 210 "CALCULATE KERNEL LAYOUT AND SYMBOL Y LOCATIONS" is the step within which the Y coordinates of the kernel are calculated based on the current row information and a primary kernel type's heights and widths. Again, as discussed above regarding the X locations, the procedure requires information regarding the number and types of rows between the origin and the current row.
Step 212 "CALCULATE KERNEL VERSION CELL NAME" is the step within which the cell name is calculated based on the current column and row location. (The phrase cell name is used to indicate a particular kernel version name.) The kernel name and kernel pin list variables are set accordingly. If only one kernel version exists for the current IC size, its name can be calculated before the column loop starts. In step 214 "OPEN KERNEL LAYOUT AND SYMBOL CELL VIEWS," the kernel's layout and symbol cell views are opened. Again, if only one kernel version exists for the current IC size, kernels can be opened before the column loop starts.
In step 216 "PLACE LAYOUT AND SYMBOL INSTANCE," the instance name is calculated and placed in IC layout and schematic cell views at the X and Y coordinates calculated above. (The term instance is used to indicate a particular instantiation of a cell or kernel version at a particular location. Multiple such instances may occur.) In step 218, "WIRE INSTANCE IN CHIP LAYOUT AND SCHEMATIC," layout and symbol instances are wired in the chip data. Again, most connections in the layout are linked by abutment (kernel has pads on its edge that touch corresponding tabs on adjacent kernels). In certain cases, wires and vias may be drawn. All layout instance pin nets are labelled with a chip level net name. Connections in the chip schematic are linked by labelling. A chip level net name is attached to every schematic instance port. Common net names on a port connect the ports together.
In step 220 "TEXT LAYOUT INSTANCE GND AND VDD NETS," all ground and VDD text shapes are copied from a layout kernel to the chip layout and offset by the kernel instance X,Y. In step 222 "CLOSE KERNEL LAYOUT AND SYMBOL CELL VIEWS," the kernel layout and symbol cell views are closed. If only one kernel version exists for the current IC size, the kernels may be closed after the column loop end. Steps 224 and 226 end the row and column loops, respectively. A test is performed to determine whether any additional rows or columns can be processed for the current kernel type. The procedure ends with step 228.
The tiler procedure can be repeated using a different desired FPGA size for as many family members as are desired. The tiler is thus a significant improvement over prior techniques because of the decreased amount of manual intervention required during the place and route phase of chip design for family members which can be formed from a common heterogeneous set of building blocks or kernels.
The method and system of the present invention can be implemented in many commonly known computer-aided design workstation environments. An example of one such environment 300 is shown in FIG. 5. A computer workstation 330, connected to network 320, and having standard storage devices 310 (along with internal RAM, not shown) is provided. In one exemplary embodiment, the SKILL language within Cadence "Design Framework II" is employed on a RS6000/AIX workstation. The online documents available with Design Framework II version 4.2.2, including at least: "DFW II User's Guide," Reference, "SKILL Fundamentals," 1993, are hereby incorporated herein by reference. The layout information is produced in DFII format, and can be easily converted to GDS or GL1 format, which are both digital formats suitable to transfer for fabrication facilities for IC fabrication. In addition, the schematic data may be retained by the IC designers for subsequent verification and test.
By employing the method and system of the present invention, a family of IC sizes can be designed and fabricated once basic building blocks or kernels for the family have been defined. Although the arrays involved are heterogeneous in nature, the automated methods and systems herein utilize the repetitive nature of the circuit types in order to automatically place and wire, and produce layouts and schematics for, an entire family of IC sizes with very little manual intervention.
While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the following claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.
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Stan Sakai was born in Tokyo, Japan, grew up on Hawai and settled in California. He is the creator, writer and artist of 'Usagi Yojimbo', the comic book series about a samurai rabbit wandering in an anthropomorphic 17th-century Japan. For this series, and for his drawing style, Sakai received several awards. The character Usagi proved so popular that he appeared on the animated 'Teenage Mutant Ninja Turtles' series, as well as on clothing and toys. Sakai also worked on 'Albedo', 'Critters', 'Donald Duck' and 'Turtle Soup'.
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Discover a selection of top forums gimme diva on the internet. Come to share your passion on forums gimme diva and meet other fans of gimme diva. Then, why don't you create your own forum of gimme diva ?
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SANDY, Utah — Joao Plata scored his sixth goal of the season and Real Salt Lake remained undefeated with a 2-1 victory over the Colorado Rapids in the opening match of the Rocky Mountain Cup rivalry Saturday night.
RSL (6-0-5) hasn't dropped a game in its first 11 matches this season and is the only undefeated team in Major League Soccer.
The Rapids (4-4-3) avoided the shutout with defender Drew Moor's header into the corner in the 83rd minute.
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- Purple Heart plant bed vandalized days before Memorial Day
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At Toronto FC 2, Red Bulls 0
Jermain Defoe and Luke Moore scored and Toronto FC (4-4-0) snapped its three-game losing streak with a win over New York (3-4-5).
At Timbers 3, Crew 3
Gaston Fernandez scored on a header in the 85th minute to pull Portland (1-3-7) into a draw with Columbus (3-4-4).
At FC Dallas 1, Chivas USA 1
Fabian Castillo scored in the 83rd minute and FC Dallas (5-5-2) tied Chivas USA (2-5-4) to end a four-game losing streak.
Revolution 5, at Union 3
A.J. Soares, Diego Fagundez, Lee Nguyen, Chris Tierney and Patrick Mullins scored as New England topped Philadelphia (2-6-5) for its fourth straight win. The Revolution (6-3-2) is 5-0-1 in its past six.
At D.C. United 1, Impact 1
Eddie Johnson scored in the 84th minute to lift D.C. (4-3-3) to a draw with Montreal. Jack McInerney scored in the 56th minute for Montreal (1-5-4).
• Aaron Ramsey ended Arsenal's nine-year trophy drought, scoring in extra time in the FA Cup final to clinch a 3-2 victory over Hull at Wembley Stadium.
• Atletico Madrid rallied for a thrilling 1-1 tie at Barcelona to secure its first Spanish league title in 18 years.


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Monster great white for real-ish
Earlier today I wrote a post titled "Monster shark photo is a fake/legit?" and based my initial suspicions on this photo.
What initially threw me off was the the odd torque of the fish's body, from its tail, where its underside is visible, to the angle of its head, which almost appears to be moving. But what really got me was what looked like a visible line just behind the gills — as if two different images were united, giving the body its odd twist. If that wasn't enough, The Sun had slugged this image as "Fake shark photo" (an item brought to my attention by a sharp-eyed reader of this blog).
However, then there is this photo, which definitely does look real and true, as noted by another reader. You can still see the line behind the gills, and the change in color on the shark's skin, but this might be due to the fact that this shark was caught on a drum line, apparently not far from a place named Deadman's Beach. Perhaps a cord or cable wrapped around its head and caused that very straight line.
Then there are these Australian TV reports:
And –
Given those interviews, I'd say that at the very least, this whole, 10-foot "white pointer" is actual, the photos are accurate and untouched, and something took a very big bite out of this shark while it was on the drum line. Some reports put that predator at "up to 15 feet," (the "big" bracket) while others say "6 meters," or pushing close to 20 feet ("monster" territory).
My initial assessment was off, but when such an image surfaces in the age of Photoshop then skepticism should rule, at least in part, until better photos arrive, as they have in this case.
Keep your eyes peeled for what I hope will be reports of the bite radius, data that should give a more accurate sense of size about the "monster shark" and if that over-heated appellation does truly apply. And, dear lord, don't go swimming at Deadman's Beach. What a freakin' name. . .
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[...] perhaps a shark head had been grafted onto a smaller shark body. I was wrong, however, as other reports with better details made clear that a very big great white did, indeed, bite this smaller great [...]
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I was driving my car on the higway and the battery light came on. when I got home it would not crank back up beccause the belt had popped. I replaced the belt and it still won't crank. I just here a clicking noise
by turki325 in Summerville, SC on March 20, 2011