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Skip to comments.Buffett, Gates create indelible UNL moment
Posted on 10/11/2005 6:56:11 AM PDT by stevestras
The appearance of Bill Gates and Warren Buffett at the Lied Center last week was a reminder of the fluidity in American society that allows talent and drive not birthright and connection to earn power and wealth.
Although both men came from comfortable backgrounds, neither was born to that old wealth stratum of American society that sometimes seems to be tantamount to an aristocracy.
Dressed casually, they sat on a couple of stools, cracking jokes, speaking plainly, fielding unscripted questions. They seemed like ordinary people, very normal, very knowledgeable and funny, observed Yong Zhao, a University of Nebraska-Lincoln graduate student from China.
Their appearance is an example of the sort of inspiring, indelible personal experiences that are an important part of a university education. This sort of special event even last years entertaining visit by rocker Tommy Lee fits the category is part of a full and varied campus life.
The audience of 1,800 was UNL business students. The appearance will be shared with all Nebraskans next year on NET.
Their comments veered widely from the humorous Gates admitted that colleagues at Microsoft blow him away when he plays video games like Halo 2 to the profound Buffett defined success as being loved by the people you hope love you.
If any students came to the session with a preconception that all the nations rich and powerful share the same low-tax political philosophy, they went away with a different impression.
Both Buffett and Gates said that they should pay more in taxes. The rich should bear a somewhat higher proportion than they are now, Gates said.
Im paying less than half of what I was paying years ago when I was making a lot less, Buffett said. There are people fighting in Iraq paying higher rates than mine.
Perhaps most encouraging was the belief expressed by both billionaires that everyone can help make the world a better place.
Gates suggested that students gain an exposure to living conditions in other places. Things are improving and there are places for people to jump in. Buffett told one student that she and by extension every individual changes the world every day by the way she behaves around other people.
At a time when American society seems rife with cronyism and Enron-style corruption at high levels, the comments from the two icons of business success, delivered in a relaxed, ordinary, disarming style, provided reassurance that basic American ideals endure that merit, hard work, optimism and decency can prevail.
Im paying less than half of what I was paying years ago when I was making a lot less, Buffett said. There are people fighting in Iraq paying higher rates than mine.
This irks me. Why don't these folks start a voluntary deficit reduction fund and contribute a billion, or two. Oh, that's right, their really trying to indoctrinate our young people, not solve the problem.
only the stupid, lazy, and middle class pay taxes
I was under the impression that soldiers in a forward area do not pay taxes.
They don't. Buffet is evidently unaware of this.
Half the rate is not half the taxes.
"Both Buffett and Gates said that they should pay more in taxes"
Go for it. I'm not stopping either of them and neither is anyone else. All talk and no action. Typical. But to say they pay "less tax" than foks in Iraq is just a disingenuous attempt to get taxes raised on the wealthy.
I think you are right about that.
That's true, they do not pay Federal taxes while in the combat tax exclusion zone. SS/FICA continues though.
But if you ask for a slice you'll find they're giving none away...away....away....away
The current tax code (NOT tax rates) benefits the rich. The code needs to be simplified to the point where everyone pays and there's no need to have to have an entire firm of tax accountants to shelter your wealth.
We don't pay taxes. Only the little people pay taxes. --
Leona Helmsley
"Why don't these folks start a voluntary deficit reduction fund and contribute a billion, or two"
That would be ok. I'd be happy if they just spent or invested their savings (which I am sure they do). That investing is what adds capital to the markets and allows the economy to grow...create jobs...increase earnings...and eventually bring in higher tax revenues (because of higher business/individual earnings, and not from higher rates). I'd rather have dork billionaires like Gates and Buffett invest the dollars than the U.S. government.
Yes, I do wish I was a dork billionaire.
Very beautiful and it's simply what sets America apart from the world. Unfortunately, most Americans have never lived elsewhere and they don't have a clue just how beautiful that sentence is.
What a load of %$&*! Both Gates and Buffett do NOT have to opt for every allowable deduction. They don't have to deduct charitable donations, etc.
They said they pay lower RATES on their income...not
lower taxes. Opener makes it sound like the kid in the military pays more than they do. The rest of us don't
give the huge amounts to charities that these guys do,
either. Their donations knock down their rate. The
reason Buffet and everyone else paid more taxes "years ago" is because the Dems wanted to tax everything possible to fatten their special programs. I'm no billionaire, but
I'm paying a lot less now, too. And I appreciate it!
You think these two don't have gaggles of lawyers and accountants seeking every loop hole in the tax codes? Hypocrits.
Warren, Bill do you guys have accountants? Fire them. Fire the financial advisors. Move your loot out of the shelters and into a money market. Use the short form this April.
Problems solved you pair of phoney bastards.
And is the Lied Center the real name of the place or is the writer being ironic?
People like them employ several millions of people and drive a good percentage of the economy. As much as it disturbs me I had rather give them a tax break than have to ultra wealthy stop investing. If they did watch our economy tank or be taken over by off-shore investors and make us more dependent on foreigners than we are now.
The Gates Foundation writes checks in the amount of approximately 14 million dollars per week. Thousands of schools benefit directly from Bill Gates. That's how you get your percentage rate down. There is an enormous flow of money from the wealthy but because they earn so much, they don't feel it. Then, the dems and the media guilt trip them into thinking they should be doing more - and maybe they should, but not by paying more taxes into the the government pork barrel. Foundations and grants are a much better way.
So you think that the fact "people fighting in Iraq [are] paying higher rates" is good, but when the billionaire complains about it is bad? And that those who do not approve it should make voluntary tax contribution but those who like it should keep the advantage?
No one in a "Combat Zone" pays taxes.
So you think that flat tax would be very unjust? Would you like the poll tax instead?
Although your comment wasn't directed at me, I'll chime in anyway. I find it objectionable, because for Buffett and Gates, the solution, unspoken here, is to levy punishing taxes throughout the populace and all the way up the income scale to finance various state-sponsored schemes. They're personally far beyond caring, themselves.
Their real issue isn't the inefficiency or irregularity of the tax code that lets their clever accountants achieve a lower rate, but their desire to increase the level of government involvement throughout the economy.
It depends how you define taxes. It is amusing to see whan the federal income tax is being compared with the total tax in Sweden (which includes dividends, social security, local etc). Sweden's federal tax is ZERO :)
If you say so. Send me your address and I'll forward my tax bill.
I'll bet they pay an entire regiment of lawyers to keep it that way too.
Both of these men are donating a higher percentage of their income to charity than 99% of the people in this country.
Their investing and capital outlay employs hundreds of thousands of other americans who can then also pay taxes.
I have no animosity towards either of them (or the Walton family for that matter).
the more they make, the more people that are employed and more unfortunate people get some sort of charitible assistance..
Unbelievable that someone can find fault with this..
There should be no income tax at all.
Your mantra is "soak the rich" I know.
But soaking the rich is not only immoral, it has horrible practical consequences as well.
Another reason to eliminate the IRS & repeal the federal income tax. Buffet and his ilk would pay more taxes from his restaurant meals alone than he's paying now if we went to a national sales tax. Go to a ten percent national sales tax on EVERYTHING...yes even real estate and groceries.
When it comes to taxes, these two are idiots.
Huh? The point of my statement was that the headline was misleading. The writer makes it sound as if Buffett were paying fewer tax dollars than a soldier in Iraq. What Buffett really said was that he is paying less as a percentage of his total income. I expressed no opinion about graduated tax rates vis a vis a flat tax.
Since you ask, however, I prefer the Fair Tax.
However, I must say that military pay ought to be exempt from all Federal taxes -- especially pay for military personnel in combat.
In that Mr. Gates, at least, draws a very modest salary from Microsoft, he pays a comparatively small amount of money in ordinary income taxes, payroll taxes, etc.
Microsoft pays a small dividend, so Mr. Gates pays 15% in federal income taxes on that amount, which is still very small in relationship to his wealth.
Otherwise, Mr. Gates pays taxes on income from any other investments he may have (still relatively small compared to the wealth in his shares of Microsoft), and will pay capital gains tax from time to time when he sells shares of Microsoft (or other smaller investments). Capital gains are a maximum of 15% on the gain at the federal level.
Thus, part of the issue is that Mr. Gates probably just doesn't generate a whole lot of income, in comparison to his wealth, and what income he generates annually is likely nearly all dividends and capital gains, which are both taxed at a maximum federal rate of 15%.
But remember that any dividends he receives are paid out of after-tax corporate profits, and thus have have already been taxed at the federal corporate income tax level (and Microsoft pays federal corporate income taxes at a rate of about 35%). As well, capital gains come from investments usually acquired initially with after-tax income.
These hypocrites can cut a check to the US Treasury any time they want.
Why don't they form a "rich guys who don't pay enough taxes club" and sign up everyone they know who can afford it? They can start with Gates dad. He's a billionaire.
World Unimpressed with Bill Gates Puny $168m Donation - September 23rd 2003
Charities around the world were shocked today to learn that Bill Gates had pledged 168 million dollars in the fight against malaria.
Quite frankly, I was disappointed. Chuck Hankman, the manager of a local branch of Oxfam announced. I mean, 168 million sounds like a lot, but to people like Bill Gates its next to nothing.
I managed to secure a $46,000 a year wage for my job at Oxfam but I give nearly $2,000 a year of that to charities. Mr Gates is worth 46 billion to parallel what I donate he would have donate 2 billion. It just exposes what a cruel hearted bastard the billionaire is. He earns far too much for what he does, all that excess money should be going to charity...
You sound familiar...
Looks like "the fix is in" for the next election.
"Unbelievable that someone can find fault with this.. "
The fault I find is preaching to impressionable young students as though this complicated situation is so simple. They are basically saying that the tax cuts Bush passed are wrong and I'm sure many students will believe them. It plays right into the "rich get richer" under Bush theme.
"And is the Lied Center the real name of the place or is the writer being ironic?"
Too funny. The Lie(d) Center is pronounced Leed, but it's a good play on words in this situation.
He may be actually telling the truth. He has never taken much of a salary. His wealth comes from the appreciation of his BH stock, the gains on which are not taxed until he sells some, which he never does except through his charitable foundation, which doesn't pay taxes. He lives modestly, as I am given to understand, and BH stock doesn't pay dividends I believe. So his taxable income is quite small.
Buffet seems to be unaware of a lot of things. Surprisingly his personal finances and company structure.
With the debate on repealing the tax on dividends Buffet complained that if the tax on dividends were repealed he would pay far less in taxes on his BH income than he does now. An enterprising reporter decided to investigage.
There was a big problem with Buffet's claim. BH doesn't pay dividends!
Relax Comrade. Even if the soldiers were paying taxes, Bill Gates made $1,000,000 in salary last year. That puts him in the 35% tax bracket. Plus 15% of any capital gains on MSFT stock sales. The average soldier is in the 10% or 15% tax bracket.
Disclaimer: Opinions posted on Free Republic are those of the individual posters and do not necessarily represent the opinion of Free Republic or its management. All materials posted herein are protected by copyright law and the exemption for fair use of copyrighted works.


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Nonnewaug boys win BL soccer title
By Ron Putetti Republican-American
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subset: commoncrawl


text:
|Publication number
|Publication type
|Application number
|Publication date
|Apr 30, 1985
|Filing date
|Mar 5, 1982
|Priority date
|Mar 5, 1982
|Fee status
|Also published as
|Publication number
|Richard A. Loskorn, Philip D. Biehl, Robert D. Catiller
|Original Assignee
|Burroughs Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Referenced by (7), Classifications (4), Legal Events (9)
|External Links: USPTO, USPTO Assignment, Espacenet
This disclosure relates to the field of data communications and more specifically to the use of line adapters used to interface remote data terminals to an I/O subsystem.
This disclosure is also related to an application entitled "Bit Oriented Line Adapter System", inventors Richard A. Loskorn, Philip D. Biehl and Robert D. Catiller, and filed Mar. 5, 1982, as U.S. Ser. No. 355,134.
Incorporated by reference are several patents which form a background and explanation for the use of the line adapters of this disclosure. These patents, which are included by reference, are:
U.S. Pat. No. 4,293,909 entitled "Digital System for Data Transfer Using Universal Input-Output Microprocessor".
U.S. Pat. No. 4,291,372 entitled "Microprocessor System with Specialized Instruction Format".
U.S. Pat. No. 4,292,667 entitled "Microprocessor System Facilitating Repetition of Instructions".
U.S. Pat. No. 4,189,769 entitled "Input-Output Subsystem for Digital Data Processing System".
A line adapter is disclosed which is particularly adapted for interfacing a byte oriented protocol system which uses data bytes to remote terminals which operate on serial bit data. The line adapter may be configured in a single line adapter format or may be in a multiple line adapter format on one card. Working in conjunction with a state machine processor, the line adapter provides means for usage of synchronous mode transmission or asynchronous mode transmission in addition to adaptation for different byte-oriented protocols. Receiver-transmitter means and timer means in the line adapter may be specifically addressed in order to control baud rate of transmission, timing control, length of bits in a character and protocol factors. The receiver-transmitter and timer means may also request service from the state machine processor and receive necessary instructions. Data may be transferred from the state machine processor to the timer and receiver-transmitter for transmission to a remote terminal. Likewise, data from a remote terminal may be packaged into bytes by the receiver-transmitter and timer means and thence routed to a multiplexor means for buffering in a RAM storage means.
FIG. 1 is a schematic drawing of slide-in cards fitting into a base module backplane and having frontplane connectors therebetween.
FIG. 2 is a block diagram of a multiple line adapter card oriented to byte-protocols.
FIG. 3 is a block diagram of the state machine processor which controls operations of the line adapter.
FIG. 4 is a block diagram of a single byte-oriented line adapter.
FIG. 5 is a drawing of logic circuitry used to select memory for a given line adapter.
The line adapter of the present disclosure is designed to be used as part of a Line Support Processor (also often called a frame recognition-data link processor) as part of a data comm I/O subsystem.
FIG. 1 shows such a data comm I/O subsystem wherein a state machine processor card 600 works in coordination with various types of line adapters. A single line adapter card 700 may be used as well as Quad line adapters such as that shown in cards 400 and 500. These Quad line adapters constitute a unit of four separately addressable line adapters, each line adapter of which may handle a single data communications line through an electrical interface.
FIG. 4 shows a block diagram of a "Single" byte oriented line adapter system. A remote data set or data terminal may be connected to input/output circuit means (single line adapter) which includes timer 507 and USART 508. This input/output circuit connects to a transceiver bus controller 503 which can route the data to a multiplexor means 504 for conveyance along I/O bus 10 to the state machine processor 600 or into a RAM buffer 550m. Data in the state machine processor 600 can be routed from the state machine's output control register 38, FIG. 3, along bus 172 into the transceiver bus controller 503 for transmission to the input/output circuit means. The input/output means, such as 507 and 508, is commonly denoted as a "line adapter". The multiplexor 504 receives control signals from the data link interface unit 700 of FIG. 1 in addition to other control signals which identify units within the line adapter system. Also provided is an automatic calling unit output register 505 which can receive signals useful for dialing remote terminals on telephone lines.
FIG. 2 is a block diagram of a "Quad" Line Adapter used for byte oriented protocol operations. The input/output circuit means which connect to remote terminals is composed of four basic units such as 507, 508 (timer 0 and USART 0). Likewise, input/output service to a remote terminal is provided by timer 509 and USART 1 designated 510. Units 511, 512 constitute an operating unit for another remote terminal as do units 513 and 514 for yet another remote terminal. Each pair of these units, such as 509 and 510, as 511 and 512, as 513 and 514, each constitute a "line adapter".
As discussed under FIG. 4, each of the Line Adapters uses a transceiver bus controller 503 and a set of multiplexors 504 and 506. It should be noted that the multiplexors such as 504 and 506 are in essence "dual operating multiplexor sets" in that they receive control signals from two different input/output units. For example, MUX 504 involves a set of eight multiplexor units (A, A0) in order to handle line adapter 0 (507 and 508); and a set of eight multiplexor units (LA1) to handle the line adapter 1 (509 and 510).
Corresponding to the Automatic Calling Unit Output Register 505 of FIG. 4, the Quad Line Adapter of FIG. 2 uses 4 such ACU output registers (5050, 1, 2, 3). Also in the Quad Line Adapter there is provided an extra set of RAM buffer memories designated 550m1 and 550m2, having inputs from the I/O bus and outputs on the MEMOUT bus 12.
FIG. 3 is a block diagram of the State Machine Microprocessor which is used to control the single line adapter or multiple configurations of line adapters. The state machine processor (sometimes designated as UIO State Machine) resides on a circuit board of chips which can be inserted as a slide-in card into the base module (FIG. 1) where it connects to the backplane. The State Machine connects to the application dependent logic through the frontplane connectors as seen in FIG. 1.
A detailed description of the elements and use of the UIO State Machine has been the subject of several prior patents which are included herein by reference. These patents are:
U.S. Pat. No. 4,293,909 entitled "Digital System For Data Transfer Using Universal Input-Output Microprocessor", inventors Robert D. Catiller and Brian K. Forbes.
U.S. Pat. No. 4,291,372 entitled "Microprocessor System With Specialized Instruction Format", inventors Brian K. Forbes and Robert D. Catiller.
U.S. Pat. No. 4,292,667 entitled "Microprocessor System Facilitating Repetition of Instructions", inventors Robert D. Catiller and Brian K. Forbes.
The use of a host computer working in conjunction with an I/O subsystem which uses peculiar commands called I/O descriptors, data link descriptors, and result descriptors is shown in U.S. Pat. No. 4,189,769, Feb. 19, 1980, to Darwen J. Cook and Donald A. Millers, II, and entitled "Input-Output Subsystem for Digital Data Processing System" and this patent is also included herein by reference.
FIG. 5 is a diagram of certain logic on the DLI/LA card 700 which is used to select or "Designate" the RAM buffer memory of the single Line Adapter card or a selected memory of a specific one of the four line adapter memories on the Quad line adapter card. Shown as RAM storage means 550m in FIG. 5 is the particular memory used for the single Line Adapter. However, in the "multiple" Line Adapter situation, each line adapter has a similar selection system for selecting the particular memory associated with that line adapter.
In FIG. 5, address lines from the State Machine Processor (MADDRnn) connect to a Comparator 100c and also to the RAM buffer 550m. A chip select signal CS/ is activated to the buffer memory 550m by means of logic signals from the Comparator 100c and the Designate Flip-Flop (DESF). A unique jumper bit provides input to the Designate Flip-Flop from the I/O bus 10 in order to particularly identify any given selected buffer memory in the system. The particular bit line to be used is "set" by the State Machine Microprocessor, 600, using one of the bit-lines of I/O bus 10.
A functional section of the Line Support Processor (also called the Frame Recognition-Data Link Processor and/or Line Support Processor-DLP) is the Line Adapter called the "Byte Oriented Line Adapter". This is sometimes also called a "Character Oriented" Line Adapter.
The data comm Line Adapter is basically a device which interfaces on one end to a data communication line "electrical interface", and on the other end interfaces to a processor which has been designated as the UIO State Machine 600 (UIOSM). The primary function of the Line Adapter is to serialize "bit" information to/from "byte" information, to provide timing, to generate service requests, to supply a RAM memory, to provide automatic calling interfacing and to provide connection to level changers which will match the data communication lines. The Byte-Oriented Line Adapter is also built in two basic configurations designated as (i) Quad Line Adapter and (ii) the Single Line Adapter. The Single Line Adapter is part of the Line Support Processor and the Single Line Adapter shares the same board with the Data Link Interface (DLI) circuitry. The Line Adapter is required regardless of the quantity of lines controlled by the Line Support Processor. The Quad Line Adapter contains essentially four (4) Line Adapters on one board. These boards are typical 10 inch by 13 inch boards which plug into the backplane of the Base Connection Module. Also a smaller version of the Line Adapter may be configured as a "Dual" Line Adapter which consists of two Line Adapters on one board rather than four Line Adapters.
As seen in FIG. 1, each of the Line Adapter cards 400,500 connect both to the State Machine Processor 600 and to the DLI/LA 700 (Data Link Interface-Single Line Adapter).
As seen in FIGS. 2 and 4, connection to the data communications line is through an electrical interface (EI) which connects to the Line Adapter. There are various types of electrical interface boards which exist and which may be mounted in different combinations on the Quad Line Adapters. Thus, depending on the electrical characteristics of the data comm line, the only change required is that of the electrical interface, while the Line Adapter remains as is.
From one to eight Line Adapters may variously be addressed by the State Machine Processor 600; thus, each Line Adapter is jumpered uniquely (as seen in FIG. 5) in order to identify its address. The Line Adapter must be "designated" for the State Machine Processor to communicate with it. Several addressable components are contained on a Line Adapter which the State Machine Processor may communicate with, in the form of Write/Read data or "Status" or "Control" signals.
The addressable components of the Byte Oriented Line Adapter are:
(i) USART (508, 510, 512, 514, FIG. 2)
(ii) Timer (507, 509, 511, 513, FIG. 2)
(iii) Auto Call Output
(iv) Auto Call Status (ACUST)
(v) Component Requestors (CRID)
(vi) Memory (RAM)
The USART (Universal Synchronous/Asynchronous Receiver/Transmitter) accepts data "bytes" from the State Machine Processor 600 and converts them into serial "bits" for transmission; it also receives serial bit data and converts this to parallel data bytes. The USART device is initialized by "writing" into its two internal control registers which then specify the manner in which it operates.
A typical USART preferred for this purpose is manufactured by Western Digital Corporation, 3128 Redhill Avenue, Newport Beach, Calif. 92663, and is designated as UC1671 and described in a Technical Manual dated August 1978 as UC1671 Asynchronous/Synchronous Receiver/Transmitter.
Various bits of the internal control registers of this USART unit specify such things as: synchronous/asynchronous mode; bits per character; parity; baud rate; transparent mode; Echo mode. The Timer used on the Byte Oriented Line Adapter serves two basic functions: (i) as program timers and (ii) as baud rate generators for asynchronous operation. Three independent internal timers are contained in each chip, two of which are used by the software for timing purposes relative to the line operations for "transmit" and for "receive" operation. The third timer is used to generate a square wave clock which is used by the USART for asynchronous operation. Each timer is initialized independently, which indicates the "mode" in which it is to operate. The two program timers are capable of activating a Flag signal to the State Machine Processor 600 when a pre-determined timing value has been reached.
The Auto Call Output Register (ACUOR 505) is a register which is loaded by the State Machine Processor with "dial digit" and control information. The output of this register drives level-changer chips which convert the logic signals to EIA RS-232 voltages. These signals drive an automatic calling unit (ACU) such as a Bell 801, which provides dial-out capabilities.
Auto Call Status is a means of providing the condition or state of input lines from the automatic calling unit (ACU) to the State Machine Processor 600. Lines from the ACU are received by level-changer chips which convert the EIA voltages to TTL logic levels. These logic levels may be read by the State Machine Processor to determine the present status.
The Component Requestors from a Line Adapter are as follows: (i) USART; (ii) Program Timer 1; (iii) Program Timer 2.
These three components are capable of generating "service requests" independently of each other at unique times relative to initialization. The "service requests" activate a flag signal to the State Machine Processor which indicates that Line Adapters require servicing. After the State Machine determines which Line Adapters are requesting service, it must then determine which "component" on a particular Line Adapter is requesting service.
Memory on the Line Adapter consists of 2,048�17-bit words of RAM for each line. Therefore, each Quad Line Adapter card actually contains 3,192�17-bit words of RAM. The Single Line Adapter card (FIGS. 9, 10) contains 4,096 words of RAM 550m, one half for the data comm line and the remainder for DLI. The RAM is used by the software for transmit/receive message buffering, for tables and for statements associated with the line operation.
Designate: When the State Machine Processor 600 executes code relative to an addressable component on a Line Adapter, (LA), the LA must be "designated". Each Line Adapter contains a Flip-Flop, DESF, FIG. 5, whose input is jumpered to a specific bit of the I/O bus. In order to "designate" a Line Adapter, the State Machine Processor must execute a PUT OP with Strobe No. 1 (D-FLDOOO) and the corresponding bit of the I/O bus must be equal to 1. Executing the same OP with the I/O bus bit equal to 0 will reset the Designate Flip-Flop shown typically as "DESF" on FIG. 5.
Flag Operation: The various components of a Line Adapter are capable of producing "service requests". These "service requests" are basically ORed together in order to drive a common FLAG line for all Line Adapters. A signal line, FLAG 2/, when being low active, notifies the State Machine Processor that some Line Adapters are requesting service. The State Machine Processor can determine which Line Adapters are requesting service by executing a GET OP with the variant field V-FLD (4:5) equal to 00001. The Line Adapter does not need to be "designated" for execution of this OP.
"Register address" (REGADRn) signals in the Line Adapters are five "V-FLD" signals from the State Machine Processor. The two least significant signals of the V-FLD are shown in Table Y-1.
Data Bus Structures: With the exception of the RAM (FIG. 5), memory 550m1, m2, all data sent to addressable components on the Line Adapter originate from the "Second Output Control Register 38 (FIG. 3) in the State Machine Processor. With the exception of RAM, all data "read" by the State Machine Processor from addressable components on the Line Adapter will go to the State Machine Processor via the I/O bus 10.
With reference to FIG. 4 (DLI/LA data bus structure), the Single Line Adapter data bus structure is shown.
As seen in FIG. 4, the Second Output Control Register 38 (FIG. 3) lines (OCREG 20n) connect directly to the inputs of the Auto Call Unit Output Register 505 (ACUOR); and they also connect directly to the Transceiver Bus Controller chip 503 which provides bidirectional bus drivers.
The Auto Call Unit Output Register 505 is a six bit "D" type flip-flop register (DR6n). When the clock input is enabled, data from the Second Output Register 38 will be strobed into ACUOR 505.
Data sent to both the Timer 507 and to the USART 508, FIG. 4, originate from the Second Output Register 38 in the State Machine Processor (FIG. 3) and is sent through the Transceiver bus controller 503; then is sent to the addressed component. The data lines for the Timer component are HI active and for the USART component they are LO active. Being as both components share the same data bus, data to one of the components must be inverted. The Timer 507 is used to receive the "inverted" data, that is, 1=0 and 0=1, while the USART 508 receives the conventional format. Thus, a "one" bit from the Second Output Register 38 in the State Machine Processor (FIG. 3) will appear as a "one" bit to the USART (active low) and as a "zero" bit to the Timer. The Transceiver bus controller 503, although being a three-state device, is not used in its third or high impedance state. It is used for driving either DIN (data in) to DOUT (data out) or DOUT to ROUT (FIG. 4) depending on the state of the RE (Read Enable) signal which originates from bit 4 of the First Output Control Register 37 in the State Machine Processor. When bit 4 of Register 37 is ON, the signal RE is positive and "enables" the DIN to DOUT direction through the Transceiver bus controller 503.
Reading of information (except RAM read) from a Line Adapter is performed by decoded GET OPs, and the read information is available on the least significant 8 bits of the I/O bus 10. The 8-1 multiplexor 504 is the source of the read information.
On the "Single" Line Adapter (FIG. 4) four of the eight inputs to MUX 504 are used by the Line Adapter and the remainder are used by the Data Link Interface (DLI). The multiplexors (MUX's) are chip selected (low level) during a GET OP when the V-FLD (3:2) is equal to "11" and either V-FLD (4:1) equals 0 (DLI GET) or the Designate Flip-Flop (DESF) is "ON" (LA GET).
On the "Quad" Line Adapter cards there are 16 multiplexors, each having an eight-one ratio. There are 8 multiplexors for each pair of Line Adapters.
As seen in FIG. 4, the eight input lines to MUX 504 are divided in half such that four lines connect to the DLI (Data Link Interface), and four lines connect to the Line Adapter. Similarly in FIG. 2, in the Quad Line Adapter, the eight input lines of each group of eight multiplexors is divided in half, similar to the Single Line Adapter, thereby making four groups. Any "group" of "four" input lines is selected by its "Designate Flip-Flop" (DESF, FIG. 5) being ON. The selection of any one of four lines of any such group is performed by the two least significant bits of the V-FLD of a GET OP, (Table Y-1).
Data "to be "written into" RAM memory in a given Line adaptor" is sent via the I/O bus in 16 bits plus parity format. The data "read from" RAM memory in a Line Adapter is placed on the MEMOUT bus 12 with 16 bits plus parity.
Component Addressing: As seen in FIG. 4, the outputs of components to be "read" are routed to the inputs of the 8-1 multiplexor which then drive the I/O bus 10. There are five components on a Line Adapter which may be "read" by the State Machine Processor, these are:
Component Requestor ID (CRID)
Timer (507)
Automatic Calling Unit Status (ACUST)
Adapter Type ID (ADPT.ID)
Although these five components on a Line Adapter may be read, the USART 508 and the Timer 507 share the same input line (ROUT) to the multiplexors. Selection of one of the four inputs in either group (of inputs to the 8-1 multiplexors) is performed by the two least significant bits of the V-FLD of the GET OP. V-FLD (3:4) equals 11XX and selection of one of the four inputs is determined as shown in Table Y-1.
TABLE Y-1______________________________________ V1(x) V0(x)______________________________________ 0 0 0 1 1 0 1 1______________________________________
In FIG. 4 the Single Line Adapter multiplexor 504 allows three components on a Line Adapter to be written into (not including RAM). These are: Automatic Calling Unit Output Register 505 (ACUOR), the USART 508 and the Timer 507. The addressing of these three components occurs in two distinct fashions: (a) decode of the V-FLD of PUT Ops and (b) the decode of bits from the First Output Control Register 37 in the State Machine Processor (FIG. 3).
The ACUOR 505 is addressed when a one-of-eight decoder chip decodes the PUT OP V-FLD (4:5) equal 01111 and the Strobe No. 2 is sent from the State Machine Processor. This decoding is performed only on the Single Line Adapter card and is sent to other Line Adapter cards via the frontplane connector. This decoded signal is received by a three input NOR gate (not shown) in each Line Adapter (whose other inputs are Clock and Designate FF). The output of this gate drives the clock input of the six bit ACU output register.
Data from the Second Output Control Register 38 (FIG. 3) will then be strobed into the ACUOR 505.
Addressing a USART or Timer on a designated Line Adapter is the same as "chip selecting" the component. This is accomplished with bits 0 and 1 of the First Output Control Register 37 in the State Machine Processor along with the Designate Flip-Flop (DESF) in a Line Adapter.
Each Line Adapter will "AND" its Designate FF with bits 0 and 1 from output control register 37 in order to provide a UCS (USART Chip Select) or a TCS (Timer Chip Select) for its USART or Timer.
The use of bits 0 and 1 in the First Output Control Register 37 is as follows:
TABLE Y-2______________________________________Register bitand Value Signal Designation______________________________________Bit 0 = 1 USARTCS = USART Chip Select-UCSBit 1 = 1 TMRCS = Timer Chip Select-TCS______________________________________
The remaining bits of Register 37 are used for control signals, primarily for the USART and Timer.
Random Access Memory (550m, FIG. 5): Each data comm line has 2,048 words of RAM available for its use. A word is equal to 16 data bits plus one parity bit. In FIG. 5 the RAM chip 550m is a 4,096�1 bit static RAM with a Read Access time of 180 nanoseconds and is arranged with 17 chips making 4,096 words. On the DLI/LA card 2,048 words are for the "Single" Line Adapter and 2,048 words are for the Data Link Interface. The "Quad" Line Adapter card provides 34 memory chips or 8,192 words of which 2,048 words are available for each line.
The data comm Line Adapter memory (for any line) is "pointed at" by the memory address lines, MADDR (15:5) equal 01110. This can be seen in FIG. 5 which shows the Data Link Interface/Line Adapter RAM. A five bit Comparator 100c on the DLI/LA card compares (for an "equal" condition) for (i) DLI memory selection; or, for a "greater than" condition, (MADDRnn 01110) provides for (ii) Line Adapter RAM selection. The signal "LARAMSEL" (Line Adapter RAM Select) will go to all Line Adapter cards via the frontplane cable to select the "designated" Line Adapter RAM memory. If memory address lines MADDR (15:5) equals 0111x (DLI or LA Select) then a slow memory flip-flop (SLMF) 100sf will be set equal to 1. The Flip-Flop 100sf output drives an open collector NAND gate whose output connects to the WAIT/ frontplane signal line to the State Machine Processor. This signal (WAIT/), when low, will force the State Machine Processor to "wait" until the signal goes "high". Using a RAM chip whose Read Access time is 180 nanoseconds requires the State Machine Processor to wait for one clock time, thereby when the DLI memory (550m, FIG. 5) or any Line Adapter memory is selected, the SLMF (slow memory flip-flop) will be "on" for one clock and then toggle off.
Selection of the RAM memory 550m on the DLI/LA card is done via MADDR (15:5) equal to 01110 or else MADDR (15:5) equal 01111 and the Designate Flip-Flop being ON. This logic controls the chip-select input on the RAM chips. The division of RAM for DLI or for Line Adapter memory is handled by controlling the "A-11" (FIG. 5) address pin on the RAM 550m chip. If MADDR (15:5) is equal to 01111 and the Line Adapter Designate Flip-Flop (DESF) is ON, the RAM is chip selected and the A-11 address input is TRUE.
The "Quad" Line Adapter card (FIG. 2) contains two groups of memory chips (550m1, 550m2) wherein Data-Comm (D.C.) lines 0 and 1 on the card share the same group of RAM chips and Data-Comm lines 2 and 3 share the other group of RAM chips. The signal LARAMSEL (Line Adapter RAM Select, FIG. 5) goes to all Line Adapters and is then essentially ANDED with appropriate Designate conditions to allow the desired RAM group to be chip selected. A "division" of RAM for the first or second data-comm line on a Quad Line Adapter is handled by controlling the "A-11" address pin (FIG. 5) on the RAM chip (signal DESn where n=1) and for the third and fourth line the "A-11" pin on the second group of RAM chips is controlled by DESn (FIG. 5) where n=3.
A "Dual" Line Adapter will only contain one group of memory chips (17) and will operate the same as line 0 and line 1 on the Quad Line Adapter. Data to be written into RAM must be placed on the I/O bus 10 by the State Machine Processor and "read data" will be sent to the State Machine Processor on the MEMOUTnn bus 12 (nn equals 00→16).
Clear: There are two methods of clearing used to clear the Line Adapters; these are "Power Up" Clear and "Designate" Clear.
The Power Up Clear is a signal which occurs during the power-up sequence for the cabinet housing the Line Adapters. The signal comes from the backplane of the Base Module cabinet and is active Low.
The Designate Clear is a function controlled by the State Machine Processor, and only the Line Adapters which are designated are the ones that get cleared. The Clear signal originates from bit 7 of the First Output Control Register 37 of the State Machine Processor (FIG. 3). The "Power-up" Clear operates to clear three components on the Line Adapter. These are: the Designate Flip-Flop; the Auto Call Output Register; and the USART.
The "Designate" Clear signal clears two components on the Line Adapter. These are: Auto Call Unit Output Register (ACUOR); and the USART.
USART Organization and Operation: The USART is a MOS/LSI device housed in a 40-pin Dual-in-line package and is TTL compatible on all inputs and outputs. The USART performs the functions of interfacing a "serial" data communications channel to a parallel digital system and is capable of full duplex communications with synchronous or asynchronous systems.
One preferred embodiment of the USART is that manufactured by Western Digital Corporation, 3128 Redhill Avenue, Newport Beach, Calif. 92663 and is designated as Model UC1671 Asynchronous/Synchronous Receiver/Transmitter and described in their Technical Data Publication of August 1978 which includes a block diagram showing the various registers, controls and components which are briefly described herein below.
(i) Receiver Register (RR): this is an eight bit shift register which inputs the received data at a clock rate determined by an internal control register. The incoming data is assembled to the selected character in length and then transferred to the Receiver Holding Register with logic zeroes filling out any unused high-order bit positions. At this time the INTR (Interrupt) output is made active for informing the State Machine of the LSP that the Receiver Holding Register contains valid data.
(ii) Receiver Holding Register (RHR): this is an 8-bit parallel buffer register which presents assembled receiver characters to the DAL (Data Access Line) bus lines (FIG. 2) when requested through a Read operation.
(iii) Comparator: the 8-bit comparator is used in the Synchronous Mode to compare the assembled contents of the Receiver Register and the SYN register or the DLE register. A "match" between the registers sets up the stripping of the received character (when programmed) by preventing the data from being loaded into the Receiver Holding Register. A bit in an internal Status Register is set when stripping is performed. The comparator output also enables character synchronization of the Receiver on two successive matches with the SYN register.
(iv) SYN Register: this is an 8-bit register which is loaded from the DAL (Data Access Line) lines (FIG. 2) by a Write operation and it holds the synchronization code used to establish receiver character synchronization. It serves as a fill character when no new data is available in the Transmitter Holding Register during transmission. This register cannot be read onto the DAL lines. It must be loaded with logic zeroes in all unused high-order bits.
(v) DLE Register: this is an eight bit register which is loaded from the DAL lines by a Write operation and holds the "DLE" (Delimiter) character used in the Transparent Mode of operation, in which an idle transmit period is filled with the combination DLE/SYN pair of characters rather than a single SYN character. In addition, the USART may be programmed to force a single DLE character prior to any data character transmission while in the "transmitter transparent mode".
(vi) Transmitter Holding Register (THR): this is an eight-bit parallel buffer register which holds parallel transmitted data transferred from the DAL lines by a Write operation. This data is transferred to the Transmitter Register (TR) when the transmitter section is enabled and the Transmitter Register is ready to send new data. During this transfer, the signal interrupt (INTR) is made active for informing the Line Support Processor that the Transmitter Holding Register is empty.
(vii) Transmitter Register: this is an eight-bit shift register which is loaded from the THR (Transmitter Holding Register), the SYN register, or the DLE register. The purpose of this register is to serialize data and present it to the transmitted Data Output lines.
(viii) Control Register: there are two eight-bit control registers in the USART which hold device programming signals such as: mode selection, clock selection, interface signal control, and data format. Each of the control registers can be loaded from the data access lines (DAL) by a Write operation, or else read into the DAL lines by a Read operation.
Operation of USART of Byte Oriented Line Adapter:
ASYNCHRONOUS MODE: The framing of asynchronous characters is provided by a Start Bit (logic low) at the beginning of a character, and by one or more Stop Bits (logic high) at the "end" of a character. Reception of a character is initiated on recognition of the first Start Bit by a positive transition of the receiver clock, right after a proceeding Stop Bit. The Start and Stop bits are "stripped off" while assembling the serial bit input into a parallel character.
The character assembly is completed by the reception of the Stop Bit after the reception of the last character bit. If this bit is a logic "high", the character is determined to have "correct" framing and the USART is prepared to receive the next character. If the Stop Bit is logic "low", the Framing Error Status flag is set and the Receiver assumes this bit to be the Start Bit of the next character. Character assembly continues from this point if the input is still a logic "low" when sampled at the theoretical center of the assumed Start Bit. As long as the Receiver input is "spacing" (i.e. receiving a space rather than a Mark), then all zero characters are assembled, and error flags and data received interrupts are generated so that line breaks can be determined. After a character of all zeroes is assembled along with a zero in the Stop Bit location, the first-received logic "high" is determined as a Stop Bit and this resets the receiver circuit to a "Ready" state for assembly of the next character.
In the Asynchronous Mode the character transmission occurs when information contained in the THR (Transmitter Holding Register) is transferred to the TR (Transmitter Register). Transmission is initiated by the insertion of a Start Bit, followed by the serial output of the character (least significant bit first) with parity, if enabled, following the most significant bit; then there is the insertion of the 1-, 1.5-, or 2-bit length Stop condition. If the THR (Transmitter Holding Register) is full, the next character transmission starts after the transmission of the Stop Bit of the present character in the TR (transmitter register). Otherwise, the "Mark" (logic high) condition is continually transmitted until the THR (Transmitter Holding Register) is loaded.
SYNCHRONOUS MODE: The synchronization of messages is carried out by a special Synchronization Character Code (SYN) transmitted at the beginning of a block of characters. The Receiver, when enabled, searches for two contiguous characters matching the bit pattern contained in the SYN register. During the time that the Receiver is searching, data is not transferred to the THR (Transmitter Holding Register) and status bits are not updated; and the Receiver interrupt is not activated. After the detection of the first SYN character, the Receiver assembles subsequent bits into characters whose length is determined by the contents of the USART internal control register. If, after the first SYN character detection, a second SYN character is present, the Receiver enters the Synchronization Mode until the Receiver Enable Bit is turned "off". If a second successive SYN character is not found, then the Receiver reverts back to the Search Mode.
In the Synchronous Mode, a continuous stream of characters are transmitted once the Transmitter is enabled. If the THR (Transmitter Holding Register) is not loaded at the time the Transmitter Register has completed the transmission of a character, this "idle" time will be filled by a transmission of a character contained in the SYN register in the Non-Transparent Mode, or filled by the characters contained in the DLE and the SYN registers respectively (while in the Transparent Mode of operation).
RECEIVER OPERATION: The Receiver data input is clocked into the Receiver Register by a 1X Receiver clock from a modem Data Set, or by a local 32X bit rate clock (asynchronous) selected from one of four timer chips. When using the 1X Receiver Clock, the Receiver data is sampled on the positive transition of the clock in the Synchronous Modes. When using a 32X clock in the Asynchronous Mode, the Receive Sampling Clock is phased to the "Mark-To-Space" transition of the Received Data Start Bit and defines (through clock counts) the center of each received Data Bit at the positive transition 16 clock periods later. When the complete character has been shifted into the Receiver Register, it is transferred to the RHR (Receiver Holding Register); the unused, higher number bits are filled with zeros. At this time the "Receiver Status bits" (Framing Error/Sync Detect, Parity Error/DLE Detect, Overrun Error, and Data Received) are updated in the Status Register and the Data Received "interrupt" is activated. Parity Error is set if encountered while the Receiver Parity Check is "enabled" in the internal control register. Overrun Error is set if the Data Received Status Bit is not cleared through a Read Operation by an external device when a new character is ready to be transferred to the RHR (Received Holding Register). This error flag indicates that a character has been lost, that is new data is lost, and the old data and its status flags are saved.
The characters assembled in the Receiver Register that match the contents of the SYN or the DLE register are not loaded into the RHR (Receiver Holding Register), and the DR (Data Received) interrupt is not generated if bit 3 of USART control register 2 (CR23=SYN Strip) or Bit 4 of USART control register 1 (CR14=DLE Strip) are set respectively. The SYN-DET and the DLE-DET status bits are set with the next non-SYN or DLE character. When both control register bits CR23 and CR14 are set (Transparent Mode), the DLE-SYN combination is stripped. The SYN comparison occurs only with the character received after the DLE character. If two successive DLE characters are received, only the first DLE character is stripped. No parity check is made in this mode.
TRANSMITTER OPERATIONS: Information is transferred to the THR (Transmitter Holding Register) by a Write operation. Information can be loaded into this THR at any time, even when the Transmitter is not enabled. Transmission of data is initiated only when the Request-to-Send Bit is set to a logic "one" in the USART control register and the Clear-to-Send input is at a logic "low". Information is normally transferred from a THR to the Transmitter Register when the latter has completed transmission of a character. However, information in the DLE register may be transferred prior to the information contained in the THR if the Force-DLE signal condition is enabled (CR15=Force, DLE and CR16=TX Transparent and set to a logic "one"). The control bit CR15 must be "set" prior to loading of a new character in the THR to insure forcing the DLE character prior to transmission of the data character. The Transmitter Register output passes through a Flip-Flop which delays the output by one clock period. When using the 1X clock generated by the modem Data Set, the output data changes state on the negative clock transition and the delay is one bit period.
When the Transmitter is enabled, a Transmitter "interrupt" is generated each time the THR is empty. If the THR is empty when the Transmitter Register is ready for a new character, the Transmitter enters an "idle" state. During this idle time, a logic "high" will be presented to the Transmitted Data Output in the Asynchronous Mode or the contents of the SYN register will be presented in the Synchronous Non-Transparent Mode (CR16=0). In the Synchronous Transmit Transparent Mode (enabled by bit-6 of USART control register 1=Logic 1), the idle state will be filled by a DLE-SYN character transmission in that order. When entering the Transparent Mode, the DLE-SYN fill-in will not occur until the first forced DLE.
If the Transmitter section is disabled by a reset of the Request-to-Send signal (RTS), any partially transmitted character is completed before the Transmitter section of the USART is disabled. As soon as the CTS signal (Clear-to-Send) goes high, the transmitted data output will go high.
When the Transmit Parity is enabled, the selected Odd or Even parity bit is inserted into the last bit of the character in place of the last bit of the Transmitter Register. This limits transfer of character information to a maximum of 7-bits plus parity or 8-bits without parity. Parity cannot be enabled in the Synchronous Transparency Mode.
INPUT/OUTPUT OPERATION OF USART: All Data, Control and Status words are transferred over the Data Access Lines (DALO-7) as seen in FIG. 2, DAL. Additional input lines provide controls for addressing a particular unit and regulating all input and output operations. Other lines provide interrupt capability to indicate to a controller that an input operation is requested by the USART. All input/output terminology is referenced to the Bus Controller-Transceiver 503, FIG. 2, so that a "Read" or Input takes data from the USART and places it on the DAL lines to the Transceiver 503, while a "Write" or an Output places data from the Transceiver 503 onto the DAL lines and into the USART. The following input/output terminology discussed below is referenced to the Bus Controller-Transceiver 503.
(i) READ: A Read operation is initiated by the placement of an 8-bit address from State Machine 600 on the DAL (FIG. 5) by the Bus Controller 503, FIG. 2. When the Chip Select signal goes to a logic "low" state, the USART (as 508) compares bits 7-3 of the DAL with its hard-wired ID code (on Pins 17, 22, 24, 25, 26) and becomes selected on a "Match" condition. The USART then sets its RPLY line "low" to acknowledge its readiness to transfer data. Bits 2-0 of the address are used to select the USART registers to "read from" as follows:
TABLE Y-3______________________________________Bits 2-0 Selected Register of USART______________________________________000 Control Register 1010 Control Register 2100 Status Register110 Receiver Holding Register______________________________________
When the Read Enable (RE) line is set to a logic "low" condition by the State Machine 600, the USART gates the contents of the address register onto the DAL bus. The Read operation terminates, and the devices become unselected, and both the Chip Select and Read Enable return to the logic "high" condition. Reading of the Receiver Holding Register clears the DR status bit. Bit zero must be a logic "low" in Read or in Write operations.
(ii) WRITE: A Write operation is initiated by making a Chip Select input go to the logic "low" state. Bits 2-0 of the address are used to select USART registers which are written into as follows:
TABLE Y-4______________________________________Bits 2-0 Selected Register of USART______________________________________000 Control Register 1010 Control Register 2100 SYN and DLE Register110 Transmitter Holding Register______________________________________
When the Write Enable (WE) line is set to a logic "low" condition by the State Machine, the USART gates the data from Transceiver 503 onto the DAL bus and into the addressed register. If data is written into the Transmitter Holding Register (THR), the THRE (THR empty) Status Bit is cleared to a logic zero.
The "100" address loads both the SYN and DLE registers. After writing into the SYN register, the device is conditioned to write into the DLE register if followed by another Write pulse which has the "100" address. Any intervening Read or Write operation with another address resets this condition such that the next "100" will address the SYN register.
(iii) INTERRUPTS: The following conditions will generate interrupts:
1. Data Received (DR)--indicates transfer of a new character to the Receiver Holding Register (RHR) while the Receiver is enabled.
2. Transmitter Holding Register Empty (THRE)--indicates that the THR register is empty while the Transmitter is enabled. The first interrupt occurs when the Transmitter becomes enabled if there is an "empty" THR, or after the character is transferred to the Transmitter Register, thus making the THR empty.
3. Carrier On--this indicates the Carrier Detector input has gone "low" when DTR is "on". (DTR=Data Terminal Ready).
4. Carrier Off--indicates that the Carrier Detector input has gone "high" when DTR is "on".
5. DSR On--indicates the Data Set Ready input has gone "low" when DTR is "on".
6. DSR Off--indicates the Data Set Ready input has gone "high" when DTR is "on".
7. Ring On--indicates the Ring Indicator input has gone "low" when DTR is off.
Each time an Interrupt Condition exists, the INTR output from the USART is made a logic "low". The State Machine then acknowledges the Interrupt Request by setting the CS (Chip Select) and Interrupt Acknowledge Input (IACK) to the USART to a "low" state, otherwise the Interrupt Condition (INTR) would never get reset.
Auto Call Operation: (For Operations Using an 801 Auto Call Unit)
The 801 ACU has a 4-bit interface for receiving digits of the call number to be dialed. This interface is defined by the EIA Standard RS-366 and involves the following signals:
TABLE Y-5______________________________________Call Request CRQData Line Occupied DLOPresent Next Digit PNDDigit Present DPRData Set Status DSSAbandon Call and Retry ACRNB 8 DigitNB 4 DigitNB 2 DigitNB 1 Digit______________________________________
The dialing sequence operates as follows:
The Line Adapter turns CRQ "on" provided that the DLO is "off". After detection of the dial tone, which is done by the 801, the digits are transferred one at a time to the 801. The 801 converts the digits to signals which duplicate the function of a rotating dial-pulse or a touch-tone frequency compatible signal. These signals are transmitted to the phone line. At call completion, DSS comes "on" to signify receipt of answer tone from the called Data Set. Receipt of DSS allows the line to be transferred to the ACU associated data set. If DSS fails to come "on", the Abandon Call and Retry (ACR) timer begins timing out.
With pulse dialing, a typical 10 digit number takes 15 seconds to dial; for touch-tone dialing the same number requires approximately one second. The answer sequence begins sometime after the last digit has been sent by the 801.
Interface Operation (Data-Comm Line-Adapter/State Machine):
The UIO Data-Communication Line-Adapter is an application dependent device which is controlled by the UIO State Machine Processor 600. The basic types of Line Adapters are available--these are the "Character Oriented" Line Adapter and the "Bit Oriented" Line Adapter, each of which may have a variety of electrical interfaces to the data communication lines.
One to eight Line Adapters may be serviced by one State Machine Processor on an individual basis. Each Line Adapter contains components which are addressable and are serviced by the State Machine Processor with PUT or GET instructions. The components on the Line Adapter are serviced with one or a series of instructions which, in some cases, provide sequential control of the component. The "communication" between the State Machine Processor and the Line Adapter can be separated into two basic groups:
(i) Undesignated
(ii) Designated
The "Undesignated" operations do not require the Line Adapter to be designated to execute those instructions. "Designated" type operations require the Line Adapter to be designated or identified to execute those instructions or series of instructions.
The following operations (except for ACUOR), in addition to requiring the Line Adapter to be "Designated", will use the First Control Register 37 in the State Machine Processor 600 for control purposes to components on a Line Adapter. With the exception of the Clear OP, all other operations will be a series of PUT/GET OPs to provide the necessary sequential control.
"Data" outputted to the Line Adapter for these operations will originate from the Second Output Control Register 38 of the State Machine in FIG. 3.
The bits of the First Output Control Register 37 of the State Machine (FIG. 6) are organized for control functions as follows:
TABLE Y-6______________________________________Bit Signal______________________________________0 UCS USART Chip Select - This bit must be a "1" when the USART requires a chip select.1 TCS Timer Chip Select - This bit must be a "1" when the Program Timer/ Baud Rate Generator requires a chip select.2 IACKI Interrupt Acknowledge In - This bit must be a "0" to acknowledge an interrupt from a designated and chip selected USART.3 WE Write Enable - This bit must be "0" to enable writing to the USART or Timer.4 RE Read Enable - This bit must be "0" to enable reading from the USART or Timer.5,6 A0,A1 Address Bit 0 or 1 - These two bits select a register within the Timer.7 CLR Clear - This bit must be "1" to provide a clear to the Line Adapter.______________________________________
USART Interfacing: Three procedures are used when communicating with a USART on a Line Adapter; these are:
(i) Interrupt Acknowledge Procedure
(ii) Read Procedure
(iii) Write Procedure
Timer/Baud Rate Generator Interfacing:
Two basic procedures are used when communicating with the timer components; these are: (i) Write Procedure and (ii) Read Procedure.
Five control signals originating from unique bits of the First Output Control Register 37 are used for the Timer. These are:
TCS--Timer Chip Select
A0, A1--Register Addressing Lines
WE--Write Enable
RE--Read Enable
Baud Rate Generator: The "character" oriented UIO Data Comm Line Adapters will use a USART which requires an input clock that is 32 times faster than the bit-time of the Asynchronous line it is communicating with. To obtain this X32 clock it is preferred to use an Intel 8253 programmable timer chip, whose squarewave output is connected to the USART. This timer is driven by a crystal controlled clock whose frequency is 1.2288 megahertz. After initializing the Timer, a divisor value must be loaded which will produce the necessary X32 clock.
|Cited Patent
|Filing date
|Publication date
|Feb 18, 1975
|Aug 17, 1976
|Motorola, Inc.
|Asynchronous communication interface adaptor
|Sep 29, 1976
|Jul 26, 1977
|Allen-Bradley Company
|Industrial control processor system
|Oct 30, 1975
|Jan 31, 1978
|Motorola, Inc.
|Synchronous serial data adaptor
|Dec 24, 1975
|Nov 7, 1978
|Computer Automation, Inc.
|Distributed input/output controller system
|Mar 31, 1977
|Nov 14, 1978
|Racal-Vadic, Inc.
|Multiline automatic calling system adapter
|Citing Patent
|Filing date
|Publication date
|Jun 15, 1987
|Sep 19, 1989
|International Business Machines Corporation
|Dynamic port reconfiguration
|Oct 23, 1992
|Feb 22, 1994
|Canon Kabushiki Kaisha
|Communication control unit
|Oct 27, 1994
|Sep 12, 1995
|Fujitsu Limited
|Apparatus for performing data transfer synchronously or asynchronously between device channels
|Apr 11, 2005
|Jul 24, 2012
|Linear Technology Corporation
|Configurable data port for I2C or single-wire broadcast interface
|Apr 11, 2005
|Oct 12, 2006
|Zhizhong Hou
|Configurable data port for I2C or single-wire broadcast interface
|Apr 11, 2005
|Oct 30, 2013
|Device having signal level different from signal level of external device and communication method thereof
|Apr 11, 2005
|Oct 19, 2006
|Linear Technology Corporation
|Configurable data port for i2c or single-wire broadcast interface
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Mar 5, 1982
Owner name: BURROUGHS CORPORATION, DETROIT, MI A CORP. OF MI
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:LOSKORN, RICHARD A.;BIEHL, PHILIP D.;CATILLER, ROBERT D.;REEL/FRAME:003993/0784
Effective date: 19820225
Owner name: BURROUGHS CORPORATION,MICHIGAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LOSKORN, RICHARD A.;BIEHL, PHILIP D.;CATILLER, ROBERT D.;REEL/FRAME:003993/0784
Effective date: 19820225
|Jul 13, 1984
Owner name: BURROUGHS CORPORATION
Free format text: MERGER;ASSIGNORS:BURROUGHS CORPORATION A CORP OF MI (MERGED INTO);BURROUGHS DELAWARE INCORPORATEDA DE CORP. (CHANGED TO);REEL/FRAME:004312/0324
Effective date: 19840530
|Oct 22, 1985
|Certificate of correction
|Sep 29, 1988
|Fee payment
Year of fee payment: 4
|Nov 22, 1988
Owner name: UNISYS CORPORATION, PENNSYLVANIA
Free format text: MERGER;ASSIGNOR:BURROUGHS CORPORATION;REEL/FRAME:005012/0501
Effective date: 19880509
|Sep 24, 1992
|Fee payment
Year of fee payment: 8
|Dec 3, 1996
|Maintenance fee reminder mailed
|Apr 27, 1997
|Lapse for failure to pay maintenance fees
|Jul 8, 1997
|Expired due to failure to pay maintenance fee
Effective date: 19970430


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VIOS Update
DanielJMartin Tags: aix vio power 2,552 Views
Following command are recommend for updating your VIOS running levels 2.1.0 and above. As a reboot is required on the system, make sure that any active environments are shutdown too (unless Dual VIO); First commit older updates with the following command...
Etherchannel with SEA
DanielJMartin Tags: vio aix sea etherchannel 2 Comments 11,238 Views
Configuring your SEA with Etherchannel. First check the shared virtual ethernet adapters you have - # lsmap -all -net SVEA Physloc ------ -------------------------------------------- ent3 U9117.MMB.101697P-V1-C2-T1 SEA NO SHARED ETHERNET...
SmartCloud Entry - Further Configuration
DanielJMartin Tags: smartcloud power vio cloud aix sce 3,150 Views
Billing and Metering Now that we have the our SmartCloud up, we need to get familiar with how it works and what we can do with it. Now most of us will be interested in setting up request approval, billing, and user/project control. But before we do...
LPAR Migration Error Messages
DanielJMartin Tags: power aix vio migration 5,933 Views
Error Message - HSCLA24E This week we where trying to migrate some VIO hosted LPARs using XIV disk from one POWER 7 system to another. The disk is hosted on a VIO server via the fabric, then using vscsi devices to map up to the servers. ...
Can't change max_transfer for a VSCSI hdisk? Check your vtopt devices!
cggibbo Tags: rmdev vtopt0 max_transfer rmvdev aix vios chdev hdisk cd0 virtual_optical vio 3 Comments 13,368 Views
When attempting to change the max_transfer attribute on a VSCSI hdisk, the following error was displayed: # chdev -l hdisk0 -a max_transfer= 0x100000 -P Method error (/etc/methods/chgdisk): 0514-018 The values specified for the following...
from Blog: Chris's AIX Blog
AIX VIO remove all devices attached to a vhost
CPatterson Tags: virtual_target_disk vio vtd aix vhost 1 Comment 12,035 Views
While at a customer site I had to delete a large number of Virtual Target Devices (VTD) and disks from a series of VIO servers. This quick command line script served well for the purpose. Remember to change the two ## entries to match your vhost adapter...
from Blog: Christian Patterson
CICS VSAM Buffering
MartinPacker Tags: gtf expanded_storage dim memory cics vsam lsr vio smf virtual_memory smf110 vlbpaa cpu 5 Comments 8,901 Views
Four score and seven years ago (or so it seems) the Washington Systems Center published a set of mainframe Data-In-Memory studies. These were conducted by performance teams in various IBM labs and were quite instructive and inspiring. I wish I could find the...
Running VIO commands from the HMC
I find interesting you can run commands on your VIO server from an HMC: user@hmc22:~> viosvrcmd -m SN2014AE-FSE -p vio33 -c "lsdev -virtual" name status description ent4 Available Virtual I/O Ethernet Adapter...
from Blog: Andrew Wojnarek
Installation without DVD, NIM or VIO
AnthonyEnglish Tags: production vmlibrary rootvg mkdvd devices vio dr mkisofs nim dvd clone lpar virtual_media_library mkcd bosinst.data aix_6.1 aix filesets mksysb all_device_kernels virtual_media_repository cd-rom optical_device 10,700 Views
MAKING THE BEST OF WHAT YOU'VE GOT A customer wants to clone his production LPAR running AIX 6.1 - it's on a Power6 server - to an LPAR on his DR site which runs an older p5 server. Both sites have HMCs. As the environment is very small, all I/O is handled...
PowerVM presentations: Over the Shoulder
AnthonyEnglish Tags: wpar virtual_optical live_partition_mobility tuning powervm aix ken_milberg rob_mcnelly resources performance vmlibrary aix7 lpm vio 6,249 Views
Among the plethora of good AIX resources coming to our browsers in the last week, a few deserve a particular mention. First, there was the Power IT Pro Virtual Conference. I had a chance to watch Rob McNelly's presentation. Rob, who writes the unmissable...
Resources for building an AIX SOE image
AnthonyEnglish Tags: vio lpar aix install virtual_user_group soe nim initial standard_operating_enviro... virtual_media tuning 5,139 Views
We do have standards! Having a Standard Operating Environment (SOE) for AIX has a lot of benefits. It's not just the consistency between images and some sort of version control over what you're rolling out. Using a SOE also saves time. If you build AIX systems...
Create DVD images with mkdvd
AnthonyEnglish Tags: image dvd mkdvd iso chvopy vio virtual_media loadopt aix vios vmlibrary mksysb mkcd read_only 18,256 Views
Not a spitting image If you want to create a DVD image on AIX, you can do it right from the command line, without even touching physical media, using the mkdvd command. It was a wonder back in ... well, a long time ago ... when these new-fangled CDs came out...
A journey into the world of VLAN tagging and Virtual I/O!
I just had to share this entertaining presentation with everyone. http://gibsonnet.net/AIX/ibm/Journey_in_VLAN_world.pps It was written by Bernard Lemal. He works for IBM GTS Belgium in AIX support. It's a humorous look at the life of an IP packet and...
from Blog: Chris's AIX Blog
AIX 7.1 new install in 25 minutes (Fun, v.1)
AnthonyEnglish Tags: installation virtual_media_library vmlibrary upgrade 7.1 aix6 aix7 nim vio aix5 fun migration 6.1 aix 10,346 Views
Fun out of the Sun In the last few days I've had lots of fun with migrations to AIX 6 and 7. And when I say "fun", I don't mean it in its usual technical sense within IT (insurmountable problems, unrelenting stress, obscure workarounds and chronic...
UPDATED: MPIO Health Check? Wait a minute!
AnthonyEnglish Tags: path mpio no_reserve lun pvid health_check single_path lun_id enabled chdev hcheck_interval status aix chpath reserve_policy vio lspv failed 15,351 Views
REDUNDANCY? YOU CAN SAY THAT AGAIN. In a dual-path VIO Server configuration, your SAN LUNs are (hopefully) protected from disk failures by being part of a RAID set of some kind. Ideally you've also got redundancy of adapters, switches, power and .... well a...
VIO Server shell prompt
MarkChandler Tags: oem_setup_env shell prompt ps1 aix vio 9 Comments 15,579 Views
As administrators, many of us enjoy the ability to use the command line tools to quickly and efficiently carry out tasks. This applies to VIO servers as well as plain AIX or GNU/Linux systems. On AIX & Linux, we can easily setup shell prompts to remind us...
from Blog: aixplode
Free coffee with every AIX 7 install
AnthonyEnglish Tags: download entitled_software_support vios virtual_media vio aix beta vmlibrary open aix7 ess 7,841 Views
THE COFFEE CUP HOLDER IN THE COOL ROOM When I went to install the AIX 7 open beta , I used the VIO server virtual media library. Virtual. No need to burn DVDs to put in the coffee cup holder in the IBM machine in the cool room a.k.a. the data centre. Did...
UPDATED: Building a channel under the SEA
AnthonyEnglish Tags: link_aggregation control_channel failover vio aix etherchannel shared_ethernet_adapter trunk virtual_adapter vlan 9,224 Views
MISSION: REDUNDANCY Once you start thinking about redundancy, your pulse beats fast every time you have a whiff of what might be a S ingle P oint of F ailure. When that happens to you, then deep in your heart you know you have a mission in life. IBM Power...
Global footprints: a Whodunnit for VIO server commands
VIO Server command history using lsgcl You'll pardon my dedicating two posts in a row to the VIO Server, but I had to share this one with my loyal readers. You can get a history of all commands on the VIO server command line by logging in as padmin and...
UPDATED: Console access from VIO to LPAR
AnthonyEnglish Tags: lpar padmin terminal_session aix hmc mkvt console vio modem 2 Comments 16,437 Views
See update at end of post. From the HMC, you can open a terminal session to the console of an LPAR. I reminisced about green screens and different console connections available to AIX in this post . But I didn't take account of one of them: you can create...
UPDATED: A SPOT of confusion about NIM
AnthonyEnglish Tags: vmlibrary network_installation_mana... nim resource aix lpp_source vio virtual_media_library spot 2 Comments 8,293 Views
<!-- @page { margin: 2cm } P { margin-bottom: 0.21cm } A:link { so-language: zxx } --> Using (or not using) NIM NIM - the AIX N etwork I nstallation M anager - allows you to install and maintain...


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Communications and Multimedia Security Issues of the New Century: IFIP TC6 / TC11 Fifth Joint Working Conference on Communications and Multimedia Security (CMS'01) May 21-22, 2001, Darmstadt, Germany / Edition 1by Ralf Steinmetz
Pub. Date: 05/31/2001
Publisher: Springer US
The volume contains the papers presented at the fifth working conference on Communications and Multimedia Security (CMS 2001), held on May 21-22, 2001 at (and organized by) the GMD -German National Research Center for Information Technology GMD - Integrated Publication and Information Systems Institute IPSI, in Darmstadt, Germany. The conference is arranged jointly by… See more details below
The volume contains the papers presented at the fifth working conference on Communications and Multimedia Security (CMS 2001), held on May 21-22, 2001 at (and organized by) the GMD -German National Research Center for Information Technology GMD - Integrated Publication and Information Systems Institute IPSI, in Darmstadt, Germany. The conference is arranged jointly by the Technical Committees 11 and 6 of the International Federation of Information Processing (IFIP) The name "Communications and Multimedia Security" was first used in 1995, Reinhard Posch organized the first in this series of conferences in Graz, Austria, following up on the previously national (Austrian) "IT Sicherheit" conferences held in Klagenfurt (1993) and Vienna (1994). In 1996, the CMS took place in Essen, Germany; in 1997 the conference moved to Athens, Greece. The CMS 1999 was held in Leuven, Belgium. This conference provides a forum for presentations and discussions on issues which combine innovative research work with a highly promising application potential in the area of security for communication and multimedia security. State-of-the-art issues as well as practical experiences and new trends in the areas were topics of interest again, as it has already been the case at previous conferences. This year, the organizers wanted to focus the attention on watermarking and copyright protection for e commerce applications and multimedia data. We also encompass excellent work on recent advances in cryptography and their applications. In recent years, digital media data have enormously gained in importance.
Product Details
- 9780792373650
- Publisher:
- Springer US
- Publication date:
- 05/31/2001
- Series:
- IFIP Advances in Information and Communication Technology Series, #64
- Edition description:
- 2001
- Pages:
- 428
- Product dimensions:
- 1.06(w) x 6.14(h) x 9.21(d)
Table of ContentsPreface. Conference Committees. Web Security. What You See Is What You Sign - Trustworthy Display of XML Documents for Signing and Verification; K. Scheibelhofer. XML Electronic Signatures; G. Karlinger. An integrated secure Web architecture for protected Mobile code distribution; M. Jalali-Sohi, et al. Secure and anonymous multicast framework; N. Weiler, B. Plattner. Vulnerabilities and Security Limitations of current IP Telephony Systems; R. Ackermann, et al. Watermarking I. Quantization Watermarking in the JPEG2000 Coding Pipeline; P. Meerwald. Theoretic Performance Analysis of a Watermarking System based on Bernoulli Chaotic Sequences; S. Tsekeridou, et al. Scalable Detection of Perceptual Watermarks in JPEG2000 Images; D. Simitopoulos, et al. Cryptographic Algorithms. Collecting randomness from the net; B. Bencsath, I. Vajda. Encryption System Based on Neutral Network; C.-K. Chan, et al. A Modified Chaotic Cryptographic Method; W. Wong, et al. An Elliptic Curve Random Number Generator; I. Lee, K. Wong. Watermarking II. Conditional and User Specific Access to Services and Resources Using Annotation Watermarks; J. Dittmann, et al. Large Scale distributed watermarking of multicast media through encryption; R. Parviainen, P. Parnes. Copyright Protection Protocols Based on Asymmetric Watermarking: The Ticket Concept; S. Craver, S. Katzenbeisser. Fingerprints for Copyright Protection; S. Encheva. System Security. Software Security Assessment through Specification Mutations and Fault Injection; R. Kaksonen, et al. Asynchronous Large-Scale Certification Based on Certificate Verification Trees; J. Domingo-Ferrer, et al. ACLA: A Framework for Access Control List (ACL) Analysis and Optimization; J. Qian, et al. Transparent Access to Encrypted Data Using Operating System Network Stack Extensions; E. Rademer, S.D. Wolthusen. A PC Cryptographic Coprocessor Based on TI Signal Processor and Smart Card System; M. Markovic, et al. Watermarking III. Optimization of Watermarking Performances Using Error Correcting Codes and Repetition; S. Zinger, et al. Using Raw Speech as a Watermark, does it work? P. Nintanavongsa, T. Amornraksa. Multiple Security Aspects. Transferability in Coin Systems with Observers; C. Fremdt, H. Neumann. Secure iLearning; F. Graf. Tree-based Multicast Key Agreement; J. Schwenk, et al. Security for the core network of third generation mobile systems; G. Horn, et al. Secure Internet Phone; P. Horster, et al. Posters. Secure Meeting Scheduling with AgenTa; T. Herlea, et al. Virtual Hidden Network; N. Shin. Gaussian Pixel Weighting Mark in Amplitude Modulation of Color Image Watermarking with 8 Neighborhood Retrieval; R. Puertpan, et al. A Prepositioned Secret Sharing Scheme for Message Authentification in Broadcast Networks; A. Eskicioglu. Secure Service Centered Networking for Nomadic Usage; M. Hollick. Last Minute Papers. A Secure Authentication Infrastructure for Mobile Communication Services over the Internet; I. Dupre la Tour, et al. Blind Compressed-Domain Watermarking for MPEG-encoded Videos; C.-L. Wu, et al. Index of Contributors.
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We are proud and excited to announce the 3rd Eindhoven Maker Faire, happening 10 and 11 September.
Save the date for an amazing weekend full of creative makers, inventors, artists, engineers, software developers, game makers, designers, architects, hobbyists, crafters, robots and more…
We are preparing for an inspiring and playful event, where makers share and teach and inspire a broad public.
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Click here to print the obituary below
John Henry Smith Jr.(1949 - 2014)
John (Jack) Henry Smith Jr., 64, of Mountaintop, Pa., went to be with his Lord and Savior on Saturday March 15, 2014. Jack was born in Orange, N.J., on December 12, 1949, to Rosemary Smith and the late John Henry Smith Sr. He attended Roselle Catholic High School. He served in the Marines from 1968 to 1970 aboard the USS America as a sergeant. He was in car sales since 1974 and worked at Coccia Ford and Marcum Motors until his retirement.
Jacked loved fishing and he loved all animals. He loved to help those who were less fortunate, giving them money if he saw them looking in need. He will be missed by many.
Jack was predeceased by his father, John H. Smith Sr. He is survived by the love of his life for thirty three years, Debra Smith; his mother, Rosemary; his brother, Phillip and his wife, Diane, their daughter, Jillian; his sons, John H III, Brian and Michael; daughters, Shannon and Shawn; several grandchildren; and many aunts, uncles and cousins.
As per his request, there will be no viewing. A memorial service will be held at the Back Mountain Harvest Church on Saturday, March 22, at 11 a.m. McCune Funeral Service Inc., Mountaintop, Pa., is handling the arrangements.
In lieu of flowers, donations may be made in Jack's name to Hospice of the Sacred Heart, 600 Baltimore Drive, Wilkes-Barre, PA.
Funeral Home
McCune Funeral Service - Mountain Top
80 Mountain Blvd South
Mountain Top, PA 18707
Published in Scranton Times on Mar. 19, 2014


text: August 22 Time: 8 AM- 2 PM Location: Mt. Hood Meadows Category: Summer Event An uphill running or walking race beginning in the main parking lot and finishing at the top of Stadium Chair for a total of 1.2 miles with 621 feet of elevation gain. Following the finish competitors will ride the Stadium Chair back down to the base area. The top man and woman will receive $120 in prize money! Registration will be at 8 AM in the main lodge. Race starts at 10 AM. BBQ on the Paradise Deck starting at 11 AM. Online Registration is closed, day of registration will start at 8am in Higher Grounds at the ski area and close at 9am. Adult 20 and Over Registration - $25 Junior 19 and Under Registration - $15 Chairlift Spectator Registration - $10


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We regret that due to the technical limitations of our site, we are unable to offer eBooks or Audio Downloads to customers outside of the UK.
For further details please read our eBooks help.
Last Years of the Waverley Route (Hardback)David Cross
Hardback Published: 25/08/2010
- Not available
Popularly known by the name 'Waverley Route, after the novels of Sir Walton Scott whose house was alongside the line, the ex-North British Railway line from Edinburgh to Carlisle via Hawick was opened between Edinburgh and Hawick in 1849 and thence to Carlisle in 1862. The southern section all but bankrupted the NBR prior to the opening of the Midland Railway's Settle-Carlisle route in the late 1870s when the two companies commenced a through service from Edinburgh to London via these two iconic lines. In 1923 the route passed to the LNER and to BR in 1948. However, amidst much controversy, the line was closed in 1969 although since then campaigning for the partial or complete restoration of the line has gained momentum. In 2006, the Scottish Parliament approved the reopening of the section from Newcraighall - where the suburban services had been extended in 2002 - to south of Galashiels with work scheduled to start in 2009 with reopening planned for 2011. This will include c5000 words of text allied to c 200 primarily mono illustrations, although the book will also include a brief colour section, featuring the line between the end of World War 2 and closure in 1969.
Publisher: Oxford Publishing Co
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I need HELP!!
Started Mar 26, 2014 | Discussions thread
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New Member • Posts: 9
I need HELP!!
Mar 26, 2014
I am looking to buy a camera for my girlfriend for Mother's Day. I have done research but a lot of the things I read come with acronyms that are another language to me. I wanna get her a decent Digital camera with a lens or something aha! She will be using to take pictures of our daughter, herself and maybe some landscape pictures of clouds or trees or what not sometimes. Then of course for like holiday functions and get together's. Can someone please point in the right direction of some cameras and why you would pick those ones. I appreciate it more than you know!
Thanks to whoever helps aha!
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Taj Mahal Hotel, Delhi Overview
Check Room Rates and Reservation Availability in Taj Mahal Hotel, Delhi
Taj Mahal Hotel, Delhi Details
Taj Mahal Hotel Hotel Overview
2.8 km from India Gate, Business Centre, Fitness Centre, Swimming Pool, Spa, Beauty Salon, Meeting Rooms & Outdoor venues, Library, Work Stations, 5 speciality restaurants, including the famous Machan Restaurant. Located in the heart of the capital city, The Taj Mahal Hotel is a 5 star luxury property. Easy accessibility from Indira Gandhi International Airport, New Delhi Railway Station, as well as prime business centres of the city makes it a preferred choice of discerning travellers. This hotel has 294 rooms, including 27 suites that are complete with all modern amenities. Rooms are categorised as Deluxe Rooms, Luxury Rooms, Taj Club Rooms, Executive Suites, Luxury Suites and The Grand Presidential Suites. The prime location combined with unmatched facilities, makes the hotel suitable for both business and leisure travellers. Three conference rooms, fitness centre, swimming pool, wellness spa, salon, and shopping arcade. The conference rooms are replete with latest audio visual aids. Upon request, the hotel provides video conferencing and secretarial service. During leisure, guests can enjoy sauna, jacuzzi, steam bath and yoga sessions. Additionally, the hotel provides free Wi-Fi upto 2 devices. For a unique and memorable dining experience, the hotel features five restaurants - Machan (multi-cuisine), The Grill Room (Mediterranean, European), House of Ming (Chinese), Wasabi by Morimoto (Contemporary Japanese) and Varq (Indian). At Emperors Lounge, guests can enjoy sumptuous beverages and dessert. For innovative cocktails and wines, guests can visit Ricks bar. Do not forget to visit the on-site Taj Khazana store that offers skilfully woven pashmina shawls and stoles. more...
Taj Mahal Hotel, Delhi Hotel DetailsDetails for Taj Mahal Hotel, Delhi. Taj Mahal Hotel, Delhi Hotel - Book Online hotel rooms of Taj Mahal Hotel, Delhi at discounted rates. Read 167 reviews, see photos & videos of Taj Mahal Hotel, Delhi at MakeMyTrip.com
By ONO HIROSHI
on 27 December, 2011
very good.
By Nisha
on 08 August, 2010
Taj is Taj. Undoubtedly the greatest of all. Ambience, staff, rooms all were awesome. The washrooms should be a little bigger which I think is the only minute negative part for the hotel. Rest it is a Mahal. Just want to mention the best woodwork and crafting I have ever seen in any hotel.


text:
Item #: 2264403 Size: 0.5 oz
FREE deluxe sample Protect and Perfect Advanced Serum with any $35 Boots purchase (offer valid 4/17/16-5/8/16 or while supplies last)
Reviewed by 1 customer
Best Uses
Comments about Boots Botanics Organic Hydrating Eye Cream:
I use this product before my face moisturizer am and pm. It's very light I never feel greasy after applying. I have combo oily skin. I have noticed my eyes looking more radiant and hydrated after two weeks of using. It's decent and affordable.


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Eight-year-old Nicholas Loughton was thinking of going out for Halloween dressed as a mad scientist. Instead, the bright-eyed Saanich student will be on Parliament Hill tomorrow lobbying for more money for real scientists, the kind who do diabetes research.
The Grade 4 student is one of about 40 children with juvenile diabetes chosen to let lawmakers know what it's like to live with the incurable disease and convince them to ante up $25 million a year over the next five years for science.
He's rehearsing his pitch: "We think a made-in-Canada cure is possible."
And how many needle-pricks since his diagnosis just before turning three: "About 15,000."
His mother Renate Schoep finds it hard to think about the possible consequences of long-term diabetes without a cure. They can include blindness and amputation. When kids are diagnosed as toddlers, they might need heart bypasses by 30.
Yes, her son's diabetes is under control but "there's a fragility" to being under control. The cost is 24-hour vigilance.
Research funding should be a national priority, she says: "It's a very straightforward, quality-of-life thing and a financial investment in the future."
The Juvenile Diabetes Research Foundation estimates that it costs Canada more than $13 billion a year in health care, absenteeism and lost productivity.
Nicholas's friend William van den Broek plans to trick or treat as a little devil. But as usual, his mother will buy all the candy he collects as "a bribe" for not eating while running with the rest of the kids.
"It's a tradition," says the soccer-loving nine-year-old Victoria boy.
When William goes door to door, he'll be wearing what he has worn since June -- the latest in high-technology diabetes management. It's called the Paradigm Real Time Insulin Pump and it retails at $7,400. It's not covered by the Medical Services Plan and not by all extended health plans, either.
William is one of the first children in Canada to have the sensor/pump and one of the youngest in B.C. Most insulin pumps don't have built-in sensors.
The device is attached to his buttock by a tiny catheter, with a wire connected to a transmitter able to send information every five minutes about glucose levels to his insulin pump. In turn, the pump emits a small amount of insulin every three minutes, negating the need for several injections of insulin every day. It even has an alarm system if glucose levels go too high or low
The device presented a "big learning curve," but his mother Janet Noden can't imagine life without it now. "All of a sudden you have a much better picture of what is going on. Having that alarm, especially for low blood sugar at night, I felt like a thousand pounds had been lifted off my shoulders."
There are 1,800 children with Type 1 diabetes in B.C. but only 75 have the sensor/pumps, says David Currie, western regional manager for Medtronic of Canada, which markets the device.
The Ontario government recently announced $42 million for continuous-insulin pumps for all 6,500 children with Type 1 diabetes in that province.
In B.C., such devices are not covered. But Pharmacare is reviewing coverage for all diabetes medications and supplies including the pump to ensure that current policies are appropriate, says Ministry of Health spokeswoman Sarah Plank.
It's a move that should be followed outside Ontario because pumps have been shown to improve control of diabetes, says Zaheer Molu of the Juvenile Diabetes Research Foundation.
Molu also says that the Ontario investment shows that if there is big money for beneficial devices, there should be national funds for research toward a cure.
"The more research we can fund, the faster that cure is going to come," adds Rita Thodos, acting regional manager for the B.C. office of the foundation.
Canada has one of the highest rates in the world of juvenile diabetes and it's rising fast. It also has one of the lowest rates of government funding, Molu adds.
Typically, the Canadian government funds about $7 million in research a year; the foundation supports $10 million to $12 million in Canada through donations.
Definition of Juvenile Diabetes, also called Type 1: an auto-immune disease that destroys the cells in the pancreas that produce insulin.
How many Canadians have Type 1: 200,000
Number of B.C. children with Type 1: 1,800
Increase in rate of incidence in children under 14: 3-5 per cent a year
Years it shortens the average life span: 15
Amount raised in Canada by the Juvenile Diabetes Research Foundation: $60 million in the past five years with a campaign to raise $100 million by 2009.
Amount raised last year in B.C.: $2.6 million.


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Whitaker Collection by Feiss
The Whitaker Lights line by Feiss is an elegant take on a traditional design. Straight, even lines of astral bronze finishes show off the clean diffused light from within. Highly appealing these lights will highlight any space. All lights are shipped with matching bulbs for your convenience.
Feiss - OL7400ASTB - Whitaker Astral Bronze 2 Light Outdoor Wall Lantern$181.00
Feiss - OL7402ASTB - Whitaker Astral Bronze 3 Light Outdoor Wall Lantern$259.00
Feiss - OL7407ASTB - Whitaker Astral Bronze 4 Light Outdoor Post Light$309.00
Feiss - OL7411ASTB - Whitaker Astral Bronze 3 Light Outdoor Pendant$339.00


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King_Penguin Feb 2, 2013 5:20 AM
in response to nvnvalli
What version you can update to will depend upon what device that you have and what it supports e.g. an iPhone 3G only supports up to iOS 4.2.1
If you already have iOS 5+ on your device then you should have a Settings > General > Software Update option on it for update directly on it, if you have iOS 4 or below then you can only potentially update via a computer's iTunes.
To update via a computer, connect the device to your computer's iTunes and copy any purchases off the it to your computer via File > Transfer Purchases (File > Devices > Transfer Purchases on iTunes 11). You may also want to copy photos and any important documents off the device as well e.g. via the file sharing section at the bottom of the device's apps tab when connected to iTunes, via wifi, email, dropbox etc - they should be included in the backup, but it's best to have a copy of them outside of the backup just in case. You can then force a backup of the device by right-clicking the 'Device' on the left-hand side of iTunes and selecting 'Backup'.
Then start the update (if one exists) by selecting the device on the left-hand side of iTunes (on iTunes 11 you can enable the left-hand sidebar via option-command-S on a Mac, control-S on a PC), and on the Summary tab on the right-hand side clicking the Check For Updates button
Updating to iOS 5+ : http://support.apple.com/kb/HT4972
It will update to the highest iOS version available for it.


text:
Showing available accommodation2 guests USD Change dates
Sorry, we couldn't find any available accommodation that matches your search criteria.
Try removing some filters.
For resorts in the area, walk-in-guests are about as common as snowstorms; if you can convince the suspicious security guards that your intentions are innocent and make it to the front desk, you'll be quoted rates that absolutely nobody staying at the resort is paying. Book all-inclusive vacations online or through a travel agent, as they can offer discounts of up to 50% off rack rates. Bear in mind that most resorts cater to a particular niche, whether it's families, honeymooners, golfers or the Spring Break crowd.
Try removing some filters.