text:
|Publication number
|Publication type
|Application number
|Publication date
|Jun 15, 1993
|Filing date
|Mar 28, 1991
|Priority date
|Mar 28, 1991
|Fee status
|Publication number
|Frank D. Ferraiolo, John E. Gersbach, Ilya I. Novof
|Original Assignee
|International Business Machines Corporation
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (25), Non-Patent Citations (8), Referenced by (44), Classifications (20), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
1. Technical Field
This invention relates in general to communication systems and information and data processing systems, and more particularly, to techniques for evaluating data link performance by measuring the quality of data received through the link.
2. Description of the Prior Art
By way of explanation, a digital communication link, such as a high speed fiber optic data communication link, typically consists of a transmitter, a line (for example, an optical fiber) and a receiver. In a fiber optic communication link, the transmitter converts electrical data signals into optical pulses and couples them into the optical fiber. The optical signal is typically attenuated and distorted as it passes through the optical fiber. At the receiving end, a photodetector converts optical signals into electrical data pulses and, conventionally, a link status monitor measures the amplitude of the photodetector output current.
In one status monitoring technique, if the average photocurrent amplitude exceeds a predefined level, an assumption is made that the arriving data is valid. Conversely, if the average photocurrent is less than the predetermined level, it is assumed that there is a broken fiber or other failed link component, e.g., a failed transmitter module (see Cooke et al., "Integrated Circuits for a Two Hundred - Mbit/s Fiber Optic Link," IEEE J. Solid State Circuits, Vol. SC-21, No. 6, December, 1986). Another known method of monitoring link status is based on peak detecting of the analog signal from the receiver (see Uda et al., "Integrated Optical Fiber Data Link Transmitter/Receiver for Local Area Network Application," Fiber and Integrated Optics, Vol. 5, Nov. 3, 1985).
Both of the above-identified analog-type link status monitoring techniques indicate whether the optical power level (i.e., amplitude) is satisfactory, but neither provides information on possible subtle degradation in data signal quality. In the case of degradation, the data signal still passes through the digital data link, but data jitter may exceed or be close to exceeding predefined specification requirements for the link. This data timing jitter may result in the data bit error rate becoming unacceptably high. Such a situation could occur, for example, if the optical fiber became damaged or the optical connectors became obstructed.
Pursuant to the present invention, timing jitter, which is used as a measure of circuit degradation, is measured as a deviation from the ideal time position of the received signal. Three types of jitter are normally identified in fiber optic communication links, i.e., duty cycle distortion, data dependent jitter and random jitter (see "American National Standard for Information Systems -- Appendix E -- System Jitter Allocations," Rev. 4, April, 1989). Duty cycle distortion, also called pulse width distortion, is often caused by differences in propagation delay between low-to-high and high-to-low data transitions. Data dependent jitter is caused by imperfections in gain and phase characteristics of the transmission channel. It is also partially due to inter data symbol interference from a bandwidth limited non-Nyquist channel. Data dependent jitter also includes effects of non-dc balanced coding. Random jitter is caused primarily by thermal noise and normally its average is zero. The major contributor of random jitter is the optical receiver. In summary, applicants are unaware of any pre-existing digital technique which monitors data timing jitter as a measure of the quality of the data link over which the data has been received.
In view of the above, there exists a need in the art for a data link performance monitor capable of evaluating data link performance degradation before an actual fail occurs and, in particular, for such a monitor/diagnostic tool which digitally evaluates the received data signal quality (i.e., by analyzing data timing jitter) as an indication of data link performance.
The present invention comprises in one aspect a method for evaluating a digital data link having a stream of digital signals serially transmitted therethrough at a certain clock rate. The method includes the steps of: sorting in time a plurality of data edge transitions of the serial stream into n time intervals, the cumulative length of the n time intervals being substantially equal to the data stream clock rate; comparing the number of data edge transitions sorted to each of the n time intervals with a predetermined threshold level; generating, in response to the comparing step, a monitor signal for each of the n time intervals, a first monitor signal being generated if the number of data edge sorts in a time interval exceeds the predetermined threshold level and a second monitor signal being generated if the number of data edge sorts in a time interval is less than the predetermined threshold level; and evaluating the data timing jitter of the stream of digital signals transmitted through the data link by an analysis of the monitor signals generated.
As enhanced processing, the method may include the step of generating, in response to the evaluating step, a flag signal indicative of the performance of the digital data link. The generated flag signal may include: a first flag representative of negligible data timing jitter in the digital signal stream; a second flag indicative of data timing jitter marginally meeting predefined data link specification, and a third flag representative of excessive data timing jitter, i.e., jitter failing to meet predefined data link specification. If desired, additional flag signals could also be provided. Further method features are also described and claimed herein.
In another aspect, the invention comprises a circuit for evaluating the data timing jitter of a stream of digital signals serially transmitted through a digital data link at a certain clock rate. The circuit includes sorting means for sorting in time each of a plurality of data edge transitions of the serially transmitted data stream to one of n successive time intervals. The cumulative length of the n time intervals is substantially equal to the data stream clock rate. The circuit also includes comparing means coupled to the sorting means for comparing the number of data edge transitions sorted to each of the n time intervals with a predetermined threshold level, and generating means for generating a monitor signal for each of the n time intervals. A first monitor signal is generated if the number of data edge sorts to the particular time interval under evaluation exceeds the predetermined threshold level and a second monitor signal is generated if the number of data edge sorts to the particular time interval is less than the predetermined threshold level. Lastly, evaluating means evaluates the data timing jitter of the stream of digital signals serially transmitted through the link through an analysis of the generated monitor signals as an indication of the performance of the digital data link.
In one specific embodiment, the circuit includes n counters, each of the counters being coupled to receive data edge sorts to a corresponding one of the n time intervals. Further, n comparators may be provided, each comparator being coupled to a respective one of the n counters for comparing the number of data edge transitions sorted to its respective counter with the predetermined threshold level. The outputs of the n comparators may comprise the generated monitor signals. Further specific circuit details are also provided and claimed herein. For example, the monitoring technique of the present invention may be used contemporaneous with the data retiming method set forth in a commonly assigned, co-pending patent application entitled "Digitally Integrating Clock Extractor," which is summarily discussed herein.
The present inventive technique, whether method or circuit, features the creation of a histogram of a preselected number of data edge transitions and the use thereof to evaluate data timing jitter. The timing jitter measurement technique described herein is advantageously accomplished contemporaneous with clock extraction and utilizes much of the same digital circuitry. The technique is suitable for high speed applications, and data jitter measurement accuracy is designable to particular application requirements. The technique can be realized in hardware or in hardware/software combinations.
These and other objects, advantages and features of the present invention will be more readily understood from the following detailed description of certain preferred embodiments of the present invention, when considered in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram representation of a digital phase locked logic (DPLL) data retiming circuit useful in combination with the present invention;
FIG. 2 is a block diagram representation of a data edge phase sorting circuit useful in combination with the present invention;
FIG. 3 is a graphical representation of a histogram of sorted data edge transitions useful in explaining the present invention;
FIG. 4 is a block diagram representation of n counters and n associated comparators of one embodiment of the present invention; and
FIG. 5 is a block diagram representation of decision circuitry of one embodiment of the present invention.
As noted above, this invention presents a novel technique for the digital measurement of timing noise inherent in data received over a digital data link, such as a communication link and, more particularly, a fiber optic communication link. This monitoring and/or diagnostic technique advantageously permits data timing jitter measurement simultaneous with clock extraction, and beneficially uses much of the same circuitry and associated signals as the clock extraction approach described in co-pending application Ser. No. 07/594,242 entitled "Digital Integrating Clock Extractor," assigned to the same assignee as the present invention, and the entirety of which is hereby incorporated herein by reference. Briefly described, the technique set forth in this co-pending application allows for selection of an appropriate clock signal, from a plurality of locally generated clock signals of different phase, for use in retiming a serial data stream. The technique is based on the integration and periodic analysis of a plurality of time sorted data edge transitions. The performance monitoring/diagnostic technique of the present invention readily integrates with this digital integrating clock extractor in that the histogram created to drive the selection of a retiming signal is also used to evaluate data timing jitter, and thus the quality of the data link through which the data is received.
A generalized embodiment of a data retiming circuit, denoted 10, is depicted in FIG. 1. Retiming circuit 10 includes a digital phase locked logic circuit (DPLL) 12, a clock phase generator 14, a multiplexer 16 and an edge triggered D-latch 18. DPLLs are now well known in the art and will therefore not be described in detail herein. (An early survey is given in an article by W. C. Lindsey et al., entitled "Survey of Digital Phase Locked Loops," Proceedings of the IEEE, Vol. 69, No. 4, pp. 410-431, April, 1981.) In operation, a serial stream of clock and data signals to be retimed, and subsequently deserialized, is received on line 13 which is coupled to an input of DPLL front end circuit 15. DPLL front end circuit 15 results from a somewhat arbitrary division of DPLL 12. Circuit 15 receives from generator 14 on line 17 a plurality of clock signals of different phase. Generator 14 and circuit 15 components may include, for example, a local clock generator, a clock delay line and data edge sorting circuitry. One circuit embodiment of these components is described by E. A. Zurfluh in U.S. Pat, No. 4,677,648, entitled "Digital Phase Locked Loop Synchronizer," assigned to the same assignee as the present invention. Another, and preferred approach to data edge transition sorting is described in co-pending application Ser. No. 07/550,516, entitled "Data Edge Phase Sorting Circuits," also assigned to the same assignee as the present invention, and the entirety of which is hereby incorporated herein by reference. An overview of this edge sorting circuitry is briefly described herein with reference to FIG. 2 hereof.
As shown in FIG. 2, a serial stream of data signals and clock signals is fed via line 31 to + on data edge detect circuit 32. Circuit 32 extracts either the rising, falling, or both the rising and falling data edge transitions occurring on line 31. The circuit generally comprises a single shot pulse generator which provides, for example, a positive output pulse to a non-sequential sorting logic circuit 38 upon receipt of a data edge transition of the desired type. Non-sequential sorting logic 38 compares these output pulses from detect circuit 32 with a plurality (n) of delay clocks f(0), f(1) . . . f(n-1), f(n) generated by a delay line 36 driven by the local master clock 34. Non-sequential sorting logic 38 outputs signals S(1), S(2) . . . S(n-1), S(n), which again flag a data edge transition location relative to the local clock. The frequency of occurrence of each sorted output is stored in n subsequent counters discussed below in connection with FIG. 4.
Returning to FIG. 1, and as already noted, DPLL front end circuit 15, through its data edge sorting circuitry (FIG. 2), outputs a plurality of pulse signals, S(1), S(2) . . . S(n-1) & S(n), on an equivalent number of lines 19 which are coupled to a choose correct clock circuit 20. Circuits 15 and 20 essentially comprise digital phase locked logic circuit 12, as shown in phantom in FIG. 1. The n outputs S(1), S(2) . . . S(n-1) & S(n) from circuit 15 represent discrete time intervals relative to the DPLL local clock. The leading edge of one time interval occurs precisely at the trailing edge of the previous interval. A pulse signal for each data edge transition of the serial stream is provided on a corresponding one of the n outputs of circuit 15 to signify the location in time of the transition relative to the DPLL local clock.
Choose correct clock circuit 20 operates to select a proper local clock phase for use in data retiming from a plurality of local clocks of identical frequency but different phase. As described above, pursuant to the cross-referenced application clock selection is made based upon an analysis of the historical distribution of a predefined number of data edge transitions. In practice, the local reference clock produced by generator 14 and used by DPLL circuit 12 is configured to cover one period or slightly more of the input data clock, which is assumed known. This guarantees that each data edge transition will be detected and sorted into one of the n time intervals. Those counters (see FIG. 4) associated with the time intervals where data edge transitions are occurring will accumulate counts at a faster rate than the remaining counters, even under a jitter or high noise condition. This information is beneficially used to select an appropriate clock signal phase, as well as pursuant to the present invention to monitor/diagnose the data link performance. Counters (FIG. 4) within choose correct clock circuit 20 thus integrate (i.e., accumulate a histogram or historic overview of) the locations of successively sorted data edge transitions. This histogram is advantageously used herein as explained further below with reference to FIG. 3 hereof.
Continuing with the retiming function, an identification of a selected clock signal is output from DPLL 12 on line 21 to a multiplexer 16 which also receives as input (on line 23) a plurality of local clock signals of different phase produced by clock phase generator 14. The output (on line 25) of multiplexer 16 is fed to the clock input "C" of the edge triggered data latch 18. A second data input "D" to latch 18 is coupled to line 13 for receiving the serial data stream. Data is latched on either the rising or falling clock edge. Retimed data is output from latch 18 on line 27, for example, to a deserialization circuit (not shown).
Graphic representation of a plurality of sorted data edge transitions is shown in FIG. 3. In this case, n clock phases have been used to sort data edges into n successive time intervals or time segments. The first time interval is from t(0) to t(1), the second one from t(1) to t(2), etc . . . , the nth time interval is from t(n-1) to t(n). As noted above, these time intervals are selected to cover the entire data clock period T. Times t(0), t(1) . . . t(n) are the time shifts of the clock phases f(1), . . . f(n) in reference to f(0). The degree of timing or horizontal shrinkage of the eye can be derived from the information depicted in FIG. 3 (see Transmission Systems for Communications. AT&T Bell Lab, Ch. 30, Ed. 5).
The measurement of the total timing jitter is the effective symbol duration decrease or amount of horizontal shrinkage of the eye diagram, as defined by equation (1). ##EQU1## For example, a generalized threshold level 50 can be chosen for comparison with the number of data sorts collected within each time interval. If the number of data sorts collected in a particular time interval is above the threshold level 50, then (as shown in FIG. 3) a "1" is assigned to that time interval, while if the total number of data sorts collected in a time interval is less than the threshold level 50, then a logic "0" is assigned to the interval. The horizontal shrinkage of the eye (e.g., time between spaced intervals having counts above the threshold level) can thus be measured based on this comparison. The total time interval can be determined by summing the time intervals having data edge sorts below the threshold level.
FIG. 4 depicts a threshold circuit comparison technique, which pursuant to one embodiment of the present invention is resident within choose correct clock block 20 of FIG. 1, wherein the number of data edge sorts falling in each of n time intervals are sorted in n corresponding m-bit counters 60. There are n comparator circuits 62 that compare counts of the n counters with a predetermined threshold level. As shown, each comparator 62 implements a word-by-word comparison wherein the m-bits of each counter 60 are compared with a corresponding number of bits of a preselected reference threshold level. If desired, the threshold level for one or more time intervals may be set at a different predetermined number from other time intervals to increase the sensitivity of the monitor to changes in the quality of the link. If the count in a particular time interval counter is below the corresponding threshold level the threshold circuit generates a zero (0) monitor signal and, conversely, if the count is above the threshold level, the threshold circuit generates a one (1) monitor signal. The equivalent condition can be assigned to either monitor signal.
The comparator outputs, Output 1, Output 2, . . . Output n, of the threshold circuit are, for example, coupled to decision logic 70, which is shown in FIG. 5 and, in one embodiment, is resident within choose correct clock block 20 of FIG. 1. Logic 70 outputs to another portion (not shown) of the communication/data processing system one of a plurality of possible flags (based upon the monitor signals received as outputs from comparators 62) as an indication of received signal quality. By way of example, logic 70 may incorporate pre-established criteria that states that receipt of: three or more zero (0) monitor signals in a row, i.e., on Outputs 1, 2 . . . n, is representative of a good quality link, resulting in a first flag being output; only two zero (0) monitor signals in a row is representative of a marginal quality data link, resulting in a second flag being output; and only one zero (0) monitor signal, or none, is indicative of a bad data link, requiring a third data link to be output from the decision logic. Those skilled in the art will recognize that these criteria, again provided by way of example, may be modified in a number of ways, and implemented with a number of different circuits or hardware/software combinations. For example, a processor with supporting registers and read only memory could be used to implement similar evaluation functions.
Typically, the worst case yet acceptable timing jitter level for a particular data link under evaluation will be specified. Assuming this, the monitor of the present invention can be used, pursuant to logic circuitry 70 (FIG. 5), to flag one of the following conditions:
Flag A: data timing jitter is negligibly small (no action required);
Flag B: data timing jitter marginally meets the specification (preventive maintenance is required); or
Flag C: data timing jitter does not meet the specification (repair is required).
Unique to the present invention is the provision of Flag B, i.e., an indication that the digital data link under evaluation has degraded in performance, but not yet broken down completely such that repair is required, which is the only function prior amplitude measuring approaches could accomplish. Further, the quality evaluation technique of the present invention is accomplished during normal link operation.
In another specific embodiment, the decision logic of the present invention could be implemented as a table wherein possible monitor signal combinations from the comparators of FIG. 4 are prestored and an appropriate flag for each combination is identified. In such a case, the outputs of the n comparators are then applied to (compared with) the table to select an appropriate flag. Data timing jitter specification is written into the table in such a way that each input binary word produced by the comparators results in a particular data link performance flag, e.g., Flag A, B or C. Those skilled in the art will recognize that additional flags could also be provided depending upon the level of information desired.
From the above discussion it will be observed that the present invention comprises a novel technique for digitally monitoring or diagnosing timing jitter in a digital data link, to thereby ascertain the quality of the link. The approach advantageously permits timing jitter measurement simultaneous with clock extraction and is suitable for high speed applications. In addition, data jitter measurement accuracy is designable to particular application requirements. Further, the monitor approach presented herein beneficially utilizes much of the same circuitry as the specified co-pending applications on digital integrating clock extraction and data edge phase sorting.
Although one embodiment of the present invention has been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the particular embodiment described herein, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope of the invention. The following claims are intended to encompass all such modifications.
|Cited Patent
|Filing date
|Publication date
|Jan 3, 1979
|Jul 8, 1980
|Kokusai Denshin Denwa Kabushiki Kaisha
|Fault location system for optical repeating paths
|Apr 9, 1979
|Jul 14, 1981
|Kokusai Denshin Denwa Co., Ltd.
|Monitoring system for optical transmission line repeaters
|Mar 30, 1981
|Jan 4, 1983
|Licentia Patent-Verwaltungs-Gmbh
|Method for monitoring the bit error rate of a digital transmission system
|Feb 27, 1981
|Mar 6, 1984
|Hartmann & Braun Ag
|Optical transmission system
|May 3, 1982
|Feb 19, 1985
|General Signal Corporation
|Fiber optic data highway
|Oct 21, 1983
|Apr 1, 1986
|Mitsubishi Denki Kabushiki Kaisha
|Signal quality monitoring device
|Apr 12, 1984
|Dec 9, 1986
|Nec Corporation
|Bit error detection circuit for PSK-modulated carrier wave
|Jul 5, 1983
|Apr 28, 1987
|U.S. Philips Corporation
|Arrangement for locating faults in an optical information transmission system
|May 21, 1985
|Jun 9, 1987
|Kabushiki Kaisha Toshiba
|Sampling clock pulse generator
|Dec 5, 1985
|Jun 30, 1987
|International Business Machines Corp.
|Digital phase locked loop synchronizer
|May 7, 1985
|Dec 1, 1987
|Kokusai Denshin Denwa Co., Ltd.
|Optical repeater monitoring system
|Jun 6, 1988
|Jun 20, 1989
|Grumman Aerospace Corporation
|High speed data-clock synchronization processor
|May 26, 1989
|Jan 8, 1991
|First Pacific Networks
|Method and apparatus for synchronizing digital data symbols
|Oct 4, 1989
|Mar 26, 1991
|Siemens Aktiengesellschaft
|Process for the reception of a binary digital signal
|Oct 23, 1989
|Jun 4, 1991
|National Semiconductor Corporation
|Method and structure for digital phase synchronization
|Mar 9, 1989
|Jun 4, 1991
|Hitachi, Ltd.
|Bit synchronization circuit
|Feb 6, 1989
|Mar 10, 1992
|Motorola, Inc.
|Bit synchronizer
|Aug 26, 1981
|Mar 10, 1983
|Siemens Ag
|Operation monitoring of digital transmission systems
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|Title not available
|"Amer. Nat. Standard for Info. Sys. Fiber Distribution Data Interface (FDDI). Phys. Layer Med. Dep. (PMD)", Amer. National Standards Inst., Inc., Appendix E-System Jitter Allocations, Rev. 4, Apr., 1989.
|Amer. Nat. Standard for Info. Sys. Fiber Distribution Data Interface (FDDI). Phys. Layer Med. Dep. (PMD) , Amer. National Standards Inst., Inc., Appendix E System Jitter Allocations, Rev. 4, Apr., 1989.
|Cooke et al., "Integrated Circuits of a 200 Mbit/s Fiber-Optic Link," IEEE J. Solid State Cir., vol. SC-21, No. 6, 1986. pp. 909-915.
|Cooke et al., Integrated Circuits of a 200 Mbit/s Fiber Optic Link, IEEE J. Solid State Cir., vol. SC 21, No. 6, 1986. pp. 909 915.
|Transmission Systems for Communications AT&T Bell Lab, Chapter 30, pp. 703 715 & 756 & 757, Ed. 5.
|Transmission Systems for Communications AT&T Bell Lab, Chapter 30, pp. 703-715 & 756 & 757, Ed. 5.
|Uda et al., "Integ. Opt. Fiber Data Link Transmitter/Receiv. for Area Net. Appln.," Fiber & Integ. Optics, vol. 5, No. 5, 1985. pp. 273-289.
|Uda et al., Integ. Opt. Fiber Data Link Transmitter/Receiv. for Area Net. Appln., Fiber & Integ. Optics, vol. 5, No. 5, 1985. pp. 273 289.
|Citing Patent
|Filing date
|Publication date
|Dec 14, 1993
|Sep 12, 1995
|Mechanism for monitoring quality of digital telephone link based upon rate of occurrence of illegal bipolar violations
|Dec 21, 1992
|Feb 13, 1996
|Communications Technology Corporation
|Eye pattern margin measurement and receiver stress detection device
|May 9, 1995
|Jul 30, 1996
|Microsym Computers, Inc.
|Single fiber transceiver and network
|Dec 9, 1993
|Oct 1, 1996
|Northern Telecom Limited
|Clock phase shifting method and apparatus
|May 23, 1995
|Apr 1, 1997
|International Business Machines Corporation
|Automated system, and corresponding method, for measuring transmitter duty cycle distortion of electro-optic modules
|May 23, 1995
|Jul 1, 1997
|International Business Machines Corporation
|Automated system, and corresponding method, for measuring transmitter data-dependent jitter of electro-optic modules
|Aug 28, 1995
|Nov 18, 1997
|Alcatel Network Systems, Inc.
|Data recovery circuit with large retime margin
|Sep 10, 1997
|May 11, 1999
|Intel Corporation
|Jitter detection method and apparatus
|Oct 29, 1997
|Nov 30, 1999
|Hyundai Electronics Industries Co., Ltd.
|Parallel bit counter using bit sorters
|Apr 30, 1998
|Jun 12, 2001
|Stmicroelectronics, Inc.
|Automatic on-chip clock tuning methodology and circuitry
|Apr 20, 1999
|Sep 25, 2001
|Arnold M. Frisch
|Jitter measurement system and method
|Jan 29, 1999
|Mar 12, 2002
|Wavecrest Corporation
|Method and apparatus for jitter analysis
|Jun 4, 2001
|Jul 12, 2005
|Intel Corporation
|Adaptive de-skew clock generation
|Oct 4, 2002
|Mar 13, 2007
|Altera Corporation
|Phase-locked loop circuitry for programmable logic devices
|Jul 15, 2003
|May 1, 2007
|Adtran, Inc.
|Data buffer-controlled digital clock regenerator
|May 26, 2005
|Sep 11, 2007
|Intel Corporation
|Methods and apparatus for providing information indicative of traffic delay of a wireless link
|Jun 27, 2005
|Jul 21, 2009
|Method of resynchronizing streams benefiting from circuit emulation services, for use in a packet-switched communications network
|May 30, 2008
|May 18, 2010
|International Business Machines Corporation
|Method and apparatus for improved storage area network link integrity testing
|Mar 9, 2007
|May 10, 2011
|Stmicroelectronics S.A.
|Method for characterizing a bit detection event
|Jun 7, 2011
|Advantest Corporation
|Jitter measurement apparatus, jitter measurement method, test apparatus and electronic device
|Jul 23, 2007
|Oct 18, 2011
|Intel Corporation
|Methods and apparatus for providing information indicative of traffic delay of a wireless link
|Dec 6, 2011
|Cypress Semiconductor Corporation
|Recursive range controller
|Feb 24, 2009
|Nov 6, 2012
|Olympus Corporation
|Clock regeneration circuit
|Dec 17, 2010
|Jul 16, 2013
|Intel Corporation
|Methods and apparatus for providing information indicative of traffic delay of a wireless link
|Aug 4, 2011
|Sep 3, 2013
|Cypress Semiconductor Corporation
|Recursive range controller
|Apr 30, 2012
|Oct 21, 2014
|Qualcomm Incorporated
|Adaptive quality of service policy for dynamic networks
|Jul 15, 2013
|Jan 12, 2016
|Intel Corporation
|Methods and apparatus for providing information indicative of traffic delay of a wireless link
|Jun 4, 2001
|Dec 5, 2002
|Hongjiang Song
|Adaptive de-skew clock generation
|Jul 15, 2003
|Jan 20, 2005
|Adtran, Inc.
|Data buffer-controlled digital clock regenerator
|Jun 27, 2005
|Jan 5, 2006
|Method of resynchronizing streams benefiting from circuit emulation services, for use in a packet-switched communications network
|Mar 17, 2006
|Aug 17, 2006
|Advantest Corporation
|Jitter measurement apparatus, jitter measurement method, test apparatus and electronic device
|May 26, 2005
|Nov 30, 2006
|Qi Emily H
|Methods and apparatus for providing information indicative of traffic delay of a wireless link
|Feb 24, 2009
|Aug 27, 2009
|Olympus Corporation
|Clock regeneration circuit
|Jun 26, 2009
|Nov 12, 2009
|Nec Corporation
|Transmission method, transmitter-receiver, and transmitting-receiving system
|Dec 3, 2009
|International Business Machine Corporation
|Method and apparatus for improved storage area network link integrity testing
|Oct 31, 2008
|Apr 15, 2010
|O'hanlon Shane
|Computer networks
|Dec 17, 2010
|Apr 14, 2011
|Qi Emily H
|Methods and apparatus for providing information indicative of traffic delay of a wireless link
|Aug 23, 2012
|Qualcomm Incorporated
|Adaptive quality of service policy for dynamic networks
|Sep 11, 1996
|Sep 12, 2000
|Integrated Network Corporation
|Performance monitoring for loops
|Mar 26, 1998
|Oct 7, 1998
|Philips Electronics N.V.
|Synchronisation circuit
|Mar 7, 2007
|Sep 19, 2007
|Stmicroelectronics Sa
|Method of characterising a bit detection instant
|Feb 24, 2009
|Sep 2, 2009
|Olympus Corp.
|Clock regeneration circuit
|May 25, 2006
|Nov 30, 2006
|Intel Corporation
|Method and apparatus for providing information indicative of traffic delay of a wireless link
|May 25, 2006
|Jan 25, 2007
|Intel Corp
|Method and apparatus for providing information indicative of traffic delay of a wireless link
|U.S. Classification
|375/226, 370/252
|International Classification
|Cooperative Classification
|European Classification
|Mar 28, 1991
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, A COR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:FERRAIOLO, FRANK D.;GERSBACH, JOHN E.;NOVOF, ILYA I.;REEL/FRAME:005656/0072;SIGNING DATES FROM 19910305 TO 19910328
|Feb 1, 1994
|Certificate of correction
|Sep 3, 1996
|Fee payment
Year of fee payment: 4
|Sep 18, 2000
|Fee payment
Year of fee payment: 8
|Dec 29, 2004
|Maintenance fee reminder mailed
|Jun 15, 2005
|Lapse for failure to pay maintenance fees
|Aug 9, 2005
|Expired due to failure to pay maintenance fee
Effective date: 20050615


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text:
Sarah Palin Makes Case For Abortion
That's what Ruth Marcus claims in today's Washington Post, quoting Sarah Palin's remarks from a—what else—a pro-life fundraiser. At the dinner, Palin discussed her "choice" to have a child with Down syndrome at the age of 44—a choice that, as Marcus points out, Palin wants to deny other women. Marcus is miffed that right-to-lifers like Palin routinely justify their anti-choice positions by describing their own "correct" "decisions" to have children. This isn't the fist time Palin has used choice to explain why women shouldn't chose—who could forget Palin's election-season classic, "We're proud of Bristol's decision to have her baby"?
Palin's pro-"choice" comments—where she describes twice considering abortion before deciding to carry her pregnancy to term—after the jump.
"I had found out that I was pregnant while out of state first, at an oil and gas conference. While out of state, there just for a fleeting moment, wow, I knew, nobody knows me here, nobody would ever know. I thought, wow, it is easy, could be easy to think, maybe, of trying to change the circumstances. No one would know. No one would ever know.
"Then when my amniocentesis results came back, showing what they called abnormalities. Oh, dear God, I knew, I had instantly an understanding for that fleeting moment why someone would believe it could seem possible to change those circumstances. Just make it all go away and get some normalcy back in life. Just take care of it. Because at the time only my doctor knew the results, Todd didn't even know. No one would know. But I would know. First, I thought how in the world could we manage a change of this magnitude. I was a very busy governor with four busy kids and a husband with a job hundreds of miles away up on the North Slope oil fields. And, oh, the criticism that I knew was coming. Plus, I was old . . .
"So we went through some things a year ago that now lets me understand a woman's, a girl's temptation to maybe try to make it all go away if she has been influenced by society to believe that she's not strong enough or smart enough or equipped enough or convenienced enough to make the choice to let the child live. I do understand what these women, what these girls go through in that thought process."
Photo by √oхέƒx™


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April 19, 2016
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by madalyn rothman TWITTER.COM/MADALYNROTHMAN | February 13, 2012 |
The Look: Taylor switched up her usual girlish aesthete with layered looks including leather jumpers over printed sheer blouses and shearling vests over deconstructed tweed peplum tops. There was a yin and yang of '90s punk and feminine flair at play in every ensemble. Our favorite piece came in the form of a charcoal double-faced wool coat in look number 19.
Beauty: Low, undone ponytails recalled the '90s.
Trimmings: Fur booties and python satchels.
Front Row: Ramona Singer, Cat Deeley, Miss J. Alexander, Olivia Palermo.Where to Wear: Down on the Bowery.
photograph by Frazer Harrison, courtesy of gettyimages.com
April 1, 2016
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Video: Tales from the Kitchen – Nike Free
Nike's Innovation Kitchen has cooked up some of the sports world's greatest products and technologies. Tales From The Kitchen Episodes 1 and 2 take a fun look inside the stories of the birth of two Nike best 'recipes', NIKE FREE and NIKE HYPERFUSE.
Check out the Hyperfuse episode after the click.


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Friday meeting in Cape to gather data for rural health plan
Thursday, May 13, 2010
Rural health issues will be the topic of a town hall meeting Friday to gather input for a statewide rural health plan.
The Missouri Office of Primary Care and Rural Health, the Missouri Foundation for Health and the Missouri Rural Health Association are sponsoring the public meeting at 11 a.m. Friday at the Cape Girardeau Public Library in the Hirsch meeting room.
"For many rural Missourians, the access to care locally is more of an issue than it is in an urban setting," said Suzanne Alewine, executive director of the Missouri Rural Health Association, a not-for-profit group. "People have to drive further to get to a doctor or a dentist or for mental health care."
Topics to be discussed include health care access, social services, education and the economy in rural Missouri.
Friday's meeting is one of more than 15 being held around the state as research is compiled to be included in Missouri's next rural health plan, which the federal government requires states to submit every three years, Alewine said.
"We welcome anyone and everyone who is interested," she said.
Pertinent address:
711 N. Clark Ave., Cape Girardeau, MO


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chinnoun [C]uk /tʃɪn/ us /tʃɪn/
B1 the part of a person's face below their mouth: To keep the helmet in position, fasten the strap beneath the chin. She sat behind the table, her chin resting in her hands.
More examples
- There was dribble all over her chin.
- Graham came back from holiday with a week's growth of beard on his chin.
- She was sitting at the desk with her chin propped on her hands.
- With the back of his hand, he rubbed the stubble on his chin.
- A trickle of melted butter made its way down his chin.


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Grateful Dead
Your shirts are incredible! Will definitely be buying some. Thank you for posting. Oh by the way, I lived near Burlington, Wisconsin for 9 years in my childhood, actually close to Alpine Valley before there were shows there. Dates me. Peace to you and keep on, keepin on with your dyes.
If the doors of perception were cleansed, everything would appear to man as it is, infinite.
Wiliam Blake
This is a theoretical question for the moment, but might be of interest to others also--do you take special orders? Specifically, I'm thinking the designs on the tapestries would look great on curtains, which would be much bigger pieces of fabric. Is that practical?
Man those are some unique shirts you have there....
very cool!!
Thanks !!
They're fun to make although sometimes time consuming but it's relaxing to work on dyes, burn incense, and of course...listen to The Grateful Dead...
mustdye's Store...
Real nice :)
HippieChuckhey y'all.anyone got a way to get 4x or 5x dies with dead or mikio or any other kewl psychedelic prints .i can find big size dyes,but none with print on em.would really love the hendrix print we've all seen around in a chubby hippies size.love to you all!!garseeyalater.
I got a brand new, ever been worn or washed with the tag still on it from Liquid Blue a tie dye Space Your Face design shirt size X-Large. Fits more like a Large though, that's why I am selling it. Too small for me. :(
Make an serious offer!! Free shipping in USA only. Outside USA must pay for shipping fees.
In mint shape, PM me if interested or drop me an email over at email@example.com
Looking for eyeglass or sunglass retainers. A neoprene band to hold the glasses on. Grateful Dead logo or some kinda of Deadish print on them. Thanks


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Oklahoma legislator looks to broaden Open Records Act
OKLAHOMA CITY (AP) — A state legislator quizzed two court clerks over why public court records aren't readily available online during a hearing on Oklahoma's Open Records Act.
Norman Republican Rep. Aaron Stiles requested Tuesday's interim study to review how the act applies to certain court files. The hearing was before the House Judiciary Committee.
Stiles questioned Canadian County Court Clerk Marie Ramsey-Hirst and Oklahoma County deputy court clerk Mike Sullivan on their office's decision to withhold some court records from an online system. This forces some people to drive to a county courthouse and pay a fee for the documents.
Ramsey-Hirst says all documents are posted online unless a judge seals them. She said she has also used her own discretion to not post documents with social security numbers and bank accounts.


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0 out of 1 people recommended this dealer.
By writing a dealer review, you can provide valuable insights to other customers.
by unhappy customer from Pearl, MS |
We purchased a car from them last year. We never received our title. We called them on several occasions and they said they were processing the paperwork. We even had the Mississippi department of revenue contact them on one occasion because they were not answering their phone. I believe they are avoiding our calls. We need to have our tag renewed, but we are not able to because they have not filed the paperwork. We paid them cash for the vehicle. The case is being investigated by the attorney general and the department of revenue. The process takes several months, in the mean time we will have a car we can not legally drive. I believe they have a maintenance man screening our calls, the owner is never in when we call; which is often. This has been a horrible experience. My daughter uses this car to drive to college in another part of the state. We were happy with the car, but this dealer is very dishonest. This experience has me wondering if they are doing something illegal. They have put us in a difficult position. I would not recommend them.
Shopped for a new car
Shopped for a used car
Does not recommend this dealer
Did make a purchase


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Video: The Deluxe Influence of Bedwin
We present the latest from Jake Davis Films. Jey Perie is the marketing and public relations man for Japanese company DLX, which houses Bedwin & The Heartbreakers and Deluxe. He gives us an inside look on how the Japanese brands are influenced by classic style. Enjoy!
Director: Jake Davis


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Check out these eight opportunities including Martin Scorsese and Mick Jagger's new HBO series, the Broadway and touring production of "Matilda," and short films on both coasts, as well as a new AMC pilot down in Louisiana.
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Stephen Greenleaf Bulfinch, Post 15
The following excerpt is from the diary of Stephen Greenleaf Bulfinch.
Sunday, July 27th, 1862
Public events, which in this trying time, occupy our thoughts greatly, have of late been very saddening in their character. I refer chiefly to the week of battles near Richmond, where, notwithstanding the skill of Gen. McClellan and the valor of his troops, all that could be accomplished was to gain by a retreat, a safer position, with great loss on both sides, - more probably on the enemy's than on ours. The result has been a comparative pause, while new enlistments are urged, - 300,000 men being called for by the President. The share of Mass is 15000, - that of Dorchester 137. Public meetings are held, - large bounty offered; - many towns have completed their quotas; & ours I hope will do her part. Some are very earnest to have a proclamation of emancipation; but our President, cautious and firm, holds back from what might at present, if it did not arouse the horrors of a slave insurrection, at least divide the North and embitter the South. Gen. Halleck is appointed Commander-in-chief. Congress has confirmed, after passing a Confiscation bill. Three from this town have died in the service; - two, Edward Foster and Ambrose Howe, by sickness; & one, - Dodge, - perhaps more, - in battle. My own young parishioners, thank God! have thus far been spared, as far as accounts have been received.
Bulfinch's pen is silent in August, but look for his next entry in the Beehive in September.
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Oval pendant in sterling silver with 1/7 carat total weight of diamonds. Delicate 18 inch link chain included.
Item No. 11089026
Diamond Oval Disc Dangle Earrings in Sterling Silver "SILVER SPECIAL OFFER"$113.40
Smoky Quartz, Ruby & Diamond Pendant in Rose Gold 14K$1199.00
Diamond Heart Necklace 14K$399.00
Trilliant Morganite & Diamond Pendant in Rose Gold 14K$2199.00
Pear Fire Opal & Diamond Pendant in Rose Gold 14K$3099.00
Morganite, Aquamarine & Diamond Pendant in Rose Gold 14K$1499.00
Garnet, Tourmaline & Diamond Pendant 14K$799.00
Apatite, Imperial & White Topaz Pendant in Rose Gold 14K$1699.00
Pear-Shaped Blue Topaz & Diamond Pendant 14K$1099.00
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Hotel Villa Glicini4
Via Valpellice 68/a, San Secondo di Pinerolo, 10060
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About the hotel
This beautiful leisure complex that takes the name of Hotel Residence Villa Glicini is the result of the minute refurbishment of a magnificent Villa of the 18th century, property of the Marquises Maffei of Boglio. The building was known at the time as "the red house", was the salon of the aristocracy. Cradle of the local activities, the Villa was also the place where were kept important historical documents, some of which undersigned by great Kings and Emperors like Napoleon Bonaparte.
These days, the residential estate is a beautiful 4 stars hotel that offers the maximum comfort in a very inviting and friendly atmosphere. Besides being situated in a strategic point, that makes it the ideal stop for businnessmen, the full leisure complex deserves a visit. The hotel has 38 rooms, a well known reataurant, happy to welcome up to 100 people, a private guarded park, an area especially thought for children, a summer dehor and 2 outdoors swimming pools where it is possible to spend a a relax day. The rooms (2 equipped for disabled people), are all provided with private bathroom with shower and wc, hairdryer, safe, satellite tv, pay tv, minibar, telephone, heating, air conditioning and HDSL connection to internet. Also at the guests' disposal is the new Congress Centre, made up of three meeting rooms that can be jointed to become a very large room (it can contain up to 200 people). These rooms are perfect for small or big meetings, products presentations, business lunches and many other situations. All the rooms are equipped with the most modern conference facilities.
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Room Availability
Showing Wednesday 4 May 2016 to Thursday 5 May 2016Change Search
Facilities Show/hide
- Main
- Hotel Non-Smoking Throughout , Disabled Facilities , Smoking allowed in bedrooms
- In room facilities
- Air conditioning in rooms , Safety Deposit Box , Minibar in each room , Telephone In Each Room
- Hotel services
- 24 Hour Reception , Limited room service for hot food , Concierge , Wake Up Call Available
- Family friendly
- Cots available , Children's Facilities - Outdoor , Pets Allowed
- Parking (charges may apply)
- Car parking available onsite , Airport Shuttle , Car Parking Available Offsite
- Business
- Wi-Fi Available , Meeting Facilities , Wi-Fi Available In Public Areas , Wi-Fi Available In Rooms , Business Centre , Secretary Service , Private dining services
- Dining
- Restaurant , Bar
- Leisure
- Outdoor Pool , Mountain Bike Hire
- In room entertainment
- TV , Satellite TV
- Other
- Doctor on call , Ground floor bedrooms , Lift to all floors , Public Air Conditioning
- Accessibility
- Disabled Access Public Areas , Disabled Access Bedrooms , Disabled toilets on ground floor , Wheelchair Access , Wheelchair Access To Reception , Wheelchair Access To Restaurant , Wheelchair Access To Bar , Wheelchair Access To Conference Rooms , Wheelchair Access To Leisure Facilities , Wheelchair Access To Disabled Car Parking Spaces
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- The price shown is based on the occupancy and dates you have searched for. Prices and availability are subject to change based on the arrival date, number of nights and occupancy searched for. All prices are inclusive of all local taxes.
- Pets are allowed
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