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Armenia–United Kingdom relations
United Kingdom
Armenian–British relations are foreign relations between Armenia and the United Kingdom. The United Kingdom recognised Armenia on 31 December 1991. The first Embassy of the Republic of Armenia in Europe was established in London in October 1992. Since 1995, the United Kingdom has an embassy in Yerevan. The two countries maintain collaborative and friendly relations.
State visits between Armenia and the United Kingdom[edit]
There are various state visits between Armenia and the United Kingdom the latest being the visit of the British State Minister of Europe David Lidington to Yerevan. Additionally President of Armenia Serzh Sargsyan have visited the United Kingdom in July 2012.
Armenian genocide recognition[edit]
Wales, Scotland and Northern Ireland recognise the Armenian genocide, however United Kingdom as a whole does not recognize the Armenian Genocide, as it considers that the evidence is not clear enough to respectively consider "the terrible events that afflicted the Ottoman Armenian population at the beginning of the last century" genocide under the 1948 UN convention. The British government states the "massacres were an appalling tragedy" and condemns them stating that this was the view of the government during that period.[1]
Armenian community of the UK[edit]
According to Vered Amit's Armenians in London: The Management of Social Boundaries, published in 1989, around 10,000 Armenians were living in Greater London at the time. The majority were thought to be first-generation immigrants from Lebanon, Syria, Iraq, Iran and Cyprus.[2] They also include Armenians from Ethiopia, India, Egypt, Israel, as well as individuals from other countries.
Manchester has been home to an Armenian population since 1835, with 30 Armenian businesses thought to have been operating in the city by 1862.[3]
See also[edit]
- ^ http://www.guardian.co.uk/world/2009/nov/03/armenia-genocide-denial-britain
- ^ Talai, Vered Amit (1989). Armenians in London: The Management of Social Boundaries. Manchester: Manchester University Press. p. 1. ISBN 0-7190-2927-9.
- ^ "Multi-Cultural Manchester: Armenians". Manchester City Council. Retrieved 2009-08-22.
External links[edit]
|Wikimedia Commons has media related to Relations of Armenia and the United Kingdom.
- Armenian embassy in London
- armeniangenocide - epetition response 6 December 2007.
- British Foreign and Commonwealth Office about relations with Armenia *British embassy in Yerevan


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Saturday, August 24, 2013 11:52 PM EDT
Football coaches weigh many factors in choosing spring or fall
Having a choice is a good thing. It's no different on the high school football field, according to area coaches.
When the CIAC gave coaches the option five years ago of keeping 10 days of spring practice or opting for an additional four days of the August preseason, they were thrilled.
The question now being asked is whether it works.
Coaches must make a decision of spring or fall practices by May 3 each year, unless there are extenuating circumstances, such as a late coaching change, that may warrant a reverse decision. In recent years, Cheshire, Pomperaug and Sacred Heart have all had springtime coaching moves, forcing a switch to late summer.
At Naugatuck, Craig Bruno was hired last April, but still opted for the traditional 10 days of spring practice, giving him a smoother transition.
"For me, spring practice is mandatory, and really there is no other option for me," said Bruno, the head coach at Bunnell for 12 years. "There are so many advantages to it, along with being able to see guys in pads and get familiar with the new players."
With so many athletes playing spring sports, Derby coach George French V said he can't make a fair decision by May 3.
"I could probably still hold spring practices, but it would include only a quarter of my team if the baseball team makes a strong tournament run," said French.
Derby went to the state baseball finals in 2012, and several players, including Dillon McMahon, who was going to be a two-way starter for the football team, were on both squads.
Holy Cross' Mike Giampetruzzi, in his fifth year as head coach, had been a proponent of spring prac-
See CHOICE, Page 11B
tices. He's been a part of the program since 1991 as a player and longtime assistant coach with the Crusaders, who had always worked out in the spring.
Until this year.
"Right now, I plan on going year-to-year to make a decision," said Giampetruzzi. "After only four days, it is hard to gauge. I'm still on the fence."
Two main reasons caused Giampetruzzi to make a switch in 2013. He was the junior varsity and assistant baseball coach for the Crusaders in the spring, and the Crusaders advanced deep into the postseason.
Second, there were several baseball, track and lacrosse athletes still competing, so Giampetruzzi didn't think it was wise to conduct practice without a full team. The Crusaders added lacrosse in 2012 and will hold their first varsity season in 2014.
"We have so many kids who play multiple sports," said Giampetruzzi, the school's assistant principal.
Holy Cross alum and current assistant coach Eric Barbarito, formerly the head coach at Hillhouse, where he guided the Academics to two state titles, loves having the option.
"There's less pressure in the spring to get things done," said Barbarito. "In the spring, you have three days where you just wear helmets and seven days for contact. It gives you a chance to see kids at different positions. If you have a new quarterback, they need time to develop. And even if you have an (established) starting quarterback, you need to get a second one ready because they are just as important. Quarterbacks are hard to replace."
Another Crusaders assistant coach, Dennis Wanzie, always conducted spring practice during his seven-year tenure as at Wilbur Cross in New Haven.
While coaches make the decision, players have to abide by it. Oxford's Kyle Chudoba was torn between the baseball team, which he pitched to the Class S state championship, and the football team. He wound up missing all but three days of spring football practice.
Chudoba couldn't bask in the glory of winning a state title for long because he needed to sharpen his skills as the successor to two-year starting QB Brennen Diaz.
"I struggled a little bit, going from baseball to football, but I felt that I had a good spring game," said Chudoba. "We have a pretty experienced team. The spring was great for the younger guys so they could get necessary repetitions. Overall, I made some mistakes, but I was able get a lot of work in before the summer camp at Southern Connecticut and the 7-on-7 passing leagues started. So having spring was a real good thing."
Former Cheshire assistant coach Greg Ferry, now in his second year at two-time defending Class LL state champion Xavier of Middletown, said the Falcons love the idea of spring practice.
"It's a great way to kick off the summer," said Ferry. "As long as we are allowed to have the spring, we will do it."
Ansonia coach Tom Brockett, who has won four state titles in his seven-year tenure, is adamant about keeping spring practice.
"As long as I am coaching here in Ansonia, we will have it," said Brockett back in 2008. "It's absolutely necessary."
There are clearly pros and cons, noted Pomperaug coach Dave Roach, in his third year as head coach.
"I I decided on the four extra days my first year because I was given the job just as school ended, and our program did not have a head coach in the spring of 2011," said Roach. "During (predecessor) Chuck Drury's tenure, we always did spring practice. Over the past few years, with the combination of track, lacrosse, and baseball being popular sports, we would start spring football with only half of the team. So we had to weigh our options."
Is it better to practice with a full squad and hit the ground running in the late summer or take the 10 days in the spring with an incomplete team?
"I chose to have a full staff and team," said Roach. "As an educator, I found it more beneficial to teach and coach with everyone present rather than half the group and then to re-teach it again in August. That's just the teacher in me. Another addition is that the freshman class will be able to start earlier with the varsity as well."
Joel Cookson, director of sports information for the CIAC, said the governing board never did a formal survey for feedback on the spring/fall practice option.
"The closest to anything formal is monitoring the posted information on our website about which teams choose to hold spring practice and which do not," said Cookson. "The informal feedback we've heard is that schools like having the flexibility to decide what works best for their program."
Reach Mark Jaffee at
or on

subset: commoncrawl


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Marshall parent Kim Kosmatka brings her camera to the classrooms and sidelines, capturing life on the Hill.
If you have photos of Marshall events you'd like to share, send them to Kim at the email above.
For more pictures from Ivy Chapel, and many more events like the 4th grade tree planting and action shots from golf, baseball, and tennis, visit the Marshall Hilltoppers Facebook page at facebook.com/marshallhilltoppers!
Check out these great photos from last night's Pops Concert! More photos can be found on the Marshall School Facebook page at facebook.com/MarshallHilltoppers.
Destination Imagination teams performed yesterday for the Middle School students during an assembly.
Taking advantage of the recent warm weather, Upper School students in Paul Schonfeld's class took to the trails to learn about the phyics behind skiing.
A Topper tunnel for our tankers! In only its second year as a varsity program, Marshall is sending its first swim relay to state!
The 400 freestyle quartet of Brent Larson, Charles Kamper, Evan Ruikka, and David Kamper dropped more than six seconds from their preliminary seed time to finish 3rd in the finals with a time of 3:32.81, beating out Mesabi East by 0.64 seconds.
The Kamper brothers are also moving on to state in two individual events; the 200 freestyle where David finished second and Charles third, and the 500 freestyle where Charles was third again and David finished first with set a new section record time.
Rounding out podium finishes in individual events was Ruikka, taking 8th in the 200 Individual Medley and 7th in the 100 Backstroke during the section swim meet at Grand Rapids Saturday.
The Toppers now swim at the U of M Aquatic Center at the state meet March 5-7.
Thanks to Jim Jarocki and Kurt Kamper for the photos!
The boys hockey season came to a close last night, as Marshall fell 4-0 to Hermantown in the 7A title game. The Toppers had an incredible season and we are so proud of them and the school spirit they helped provide! See more photos from last night on the Marshall Facebook page at facebook.com/marshallhilltoppers
Attention all Parents:
Want a quick and easy way to help out at Marshall and show your appreciation to our wonderful faculty and staff? Contribute an item to the monthly luncheon that the Marshall Parent Organization provides to faculty and staff. The next one is coming up this Friday, February 6. You can have your child bring the item with them to school and bring to the Lakeside Room, or drop it off any time in the morning before 10am. There is a simple online sign up that you can use to contribute a main dish, salad or dessert. Click on this link to go to the online sign up. http://vols.pt/j7P7y4 Thanks! If you have any questions, feel free to contact Jeana Marshak and Sue Van Oss; Co-chairs of the Faculty/Staff Lucheons. If you can't help out this month, but would like to be added to an email list that we send out for future luncheons, please send your email address to firstname.lastname@example.com
Choose groups to clone to:


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Sidney Crosby practices, shows Penguins' scary potential
More NHL: Scores | Standings | Odds | Fight-O-Meter | League Leaders | Rumors
Sidney Crosby was back at practice with his Penguins teammates on Friday after getting clearance, and what we saw was scary.
Not that Crosby had any setbacks. All was fine there, though he still won't play Saturday vs. Carolina in the Pens' regular-season finale.
"[Returning] is not really up to me," Crosby said. "I'll just keep talking with the doctors. It's something they have to feel comfortable with the healing. As soon as they say the word, I'll be ready to go."
What was so scary was seeing the power-play unit that the Pens were practicing with. Scary for the rest of the NHL, that is.
Penguins practicing a power-play unit of Crosby, Malkin, Neal, Letang and Iginla.— Seth Rorabaugh (@emptynetters) April 26, 2013
Oh, is that the best you can do, Pittsburgh? It's only four guys who have scored 40 goals or more in one season and arguably the best power-play quarterback in the NHL in Kris Letang.
We knew after the Penguins acquired Jarome Iginla that this was possible, but it's still eye-popping to see on paper. The idea is that it will be just as eye-popping on the ice. Before this group has even played together, the Pens already have the league's second-best power play at a 24-percent conversion rate.
Some will suggest that with that kind of talent, you might as well share the wealth and make a second power-play unit that is a little more balanced. Never mind that they still have Chris Kunitz, Jussi Jokinen, Pascal Dupuis and Brenden Morrow who can make a second unit -- you might not even need it often. With that initial quintet, you imagine they might be kind of effective at scoring.
Word to the wise for Penguins opponents in the playoffs when they are back up and completely healthy; stay out of the box.
As for the regular lines, it appears the Penguins are going to have Malkin centering Kunitz and Neal, a line that worked well last season, while Crosby would likely center Iginla and Dupuis.


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Was looking at JD's ride in Patrick SC, right around thanksgiving, The thought of pulling a horse trailer north through DC baltimore, jersey gives me the heebee jeebies.
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Vertically Integrated Circuits at Fermilab Grzegorz Deptuch, Senior Member, IEEE, Marcel Demarteau, James Hoff, Member, IEEE, Ronald Lipton, Alpana Shenai, Marcel Trimpl, Member, IEEE, Raymond Yarema, Life Member, IEEE, Tom Zimmerman Abstract– The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time. I. INTRODUCTION HE discussion of vertically integrated circuits entails definitions of the subject and the methods used for its physical realization. The first definition refers to a chip in a vertically integrated circuit technology, also commonly known as 3D-IC technology, as a structure composed of two or more layers of active electronic components, integrated both vertically and horizontally [1]. The second definition introduces a set of methods [2], which emergence in the industry, enabled the 3D-IC technology. Those are: advanced and ultra high precision wafer thinning, high aspect (depth/diameter) ratio through silicon vias (TSV) fabrication [3] [4] and oxide or metal compression bonding. The required steps for wafer processing, which were not common so far in the microelectronics industry, include patterning of a back side of wafers, back-side metallization in order to provide connectivity between bonded tiers and establishing of bonding pads on the last tiers in the stack. The connectivity, enabling flow of signals, biases and distribution of power supply between different layers, commonly called tiers, is provided by technological means falling in different categories of advancement and complexity. Large diameter TSVs, located at the pad areas, allow stacking of circuits with communication at the level of input/output (I/O) pads only. Manuscript received November, 13, 2009. G. Deptuch, J. Hoff, A. Shenai, M. Trimpl, R. Yarema, T. Zimmerman are with ASIC Development Group of Electrical Engineering Department of Particle Physics Division at Fermi National Accelerator Laboratory, BP 500, Batavia, IL, 60510, USA, (telephone: +1 630 840 4659, fax: +1 630 840 2950, e-mail: email@example.com, email@example.com, email@example.com, firstname.lastname@example.com, email@example.com ). R. Lipton and M. Demarteau are with Particle Physics Division at Fermi National Accelerator Laboratory, BP 500, Batavia, IL, 60510, USA, ( e-mail: firstname.lastname@example.com, email@example.com ). Fermi National Accelerator Laboratory is operated by Fermi Research Alliance, LLC under contract No. DE-AC02-07CH11359 with the U.S. Department of Energy firstname.lastname@example.com, Small diameter TSVs that vertically interconnect individual blocks located on different strata lead to the most efficient use of the 3D-IC technology, shortening the interconnects, thus minimizing RCs and bringing effectively more transistors into the blocks not causing penalty of the increased net area occupied [5]. The functionality of processing units can be extended. The latter is of extreme importance for number of devices. Especially pixel detectors, targeting high spatial resolution, are in focus. The inter-strata connectivity may extend to individual transistors as TSVs placed on a pitch of a few micrometers are achievable in the most advanced 3D-IC processes. The introduction of TSVs is tackled in diverse ways by different manufacturers. TSVs may be added as the last step after wafer bonding or may be an integral part of the foundry process. The first approach is referred to as via last and the second one as via first. The stacking of tiers can be achieved by bonding directly whole wafers together (wafer-to-wafer), bonding singulated chips to host wafers (chip-to-wafer) or bonding individual dice (chip-to-chip). The wafer-to-wafer bonding is the most common way resulting from the easiness of alignment thus yielding lowest costs. However, high fabrication yield of chips on wafers is assumed as selection of known good dice is unachievable in this method. The wafers are typically fused in one of two ways, i.e. by face-to-face or face-to-back bonding. The face-to-face assembly uses bonding posts on one metal layer that is last in the process and wafers are bonded in such way that front sides of both wafers are brought in contact. The face-to-back bonding requires extraction of bonding posts to the back side of one of the wafers and bonding is achieved by adding next strata in such way that front sides are facing the same direction. The requirements on the quality of the surfaces, to be appropriate for bonding of tiers are generally satisfied with typical foundry criteria for nowadays planarized processes, including chemical-mechanical polishing and metal filled vias. The thinning of wafers leads to the reduction of their thickness from initial several hundreds micrometers to even less than 10 μm. The post-thinning planes must be planar to the same degree as top sides of bonded wafers. The criteria on the surface topography are more strict on bonding based on oxide adhesion only. The topography should typically be not worse than a few hundred of nanometers and the wafer bow should typically not exceed a few tens of micrometers to yield 3D bonding steps successful [6] [7]. A. Steps at Fermilab The exploration of the technologies for 3D circuits began at Fermilab in 2006. Fermilab participated in two Multi-Project-Wafer (MPW) runs (3DM2 and 3DM3) organized by MIT-LL under the DARPA Advanced Microelectronics T
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Technology Development Program. Two versions of a prototype pixel readout chip targeting the specification of the vertex detector at the ILC were submitted. The 3D-IC 3DM2 and 3DM3 MIT-LL runs included stacking of three 6" wafers, fabricated in a 0.18 μm fully depleted Silicon-on-Insulator (FDSOI) process. The 3D method used in the MIT-LL process is via last [8][9][10]. Following the experience with 3D stacking of circuits on SOI wafers, Fermilab gained an access to the via first 3D process based on a commercial 0.13 μm bulk CMOS run at Chartered Semiconductor. The 3D integration is performed by Tezzaron Semiconductor using wafer with TSVs added after completion of the front-end-of-line (FEOL) part of the process [11][12]. The agreement with Tezzaron led Fermilab to the organization of a own MPW run and formation of an international consortium oriented on exploration of 3D-IC technologies for applications in High Energy Physics (HEP) and related fields [13]. The reticule was divided into 12 units of 5.5×6.3 mm2. Fermilab submitted 3 fully functional prototypes on the run that was submitted for fabrication in mid 2009. B. Sketch of new frontiers for detectors with 3D-IC The 3D-IC technology allows not only to increase the complexity of the circuitry that can be fitted on a single die by allowing bigger density of transistors per an unit area resulting for example in a decrease of access time to a cache memory in a computer system [14] but the 3D-IC methods can be perceived as opening of new frontiers for detectors' and imagers' architectures [15],[16]. The introduction of TSVs embedded in the fabrication stage of the wafers, wafer thinning, leading to exposing of buried TSVs and wafer bonding with vertical electrical connections offer unprecedented opportunities for highly segmented detectors with optimized signal and power routing. The area not sensitive to the radiation can virtually be eliminated. Typical peripheral pad-rings in chips not reaping the advantages of the 3D-IC technology, occupy a few hundred of micrometers. They are necessary at least on one side of the die [17][18]. The mechanical mounting of the detectors in the imaging frame may be complex as dead area that is grown by the clearance for wire bonding cannot be eliminated. By applying 3D-IC methods, all connections can be routed to the back-side of the stacked device and redistributed over the available surface. Coming back to the front side, a detector connected to a readout chip by means of one of the 3D-IC bonding techniques yields a structure that is indistinguishable from monolithic configurations. The operation can be referred to as fusion bonding and offers a replacement of typical bump bonds. One of the processes that can be cited in this place is an oxide-to-oxide fusion bonding, called Direct Bond Interconnect (DBI). Fermilab has gained experience with DBI working with Ziptronix [19][20]. The 3D-IC technology is an efficient tool in providing separation of low-noise analog circuitry from digital blocks. This task is crucial in detector readout systems. A designer typically struggles how to floor plan a 2-dimensional chip attempting minimization of cross talks, substrate currents and capacitive couplings. The analog and digital functions can be allocated to separate tiers using 3D stacking. Completing the allocation of analog and digital parts is the methodology for routing of all lines carrying swinging signals. The polluting lines can be moved to tiers that are farther from the detector. The paper discusses these new opportunities using the designs submitted by Fermilab as examples for illustration of the developed claims. Section II reviews the guidelines of the 3D-IC processes used by Fermilab. The details of the designed circuits are presented in Section III with related perspectives and goals that are also outlined. II. 3D-IC PROCESSES USED BY FERMILAB The fabrication of the first 3D chip, called Vertically Integrated Pixel (VIP1) designed at Fermilab, was realized wit the 3D-IC MIT-LL process using the via last approach [21]. The VIP1 chip is a demonstrator serving as proof of the 3D-IC principle for HEP. The implemented functionality targeted the vertex detector at the International Linear Collider (ILC) [22]. The stacked wafers were manufactured in an SOI process, featuring 400 nm-thick buried oxide (BOX) layer. The stacking processing consists of a few steps that are performed in sequence for each tier added. A simplified list of steps can be presented as follows: oxide-to-oxide bonding of planarized surfaces, thinning to the BOX level of the added tier, etching cavities for TSVs in the designated points, filling the obtained cavities with tungsten and preparation of the surface for adding a new tier. The presence of BOX is used as a naturally available limit for etching in the wafer thinning process. Ubiquitous oxides lead to a significant simplification of the 3D stacking process by naturally isolating the inserted TSVs. The TSVs are making contacts to the routing metals by means of specially designed landing posts that serve also as etch stops in creation of the cavities for TSVs. The fabrication of a 3D-IC chip using the via last method and circuits manufactured on CMOS SOI type wafers is shown in Fig. 1. It can be noticed that the first two wafers are bonded face-to-face, and the most top wafer is added using back-to-face bonding. Each tier has 3 routing metal layers and two top tiers have additional back metals layers deposited on BOX after thinning. These back metals are used in establishing connectivity between tiers and are also available for additional signal routing. The total thickness of the structure after completion of the 3D assembly is about 700 μm, while the thickness of the 3 active tiers is only about 22 μm. The actual area required for each TSV is about 5×5 μm2. This number acounts for clearance from neighboring circuitry. A TSV can be a buried via, providing connectivity between internal tiers only or can be a fully stacked pillow, allowing direct connectivity from the top tier to the bottom one. The tests of the VIP1 chip showed correct functional operation of the structure. On the other hand, the fabrication yield was very poor and it was concluded that FDSOI processes are not best suitable for mixed-mode circuitry that includes high precision and low noise parts. The performance of the analog circuitry is strongly compromised by number of
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factors, like variation of temperatures in the structure due to poor heat flow being impeded by the existence of oxides, presence of inter-tier cross-talk paths that may be dominant over interferences between components on the same tier, varying carrier mobility due to the straining of transistor on the BOX, variation of transistors' threshold voltages due to flow of ions eased through oxides, etc. [23][24][25][26]. Fig. 1. Conceptual representation of the fabrication of a 3D-IC chip using the via last method and circuits manufactured on CMOS SOI type wafers. The immediate successor, called VIP2a, of the first prototype was submitted in the FDSOI process to the next 3DM3 run opened by MIT-LL in 2008. The guidelines, aimed at the increase of yield and improvement in the operation of the circuitry were worked out and used in the design of the VIP2a chip. The power and ground routings were strengthened by linking them in a extensive mesh with connections between tiers in each pixel. The rules for trace routing were scaled by a factor equal to 1.2, resulting in wider paths and larger clearances. The process was virtually down-graded to a 0.5 μm feature size in respect to the rules for transistor sizes to decrease off-state leakages and to average structural effects. The delivery of the VIP2a chip is expected in early 2010. More recent design work at Fermilab has focused on a 3D-IC process using bulk CMOS wafers with Cu-Cu thermo-compression bond interface. The processing of a commercial full CMOS 0.13 μm is supplemented by insertion of TSVs after completion of FEOL. The reactive ion etching (RIE) technique, as a first function meeting the installment of shallow trench isolations (STI), is applied for incising cavities for TSVs that are filleed with tungsten afterwards. The wafers are fabricated by Chartered Semiconductor and the stacking, as well as all processing steps required beforehand, is done by Tezzaron. Although as many as five stacked layers have been demonstrated by Tezzaron, the current Fermilab designs only use two layers and the face-to-face stacking method. The sketch how a 3D-IC chip using the Tezzaron via first method is obtained is shown in Fig. 2. The TSVs can be inserted either in one wafer only, as it is indicated in Fig. 2a, or in both wafer as it is followed in Fig. 2b. The presence of TSVs in both wafers is mentioned later in the article as fulfilling a crucial role for bonding of a detector to the readout chip on one side and protract all signals to the opposite side of the structure. The bonding interface, composed of uncovered metal bond-points, is highlighted in Fig. 2a. The bond-points are small 2 μm hexagons instantiated on the continuous hexagonal grid at a pitch equal to 4 μm. The bond-points are on the last metal layer. The sketch in Fig. 2b shows that one wafer, that will be called 'top tier' remains thick and another one, which will be called 'bottom tier', is thinned down to expose the tips of TSVs after bonding. Tezzaron delivers 3D structures in such arrangements of top and bottom wafers. It is worth mentioning, that the top tier can be in principle thinned down too. The whole structure may require interim attachment to a handle wafer to achieve this thinning goal. The characteristics of the CMOS process used are: large, about 26×31 mm2, reticule, single poly layer, 6 Cu metal layers, redistribution metal layer for pads, deep nwell, single mask metal-insulator-metal capacitors, low power 1.5V transistors (standard threshold voltage (SVT), low threshold voltage (LVT, zero threshold voltage (ZVT), IO 3.3V MOSFETs, high resistivity poly resistors. TSVs, intrinsic to the wafer processing, are 1.3 μm in diameter, 6 μm deep and 3.8 μm minimum spacing is required. Fig. 2. Conceptual representation of the fabrication of a 3D-IC chip using the via first method and circuits manufactured on CMOS bulk type wafers, bonding interface a), bonding, thinning and I/O pads b). To limit costs of the run, by using eventually only one set of masks, the reticule was divided symmetrically into two halves. So that the reticule hosts top-tier chips and bottom-tier a)b)
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chips on its left and right side, respectively. The vertical symmetry about the center of the frame guaranteed matching of circuits for 3D assembly after flipping one wafer over another. The view of the whole frame fabricated is shown in Fig. 3. The Fermilab sub-reticules are H-H*, I-I* and J-J*, where the H-H* sub-reticule is occupied by the VICTR chip (Vertically Integrated CMS Tracker Readout), the I-I* sub-reticule is occupied the VIP2b chip (Vertically Integrated Pixel ver. 2b) and the J-J* sub-reticule is occupied by the VIPIC chip (Vertically Integrated Photon Imaging Chip). Simple, planar, silicon detectors are under preparation for use with the 3D-chips submitted on the Tezzaron run. The detectors are in fabrication at the Instrumentation Division at Brookhaven National Laboratory (BNL). The design follows the rules for the DBI wafer bonding process. The DBI process begins with very small metal contacts imbedded in a smooth oxide surface. The wafer bond is achieved immediately after the two oxide surfaces are brought together. After the desired strength of the oxide bond is established, the heating is applied to expand the metal contacts to fuse compression bonds. The sub 10 μm bonding pitches are achievable, while the upper limit on the bonding metal density is around 10%. The DBI process is not limited to the wafer-to-wafer type bonding. Indeed, the assembly of the chips from the Tezzaron run to the detector will be done on the chip-to-wafer basis. Fig. 3. View of the whole frame with Fermilab chips (H-H*, I-I*, J-J*). III. 3D-IC DESIGNS BY FERMILAB A. VIP2b The VIP2b is a time stamping pixel readout chip for the vertex detector at the ILC. The chip is a re-design of the earlier VIP1/VIP2a device from the 3-tier designs submitted to the MIT-LL process to a two-tier circuit. The new circuit is an array of 192×192 pixels laid out in a square pitch of 24 μm2. It has 8 bit digital time stamp allowing time bins equal to Δt=3.9 μs in the ILC time operation regime with readout between ILC bunch trains. The chip implements sparsification based on the token passing scheme that remains unchanged from the earlier prototypes. The front-end is a single stage integrating charge signal amplifier with discriminator and with 2 sample/hold (S/H) cells for analog signal output capability with in a correlated double sampling (CDS) mode. The front-end implements a polarity switch allowing accepting collecting of e- or h+. Each pixel features a separate test input allowing injection of test charges through a series capacitor. The addresses of hit pixels are output on a serial bus in parallel with the analog information on signal amplitudes that are available on the analog outputs. The detector for the VIP2b chip has diode implant on the 24 μm pitch. The conceptual view of the mounting of a single VIP2b chip onto a detector is shown in Fig. 4. The detector wafers, fabricated at BNL, contain sensors for all Fermilab 3D-IC chips. The whole sensor wafers undergo necessary processing finished up with metal bonding posts. The image processing is performed on the wafers with chips. The chips with prepared bonding posts are singulated out from the 3D wafer. The individual chips are mounted on the corresponding sensors. The alignment targets integrated on both bonded components can be seen in infra-red light through the whole structure and allow precise alignment. All pads for power supplies, biases and analog and digital I/Os are routed to the pad-ring around the matrix of pixels on the VIP2b chip. The DBI bonding includes transferring of the VIP2b pads onto the sensor. The new pads are recreated on the sensor where the access is not obscured by the VIP2b chip and are reachable with a wedge or ball bonding head. There is a fan-out connection routed on the sensor. The traces are shielded from the sensor by a metal plane between the bonding positions and the pads on the sensor. Fig. 4. Assembly of the VIP2b chip on the dedicated detector with the fan-out connection and pads for wire bonding on the detector. The VIP2b chip and its assembly with the detector qualifies as the most moderate challenge in transition from conventional detector architectures to those that might be allowed exploiting the 3D-IC technologies that are addressed with the devices described in this paper.
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B. VICTR The next 3D chip, VICTR, embodies an initial step toward developing an intelligent tracker capable participating in production of Level 1 trigger at the upgrade of the CMS experiment at SLHC. It is expected that the tracker is able to identify hits associated with transversal momentum pt>2 GeV for data transfer off the tracker and to participate in building tracks and identification those with pt>15-25 GeV. The need for momentum cut automatically asks for hisgh spatial resolution the rφ plane however, the tracker should provide good of about 1 mm resolution in the 'z' coordinate [27]. The pt cut of the desired threshold can be achieved by processing hit coincidences from two layers of strips sensors. The sensors must be separated by a distance allowing enough track curvature that can be detected by observing offsets of hit positions from two layers providing the pitch of strips is tight enough. The prototype system for the intelligent tracker is sketched in Fig. 5. The sensors for the VICTR chip are fabricated on the BNL sensor run too. There are two sensors used in the prototype as different strip arrangements are required. The top sensor, called φ strips, has 64 strips laid out on the pitch of 80 μm and its active part is 5 mm long. The bottom sensor, called 'z' strips, is a matrix of 64×5 short strips of 80 μm×1 mm. The VICTR chip is designed in such way that charge signals are transferred to the VICTR chip from two directions normal to the surface, i.e. form the bottom and top sensor. The required, for the momentum resolution, spacing between the sensors is achieved by insertion of a 1 mm thick interposer between the top sensor and the VICTR chip. Fig. 5. Block diagram of the prototype unit implementing L1 trigger in the tracker upgrade of the CMS experiment at SLHC using the VICTR chip. The candidate material for the interposer is silicon and charge signals are transferred through deep TSVs to the VICTR chip. The studies of the interposer are underway. The top tier of the VICTR chip looks at the φ strips, while the bottom one looks at the z strips. The coincidences are detected between each strip on the φ layer and each group of 5 short strips on the z layer. The processing electronics uses the FEI4 front-end design for the pixel detectors at the ATLAS experiment at LHC [28]. The design was graciously shared with Fermilab by the ATLAS pixel community. The segmentation of the z layer provides the necessary spatial resolution but it is not used in the processing of coincidences. The VICTR chip processes signals with the typical LHC cadence of 25 ns. It provides serial readout of all top and bottom strips along with coincidence information. In the final circuit, the simple coincidence, circuit that is currently based on the AND logic, will take into account spread of signals onto the neighboring strips for improved spatial resolution. The construction of the prototype unit for the implementation of the L1 trigger in the tracker upgrade of the CMS experiment at SLHC extends significantly exploitation of the 3D-IC methods comparing with the VIP2b chip. The VICTR chip must be thinned to about 24 μm so that the connections on the top and bottom of the chip could be used. Typically, silicon wafers cannot be handled if such aggressive thinning is applied. Thus, a handle wafer must be used in the fabrication of the final structure of the trigger module. The process starts with deposition of back metal, forming bases for the bump bonding pads on the top tier that is thinned by Tezzaron at the very first step. Then, the whole wafer is bonded to a handle dummy wafer. The bump bonding pads are buried between the wafer with readout chips and the handle wafer. The bond to the handle wafer is strong enough to thin the opposite side to expose TSV that will be contacted to the bottom sensor. The preparation of the bonding posts is performed on an exposed thinned surface and the 3D chips are singulated. The DBI mounting of each VICTR chip of the bottom sensors is done in the next step. The sensors wafer with VICTR chip is diced. The final processing step consists of dicing assemblies composed of the bottom sensors and the VICTR chip that are ready for connection using bump bonding to the top sensor. C. VIPIC The last 3D chip, VIPIC, was designed for X-ray photon correlation spectroscopy (XPCS) experiments on light sources. The XPCS is a technique that is used for studying of the dynamics in various processes on a nanometer scale lengths [29]. In these analyses, so called speckle patterns are generated. The photons are registered at different space positions with their arrival times. The results of the analysis are time correlation functions that are calculated for different sampling time intervals at different position. The detector must allow time resolved data acquisition. The targeted readout is continuous, registering of all data from the observed process. The time resolution set for the design was Δt=10 μs. The VIPIC chip is a prototype matrix of 64×64 pixels. The pixel size is 80×80 μm2. The fast data readout is achieved by using the data sparsification as the primary readout mode. The imaging mode is implemented as a second readout mode. Each pixel is able to count individual radiation events in both modes; however the imaging mode leads to reading out all pixels without sending out their addresses to the data acquisition system. The VIPIC chip functions dead-timelessly in both modes of operation. The main components of the pixel are: the charge sensitive amplifier followed by the 2-stage
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shaping filer and the single threshold level discriminator; there are two DACs for tuning the decay time constant of the amplifier response and the threshold of the discriminator; there is the test charge injection circuitry; the hit holder circuitry; and there are two alternatively used 5-bit long event counters per pixel. The hit holder acquires new hits and feeds the hits to the sparsification circuitry in te time resolved manner. The hit holder integrates flexibility of managing acquisition of hits. It can be permanently set to ignore any hits or to always contain hit. It operates in a pipe-line. The toggling between pipe-line phases occurs with rising edges of the main time stamping clock. With a new rising edge of the clock the hit information is handed off from the cell waiting for hits to the cell connected to the readout. The time bins are defined by the time stamping clock. The period of the clock must be selected aiming at readout of all data within it each cycle. The analog part of the pixel was designed in collaboration with UST-AGH, Krakow, Poland. The chip is divided in 16 group of 256 pixels read out in parallel through separate serial ports running on the LVDS standard. The data sparsification process is run simultaneously in each group. The block diagram of the VIPIC chip showing subdivision into the readout groups is presented in Fig. 6. The sparsification circuitry is common for each group of 256 pixels. The sparsification circuitry is a modified version of an old idea proposed for the MEPHISTO prototype [30]. It is primarily a multi-input logic OR gate integrated with priority encoder. The encoder selects pixels for readout and generates addresses of hit pixels automatically in the binary code. The layout of the sparsification circuit is distributed into all pixels. Fig. 6. Block diagram of the VIPIC chip. The readout of the VIPIC chip is binary. Each hit is represented by a 16 bit-long word, where 3 bits are the start sign, 5 consecutive bits are the content of the in-pixel counter and the remaining 8 bits are the pixel address in the sparsification mode. The pixel addresses are not required in the imaging mode, thus the output word is shorter. The maximum number of hits that can be sent out within a 10 μs time period is 60 from one group of 256 pixels. This estimation assumes a moderate frequency of 100 MHz for the serial clock and occupation of separate pixels by 60 hits, i.e. each pixel is hit only once. The imaging mode allows the rate of 50×103 frame/s. The length of the counter that is 5 bits guarantees dead-timeless and lossless operation in the imaging mode. This confidence stems from the fact that the time required to send out all data from all pixels in the group is shorter than the time to fill the working counter by new hits at the serializer operating at 100 MHz. The maximum speed at counting can occu is limited by the time at which the front-end returns to the baseline, otherwise signa; pile-ups are present. The VIPIC main features are summarized in Table I TABLE I. MAIN FEATURES OF THE VIPIC CHIP Feature X-ray detection (8 keV) with Si pixel detector XPCS application 64×64 pixels, pixel area: 80×80 μm2 5120×5120 μm2 separate analog and digital tiers analog=280 transistors, digital=1400 transistors chip area 6.3×5.5 mm2 (6.3×5.6 mm2) larger dicing for DBI single threshold for discriminator, trim DAC/pixel for offset corrections 3 bits CSA feedback, 7 bits discriminator threshold permanent set and permanent disable bit per pixel test charge injection circuitry single ended or differential configuration of the front-end power consumption 25 μW/analog pixel CSA: noise ENC < 150 e-, τp < 250 ns, gain 115 mV / 8 keV readout modes: - sparsified, binary readout (sparsified time slicing mode), - imaging binary readout mode (5 bit signal depth) dead-timeless and trigger-less operation in both readout modes sparsification: priority encoder based sparsification circuitry 16 parallel serial LVDS output lines (16 groups of 4×64 pixels) two 5 bit counters per pixel for recording multiple hits per time slice (useable in the imaging mode) frame readout at 100 MHz serial readout clock - 160 ns / hit pixel in sparsified time slicing mode (up to 60 hit pixels / 10 μs) - 50×103 frame/s in imaging mode (5 bit counting) The design of the VIPIC chip uses the capacities of the3D-IC technology in the most complete way among all Fermilab's designs. Achieved the first step is full separation of analog and digital circuits. The dividing line runs along the interface between tiers. The analog part of the pixel is connected to the digital part by 27 connections passing through the bonding interface for signals. Additional terminals, consisting of multiple bond-points, are used to transfer power supplies and grounds. The 27 signal connections include 10 pairs of complementary inputs of DACs, routed from the shadow latches of the configuration shift registers implemented on the digital level, 1 complementary global strobe signal for injection of test charges into the selected pixel, 1 complementary signal for selecting pixel for charge injection and one complementary signal for toggling between the single-ended and differential administration of the reference Comments Cinj=1.7 fF Cfeed=8fF
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level in a shaping filter. The last signal is an output of the discriminator feeding the hit holder circuitry located on the digital layer. Achieved the second step is such preparation of the design that all pins of the chip are available on both side of the die. Such redundant configuration is a step bringing a detector structure without any connectivity on the sensor side into practical realization. Connections for diosed and I/Os on the same side are irrevocably introducing a significant dead area. Protraction of all signals and power supplies with no exception on the back of the chip and preserving the connectivity in a classical pad-ring on the front side is an opportunity of performing comparative testing. The VIPIC chip is prepared to test the mounting to the detector in the manner discussed for the VIPI2b chip. The front-side view of the chip, exposing bonding posts designed to connect front-ends to the diodes, and the signal fan-out traces routed on the detector, is shown in Fig. 7. Fig. 7. Front-side view of the chip with bonding posts to the diodes and the signal fan-out routed on the detector. The exploration of the mounting of the VIPIC in the manner not requiring any other connections on the side facing the detector than contacts to the diodes only is possible thank to the redistribution of all pins on the back side of the chip. The corresponding view of the back-side pins is shown in Fig. 8. A better distribution of the power supplies and grounds, that can be measured in the pursuit of the lowest impedance, is achieved by multiple, intertwined connection points spread over the whole area of the matrix of pixels. The distance between pins is 450 μm on the back side. Low pitch bump bonding, like Sn bump bonding, or gold stud bonding are proposed for mounting of the VIPIC chip on the dedicated host board. The embedding of TSVs in a single layer detector readout integrated circuit or more generally on both sides of the multi-layer structure allows venturing announcement of the feasibility of a full 4-side buttable pixel detector tile. The cross-section of the targeted detector architecture is shown in Fig. 9. The designs carried out at Fermilab gradually lead to the achievement of this objective. The VIPIC chip, being the most advanced prototype, is actually a demonstration of the possibility of achieving this technological dimension. Fig. 8. Back-side view of the chip with bump-bonding pads distributed over the whole surface of the chip; the polygon shadowed shapes mark pins holding the same potential and the same use. Fig. 9. Cross-section of a 4-side buttable pixel detector tile. The detector can be fabricated as a homogeneous array of diodes using a whole area available on a wafer. Individual readout chips can be tailed on the detector wafer by fusion bonding. The low pitch connectivity on the back of the chips can be connected to the hosting substrate. The system can be built on an alumina or silicon interposer board, classical printed circuit board, etc. D. Sensors and DBI bonding The chips submitted on the Tezzaron/Chartered run require radiation sensors of characteristics that make them able to use fusion bonding technology. The fabrication of the dedicated sensors is underway with BNL. The sensors are p-on-n. The thickness and the resistivity of the wafer are 500 μm and 4 kΩcm, respectively. The pitch of the pixel devices is 24 μm and 80 μm for the VIP2 and VIPIC chip, respectively. The sensors for the VICTR chip are short strips laid out in the pitch of 80 μm. The cross-section of a single fusion bonding node of a 3D readout Tezzaron/Chartered 3D-IC run and the detector is shown in chip fabricated on the
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Fig. 10. The bonding process is the Ziptronix's DBI technology. Seen no access to metal filled vias and planarization in the fabrication process of the detector, the thicknesses of the deposited layer must have been chosen carefully in order to provide surface topography sufficiently small for the DBI process . The thickness of oxide is 2000 Å, the thickness of sensor metal is 2000 Å and the thickness of oxide II is 2000 Å on the detector. The seed metal, DBI post and DBI oxide are deposited in the processing by Ziptronix. The size of the DBI post is 6 μm. Fig. 10. Cross section of a single fusion bonding node of a 3D readout chip a detector using the Ziptronix's DBI technology. IV. CONCLUSIONS Fermilab has made first steps in introduction of the 3D-IC technology to the applications of particle tracking and imaging of ionizing radiation in HEP and domains that are closely linked by the same needs for detectors. Fermilab has had an opportunity to explore freshly emerging technologies, i.e. via last 0.18 μm FDSOI CMOS process available at MIT-LL, via first 0.13 μm bulk CMOS Tezzaron/Chartered and the DBI fusion bonding process available at Ziptronix. The early Fermilab's experience was translated into the International Consortium of institutions that have come together to develop 3D integrated circuits for physics applications. The access to diverse technological approaches through the very early stages of the work allowed gaining valuable knowledge on usefulness of technological approaches in achieving reliable designs. The identification of the methods applied in the 3D-IC technology that, even when used alone without vertical stacking of the wafers with electronics, can solve many problems mounted up in the detector engineering, was another result. It can be summarized that 3D-IC offers new approaches to old problems in the process available at detector development. The five circuits designed by Fermilab target the wide spectrum of applications; four chips are still 'in fab'. The first earnest results are expected very soon. The paper attempted a review of the opportunities that are brought with the 3D-IC methods. The designs of chips, done at Fermilab, are employed as an illustration of the gradual progress and to expose the potential residing in the new tools. The feasibility of a 4-side buttable device, obtained by dragging and distributing of all connections on the side of the structure opposite to that bonded to the detector, has been demonstrated on the actual designs. One may venture to say that another advantage of the 3D-IC technology is to slow down the pace at which designs of readout chips for radiation detectors need to reach out nano-scale processes, where challenges for example related to matching of active components need to be faced [31]. It is known that higher densities of electronic circuitry per unit area is needed to fit the functionalities requested in nowadays systems, but nano-scale processes exhibit extreme challenges in low-noise, precise analog design. Further reflection on the 3D-IC technology is the use of heterogeneous wafers, i.e. wafers from different foundries or from different process families. This view may lead to the optimization of each tier in the 3D stack for the specific function, like detector, analog processing tier, digital communication tier, etc. [32]. The mixing of heterogeneous wafers because of technological or economical reasons may be unreachable directly at the foundry. The bonding of heterogeneous wafers can however can be achieved by using methods as DBI, offered by Ziptrornix, or similar approaches available elsewhere. An example of such heterogeneous wafer stacking is attachment of the detectors and it was presented in this paper too. ACKNOWLEDGMENT The authors would like to acknowledge Dr. Craig Keist and Dr. Chenson Chen, from MIT Lincoln Laboratory for the assistance and opening access to the 3D runs using the via last and FDSOI process. The VIP1 and VIP2a chips were designed and fabricated in MIT Lincoln Laboratory's 3D-IC process, funded under Microelectronics Technology Development Program managed by Dr. Daniel Radacks. Special thanks go to Brian Tyrrell, for fruitful discussions and for revealing details of the 3D-IC integration and FDSOI process. We would like to acknowledge Dr. Robert Patti from Tezzaron Semiconductor for guiding us through the 3D-IC technology based on the via first Tezzaron/Chartered approach and Dr. Paul Enquist from Ziptronix for the revocation of seam secret steps of DBI. We would like to thank Dr. Julien Fleury, Dr. Abderrezak Mekkaoui from Lawrence Berkeley National Laboratory and Dr. Jean-Claude Clemens from Centre de Physique des Particules de Marseille for discussions and primarily for sharing with us the FEI4 design. Expression of gratitude go to our close collaborators Prof. Pawel Grybos, Dr. Robert Szczygiel, Maciej Kachel and Piotr Kmon from AGH the DARPA Advanced
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University of Science and Technology for being with us on the boat of the VIPIC chip design. Last but not least, we would like to thank Dr. Peter Siddons and Dr. Gabriela Carini from Brookhaven National Laboratory for giving us inspiration for the design ideas and collaborating on the fabrication of the dedicated detectors. REFERENCES [1] P.Garrou, C.Bower, P.Ramm, "Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits", Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim, 2008 [2] G.Poupon, M.Scannell, L.Di Cioccio, D.Henry, P.Leduc, L.Clavelier, et al., "3D Integration: a technological toolbox", 3r International Microsystems, Packaging, Assembly Conference, IMPACT 2008, 22-24 Oct. 2008, pp. 375-378 [3] M.Puech, J.M.Thevenoud, J.M.Gruffat, N.Launay, N.Arnal, P.Godinat, "Fabrication of 3D Packaging TSV using DRIE", in DTIP of MEMS & NOEMS, DTIP 2008, April 9-11, 2008 [4] C.Laviron, B.Dunne, V.Lapras, P.Galbiati, D.Henry, F.Toia, et al., "Via First Approach Optimisation for Through Silicon Via Applications", in 59th Electronic Components and Technology Conference, ECTC 2009, 26-29 May, 2009, pp. 14-19 [5] W.Haensch, "Why should we do 3D integration", in Design Automation Conference, DAC 2008, 8-13 June 2008, pp. 674-675 [6] Robert Patti, private communication [7] Paul Enquist, private communication [8] C.K.Chen, N.Checka, B.M.Tyrrell, C.L.Chen, P.W.Wyatt, D.R.W.Yost, J.M.Knecht, J.T.Kedzierski, C.L.Keast, "Characterization of a three-dimensional SOI integrated-circuit technology", IEEE International SOI Conference, 2008, 6-9 Oct. 2008, pp. 109 – 110 [9] J.A.Burns, B.F.Aull, C.K.Chen, J.M.Knecht, V.Suntharalingam, K.Warner, P.W.Wyatt, D.-R,W.Yost, "A Wafer-Scale 3-D Circuit Integration Technology", Electron Devices, IEEE Transactions on Vol. 53, Issue 10, Oct. 2006 pp. 2507 - 2516 [10] MITLL Low-Power FDSOI CMOS Process Design Guide, Revision 2006:7, Oct. 2006, Comprehensive Design Guide, Advanced Silicon Technology Group, MIT Lincoln Laboratory, Boston, MA, USA [11] R.S.Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", Proceedings of the IEEE, Vol. 94, Issue 6, June 2006, pp. 1214-1224 [12] R.S.Patti, "3D Scaling to Production", Conference on 3D Architecture for Semiconductor Integration and Packaging, San Francisco, CA, 31 Oct. - 2 Nov. 2006 [13] 3dic.fnal.gov [14] A.Zeng, J.Lu, K.Rose, R.J.Gutman, "First-order performance prediction of cache memory with wafer-level 3D Integration", IEEE Design & Test of Computers, Vol. 22, Issue 6, Nov. – Dec. 2005, pp. 548-555 [15] Y.Kaiho, Y.Ohara, H.Takeshita, K.Kiyoyama, K.-W.Lee, T.Tanaka, "3D Integration Technology for 3Dstacked Retinal Chip", ", in IEEE International Conference on 3D System Integration, 3DIC 2009, 28-30 Sept., 2009, pp. 1-4 [16] R.Yarema, G.Deptuch, J.Hoff, A.Shenai, M.Trimpl, T.Zimmerman, et al., "3D design activities at Fermilab – opportunities for physics", Nucl. Instr. and Methods in doi:10.1016/j.nima.2009.09.045 [17] X.Llopart, M.Campbell, R.Dinapoli, D.San Segundo, E.Pernigotti, "Medipix2: A 64-k pixel readout chip with 55 μm square elements working in single photon counting mode", IEEE Transactions Nucl. Sci., Vol. 49, No. 5, Oct. 2002, pp. 2279 – 2283 [18] P.Kraft, A.Bergamschi, Ch.Bronnimann, R.Dinapoli, E.F.Eikenberry, H.Graafsma, et al. "Characterization and calibration of PILATUS detectors", IEEE Transactions on Nuclear Science, Vol. 56, No. 3, June 2009, pp. 758-764 [19] Q.-Y.Tong, "Room temperature metal direct bonding", Appl. Phys. Lett. 89, 182101, 2006 [20] Q.-Y.Tong, G.Fountain, P.Enquist, "Room temperature SiO2/SiO2 covalent bonding", Appl. Phys. Lett. 89, 042110, 2006 [21] G.Deptuch, D.Christian, J.Hoff, R.Lipton, A.Shenai, M.Trimpl, R.Yarema, T.Zimmerman, "A vertically integrated pixel readout device & Circuits Technology Chang-Lee Chen, C.L.Keast, Physics Research A, 2009, for the Vertex Detector at the International Linear Collider", FERMILAB-PUB-08-564, Dec. 2008 [22] J.E.Brau, M.Breidenbach, C.Baltay, R.E.Frey, D.M.Strom, "Silicon detectors at the ILC", Nucl. Instr. and Methods in Physics Research A, 579, 2007, pp. 567-571 [23] M.Connell , M.Grady, P.Oldiges, D.Onsongo, M.Passaro, W.Rausch, P.Ronsheim, D.Siljenberg, "Impact of Mobile Charge on Matching Sensitivity in SOI Analog Circuits", 2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2007, ASMC 2007, IEEE/SEMI, Stresa, Italy, 11-12 June 2007, pp. 6-10 [24] Ying-Che Tseng; W.M.Huang, D.J.Monk, P.Welch, J.M.Ford, J.C.Woo, "AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's", Electron Devices, IEEE Transactions on, Vol.: 46, Issue. 8, Aug 1999, pp. 1685-1692 [25] B.M.Tenbroek. M.S.L.Lee, W.Redman-White, C.F.Edwards, M.J.Uren, R.J.T.Bunyan, "Drain Current Mismatch in SOI Current Mirrors and D/A Converters Due to Localised Internal and Coupled Heating", 23rd European Solid-State Circuits Conference, 1997, ESSCIRC '97, 16-18 Sept. 1997, pp. 276 – 279 [26] W.Redman-White, B.M.Tenbroek, M.S.L.Lee, C.F. Edwards, M.J.Uren, R.J.T.Bunyan, "Analogue design issues for SOI CMOS", IEEE International SOI Conference, 1996, Sanibel Island, FL, USA, 30 Sept. – 3 Oct. 1996, pp. 6-8 [27] R.Lipton, et al., "Proposal for phase II tracker and trigger planes based on vertically integrated http://cmsdoc.cern.ch/cms/electronics/html/elec_web/slhusg/proposals/proposal_list.html [28] R.Beccherle, "Front-end electronics for the B-layer replacement or SLHC in ATLAS", in Proceedings of Science, PoS (Vertex 2008), 045 [29] G.Grubel, A.Madsen, A.Robert, Spectroscopy (XPCS)" in R.Borsali, R.Pecora, (Eds.), "Soft Matter Characterization", Springer Netherlands, 2008, pp. 953-995 [30] P.Fischer, "First implementation of the Mephisto binary readout architecture for strip detectors", Nucl. Instr. and Methods in Physics Research A, 461, 2001, pp. 499-504 [31] M.Vertregt, "The analog challenge of nanometer CMOS", International Electron Devices Meeting, 2006, IEDM '06, San Francisco, CA, USA, 11-13 Dec. 2006, pp. 1-8 [32] C.L.Chen, D.-R.Yost, J.M.Knecht, L.J.Mahoney, et al., "Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout Circuits", IEEE International Conference on 3D System Integration, 3DIC 2009, 28-30 Sept. 2009, pp. 1-4 electronics", 2009, "X-Ray Photon Correlation D.C.Chapman, D.C.Oakley,


text: The All-American Gift Guide Say hooray for the red, white, and blue. November 29, 2013 12:15 PM | by W magazine Next Up - Begins in 5 The Modernist Gift Guide Start Slideshow 1/23Justin Timberlake plays president in October 2011's "Yes They Can!" shot by Michael Thompson and styled by Edward Enninful. 2/23Valentino jacket, $3,550. 3/23See by Chloé Paint a Scent eau de parfum, $35, macys.com. 4/23Rena Lange top, $495, Neiman Marcus. 5/237 For All Mankind shorts, $159, 7forallmankind.com. 6/23Fendi L'Acquarossa eau de parfum, $98, saks.com. 7/238/23Henry Handwork towels, $30 each, frenchquarterlinens.com. 9/23Jonathan Adler backgammon set, $395, jonathanadler.com. 10/23Alexander Olch neckties, $160 each, olch.com. 11/23Soludos shoes, $36, shopbop.com. 12/23Mulberry wrap, $670. 13/23Myriam Schaefer bag, $5,770, Bergdorf Goodman. 14/2315/23Michele stainless steel and diamond watch, $1,895, michele.com. 16/23Ceramica ND Dolfi bowl, $295, Bergdorf Goodman. 17/23Smythson iPad sleeve and iPad mini sleeve, $330 each, smythson.com. 18/23Lisa Marie Fernandez maillot, $475, net-a-porter.com. 19/23SK-II Swarovski Elements Facial Treatment Essence, $195, saks.com. 20/23Carelle gold and diamond rings, $1,140 each, and (middle) gold and tanzanite ring, $775, carelle.com. 21/2322/23Alice + Olivia by Stacey Bendet skirt, $253, aliceandolivia.com. 23/23 Related Stories Around The Web Previous The Modernist Gift Guide Next Who's Who of Alexander Wang's "Squad" Follow Us: Most popularPerfect 10The French Girl LookCelebritiesSelena Gomez: Liked by ManyCelebritiesSelena Gomez: Hotter Than EverFashionBodysuits and Ferraris: How to Do Valentine's Day Like an Italian Lingerie DesignerFashionEvery Time Beyoncé Slayed in Givenchy Follow us on Facebook Please don't show this again. Close


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Ask the Experts
Rash and thrash with NevilastMy sister just started taking Nevilast for a week now. Prior to this she was treated for toxoplasmosis. Now she is rashes all over her face, hands and legs. she is also developing thrash (white pumps) in her month. Left leg is some how swollen. ...
Response from Keith Henry, M.D.
University of Minnesota, School of Medicine...such severe rashes are lower in women who have CD4 count thrush (mouth washes or lozenges or sometimes a pill). As her CD4 count increases then chances for thrush decrease over... Read more »
Please post!! To All who r worried!! Thank DR BOBDr. Bob I wanted to say thank you for being there for the people you are afflicted and who are not.... Read more »
Contact lenses????OK this may sound silly but I am a little concerned. You provide a great service here and I am... Read more »
Fluconazole (Diflucan)...your body gets swollen. In rare cases, fluconazole can cause a serious reaction (Stevens-Johnson syndrome) that shows up as a skin rash. Pregnant women or women who are breastfeeding should not take fluconazole. How Does It React With Other... Read more »
Candidiasis (Thrush)... What Is Thrush? Can It Be Prevented? How Is It Treated? Natural Therapies The Bottom Line What Is Thrush? Candidiasis is a common Read more »
What Are the Symptoms of HIV and AIDS?...mind is a powerful thing. Your mind can make it seem as if your tongue is covered in the white spots that sometimes indicate thrush , when in fact it's perfectly pink. Your mind can also make you feel tired and lethargic even though you're... Read more »
Women and HIV...men. On average, women weigh less than men and might have higher blood levels of drugs. Women are more likely than men to get skin rashes and liver problems, and to experience body shape changes (lipodystrophy, see Fact Sheet 553 ). Bone loss... Read more »
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Skin Rash
Posted by DJones, 8 Replies...I have been on Atripla since January. I am also on Fluconazole and Acyclovir. In the last month I have developed a skin rash where the sun seems to hit my skin on my back of my neck where my hair line ends and lower arms. I thought it was... Read more »
Itchy skin rash from sun and meds?
Posted by DJones, 4 Replies...I have been on Fluconazole, Acyclovir and Atripla for about 6 months. I noticed problems with a terrible itchy skin rash when I was in the sun when the summer began. I have stayed out of the sun or put sun block on until last Saturday I was at a Read more »
unprotected oral scare
Posted by Breezy, 2 Replies...allergy thing, right? And one week would have been too soon for ARS too. But... At the end of week five I also have oral thrush and hives/rash on my back, chest, and around my face. Plus I'm still really fatigued all the time. I had taken... Read more »
Thrush symptoms?
Posted by Anonymous, 1 Reply...immune system? The only other syptom I think I might have is that my tongue is a little white tinted. Could this be like minor thrush? or is thrush pretty easily recognizable when someone has it? Are there varying intesities of thrush? And are... Read more »


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Repair crack D2h body, Suggestions Please?
Started Jul 7, 2013 | Questions thread
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Veteran Member • Posts: 3,464 • Gear list
Gpruitt54 wrote:
user_name wrote:
It's magnesium.
Since the cost of replacing the part is more than the camera's worth, I would just get some JB Weld or better yet, JB Quick and fill the crack and clamp it together.
Thanks, the camera is working like a champ, The D2h is an excellent piece of engineering. I almost don't even care about the crack, it is not an issue at all to the functioning of the camera. Though I am somewhat concerned about moisture and/or dust getting in there.
So, where do I buy this JB Weld or JB Quick product?
I've seen it at Lowe's, Ace Hardware, Home Depot, and the True Value hardware stores. Probably at the big auto parts stores too.
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1 Passenger Stand-upOnce the model of choice for personal watercraft enthusiasts, 1 passenger stand-up PWCs are currently only made by two manufacturers Kawasaki and Yamaha. These crafts feature smaller 2-stroke engines and lightweight hulls. They may not have the power of the larger runabouts, but stand-up crafts accelerate in a hurry and are much more agile. Ideal for short-course racing, stand-up crafts are also used in freestyle competitions where they put on sensational aerial displays.
View All 1 Passenger Stand-up ReviewsLatest 1 Passenger Stand-up Reviews
2015 Yamaha SuperJet Review
The last of the stand-up PWC lives onBelieve it or not, Yamaha still produces the once-popular SuperJet. The craft comes with a catch: its for closed-course racing use only, meaning you cant register it and ride it on your local waterway.
2014 Yamaha Super Jet Review
The lone remaining stand-up craft rides againYamahas Super Jet, the lone remaining stand-up in the industry, handles like a champ and has got reliable power with plenty of upgrade potential.
2013 Yamaha Super Jet Review
When it comes to buying a standup, racers have all the funLook at the Yamaha WaveRunner product lineup for 2013 and youll see a familiar craft down toward the bottom of the list the Super Jet. But wait, didnt all stand-ups go out of production in 2012?
View All 1 Passenger Stand-up ReviewsLatest 1 Passenger Stand-up Reviews
Yamaha 2013 WaveRunner Lineup PreviewA very familiar WaveRunner family returns for 2013
2012 Yamaha SuperJet ReviewPopular stand-up lives on in 2012...for racers only
2011 Yamaha SuperJet ReviewCatch the final year of Yamaha's fun, agile stand-up
2011 Kawasaki Jet Ski 800 SX-R ReviewFun, Agile Standup Back For One Final Year
2010 Yamaha SuperJet ReviewLight and agile stand-up remains an enthusiast favorite
2010 Kawasaki Jet Ski 800 SX-R ReviewOld-school meets new in versatile stand-up PWC
2009 Kawasaki Jet Ski 800 SX-R ReviewVersatile stand-up satisfies both beginner and expert
2009 Yamaha SuperJet ReviewYamaha's stand-up craft is made for racing
2009 Yamaha WaveRunner LineupNew FZ Series features telescopic steering column
HSR-Benelli press launch: Part 2Compact three-cylinder motor powers entire lineup
HSR-Benelli press launch: Part 1Mechanical problems and bad luck overshawdow new watercraft
2004 Kawasaki Jet Ski SX-R 800 PreviewPower and handling yet unmatched in the stand-up world


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We'll be there, unBoothing at HIMSS – February 29 thru March 4, 2016. Vegas. Fuzzy dice, magic tricks, fresh oranges and our famous 24 hour buffet. And – an extravaganza of population health artistry – you haven't seen a booth like the FHG unBooth. Number 2477. Of course. HIMSS16. FastForward yourself to our value-based population health management solutions. Read more.
We transform your health care data into fuel you can use to manage populations of patients effectively. That's real population health management.Find out how we do it.
By harvesting messy, health care data from all of your disparate data sources, transforming it into actionable metadata, and delivering intuitive results through PopulationManager®, a powerful web-based engine that reveals gaps in care. With clean data and smart population health management, you will do amazing things.
Director of AODA Services ARC Community Services
Triage Nurse Evanston Internal Medicine, Family Medicine & Dermatology Northwestern Medical Group
Dr. GILBERT SIMON
Medical Director Sacramento Family Medical Clinic
We give clinicians information they want and need but could never access. When they (and their teams) can leverage this information to do the job they were born to do, patients will be healthier, quality will go up and costs will go down. That's where everyone is trying to go. With FHG, your information isn't just a fuzzy pile of data, it's transformed into focused, care coordination action lists that will become your organization's richest asset.
Getting data right is the first step in your improvement journey. Traditional IT approaches like data warehouses and BI platforms are not solving anybody's problems. Our approach to harvesting clinical and administrative data works. And to be clear, we don't have a magical algorithm or a mystical black box. Instead, we build solid, clean denominators. Your data is better because we build the cohorts of patients that all of your stakeholders will recognize and accept as accurate. From there, you pick the numerators that align with your goals.
Not an empty claim, a promise.
To move the needle of patient care…to really, really improve care, you have to do more than just spit out data. You have to get the data right. That means organizing it, cleaning it, deciding what to measure, what to focus on and even then you can't stop there. You have to present it intuitively so a care team can do something with it. Quickly. Efficiently.Find out how.
"PopulationManager has emerged as a great tool in the AMA Improving Health Outcomes program. It has helped us identify difficult-to-treat-patients - they are now more "on our radar." Additionally, using PopulationManager will positively affect the care we provide our patients by reducing end-organ damage that arises from uncontrolled hypertension. "
"PopulationManager has emerged as a great tool. It has helped us identify difficult-to-treat-patients - they are now more "on our radar." Additionally, using PopulationManager will positively affect the care we provide our patients by reducing end-organ damage that arises from uncontrolled hypertension."
"PopulationManager is a huge asset to our practice. Its intuitive and graphical interface makes it incredibly easy for us to quickly identify hypertensive patients needing close monitoring and to manage our high-risk populations."
"PopulationManager can look at the social determinants of health that are often associated with negative outcomes so I can focus on those populations."
Don't worry, we're not going to spam your inbox. We'll just take you through product demonstrations to get your feet wet or determine the best way to help you make a difference in your organization.


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"A psychological suspense story smartly narrated...Zoe has a quick wit that emerges in wickedly unexpected ways."
-New York Times Book Review
"The suspense keeps building throughout until the shocking ending. This is a riveting debut from a promising new thriller writer."
"Little Black Lies is a darkly intriguing mystery with a feisty young doctor as protagonist. Sandra Block pulls you in deep and doesn't let go."
—Meg Gardiner, Edgar Award-winning author
"Little Black Lies is a daring, original debut that explores the dark side of memory. In Zoe, Block has created a character who is complicated, smart, and sympathetic. I can't wait to see what Block has in store for Zoe next."
—Heather Gudenkauf, New York Times bestselling author


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San Diego / Re: USD 2007« on: August 09, 2007, 11:56:55 PM »
haha I found you. well if you can make it, it will be at the above mentioned tioni's crazee burger at 7pm. iSalute also sent a message out about it on the facebook message board. come!
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i will be volunteering for orientation on thurs/fri but i'm not a leader (meaning any actual planning)...i will, however, be working the book exchange table all day on wed


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Bring Me Kel'gash's Head!
Return the Head of Kel'gash the Wicked to Captain Helios at the Farstrider Enclave in the Ghostlands.
WANTED: Bring the head of Kel'gash the Wicked, chieftain of the Shadowpine trolls, to Captain Helios. No questions asked. Kel'gash is known to dwell somewhere to the south in Zeb'Nowa.
REWARD: Yes, but no advances!
You will be able to choose one of the following items:
|Well Crafted Long Bow
|Well Crafted Sword
|Well Crafted Staff
You will also receive:
- 1,950 experience
- 25
- 350 reputation with Silvermoon City


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|This document may not represent best practices for current development, links to downloads and other resources may no longer be valid. Current recommended version can be found here. ArchiveDisclaimer
/Runexit (devenv.exe)
Visual Studio 2005
Compiles and runs the specified project or solution, and then closes the integrated development environment (IDE).
Compiles and runs the specified project or solution according to the settings specified for the active solution configuration. This switch minimizes the IDE while the project or solution is run, and it closes the IDE after the project or solution has completed running.
Enclose strings that include spaces in double quotation marks.
Summary information, including errors, can be displayed in the Command window, or in any log file specified with the /out switch.
This example runs the solution MySolution in a minimized IDE using the active deployment configuration, and then closes the IDE.
devenv /runexit "C:\Documents and Settings\someuser\My Documents\Visual Studio\Projects\MySolution\MySolution.sln"


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Hi Tobias,
Just out of curiosity, as I was unable to locate any documentation on this.I have two questions. 1)Currently on back end in admin area of tablepress, the list of tables currently sort by table ID. I know I can click on Table name to sort by that, but is there a spot you can lead me to within files that I can change sorting to always sort by table name. 2) is there a spot within php files that I can change number of tables shown per page in backend?
If I have some how missed documentation on this please lead me to it and I will gladly read.
Thank you, as always, for your great work and continuous effort on this project. I put review and rating in this morning.


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Translation of sheaf in Spanish:
noun plural sheaves
- 1 (Agriculture)Example sentences
- A widespread custom, also designed to please the prophet and maximise crops, was to leave uncut on the field the last sheaf of grain, tying it into a special twist, known as 'Il'ia's beard'.
- Reaping will be by scythe and a 1953 Ferguson tractor, stooking - stacking the sheaves - will be by hand and threshing will involve a Victorian barn thresher.
- The reaper and self-binder (which bound the grain into sheaves mechanically) enabled farmers to work vast tracts with small crews.
- 2 (of notes)(of arrows) haz (masculine)Example sentences
- She pulled a sheaf of papers from her knapsack and shuffled through them.
- Upon making a decision the Emperor would have his servants place a sheaf of paper either over or under the rock.
- Today morning while stapling a sheaf of papers, I forgot that my finger was below and I was in such a fit of caffeine-induced working enthusiasm, I stapled my finger along with the papers.
Definition of sheaf in:
- British & World English dictionary
- US English dictionary
- English synonyms
- US English synonyms
What do you find interesting about this word or phrase?
Comments that don't adhere to our Community Guidelines may be moderated or removed.
Grammar and usage help for Spanish:
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= trending


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Icebreaker Q & A from 9/27/12
Question: What kinds of fruits and veggies do you put in smoothies to trick your kids into drinking something healthy?
The building blocks of smoothies were: Greek Yogurt, honey or agave nectar (to sweeten), whole milk or apple juice (or any juice) to thin out the drink.
Good veggies to put into drinks so they can't tell: spinach & kale
Good fruits to add:
- Avocados – to make creamy
- Frozen berries – to make icy and cold
- Pears, apples, bananas, berries – to add good flavor
Suggestions were to use a blender or a very good, expensive type of blender brand Vitamix to totally blend anything! The vitamixlady.com has good recipes for smoothies–she has 5 magic veggies that don't have much taste in smoothies: yellow squash, cabbage (red or green), carrot, zucchini, spinach.
Other sites (thanks, Sara)
Icebreaker Q & A from 10/25/12
What are some tips for date nights with your husband?
- It doesn't just happen easily, so be intentional (budget, ask around for babysitters, ask family, put it on calendar and work around it, etc.).
- Key is spending time together and re-establishing connection as a couple.
- After the kids are in bed, do something at home that you normally don't do (watch a movie & cuddle, light candles and have special coffee drink or dessert, etc.).
- Men like to talk while doing something else, so pick an activity to do on a date night (i.e. bowling -Latitude30 has a dinner and a movie option as well-, miniature golf, trivia night, etc.).
- Some other places suggested: Kilwins ice cream, walk around the Town Center, beach, Lillie's coffee bar at Neptune Beach (live outdoor music on weekends).


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Amber lynn is planning on going to vegas. before she leaves, she needs to decide which outfits to bring and her son's friend is the perfect person to help her decide. he's come over looking for his pal, but the only one home is amber. she knows her clothe
Produced by studio: My Friends Hot Mom.
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Nik Software Product Keys and Activation
I am trying to activate the Nik Collection, but I do not see where to enter the Product Key?
One of the improvements to the Nik Collection is the change to the activation process - there is no longer the need to enter a Product Key number to activate. We have taken care of the activation part on our end, and will send you individualized download links for your already-registered software.
The registered software is different from the trial software, so if you have installed the trial and need to activate it to the permanent version of the software, please contact us to receive your download link. We will send you your registered installation file, and that will overwrite the trial that is currently installed.
Was this article helpful?


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Bracciano Robe Hook
Unique geometric lines add polish and sophistication to today's stress-relieving retreats. Complement the look with the classic silhouettes of Bracciano's faucets, accessories.
- Zinc alloy die-cast
- Mounting hardware included
Additional Delacora Links
This Delacora item can also be referenced by the following color/finish specific model #:
- Delacora DELBARHBB*
Brushed Brass
- Delacora DELBARHBN*
Brushed Nickel
- Delacora DELBARHORB*
Oil Rubbed Bronze
- Delacora DELBARHCP*
Polished Chrome
- Delacora DELBARHPN*
Polished Nickel
*Discontinued model or finish
More Than Just a Store - Your Reasons to Shop
Discover the best online deals for the DELBARH and everything else for your home from the leading online home improvement store.
We're committed to providing you with the best assortment of Delacora products with over 400 warehouses across the country.
Our knowledgeable product specialists work to bring you the best prices on every product and provide unmatched customer service. Your satisfaction is our highest priority!
Manufacturer Resources
Installation Resource Center
Whether you are installing the product yourself or hiring a professional, our installation Resource Center has everything you need to get your project done. Visit the Installation Resource Center to get started.


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Would it be possible to take a capacitive/multitouch screen from an android tablet and use that as a display? Most tablets run off ARM as does the IGEP and the SEIKO screen has a ribbon interface. I can almost guarantee that the screen on, let's say, a cheap 7" android tablet would have the same if not similar interface. Another inspiration was the thread "How to use an alpine screen with your carpc" by etsicc.
I'm sure the biggest issues would be
1) physical interface with the IGEP
2) drivers (but since the screen was from an Android tablet technically it should work on a linux based distro)
3) form fitting into the bybyte case/double-din opening