text:
|Publication number
|Publication type
|Application number
|Publication date
|Dec 5, 1978
|Filing date
|Jun 30, 1976
|Priority date
|Jun 30, 1976
|Also published as
|Publication number
|Seymour R. Cray, Jr.
|Original Assignee
|Cray Research, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Referenced by (323), Classifications (10), Legal Events (5)
|External Links: USPTO, USPTO Assignment, Espacenet
The present invention pertains to the field of high speed digital data processors, and more particularly to computing machines adapted for vector processing.
Most prior art computers are organized with an arithmetic unit which can communicate with a memory and with input-output (I/O). To perform a given arithmetic function, each of the operands must be successively brought to the arithmetic unit from memory, the function must be performed, and the result must be returned to the memory. This process typically takes a great deal of time, since a number of clock periods are required for transmission between memory and the arithmetic unit, plus several clock periods for performing the operation. Machines operating with this type of organization are called scalar machines.
There are many circumstances in problem solving with computers where it is necessary to perform the same operation repetitively on each successive element of a set of data. In scalar machines, in order to perform this type of repetitive operation, it is necessary to operate by software program and indexing so as to successively bring each operand to the arithmetic unit and to return the result to memory. This type of task is very time consuming because of the delays associated with the memory-arithmetic unit transfers for each operation on the individual elements of the ordered set.
In order to provide more rapid processing when dealing with ordered arrays of data, vector machines have been developed. As used in the data processing field, the term vector refers to an ordered set or array of data. An illustrative vector operation performed by a vector machine would be the adding of two operand vectors to perform a result vector. Each element of the result vector in this example would be the sum of the correpondingly ordered operands of the operand vectors. Basically, a vector machine is one which deals with these ordered sets of data by virtue of its hardware organization, rather than by a software program and indexing, thus attaining a higher speed of operation.
One prior art vector machine is known as the Illiac, which attempts to provide full parallel operation on arrays of data. A network of 256 arithmetic unit processors are provided, and entire vectors up to 256 elements long are transmitted in parallel to the arithmetic unit processors. Results are transmitted in parallel back to memory. One obvious problem with this parallel approach to vector processing is the extremely high cost of providing a great number of independent arithmetic unit processors. Another problem is the inherent reliability problems with synchronizing all elements of such a large network.
Another type of vector machine makes use of four programmable arithmetic units, each having high speed paths termed "pipes" to bring operands to the arithmetic unit and to return results to memory. In operation, the vector is read through the pipes under hardware control to supply a stream of data to an arithmetic unit. One type of streaming machine employing pipes has been developed by Texas Instruments.
Another type of streaming system is represented by the Control Data Corporation Star machine. In this machine, one large stream of data, called a "sword" is provided to an arithmetic unit, rather than four smaller streams for pipes.
All streaming types of vector machines operate memory-to-memory. As such, they all suffer from the start-up time lag which is inherent in the memory to arithmetic unit path. It may take from 10 to 100 clock periods from initial instruction before the first pair of operands begin to arrive through the pipe or sword to the arithmetic unit. In other words, it takes a considerable period of time to fill the pipe with the stream of data. However once the pipe is filled and the data begins arriving, streaming type vector machines will give successive answers at a high rate of speed, much faster than scalar machines. Streaming type vector machines are thus put to their most efficient use when operating on very long vectors containing a great number of individual elements.
The length of vectors associated with the solution of a given problem is of course determined by the nature of the problem. Vector lengths can vary from two elements on up, with no theoretic upper limit. From actual experience in working with vector processing, it has been found that the most usually encountered vector problems involve rather short vectors of approximately 5 to 10 elements. With short vectors, it is generally not worth the start-up time required to operate in vector processing mode on prior art streaming type vector machines. As a result, the short vectors routinely encountered in numerous scientific calculations are generally still performed in the time inefficient scalar mode.
The present invention provides a vector processing machine which is uniquely adapted for efficient processing of short and moderate length vectors. Longer vectors can also be accommodated by processing in groups under program control.
The present invention provides vector processing apparatus for a computer. A plurality of vector registers are provided, each of which is adapted for holding a plurality of elements of an ordered set of data. At least one segmented functional unit, and in the preferred embodiment, a plurality of independent segmented functional units are provided. Each functional unit has an input for receiving operands and an output for delivering results computed or processed by the functional unit. Means are provided for successively transmitting the elements of one or more of the vector registers as operands to the input of a functional unit, and for successively transmitting results from the output of the functional unit to the elements of one of the vector registers.
As soon as results begin to be received in the result vector register, they may become available through a mode of operation known as chaining, for being simultaneously supplied as operands to another functional unit. In the chaining mode, more than one result can be obtained per clock period.
In the drawing,
FIG. 1 is a block diagram of a computer system which may incorporate the present invention;
FIG. 2 is a more detailed block diagram of the computation section of a computer incorporating the present invention;
FIG. 3 is a graphical representation of the concept of vector register processing of the present invention;
FIG. 4 is a timing diagram;
FIG. 5 is a graphical representation of the concept of vector register chaining according to the present invention;
FIG. 6 is a timing diagram for the chaining example of FIG. 6;
FIG. 7 is a schematic block diagram of a vector register and its control;
FIG. 8 is a schematic block diagram of the reservation and instruction issue portion of the vector register control; and
FIG. 9 is a table illustrating recursive operation of a vector register according to the present invention.
The configuration and operation of the vector processing and control means according to the present invention can best be understood by beginning with a general description of the organization of a computer system employing the present invention. Details of the configuration and operation of the vector processing will then be presented.
In the block diagram of FIG. 1, reference number 10 generally designates the central processor unit. Central processor 10 includes a computation section 11, a memory section 12, and an I/O section 13. Computation section 11 includes functional units, registers including vector registers, instruction buffers and control hardware for operating in either scalar or vector mode. Computation section 11 interfaces with memory section 12, and the memory section also interfaces with I/O section 13. Because of the extremely high data rate demands made by the computation section, especially when operating in vector mode, it is important that the memory section be large and fast if the full potential of the vector processing of the present invention is to be utilized. In a computer system built according to the preferred embodiment of the present invention, bipolar LSI memory chips are used, and one-quarter million to one million words of memory are provided.
The I/O section preferably contains 12 full duplex I/O channels which connect to I/O stations and peripheral equipment indicated by reference number 14 and to mass storage subsystems 15 which may include disc units. A maintenance control unit 16 may be connected through one of the I/O channels. The I/O channels are scanned sequentially for I/O requests which may be serviced on a priority basis.
FIG. 2 shows the computation section of the computer system of FIG. 1 in greater detail. Memory 12 is also shown in block diagram form. The computation section includes a set of vector registers generally designated by reference number 20. The vector registers form the major computational registers of the computer, since they provide for the high speed vector processing of data. In the preferred embodiment there are eight individual vector registers, designated V0 through V7. Each register has 64 individual elements, as indicated by the designation of elements 00 through 63 on vector register V0. Each element can hold a 64 bit word.
The specific numbers used herein for word length, number of registers, length of vector registers and the like relate to the presently preferred embodiment. It will be understood that the principles according to the present invention as set forth herein are equally applicable to other configurations of machines using a different number of vector registers, vector lengths, or a different word size.
A data path or trunk 21 is provided for data transfers between the vector registers and memory 12. Data path 21 connects to a signal path select, or fan-out 22 for communicating with individual vector registers. Another fan-out 23 is indicated for communicating from any of the vector registers to the functional units.
In the computer organization of FIG. 2, there are three functional units dedicated to vector processing. These are the add unit, the logical unit and the shift unit. Three additional functional units are shared between the vector and scalar portions of the machine. These are the floating point functional units for addition, multiplication and reciprocal approximation.
There are four scalar functional units: the addition, logical, shift, and population/leading zero functional units. Two functional units are associated with address functions: the add and multiply address functional units. Together the vector, floating point, scalar, and address functional units comprise the arithmetic unit of the machine. The vector and floating point functional units are each fully segmented for vector operation, as explained more fully hereinafter.
Scalar registers are provided as indicated by reference number 30. In the preferred embodiment eight scalar registers numbers S0 through S7 are used. A plurality of T registers 40 are provided to support scalar operations. In the preferred embodiment 64 T registers numbered T00 through T63 are employed. These T registers communicate with memory by a data path 41. Fan-outs 31 and 32 are provided for communicating with individual S registers. A data trunk 33 leads directly between fan-out 31 and memory 12. Another data path 34 communicates between the T registers and the fan-out for the scalar registers.
A plurality of address registers 50 are provided. In the preferred embodiment eight such registers A0 through A7 are used. Fan-outs 51 and 52 are used for communication with individual address registers. A plurality of B registers 60 are provided to support address operations. The preferred embodiment uses 64 such registers, numbered B00 through B63. A data path 61 provides two-way communication betwen memory 12 and the B registers. A data path 54 provides communication from the B registers to fan-out 51 for the A registers, and a data path 53 interconnects memory 12 and the A registers.
Instruction buffers 70 are provided as part of the instruction issue and control portions of the computer. In the preferred embodiment four instruction buffers are utilized, numbered 0 through 3. Each instruction buffer can contain 64 instruction parcels, numbered 00 through 63 as indicated with respect to instruction buffer 0. Instructions from the instruction buffers are fed via an instruction line 72 to a pair of control registers NIP, which stands for next instruction parcel and LIP which stands for lower instruction parcel. Instructions from NIP may be passed to the current instruction parcel register (CIP). Instructions may then be issued for execution as explained more fully hereinafter.
The P register is part of the instruction issue and control portions of the computer. It connects via lines 62 and 63 to the B registers and to the instruction path 72.
A set of channel address registers (CA) and the set of channel limit registers (CL) are provided for each channel of I/O. The CA register contains the address of the next channel word and the CL register specifies the limit address. In programming a channel, the CL register is first initialized with the channel limit address and then the channel is activated by setting the beginning address in CA. During transfer, the contents of CA is incremented towards the contents of CL. When the channel address equals the channel limit, the I/O transfer is complete and interrupt occurs.
A vector length register VL is provided, which may receive an input on a data line 80 from the A registers. XA refers to an exchange control register which is connected by a data line 81 to the A registers. VM is the vector mask register, and RTC is the real time clock.
The data and instruction paths or trunks among the various registers and functional units will now be described. The paths are indicated in the block diagram of FIG. 2 by means of letters V for vector, S for scalar, and A for address. In addition, subscripts i, j and k are used. Subscripts j and k are used for registers or data paths supplying operands, and subscript i is used for registers or data paths receiving results.
Data paths Vj and Vk run from vector register fanout 23 to the vector functional units and the floating point functional units. Data path Vi runs from the vector functional units and the floating point functional units to vector register fan-out 23.
In similar manner data paths Sj and Sk run from scalar register fan-out 32 to the scalar functional units and the floating point functional units. Data path Si returns from the floating point functional units and the scalar functional units to fan-out 32. Additionally, Sj data path connects to the real time clock, the vector mask register, and to the vector functional units. A data path 82 connects from the logical unit of the vector functional units to the vector mask register.
Data paths Aj and Ak run from fan-out 52 of the address registers to the address functional units. In addition, the Ak path provides address operands to the shift scalar functional unit and the shift vector functional unit. Data path Ak also runs to the channel address and channel limit registers. Ai data path runs from the address functional units, the CA and CL registers, and from the population/leading zero scalar functional unit to fan-out 52 of the address registers.
The purpose of each of the registers and functional units in FIG. 2 will now be briefly explained. As previously mentioned, the V registers are the major computational registers of the computer of FIG. 2. Each register has 64 elements. When associated data is grouped into successive elements of a V register, the register quantity may be considered a vector. Examples of vector quantities are rows or columns of a matrix or elements of a table. Computational efficiency is achieved by processing each element of a vector identically. Vector instructions provide for the iterrative processing of successive V register elements. For a given vector operation, one or more V registers are designated for providing operands (Vj and Vk registers), and another V register is designated to receive the results (Vi register). A vector operation begins by obtaining operands from the first element of one or more V registers and delivering the results to the first element of the Vi register. Successive elements are provided in each clock period, and as each operation is performed the result is delivered to successive elements of the result V register (Vi). The vector operation continues until the number of operations performed by the instruction equals a count specified by the contents of the vector length (VL) register. Vectors having lengths exceeding 64 are handled under program control in groups of 64 and a remainder.
A result may be received by a V register and retransmitted as an operand to a subsequent operation in the same clock period. The use of a register as both a result and operand register allows for the "chaining" of two or more vector operations together. In this mode, two or more results may be produced per clock period.
The contents of a V register are transferred to or from memory over data path 21 in a block mode by specifying a first word address in memory, an increment for the memory address, and a vector length. The transfer then proceeds beginning with the first element of the V register at a maximum rate of one word per clock period, depending upon memory bank conflicts.
In order to achieve high block transfer rates to and from memory, the memory 12 is preferably organized in four phased banks. By placing successive words in successive banks in rotating fashion, data can be transferred at a rate four times the random access time for a single memory bank.
Single word data transfers may be performed over the data path network between an S register and an element of a V register.
The vector length register (VL) can be set by transmitting a value to and from an A register. The VL register specifies the length of all vector operations performed by vector instructions, and the corresponding length of the vectors held by the V registers.
The vector mask register (VM) has 64 bits, each of which corresponds to a word element in a vector register. Bit 0 corresponds to element 0, and bit 63 to element 63. The mask is used in conjunction with vector merge and test instructions to allow operations to be performed on individual vector elements. The vector mask register may be set from an S register, or the vector mask contents may be generated by testing a vector register for a condition by the logical vector functional unit.
The mask controls element selection in a vector merge instruction. In one type of vector merge operation, the first operand is a scalar constant from register Sj, and the second operand is a successive element from a Vk register. In the other type of vector merge operation, the first operand is a successive element from a Vj register, and the second operand is a successive element from a Vk register. In either type of vector merge operation, the vector mask controls which of the operands will be transmitted to the Vi result register. If bit n of the vector mask is one, the first of the nth ordered operands is transmitted; if bit n of the mask is 0, the second of the nth ordered operands (the nth Vk element) is selected and transmitted to the nth element of the Vi register.
The eight 64 bit S registers are the principle scalar registers for the central processing unit. These registers serve as the source and destination for operands and results in the execution of scalar arithmetic and logical instructions. The related functional units perform both integer and floating point arithmetic operations. As will be explained more fully hereinafter, S registers may furnish one operand in a vector process.
Data can move directly between memory and S registers on data path 33, or it can be placed in T registers as an intermediate step. This allows buffering of scalar operands between S registers and memory. Data can also be transferred between A and S registers.
Another use of the S registers is for setting or reading the vector mask (VM) register or the real time clock register (RTC).
The T registers are used as intermediate storage for the S registers. Data may be transferred between T and S registers on data path 34, and between T registers and memory on data path 41.
The A registers serve a variety of applications. They are primarily used as address registers for memory references and as index registers but also are used to provide values for shift counts, loop control, and channel I/O operations. In address applications, they are used to index the base address for scalar memory references and for providing both a base address and an index address for vector memory references.
The address functional units support address and index generation by performing integer arithmetic on operands obtained from A registers and delivering the results to A registers. Data can move directly between memory and A registers via data path 53, or can be placed in B registers for buffering between A registers and memory. Data can also be transferred between A and S registers. The vector length register VL is set by transmitting a value to it from an A register.
The B registers are used as intermediate storage for the A registers. Typically, the B registers will contain data to be referenced repeatedly over a sufficiently long span that it would not be desirable to retain the data in either A registers or in memory. Examples of uses are loop counts, variable array base addresses, and dimensions.
The functional units perform the mathematical and logical functions in the computer. Functional units receive operands from registers and deliver results to registers when the function has been performed. All functional units perform their algorithms in a fixed amount of time, depending upon the particular functional unit. The amount of time required from delivery of operands to the unit to the completion of the calculation is termed the functional unit time, and is measured in multiples of the clock period.
The functional units are all fully segmented. This means that a new set of operands for unrelated computation may enter a functional unit each clock period even though the functional unit time may be more than 1 clock period. This segmentation is made possible by capturing and holding the information arriving at the unit or moving within the unit at the end of every clock period.
The address functional units perform integer addition and subtraction, and integer multiplication for address operands.
The scalar add unit performs integer addition and subtraction on scalar operands, and delivers results to scalar result registers.
The scalar shift unit may be used to shift the entire 64 bit contents of an S register or to shift the double 128 bit contents of two concatenated S registers.
The scalar logical unit performs bit by bit manipulation of 64 bit quantities obtained from S registers.
The population/leading zero count unit counts the number of bits having a value of one in an operand, and counts the number of bits of zero preceding a one bit in the operand. Operands are obtained from an S register, and a result is delivered to an A register.
Most of the vector functional units perform operations on operands obtained from one or two V registers or from a V register and an S register. The reciprocal approximation unit, which requires only one operand, is an exception. Results from vector functional units are delivered to a V register.
Successive operand pairs are transmitted to a functional unit each clock period. A corresponding result emerges from the functional unit n clock period later where n is the functional unit time and is constant for a given functional unit.
A functional unit engaged in a vector operation remains busy during each clock period and may not participate in another operation. In this state, the functional unit is said to be reserved. Other instructions that require the same functional unit will not issue until the previous operation is complete. When the vector operation completes, the reservation is dropped and the functional unit is then available for another operation.
Similarly, the vector registers are reserved for a time period in which they are involved in a vector operation. Other instructions that require the same vector registers will not issue until the previous operation is complete. An exception to this latter rule is in the case of chaining of vector functions, which is explained more fully hereinafter. However, since all functional units are independent, multiple unrelated vector processing can be underway simultaneously using different functional units and different operand and result registers for each period.
The vector add unit performs integer addition and subtraction for a vector operation and delivers the results to the elements of a designated Vi register. The vector shift unit shifts the entire 64 bit contents of a V register element or the 128 bit value formed from two consecutive elements of a V register. Shift counts are obtained from an A register. Shifts are end-off with zero fill.
The vector logical unit performs bit by bit manipulation of 64 bit quantities. The unit also performs the logical operations associated with the vector mask registrator, discussed previously.
The three floating point functional units perform floating point arithmetic for both scalar and vector operations. When executing a scalar instruction, operands are obtained from S registers and the results are delivered to an S register. When executing most vector instructions, operands are obtained from pairs of vector registers or from a V register and an S register and the results are delivered to a V register.
The floating point add unit performs addition or subtraction of 64 bit operands in floating point format. The floating point multiply unit provides multiplication of 64 bit operands in floating point format. The reciprocal approximation unit finds the approximate reciprocal of a 64 bit operand in floating point format.
The CIP register holds the instruction waiting to issue. If this instruction is a two parcel instruction, the CIP register holds the upper half of the instruction and the LIP holds the lower half. Once an instruction enters the CIP register it must issue. However, issue may be delayed until previous operations have been completed. Data arrives at the CIP register from the NIP register. The indicators which make up the instruction are distributed to all elements of the computer which have mode selection requirements when the instruction issues.
The NIP register holds a parcel of program code prior to entering the CIP register. If issue of the instruction in the CIP register is delayed, the data in the NIP register is held over for the next clock period.
The P register indicates the next parcel of program code to enter the NIP register in a linear program sequence. Instruction words contain four parcels of program code. The upper 20 bits of the P register indicate the word address for the program word in memory. The lower two bits indicate the parcel within the word. The content of the P register is normally advanced as each parcel successively enters the NIP register. The value in the P register normally corresponds to the parcel address for the parcel currently moving in the NIP register.
The four instruction buffers 70 each hold 64 consecutive 16 bit instruction parcels. These instruction parcels are held in the buffers prior to being delivered to the NIP or LIP registers.
The beginning instruction parcel in a buffer always has a parcel address that is an even multiple of 1008. This allows the entire range of addresses for instructions in a buffer to be defined by the high order 18 bits of the beginning parcel address. For each buffer, there is an 18 bit beginning address register which contains this value.
The beginning address registers are scanned each clock period. If the high order 18 bits of the P register match one of the beginning addresses, an in-buffer condition exists and the proper instruction parcel is selected from the instruction buffer. An instruction parcel to be executed is normally sent to the NIP register. However, the second half of a two parcel instruction is blocked from entering the NIP and is sent to the LIP, and is available when the upper half is used from the CIP register. An out-of-buffer condition exists when the high order 18 bits of the P register to not match any instruction buffer beginning address. When this condition occurs, instructions must be loaded into the instruction buffers from memory via data paths 71 before execution can continue.
The XA register is used in conjunction with an exchange mechanism for switching instruction execution from program to program. The XA register specifies the first word address of an exchange package which contains the necessary information for switching program execution.
The concept of vector register operation will now be generally described with the aid of FIG. 3. Vector instructions may be classified into four types. One type of vector instruction illustrated in FIG. 3A takes operands from a pair of vector registers and delivers results to another. In FIG. 3A, three vector registers are indicated, labeled Vj, Vk, and Vi. The curved figure labeled 90 is a symbolic representation of a data path through a functional unit. It is marked off in n clock periods, where n is the functional unit time for the given operation. As indicated by arrows 91 and 92, operands are successively read from the Vj and Vk registers and brought in pairs to the functional unit. Beginning n clock periods later, results are delivered at 93 into successive element of the Vi register.
The second type of vector instruction is illustrated in FIG. 3B. In this type, one operand is obtained from an S register, and one from a V register. A copy of the contents of the designated Sj register is delivered as indicated at 94 with each Vk register operand. Results again are delivered to the Vi register, beginning n clock periods later.
The other two types of vector instructions transmit data between memory and the V registers, as indicated in FIGS. 3C and 3D. A path between memory and the V registers may be considered a functional unit for timing considerations. In FIG. 3C, curved FIG. 95 is a symbolic representation of the data path from memory to a V register which is being loaded. Data begins entering the path from memory as indicated by arrow 96. Beginning six clock periods later, data is loaded into the successive elements of the Vi register, one element per clock period. FIG. 3D illustrates the inverse operation, with the contents of a V register being transmitted one word per clock period to memory.
The important concept of vector operation and functional unit segmentation will now be explained with the aid of the timing diagram of FIG. 4. Let a particular element of a V register be specified by adding the element number as a subscript to the register name. For example, the first three elements of register V1 are V10, V11, and V12, respectively. Since a vector register has 64 elements, the last element of V1 is V163.
The timing chart in FIG. 4 is for execution of a floating point addition instruction. This instruction is of the general type indicated in FIG. 3A since operands are obtained from two vector registers. In this example, V1 and V2 serve as the j and k operand registers, and Vo is the i or result register. When the instruction issues at clock period t0, the first pair of elements V10 and V20 is transmitted to the add functional unit where it arrives at clock period t1. The dashed lines indicate transit to and from the functional unit, and the bars or solid lines indicate time in the functional unit. The functional unit time for this unit is six clock periods, so the first result, which is the sum of V10 and V20 exits from the functional unit at clock period t7. The sum is transmitted to the first element of result register V0 arriving at clock period t8. Because the functional unit is fully segmented, the second pair of elements V11 and V21 is transmitted to the add functional unit at clock period t1. At clock period t2 the functional unit is in the process of performing two additions simultaneously, since the addition of V10 and V20 was begun in the previous clock period. The second result, which is the sum of V11 and V21, is entered into the second element of result register V0 at clock period t9. Continuing in this manner, a new pair of elements enters the functional unit each clock period and the corresponding sum emerges from the unit six clock periods later and is transmitted to the result register. Since a new addition is begun each clock period, six additions may be in progress at one time. In general, the number of operations which can be performed simultaneously by a functional unit is equal to the functional unit time.
The vector length determines the total number of operations performed by a functional unit. Although each vector register has 64 elements, only the number of elements specified by the vector length register is processed by vector instruction.
As previously mentioned, when a vector instruction issues, the required functional unit and the operand registers are reserved for the number of clock periods determined by the vector length. A subsequent vector instruction which requires the same functional unit or operand register cannot issue until the reservations are released. When two vector instructions use different functional units and vector registers, they are independent and may issue in neighboring clock periods.
When a vector instruction issues, the result register is reserved for the number of clock periods determined by the vector length and functional unit time. This reservation allows the final operand pair to be processed by the functional unit time and the corresponding result to be transmitted to the result register.
A result register becomes the operand register for a succeeding instruction. In the process called "chaining," the succeeding instruction issues as soon as the first result arrives for use as an operand. This clock period is termed "chain slot time" and it occurs only once for each vector instruction. If the succeeding instruction cannot issue at chain slot time because of a prior functional unit or operand register reservation, then it must wait until the result register reservation is released.
FIG. 5 is a graphic illustration of the chaining of vector functions. Curved figure 100 indicates a memory read instruction wherein date from memory is loaded into vector register V0. Curved figure 101 indicates an integer add function, wherein operands from the V0 and V1 register are added and delivered to the V2 register. Curved figure 102 graphically represents a shift function wherein operands are received from the V2 register and delivered to the V3 register. Curved figure 103 indicates a logical product in which operands are taken from the V3 and V4 register, and the results are delivered to the V5 register.
FIG. 6, which is a timing diagram of the example of FIG. 5, will help clarify the concept of chaining. Gradations along the horizontal axis represent clock periods. The memory read instruction issues at clock period t0. Each horizontal line shows the production of one element of the V5 result vector. Time spent in passing through each of the four functional units used in the instruction sequence is indicated by bars of corresponding length. Broken lines indicate passage of data to and from V registers, between functional units. Note that the production of a new element of V5 begins each clock period. Production of the first element of V5 begins at clock period t0 with the reading of the first word from memory, production of the second element V5 begins at clock period t1, with the reading of the second word from memory and so on. The first result enters V5 at clock period t23 and a new result enters V5 each clock period thereafter. In the first horizontal line, which shows the production of the first element of V5 (V50), chain slot times for each functional unit are marked by asterisks.
The vector read instruction issues at clock period t0. The first word arrives in element 0 of register V0 at clock period t8, and is immediately transmitted along with element 0 of register V1, as an operand to the integer add functional unit. When the two operands arrive at the integer add functional unit at clock period t9, the computation of the sum of V00 and V10 is begun. Three clock periods later at t12 the sum is sent from the functional unit to element 0 of V2. It arrives at clock period t13 and is immediately transmitted as an operand to the shift functional unit. At clock period t14 the operand arrives at the shift functional unit and the shift operation is begun. The operation is completed four clock periods later at t18 and the shifted sum is sent from the functional unit to element 0 of V3, arriving the next clock period. It is immediately transmitted, along with element 0 of V4, as an operand to the logical functional unit. When the two operands arrive at the logical functional unit at clock period t20, the computation of the logical product of V30 and V40 is begun. Two clock periods later at t22 the final result is sent from the functional unit to element 0 of V5 arriving at clock period t23. While all this has been going on, production of the second element of V5 has been tracing the same path through the vector registers and functional units with a one clock period lag. Production of the third element of V5 lag is one more clock period behind, and so on. A new result arrives at the V5 result register each clock period.
The vector register control and instruction issue will now be explained in greater detail with reference to FIGS. 7 and 8. In FIG. 7, a representative one of the eight registers is indicated by reference number 120. A data path 121 goes from the vector register to a path select network 122. Another data path runs from path select 122 to a functional unit, indicated by reference number 124. This functional unit could be any one of the six which are designed for vector processing, since each can be supplied from any V register. Another data path 125 runs from path select 122 to memory 12. Indicated in broken lines are a data path 126 which feeds data from another of the vector registers into a functional unit. Also indicated by broken line is a date path 127 which may deliver a copy of a scalar register to functional unit 124 with each operand during vector processing.
On the other side of the drawing is a functional unit also indicated by reference number 124 and the memory 12. These units deliver data to a path select 130 by means of data paths 131 and 132, respectively. Data from path select 130 is delivered via data path 133 to the vector register 120.
Vector processing control for vector register 120 of FIG. 7 is provided by element address counter 134, vector length counter 135, write control counter 136 and associated logic elements. Address counter 134 when enabled may be incremented by clock pulses applied thereto by lead 137. Address register 134 has possible count states 0 through 63, each one of which enables a given element of vector register 120 for a read or write operation. This function is indicated in FIG. 7 by control lead 140 which branches to each of the elements of register 120. Enable for address counter 134 is provided by an AND gate 141 which receives inputs from an OR gate 142 and from the vector length counter 135. Vector length counter 135 receives clock pulses on lead 143, and the vector length information on lead 144. This information is supplied from a gate 145 which receives go parameter and VL register data as its inputs. The output of OR gate 142 also supplies an enable signal to the vector length counter.
The go sequence signal supplies one input to a gate 150, the other input of which is supplied by the clock. The output of this gate goes to decrement write control counter 136. An initial count is loaded into write control counter 136 by count select unit 151, when the count select unit receives a go functional unit signal. This an other timing and control signals are explained further with reference to FIG. 8.
Write control counter 136 in turn supplies a chain slot signal on lead 152 and a go write signal on lead 153.
The go write signal and a Vi register select signal are supplied as inputs to an AND gate 154. A go sequence signal and a Vj or Vk register select signal are provided as inputs to AND gate 155. The outputs of AND gates 154 and 155 are applied as inputs to OR gate 142.
Referring now to FIG. 8, the contents of the CIP register (current instruction parcel) are applied to a decoder 160. Before this instruction is allowed to issue, it is examined for possible timing conflicts with vector registers and functional units already involved in previous operations. This examination is performed as follows.
If the instruction is a vector instruction, the i, j and k requests are decoded. The j and k requests indicate which of the eight vector registers are sought as operand registers, and the i request indicates which of the vector registers is sought as the result register. The i request is transmitted to 161, then via lead 163 to a comparison circuit 165. The j and k requests are transmitted to 162, then via lead 164 to comparison circuit 165.
Reference number 170 generally designates the reservation register. It has eight sections, each corresponding to one of the vector registers V0 through V7. At a given moment, reservation register 170 contains set bits for each vector register currently involved in a vector process. These reservation bits were set via set lines from gate 171 by the issuance of a previous instruction. When a register becomes free upon completion of the vector process in which it was involved, a control signal is generated by the vector control circuits and is transmitted to the appropriate section of reservation register 170 as a register free signal. This removes the set bit in the reservation register.
The outputs indicating whether set or not for each of the sections of reservation register 170 are transmitted via leads 172 to a chain slot control 173. Chain slot control 173 has eight sections each corresponding to one of the vector registers V0 through V7. Ordinarily the signal applied thereto from lead 172 is transmitted through the chain slot control and leads 174 to compare circuit 165. During the chain slot time for a given vector register, a chain slot signal may be applied to the corresponding section of the chain slot control. Receipt of a chain slot signal momentarily blocks or removes any reservation signal which would otherwise be transmitted to compare circuit 165, but only for the single clock period of the chain slot signal.
Comparison circuit 165 functions to compare the i, j and k requests at leads 163 and 164 against the vector register reservation bits applied by leads 174. If no conflict exists, an enable is passed via lead 175 to AND gate 176. If a conflict exists, the enable is held until the conflict is resolved.
The functional units are also tested to see whether they are busy. This is accomplished by decoding a functional unit request signal from the decoder which is applied to a test circuit indicated by reference number 180. Associated with test circuit 180 are six counters C0 through C5, each of which is associated with a given functional unit. When a functional unit is involved in a vector process, the vector length information is applied to a set circuit 181 which sets the appropriate counter C0 through C5 involved in the process, according to the vector length. The counter then begins to count down on successive clock periods until it reaches zero, indicating that the functional unit is no longer reserved and is ready for another instruction.
Test unit 180 compares the functional unit request with the status of the functional unit counters. If the requested unit is available, an enable signal is passed on lead 182 to the other input of AND gate 176. If the requested counter is not available, the enable is held until the counter becomes available. At the same time as an enable signal is passed, the functional unit request is passed by lead 183 to a gate 184. Gate 184 also receives the j and k requests via control line 164. The i request information is combined with the j and k request information at 185, and the combined request information is passed via lead 186 to gate 184.
The output of gate 176 is called the go issue signal, and it is supplied via lead 190 to gate 184, and also to gate 171. The go issue enables the i, j and k request data to issue as a go parameter signal. At the same time, the functional unit request is issued as a go functional unit signal. The j and k data is passed through a variable delay 191 then issues as a go sequence signal.
The issue of instructions and flow of data will now be explained with reference to FIGS. 7 and 8 for an example. Assume that an instruction parcel has been loaded into CIP and is being decoded and checked for reservations on the requested vector registers and functional units. If the registers requested by the i, j and k designators do not have bits set in the reservation register, an enable is provided at 175. If the functional unit requested is not busy in a previous process, an enable is provided at lead 182. A go issue signal then issues on lead 190. The present i, j and k requests are then gated through gate 171 and into the sections of reservation register 170 corresponding to the registers to be used by the just issued instruction. At the same time gate 184 is enabled and the go parameter and go functional unit signals are passed. These signals are applied to the vector registers, path select networks and functional units involved in the just issued vector instruction, to provide setup. Delay 191 is provided to allow time for setup before the go sequence signal starts the vector process. Variable delay 191 is selected by a table or other means not shown according to the required setup time for the given functional unit and process involved.
Assume that vector register 120 of FIG. 8 has been selected as an operand register Vk in the just issued instruction. Path select 122 is then set up to provide a data path from register 120 to the desired functional unit 124. Data path 126 or 127 may also be set up to provide date to the same functional unit from another vector register or a scalar register, depending upon the nature of the instruction. Alternatively, if the vector instruction is to write from the vector register into memory, path select network 122 will set up data path 125 to memory. The go functional unit signal sets up the selected functional unit for operation.
The go parameter signal also enables gate 145 so that the vector length number from the VL register is loaded into vector length counter 135. Since we are assuming that vector register 120 of FIG. 7 is to be an operand register, there will be no Vi register select signal, so gate 154 will not be enabled. Instead, a Vj or Vk register select signal will be applied to gate 155 of this register, and all paths and units are now set up waiting for the go sequence signal.
Upon receipt of the go sequence signal, gate 155 is enabled, and this signal is transmitted through OR gate 142 as a start signal for gate 141 and an enable signal for the vector length counter.
Successive clock pulses now proceed to increment address counter 134, and with each increment a successive word element of vector register 120 is sent out over data path 121 to the functional unit. The functional unit then begins operating on the operands thus supplied together with the operands from the other source, data path 126 or 127.
At the same time, vector length counter 135 is enabled and successive clock pulses begin to decrement the vector length counter. If the count is not equal to zero, lead 146 remains enabled, and the address counter remains enabled. After a number of clock pulses equal to the vector length VL, the vector length counter reaches zero. At this point lead 146 removes the enable from gate 141 and address counter 134 so that no further elements will be clocked out of vector register 120. At the same time, a control signal is transmitted over line 147 as a register free signal. This signal is applied to the appropriate register free input to the reservation register 170, thus removing the reservation previously set on the particular vector register.
Assuming now that FIG. 7 represents the Vi or result register in the previous example, vector control and processing proceeds as follows.
Upon issue, go parameter control will set up path select 130 to receive data from whichever functional unit is selected, and transmit data to the result vector register 120. If the instruction is one for transferring data from memory to the vector register, path 132 will be selected.
Vector length counter 135 will be loaded with the vector length as before, and address counter 134 is reset to zero ready to begin incrementing when enabled. Since the register is not selected as a Vj or Vk register, gate 155 is not enabled. Since the register is selected as a Vi register, one enable is provided for gate 154. The other enable must come from the write control counter 136. Upon receipt of the go functional unit signal, count selector 151 loads a predetermined number into the write control counter. This predetermined number corresponds to the functional unit time for the functional unit involved.
Upon receipt of the go sequence signal, gate 150 is enabled, and successive clock pulses begin decrementing write control counter 136. However, address counter 134 and vector length counter 135 are not yet enabled for this Vi register. Meanwhile, the operand registers are supplying elements to the functional unit, but results are not yet available at the output of the functional unit.
Two clock pulses before write control counter 136 reaches zero, a one period long pulse is transmitted over lead 152 as the chain slot signal. When the zero count is reached, an enable is provided on lead 153 to gate 154, gate 142, gate 141, the address counter and the vector length counter. On the next clock pulse, the address counter begins clocking the successive elements of vector register 120 to receive data which is now coming through signal path 131 and 133 from the functional unit. The delay provided by write control counter 136 thus correlates with the delay in receiving the first result from the functional unit. Thereafter, results are received on each successive clock period, and address counter 134 increments the elements of register 120 to receive the result vector. Vector length counter 135 operates in the manner previously described to halt the process when VL is reached, and to transmit a register free signal to the corresponding portion of the vector reservation register 170.
Assume that very shortly after issuance of the vector instruction in the previous example, a second vector instruction were to appear in CIP. Assume further that this instruction called for a different functional unit and result vector register, but that it called for the result register from the previous instruction to be an operand register in the subsequent instruction. An enable would be received at lead 182 in FIG. 8, since there would be no conflict with the functional units. However, the j or k requests would conflict with the result register from the process currently in progress as indicated by a set bit in the reservation register. No enable will then be provided at lead 175, and issue of the second instruction will be delayed. However, at two clock periods before the i register of the previous instruction (intended to be an operand register for the subsequent instruction) begins to receive results, the chain slot signal is generated by the write control counter of the result register. This chain slot signal is applied to chain slot control 173 and removes, for one period only, the i register reservation. During this clock period, the conflict detected by comparison circuit 165 is removed and the next control is immediately issued. Assuming two clock periods for setup time, the path select and functional unit select for the next vector instructions will be ready for the next vector instruction's go sequence signal, and the second vector process will be chained to the first. In other words, results received at the i register for the first instruction will be simultaneously retransmitted as operands to the functional unit for the next instruction.
In a vector operation, the result register Vi is not normally the same vector register as the source of either of the operands (Vj or Vk), although the result register can become an operand register for a chained successive vector operation. However, turning the output stream of a vector functional unit back into the input stream by setting the i designator to the same register designator as j or k may be desirable under certain circumstances since it provides a facility for reducing 64 elements down to just a few. The number of terms generated by the partial reduction is determined by the number of values that can be in process in a functional unit at one time (i.e., functional unit time plus two clock periods).
When the i designator is the same as the j or k designator, a recursive characteristic is introduced into the vector processing because of the way in which element address counters (134) are handled. At the beginning of the operation for which i is the same as j or k, the address counters for both the operand register and the operand/result register are set to zero. The address counter for the operand/result register is held at zero and does not begin incrementing until the first result arrives from the functional unit at functional unit time plus two clock pulses. This counter then begins to advance by one each clock period. Note that until functional unit plus two clock periods, the initial contents of element zero of the operand/result register are repeatedly sent to the functional unit. The element counter for the other operand register, however, immediately begins advancing by one on each successive clock period thus sending the contents of elements zero, one, two. . . one successive clock periods, in accordance with the description previously set forth with respect to the operation of FIG. 7. Thus, the first functional unit time plus two elements of the operand/result register contain results based on the contents of element zero of the operand/result register and on successive elements of the other operand register. These functional unit time plus two elements then provide one of the operands used in calculating the results for the next functional unit time plus two elements. The third group of functional unit time plus two elements of the operand/result register contains results based on the results delivered to the second group of functional unit time plus two elements, and so on until the final group of functional unit plus two elements is generated as determined by the vector length.
As an example, consider the situation in which it is desired to sum all the elements of a single vector. Rather than performing successive addition operations on each element, the recursive characteristic of the vector functional unit can be employed for this vector summation. Assume that the initial conditions for the vector operation are the following: All elements of register V1 contain floating point values. Register V2 will provide one set of operands and will receive the results. (i = j) Element zero of this register contains a zero value. The vector length register VL contains 64.
A floating point add instruction is then executed using register V1 for one operand and using register V2 as an operand/result register. This instruction uses the floating point add unit which in the preferred embodiment has a functional unit time of 6 clock pulses causing sums to be generated in groups of eight (functional unit time plus 2 = 8). The final eight partial sums of the 64 elements of V1 will end up being contained in elements 56 through 63 of V2. Specifically, the elements of V2 will contain the sums indicated in FIG. 9, where subscripts indicate the individual elements of the specific registers, V1 or V2. The eight partial sums can then be summed in a separate process, with the entire summation having taken only a fraction of the time for scalar summation at 64 elements.
In the preferred embodiment of the present invention, if an integer summation were performed instead of a floating point summation, five partial sums would be generated and placed in elements 59 through 63 since the functional unit time for the interger add unit in the preferred embodiment is three clock pulses.
This recursive characteristic of vector processing is applicable to any vector operation, arithmetic or logical. The value initially placed in element zero of the operand/result register will depend on the operation being performed. For example, when using the floating point multiply unit, element zero of the operand/result register will usually be set to an initial value of 1.0.
In general, the vector processing means of the present invention may find wide use in many types of problems. One example may be with Do Loops in FORTRAN programs. Since these loops inherently involve repetitive operations on a set of data, they are readily adaptable to vector processing, and perhaps chaining. In addition, inner Do Loops nested within outer loops can be efficiently solved with a computer according to the present invention. Attempts have been made for many years to unwrap nested Do Loops by compiler action so as to speed efficiency in prior art machines, but the attempt has been largely unsuccessful. However, in the present invention, the inner loop may be run in vector mode while the loading and organizing for scalar mode running of each outer loop, and the memory to vector register loading for successive inner loop runs is taking place. Therefore, the startup time for the outer Do Loop in scalar mode is not wasted, but is hidden since it is concurrent with the running of an inner loop in vector mode.
If the number of elements in a loop or other vector exceeds 64, a vector loop is required to process the entire vector. The loop or vector is divided by 64 to determine the loop count. The loop is then processed in segments plus a remainder.
Another very useful example of a type of problem which can be efficiently solved by the present invention is matrix multiplication. When matrix A and matrix B are multiplied to give matrix C, the elements of matrix C are calculated by a summation of products of the row and column elements of matrix A and B. The calculation of this combination of multiplication and addition lends itself well to chaining, and as a result this type of problem can be performed with extreme efficiency according to the present invention.
Matrix multiplication is typical of the large class of problems which can be vectorized. For these problems a significant increase in processing speed can be achieved over conventional scalar processing. The use of register to register vector instructions, the concept of chaining, and the use of the plurality of independent segmented functional units provides a large amount of concurrency of processing. Further, since the startup time for vector operations are nominal, the benefits of vector processing are attainable even for short vectors. The resulting high processing speeds exceed those of other existing vector machines.
|Cited Patent
|Filing date
|Publication date
|Sep 28, 1966
|Aug 19, 1969
|Execution unit with a common operand and resulting bussing system
|Jul 11, 1968
|Apr 6, 1971
|Texas Instruments Inc
|Memory buffer for vector streaming
|Apr 28, 1972
|Jan 22, 1974
|Texas Instruments Inc
|Pipelined high speed arithmetic unit
|Aug 29, 1972
|Jun 4, 1974
|Texas Instruments Inc
|General-purpose array processor
|Nov 2, 1973
|Apr 1, 1975
|Raytheon Co
|Pipeline signal processor
|Citing Patent
|Filing date
|Publication date
|Aug 29, 1979
|May 26, 1981
|Fujitsu Limited
|Data processing system having a high speed pipeline processing architecture
|Jun 29, 1979
|Oct 13, 1981
|International Business Machines Corporation
|Machine for multiple instruction execution
|Jul 10, 1979
|Nov 24, 1981
|Texas Instruments Incorporated
|Micro-vector processor
|Sep 21, 1981
|Sep 21, 1982
|Hall Jr William B
|Parallel digital computer architecture
|Apr 15, 1980
|Dec 28, 1982
|National Semiconductor Corporation
|Modular digital computer system for storing and selecting data processing procedures and data
|May 30, 1980
|Jan 4, 1983
|Canon Kabushiki Kaisha
|Calculator for cross summing a plurality of operands
|Sep 29, 1980
|Feb 1, 1983
|Control Data Corporation
|Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units
|Mar 23, 1982
|Sep 10, 1985
|Hitachi, Ltd.
|Data processing system including scalar data processor and vector data processor
|Feb 22, 1983
|Jan 28, 1986
|The United States Of America As Represented By The Director Of The National Security Agency
|Fast parallel sorting processor
|Mar 8, 1982
|Apr 22, 1986
|International Business Machines Corp.
|Method of controlling use of resources in a data processing system by at least two processes
|Dec 22, 1982
|Jun 10, 1986
|Ibm Corporation
|Vector processing
|Dec 27, 1982
|Oct 14, 1986
|Hitachi, Ltd.
|Vector processor
|Jun 20, 1984
|Oct 28, 1986
|Wallach Steven J
|Computer system
|Dec 16, 1983
|Nov 4, 1986
|Hitachi, Ltd.
|Processor for carrying out vector operation wherein the same vector element is used repeatedly in succession
|Jun 13, 1983
|Nov 4, 1986
|Duke University
|SIMD machine using cube connected cycles network architecture for vector processing
|May 18, 1983
|Dec 16, 1986
|International Business Machines Corporation
|Apparatus for executing an instruction and for simultaneously generating and storing related information
|Feb 1, 1983
|Dec 30, 1986
|Hitachi, Ltd.
|Vector processor system comprised of plural vector processors
|Apr 25, 1983
|Jan 13, 1987
|Cray Research, Inc.
|Computer vector multiprocessing control
|Jan 20, 1984
|Feb 3, 1987
|Hitachi, Ltd.
|Vector processor having pair process mode and single process mode
|Jun 20, 1984
|Feb 24, 1987
|Weatherford James R
|Physical cache unit for computer
|Mar 28, 1984
|Mar 17, 1987
|Hitachi, Ltd.
|Vector data processor
|Dec 14, 1982
|Apr 14, 1987
|Hitachi, Ltd.
|Pipeline arithmetic apparatus
|Apr 30, 1986
|Apr 28, 1987
|Cray Research, Inc.
|Flexible chaining in vector processor with selective use of vector registers as operand and result registers
|Dec 21, 1984
|Jun 30, 1987
|Nec Corporation
|Device for controlling access to a computer memory
|Jan 12, 1984
|Jun 30, 1987
|Hitachi, Ltd.
|Vector processor
|Sep 27, 1984
|Sep 22, 1987
|Honeywell Information Systems Inc.
|Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization
|Jul 31, 1985
|Nov 10, 1987
|Sperry Corporation
|Local store for scientific vector processor
|Aug 6, 1986
|Nov 17, 1987
|Honeywell Bull Inc.
|Prioritized secondary use of a cache with simultaneous access
|Jul 11, 1985
|Dec 1, 1987
|Nec Corporation
|Vector processing system
|Jul 24, 1984
|Dec 8, 1987
|Hitachi, Ltd.
|Data processing apparatus
|Feb 17, 1984
|Mar 29, 1988
|Hitachi, Ltd.
|Data process system including plural storage means each capable of concurrent and intermediate reading and writing of a set of data signals
|Dec 6, 1985
|Apr 19, 1988
|Nec Corporation
|Information processing device capable of rapidly processing instructions of different groups
|Mar 26, 1986
|Apr 26, 1988
|Schlumberger Systems And Services, Inc.
|Computing processor with memoryless function units each connected to different part of a multiported memory
|Jun 28, 1985
|May 17, 1988
|Cray Research, Inc.
|Memory reference control in a multiprocessor
|Jun 17, 1985
|May 17, 1988
|International Business Machines Corp.
|Vector processing
|Jun 28, 1985
|Jun 28, 1988
|Cray Research, Inc.
|System for multiprocessor communication using local and common semaphore and information registers
|Dec 21, 1984
|Jul 5, 1988
|Hitachi, Ltd.
|Vector processing unit capable of reading vector data from a vector register simultaneously to plural resources
|Dec 21, 1984
|Jul 12, 1988
|Hitachi, Ltd.
|Vector processor capable of performing iterative processing
|Feb 28, 1986
|Jul 26, 1988
|Scientific Computer Systems Corporation
|Bi-directional databus system for supporting superposition of vector and scalar operations in a computer
|Sep 27, 1984
|Aug 2, 1988
|Nec Corporation
|Vector processing apparatus
|Sep 7, 1984
|Aug 2, 1988
|Nec Corporation
|Vector processor wherein outputs of vector registers are fixedly coupled to inputs of vector calculators
|May 5, 1986
|Aug 30, 1988
|Hitachi, Ltd.
|Vector data refer circuit with a preceding paging control for a vector processor apparatus therefor
|Jun 22, 1984
|Sep 13, 1988
|International Business Machines Corp.
|Virtual vector registers for vector processing system
|Dec 24, 1985
|Sep 20, 1988
|Hitachi, Ltd.
|Vector operation designator
|Jun 16, 1986
|Oct 11, 1988
|Nec Corporation
|Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
|May 24, 1985
|Oct 25, 1988
|Hitachi, Ltd.
|Data processor with associative memory storing vector elements for vector conversion
|Jun 10, 1986
|Nov 1, 1988
|Hitachi, Ltd.
|Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions
|Mar 2, 1987
|Dec 13, 1988
|International Business Machines Corporation
|Vector processing unit
|Sep 29, 1983
|Jan 24, 1989
|Tandem Computers Incorporated
|Multiple data patch CPU architecture
|Oct 14, 1987
|Feb 21, 1989
|Cornell Research Foundation, Inc.
|Instruction issuing mechanism for processors with multiple functional units
|Nov 18, 1985
|Feb 28, 1989
|Shunichi Torii
|Data storage device
|Jan 21, 1988
|Feb 28, 1989
|Convex Computer Corporation
|Concurrent processing of data operands
|Aug 19, 1987
|Mar 14, 1989
|Convex Computer Corporation
|Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of machine instructions
|Mar 2, 1987
|Apr 25, 1989
|Hitachi, Ltd.
|Vector processor for reordering vector data during transfer from main memory to vector registers
|Feb 6, 1987
|Jun 6, 1989
|Scientific Computer Systems Corporation
|Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations
|Mar 28, 1988
|Jul 18, 1989
|Nec Corporation
|Data processing circuit for calculating either a total sum or a total product of a series of data at a high speed
|Jul 31, 1985
|Aug 15, 1989
|Unisys Corporation
|Loop control mechanism for scientific processor
|Oct 6, 1987
|Aug 22, 1989
|Nec Corporation
|Vector data processing system comprising an I/O control for each vector data processor and another I/O control for at least one other vector data processor
|Dec 15, 1987
|Oct 10, 1989
|Convex Computer Corporation
|Instruction processing unit for computer
|Mar 8, 1989
|Nov 28, 1989
|International Business Machines Corp.
|High performance parallel vector processor having a modified vector register/element processor configuration
|Mar 20, 1989
|Dec 19, 1989
|International Business Machines Corp.
|Parallel vector processor using multiple dedicated processors and vector registers divided into smaller registers
|Dec 10, 1985
|Dec 26, 1989
|Hitachi, Ltd.
|Vector processing apparatus for incrementing indices of vector operands of different length according to arithmetic operation results
|Jun 16, 1988
|Feb 13, 1990
|Cray Research, Inc.
|Computer vector multiprocessing control with multiple access memory and priority conflict resolution method
|Apr 22, 1988
|Mar 20, 1990
|Hitachi, Ltd.
|Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit
|Apr 12, 1988
|May 15, 1990
|Convex Computer Corporation
|Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses
|Jul 31, 1985
|Jul 31, 1990
|Unisys Corporation
|Tightly coupled scientific processing system
|Feb 23, 1988
|Aug 14, 1990
|Stellar Computer, Inc.
|System for transferring multiple vector data elements to and from vector memory in a single operation
|Mar 18, 1988
|Aug 14, 1990
|Digital Equipment Corporation
|Method and apparatus for executing instructions for a vector processing system
|May 6, 1988
|Nov 27, 1990
|Science Applications International Corporation
|Array processor
|Aug 31, 1987
|Dec 25, 1990
|Digital Equipment
|Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports
|Jul 29, 1988
|Jan 15, 1991
|Hitachi, Ltd.
|Computer for synchronized read and write of vector data
|Sep 14, 1987
|Jan 15, 1991
|Visual Information Technologies, Inc.
|High speed image processing system using separate data processor and address generator
|Mar 18, 1988
|Apr 16, 1991
|Digital Equipment Corporation
|Context switching method and apparatus for use in a vector processing system
|Feb 28, 1989
|May 7, 1991
|Nec Corporation
|Vector operation instruction activation controller for vector arithmetic units having arithmetic functions with different numbers of pipeline stages
|Jul 2, 1985
|May 28, 1991
|Nec Corporation
|Computer system for directly transferring vactor elements from register to register using a single instruction
|Aug 2, 1989
|Jul 30, 1991
|Texas Instruments Incorporated
|Master/slave sequencing processor
|Mar 18, 1988
|Aug 27, 1991
|Digital Equipment Corporation
|Exception reporting mechanism for a vector processor
|Feb 29, 1988
|Sep 17, 1991
|Convex Computer Corporation
|Multi-processor computer system having self-allocating processors
|Jan 10, 1988
|Feb 4, 1992
|Hitachi, Ltd.
|Parallel computer with asynchronous communication facility
|Apr 27, 1989
|Mar 31, 1992
|Nec Corporation
|Memory access control device which can be formed by a reduced number of lsi's
|Jan 24, 1989
|Apr 28, 1992
|Visual Information Technologies, Inc.
|High speed image processing computer
|Aug 29, 1988
|Apr 28, 1992
|Hitachi, Ltd.
|Vector multiprocessor system which individually indicates the data element stored in common vector register
|Jan 9, 1991
|May 12, 1992
|Digital Equipment Corporation
|Method and apparatus for handling faults of vector instructions causing memory management exceptions
|Jan 17, 1989
|Jun 30, 1992
|Cray Research Inc.
|Computer look-ahead instruction issue control
|Jan 24, 1989
|Jul 7, 1992
|Visual Information Technologies, Inc.
|High speed image processing computer
|Apr 8, 1991
|Aug 25, 1992
|Cray Research, Inc.
|Apparatus for sharing memory in a multiprocessor system
|Jan 24, 1989
|Sep 8, 1992
|Visual Information Technologies, Inc.
|High speed image processing computer with overlapping windows-div
|Mar 7, 1990
|Sep 8, 1992
|Hitachi, Ltd.
|System for fetching a plurality vector-data groups using a plurality of addressing device
|Nov 28, 1990
|Sep 29, 1992
|Cray Research, Inc.
|Method and apparatus for producing successive calculated results in a high-speed computer functional unit using low-speed VLSI components
|Mar 7, 1991
|Oct 27, 1992
|Convex Computer Corporation
|Multi-processor computer system having process-independent communication register addressing
|Mar 24, 1989
|Dec 1, 1992
|Digital Equipment Corporation
|Memory device for storing vector registers
|Nov 21, 1990
|Dec 8, 1992
|Cray Research, Inc.
|Vector bit-matrix multiply functional unit
|Jul 16, 1990
|Feb 16, 1993
|Computer Motion, Inc.
|Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units
|Oct 6, 1989
|Apr 6, 1993
|Nec Corporation
|Control system for transferring vector data without waiting for transfer end of the previous vector data
|Feb 13, 1992
|Apr 13, 1993
|Cray Research, Inc.
|Method for sharing memory in a multiprocessor system
|Jun 10, 1992
|Apr 13, 1993
|Supercomputer Systems Limited Partnership
|Method for optimizing instruction scheduling for a processor having multiple functional resources
|Sep 12, 1990
|Apr 27, 1993
|Cray Research, Inc.
|Fault tolerant networking architecture
|Sep 11, 1990
|Nov 9, 1993
|Digital Equipment Corporation
|Apparatus and method for single operand register array for vector and scalar data processing operations
|Oct 5, 1990
|Jan 18, 1994
|Bull Hn Information Systems Inc.
|State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections
|Jan 13, 1989
|Mar 15, 1994
|Hitachi, Ltd.
|Data storage device
|Nov 27, 1990
|Jul 5, 1994
|Cray Research, Inc.
|Disabled memory sections for degraded operation of a vector supercomputer
|Jul 10, 1991
|Jul 26, 1994
|Nec Corporation
|Advanced instruction execution system for assigning different indexes to instructions capable of parallel execution and same indexes to instructions incapable of parallel execution
|Jun 7, 1993
|Sep 20, 1994
|Nec Corporation
|Instruction handling sequence control system for simultaneous execution of vector instructions
|Apr 26, 1994
|Dec 6, 1994
|Cray Research, Inc.
|Apparatus and method for testing of new operating systems through priviledged instruction trapping
|Jun 22, 1992
|May 23, 1995
|Digital Equipment Corporation
|Digital computer system with cache controller coordinating both vector and scalar operations
|Feb 14, 1991
|Jul 18, 1995
|Cray Research, Inc.
|System for distributed multiprocessor communication
|Jan 21, 1994
|Nov 28, 1995
|Branigin; Michael H.
|Computer processor with an efficient means of executing many instructions simultaneously
|Mar 29, 1994
|Jan 2, 1996
|Cray Research, Inc.
|Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register
|Aug 8, 1991
|Mar 5, 1996
|Hitachi, Ltd.
|Vector data buffer and method of reading data items from a banked storage without changing the data sequence thereof
|Jun 27, 1994
|Mar 12, 1996
|Matsushita Electric Industrial Co., Ltd.
|Digital processor capable of concurrently executing external memory access and internal instructions
|Jun 6, 1995
|Mar 12, 1996
|Fujitsu Limited
|Vector data processing system with instruction synchronization
|Jan 25, 1993
|Mar 12, 1996
|Hitachi, Ltd.
|Input/output execution apparatus for a plural-OS run system
|Apr 26, 1993
|Apr 23, 1996
|Apple Computer, Inc.
|Polycyclic timing system and apparatus for pipelined computer operation
|Jan 27, 1995
|Jun 4, 1996
|Cray Research, Inc.
|Method and apparatus for accessing global registers in a multiprocessor system
|Feb 9, 1989
|Jun 11, 1996
|Cray Research, Inc.
|System for multiprocessor communication
|Jun 5, 1992
|Jun 25, 1996
|Hitachi, Ltd.
|Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs
|Feb 22, 1994
|Jul 30, 1996
|Nec Corporation
|Method for controlling vector data execution
|Jun 7, 1995
|Aug 6, 1996
|Cray Research, Inc.
|Vector processor having registers for control by vector resisters
|Mar 25, 1993
|Jan 28, 1997
|Texas Instruments Incorporated
|Circuitry and method for performing two operating instructions during a single clock in a processing device
|Jun 7, 1995
|Jan 28, 1997
|Cray Research, Inc.
|Vector processor having functional unit paths of differing pipeline lengths
|Mar 16, 1994
|Mar 18, 1997
|Matsushita Electric Industrial Co., Ltd.
|Data transfer device and multiprocessor system
|Jun 7, 1995
|Apr 22, 1997
|Cray Research, Inc.
|Method of processing a sequence of conditional vector IF statements
|Dec 1, 1994
|Apr 22, 1997
|Cray Research, Inc.
|Vector register validity indication to handle out-of-order element arrival for a vector computer with variable memory latency
|Feb 28, 1995
|Jun 17, 1997
|Cray Research, Inc.
|Method and apparatus for chaining vector instructions
|Dec 9, 1994
|Jul 15, 1997
|Vlsi Technology Inc.
|Microprocessor with instruction-cycle versus clock-frequency mode selection
|Jun 7, 1995
|Aug 19, 1997
|Cray Research, Inc.
|Vector/scalar processor with simultaneous processing and instruction cache filling
|Mar 19, 1991
|Jan 6, 1998
|The United States Of America As Represented By The Secretary Of The Navy
|Variable architecture computer with vector parallel processor and using instructions with variable length fields
|Jun 7, 1995
|Feb 10, 1998
|Cray Research, Inc.
|Data processing system for processing one and two parcel instructions
|Aug 22, 1994
|Apr 21, 1998
|Inmos Limited
|System for grouping instructions for multiple issue using plural decoders having forward and backward propagation of decoding information
|Feb 15, 1996
|Apr 21, 1998
|Fujitsu Limited
|Data processing apparatus for executing a vector operation under control of a master processor
|Apr 22, 1996
|Jun 16, 1998
|Fujitsu Limited
|Multiple bank structured memory access device having flexible setting of a pipeline stage number
|Nov 23, 1994
|Sep 1, 1998
|Cray Research, Inc.
|Outer loop vectorization
|Sep 13, 1996
|Sep 8, 1998
|International Computer Science Institute
|Vector processing system with multi-operation, run-time configurable pipelines
|Aug 30, 1995
|Dec 8, 1998
|Cray Research, Inc.
|Vector word shift by vo shift count in vector supercomputer processor
|Dec 9, 1996
|Jan 26, 1999
|International Business Machines Corporation
|Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding
|Oct 18, 1996
|Mar 30, 1999
|Elbrus International
|Array prefetch apparatus and method
|Sep 3, 1996
|Apr 20, 1999
|Cray Research, Inc.
|Virtual memory system for vector based computer systems
|Sep 11, 1997
|Jul 6, 1999
|Cray Research, Inc.
|System and method for distributed multiprocessor communications
|Sep 3, 1996
|Aug 17, 1999
|Cray Research, Inc.
|Density dependent vector mask operation control apparatus and method
|Oct 18, 1996
|Nov 9, 1999
|Elbrush International Limited
|Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups
|Dec 1, 1994
|Jan 4, 2000
|Cray Research, Inc.
|Computer having multiple address ports, each having logical address translation with base and limit memory management
|Aug 24, 1998
|Aug 1, 2000
|Cray Research, Inc.
|Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register
|Jan 10, 2000
|Jun 19, 2001
|Seiko Epson Corporation
|RISC microprocessor architecture implementing multiple typed register sets
|Oct 30, 1998
|Jul 17, 2001
|Nec Corporation
|Method of implementing vector operation using a processor chip which is provided with a vector unit
|Mar 5, 1999
|Jul 24, 2001
|Mips Technologies, Inc.
|Alignment and ordering of vector elements for single instruction multiple data processing
|Aug 2, 1999
|May 14, 2002
|International Business Machines Corporation
|Efficient non-contiguous I/O vector and strided data transfer in one sided communication on multiprocessor computers
|Jun 19, 1998
|Aug 6, 2002
|Hynix Semiconductor, Inc.
|Single precision array processor
|Mar 3, 1999
|Aug 20, 2002
|Computer Motion, Inc.
|Method and apparatus for performing minimally invasive surgical procedures
|Sep 22, 1994
|Oct 8, 2002
|Computer Motion, Inc.
|Speech interface for an automated endoscopic system
|Aug 6, 1996
|Nov 11, 2003
|Computer Motion, Inc.
|General purpose distributed operating room control system
|Apr 24, 2000
|Mar 2, 2004
|Computer Motion, Inc.
|Method and apparatus for performing minimally invasive surgical procedures
|Oct 26, 1998
|Mar 30, 2004
|Computer Motion, Inc.
|Head cursor control interface for an automated endoscope system for optimal positioning
|Aug 15, 2000
|Apr 27, 2004
|Computer Motion, Inc.
|Instrument guide
|Sep 7, 2001
|Apr 27, 2004
|Computer Motion, Inc.
|Modularity system for computer assisted surgery
|Jan 28, 2003
|May 25, 2004
|Nec Electronics, Inc.
|Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page
|Apr 24, 2003
|Aug 31, 2004
|Computer Motion, Inc.
|Modularity system for computer assisted surgery
|Dec 8, 2001
|Sep 21, 2004
|Computer Motion, Inc.
|Multifunctional handle for a medical robotic system
|Apr 24, 2003
|Sep 28, 2004
|Computer Motion, Inc.
|Modularity system for computer assisted surgery
|Nov 28, 2001
|Oct 12, 2004
|Computer Motion, Inc.
|Automated endoscope system for optimal positioning
|Apr 24, 2003
|Dec 28, 2004
|Computer Motion, Inc.
|Modularity system for computer assisted surgery
|Dec 7, 2001
|Jan 4, 2005
|Institute Surgical, Inc.
|Microwrist system for surgical procedures
|Jan 16, 2002
|Feb 8, 2005
|Computer Motion, Inc.
|Minimally invasive surgical training using robotics and tele-collaboration
|Dec 18, 1997
|Feb 8, 2005
|Hyundai Electronics America
|Video frame rendering engine
|Apr 24, 2003
|Mar 22, 2005
|Intuitive Surgical, Inc.
|Modularity system for computer assisted surgery
|Apr 17, 2003
|May 10, 2005
|Computer Motion, Inc.
|Modularity system for computer assisted surgery
|Mar 21, 2001
|May 31, 2005
|Apple Computer, Inc.
|Matrix multiplication in a vector processing system
|Dec 30, 1997
|Jun 14, 2005
|Intuitive Surgical, Inc.
|Apparatus for performing minimally invasive cardiac procedures with a robotic arm that has a passive joint and system which can decouple the robotic arm from the input device
|Sep 17, 2002
|Oct 4, 2005
|Intuitive Surgical, Inc.
|Tele-medicine system that transmits an entire state of a subsystem
|Mar 11, 2002
|Nov 15, 2005
|Computer Motion, Inc.
|Speech interface for an automated endoscopic system
|May 8, 2001
|Apr 11, 2006
|Seiko Epson Corporation
|High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
|Sep 18, 2003
|May 30, 2006
|Intuitive Surgical
|General purpose distributed operating room control system
|Dec 15, 1999
|Jun 13, 2006
|Matsushita Electric Industrial Co., Ltd.
|Conditional vector arithmetic method and conditional vector arithmetic unit
|Sep 10, 2002
|Jul 11, 2006
|Intuitive Surgical Inc
|Method and apparatus for performing minimally invasive cardiac procedures
|Dec 15, 2003
|Aug 1, 2006
|Intuitive Surgical
|Medical robotic arm that is attached to an operating table
|Feb 23, 2001
|Aug 8, 2006
|Fujitsu Limited
|Packet processing device processing input packet data in a packet routing device
|Nov 26, 2003
|Aug 29, 2006
|Intuitive Surgical, Inc.
|Multi-functional surgical control system and switching interface
|Sep 8, 2003
|Aug 29, 2006
|Motorola, Inc.
|Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values
|Sep 8, 2003
|Sep 12, 2006
|Freescale Semiconductor, Inc.
|Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect
|Oct 8, 1998
|Oct 10, 2006
|Computer Motion, Inc.
|Method and apparatus for performing minimally invasive cardiac procedures
|Jun 28, 2002
|Nov 21, 2006
|Motorola, Inc.
|Scheduler of program instructions for streaming vector processor having interconnected functional units
|Jun 28, 2002
|Jan 2, 2007
|Motorola, Inc.
|Streaming vector processor with reconfigurable interconnection switch
|Dec 30, 1998
|Jan 2, 2007
|Mips Technologies, Inc.
|Method for providing extended precision in SIMD vector arithmetic operations
|Dec 20, 2002
|Feb 20, 2007
|Dotcast, Inc.
|Joint adaptive optimization of soft decision device and feedback equalizer
|Feb 21, 2001
|Feb 20, 2007
|Mips Technologies, Inc.
|Extended-precision accumulation of multiplier output
|Mar 31, 2004
|Mar 27, 2007
|Sony Corporation
|Parallel vector processing
|Sep 15, 2000
|Mar 27, 2007
|Mips Technologies, Inc.
|Alignment and ordering of vector elements for single instruction multiple data processing
|Jul 14, 2004
|May 15, 2007
|Intuitive Surgical, Inc.
|Heart stabilizer
|Jul 16, 2002
|May 29, 2007
|Mips Technologies, Inc.
|Extended precision accumulator
|Jan 6, 2005
|Jul 3, 2007
|Intuitive Surgical, Inc
|Modularity system for computer assisted surgery
|Jun 23, 2005
|Aug 21, 2007
|Intuitive Surgical, Inc.
|General purpose distributed operating room control system
|Sep 8, 2003
|Sep 25, 2007
|Freescale Semiconductor, Inc.
|Data processing system using multiple addressing modes for SIMD operations and method thereof
|Jun 24, 2004
|Oct 16, 2007
|International Business Machines Corporation
|Digital data processing apparatus having multi-level register file
|Aug 29, 2003
|Oct 30, 2007
|Motorola, Inc.
|Dataflow graph compression for power reduction in a vector processor
|Nov 25, 2003
|Nov 20, 2007
|Agere Systems Inc.
|Vector indexed memory unit and method
|Sep 8, 2003
|Jan 1, 2008
|Moyer William C
|Data processing system having instruction specifiers for SIMD register operands and method thereof
|Aug 9, 2002
|Feb 19, 2008
|Dotcast, Inc.
|Expanded information capacity for existing communication transmission systems
|Apr 25, 2005
|Feb 26, 2008
|Apple Inc.
|Matrix multiplication in a vector processing system
|Sep 16, 2004
|Jul 1, 2008
|Intuitive Surgical, Inc.
|Speech interface for an automated endoscope system
|Sep 3, 2004
|Aug 5, 2008
|Intuitive Surgical, Inc.
|Method and apparatus for accessing medical data over a network
|Sep 23, 2004
|Aug 19, 2008
|Intuitive Surgical, Inc.
|Minimally invasive surgical training using robotics and telecollaboration
|Aug 29, 2003
|Aug 19, 2008
|Motorola, Inc.
|Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
|Dec 11, 2002
|Mar 24, 2009
|Intuitive Surgical, Inc.
|Method and apparatus for performing minimally invasive cardiac procedures
|Dec 21, 2006
|Apr 7, 2009
|Seiko Epson Corporation
|System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
|Jun 10, 2005
|Apr 21, 2009
|Seiko Epson Corporation
|System and method for handling exceptions and branch mispredictions in a superscalar microprocessor
|Jun 21, 2006
|Jun 9, 2009
|Intuitive Surgical, Inc.
|Multi-functional surgical control system switching interface
|Jan 24, 2006
|Jun 9, 2009
|Mips Technologies, Inc.
|Providing extended precision in SIMD vector arithmetic operations
|Jan 31, 2002
|Jun 30, 2009
|Sanjiv Garg
|RISC microprocessor architecture implementing multiple typed register sets
|Dec 27, 2005
|Jun 30, 2009
|Seiko Epson Corporation
|High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
|Sep 27, 2005
|Jul 7, 2009
|Seiko Epson Corporation
|System and method for register renaming
|Feb 19, 2004
|Aug 25, 2009
|Endres Thomas J
|Joint, adaptive control of equalization, synchronization, and gain in a digital communications receiver
|May 21, 2004
|Aug 25, 2009
|Nintendo Co., Ltd.
|Method and apparatus for efficient loading and storing of vectors
|Feb 21, 2001
|Oct 6, 2009
|Mips Technologies, Inc.
|Binary polynomial multiplier
|Sep 5, 2003
|Oct 27, 2009
|Freescale Semiconductor, Inc.
|Data processing system using independent memory and register operand size specifiers and method thereof
|Dec 22, 2006
|Nov 10, 2009
|Mips Technologies, Inc.
|Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution
|Jul 5, 2005
|Dec 1, 2009
|Qualcomm Incorporated
|Methods and apparatus for encoding LDPC codes
|May 19, 2005
|Mar 23, 2010
|Intuitive Surgical, Inc.
|Tele-medicine system that transmits an entire state of a subsystem
|Jan 9, 2007
|Mar 23, 2010
|Sanjiv Garg
|RISC microprocessor architecture implementing multiple typed register sets
|Jul 17, 2006
|Apr 13, 2010
|Intuitive Surgical, Inc.
|Medical robotic system with different scaling factors
|Feb 21, 2001
|May 4, 2010
|Mips Technologies, Inc.
|Microprocessor instructions for performing polynomial arithmetic operations
|Dec 21, 2006
|Jun 15, 2010
|Seiko Epson Corporation
|High-performance, superscalar-based computer system with out-of-order instruction execution
|Feb 6, 2007
|Sep 7, 2010
|Mips Technologies, Inc.
|Alignment and ordering of vector elements for single instruction multiple data processing
|Apr 2, 2007
|Sep 21, 2010
|Sanjiv Garg
|Superscalar RISC instruction scheduling
|Apr 25, 2006
|Dec 28, 2010
|Mips Technologies, Inc.
|Extended precision accumulator
|Dec 27, 2005
|Mar 29, 2011
|Intuitive Surgical Operations, Inc.
|Method and apparatus for performing minimally invasive cardiac procedures
|Sep 17, 2008
|Apr 26, 2011
|Seiko Epson Corporation
|System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
|Dec 19, 2006
|May 10, 2011
|Seiko-Epson Corporation
|High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution
|Dec 31, 2009
|May 10, 2011
|Intellectual Venture Funding Llc
|RISC microprocessor architecture implementing multiple typed register sets
|Jun 5, 2008
|May 17, 2011
|Motorola Mobility, Inc.
|Method and apparatus for nested instruction looping using implicit predicates
|Feb 26, 2009
|Jun 7, 2011
|Seiko Epson Corporation
|System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
|May 26, 2009
|Jul 12, 2011
|Seiko Epson Corporation
|System and method for register renaming
|Jan 16, 2004
|Jul 26, 2011
|Microunity Systems Engineering, Inc.
|Multithreaded programmable processor and system with partitioned operations
|Jan 16, 2004
|Aug 16, 2011
|Microunity Systems Engineering, Inc.
|Method and software for partitioned group element selection operation
|Aug 18, 2004
|Aug 23, 2011
|Intuitive Surgical Operations, Inc.
|Multifunctional handle for a medical robotic system
|Sep 15, 2008
|Dec 6, 2011
|Seiko Epson Corporation
|System and method for assigning tags to control instruction processing in a superscalar processor
|Jun 8, 2009
|Dec 6, 2011
|Mips Technologies, Inc.
|Providing extended precision in SIMD vector arithmetic operations
|Aug 5, 2008
|Jan 10, 2012
|Convey Computer
|Memory interleave for heterogeneous computing
|Sep 12, 2007
|Feb 21, 2012
|Convey Computer
|Dispatch mechanism for dispatching instructions from a host processor to a co-processor
|Aug 20, 2007
|Apr 10, 2012
|Convey Computer
|Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
|Aug 24, 2009
|Jun 5, 2012
|Omereen Wireless, Llc
|Joint, adaptive control of equalization, synchronization, and gain in a digital communications receiver
|Oct 31, 2008
|Jun 19, 2012
|Convey Computer
|Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor
|Nov 16, 2009
|Apr 16, 2013
|Convey Computer
|Systems and methods for mapping a neighborhood of data to general registers of a processing element
|Dec 5, 2011
|May 14, 2013
|Convey Computer
|Memory interleave for heterogeneous computing
|Mar 6, 2009
|May 21, 2013
|Bridge Crossing, Llc
|Substituting portion of template instruction parameter with selected virtual instruction parameter
|Jun 12, 2009
|Jun 4, 2013
|Cray Inc.
|Vector atomic memory operation vector update system and method
|Dec 3, 2010
|Jul 16, 2013
|Intuitive Surgical Operations, Inc.
|Cooperative minimally invasive telesurgical system
|Nov 18, 2011
|Aug 6, 2013
|Intuitive Sugrical Operations, Inc.
|Cooperative minimally invasive telesurgical system
|Dec 27, 2005
|Sep 3, 2013
|Intuitive Surgical Operations, Inc.
|Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures
|Aug 29, 2007
|Oct 15, 2013
|Convey Computer
|Compiler for generating an executable comprising instructions for a plurality of different instruction sets
|Jun 12, 2009
|Nov 12, 2013
|Cray Inc.
|System and method for managing processor-in-memory (PIM) operations
|Feb 17, 2006
|Feb 4, 2014
|Intuitive Surgical Operations, Inc.
|Pivot point arm for robotic system used to perform a surgical procedure
|Jul 10, 2013
|Mar 4, 2014
|Intuitive Surgical Operations, Inc.
|Cooperative minimally invasive telesurgical system
|Jun 11, 2012
|Mar 25, 2014
|Microunity Systems Engineering, Inc.
|System and apparatus for group floating-point inflate and deflate operations
|Nov 17, 2009
|Jun 10, 2014
|Qualcomm Incorporated
|Methods and apparatus for encoding LDPC codes
|Jun 11, 2012
|Jul 1, 2014
|Microunity Systems Engineering, Inc.
|System and apparatus for group floating-point inflate and deflate operations
|Aug 8, 2007
|Jul 29, 2014
|International Business Machines Corporation
|Digital data processing apparatus having multi-level register file
|Jun 12, 2009
|Sep 2, 2014
|Cray Inc.
|Using vector atomic memory operation to handle data of different lengths
|Oct 3, 2012
|Sep 30, 2014
|Intuitive Surgical Operations, Inc.
|Rigidly-linked articulating wrist with decoupled motion transmission
|Mar 21, 2007
|Oct 28, 2014
|Intuitive Surgical Operations, Inc.
|Endoscopic beating-heart stabilizer and vessel occlusion fastener
|Jan 24, 2014
|Dec 16, 2014
|Intuitive Surgical Operations, Inc.
|Cooperative minimally invasive telesurgical system
|Jun 10, 2011
|Jan 27, 2015
|Intuitive Surgical Operations, Inc.
|Multifunctional handle for a medical robotic system
|Dec 31, 2013
|Apr 21, 2015
|Intuitive Surgical Operations, Inc.
|Pivot point arm for a robotic system used to perform a surgical procedure
|Aug 5, 2008
|Apr 21, 2015
|Convey Computer
|Multiple data channel memory module architecture
|Jul 16, 2008
|May 26, 2015
|Intuitive Surgical Operations, Inc.
|Minimally invasive surgical training using robotics and telecollaboration
|Jan 13, 2012
|Sep 1, 2015
|Intuitive Surgical Operations, Inc.
|Stabilizer for robotic beating-heart surgery
|May 8, 2001
|Feb 7, 2002
|Nguyen Le Trong
|High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
|Feb 23, 2001
|Feb 7, 2002
|Yuji Kojima
|Packet processing device
|Dec 30, 1998
|May 23, 2002
|Timothy J. Van Hook
|Method for providing extended precision in simd vector arithmetic operations
|Feb 21, 2001
|Aug 22, 2002
|Morten Strjbaek
|Extended precision accumulator
|Jul 16, 2002
|Nov 28, 2002
|Mips Technologies, Inc., A Delaware Corporation
|Extended precision accumulator
|Jan 31, 2002
|Jun 19, 2003
|Sanjiv Garg
|RISC microprocessor architecture implementing multiple typed register sets
|Jan 28, 2003
|Sep 4, 2003
|Nec Electronics, Inc.
|Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page
|Feb 13, 2003
|Nov 27, 2003
|Simovich Slobodan A.
|Configurable stream processor apparatus and methods
|Jun 28, 2002
|Jan 1, 2004
|May Philip E.
|Streaming vector processor with reconfigurable interconnection switch
|Jun 28, 2002
|Jan 1, 2004
|May Philip E.
|Scheduler for streaming vector processor
|Sep 8, 2003
|Jun 17, 2004
|Norris James M.
|Partitioned vector processing
|Aug 29, 2003
|Jul 1, 2004
|May Philip E.
|Method and apparatus for elimination of prolog and epilog instructions in a vector processor
|Nov 25, 2003
|Aug 5, 2004
|Rainer Buchty
|Vector indexed memory unit and method
|Jan 16, 2004
|Aug 5, 2004
|Microunity Systems Engineering, Inc.
|Method and software for partitioned group element selection operation
|May 21, 2004
|Jan 27, 2005
|Nintendo Co., Ltd.
|Method and apparatus for efficient loading and storing of vectors
|Aug 29, 2003
|Mar 3, 2005
|May Philip E.
|Dataflow graph compression for power reduction in a vector processor
|Sep 8, 2003
|Mar 10, 2005
|Moyer William C.
|Data processing system having instruction specifiers for SIMD register operands and method thereof
|Sep 8, 2003
|Mar 10, 2005
|Moyer William C.
|Data processing system having instruction specifiers for SIMD operations and method thereof
|Sep 8, 2003
|Mar 10, 2005
|Moyer William C.
|Data processing system using multiple addressing modes for SIMD operations and method thereof
|Sep 5, 2003
|Mar 10, 2005
|Moyer William C.
|Data processing system using independent memory and register operand size specifiers and method thereof
|Apr 25, 2005
|Sep 1, 2005
|Apple Computer Inc.
|Matrix multiplication in a vector processing system
|Mar 31, 2004
|Oct 6, 2005
|Mikhail Dorojevets
|Parallel vector processing
|Mar 31, 2004
|Oct 13, 2005
|Mikhail Dorojevets
|2D block processing architecture
|Jul 5, 2005
|Nov 3, 2005
|Hui Jin
|Methods and apparatus for encoding LDPC codes
|Jun 24, 2004
|Dec 29, 2005
|International Business Machines Corporation
|Digital data processing apparatus having multi-level register file
|May 19, 2005
|Mar 2, 2006
|Modjtaba Ghodoussi
|Tele-medicine system that transmits an entire state of a subsystem
|Feb 21, 2001
|Aug 24, 2006
|Ekner Hartvig W
|Binary polynomial multiplier
|Feb 6, 2007
|Aug 9, 2007
|Boris Prokopenko
|Stream Processor with Variable Single Instruction Multiple Data (SIMD) Factor and Common Special Function
|Feb 6, 2007
|Oct 25, 2007
|Mips Technologies, Inc.
|Alignment and ordering of vector elements for single instruction multiple data processing
|Sep 12, 2007
|Mar 12, 2009
|Convey Computer
|Dispatch mechanism for dispatching insturctions from a host processor to a co-processor
|Jun 8, 2009
|Oct 1, 2009
|Mips Technologies, Inc.
|Providing Extended Precision in SIMD Vector Arithmetic Operations
|Jun 5, 2008
|Dec 10, 2009
|Motorola, Inc.
|Method and Apparatus for Nested Instruction Looping Using Implicit Predicates
|Feb 11, 2010
|Convey Computer
|Memory interleave for heterogeneous computing
|Oct 31, 2008
|May 6, 2010
|Johnson Timothy J
|Large integer support in vector operations
|Oct 31, 2008
|May 6, 2010
|Convey Computer
|Dynamically-selectable vector register partitioning
|Oct 31, 2008
|May 6, 2010
|Convey Computer
|Co-processor infrastructure supporting dynamically-modifiable personalities
|Nov 17, 2009
|Jun 17, 2010
|Qualcomm Incorporated
|Methods and apparatus for encoding ldpc codes
|Jun 12, 2009
|Dec 16, 2010
|Cray Inc.
|System and method for managing processor-in-memory (pim) operations
|Jun 12, 2009
|Dec 16, 2010
|Cray Inc.
|Using vector atomic memory operation to handle data of different lengths
|Jun 12, 2009
|Dec 16, 2010
|Cray Inc.
|Vector atomic memory operation vector update system and method
|Oct 4, 2012
|Jesus Corbal San Adrian
|Systems, apparatuses, and methods for blending two source operands into a single destination using a writemask
|Feb 20, 2009
|Jul 19, 2011
|Omereen Wireless, Llc
|Joint adaptive optimization of soft decision device and feedback equalizer
|Aug 30, 2004
|Apr 22, 2009
|Data processing system for implementing SIMD operations and method thereof
|Dec 27, 1982
|Aug 18, 1983
|Hitachi Ltd
|May 24, 1985
|Nov 28, 1985
|Hitachi Ltd
|Datenverarbeitungsvorrichtung und verfahren und vorrichtung zur umsetzung von datenelementen
|Jul 21, 1981
|Jan 27, 1982
|Hitachi, Ltd.
|Vector data processor
|Feb 3, 1983
|Aug 10, 1983
|Hitachi, Ltd.
|Array processor comprised of vector processors using vector registers
|Dec 15, 1983
|Aug 1, 1984
|International Business Machines Corporation
|Vector processing hardware assist and method
|Apr 18, 1984
|Oct 31, 1984
|Cray Research, Inc.
|Computer vector multiprocessing control
|Jul 1, 1985
|Jan 15, 1986
|Nec Corporation
|Computer vector register processing
|Jul 11, 1985
|Jan 22, 1986
|Nec Corporation
|Data processing circuit for calculating either a total sum or a total product of a series of data at a high speed
|Jun 16, 1986
|Dec 17, 1986
|Nec Corporation
|Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
|Jul 31, 1986
|Feb 25, 1987
|Unisys Corporation
|A scientific processor
|Feb 11, 1987
|Sep 9, 1987
|Scientific Computer Systems Corporation
|Bi-directional databus system for supporting superposition of vector and scalar operations in a computer
|Feb 11, 1987
|Sep 16, 1987
|Scientific Computer Systems Corporation
|Backplane structure for a computer superpositioning scalar and vector operations
|May 9, 1989
|Dec 27, 1989
|International Business Machines Corporation
|Computing sequence result availability
|Dec 15, 1999
|Apr 17, 2002
|Matsushita Electronics Corporation
|Conditional vector operation method and device thereof
|Mar 15, 1989
|Oct 5, 1989
|Digital Equipment Corp
|Method and apparatus for executing instructions for a vector processing system
|Aug 30, 2004
|Mar 24, 2005
|Freescale Semiconductor Inc
|Data processing system for implementing simd operations and method thereof
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Jun 28, 2000
|Apr 27, 2001
|May 9, 2001
|Dec 31, 2001
|Aug 24, 2005
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