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USA Travel thread #30
Started by Therese , Nov 15 2012 12:00 PM
148 replies to this topic
Posted 15 November 2012 - 12:00 PM
New thread time
Your last thread is Here
Posted 15 November 2012 - 12:33 PM
kee - great news about your DH, i am so happy for him and you.
and also great news about your parents going with you.
my mum isnt the best with flying (she does go from nsw to qld a few times a year now so that is an improvement). when she was younger she lived in New Zealdand for 10 years. i would really love to take her back there and visit her friends. her closet friend there has said that she wouldnt fly over to sydney again, so i keep telling mum she has to go and visit her. DD may get an opportunity to go to new zealand (im keeping everything crossed) in january 2014 so we have mentioned to mum that if we did go she would just HAVE to come with us.
i am suprised as she is really excited.
DH thought it was ok as well.
if we dont get the opportunity to go in that january, maybe i will just have to organise a trip for her and we tag along.
i think she was happier if she had some company on the plane ride.
sorry i now that was a ramble and off the subject of the USA
jo - we stayed at the aston kaanapali shores in september this year and loved it. anything you need to know about the tours etc i will be happy to answer and shed the information we found.
Edited by FionaM, 15 November 2012 - 12:39 PM.
Posted 15 November 2012 - 12:37 PM
So happy for you and DH kee
Posted 15 November 2012 - 05:31 PM
Thanks girls. Unfortunately today has gone from great to awful. My awesome, amazing Dad had a heart attack at work and passed away earlier today. I keep thinking it's not real because he's meant to be coming on the cruise with us. I tragically came to my parents house today to bring them their cruise confirmation paperwork which was emailed to me this morning. I walked in to the police and Dad's boss breaking the news to Mum.
I don't even know what to do about the cruise now, I can't think straight.
Posted 15 November 2012 - 05:35 PM
Kee that is horrible. I am so sorry to hear such horrible news. Thinking of you at this sad time xx
Posted 15 November 2012 - 06:00 PM
Oh Kee, I'm so very sorry. Thinking of you and your Mum and family.
Posted 15 November 2012 - 06:35 PM
I am so very sorry to hear that Kee. You and your family are in my thoughts!
Posted 15 November 2012 - 06:42 PM
Kee, that is tragic, horrible news. I was catching up on the US travel threads earlier today, and read how excited you were that your parents had decided to travel with you on your cruise. What a truly devastating turn of events. My deepest condolences to you and your family.
Posted 15 November 2012 - 06:42 PM
OH Kee!!! I am so sorry to hear about your Dad. You are in my thoughts during this hard time.
Posted 15 November 2012 - 07:32 PM
OMG Kee I have no words I'm in tears for you, your Mum & Dad sound so fantastic and amazing from everything that you've said about them. I'm so so sorry
Posted 15 November 2012 - 07:56 PM
So sorry to hear about your Dad Kee.
Posted 15 November 2012 - 08:08 PM
Oh, Kee:( So sorry to hear about your dad.
Oh, Kee:( So sorry to hear about your dad.
Posted 15 November 2012 - 08:14 PM
Oh kee im so sorry for the loss of your dad,may he rest in peace
Posted 15 November 2012 - 08:22 PM
Kee oh hon, I am so sorry. I have loved reading and living thru your passions for travel and how you have loved to share with your family and us here. Your Dad sounded like he was game for a go and to try anything you put him up to. It will be hard in the short term but you will get through it, I know my dad passed away six years ago this Xmas, but you will get up each morning and make it through the day. You are a strong woman who I am sure he was very proud of and we will be here for you. This thread is full of amazing chicks, you are gold girl! Sending you all you need.
Posted 15 November 2012 - 09:28 PM
Kee I am so sorry for your loss.....
Posted 16 November 2012 - 05:42 AM
Omg Kee! How awful and shocking. I had to read your post twice I couldn't quite believe it. My thoughts are with you and your poor mum. So very sorry for your loss.
Posted 16 November 2012 - 06:29 AM
Kee - I'm so sorry to hear about your Dad, my sincere condolences to you and all those who loved him.
I read the posts you wrote the other day about the holidays you and your DH had with your parents recently in Hawaii, what wonderful memories to treasure.
Posted 16 November 2012 - 07:35 AM
so sorry to hear your tragic news Kee - condolences to you and your family.
Posted 16 November 2012 - 08:58 AM
Ohh Kee - how terrible and heartbreaking for you and all your family. Thoughts and prayers are with you at this hard time.
Posted 16 November 2012 - 09:03 AM
I am so sorry Kee for the loss of your wonderful dad. You are in my thoughts.
Posted 16 November 2012 - 09:38 AM
So sorry Kee to hear the news of your Dad. Thinking of you and your family.
Posted 16 November 2012 - 10:02 AM
Kee, I'm really sorry about your dad...
Posted 16 November 2012 - 11:21 AM
I'm thinking of you Kee at this sad time.
Posted 16 November 2012 - 01:04 PM
Kee so sorry to read your awful news....
Posted 16 November 2012 - 04:43 PM
Thinking of you and your family Kee xo
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Sitter in 1 portrait
by Camille Silvy
Vere Fane-Benett (né Fane, later Fane-Benett-Stanford)(1839-1894), Politician and Lieutenant-Colonel
Sitter in 1 portrait
Vere Fane-Benett (né Fane, later Fane-Benett-Stanford)
by Camille Silvy
albumen print, 8 July 1861
NPG Ax54826
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That's it. There are just some last touches on the script, a little more copy editing and correcting translations and tomorrow a year's worth of writing is ready for 30 busy and pressured days of filming. As always when I finish a writing project, the tears begin on their own. I finish writing, know that I have completed the main part of my job and I simply start crying for weeks on end. It began a few...
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Phuket Gazette - 2015-10-10 11:51 AM
With only a week left, Isaac has some serious running around to do to achieve his 6-week 6-pack. First it's off to Land & House to check in with the Vitruvian Method's Craig and Krix, then a dash down to Rawai for some electrical rewiring to fix his posture and finally he's back to the Phuket Country Home pool for some swim training with Krix's older - and much better looking - sister, Davina Luther.
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Which new initiative will have the greatest short-term impact on public transportation in Phuket?
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Which new initiative will have the greatest short-term impact on public transportation in Phuket?
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The Phuket Gazette Co Ltd
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The city said it rejected the test scores because they were discriminatory, as all but one of the candidates who qualified were white.
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Justice Samuel A. Alito Jr. was hammered on his reported membership in the Concerned Alumni of Princeton, a group that opposed affirmative action policies at the Ivy League school.
Justice Ruth Bader Ginsburg's work for the ACLU and other women's rights groups became a point of contention during her 1993 confirmation hearings among senators who questioned her ability to be impartial.
Judge Sotomayor's confirmation hearing is scheduled to start in the Senate Judiciary Committee on July 13.


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|Publication number
|Publication type
|Application number
|Publication date
|Jul 6, 1999
|Filing date
|Sep 2, 1997
|Priority date
|Sep 2, 1997
|Fee status
|Publication number
|Tam-Anh Chu
|Original Assignee
|Acorn Networks, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (3), Non-Patent Citations (2), Referenced by (42), Classifications (4), Legal Events (7)
|External Links: USPTO, USPTO Assignment, Espacenet
The research involved in this application was funded in part by the Naval Research Laboratory, contract number N00014-95-C-2216, dated Aug. 28, 1995. The intellectual property rights of the applicant and the government of the United States of America are governed by Title 37 Code of Federal Regulations Part 401.
1. Field of the Invention
The present invention relates to electronic pipelines, more specifically, to pipelines in which data is transferred between internal stages asynchronously.
2. The Prior Art
Pipelining is a process by which an operation is separated into stages, where each stage is an independent component of the operation. Each stage of a pipeline operates on data passed to it from the previous stage, and when complete, passes the result to the next stage. Pipelining thus allows independent components of an operation to be performed concurrently, increasing throughput. The simplest example of a pipeline is the first-in/first-out buffer, or FIFO, which is used to transfer data between two independent devices in a way that maintains the independence of the devices. The FIFO stores the output from one device until needed by the next device, assuring that the data is received in the same order that it is generated. The first device stores its output in the FIFO at the rate it is generated, and the second device reads its input from the FIFO when needed, effectively coupling the two devices together with respect to data, but decoupling them with respect to timing. An important application for FIFOs is in the interface between a processor and a disk drive. The processor generates data to be written to the disk in infrequent, but high-speed bursts, and disk drive writes the data at a much slower, albeit steady, rate. Another important application for FIFOs is in data communication, where there is a need to buffer data between two systems that operate at different speeds.
A pipeline can be implemented to operate either synchronously or asynchronously. In synchronous operation, data movement from each stage of the pipeline to the next is controlled by a single global clock. In asynchronous operation, data movement between stages is controlled by a local handshake operation. When a stage has data ready for the next stage, it sends a request to that stage, and when that stage accepts the data, it returns an acknowledgement. There are a number of advantages that asynchronous pipelines have over synchronous pipelines. In a synchronous pipeline, it is assumed that the processing time of every stage is no greater than the time period of the clock. Consequently, the pipeline operates at the speed of the slowest stage, reflecting the worst-case time for the operation to complete. On the other hand, each stage of an asynchronous pipeline transfers data when ready, reflecting the average time for the operation to complete.
In a synchronous pipeline, the fastest speed is obtained when the clock period is as close as possible to the speed of the slowest stage. Careful planning and design are required to provide proper control to each stage. The physical layout of the pipeline must be designed to minimize the difference in time that the clock reaches all stages. The greater the difference, the slower the clock must be to accommodate the difference, resulting in slower operation. In an asynchronous pipeline, data transfer between stages is controlled locally, without dependence upon the other stages.
In a synchronous pipeline, the clock must always be active, so the stages are always active, consuming power. The clock can only be shut off with careful timing and after significant latencies. On the other hand, when there is no input data, an asynchronous pipeline ceases operation completely, consuming no power in typical designs. For high-speed designs that use a large number of pipelines, the power savings can be significant.
The design of an asynchronous pipeline is based on the serial connection of a number of pipeline stages, as shown in the four-stage pipeline 100 of FIG. 1. Each stage 102 includes a registered data path 104 and a stage controller 106. In the simple case of a FIFO, the registered data path 104 reduces to a data register 108. Each data register 108 has a number of identical cells 110, one for each bit in the width of the data, typically an integral power of 2, such as 8, 16, 32, or 64 bits. Unless specifically stated otherwise, all further references in this specification to a data register means a reference to all of the cells of the data register. Data enters the first stage data register 108 through the entry port DIN and is sequentially transferred from one data register 108 to the next until it is available as output data at the output port DOUT.
Data moves into and out of a stage 102 under the control of the stage controller 106. The stage controller 106 generates a load signal L to the data register 108, causing the data register 108 to latch the data at its input DI. A short time later, represented by the propagation delay through the data register 108, the data becomes available at the register output DO. The data transfer is coordinated by a pair of handshake signals between stage controllers 106 of adjacent stages 102. The signal pair include a request signal R and an acknowledge signal A. Together they form a closed-loop communication between two adjacent stages. Basically, when a stage 102 has data available at its output DO, it asserts the request signal R. When the succeeding stage has accepted the data, it asserts the acknowledge signal A.
There are two protocols used to transfer data between stages, four-cycle signaling and two-cycle signaling, shown in the timing diagrams of FIGS. 2a and 2b, respectively. In four cycle signaling, a signal is always asserted by the same transition of the signal line, illustrated as a low-to-high transition in FIG. 2a. After the data is available from the sender, the sender changes R from low to high. The receiver acknowledges the data by changing A from low to high. Upon receiving the low-to-high acknowledgement, the sender resets the R to low, and upon seeing R go low, the receiver resets A to low. The term four-cycle refers to the fact that there are four transitions of the two signal lines during a transfer.
In two-cycle signaling, a signal is asserted by any transition of the signal line, called an event. After data is available from the sender, the sender changes the state of R, either from low-to-high or from high-to-low, causing an event on R. The receiver acknowledges receipt of data by changing A to its opposite state, causing an event on A. No other transitions of R and A are involved. Two-cycle signaling is potentially twice as fast as four-cycle signaling, the expense being a more complicated circuit implementation. Thus, for maximum throughput of a pipeline, two-cycle timing is preferred.
A block diagram of a pipeline stage 120 with a two-cycle stage controller 122 is shown in FIG. 3 and the associated timing diagram is shown in FIG. 4. The nomenclature used in the art is that the input request signal is RI, its associated acknowledge signal is AI, the output request signal is RO, and its associated acknowledge signal is AO. The stage controller has a latch 126 to generate RO, a latch 128 to generate AI, and a logic circuit 130 to generate L for the data register 124. A cycle begins by an event on RI. If there is no data in the data register 124, as indicated by an AO event in the previous cycle, the RI event causes L to be asserted, latching the data DI from the previous stage into the data register 124. The RI event also causes an event on RO, signaling to the next stage that the data DO at the output of the data register 124 is available. The RO event causes L to be deasserted, which, in turn, causes an event on AI, indicating to the previous stage that its data DI has been accepted, and terminating the cycle. Meanwhile, the next stage has acknowledged the RO event by an event on AO. The next cycle begins by a RI event, but this does not cause L to be asserted until the data DO has been read by the next stage, indicated by an AO event in the previous cycle.
The throughput of a single stage of a two-cycle asynchronous FIFO is 1/TCYCLE, where TCYCLE is the maximum of the delays between consecutive events on RI, AI, RO, and AO, that is
TCYCLE =max(TRI, TAI, TRO, TAO)
where TRI, TAI, TRO, TAO represent the greater of the positive transition time and the negative transition time of each signal. Thus, to increase the throughput of the pipeline, TCYCLE must be decreased.
In most state-of-the-art pipelines 140, a single stage of which is shown in FIG. 5, the width of the data register 142 can be large, 64, 128, or more bits. For each one of these bits, the data register 142 includes a data register cell 144 to hold the data. Each of these cells 144 must be driven by the load signal L in order to latch in the data. Because of the large number of loads on L, a buffer 146 is needed to provide adequate rise and fall times for the load signal LB.
The timing diagram for the FIFO of FIG. 5 is shown in FIG. 6. To guarantee that the data DIN has been successfully loaded into the data register 142, the buffered load signal LB, rather than the unbuffered load signal LU, is monitored, and AI and RO are issued only after LB has indicated that data DIN has been safely latched into the data register 142. This introduces an extra delay TB to TCYCLE, which adversely affects the throughput of the system.
A typical FIFO includes a 64-bit-wide register and uses 0.5 micrometer CMOS technology. In this system, TCYCLE, when excluding TB, is approximately 3 nanoseconds (ns) which results in a throughput of approximately 333 MHz. The buffer needed to drive a 64-bit register has a delay TB of approximately 3 ns. This buffer delay essentially doubles TCYCLE, from 3 ns to 6 ns, resulting in a 50% reduction in throughput from 333 MHz to 167 MHz. This situation will not improve with future submicrometer technologies because wire delays will become a more significant factor in the total delay TCYCLE and because data paths will increase in width, requiring buffers with greater drive capability and the resulting greater buffer delays. The time needed to load data into a data register will remain at approximately 50% of total cycle time.
An object of the present invention is to provide a pipeline that increases overall throughput significantly over those of the prior art.
Another object is to provide a pipeline that moves data through empty stages faster than in pipelines of the prior art.
Yet another object is to provide a pipeline that minimizes the amount of time that the source device is forced to wait before writing data to the pipeline.
The present invention is an asynchronous pipeline that maximizes throughput. When the first stage of a pipeline is full, the source device must wait to write the next piece of data into the pipeline. The pipeline of the present invention seeks to minimize this wait by emptying the first stage into the second stage, and so on, as fast as possible so that the source can write its next piece of data into the first stage as soon as possible.
The present invention essentially divides the pipeline into separate data and signal chains by moving the data register load signal buffer outside of the closed loop that generates AI and RO. Consequently, LB is no longer used in the handshake timing, but merely synchronizes the data chain with the signal chains.
When data is available from the previous stage, it causes an event on RI, which, assuming that the next stage is empty, generates an event on RO a time interval TC later. The RO event causes a circuit to generate a pulse on the data register load signal LU, causing the buffered load signal LB to pulse a time interval TZ after RO, latching the data into the data register. The output data is available a time interval TD after the buffered load signal LB. Finally, the trailing edge of LU causes an event on AI, indicating to the previous stage that the data has been accepted. As can be seen, the RO event occurs TZ +TD before the output data is actually available, which is a violation of asynchronous handshake timing requirements. This violation is inconsequential as long as the last stage of the pipeline makes the output data available before causing an RO event.
At the internal stages of the pipeline, delay matching of the stages is the key for proper operation. As stated above, the output data is not available until TZ +TD after the RO event. However, as long as the stages have matched delays, the load signal to latch the output data into the next stage does not occur until TC +TZ after the RO event. Consequently, as long as TC is greater than TD, there is no problem with the handshake violation. In order to guarantee that the delays are matched between stages, four requirements must be met: (1) that every stage has the same loading; (2) that the logically adjacent stages are physically located next to each other; (3) that the buffered load signal LB has enough drive to latch data reliably; and (4) that TC is greater than TD.
The simplest form of a pipeline is a FIFO, where no transformative processing of the data takes place. In the general asynchronous pipeline, each stage has a logic circuit to process the data along with the data register, and the logic functions are not necessarily the same from one stage to the next. In order to meet the delay matching requirement, the worst case propagation delay path of the logic function is identified and delay circuit matching that delay that is inserted between RO of the stage and RI of the next stage. The delay circuit essentially eliminates the effect of the logic circuit propagation delay.
The pipeline of the present invention must interface to external source and destination devices, which are either asynchronous or synchronous. To interface to an asynchronous source device, the first stage merely delays the event on AI until the input data is latched. To interface to an asynchronous destination device, the last stage merely delays RO until the output data is available. Interfacing to synchronous devices is more complicated, requiring conversion circuits to convert the non-standard handshake signals of the pipeline of the present invention to the clock-controlled signals of the synchronous source or destination device.
Other objects of the present invention will become apparent in light of the following drawings and detailed description of the invention.
For a fuller understanding of the nature and object of the present invention, reference is made to the accompanying drawings, wherein:
FIG. 1 is a block diagram of a four-stage prior art asynchronous pipeline;
FIG. 2a is a timing diagram of a four-cycle handshake between two stages of the pipeline of FIG. 1;
FIG. 2b is a timing diagram of a two-cycle handshake between two stages of the pipeline of FIG. 1;
FIG. 3 is a block diagram of a simple prior art asynchronous FIFO stage;
FIG. 4 is a timing diagram of the FIFO of FIG. 3;
FIG. 5 is a block diagram of a buffered prior art asynchronous FIFO stage;
FIG. 6 is a timing diagram of the FIFO of FIG. 5;
FIG. 7 is a block diagram of a four-stage asynchronous FIFO implementing the present invention;
FIG. 8 is a timing diagram of the FIFO of FIG. 7;
FIG. 9 is a detailed block diagram of a single stage of the FIFO of FIG. 7 showing a preferred controller design;
FIG. 10 is a detailed block diagram of a single stage of the FIFO of FIG. 7 showing an alternate preferred controller design;
FIG. 11 is a detailed schematic of a C-element as used in the present invention;
FIG. 12 is a detailed schematic of a static true single-phase latch as used in the present invention;
FIG. 13 is a detailed schematic of a lower-power version of the static true single-phase latch of FIG. 12;
FIG. 14 is a timing diagram of a stage controller of FIG. 9;
FIG. 15 is a block diagram showing how the present invention is extended to a general asynchronous pipeline;
FIG. 16 is a block diagram showing an interface between a pipeline of the present invention and asynchronous external devices;
FIG. 17 is a block diagram showing an interface between a pipeline of the present invention and synchronous external devices;
FIG. 18 is a timing diagram of the input interface of FIG. 17; and
FIG. 19 is a timing diagram of the output interface of FIG. 17.
The present invention is an asynchronous pipeline design and stage controller that maximizes throughput of the pipeline. When the first stage of a pipeline is full, the source device must wait to write the next piece of data into the pipeline. The pipeline controller of the present invention seeks to minimize this wait by emptying the first stage into the second stage, and so on, as fast as possible so that the source can write its next piece of data into the first stage as soon as possible. Consequently the source device does not have to wait as long or as often for the pipeline.
As shown in FIG. 7, the present invention essentially divides an asynchronous FIFO 10 into two separate and parallel chains by moving the data register load signal buffer 16 outside of the closed loop that generates AI and RO. Instead of using LB to indicate that the data has been stored and is now available to the next stage, LU is used to indicate that the data storage will begin. The two chains are the signal chain 12 involving RI, AI , RO, and AO of the stage controller 18, and the data transfer chain 14 involving LB, DI, and DO. The signal chain 12 performs the handshake between stages 20 and the data transfer chain 14 propagates data from one stage 20 to the next through the action of LB generated at each stage 20. Both chains 12, 14 are triggered by an event on RI of the first stage 20a.
A timing diagram for the FIFO of FIG. 7 is shown in FIG. 8. When data is available from the previous stage at DI, the previous stage causes an event on RI. Assuming that the data register 22 is empty or has already been read by the next stage, the RI event causes an event on RO, indicating that the data is available at the output DO. The RI event also causes LU to rise. The data register load signal LB occurs TB later, latching the data into the data register 22. Finally, the RI event causes an event on AI, indicating to the previous stage that the data has been accepted.
As can be seen, the RO event can occur before DO is actually available, which is a violation of handshake timing requirements. However, as will be shown below, this violation is inconsequential as long as the last stage 20d of the FIFO makes DO available before causing an RO event.
Block diagrams of two preferred stage controllers 18 are shown in FIGS. 9 and 10. The C-element 28, a detailed CMOS schematic of which is shown in FIG. 11, is logic gate where the output O remains constant as long as the inputs are different. When the inputs I1, I2 become equal and different from the output O, the output O changes to the input level. For example, if the output O is low, it will remain low as long as at least one of the inputs I1, I2 is low. When both inputs I1, I2 become high, the output O will become high. A high level on the reset signal R sets the output O low. If a reset is not needed, the NOR gate is replaced by an inverter. If a set signal is desired, the NOR gate is replaced by a NAND gate, where a high level on the second input to the gate allows for normal operation and a low level sets the output O high.
A true single-phase latch (TSPL), a detailed CMOS schematics of which is shown in FIG. 12, is a latch whose operation requires only one phase of the clock (or enable signal). A conventional CMOS latch uses both phases of the clock to control the CMOS transmission gates required in the implementation, where the true phase performs an internal data transfer from the input and the complement phase performs an internal data transfer to the output. On the other hand, in a TSPL, both transfers occur on the same clock edge, removing any skew between the true and complement clock signals. Thus, a TSPL can be clocked at a much higher speed than conventional CMOS latches, resulting in a smaller delay and greater throughput.
A feature of the TSPL for use in the present invention is the addition of the three elements R1, R2, R3. These elements combine to make the TSPL a static, rather than dynamic, device. All three are weak devices, having a strength of less than 1:1. In other words, their outputs are easily overdriven by the other devices driving the same node. The pull-up device R1 makes sure that the input to the second totem 90 does not float when the latch enable E is not active. The other two elements R2, R3 combine to form a feedback inverter. They guarantee that the output will remain constant when the output of the second totem is floating.
An optional feature, used in conjunction with the static feature above and shown in FIG. 13, is the addition of the element R4, a device that supplies power to the pull-up elements R1 and R2 only when the latch enable E is not active. Since R1 and R2 only need to be active when the latch enable E is not active, a power savings is realized. In addition, since R1 and R2 are active only when no other drivers on the node are active, they do not have to be weak devices because they no longer have to be overdriven.
If a TSPL with a negative enable is desired, the gate of the center devices 92, 94 is changed from non-inverting to inverting. In addition, device R1 is converted from a pull-up to a pull-down and its gate is changed from inverting to non-inverting. If a reset signal is desired, the inverter 96 is replaced by a NAND gate, where a high level on the second input to the gate allows the TSPL to operate normally and a low level resets the output /Q high.
Returning to FIGS. 9 and 10, the data register 22 is composed of N TSPL register cells 24 in parallel, where N is the width of the data in bits. Each input D is driven by one of the data signals comprising DIN. The combination of all of the cell outputs Q is the data output DOUT. The cell load signals E are driven simultaneously by LB from the load signal buffer 16.
In the stage controller 18, the C-element 28 generates RO from RI and /AO, the logical inversion of AO. The purpose of using the C-element 28 to combine /AO and RO is to prevent an event on RO if the next stage is not empty. RO, in exclusive-OR combination with an internal signal B, is used to assert LU, which, in turn, drives the load signal buffer 16. LU also clocks RO into an internal TSPL 30 to generate B, which feeds back to the XOR gate 32 to deassert LU. The falling edge of LU clocks the TSPL 34 used to generate /AI, the logical inversion of AI, to indicate to the previous stage that the data has been accepted.
The timing of the stage controller 18 of FIG. 9 is shown in FIG. 14. This timing diagram assumes that the previous and next stages include stage controllers of the same design and that the FIFO has just been reset. An RI event occurs, starting TCYCLE. After a propagation time TC through the C-element 28, an RO event occurs, indicating to the next stage that data is available at DO, although the data is not actually available yet. After a propagation time TX through the XOR gate 32, the load signal LU goes high. On the rising edge of LU, RO is clocked into the internal TSPL 30, sending internal signal B to a high level after the TSPL propagation time of TL. A high level on B causes LU to go low after a delay of TX. Consequently, the width of the load signal LU is the sum of TL and TX. On the falling edge of LU, B is clocked into the AI TSPL 34, causing an event on /AI, indicating to the previous stage that its data DI has been loaded. Meanwhile, after a propagation time of TB through the load signal buffer 16, the data at DI is loaded into the data register 22 by LB, which occurs at time interval TZ =TX +TB after the RO event. DO becomes available to the next stage after a propagation time of TD through the data register 22. The next cycle does not begin until /AO is received by the C-element 28.
Note that the RO event occurs TZ +TD prior to the time that the data is actually available at DO. As indicated above, this is a fundamental violation of the handshake timing for normal asynchronous communications. However, there is no need for normal handshake timing between stages provided that the handshake signals and data remain synchronized. The load signal provides this synchronization.
At the internal stages, delay matching is the key for the FIFO to operate properly. Essentially, each stage must have nearly the same propagation delays, and the propagation delays between adjacent pairs of stages must be approximately the same. When the stages 20 have the same propagation delays, the data will not actually be loaded into the data register 22 when the stage controller 18 receives the RI event. Rather, the RI event propagates through the stage controller 18 before the LB pulse occurs, which is TC +TZ after the RI event. And if the stage delays are matched, it is the same TC +TZ amount of time that the RO event occurs before the data DO is actually available in the previous stage. Thus, the data and handshake signals propagate through the FIFO at the same speed, where the data is behind the handshake signals by the amount of time equal to the delay from RI to LB, which is TC +TZ.
Propagation delays depend upon the physical parameters of the stages. If the four requirements described below relating to the layout and components of each stage are met, delay matching is easily accomplished.
The first layout requirement is that every stage has the same loading. There will always be variations between the parameters of two components that are designed to be the same. As a result, there will always be at least slight differences in the operation and propagation delay between components. This first rule acknowledges that there will be differences and seeks to minimize their effects by making the timing within each stage be the same as all other stages.
The second requirement is that the logically adjacent stages are physically located next to each other. Process parameters vary over the area of an integrated circuit. Putting logically adjacent stages next to each other minimizes the variations between stages, essentially making the variations negligible and providing the adjacent stages with similar delays.
The third requirement is that the buffered load signal LB have enough drive to latch data reliably. The load signal buffer 16 must be able sink or source enough current (depending on the data register type) to provide adequate rise and fall times for the load signal. As described above with reference to FIGS. 9 and 14, the length of the load signal pulse is TX +TL, a relatively short time span. However, the rise and fall times of the pulse determine the actual length of time of the load signal pulse as seen by the data register. As the rise and/or fall times increase, the load signal pulse effectively shortens. If the load signal pulse is too short, there will not be enough time to latch the data into the data register before the load signal pulse terminates, leading to indeterminate data at the output. The determining factor in how long the load signal pulse must be is the propagation delay through the data register. For a traditional latch, the delay is approximately that of two inverters. Thus, the length of the load signal pulse would need to be at least that of two inverter delays. If TSPLs are used for the data register, the propagation delay is shorter, so a shorter load signal pulse is necessary.
The final requirement is the data register 22 forward data from one stage to the next no slower than the RI -to-RO delay of the stage controller 18. In other words, the propagation delay TD of the data register must be no greater than the propagation delay TC through the C-element 28. When AO is inactive, meaning that the next stage is empty, the handshake signals will propagate to the next stage with a speed of TC. Thus, in order to keep up, the data must travel at least as fast. This way, a data travels from stage to stage at the same rate as the handshake signals. In the event that TD is less than TC, so that the data could potentially move faster than the handshake signals, it will have to wait for the load signal LB to arrive before it can be forwarded to the next stage. Thus, the load signal LB synchronizes the data and signals so they travel through the FIFO at the same speed.
FIG. 10 shows a modification to the basic stage controller design. In some situations, it is necessary to lengthen the load signal LB or to delay the AI event to guarantee that data is loaded before the AI event occurs. An example of such a situation is when the device sourcing data to this stage implements a normal handshake protocol and expects that it can remove or change the data as soon as it receives an AI event. A multiplexer 36 is inserted between the XOR output LU and the D TSPL clock input E. The second input of the multiplexer 36 is LB. When the multiplexer 36 is selected to use the LB input, the load signal LB is lengthen by TB, the load buffer delay, and the AI event is delayed by TB. A penalty is paid by the versatility gained. Like any other logic gate, the multiplexer 36 has a propagation time TM, which increases the RI -to-AI time by about 10% when LU is selected. Consequently, the throughput of the FIFO is reduced by approximately 10%, even if LU is selected.
The previous discussion of the present invention has been relative to a FIFO, which is the simplest form of a pipeline. In a FIFO, no transformative processing of the data takes place within stages. FIG. 15 shows how the present invention can easily be extended to general asynchronous pipelines that have functions more complicated than storing and forwarding data. A pipeline stage 40 stores data for use by a logic function circuit 42 of the stage. Consequently, the logic function circuit 42 is inserted into the stage 40 after the register 44. There is no requirement that the logic function 42 be the same for each stage and, in fact, in the typical complex pipeline, they are not the same. The worst case propagation delay path of the logic function 42 is identified, which has a time interval TP, and replicated to generate a matched delay circuit 46 that is inserted between RO of the stage and RI of the next stage. This delay circuit 46 delays the event on RO, not until the logic function circuit 42 is complete and the data is available, but until TZ +TD before the data is available. The delay circuit 46 essentially matches this stage's timing to that of the other stages by eliminating the effect of time interval TP from the delay equations.
Because a pipeline incorporating the present invention must operate as a component of a circuit, its input and output must interface properly with the external devices that provide the source and destination for its data. The external devices are either asynchronous or synchronous. An example interface between an asynchronous source device 50 and a pipeline 52 of the present invention is shown in FIG. 16. In the general situation, no assumptions can be made about the operation of the source device 50 except that it will use the normal handshake protocol. This means that the data DI may disappear at the same time that an event is asserted on AI by the pipeline 52. Therefore, the pipeline 52 must hold off asserting AI until it is sure that the data DI is properly latched in the data register 54. To accomplish this, a delay line 56 is inserted between AI of the pipeline 52 and AO of the source device 50. Assuming that the data TSPLs and the AI TSPL have similar latch times, the minimum period of the delay is set to the worst-case delay period of the load signal buffer 58. Naturally, if some characteristics of the source device 50 are known, such as the delay between when AO is asserted and the data is no longer valid, this knowledge can be exploited to decrease the delay period, increasing throughput. An alternate to the delay line 56, using the buffered load signal LB to cause the AI event, is described above with reference to FIG. 10.
Also shown in FIG. 16 is an interface between the pipeline 52 and an asynchronous destination device 60. Since, once again, it must be assumed that the destination device 60 will use proper handshake protocol, RO must not occur until the output data DO is actually available to the destination device 60. This is accomplished by providing a delay line 62 having a period equivalent to the delay period through the XOR gate in the stage controller 64, the load signal buffer 68, and the data register 66. Essentially, the delay line 62 simulates the length time that the RO signal occurs before the output data DO is actually available. As above, known characteristics of the destination device 60 can be exploited to increase throughput.
The more complicated and common situation is when the asynchronous pipeline must interface with a synchronous device such as a microprocessor or disk drive controller. Examples of such interfaces are shown in FIG. 17. At the input, the synchronous signals of the data source 70 must be translated to asynchronous signals for the pipeline 72. Following a reset, RI and BUSYIN are low and there is no activity until EnIN is set high, as shown in the timing diagram of FIG. 18. When that occurs, the interface data register 74 and RI toggle flip-flop 76 become active. At the next rising edge of the clock ClkIN, data DIN is latched into the interface data register 74 and an RI event occurs. The pipeline 72 processes the RI event and returns AO, which is ignored by the synchronous circuitry. Meanwhile, if all stages of the pipeline 72 are holding data, the Full signal is clocked into the Busy flip-flop 78, signaling to the source device 70 that no more data can be accepted. Full is generated by the OR of a small number of Fulls signals from the first two to four successive individual stages at the input end of the pipeline. Fulls is generated by an XOR of RI and AI, which essentially means that the data is available to a stage but has not yet been read by the stage.
At the output, the asynchronous signals of the pipeline 72 must be translated to synchronous signals of the destination device 80. Following a reset, AO, the output enable signal EnO, and the enable E of the interface data register 82 are low, as shown in the timing diagram of FIG. 19. It is assumed that RO and the destination device busy signal BusyO are initially low. Upon an RO event, the internal enable En is set, enabling the interface data register 82. On the rising edge of the next clock ClkO, DO is stored in the interface data register 82 and is available at DOUT, EnO is set to indicate valid data DOUT to the destination device, and the AO T flip-flop 84 toggles to cause an event on AO. When the AO event occurs, En goes low, disabling the interface data register 82 and causing EnO to return to low at the next clock. If BusyO should rise, indicating that the destination device 80 cannot except data, the interface data register 82 will not be enabled, EnO will not set, and the AO T flip-flop 84 will not toggle.
Thus it has been shown and described an asynchronous pipeline which satisfies the objects set forth above.
Since certain changes may be made in the present disclosure without departing from the scope of the present invention, it is intended that all matter described in the foregoing specification and shown in the accompanying drawings be interpreted as illustrative and not in a limiting sense.
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|Logic synthesis of multi-level domino asynchronous pipelines
|Aug 18, 2005
|Jul 13, 2006
|Fulcrum Microsystems, Inc.
|Shared-memory switch fabric architecture
|Sep 15, 2010
|Mar 15, 2012
|International Business Machines Corporation
|Circuit and method for asynchronous pipeline processing with variable request signal delay
|Dec 16, 2011
|Jun 20, 2013
|International Business Machines Corporation
|Asynchronous circuit with an at-speed built-in self-test (bist) architecture
|Jul 22, 1999
|Feb 3, 2000
|California Inst Of Techn
|Reshuffled communications processes in pipelined asynchronous circuits
|Dec 17, 2001
|Jun 27, 2002
|Sun Microsystems Inc
|Apparatus and method for generating fifo fullness indicator signals
|Nov 6, 2007
|May 14, 2009
|Koninkl Philips Electronics Nv
|Data processing arrangement, pipeline stage and method
|Nov 18, 2008
|May 28, 2009
|Koninkl Philips Electronics Nv
|Asynchronous pipeline controller
|U.S. Classification
|International Classification
|Cooperative Classification
|European Classification
|Sep 2, 1997
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Archive: 16/04/2014
A greener source of polyester—cork trees
On the scale of earth-friendly materials, you'd be hard pressed to find two that are farther apart than polyester (not at all) and cork (very). In an unexpected twist, however, scientists are figuring out how to extract a ...
Alibaba steals Yahoo's thunder ahead of IPO
If Yahoo appears back in favor, it can thank Alibaba, the Chinese Web giant in which it holds a big stake and which is set for a public stock offering.
Study: The trials of the Cherokee were reflected in their skulls
Researchers from North Carolina State University and the University of Tennessee have found that environmental stressors – from the Trail of Tears to the Civil War – led to significant changes in the shape of skulls in ...
Researchers question emergency water treatment guidelines
The Environmental Protection Agency's (EPA's) recommendations for treating water after a natural disaster or other emergencies call for more chlorine bleach than is necessary to kill disease-causing pathogens and are often ...
Micro-macro entangled 'cat states' could one day test quantum gravity
(Phys.org) —In Schrödinger's famous thought experiment, a cat's quantum state becomes entangled with the quantum state of a decaying nucleus, resulting in the odd situation that the cat is both alive and dead at the same ...
Team finds electricity can be generated by dragging saltwater over graphene
(Phys.org) —A team of researchers at China's Nanjing University of Aeronautics and Astronautics, studying graphene properties, has discovered that the act of dragging saltwater over a piece of graphene can generate electricity. ...
EU must take urgent action on invasive species
The EU must take urgent action to halt the spread of invasive species that are threatening native plants and animals across Europe, according to a scientist from Queen's University Belfast.
New US-Spanish firm says targets rich mobile ad market
Spanish telecoms firm Telefonica and US investment giant Blackstone launched a mobile telephone advertising venture on Wednesday, challenging internet giants such as Google and Facebook in a multi-billion-dollar market.
Travelling dunes encroach on infrastructure, and reveal geological pattern
Recent research shows shifting sand dunes threaten to envelop several important Mid West roads within the next few years.


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The ABCs of Assistive Technologies
"Assistive technology (AT) can be defined as any item, piece of equipment, or product system, whether acquired commercially off the shelf, modified, or customized, that is used to increase, maintain, or improve the functional capabilities of individuals with disabilities. (29 U.S.C. Sec 2202(2))."
Assistive technologies are mobility devices that can increase or improve the functional capabilities of students with special needs and many teachers, including those at VFES, are finding great use for them in the classroom.
But how do you know if a student would benefit from Assistive Technology? When a student is identified as one who may need the assistance of technology, educators enter the student into the SETT process (Student, Environments, Tasks, and Tools), an ongoing, collaborative decision-making process for the student's team. The SETT framework guides the team to work together to find the best strategies or tools for that student in an attempt to break down any barriers to student achievement. These tools could be as simple and low tech as a pencil grip or as high tech and involved as an iPad with an Augmentative and Alternative Communication (AAC) App installed.
|Scooped by adpcenter


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Search Inside Zip Files Software
editor's review
buy now $19.99
Search Inside Zip Files Software is a lightweight Windows application whose purpose is to help you look for files within ZIP archives by filename.
Clean design
The tool impresses with an intuitive layout and easy-to-decode configuration parameters. A help manual is not included in the package but you can watch a video tutorial that explains how to make the most out of the utility. In addition, you are allowed to load some sample files in order to test the program's search capabilities.
Search options
Search Inside Zip Files Software gives you the possibility to add ZIP files in the working environment using the built-in browse button (you cannot rely on the drag-and-drop support). Plus, you may add the content of an entire folder.
You may create a list with the items that you want to process, clear the entire list with a single click, and make the application list all files inside ZIP archives. What's more, you are allowed to perform searches within the ZIP files by filename or custom strings that are contained within the files.
The results are displayed directly in the main window and you may copy them to the clipboard so you can easily transfer them into other third-party programs. You may also export the results to plain text file format.
Tests have shown that Search Inside Zip Files Software performs search tasks quickly and without errors. It is not a resource hog so you don't have to worry that it eats up CPU and memory resources.
Bottom line
All things considered, Search Inside Zip Files Software provides a straightforward software solution for helping you quickly identity files within ZIP archives, and can be configured by rookies and professionals alike.
top FREE alternatives
top PAID alternatives


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Narrow your search
A new quick-access gesture in the latest Lollipop build turns on the phone's flashlight with a wave of the wrist.
Donald Bell shows you an alternative, faster way to switch off your iPhone's flashlight feature.
You can skip the Control Center to turn off the flashlight on your iPhone.
Looking to get more out of Spotlight on your Mac? This free app is your answer.
A tiny doughnut-shaped chip that attaches to the end of a catheter could improve the way doctors peek inside our circulatory systems.
CNET's Michael Franco falls in love with an inflatable lantern.
The Million Mile Light skips the batteries and instead uses a runner's motion to power the bright LEDs.
The first teaser for the new "X-Files" reboot offers a quick glimpse at the reboot along with some nostalgia and the assertion that "the truth is in there."
An honest-to-goodness card delivered by honest-to-goodness US Mail. Nice gift item for a mom, dad or grad! Plus: three bonus deals!
Turning the flashlight off on your iPhone using Control Center is so 2013. Instead, use this helpful tip to quickly turn it off.


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Osburne Ievers
1 portrait of Osburne Ievers
Osburne Ievers
by Walter Stoneman
bromide print, 1936
7 5/8 in. x 5 5/8 in. (194 mm x 143 mm) image size
Commissioned, 1936
Photographs Collection
NPG x168521
Click on the links below to find out more:
Sitterback to top
- Osburne Ievers (1879-1963), Major-General. Sitter in 1 portrait.
Artistback to top
- Walter Stoneman (1876-1958), Photographer. Artist associated with 18438 portraits, Sitter in 8 portraits.
Portrait setsback to top
Tell us moreback to top
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Home > > Debrecen > Squad > Profile: Balazs Farkas Ii
Balazs Farkas Ii Debrecen
Profile of the footballer Balazs Farkas Ii, who currently plays as a at Debrecen. The -year old player Ii joined Debrecen from and wears the number shirt.
Balazs Farkas Ii Career
Balazs Farkas Ii Photos
Balazs Farkas Ii : Debrecen News
Balazs Farkas Ii Career Honours
Source: wikipedia.org
Balazs Farkas Ii Wiki, Stats & Links
Sepp Blatter's reign may be crumbling but Fifa cannot rebuild itself
'Northern Ireland reaching Euro 2016 feels like the glory days of 1982'
Sam Allardyce to open talks with Sunderland over manager's job
Wales's Chris Gunter eyes Euro 2016 qualification, not personal landmarks
Overweight Diego Costa takes heat off Chelsea's José Mourinho
Harry Kane and Theo Walcott head England's forward thinking


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TUSCALOOSA, Ala. — Hollis Thompson found just the right spot for a game-winning shot: Right in front of Georgetown's bench.
Thompson hit a long 3-pointer with 1.8 seconds left to lift the Hoyas to a 57-55 win over No. 12 Alabama on Thursday night, ending the Crimson Tide's 24-game home winning streak. Then he didn't have to go far for the celebration.
Jason Clark, who had 22 points, dribbled up the court and handed off to Thompson, who drilled it to giveGeorgetown (6-1) its second win in three games over a team ranked in the Top 12.
"We drew a play trying to penetrate and they played it pretty well," Thompson said.
So he took the only option left, and delivered.
"Jason didn't have anything so he went to Hollis, and Hollis did what Hollis does," Georgetown coach John Thompson III said.
Alabama (7-1) had taken its second lead of the second half on Trevor Releford's two free throws with 13 seconds remaining. After a quick timeout by Georgetown, Clark and Hollis Thompson silenced a crowd thinking it was going to escape with the nearly 2-year-old streak alive.
Then, a ball screen and an apparent defensive mixup from Trevor Lacey and JaMychal Green helped get Thompson the contested shot.
"We didn't effectively defend that the way we were supposed to," Alabama coach Anthony Grant said. "Neither of the players that were involved defended it the way that we were supposed to."
The Tide rallied from a nine-point deficit over the final 3 minutes. Thompson hit the final two baskets forGeorgetown, which also beat then-No. 8 Memphis in overtime last week.
Henry Sims scored 13 points and Thompson added 12 points and eight rebounds for the Hoyas, who came in averaging 82 points but matched Alabama's stingy defense stop for stop.
Tony Mitchell scored 16 of his 20 points in the second half for Alabama and finished off a couple of alley oops from Releford.
"He certainly ignited our team and the building," Grant said.
Green seldom got the ball inside against Georgetown's zone and scored six of his 13 points over the final 5 minutes. Releford had nine points and six assists.
"It just got us out of whack, and we weren't aggressive against the zone," Green said. "There's just a lot of things we could have done differently. Just getting the ball in the middle. Once you get the ball in the middle, it beats the zone and we really didn't do that."


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The Holocaust and the United Nations Outreach Program
Sponsored by Kleinmann Family Foundation. Kimberly Mann, chief, Special Projects Unit, Public Relations Section, United Nations. Free admission. All welcome.
Contact Information
Ethical dilemmas and palliative care
Workshop on caring for a person with a terminal illness. Dr. Manny Borod, MD, clinical director, Division of Palliative Care, MUHC.
Contact Information
Home vs. hospital: Exploring the options
Workshop on caring for a person with a terminal illness. Joan Foster, BN, CSSS homecare nurse.
Contact Information
Communications in palliative care
Workshop on caring for a person with a terminal illness. Sue Britton, RN, psychotherapist, yoga teacher.
Contact Information
10th annual Sandra Goldberg Lecture: Palliative care isn't just about cancer
Dr. Gian Domenico Borasio, MD, Chair in Palliative Medicine, Munich University Hospital, Germany
Markers of F. hepatica infection in sheep and cattle: Insights into fasciolosis host-parasite interactions
Marie-Claire Rioux
Contact Information
DNA targets and kinase activity in Plasmodium: Unraveling the mechanisms of transmission in the malaria parasite
Lisa Purcell
Contact Information
Prospects for a Gal-lectin based vaccine against Entamoeba histolytica
Catherine Ivory. This seminar will be by video conferencing.
Contact Information
Sustaining parasite control in livestock in the face of developing drug resistance: Ivermectin and Benzimidazole selection on β-tubulin in Haemonchus contortus
Dr Lourdes Mottier
Contact Information
Sodom rediscovered
Rabbi Steven Greenberg, Senior Teaching Fellow at CLAL, the National Center for Jewish Learning and Leadership in New York City, author, and the first openly gay Orthodox rabbi, in his first visit to Montreal. Rabbi Greenberg has spoken all over the world about homosexuality in the Jewish tradition, and has become a public advocate for ending the silence in the Orthodox community on the issue of homosexuality in the US and abroad.


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Dalai Lama Lesson
India shows the world how to stand firm with China.
As President Obama prepares for his trip to Beijing next month, he'd be wise to cast an eye toward New Delhi, where Prime Minister Manmohan Singh is showing the rest of the world how to deal with Beijing when it gets into a bullying mood.
At issue is the Dalai Lama's proposed trip next month to visit Tibetan Buddhist believers in Arunachal Pradesh, a province governed by India but claimed by China since the 1962 border war. Chinese spokesperson Ma Zhaoxu said last week the trip "further exposed the anti-China and separatist nature of the Dalai clique."
But India stood firm. During a regional summit over the weekend Prime Minister Manmohan Singh says he "explained to Premier Wen [Jiabao] that the Dalai Lama is our honored guest; he is a religious leader." The prime minister went on to imply that the Dalai Lama was free to travel where he pleased, so long as he did not engage in politics.
This contrasts with Mr. Obama's decision not to meet with the Dalai Lama earlier this month. His cave-in broke Presidential precedent and emboldened Beijing to step up anti-Dalai Lama rhetoric, particularly in—guess where—India, which has hosted Tibet's government-in-exile for more than 50 years.
Mr. Singh will face further China tests soon, given the other conflicts with his northern neighbor. China and India still dispute their 2,200-mile long border, and Indian defense officials say that Chinese incursions into Indian territory are on the rise. The two also have disputes over Kashmir and Nepal.
Those irritants are more reason for Mr. Singh to stand firm on the principles for which India stands—the very same principles of democracy and freedom that America holds. Therein lies a lesson for Mr. Obama's China diplomacy as well.


text:
Standard Life Spurns 'Adrenaline Junkie' Greek Debt
Standard Life Investments said it isn't tempted to buy Greek, Portuguese and Irish securities as they get cheaper and yields surge, given it remains skeptical about the fiscal outlook for Europe's most indebted nations.
"You have to be an adrenaline junkie to be very active in those markets," Frances Hudson, head of global thematic strategy at the division of Standard Life Plc, said in an interview in London today. "We aren't heavy in any of the peripherals. It's obvious people are going to buy German bunds for safety."
Standard Life Investments prefers pound-denominated assets to those in euros given Britain's perceived political stability is drawing foreign investment as the sovereign-debt crisis persists, Hudson said.
Irish and Portuguese bonds tumbled today, pushing yield spreads on their 10-year securities over benchmark German bunds to records on renewed concern that European banks are vulnerable to losses on their holdings of peripheral debt. German and U.K. bonds rose today, while the pound climbed against the euro.
Greek 10-year government bonds also fell today, widening the spread over bunds to the most since May 7. That was the last trading day before the European Central Bank said it would buy sovereign bonds to back a European Union bailout plan. The Wall Street Journal, citing its own analysis, reported on its website yesterday that stress tests underestimated some banks' holdings of potentially risky government bonds.
British Haven
Standard Life Investments, which is based in Edinburgh, has $175 billion of assets under management.
Foreign investors bought a net 5.6 billion pounds of U.K. government bonds in July, compared with a net sale of 674 million pounds in the prior month, Bank of England data released on Aug. 31 showed.
"Sterling is enjoying a safe-haven status, while you have wobbles in the euro because of concern over peripheral countries," said Hudson.
The U.K.'s Conservative-Liberal Democrat coalition government, which took power in May, is also becoming less of a concern to international investors given what has happened in other recent national votes, she said.
"We've had a series of elections in developed countries this year, and all of them produced less decisive outcomes," Hudson said. "We still don't have an effective coalition in place in Belgium. Australia struggled to form one. This makes the U.K. look better by comparison."
Standard Life prefers U.K. corporate bonds to gilts to take best advantage of inflows to Britain, Hudson said.
"You can still get some pick-up in yields in the corporate bond market," Hudson said. "Gilts have had a 10 percent return this year. It's unlikely they will give another 10 percent."
The Bank of England is unlikely to expand its bond-purchase program, known as quantitative easing, given U.K. economic data is improving, Hudson said. The central bank will probably keep its official rate at a record low of 0.50 percent for at least a year, she said.


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25 Times Marjorie Harvey's Instagram Outdid Your Favorite Fashion Magazine view
The 10 Best Dressed Celebs of the Week view
Jada Pinkett Smith Is Killing It at Paris Fashion Week view
Check out which celeb looks we're swooning over!
The haute Girlfriend honoree looked ravishing in this red form-fitted dress,...
The haute Girlfriend honoree looked ravishing in this red form-fitted dress, matching satin sandals and spiked McQueen clutch for edge.
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text:
McIlroy frustrated by distractions in rough 2013
DUBAI, United Arab Emirates (AP) – Embroiled in court cases on both sides of the Atlantic, Rory McIlroy has been visiting lawyers' offices instead of winning golf titles this year.
The Northern Irishman remains without a victory in 2013 as he returns to Dubai this week to defend his last victory, the World Tour Championship. He's slipped from No. 1 in the rankings to No. 6.
In the 12 months since, he has become tied up in legal wrangling with his former management company, Horizon Sports Management, and his former sponsor, Oakley.
"I've seen more lawyers' offices and more lawyers this year than I care to see in my entire life," McIlroy said Tuesday. "It's not something I ever want to go through again, and I'm making sure that I won't go through it again.
"As a golfer, you want your mind as clear as possible, and it's hard for that to happen when you've got other things that are going on that, firstly, you don't want to happen, and secondly, you don't feel should be happening. It has been a distraction."
McIlroy said he was taking some advice from Tiger Woods about how to handle his off-course issues.
"Sometimes you have to say `no' and sometimes you have to put yourself first and say `no,' and I need to do this for myself to maintain the level in my game," McIlroy said.
"It's something Tiger actually said to me last year. He said you have to remember what got you here in the first place, and you know Tiger, it's `no' 99 percent of the time for him."
McIlroy won last year's World Tour Championship at the Jumeriah Estates course when he birdied the closing five holes to overtake Justin Rose and end the year with money titles in Europe and on the PGA Tour.
He still has two more tournaments left in 2013, the Australian Open in Sydney and the Woods-hosted World Challenge at Thousand Oaks.
(Copyright 2013 The Associated Press. All rights reserved. This material may not be published, broadcast, rewritten or redistributed.)


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O2's internal communications traditionally took the form of topdown emails from the communications team and blog posts from executives. Looking for cutting edge tools that would allow groundup communication and innovation, O2 began exploring enterprise social networking in 2009. Now, Yammer "connects the dots" in O2, enabling greater operational efficiency and more innovation. Greater operational efficiency allows O2 to provide better customer service, making more customers happy.
Before embracing Yammer, O2 operated with a traditional communications system made up of three components: email, phone, and a company intranet that incorporated a basic blogging tool. Company-wide communication was generally top down, taking the form of emails from the communications team and blog posts from executives. The need for a tool to allow employees to share thoughts across the company in real time became increasingly clear. Starting in June of 2009, O2's Yammer network has grown completely organically across departments to 5,500 members, half of O2's staff. Employees are incredibly excited about the tool and the value it provides the company, regularly adding the topic #YammerHelpedMe to their posts.
O2 customer service representatives are able to provide faster, more accurate customer service because Yammer has helped streamline O2's internal customer service processes. Many customer service team leaders are on Yammer, serving as information-sharing nodes for the entire customer service team. When customer service reps come up against new and complicated problems, they can alert their team leads, who post the questions to O2's Yammer network. Within minutes, the team leads get weigh-in from other customer service team leads, the Networks Team, the Devices Team, and the IT organization. With each relevant party represented on these Yammer threads, a solution or plan of action is regularly delivered within an hour of collaborating together. When a solution is reached, customer service team leads disperse the information back to the customer-facing reps, who can promptly relay the solutions to O2's customers. Because of this streamlined process, customers get help faster and internal parties save enormous amounts of time and effort. O2 uses an idea suggestions tool called O2 Crowd that lets people from around the business submit their ideas to help solve company challenges. When support reps began getting thousands of tickets about a specific Blackberry feature, one of the reps posted her idea to help resolve the issue to O2 Crowd. Rather than waiting a week or so for the idea to go through the normal vetting process, she posted to Yammer "I just submitted this idea to O2 Crowd – what do you think?" Within a day, she had the Networks, Devices and IT teams working to make the idea a reality. As a result, her idea to text helpful instructions to Blackberry users on how to solve the problem was implemented within a day, and the support team saved themselves thousands of help tickets.
Yammer allows new O2 employees to quickly integrate into the company and feel part of the community. A big part of joining a new large enterprise is learning lots of new names, quickly. Yammer has been incredibly helpful in this regard, giving new employees a study guide of new faces and names, especially when broken down into Yammer group directories. Beyond getting to know their new coworkers, new O2 hires can get quick answers to their questions around a variety of topics like policies, resources, and technical systems. A recent graduate at O2 describes the way Yammer helped him ramp up quickly: "I joined O2 about two months ago. When I first arrived I was just astonished at how huge the corporation is. I was lost in internal processes, I didn't know who to talk to, and a couple of weeks later I joined Yammer. Within seconds, I discovered that the information was at my fingertips. I could access it instantly, I could ask the crowd a question, and I could see people's names and match them to their faces. Yammer was useful all around."
In addition to reducing the number of customer help tickets, Yammer has decreased the number of internal IT tickets at O2. The #YammerHelpedMe Topic has become very popular for threads where someone is able to resolve an IT issue in a short period of time. One person posted about an issue he was having with Microsoft Outlook's autocomplete functionality. Within two hours, he had a solution from a non-IT coworker that had troubleshooted the problem himself. Another employee was having trouble setting up SharePoint shortcuts in her Windows 7 environment, and described her issue on Yammer. Over the course of a day, coworkers from her department and IT weighed in and came to a solution collaboratively by the next morning. In all of these cases, the original poster happily added the #YammerHelpedMe Topic to the thread, exemplifying the type of helpful conversations that go on within O2's Yammer network on a daily basis.
To reach more employees with Yammer, O2 is rolling out Yammer's SharePoint integration, allowing employees to connect via Yammer feeds dropped into SharePoint pages. Not only does this extend the reach of Yammer, it integrates it into SharePoint's document sharing and search functionalities. Like Yammer, SharePoint is used widely across the company, so to turn the two knowledge bases into one was an obvious choice. O2 will also implement Yammer's AD sync tool to streamline the administration of network membership. O2's Yammer administrators have gained significant insight from their Customer Success Manager (CSM), who has helped the team maximize the value of their network. O2's CSM has provided training materials and services, best practices for maximizing business value, and lessons learned from other successful Yammer customers. On the whole, O2's CSM has been a helpful consultant and guide for the company as they explore the new world of enterprise social networking. Perhaps most important for O2 was having granular control over network security. Because O2 deals with highly confidential intellectual property, the company performs regular security audits of all business tools. For this reason, features like enforcing password complexity rules and requiring regular password changes have been crucial.
Yammer is an enterprise social network that transforms organizational communication and collaboration among employees, customers, partners and suppliers. More than 80 percent of Fortune 500 companies are using Yammer's award-winning Software-as-a-Service (SaaS) solution to break down silos, drive organizational alignment, increase agility and improve decision making.


text:
e days before computer type, was to have them printed on condoms, which he then pinned down in stretched and distorted form and photographed.
As Laetitia Wolff concludes in her introduction of Massin and his work, "This free-spirited and compulsive creator is the unsung hero of an immense graphic heritage. Make way for Massin."
Rick Poynor's vices & virtues
Former Eye editor Rick Poynor issues a call for critical thinking among graphic designers.
[May 25, 2001]
Rick Poynor, design critic and founder of the incisive British graphic-design magazine Eye, spoke to an audience of graphic designers in San Francisco in May 2001, as part of the Design Lecture Series sponsored by the local AIGA and SFMOMA. He presented his audience, which looked to be mostly young designers, with a sort of "manifesto" (he made the quotes audible) about graphic design, consisting largely of paired lists of "six vices" and "six virtues." It was a call to responsibility an
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5 Strategies that are shining a new light on old ways of marketing
With an infusion of capital and a major acquisition, Eagle Golf has reinvented itself as Arcis Golf
The Curtis family has made Mill Creek Golf Club a family affair for more than four decades
Sales and marketing is an essential aspect of any golf course operation. In this video from the 2015 NGCOA Annual Conference, the leaders of Hyatt Hill Country Golf Club share how they leverage the facilityís unique competitive advantages, which are grounded in knowing who they are and where they fit in the market.
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