text:
|Publication number
|Publication type
|Application number
|Publication date
|Jun 26, 2003
|Filing date
|Dec 6, 2002
|Priority date
|Dec 7, 2001
|Also published as
|Publication number
|Cho Moon, Harish Kriplani, Krishna Belkhale
|Original Assignee
|Cadence Design Systems, Inc.
|Export Citation
|BiBTeX, EndNote, RefMan
|Patent Citations (5), Referenced by (20), Classifications (6), Legal Events (3)
|External Links: USPTO, USPTO Assignment, Espacenet
[0001] The present application claims priority to U.S. Provisional Application Serial No. 60/339,235, filed Dec. 7, 2001, which is hereby incorporated by reference in its entirety.
[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files and records, but otherwise reserves all other copyright rights.
[0003] The invention relates to the field of electrical circuit design, and more particularly, to the field of timing model extraction.
[0004] Timing extraction or block characterization refers to the process of creating a timing model of a digital circuit for use with a timing analyzer, e.g., a static timing analyzer. Timing extraction plays an important role in hierarchical top-down flow and bottom-up IP authoring flow by reducing the complexity of timing verification and by providing a level of abstraction which hides the implementation details of IP blocks. Three desired features in timing extraction are accuracy, efficiency, and usability.
[0005] The extracted model should preserve the timing behavior of the original circuit and produce accurate results including correct transparent latch behaviors and timing violations. The model also needs to be efficient in terms of the resources needed to generate the model and in terms of the final model size. The model should also be easy to use with existing static timing analyzers. This includes model instantiation, translation of original timing constraints and easy-to-follow timing reports.
[0006] Timing model can often be classified into two types: black box model and gray box model. Black box models have no internal visibility into the block—all the timing information relates to the pins at the boundary of the block. Gray box models, on the other hand, have internal pins that allow for modeling behaviors like time borrowing across multiple latches. Such internal pins provide advantages such as capability to reduce model size and capability to apply original timing constraints or assertions.
[0007] In one approach for implementing a black box model, users supply a set of input slew values and output load values and the tool performs path tracing to determine all port-to-port path delays and relevant timing checks. Although black box models have been widely used, they suffer from significant drawbacks. For example, tracing each possible path in the timing graph is a potentially complex task that could consume a significant amount of computing resources—often requiring a full timing analysis process to extract a model. Moreover, the resulting model size in this approach may actually end up larger than the original timing graph size. This is illustrated in FIG. 1, in which path tracing is employed to derive a black box model 140 from a timing graph 100. In this approach, every potential path is identified by tracing from an individual input port to an individual output port. Thus, the path through arc 102 and arc 108 in the original timing graph 100 is traced through pin 150 to form path 120 in the black box model 140. Tracing each possible path results in nine arcs or paths in the resulting timing model 140 (arcs 120, 122, 124, 126, 128, 130, 132, 134, and 136). As can be seen, there are only six arcs in the original timing graph 100 (arcs 102, 104, 106, 108, 110, and 112). Thus, the black box model 140 is actually larger than the original timing graph 100.
[0008] Another drawback with known black box models is that only limited latch behavior can be modeled. The model can capture the latch time borrowing behavior of the original netlist for some given clock waveforms. If the clock waveforms change after the model is extracted, the model becomes invalid. Moreover, support for assertions in black box models is limited, even for those assertions that are fully contained in the block. Only assertions that originate from and terminate at boundary ports can be fully supported. For example, multi cycle paths that do not originate from or terminate at boundary ports cannot be supported. Also, assertions that span multiple blocks cannot be supported. For example, consider a multi cycle path that originates from block A and terminates in the middle of block B. The black box model for block B cannot support this multi cycle path assertion.
[0009] Approaches to gray box modeling also suffer from drawbacks. Conventional gray box approaches cannot adequately handle arbitrary levels of transparency in latches. Latches may be transformed to registers or combinational gates but such transformations could lead to models that are too conservative and do not allow for time borrowing. One approach provides latch path compression work that collapses latch paths instead of individual latches, in which the extent of compression is controlled by specifying the desired level of latch transparency. However, this approach cannot guarantee a reduction in model size and in some cases, the model size actually increases after latch path compression. Moreover, the method does not scale well with the number of latch paths or with the level of latch transparency.
[0010] Disclosed is a method and system to generate a timing model by reducing the timing graph. The method can generate a model that is accurate within a specified tolerance and is very efficient. Also described is an approach for preserving and applying timing constraints/assertions to a model. In one embodiment, the timing constraints/assertions are viewed as part of the model, and a set of new timing constraints can be generated is automatically applied as part of the model extraction process. Latch time borrowing and support for the application of original assertions can be accomplished by retaining some internal pins. Further and additional objects, details, and advantages of the invention are described in the figures and text below.
[0011]FIG. 1 illustrates a problem with existing blackbox modeling methods.
[0012]FIG. 2a depicts an example timing graph.
[0013]FIG. 2b shows an example transition matrix for the circuit of FIG. 2a.
[0014]FIG. 3a shows a flowchart of an embodiment of a process for implementing model extraction.
[0015]FIG. 3b shows a flowchart of an embodiment of a process for graph reduction.
[0016]FIG. 3c depicts an embodiment of an architecture for model extraction.
[0017]FIGS. 4a-c show examples of pseudo code for implementing graph reduction according to an embodiment of the invention.
[0018]FIGS. 5a and 5 b illustrate an serial merge (s-merge) operation according to an embodiment of the invention.
[0019]FIGS. 6a and 6 b illustrate a parallel merge (p-merge) operation according to an embodiment of the invention.
[0020]FIG. 7 illustrates that p-merge operation accurately reflects changes in critical path according to an embodiment of the invention.
[0021]FIG. 8 depicts a process for reducing a circuit portion according to an embodiment of the invention.
[0022]FIG. 9 shows a forward s-merge operation according to an embodiment of the invention.
[0023]FIG. 10 shows a backward s-merge operation according to an embodiment of the invention.
[0024]FIG. 11 illustrates processing of a self-loop check arc according to an embodiment of the invention.
[0025]FIG. 12 illustrates handling of hierarchical pin assertions according to an embodiment of the invention.
[0026]FIG. 13 shows a timing graph portion requiring a special processing for check arcs.
[0027]FIG. 14 illustrates an example of graph reduction on a circuit having two registers and a latch according to an embodiment of the invention.
[0028]FIG. 15 depicts one approach to assertion handling for model extraction.
[0029]FIG. 16 depicts an alternate approach to assertion handling for model extraction in an embodiment of the invention.
[0030]FIG. 17 shows a flowchart of an embodiment of a process for assertion handling.
[0031]FIG. 18 illustrates an approach for handling assertion across multiple blocks according to an embodiment of the invention.
[0032]FIGS. 19a-c and 20 a-b illustrate an embodiment of a process for addressing hierarchical pin assertions for model extraction.
[0033]FIGS. 21a-b illustrate an embodiment of a process for addressing assertions at input or output ports.
[0034] Overview
[0035] Disclosed embodiments of the invention are directed to a method and system to generate a timing model by reducing the timing graph. The method can generate a model that is accurate within a specified tolerance and is very efficient. Also described is an is approach for preserving and applying timing constraints/assertions to a model. In one embodiment, the timing constraints/assertions are viewed as part of the model, and a set of new timing constraints can be automatically generated as part of the model extraction process. Latch time borrowing and support for the application of original assertions can be accomplished by retaining some internal pins.
[0036] In an embodiment of the invention, model extraction is performed by simplifying the original timing graph. The simplification is accomplished by iteratively removing timing pins from the timing graph and combining timing arcs. This leads to a spectrum of models which allows for a tradeoff in model size and cpu/memory resources. For the sake of exposition, consider timing graph G as a three-tuple G=(P, D, C), where P is a set of pins, D a set of delay arcs and C a set of check arcs. Delay arcs and check arcs originate from and terminate at pins: D⊂(P�P), C⊂(P�P). Associated with each delay arc is a transition matrix which defines valid transitions between the source pin and the sink pin. Associated with each check arc is a transition matrix which defines valid rising or falling transitions between the signal pin and the reference pin. Each check arc has a type such as setup, hold, recovery, removal, etc. To illustrate the terminology and conventions used herein, an example timing graph representation of a simple D-type register is shown in FIG. 2a. Delay arc 202 is represented as a solid-line arrow and check arcs 204, 206 as dotted-line arrows. An example transition matrix for CLK→Q delay arc is shown in FIG. 2b. This matrix identifies transitional relationships between check arcs and delay arcs on input and output transitions. Delay/check values are associated with delay/check arcs. Delay or check values can be, for example, linear functions, lookup tables or delay equations.
[0037]FIG. 3a shows a high-level flowchart of a process for extracting a timing model according to an embodiment of the invention. At 302, a timing graph is received for processing. In one embodiment, this action is accomplished by copying the original timing graph generated by a timing engine to a new model graph. Any timing analysis tool can be employed to generate this timing graph, e.g., the BuildGates timing analysis tool available from Cadence Design Systems of San Jose, Calif. In one embodiment, the given timing graph is assumed to be cyclic. At 304, the model graph is reduced by removing timing pins and combining timing arcs. At 306, assertions within timing graph are automatically processed and reproduced in the extracted model. The assertions in the original circuit are automatically mapped to those in the model graph using internal pins, as described in more detail below. At 308, the timing model is extracted from the model graph.
[0038]FIG. 3b shows a flowchart of an embodiment of a process for implementing the model graph reduction action 304 of FIG. 3a. At 402, an identification is made of timing pins to process and of timing graph elements to exclude from the model reduction action. Examples of pins/elements to possibly exclude from reduction include anchor points, latch points, and assertion points. An anchor points are pins for which the model graph would become larger than the original timing graph if the anchor points were eliminated. The anchor pin is illustrated, for example, by pin 150 in FIG. 1. Latch points are excluded from reduction to ensure preservation of latch behavior. Examples of excluded latch points include the input and output pins, but not clock pins, of a latch element. Pins associated with an assertion or a constraint are excluded from reduction to preserve and apply original constraints.
[0039] At 404, the timing graph portion is processed for possible reduction, except with respect to the elements and pins identified for exclusion in 402. For the sake of exposition, timing models are divided into at least two parts comprising a combinational part that deals with interaction among delay arcs and are captured in the combinational model 412 and a sequential part that deals with interaction between delay arcs and check arcs that is captured in the sequential model 414. Special processes can also be defined to handle special types of arcs 416 that cannot be acceptably reduced using the standard models. For instance, a self-loop arc is an example of a special type of arc for which a separate process can be employed for reduction. The pins and arcs in the timing graph are processed with BFS (breadth first search) ordering until no further pins remain for processing (430). Multiple iterations of the reduction process may be performed to all or part of a timing graph.
[0040] The embodied timing model extraction process builds a timing model of a digital circuit for use with a static timing analyzer, in which a gray box timing model is generated from gate-level netlist by reducing the timing graph. This provides model accuracy including arbitrary levels of latch time borrowing, correct support for self-loop timing checks and capability to preserve original timing constraints. Also, cpu and memory resources required to generate the model scale well with size of the circuit.
[0041] The model extraction process is accurate, e.g., since the worst-case behavior of the original circuit is accurately preserved in the model. Any timing violation which occurs in the original circuit is reproducible in the model. Also, critical paths which change with respect to a change in input slew value are accurately reflected in the model. This provides better accuracy than prior approaches where critical paths are determined with one particular input slew value and later re-characterized for a combination of input slews and output load values. In addition, self-loop timing checks such as period and minimum pulse width checks are also preserved. Moreover, the model extraction process can be applied more efficiently, since in the embodied approach, extraction is based on a simple graph contraction rather than prior approaches that essentially required full-blown timing analysis to extract a model. Also, the model size can be reduced significantly, e.g., by retaining anchor points. Generating a gray box model also provides more visibility into the internal pins in the circuit as compared to black box modeling approaches. Internal pins allow for accurate modeling of latch timing borrowing behavior and register-to-register constraints. The embodied gray box model produces a model that is clock context independent—it is valid for clock waveforms different from the ones used to build the model. In an disclosed embodiment, path delays can be characterized with respect to input slews and output loads, while timing checks are characterized with respect to input slews and clock slews.
[0042]FIG. 3c shows en embodiment of an architecture for a model extraction mechanism 390 according to the invention. The model extractor mechanism 390 comprises four functional components. The model graph builder 391 copies the original timing graph from the timing engine 396 to a new model graph. The model graph reducer 392 is the extractor's core engine that simplifies the model graph. The model writer 393 writes out a timing model from the reduced model graph. Assertion handler 394 takes care of original timing constraints. Each of these functional components is described in more detail below.
[0043] Model Graph Builder
[0044] This section describes an embodiment of a process and mechanism for building a model graph. In this approach, all check arcs in the original timing graph are added to the new model graph. Most or all of the delay arcs in the original timing graph are copied to model graph, for example: (a) latch D->Q flush arcs; and (b) clock gating arcs (all arcs from clock gate input pin to clock gate output pin). In this embodiment, delay arcs and check arcs that are disabled by constraints such as set_disable_timing are not included in the model graph.
[0045] The model graph consists of objects associated with pins, delay arcs, and check arcs. Each of these objects has a pointer to the corresponding object in the original timing graph. A BFS traversal routine is employed which returns an array of pins sorted in BFS order from inputs to outputs. In order to avoid introducing a cycle which was not present in the original timing graph, BFS graph traversal routine should take into account latch flush arcs and clock gating arcs.
[0046] Model Graph Reducer
[0047]FIG. 4a shows pseudocode for an embodiment of process and mechanism for performing graph reduction. In this approach, the timing graph is reduced one pin at a time by visiting each internal pin in breadth first search (BFS) order. The reduction is repeated until no further changes are possible. Reasons for using BFS traversal include ensuring that incoming delay arcs to a pin have already been processed before the pin is removed, and that the delay arcs are characterized with respect to a minimum number of input slew values. removePin( ) is the main routine which performs the merge operations. The postProcess( ) routine takes care of delay arcs or check arcs which originate from primary input pins (or preserved internal pins) and terminate at primary output pins (or preserved internal pins). For such arcs, delay computation routines can be explicitly since no pin removal is performed for such arcs.
[0048] Pseudocode for an embodiment of the removePin( ) routine is shown in FIG. 4b. Section 472 makes the determination whether a particular pin should be removed from the model or excluded from the reduction process. Pseudocode for an embodiment of the retainPin( ) routine of section 472 is shown in FIG. 4c. Sections 474, 476, and 478 contain pseudocode for reducing the subject portion of the timing graph. For the sake of exposition, timing models can be divided into at least two parts. A combinational part deals with interaction among delay arcs and are captured in the combinational model. A sequential part deals with interaction between delay arcs and check arcs and are captured in the sequential model. Section 474 of the pseudo code in FIG. 4b is directed at reducing combinational models using the "s-merge" and "p-merge" operations. Section 476 is directed at reducing sequential models using the "backward-s-merge" operation. Section 478 is directed at reducing sequential models using the "forward-s-merge" operation. Each of these operations are described in more detail below.
[0049] Identifying Timing Graph Elements to Reduce or to Exclude from Reduction
[0050] This section describes an embodiment of a process and mechanism for determining whether a particular timing graph element should be included or excluded from the model reduction process.
[0051] The pins and arcs in the timing graph are processed with BFS ordering until no further pins remain for processing. Each element is subject to reduction unless excluded from the reduction process. Timing graph elements may be excluded from eligibility for reduction for a variety of reasons, such as to preserve certain identified types of behaviors/information in the resulting timing model or to ensure that the reduction process does not detrimentally increase the size of the timing model. The present approach may use heuristics to avoid blowup in model size such that the model size will be smaller than or equal to the original circuit size.
[0052] A first set of example elements of a timing graph element to exclude from reduction are timing pins for latches. Excluding the latch timing pins from removal in the timing model is helpful for preserving latch behavior. This occurs in part because the sense of transparency associated with latches can be useful for "time-borrowing", which is preserved if the input and output pins for a latch element are excluded from the reduction process. In is noted that in a present embodiment, the clock pin for a latch is not excluded from eligibility for reduction. Latch points can be identified by a number of techniques, including accessing structure information in the design or by analysis of latch profiles in the timing graph. Latch-based designs with many latch-to-latch connections are expected to benefit most from this optimization.
[0053] Other such pins can be excluded from reduction to preserve original timing behavior. Examples of such pins include: latch input pins, latch output pins, gated clock output pins, gated clock input pins, pins associated with assertions, and pins associated with output-to-output paths.
[0054] When pins are preserved, the slew values coming from input delay arcs to the pin are used to compute delay across the arcs originating from the pin. Pins associated with output-to-output paths refer to all internal pins fed by a "net pin". A net pin is a pin which connects to a primary output ("PO") port via a net arc. This preservation is used to capture the correct output loading dependency on output-to-output paths and to account for the correct delay across net arcs.
[0055] As another example, timing pins associated with assertions can also excluded from reduction. As explained in more detail below, assertions can be directly embedded into the timing model and associated with individual timing model elements. Excluding these elements from eligibility for reduction is helpful in retaining the association between an assertion and its associated timing graph element.
[0056] The goal of model extraction is to produce a model which is smaller than the original circuit. However, in some cases, removal of certain timing pins leads to a geometric blowup in the number of timing arcs. "Anchor points" refer to existing pins (e.g., internal pins) which, if removed, may lead to an increase in model size. To avoid having the timing model become larger than the original timing graph, such anchor points can be excluded from the reduction process. The number of delay arcs can be used to estimate the model size. In this approach, it is assumed that all the delay arcs make equal contribution to the final model size. Given this assumption, the identification of anchor points is similar to the problem of finding a set of pruning pins in the context of static circuit optimization. The objective is to minimize the number of delay arcs, not the number of variables. Also, since it is desirable to characterize the delay arcs with respect to a minimum number of input slew values, this approach will not remove internal pins at random without first processing their incoming delay arcs. This constrains the order in which anchor points are identified and retained.
[0057] To identify anchor points, a Gain value is determined for a pin as follows:
Gain =(#incoming delay arcs�#outgoing delay arcs)−#incoming delay arcs−#outgoing delay arcs.
[0058] This value represents an increase in the number of delay arcs if the pin is removed. In one embodiment, any pin that has a positive gain and is observable is a candidate for an anchor point. A pin is observable if there exists a path from the pin to a primary output or to a preserved pin. In this approach, observability prevents anchor points from being formed in the transitive fanin cone of pins that will eventually be removed. For example, register input pins are not observable and may be eventually removed.
[0059] For example, in FIG. 1, there are six delay arcs in the original timing graph 100 before removal of the internal pin 150 (i.e., arcs 102, 104, 106, 108, 110, and 112). If the pin 150 is removed, the number of delay arcs becomes nine (i.e., arcs 120-136), leaving a gain of 3. This gain value can be identified using the above equation in which the number of incoming delay arcs is equal to three (arcs 102, 104, and 106) and the number of outgoing delay arcs is also equal to three (arcs 108, 110, and 112). Thus, Gain=((3�3)−3−3))=3 for pin 150. Therefore, since the gain value for internal pin 150 exceeds zero, pin 150 can be considered an anchor point that is excluded from the reduction process.
[0060] Once anchor points are identified, they are valid for a particular pass. One pass constitutes a complete sweep of all internal pins. Anchor points should be re-identified in the subsequent passes.
[0061] The threshold gain value for determination of an anchor point can be adjusted to obtain or vary performance expectations. With a high enough value for the gain threshold, all anchor points can be removed from the design. The maximum number of anchor points is identified by setting the gain threshold to a value of "1". To ensure that the resultant timing model will not exceed to the size of the original timing graph, the gain threshold value can be set to 1.
[0062] It may happen that when the gain threshold is set to a high value, the number of delay becomes smaller than that for a smaller gain threshold although the final model size is larger. This happens because some delay arcs are "denser" than others in terms of transition matrix. This occurs because the assumption that all delay arcs make equal contribution to the final model size is not necessarily valid beyond the local scope. However, this does not affect the cost computation associated with anchor points because the number of immediate incoming/outgoing delay arcs are viewed this approach, not all the delay arcs.
[0063] For a more global view, different density or weights of delay arcs are also taken into consideration when determining anchor points.
[0064] Reducing Combinational Models
[0065] This section describes an embodiment of an approach for implementing section 474 of FIG. 4b to process combinational models. Two operations in this approach for reducing the timing graph are the serial-merge ("s-merge") and the parallel-merge ("p-merge") operations.
[0066] In this embodiment, the s-merge operation takes two delay arcs (d1 and d2) in series and creates a new arc (d3) from the source of the first arc (d1) to the sink of the second arc (d2) to represent the "sum" of d1 and d2. s-merge is a fundamental reduction operation that allows removal of internal pins from a timing graph without losing accuracy. When s-merge is performed, a new arc delay for the merged arc is computed.
[0067] Referring to FIG. 5b, consider two arcs arc1 502 and arc2 504 which are in series across internal pin 508. Arc1 502 and arc2 504 have the delay values shown in FIG. 5a. These two arcs are serially merged by removing the internal pin 508. The new arc3 506 resulting from s-merge between arc1 502 and arc2 504 has a delay calculated by summing the individual delays for arc1 502 and arc 504.
[0068] Note that in this embodiment, a "lazy" slew computation is used so that output slew and arc delay are computed only for new input slew values which can lead to changes in delay and output slew values. Also, the load-dependent delay computation can be confined to the last arc that drives an output port.
[0069] The p-merge operation takes two parallel arcs and merges them into a single arc. The p-merge operation can lead to a substantial reduction in model extraction time as it reduces the number of arcs which need to be processed in the next stage of computation. In one embodiment, given two parallel delay arcs, p-merge chooses the "worst" of the two arcs and allows the other arc to be discarded
[0070] Referring to FIG. 6b, consider two parallel arcs arc1 602 and arc2 604 that originate from pin 600 and end at pin 608. The delay values for these arcs are set forth in the tables of FIG. 6a. It is desired to merge the information from two arcs using a single arc3 602.
[0071] Assume that the arc delay d1 for arc1 602 is less than the arc delay d2 for arc2 604 (i.e., d1<d2). If a late path is of interest, then the p-merge action picks the output slew and arc delay from the worst-case arc, which in this example is arc2 604 since it has the greater arc delay value. If both early and late paths are of interest, then p-merge can pick up the worst early delay of d1 from arc1 602 and the worst late delay of d2 from arc2 604. The arc 602 will then have two delays after p-merge: early delay of d1 and late delay of d2.
[0072] In one embodiment, resultant arc3 606 is not a new arc—it is the arc selected to remain from the set of parallel arcs 602 and 604 to reduce in the p-merge process. Thus, for a p-merge operation conducted upon arcs 602 and 604, if the late path is of interest and it is assumed arc2 604 has a greater arc delay value than arc1 602, then after the p-merge process, arc1 602 is removed and only arc2 604 remains as the resultant arc3 606. In an alternate embodiment, arc3 606 is an entirely new arc formed with the required properties based upon the selected arc values to preserve based upon the p-merge operation.
[0073] Note that the p-merge operation can be configured to take into account critical paths that change due to a change in input slew values. Consider the timing graph in FIG. 7 where the critical path changes from A to B to C as input slew value changes from s1 to s2 to s3. The resulting arc delay after two p-merge operations correctly reflects the change in the critical path. Thus, the present approach is not locked into a particular critical path that is originally selected, but can dynamically determine the critical path, e.g., based upon a change in input slew value.
[0074]FIG. 8 illustrates the series of p-merge and s-merge actions that can be performed to reduce a portion of a timing graph. Initially, the timing graph portion includes a first timing pin 800 that has a delay arc 810 connected to a second timing pin 804. Another delay arc 806 extends from timing pin 800 to an internal timing pin 802. A delay arc 808 extends from internal timing pin 802 to timing pin 804.
[0075] It can be seen that delay arc 806 and delay arc 808 extend serially through internal timing pin 802. Therefore, the s-merge action can be performed to reduce these two arcs into a merged delay arc 812. If delay arc 806 has a delay value d1=1 and delay arc 808 has a delay value d2=2, then the delay value d4 for the s-merged arc 812 is equal to the sum of the two delay values (i.e., d4=d1+d2=1+2=3). After the s-merge operation, the internal timing pin 802 has been eliminated and the two delays arcs 806 and 808 has been merged into a single delay arc 812 having the delay value d4=3.
[0076] At this point, the merged delay arc 812 is in parallel with original delay arc 810, since both extend from the same input timing pin 800 to the same output timing pin 804. A p-merge operation can be performed to further reduce these two arcs into a single merged arc 810. If a late path is of interest, then the merged arc 810 is associated with the delay value for whichever arc 810 or 812 that has the greater delay value. Here since arc 810 has a greater delay value than its parallel arc 812, the merged arc 810 is associated with the delay value for arc 810 (i.e., delay value d5=(greater of d3 or d4)).
[0077] When the reduction operations have completed, the final timing model includes only a single delay arc and two timing pins, whereas there existed three delay arcs and three timing pins in the original timing graph portion.
[0078] It is noted that when merging is performed, e.g., either p-merge and s-merge, the associated transition matrixes may also change.
[0079] Sequential Models
[0080] This section describes an embodiment of an approach for implementing section 476 and 478 of FIG. 4b to process sequential models. Sequential models involve both delay arcs and check arcs. Check arcs can be classified into at least two main groups. One group is called the "setup" group where the data signal is expected to arrive before the reference or clock signal. Examples of "setup" group are setup, recovery, skew, clock separation, etc. The other group is called the "hold" group where the reference signal is expected to arrive before the data signal. Examples of "hold" group are hold and removal.
[0081] Registers or flip-flops are removed and, as noted above, part of latch information is retained to preserve latch behavior. In this embodiment, all latch input pins and latch output pins are retained. The operations associated with the removal of sequential elements are similar to those for combinational models. To correctly model the interaction between delay arcs and check arcs, two different s-merge operations are used: forward s-merge 478 and backward s-merge 476. Sequential p-merge is essentially the same as combinational p-merge. The difference is that only check arcs of the same type are merged.
[0082] A forward s-merge operation is used when register/latch clock pins are removed. When a delay arc and a check arc meet at a clock pin, a new check arc is created to represent a new check value between the old data signal (signal end of the check arc) and the new clock signal (source of the delay arc). Let d denote the delay value on the delay arc and c the check value on the check arc. In one embodiment, when merging the two arcs for the setup group the new check value becomes c−d and for the hold group, the new check value becomes c+d.
[0083]FIG. 9 illustrates the forward s-merge operation. This figures shows the timing graph for a register in which a check arc 902 and a delay arc 904 are associated with a clock pin 906. The forward s-merge operation is used to reduce this timing graph by merging the two arcs and removing the clock pin 906. The merged arc 908 is a check arc having the check value c−d for setup group and c+d for hold group.
[0084] The backward s-merge operation is used when register input pins are removed. When a delay arc and a check arc meet at a data pin, a new check arc is created to represent a new check value between the source of the delay arc and the old clock signal (reference end of the check arc). For the setup group, the new check value becomes c+d and for the hold group, the new check value becomes c−d.
[0085]FIG. 10 illustrates the backward s-merge operation. This figure shows the timing graph for a register in which a check arc 1002 and a delay arc 1004 meet at an input pin 1006. The backward s-merge operation is used to reduce this timing graph by merging the two arcs and removing the input pin 1006. The merged arc 1008 is a check arc having the check value c+d for setup group and c−d for hold group.
[0086] Self-Loop Check Arcs
[0087] There are certain "self-loop" check arcs where both the signal end and the reference end point to the same pin. Such timing checks include, but are not limited to, minimum pulse width (MPW) and minimum period (MP) checks on clocks. By using forward and backward s-merge operations, such self-loop check arcs can be modeled with correct clock path delays (including asymmetrical rise/fall) and slew propagation.
[0088]FIG. 11 shows an example of a timing graph fragment for a clock path having a MPW self-loop check arc 1102 . An incoming delay arc 1104 is shown connected to the same pin 1106 as both the signal and reference end of the self-loop check arc 1102.
[0089] Self-loop check arcs may be "expanded" as a check arc with no self-loop by conceptually duplicating the incoming delay arc. The delay arc 1104 is duplicated to produce two arcs d1 1104 a and d2 1104 b. By connecting each end of arc 1102 to the duplicated arcs 1104 a and 1104 b, the check arc 1102 is transformed such that it is longer a self-loop arc.
[0090] Thereafter, a backward s-merge can be performed on delay arc d1 1104 a and the check arc 1102 to produce a merged check arc 1106. Then, a forward s-merge operation is performed on delay arc d2 1104 b and check arc 1106. This leads to another self-loop check arc 1108 at port CK that correctly reflects the clock path delay and the slew propagation. Note that no delay arcs or pins need actually be duplicated here. The duplication in FIG. 11 is for the sake of exposition only.
[0091] Delay Calculations and Load Characterizations
[0092] In one embodiment, delay calculations are performed during s-merge and p-merge operations in which delays are computed over a fixed range of slew, load, and/or data values. For example, load ranges can be utilized for delay arcs which terminate at output ports. The ranges may vary from one delay arc or check arc to the other.
[0093] It is desirable for accurate ranges of load and slew values be obtained. For table-based libraries (such as TLF, .lib, or ALF), the ranges can be obtained as specified in library templates. For equation-based libraries (such as OLA) the ranges can be characterized. The following sections describe embodiments of approaches for obtaining slew/load range values.
[0094] For table-based libraries, the load ranges can obtained by looking at the table templates associated with the delay arc. Consider a delay arc with the following template(e.g., from a TLF library):
Timing_Model("Model0" (Spline (Input_Slew_Axis 0.0500, 0.3000, 0.5500, 0.8000, 1.0500) (Load_Axis 0.0820, 0.1639, 0.3279, 0.6557, 1.3115, 2.6230, 5.2459) data() ) )
[0095] The initial load range for this template consists of the following 7 values:
[0096] 0.0820, 0.1639, 0.3279, 0.6557, 1.3115, 2.6230, 5.2459
[0097] An approach to determining the slew/load ranges is to establish a tolerance value to specify a desired accuracy value for the range. In this approach, every value in the initial range is evaluated to check if it can be dropped while meeting the desired accuracy level. Once a value is dropped from the range, the delay and the output slew values need to be interpolated using the points from its neighbors. If the interpolated delay and output slew values are within the specified tolerance limit, a value can be dropped from the range. The higher the tolerance percentage in this approach, the more values can be removed from the range. This approach reduces both the input slew values as well as the output load values to process.
[0098] For equation-based libraries, iterative weighted bi-sectioning technique can be used. The process starts with an initial range {0, MaxVal}. MaxVal can be the maximum output load or input slew value and can be specified by the user. The range is split into two ranges at midpoint. Then, out of all the existing sub-ranges, the one with more weight is selected. The weight is the gradient in output delays (or output slews) between the two endpoints of the range. This bi-sectioning continues until the desired number of data points are obtained. Once a range has been determined, it can be further reduced by tolerance-based pruning proposed for table-based libraries.
[0099] In another approach, if the number of load values in a range exceeds the maximum number of output load (N), then the range can be pruned by selecting N values with highest distances to adjacent neighbors. If the range is sorted in ascending order, the distance for the (i)th value in the range is found by the difference in load values between the (i+1)th value and the (i−1)th value. The distance for the first value in the range is assumed to be infinity and the distance for the last value half of infinity. This is to give higher weights to end points (highest weight is given to the first value in the range). Suppose N=6 for the above example. The distance table is shown as follows:
Load Value 0.0820 0.1639 0.3279 0.6557 1.3115 2.6230 5.2459 Distance Inf 0.2459 0.4918 0.9836 1.9673 3.9344 Inf/2
[0100] By picking 6 values with highest distances, the range can be pruned to
[0101] 0.0820, 0.3279, 0.6557, 1.3115, 2.6230, 5.2459
[0102] Multiple Fanin and Fanout Considerations
[0103] Input ports may lead to reconvergent paths and this can create problems in p-merge if delay tables associated with reconvergent paths have different slew ranges. Likewise, output ports may have multiple fanin paths arising from designs containing multiplexors. For this reason, it is appropriate to use the same slew range for all delay arcs and check arcs emanating from an input port and the same output load range for all delay arcs terminating at an output port. The ranges may differ from one input/output port to the other. To accommodate this, the slew(load) ranges are characterized for all delay arcs and check arcs which emanate from (terminate at) input(output) ports. Then, all the slew/load values are merged into a list for each input/output port.
[0104] Check Arc Considerations
[0105] The BFS traversal approach of the present embodiment ensures that all the input delay arcs to a pin have already been processed before the pin is removed. Check arcs, however, sometimes need special consideration since, to completely characterize a check arc, a range of slew values should be available at both the signal end and the reference end. In some circumstances, the BFS traversal does not guarantee that both the signal end and the reference end of all check arcs are processed before forward s-merge or backward s-merge operations.
[0106] For example, consider the timing graph of FIG. 13. When pin c1 is removed, the range of slew values coming from the signal end (d2) of the check arc is not available. In one embodiment, the check arc is characterized with respect to all possible slew values (in most cases, fewer than 6 slew values are sufficient to characterize a check arc). Later when pin d2 is processed, the check arc is re-characterized for appropriate slew values. In an alternate embodiment, the range of slew values at d2 after removal of c1 is estimated. Only when pin d2 is processed does the slew range becomes available. Then, the check arc delay can be recomputed by performing interpolation.
[0107] Insertion Delays
[0108] An insertion delay refers to a delay from a clock source port to internal clock pins that belong to registers and latches. Insertion delay enables the characterization of fast (early) and slow (late) paths through a clock tree embedded within a cell. To compute insertion delays, additional computation can be performed at internal clock pins. In one embodiment, the insertion delay is computed when the process encounters a clock pin at a register or latch. The following is pseudocode to compute the insertion delay in one embodiment of the invention:
/* pin is an internal clock pin for a register or a latch */ computeInsertionDelay(pin) { paths = tracePathsToClockSourcePin(pin); for each path in paths { addInsertionDelay( src pin of path, path); } }
[0109] A path is a list of delay arcs. The addInsertionDelay( ) procedure computes a path delay and stores that to the path originating pin which is the clock source port. The s-merge and p-merge operations described earlier can be used in this routine. In effect, when a clock pin for a latch or register is encountered, the process traces paths all the way back to the original clock source and tracks the one pin with the worst-case behavior.
[0110] Reduction Example
[0111]FIG. 14 illustrates an example of graph reduction on a circuit with two registers 1350, 1352 and one latch 1354. In this example, arcs 1306 and 1307 are merged into check arc 1308 using the backwards s-merge operation. Arcs 1301, 1302, 1303, 1304, and 1305 are merged into self-loop check arc 1300 using a combination of s-merge, backward s-merge, and forward s-merge operations. Arcs 1309 and 1310 are merged into arc 1311 using the forward s-merge operation. Arcs 1305, 1312, and 1313 are merged into arc 1314 using the s-merge operation. Note that arc 1305 was involved in two separate sets of operations that resulted in both arcs 1300 and 1314 in the final timing model. Arcs 1310 and 1313 are merged into arc 1319 using the s-merge operation.
[0112] Since pins 1330 and 1332 are the input and output pins for a latch 1354, they are not removed from the model. The final model includes the two internal pins 1330 and 1332 to preserve the latch behavior. Note that the setup/hold checks on reg1 1352 are modeled as self-loop setup/hold check arcs on clock C.
[0113] Model Writer
[0114] This section describes an embodiment of a process and mechanism for writing the timing model. The model writer mechanism traverse or walks the reduced model graph to dump out the pins, the delay arcs and the check arcs in the desired format.
[0115] To reduce model size, the timing models can be shared among different delay arcs and check arcs. In one approach, this is accomplished by hashing delay tables. In addition, model size can be reduced by sorting and reducing delay tables. Although slew values can be sorted and duplicates removed in the model graph reducer, some final tuning may be needed if the model reducer misses some optimization because it considers all transition possibilities (rise, fall, early, late). Given the values in the delay table, the model writer mechanism can examine the slew values which appear in the axis and perform sorting and removal of duplicates.
[0116] As described in more detail elsewhere, the model writer mechanism can: a) preserve all internal pins associated with exceptions; b) store exceptions at model I/O ports to dummy internal pins; and, c) write out new exceptions as part of the model. This facilitates the preservation of assertions and constraints since exceptions are incorporated into timing model. In one embodiment, only user assertions which are present on the original circuit will be written as part of the model.
[0117] Assertion Handler
[0118] This section describes how assertions are processed for model extraction in one embodiment of the invention. For purposes of explanation, assertion handling is described in the context of graph reduction for model extraction and in the context of internal pins. However, it is noted that the present inventive concepts for handling assertions are equally applicable to other model extraction approaches and non-internal pins, e.g., handling assertions for path-tracing for black box models, and thus is not to be limited to the specific embodiment(s) disclosed herein for illustration, and for extraction from different sources of data, e.g., extracting the timing model from a netlist, timing graph, etc.
[0119] Examples of "generated assertions", which are assertions that come from tools such as a budgeter include the following:
[0120] clock arrival time
[0121] clock required time
[0122] data arrival time
[0123] data required time
[0124] slew time
[0125] constants for timing
[0126] drive resistance
[0127] drive cell
[0128] input delay
[0129] output (external) delay
[0130] Examples of "user assertions", which are assertions set by the user include the following: false path, multicycle path, or disable timing.
[0131] One of the problems in known model extracting approaches is that original assertions/constraints are difficult to apply to the extracted model. The loss or name mutation of internal pins contributes to this difficulty.
[0132]FIG. 15 illustrates this drawback of the known approaches. Consider an original netlist 1502 having a circuit block 1506 instantiated as an instance i1 with pins a and b. An assertion 1508 at the top level exists as follows: "set_false path -from i1/a -to i1/b". If an extracted timing model is instantiated in a different instance, the assertions need to be changed or sourced in a different manner to reflect changes in pin names. In conventional model extractors, a manual process is employed to ensure proper association of the assertion 1508 to the extracted model 1510. In this example, the assertion 1508 would be converted to a revised assertion 1508′ as follows:
[0133] set_false_path -from i2/a -to i2/b
[0134] Since a typical circuit design contains a very large number of circuit elements (potentially numbering in the millions), and these elements must be searched and reviewed to ensure that assertions are properly associated with corresponding elements, it is evident that any process that relies upon manual correction and association of assertions would be a tedious and time-consuming procedure that is fraught with potential for introducing or overlooking errors. In addition, once the assertions has been corrected, they would be stored in a separate storage location 1522 from the storage location 1526 for the timing model 1524. This means that at least two separate data storage locations would have to be accessed to retrieve the model information for a timing model portion.
[0135] To address these problems in one embodiment of the invention, internal pins associated with assertions are retained. This allows the original assertions to be applied to the model with no or little modification, including assertions that span multiple blocks. Also, the present approach makes it easy to preserve and apply the original timing constraints/assertions. The timing constraints/assertions are viewed as part of the model, and a set of new constraints can be generated automatically as part of the model extraction process. The support for timing constraints is important for top-down hierarchical flows.
[0136]FIG. 16 illustrates an embodiment of the invention. Here, the timing graph portion 1602 includes a circuit block between pins a and b. An assertion 1608 exists similar to the previous example: "set-false_path -from a -to b". However, when model extraction is performed, pins a and b are purposely excluded from removal, renaming, or other change since assertion 1608 has been identified as being associated with these pins. Thus, pins a and is b are retained in the extracted model graph 1610. This approach inherently preserves the validity and applicability of the original assertion 1608 to the corresponding pins a and b in the extracted model.
[0137] Moreover, the assertions can be automatically written and placed into the model graph 1610 and timing written out to the timing model 1624. This information can be stored, for example, as a cell-level attribute in the timing model. The stored version of the timing model 1624 therefore includes both timing data as well as associated assertion data corresponding to the timing model. The model more accurately ensures the integrity of original assertions. Assertions become part of the model and are applied automatically when model is read in.
[0138]FIG. 17 shows a flowchart of an embodiment of a process for processing assertions. At 1704, a determination is made whether a particular pin is associated with an assertion. If so, then the pin is retained and is removed from eligibility for removal (1706). At 1708, the identified pin is associated with the assertion such that when the model is written, the assertion is automatically embedded into the model. At 1710, the normal model extraction process continues.
[0139] Referring to FIG. 18, consider the situation when an assertion spans multiple blocks. Shown are two blocks 1802 and 1804 with a first pin i1802/a in block 1802 and a second pin i1804/b in block 1804. Assume that an assertion exists as follows: "set_false_path -from i1802/a -to i1804/b".
[0140] In the present embodiment, assertions that extend between multiple blocks cause all associated pins in the respective blocks to be retained in the timing model. Thus, pins i1802/a and i1804/b would be retained during the model extraction process for blocks 1802 and 1804. As with the situation involving pins for a single block, this approach of retaining assertion-related pins for multiple blocks help to ensure that timing behavior will be appropriately preserved during model extraction. The assertion information is automatically written to the timing model after extraction. In one approach, if assertions span more than one block, then user may not make changes to such assertions after the model is read in.
[0141] Hierarchical Pin Assertions
[0142] There may be at least two types of pins that appear in a circuit: instance pins and hierarchical pins. The hierarchical pin establishes a hierarchical boundary; when a signal crosses a hierarchical pin, it moves from one hierarchy to another. Hierarchical pin is a place holder for boundary crossing information and has no underlying physical pin representation.
[0143] Assertions may be associated with hierarchical pins as well as instance pins. For many timing tools, hierarchical pins may not appear when a timing graph is built. This may present a problem if there is an assertion associated with hierarchical pins. In one embodiment of the invention, if assertions are associated with hierarchical pins, the timing graph is modified to insert newly created internal pins for the hierarchical pins, and the assertions are re-expressed in terms of these new pins. This mapping is used to support different types of assertions in full generality. Zero delay arcs that preserve slews (i.e., output slew=input slew) extend to or from these new "dummy" internal pins.
[0144] Consider the example circuit shown in FIG. 19a. Each rectangle in the figure represents an instance. Shown are instances 1902, 1904, 1906, and 1908. Pins are represented as black dots. shown are instance pins 'a', 'b', 'c' and 'd'. Pin 'h' is a hierarchical pin.
[0145] The timing graph for this circuit is shown in FIG. 19b. Here, hierarchical pin 'h' can be accessed through two delays a->c and d->b.
[0146] Consider if there is a through pin assertion on pin 'h' as follows:
[0147] set_false path -from a -through h -to c
[0148] To capture this assertion in the extracted model, two new internal pins are introduced in the model. These new pins can be considered "dummy" internal pins. In this example, two pins are used because a->b and a->c delays may differ from d->b and d->c delays. The expanded timing graph with the new internal pins 'h1' and 'h2' looks as shown in FIG. 19c. When new pins h1 and h2 are introduced, new arcs a->h1 and d->h2 are also introduced. Note that in this example, a->h1 and d->h2 denote zero-delay arcs. h1->c and h2->b delays are the same as a->c and d->b delays in the original timing graph, respectively.
[0149] Since pin 'h' is split into two pins 'h1' and 'h2', the original assertion is transformed to the following:
[0150] set_false path -from a-through h1 -to c
[0151] set_false_path -from a -through h2 -to c
[0152] Two actions involved in supporting hierarchical pin assertions are: 1) timing graph expansion and 2) model assertion writer.
[0153] Timing graph expansion refers to the process of inserting new internal pins in the timing graph to correctly capture hierarchical pin assertions. This can be done by iterating through all the delay arcs and searching for hierarchical pins that have assertions. If such hierarchical pins are found on a delay arc, then a greedy "find or create" strategy can be used to expand the timing graph. FIG. 12 gives a pseudo code for such a process. There are two mapping tables in the code:
[0154] 1. 'map_table' maps a hierarchical pin to one or more newly created internal pins (one-to-many mapping). This is used in the model assertion writer.
[0155] 2. 'visited' maps a hierarchical pin to the most recently created internal pin (one-to-one mapping).
[0156] Consider the timing graph shown in FIG. 20a. The hierarchical pins are shown in parentheses on the delay arcs. After timing graph expansion, the new timing graph becomes as shown in FIG. 20b.
[0157] The contents of the map_table for this example is as follows:
[0158] h1: h11, h12
[0159] h2: h21, h22
[0160] h3: h31, h32
[0161] The model assertion writer refers to the mechanism for traversing the model data and writing the assertion information associated with pins in the model. If hierarchical pin assertions are not supported, then the assertion writer can simply traverses all of given hierarchies and writes out assertions at all module ports and all instance pins. In one embodiment, no global assertions such as clock definitions are written, e.g., because in certain circumstances, such assertions may lead to an infinite loop during the build of the model. Also, in an embodiment, no electrical port assertions are written.
[0162] Implementing hierarchical pin assertions may result in the change of pin names as well as the creation of additional assertions. Both of these actions can be performed using the mapping table from the previous action of expanding the timing graph. For example, a callback function can be defined to perform this action similar to how it can be done for sourcing assertions.
[0163] Consider the following assertion where pin 'a' is a hierarchical pin which is split into two internal pins 'a1' and 'a2'.
[0164] set_false_path -from a -to b
[0165] The assertion writer maps this assertion to the following assertions:
[0166] set_false_path -from a1 -to b
[0167] set_false_path -from a2 -to b
[0168] Port Assertions
[0169] Special considerations may be taken with respect to assertions on I/O ports. It is often desirable for the assertions associated with the model to be sourced automatically when the model is used and removed automatically when the model is removed or replaced. In certain circumstances, the assertions on I/O ports make the removal process difficult. For this reason, in one embodiment, the assertions on I/O ports are moved to internal pins using a similar graph expansion technique of the previous section. This allows to model not to have assertions directly attached to input and output ports, making the model more self-contained.
[0170] For assertions on an input port or a bidi input part, a new "dummy" internal pin is created for this input port and the input port assertion is transferred to this pin. The new internal pin drives all the pins that were driven by the input port and is driven by the input port through a zero-delay arc. Also, all check arcs associated with the input port are now associated with the new internal pin.
[0171] An example of this expansion is shown in FIG. 21a. Here, the original graph 2102 includes an input port a having arcs 2104 and 2106 to pins b and c, respectively. Assume that there is an assertion associated with port a. The modified graph 2110 includes a new internal pin "a_IN_ASRT" associated with arcs 2104 and 2106. The assertion that was associated with port a is now associated with pin a_IN_ASRT. A new arc 2112 is created that extends from pin a to pin a_IN_ASRT. This new arc is created with a zero delay value such that output slew is the same as input slew.
[0172] Assertions on an output port or a bidirectional output part are handled in a similar manner. An internal pin is created such that all the delay arcs feeding the output port now feed the internal pin. To preserve the dependency on output load at the port, three-dimensional tables are created for all delay arcs coming into the new internal pin.
[0173] Consider the example shown in FIG. 21b. The original timing graph 2150 has a delay arc 2152 extending from pin a to output pin c and a delay arc 2154 extending from pin b to output port c. The modified graph 2160 includes a new pin 'c_OUT_ASRT', which is the new internal pin to which the port assertions are transferred. A new zero delay arc 2162 is created from pin c_OUT_ASRT to the output port c such that output slew is the same as input slew. Note that the arc 2152 from pin a to pin c_OUT_ASRT and the arc 2154 from pin b to pin c_OUT_ASRT can be associated with three-dimensional delay table(s) to capture the load dependency at port c.
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|U.S. Classification
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Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MOON, CHO WOO;KRIPLANI, HARISH;BELKHALE, KRISHNA PRASAD;REEL/FRAME:013572/0773
Effective date: 20021205
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text:
How Water Went on Sale and Why We Bought It
Bloomsbury Publishing PLC, Hardcover, 9781596913714, 248pp.
Publication Date: May 13, 2008
An incisive, intrepid, and habit-changing narrative investigation into the commercialization of our most basic human need: drinking water.
Having already surpassed milk and beer, and second now only to soda, bottled water is on the verge of becoming the most popular beverage in the country. The brands have become so ubiquitous that we're hardly conscious that Poland Spring and Evian were once real springs, bubbling in remote corners of Maine and France. Only now, with the water industry trading in the billions of dollars, have we begun to question what it is we're drinking and why.
In this intelligent, eye-opening work of narrative journalism, Elizabeth Royte does for water what Eric Schlosser did for fast food: she finds the people, machines, economies, and cultural trends that bring it from nature to our supermarkets. Along the way, she investigates the questions we must inevitably answer. Who owns our water? What happens when a bottled-water company stakes a claim on your town's source? Should we have to pay for water? Is the stuff coming from the tap completely safe? And if so, how many chemicals are dumped in to make it potable? What's the environmental footprint of making, transporting, and disposing of all those plastic bottles?
A riveting chronicle of one of the greatest marketing coups of the twentieth century as well as a powerful environmental wake-up call, Bottlemania is essential reading for anyone who shells out two dollars to quench their daily thirst.
"Fantastic." – Michiko Kakutani, The New York Times
"Ingenious.... Amiably, without haranguing or hyperventilating, this veteran environmental writer has produced what could be, assuming enough people read it, one of the year's most influential books." - Boston Globe
"Royte's lively investigation of water politics will leave you ashamed to drink out of plastic, uneasy about the tap, and impressed by her ability to synthesize complicated material into such a witty and engaging book." —Entertainment Weekly "An easy-to-swallow survey…. after you read it you will sip warily from your water bottle (whether purchased or tap, plastic or not), as freaked out by your own role in today's insidious water wars as by Royte's recommended ecologically responsible drink: "Toilet to tap."" —Lisa Margonelli, New York Times Book Review
"Light and easy-to-read narrative…lots of interesting factoids…" —Providence Journal-Bulletin
"At a time of climate change and increasing risks to global water supplies, we must change the way we think about this crucial resource and begin treating it as a public good to be preserved, rather than the equivalent of an oil deposit or timber forest, ripe for corporate exploitation." —New Scientist
"An intriguing look at a totem of the ultramodern, perhaps selfish, way we live now" —Time Out Chicago
"a well-balanced, interesting and instructive book about our fundamental human need to drink water" —Chicago Sun Times
"Seamlessly blending scientific explanation and social observation" —LA Times Book Review
"Bottlemania makes the case that it's not in our interests to let private multinational corporations float their boats on our nation's water. That's not democracy, it's dam-ocracy, and it could damn us all if we let their unquenchable thirst for profit take precedence over our right to clean, safe, free drinking water." —Kerry Trueman, Huffingtonpost.com
"An intrepid, intelligent analysis of Americans' raging thirst for bottled water." —BookPage
"An essential, if somewhat disturbing, read." —VeryShortList.com
"A breezy, accessible history of water through the ages....a good account of the tensions in the little town of Fryeburg, Maine." —New York Post
"A sharp indictment of the bottled-water industry" —New York Observer
"Informative" —Meghan O'Rourke, Slate.com
"Compelling and dynamic" —Library Journal
"Entertaining and eye-opening" —Publishers Weekly
"Bottlemania is eye-opening and informative; you will never look at water – either "designer" or tap – in quite the same way. Royte demonstrates how everything is, in the end, truly connected." —Elizabeth Kolbert
Royte deserves credit for her tenacity and well-balanced approach….Lively investigative journalism." —Kirkus Reviews
One of Entertainment Weekly's 10 Best Non-Fiction Books of 2008

subset: commoncrawl


text:
Hey Friends, I just wanted to share a few pics with you, as I'm getting the front porch readied for my favorite month... October! I've had some mums out, and my door basket decorated for Fall, but I wanted to wait and share it all with you when I had my French Goat Cart decorated. I was going to use real pumpkins, but I decided to repaint some of my faux stash, and just ended up with them instead.
Friday, October 2, 2015
Wheelbarrows, Wagons, and "Hoo" Else?
Posted by Debra Oliver at 8:37 AM 15 comments:
Labels: Autumn, fall, faux pumpkins, goat cart, kitchen, owls, pumpkins, wheelbarrow
Thursday, October 1, 2015
Share Your Style #33
Welcome Friends,
Glad you're here to Share Your Style!
First, I have 3 great features from last week,
then please read on, I have a little blogging news.
Posted by Debra Oliver at 8:00 AM 34 comments:
Labels: Autumn, fall, Share Your Style
Monday, September 28, 2015
Kitchen China Cupboard for Fall
Before we moved to this house, my kitchen china cupboard, had always been just that... a china cupboard. It held china, and some colored crystal and a few antique floral teapots. It never changed, no matter what the Season or Holiday. I had lots of other places to "play" and decorate, so this one I left alone...
Posted by Debra Oliver at 11:27 AM 23 comments:
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text: Summer vacation at Ruka, which is really peaceful during the summer. I have stayed at Rukavillage several times and it never lets down. Spacious apartment with modern furniture, well equipped kitchen. Clean, spacious bathroom and small sauna. The restaurant in the hotel building closes early summertime, but there are several options in the neighborhood.


text:
inFOCUS Quarterly
Fall 2015
Twenty-Five Years Since the First Gulf War
The JPC on
Top Research Issues and Regions
Most Viewed
February 19, 2013
A Gaza military court on Tuesday accepted the appeal by two militants convicted last year of the kidnap and murder of an Italian national, reducing their sentences from life to 15 years.
"The High Military Court has accepted the appeal presented by (Mahmud) al-Salfiti and (Tamer) al-Husasna to reduce their sentence from hard labour and life, to 15 years," said the judge in a brief hearing.
The two men, both former police officers, were convicted in September 2012 for the kidnap and murder of Italian activist Vittorio Arrigoni and sentenced to life imprisonment.
They filed an appeal asking for the murder conviction to be dropped.
"We asked in our appeal for the conviction for murder and abduction to be dropped to only abduction," their lawyer Mohammed Zarqut told AFP.
It was not immediately clear whether the court had agreed to drop the murder charge as requested in the appeal.
Arrigoni, 36, a long-time member of the pro-Palestinian International Solidarity Movement, was kidnapped on April 14, 2011.
In a video, a previously-unknown Salafist group threatened to kill him within 30 hours if Gaza's Hamas rulers failed to free a group of jihadist prisoners.
But the security forces found his body shortly afterwards in an abandoned house in northern Gaza.
Two other men were also convicted of involvement in the case, with Khadr Faruk Jerim, also a former policeman, receiving 10 years for kidnapping while Amer Abu Ghola was jailed for a year for providing the house in which Arrigoni was found hanged.
All four were members of a radical Salafist group.
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Photos: A look at the career of the Cowboys' Jason Witten
Photo: BRENDAN SULLIVAN/Staff Photograp
Classic Jason Witten. The Cowboys' tight end punishes Redskins safety Kareem Moore after catching a pass during a game at Cowboys Stadium in Arlington on Dec. 19, 2010.
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Two people were hospitalized, one of them in critical condition, after a crash that closed outbound lanes of the Glenn Highway at the North Birchwood exit early Sunday, Anchorage police said.
At 2:20 a.m., police received a report of a single-vehicle rollover accident, and that a man was in the middle of the road, said an email from police spokeswoman Dani Myren.
The vehicle, a Saturn SUV, apparently lost control at the exit, police said.
The driver, a 23-year-old man, was taken to a hospital in critical condition, Myren said.
A passenger, a 21-year-old woman, was also taken a hospital with minor injuries, police said.
Police had not identified the two people early Sunday.
The outbound lanes were closed and reopened around 4:30 a.m., Myren said.
This is a developing story. Check back for updates.
Anchorage Daily News / adn.com


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Big-serving Jo-Wilfried Tsonga crashed out of the Shanghai Masters on Wednesday, beaten by Japan's Kei Nishikori.
Posted| Updated
Technology giant Sony says it has suspended 93,000 accounts on its online entertainment networks after detecting a wave of unauthorised sign-in attempts, months after a huge breach forced it to halt some services.
Topics: hacking, computers-and-technology, science-and-technology, law-crime-and-justice, japan
A group of Queensland farmers has gone to Parliament to explain how they're spending government money to reduce runoff from their properties and help the Great Barrier Reef.
Topics: oceans-and-reefs, rural, sugar, beef-cattle, canberra-2600, brisbane-4000
Posted| Updated
Climate Change Minister Greg Combet vows to work hard to win public support for the carbon tax, but the Opposition says its fight against the law will be just as relentless.
Topics: federal-government, climate-change, environment, government-and-politics, parliament, federal-parliament, laws, tax, australia
It is a multi-million dollar criminal industry and it could be thriving in hot-houses just next door.
Topics: drug-offences, cannabis, crime, law-crime-and-justice, macquarie-fields-2564, australia, nsw
Posted| Updated
Manly forward George Rose had a grade two striking charge downgraded at the NRL judiciary on Wednesday evening.
Topics: nrl, rugby-league, sport, manly-2095, nsw, australia
Posted| Updated
NZ authorities say bad weather is causing major structural problems to the container ship causing an oil spill.
Topics: oil-and-gas, disasters-and-accidents, environment, new-zealand
A video showing former FIFA vice-president Jack Warner telling Caribbean officials how to deal with cash gifts from Mohamed Bin Hammam has been published by a British newspaper.
Topics: soccer, england, united-kingdom
Posted| Updated
An antelope has charged into a cyclist during a race through a nature park in South Africa.
Topics: human-interest, cycling, animals, south-africa
Posted| Updated
Australia secured victory in the three-Test netball series against England with a dominant 67-36 display in Canberra on Wednesday night.
Topics: netball, sport, canberra-2600, act, australia, england, united-kingdom
Posted| Updated
An unbeaten century to Liam Davis and Michael Hogan's five-wicket haul thrust WA into the box seat in its Sheffield Shield clash with Tasmania.
Topics: cricket, sport, perth-6000, wa, australia
The Federal Government has broken an election promise to build a $5 million GP Super Clinic in Darwin's northern suburbs.
Topics: healthcare-facilities, government-and-politics, federal-government, health, health-policy, darwin-0800, nt, australia
The City of Vincent says the lease of the Perth Oval to the State Government is a major boost to the city's finances.
Topics: local-government, perth-6000, wa
Posted| Updated
Dick Thornett, part of a select breed of sportsmen to have represented Australia in three sports, died on Wednesday morning aged 71.
Topics: sport, rugby-league, rugby-union, olympics-summer, sydney-2000, nsw, australia
The Federal Court has overturned a decision last year to award hundreds of thousands of dollars in compensation to a Melbourne man who claimed his heart attack was caused by arthritis drug Vioxx.
Topics: chemicals-and-pharmaceuticals, pharmaceuticals, arthritis, heart-disease, law-crime-and-justice, australia
About 150 nurses at the Royal Hobart Hospital have passed a vote of no confidence in the Health Minister and the State Government over savage health budget cuts.
Posted| Updated
Greater Western Sydney shelved thoughts of legal action against the AFL on Wednesday as it celebrated securing the top five picks in next month's national draft.
Topics: australian-football-league, sport, carrara-4211, qld, blacktown-2148, nsw, australia
Posted| Updated
Indonesian prosecutors say they are prepared to allow the Australian teenager accused of buying marijuana on a Bali beach to wait for his trial outside prison.
Topics: courts-and-trials, law-crime-and-justice, crime, drug-offences, bali, indonesia, newcastle-2300
Police investigating suspected child abuse have removed six children from a substance rehabilitation centre in Central Australia.
Topics: crime, child-abuse, community-and-society, law-crime-and-justice, rehabilitation, alice-springs-0870, australia, nt
Posted| Updated
Suicide bombers and roadside blasts have targeted police in a wave of attacks across Baghdad, killing at least 23 people and wounding dozens in the Iraqi capital.
Topics: unrest-conflict-and-war, iraq
Posted| Updated
Burma releases some of its high-profile political prisoners as part of a mass amnesty.
Topics: world-politics, law-crime-and-justice, prisons-and-punishment, burma
Elevated levels of radioactive strontium, which can cause cancer, have been found 250 kilometres from the stricken Fukushima nuclear plant.
Topics: nuclear-accident, disasters-and-accidents, japan
Posted| Updated
Two researchers who revolutionised polymer science to create never before seen molecules have been awarded the Prime Minister's Science Prize for 2011.
Topics: science-awards, science-and-technology, biology, biotechnology, chemistry, research, australia, act, canberra-2600


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Season's first dolphins killed in Japan, say activists
The first dolphins of the season were slaughtered on Tuesday in the small Japanese town of Taiji, campaigners said, commencing an annual cull repeatedly condemned by animal rights groups.
The first dolphins of the season were slaughtered on Tuesday in the small Japanese town of Taiji, campaigners said, commencing an annual cull repeatedly condemned by animal rights groups.
Fishermen in the small Japanese town of Taiji killed more than two dozen striped dolphins on Thursday, campaigners said, as global outrage over the slaughter grows.
Japan's Fisheries Agency said Wednesday it plans to refit the factory ship used every year on its Antarctic whaling expeditions, in the hope of getting at least another decade's service.
Activist group Sea Shepherd has failed to secure an injunction to halt a controversial shark cull policy in Western Australia, it said Thursday, vowing to fight on to prevent the killings.
Militant conservation group Sea Shepherd said Wednesday that two of its volunteers had been arrested in the Faroe Islands for allegedly interfering with the territory's traditional whale hunt.
The Sea Shepherd conservation group asked the US Supreme Court on Monday to lift an order forcing it to steer clear of Japan's whalers, who are seeking legal reprisals over harassment at sea.
Militant anti-whaling group Sea Shepherd said Wednesday it had zeroed in on the Japanese fleet before a single mammal had been killed, claiming an early victory in their annual Southern Ocean battle.
The waters off the Hawaii's largest island are home to a half-million brightly-colored tropical fish that are scooped up into nets each year and flown across the globe into aquariums from Berlin to Boston.
Environmental campaigners from the militant Sea Shepherd group said on Wednesday a Japanese whaling ship had "rammed" its vessels in a skirmish in the Southern Ocean.
The fugitive founder of Sea Shepherd has stepped down from key roles at the militant anti-whaling group, passing the Antarctic harpoon chase mantle to a former Australian politician.


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UMW News BureauCanadian painter Ken Dalgarno's "Scultped Landscapes" will be the next exhibition at the University of Montana Western Art Gallery/Museum. Dalgarno's work will be available for viewing Feb. 1 through March 3, 2010. By Ashley Makowski [caption id="" align="alignleft" width="240" caption=""Rust" by Ken Dalgarno"][/caption] Canadian painter Ken Dalgarno's "Scultped Landscapes" will be the next exhibition at the University of Montana Western Art Gallery/Museum. Dalgarno's work will be available for viewing Feb. 1 through March 3, 2010. Dalgarno, a self-taught artist who was born and raised in Moose Jaw, Saskatchewan, Canada, is inspired by his ancestors' strong bond with the sweeping vistas of the Canadian prairie. "I'm trying to show that the prairie landscape can be a fascinating place," Dalgarno said of his work. With an attention to texture and the giant prairie sky, Dalgarno uses his own take on the "impasto" method applying thick acrylic on canvas to paint the colorful prairie landscapes featured in "Sculpted Landscapes." Dalgarno's painting "Rust" was featured in the "Art on the Plains" exhibition at the Plains Art Museum, Fargo, North Dakota. He has also exhibited in numerous group and solo shows across Western Canada and North Dakota. This exhibition — Dalgarno's second Montana showing — is sponsored by The Montana Art Gallery Directors Association, a state-wide service organization for non-profit museums and galleries. Funding is also provided by the Montana Cultural & Aesthetic Trust and The Montana Arts Council. The Montana Western Museum and Art Gallery is located in Montana Western's Main Hall and is open Monday through Friday, 9 a.m. to 4 p.m.
Montana Western is the only public college in the country to offer a block scheduling program. We call this innovative program Experience One (X1).
It's really the best way to decide which college or university is right for you. Set up a campus visit today. And, oh by the way, we have a special gift for you just for stopping by.
We'd like to tell you more about our remarkable university. Join our mailing list and we'll send you information.
You are cordially invited to join us in a celebration of the remarkable success of Experience One and the inauguration of Chancellor Beth Weatherby Oct. 3.
Recent Montana Western graduate Taeler Rodriguez has been accepted to the University of Denver's graduate program.
UMW grad Justinn Marshall was accepted into the University of Washingston's regional medical education program.
Rodeo has always been a way of life for Kody Lahaye, from when he was a child to now as a fifth-year senior in college.
Misha Craddock may have finally found her place at the University of Montana Western.


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The Meeting Matrix - Clinecta.doc
Visitors can then submit their profile ... Netscape 7.0 or, Mozilla 1.0 or greater. Network ... requirements and details of The Meeting Matrix Last modified ...
Last updated 29/01/2013. by Ariella de Gennaro 1. Working with the media. EurActiv i. Letters to the editor ... – to check website visitors (free) Google alerts ...
Dear Sir/Madam - Ammas.doc
Dear Sir/Madam! ... Mozilla Firefox, Picasso, ... Out of this 100 visitors, if you get 20 clicks or 1 Free download on your single webpage, ... Down
Dear Sir/Madam - Ammas
Dear Sir/Madam! ... Mozilla Firefox, Picasso, ... Out of this 100 visitors, if you get 20 clicks or 1 Free download on your single webpage, ...www.ammas.com/uploadedfiles/13645425283703_Deatils...
The students are instructed to download the Zotero software on their machines along with Mozilla ... the visitors themselves to add ... 09/30/what-is-web-20.html ...eprints.rclis.org/20923/1/Practical%20applications%20of%20Open%20...
TERMS OF REFERENCE - UNDP in Armenia
The Web Site will support all browsers - IE 5.0 and higher: Mozilla Firefox, Opera, etc. ... The web page will contain as minimum 2 visitors counters ...operations.undp.am/Recruitment/temp/Job%20description-27.doc
Table of Contents - Multimedia University
Making sure visitors can get the information that they wanted within 3 clicks ... Mozilla Firefox or Chrome in order to interact with the ... Last modified by: Lim ...cdp.mmu.edu.my/FYP/downloads/TEMPLATE_FYP_FINAL...
Website accessibility guide: Part 7 - East Riding of ...
Title: Website accessibility guide: Part 7 Subject: Accessibility Author: Becta Last modified by: Sharliza A Rahman Created Date: 3/20/2006 10:57:00 AMwww.eriding.net/.../070917_ifleming_ict_accessibility_guide_part7.doc
ISU Alumni Association Online Store - Senior Design
The presentation tier handles interaction with visitors to ... Mozilla Firefox, and Safari ... 55 15 120 10 230 Jordan Jump 30 50 20 100 10 210 Andrew Kirpalani 30 50 ...seniord.ece.iastate.edu/may0539/design.doc
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Introduction - McDaniel College
Dynamic models 20 Introduction ... This system will allow visitors to register as students and then for student to ... For example, it must run smoothly on Mozilla ...www2.mcdaniel.edu/kyoon/2005-Fall-2205/Group4-RAD.doc
Summary of FrontPage 97/98 Procedures
Summary of Expression Web Procedures (Rev. 3) VERY IMPORTANT!!! PLEASE READ BEFORE STARTING TO WORK ON YOUR WEB SITE: It is highly recommended that …my.ilstu.edu/~bafrans/handouts/ewsummr3.doc
Mozilla Firefox or any other Internet Browser: ... Since the Consumer Portal that you have now signed in to is the Visitors Version, ... to go back to the last screen.dcmsdemo.hpcl.co.in/Manuals/TrainingManuals/...


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Female Bengal cat 15 weeks old
shot and dewormed
no emails please
serious people only
call Jorge 210 797-1816
Oct 6 -
San Antonio :
San Antonio - Cats & kittens
Classy companions,
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Select from some cuties at our website: bengalcatwildtales.weebly.com
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I'm working with jQuery / AJAX and ASP.NET. I'm creating two forms, create and update.
For this project I've gotten in the habit of doing everything via AJAX including submitting the the create form and populating the update form.
Are there any guidelines on when you should use AJAX and when you should do the work server side. Both will get the job done and I'm just wondering if I'm overdoing it on the client side.


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Digital Publishing Leader
Barry is an accomplished print and digital publishing leader with experience in transitioning traditional publishing companies into digitally savvy and profitable organizations. He has built up a broad knowledge of international publishing/digital content business models in Europe, the U.S., and Asia.
Barry has a strong commercial record developing new revenue streams and considerable expertise with multiple platform content and revenue strategies spanning print, desktop, mobile, tablet, and social media.
October 21-22, 2015
November 17-19, 2015
November 25-26, 2015
April 11-13, 2016
Spring 2016
US Consumer Device Preference Report
Traditionally desktops have shown to convert better than mobile devices however, 2015 might be a tipping point for mobile conversions! Download this report to find why mobile users are more important then ever.
E-Commerce Customer Lifecycle
Have you ever wondered what factors influence online spending or why shoppers abandon their cart? This data-rich infogram offers actionable insight into creating a more seamless online shopping experience across the multiple devices consumers are using.
October 13, 2015
1pm ET/ 10am PT
November 12, 2015


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South Hackensack, NJ (PRWEB) January 05, 2014
RevitaRUGS, the premier antique, oriental, Persian and high end designer area rug cleaning company will be participating exclusively in The Atlanta International Area Rug Market® from January 9 to 12th. Hamid Zarei, the founder and owner of revitaRUGS, and Azita Goldman, VP Business Development, are enthusiastic about attending the AmericasMart, Atlanta once again and re-connecting with their customers.
The event is not only a product destination for those wanting to explore different collections of area rugs, it also focuses on the area rugs economy, including ending child labor, utilizing earth friendly fibers, and educating the public on area rug impact on health and indoor air quality.
Hamid Zarei commented on the importance of this event. "Rug manufacturers have been joining organizations such as goodweave which works in ending child labor in carpet weaving communities around the world. In addition, the demand for use of natural fibers such as Bamboo, Sisal and Seagrass has generated a completely new economic opportunity in many parts of the globe. The EPA's health warnings and the public health concerns regarding the use of harsh chemicals to clean carpets and area rugs, has also put the spot light on the after-market cleaning processes by rug cleaners."
Azita Goldman commented on why rug cleaning is crucial. "Area rugs act like an air filter, collecting dust, pollen, bacteria and other pollutants, so proper vacuuming and annual professional cleaning is important to keep them in their original condition."
RevitaRUGS is proud to be attending the event again and looks forward to bringing industry experts and consumers up-to-date on the newest methods of area rug c
|Source: PRWeb
Copyright©2012 Vocus, Inc.
All rights reserved


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Corvette Tiger Shark Kits are Back!
It looks like those popular Tiger Shark treatments for Corvettes are revving up to make a comeback.
Comments | By Detroit Steel - July 16, 2015
OPTIMA Presents How-To Tuesday: Blackout Those Corvette Taillights
Taillight tinting has never been easier. Take the time to do this project on your own and save money for another modification later!
Comments | By Nick Vaughn - July 14, 2015
'Flawless' New Leather C5 Corvette Dash Prompts Fit of Joy
One happy Corvette Forum member was so impressed with the look and quality of his custom made Napa leather dash that he had to record a video just to show the world.
Comments | By Christian Moe - July 13, 2015
OPTIMA Presents How-To Tuesday: Installing Carbon Fiber Corvette Wheel Center Caps
Carbon fiber center caps are not out of reach. Just follow these simple directions to give your Corvette that extra touch.
Comments | By Nick Vaughn - July 7, 2015
Here's a Belated Fourth of July Celebration, Corvette Style
Here's a pair of Corvette burnouts to keep the Fourth of July vibe going.


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View gay Singles in Franklin
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Discount program... Near Redstone Shopping, route 128, route 93... On site management... Maintenance free!
We offer elevators with level access, laundry in building, discount program. balconies, fitness room, game rooms, free parking, close to major routes, only 20 minutes to Boston.
10 month leases available.
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The Bump Baby Registry
Now is the perfect time to start your Baby Registry!START A REGISTRY
It's National Children's Dental Health Month, which means we'll be giving you helpful tips on dental care for baby and answering all those questions you have about those adorable baby teeth. Here, Chris Kammer, DDS, Lifetime Family Dentistry and president of The American Academy for Oral Systemic Health, weighs in on the best time to schedule baby's first...Read more
Soleil Moon Frye rose to fame on the 1980s TV series Punky Brewster. Now the married mom of three is the author of two books: Let's Get This Party Started and Happy Chaos, is a co-founder of children's lifestyle brand Seedling, hosts the TV show "Home...Read more


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Recent Posts
- Harvest Monday, October 5, 2015 – Flowers + Container Eggplants & Beets
- Harvest Monday, September 28, 2015 – Fall Harvest from the Garden & Containers
- Harvest Monday, September 21, 2015 – Flowering Leek
- Harvest Monday, September 14, 2015 – Onions Failure + Leek & Parsnip + Bolted Napa
- Harvest Monday, Auugust 31, 2015 – Figs + Long Beans
Tag Archives: hellebores
Harvest Monday, April 20, 2015 – Growing Potatoes & Sweet Potatoes in Containers + Garden Overwintered Root Crops
My daughter, Kathy, grew vegetables for the first time last year and had bountiful harvest. So pleased with her success she is enthusiastically looking forward to this new gardening season even installed grow lights and started some veggies and flowers … Continue reading
Harvest Mondays, March 19, 2012
Spring greetings from my garden to yours! Hellebores (Lenten Rose). One of the few plants the deer decided to leave alone, so far. Miniature Iris, the ones the deer could not get at. While walking around the property, I discovered a large clump … Continue reading
Posted in Harvest Monday Tagged carrot, garlic green, hellebores, leeks, miniature iris, parsley, parsnip 73 Comments


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Shamsiel And The Little Father
Al Goldfarb
Drawing - Color Pencil, Markers, Opaque Inks
This is one of over a hundred illustrations from the first book of the fantasy/adventure series titled "The Vine Of Hours". I am the author/illustrator. Shamsiel is suffering. He hates this environment more and more by the second. His clothing is torn and his flesh is scratched and bleeding from fighting his way through this impossibly thick subterranean forest of roots. This place creeps him out. He has never been down here for so long, and he has made an alarming discovery, they are moving! All the roots are moving minutely this way and that, writhing serpentinely, like millions of hanging snakes. Disgusting! Shamsiel stops struggling to push his way through the roots in his search for the Little Father. He is beyond frustration, and with the rage of one who is just about to lose control he screams out loudly from all four of his heads, " If he is here, why can't I find him?!" Immediately the Little Father walks out from between two very thick roots right in front of Shamsiel and says tenderly, "Shamsiel. what is the matter? Are you in pain?" The Little Father is a strange looking creature. His face is like no other in the world.There are no features as one would expect to see on the front of a being's head. His face is flat, viscious and watery, reflective, like a pool. What shows in the pool that is the Little Father's face is what, or who, is facing him. But not their exact features. No, not their features but their emotions, their true emotions at that moment. The exact emotions of the being facing him is what is reflected in the mirror that is the Little Father's face, be it good or bad, happy or sad, benificent, or malicious, it is all the same to the "pool of truth" face, which is always unerringly accurate.
August 1st, 2011
Viewed 52 Times - Last Visitor from New York, NY on 08/13/2015 at 6:32 PM
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Partners at a Glance
- A one-on-one discipleship program written by Pastor Mike Fabarez.
- A Spiritual growth program designed for new or longtime believers who are serious about maturing in their faith.
- A program which overviews the fundamental issues of the Christian faith.
- Designed to help you learn how to live an effective, pleasing Christian life.
- A ten chapter program which can be completed in 14 weeks.
- A program which prepares you to teach what you have been taught.
- Life changing!
The Partners Program exists to:
- Help people enhance their walk with Jesus by learning how to live an effective and pleasing Christian life, and to put into practice what they are learning.
- Build relationships.
- Prepare each person to take another person through.
- Make disciples of Jesus Christ.
Partners Celebration Dinner
If you are a Partners Graduate, please join us on Friday, October 16th for dinner & teaching with Pastor Mike.
We'll be enjoying Cafe Rio for dinner starting at 6:30pm, then we'll hear a message from Pastor Mike.
KIDS Bible Club is available with pre-registration by October 12th. Please register yourself for the dinner and on the confirmation page, click the link to register you child(ren) for KIDS Bible Club.