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A process for releasing sectors of a flash EEPROM memory array which includes a plurality of individually erasable blocks and stores sectors of data in such blocks with a header providing a logical sector number, an indication of validity of data stored, and an indication of whether data is stored with the header. The process includes the steps of finding the header of a sector with data to be released, setting the indication of validity of the data stored to indicate that the data is invalid, and writing a new header for the sector to a new position in the array without data and with an indication that data is not attached.
1. A method of releasing sectors of memory in a flash EEPROM memory array comprising the steps of:
storing a list of sectors to be deleted in a first table,
selecting a sector from the first table,
searching a second table for a physical position of the sector,
seeking the sector specified by the physical position in the flash EEPROM memory array,
marking a header of the sector found as invalid,
writing in free space in the flash EEPROM memory array without data a new header for the sector found,
updating the second table with a new physical position of the new header for the sector, and
repeating the steps of selecting a sector from the first table until a selected number of sectors listed in the first table have been selected.
2. A method of releasing sectors of memory in a flash EEPROM memory array as claimed in claim 1 in which the step of writing in free space in the flash EEPROM memory array without data a new header for a sector found comprises furnishing an indication in a new header that no data is attached to the new header.
3. A method of releasing sectors of memory in a flash EEPROM memory array as claimed in claim 2 in which the step of furnishing an indication in a new header that no data is attached to the new header comprises setting a bit in a new header.
4. The method of releasing sectors of memory in a flash EEPROM memory array as claimed in claim 1 further comprising the steps of:
writing any valid data remaining in a selected portion of the flash EEPROM memory array to free space in the flash EEPROM memory array when a predetermined number of headers specified as invalid in the selected portion of the flash EEPROM memory array exist, and
completely erasing the selected portion of the flash EEPROM memory array.
1. Field Of The Invention
This invention relates to flash electrically-erasable programmable read-only memories (flash EEPROM) and, more particularly, to methods for releasing portions of such arrays in which data is stored which is no longer of value so that the efficiency of the process for storing and maintaining the memories is increased.
2. History Of The Prior Art
Modern computer systems make extensive use of long term memory. Typically this memory is provided by one or more electro-mechanical hard (fixed) disk drives made of flat circular magnetic disks which rotate about a central axis and which have a mechanical arm to write to or to read from positions on the magnetic disk. Hard disk drives are very useful and have become almost a necessity to the operation of personal computers. However, such electro-mechanical drives are relatively heavy, require a significant amount of space within a computer, require a significant amount of the power in use, and are very susceptible to shock. A hard drive within a portable computer which is dropped is quite likely to cease functioning with a catastrophic loss of data.
Recently, forms of long term storage other than electro-mechanical hard disk drives have become feasible for use in computers. One of these is flash EEPROM. A flash EEPROM memory array includes a large plurality of floating-gate field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing the individual cells and placing the memory transistors of those cells in one of two memory conditions. A flash memory cell, like a typical EPROM cell retains information when power is removed. Flash EEPROM memory has a number of characteristics which adapt it to use as long term memory. It is light in weight, occupies very little space, and consumes less power than electro-mechanical disk drives. More importantly, it is especially rugged. It will withstand without adverse effects repeated drops each of which would destroy a typical electro-mechanical hard disk drive.
A peculiarity of flash EEPROM, however, is that it is erased by applying a high voltage simultaneously to the source terminals of all of the transistors (cells) used in a large portion of the array. Because these source terminals are all connected to one another in the array by metallic busing, the entire portion of the array must be erased at once. While an electro-mechanical hard disk drive will typically store information in a first area of the disk and then rewrite that same area of the disk when the information changes, this is not possible with a flash memory array without erasing all of the valid information that remains in that portion of the array along with the invalid (dirty) information.
Because of this, a different arrangement may be advantageously used for rewriting data and erasing dirty sectors of a flash EEPROM array. In a recently devised arrangement, the entire array is divided into smaller separately erasable blocks so that when a block is erased the amount of valid data which must be reprogrammed is reduced. Such an array is composed of a number of silicon chips; and each such chip includes a number of such blocks. Then, when the information at a data entry changes, the changed information is written to a new sector on an available block rather than written over the old data; and the old data is marked dirty. After a sufficient number of sectors on a block have been marked dirty, the entire block is erased. When erasure occurs, all of the valid data in the block to be erased is written to a new block; and then the dirty block is erased and put back into use as a clean block of memory. Because of this involved erasure process, it typically takes as much as two seconds to erase a block of a flash EEPROM array. However, because erasure need not occur with each entry which is rewritten, erasure may be delayed until a block contains a sufficient amount of dirty information that cleanup is feasible. This reduces the number of erasure operations to a minimum and allows erasure to occur in the background when the facilities for controlling the array are not otherwise occupied with reading and writing. Such an arrangement is described in U.S. patent application Ser. No. 07/969,131, entitled Method And Circuitry For A Solid State Memory Disk, S. Wells, filed Oct. 30, 1992, and assigned to the assignee of the present invention.
The typical personal computer operating system was not designed to handle such a memory arrangement. For example, the Microsoft DOS operating system (hereinafter DOS) allocates long term memory space through the use of a file allocation table associated with the particular memory hardware. When an electro-mechanical hard disk drive is first put into use, it is divided into sectors each of a fixed size and residing at a fixed place on the drive media. Each sector is numbered. The file allocation table is a way for the DOS operating system to figure out which sectors on a disk are used for a file. The file allocation table is a linked list that maps the file to the sectors; each link in the list includes a number of sectors allocated to a particular file and points to the next link. The DOS system typically saves the file allocation table on the disk with which the table is associated. The DOS system includes a utility program called delete which hunts out the sectors related to the files the user wants to remove and marks those sectors as free in the file allocation table. When the host computer then desires to write to an electro-mechanical hard disk drive, it may write data to those sectors over the data previously stored. The data previously stored does not have to be erased for a sector to be rewritten in an electro-mechanical hard disk drive.
However, this is not true in a flash disk memory array because each block of the array must be erased before new data may be written to it. Thus, information which though valid is no longer of use to the operator of the computer is left in the memory array reducing the efficiency of storage. Consequently, a new method for releasing space in a flash memory array which stores information which though valid is no longer of use to the operator of the computer would be useful.
It is, therefore, an object of the present invention to provide a method for releasing allocated space in a flash EEPROM memory array occupied by out-of-date data so that processes controlling the memory array may operate more efficiently.
It is an additional object of the present invention to provide a method for automatically deattaching space occupied by out-of-date data in a flash EEPROM memory array to increase the efficiency of operation of the array.
These and other objects of the present invention are realized in a method for releasing for use by new data sectors of a flash EEPROM memory array which includes a plurality of individually erasable blocks and stores sectors of data in such blocks with a header providing a logical sector number, an indication of validity of data stored, and an indication of whether data is stored with the header. The process includes the steps of finding the header of a sector to be released, setting the indication of validity of the data stored to indicate that the data is invalid, and writing a new header for the sector to a new position in the array without data and with an indication that data is not attached.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
FIG. 1 is a block diagram illustrating a flash EEPROM memory array in which the present invention may be used.
FIG. 2 is a diagram illustrating an individual block of the flash EEPROM memory array of FIG. 1.
FIG. 3 is a flow chart illustrating a method in accordance with the present invention.
Some portions of the detailed descriptions which follow are presented in terms of symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to a method for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
Referring now to FIG. 1, there is illustrated in block diagram form a flash EEPROM memory array 10 in which the present invention may be practiced. The array 10 includes a plurality of blocks B0-B15 of flash EEPROM memory. Each block includes floating-gate field effect transistor memory devices or cells (not shown) arranged in typical row and column fashion and having circuitry arranged for selecting any particular block of memory and any particular row and column so that the memory device at that position may be written or read. The details of the layout of transistor memory arrays and the associated accessing circuitry are well known to those skilled in the art and are, therefore, not shown here.
As has been described above, flash EEPROM memory is essentially an EPROM array with facilities provided so that when divided into blocks in the manner illustrated an entire block of CMOS memory cells may be erased by a high voltage value applied simultaneously to the source terminals of all the memory transistors of the block. Such an erasure places each of the cells in the one condition. When in that condition, a zero or a one may be written to a cell. A one leaves the cell in the same one condition while a zero switches the cell to the zero condition. A cell cannot be switched back from the zero condition to the one condition without the application at its source terminal of the high value of voltage required for erasure. Since all source terminals of the memory transistors of a block are joined together, a cell in a zero state remains in that state until the entire block of the array is erased once again.
In the array 10 illustrated in FIG. 1, blocks B0-B15 of memory are shown positioned on a first chip 11 of the array 10. Additional silicon chips 11 each hold additional blocks of the array 10 to provide a total number of blocks sufficient to furnish the desired size of memory array.
Once any one of the blocks has been erased, data may be written to any position on the entire block. When, a host begins writing (in a manner to be described) the data to be stored in the array (such as an application program) to some block of the array having free space, the data to be stored in the array 10 is written sequentially, sector by sector, to the free space in this first block until that block has been filled with data. Then writing proceeds to the next sequential block having free space. At any point after writing is completed, the information may be read back from the array 10 by interrogating the block and sector at which the data is stored.
When updated information is to be written to a sector which already contains information, in contrast to the prior art, the new information is written to new or newly-erased free space on some one of the blocks of the array 10. This, rather than writing over the old information, occurs because the old information can only be rewritten if the entire block on which it is stored is first erased. To erase an entire block without destroying valid data would entail copying all of the valid data to another block of the array 10, erasing the original block, rewriting the valid data back to the original block, then rewriting the updated data over the old entry on the original block. Instead the updated information is written to a new position on a different unfilled block (e.g., block B7), and the old position is marked invalid (dirty). A block is usually not erased until a large number of dirty sectors exist on the block and the number of valid sectors on the block which must be saved is substantially reduced.
Because of this arrangement by which data is replaced in the array by writing it to a different physical position, the sector number which is used to indicate where data is stored is really a logical sector number. In order to allow the use of logical sector numbers, a lookup table 17 (held in static random access memory 16 in one embodiment) listing logical sector numbers against physical sector positions is utilized with the array 10 so that the physical position in the array 10 at which any particular logical sector exists may be determined.
Also, because of this arrangement by which data is replaced, each block of the array will after some time have a number of entries which are marked invalid and cannot be used for storage. Consequently, as the array 10 fills with data, a point will come when it is necessary to clear out invalid data from a block in order to provide space for new data to be stored. Typically, the dirtiest block of the array 10 is chosen for erasure. This allows the smallest amount of valid data to be moved to another block of the array from the block to be erased. Once the valid data is written to another block and the new physical addresses are recorded in the lookup table 17, the block from which the information was read is erased. It is then placed back into operation as an entirely clean block.
FIG. 2 is an idealized drawing which illustrates one arrangement of an individual block of the array 10 and is useful in describing the way data is stored. A typical block 20 is illustrated as a rectangular area. The area includes a plurality of transistor devices typically arranged in rows and columns to provide the desired storage.
The individual transistors and the various column and row select lines and other conductors for operating the block are not illustrated but are well known to those skilled in the art of designing flash memory.
As may be seen in FIG. 2, data is stored in the block 20 beginning at the top of the block and near to the bottom. At the top of the block 20 are stored the logical sector numbers used by the operating system as addresses for the data in an identification field referred to as a sector translation table or "header." For example, a first sector number 58112 is stored as a part of the first header at the top. In the header with the sector number are stored a pointer value and a set of attributes. The attributes included in one embodiment are an indication of the validity of the entry, a revision number, an indication whether the data is compressed or not, and a bit which indicates whether the entry includes data. The indication of the validity of the entry stores at least one bit which indicates valid when it is a one value and invalid when it is a zero value; in one embodiment, two bits are used and both must be ones to indicate a valid entry. The revision number is, in one embodiment, a four bit number. The bit which indicates whether the entry includes data or not is utilized to allow sectors to be created without data. This is the initial state of sectors on a block when the array is first formatted. This allows information regarding the condition of sectors to be transferred to the host computer even though those sectors have not been used or are not presently in use to store data.
The pointer value points to a physical address on the block 20 which is an offset from the beginning of the block at which the data for logical sector 58112 is stored. An arrow in FIG. 2 illustrates this physical position at which the first byte of data for the logical sector is stored. In the case of logical sector 58112 which is the first sector on the block 20, the data is written from the position indicated by the pointer stored with the sector number 58112 in the header to a point at the beginning of the data area which is marked by a beginning pointer value illustrated by an arrow extending from the upper left hand corner of the block 20. FIG. 2 also shows a second logical sector 5 and its pointer directed to a physical position on the block 20 which stores the first byte of the data for sector 5.
The header for a third logical sector number 867 is also shown; this sector includes an indication "WOD" that "no data is attached." By the use of this indication, the header may be positioned on a block of the array, yet the space usually allocated for data is not used. This allows various information about the sector to be transferred to the host without a great deal of space being used. In one embodiment, a header requires only four words (eight bytes) of memory in the array whereas a sector of data may use as much as 512 bytes of memory.
As was pointed out above, the physical position of the sector number is stored in a lookup table 17 (which is preferably held in random access memory 16) with the chip number, the block, and other information (such as the position in the block) for retrieving the data. The data stored in any sector of the block 20 may be retrieved by retrieving the physical position of the logical sector number from the table 17 in random access memory 16, going to the position on the block 20 where the sector number is stored, and retrieving the pointer to the beginning position of the data and the pointer to the beginning position of the sector whose number is stored immediately above the sector number being retrieved. These two values determine the starting and ending positions (its size) for the sector the data of which is sought.
An arrangement has been devised to control the operation of the programming, reading, and erasing of the flash EEPROM memory array. This arrangement is shown as a read/write control circuit 14 in FIG. 1. The control circuit 14 utilizes a microprocessor such as the Intel 80188 processor to execute various processes stored in read only memory within the control circuit 14. These processes utilize random access memory 16 to provide various services which allow the array 10 to be utilized as long term storage in the manner described.
The control circuit 14 shown in FIG. 1 is also illustrated as including a command state machine which provides a command interface between the control circuit 14 and the flash EEPROM memory array. In one embodiment, the command state machine and the write state machine actually reside on each of the chips 11. The command state machine controls the programming, reading, and erasing of the flash EEPROM memory array. The command state machine using the write state machine sequences the data flow to and from the array to ensure that the writing to, the reading from, and the erasure of the array take place properly. The microprocessor of the controller 14 controls the transfer of information between the host and the array and runs processes to provide services to the array; in doing so, the microprocessor may make use of various operations provided by the command state machine. Details of the command state machine and the write state machine are disclosed in U.S. patent application Ser. No. 07/655,643, entitled Command State Machine, Fandrich et al, filed Feb. 11, 1991, and assigned to the assignee of the present invention, and in U.S. patent application Ser. No. 07/654,375, entitled Circuitry and Method For Programming and Erasing A Non-Volatile Semiconductor Memory, Kynett et al, filed Feb. 11, 1991, and assigned to the assignee of the present invention.
Because it controls all information passed between the host and the command state machine interface to the memory array, the microprocessor of the control circuit 14 is able to control the operations so that the external host which is writing to and receiving information from the flash array is typically not aware that an erasure is taking place even though the erasure may require one or two seconds.
When the flash EEPROM memory array described is manufactured for use in place of an electro-mechanical hard disk drive, it typically receives low level formatting. This low level formatting stores on the blocks of the array data to define all of the logical sectors which may exist in a drive of the particular size. For example, one embodiment of a forty megabyte drive will have approximately 83,000 sectors placed on a first number of blocks; approximately the first forty blocks of the 240 blocks available in in this array will hold such preformatted sectors. In this embodiment, a limited number of sectors (2047 in one embodiment) may be placed on each of a first number of the blocks of the array; the remaining blocks contain free space. Each of these sectors has a logical sector number and the remainder of the information necessary to complete the header fields. However, since none of the sectors includes data at this point in time, the data attached bit of the attribute field indicates that no data is attached to the sector.
Each time power is applied to the array, the microprocessor of the controller 14 runs a process which reviews all of the blocks of the array and compiles the table 17 from the valid logical sector entries found. These valid logical sector numbers are listed in the table 17 along with the physical offset, block, and chip at which they are positioned. Since the addressing scheme used treats the host address as a logical address and records that logical address along with the physical position in the table 17 in random access memory 16, this table 17 must be updated whenever data is written to the array. The writing of changed data to a new physical address requires that the lookup table entry in table 17 be updated with the new physical position of the sector in the array and that the old entry on the block to be erased be marked as invalid by programming the valid bit(s) of the header to zero. The old entry must be so marked so that the RAM lookup table 17 may be accurately constructed after power is removed and reapplied.
The normal manner in which the writing of data takes place is as follows. Each sector of data is provided by the host with the number of the cylinder, head, and sector to which it is to be written. The microprocessor uses a conversion equation to change this value from the format used by an electro-mechanical drive to a logical sector number for use by the controller 14. The controller 14 looks up the logical sector number in the table 17 and finds the physical position of the sector in the array. The controller then finds the sector header in the block of the array on which it is positioned. The first time any sector is written, the header will be one which describes the sector as having no data attached (the low level format condition). The controller 14 marks the old sector header invalid, then assigns free space (space not already assigned to a sector) on some block of the array to the sector, and writes a new header to the free space. This header includes, among other things, the logical sector number, a pointer to a position on the block at which the data will commence, and an indication that data is attached. The controller then writes the data furnished by the host to the data space at the new entry position for the sector. The controller 14 then updates the table 17 with the new physical position of the sector.
This places the table 17 in condition so that the changed (new information) may be recovered. This also leaves the old sector marked invalid so that it may be cleaned up when a sufficient number of sectors of the array have been marked dirty.
Because the space marked dirty on a block cannot be released for use until the entire block is erased, each block of the array will after some time have a number of entries which are marked dirty and cannot be used for storage. Thus, the amount of dirty space in the array will mount as the array is used to store data. After some period of time, a sufficient amount of invalid data will exist that it will be desirable to release space by moving the valid information from some especially dirty block to some other block and erasing the entire block from which the valid information has been removed. The process of writing valid data to other blocks and erasing a dirty block is referred to as "cleaning up a block" and has the effect of freeing up an additional number of sectors equal to all of the sectors on the erased block which have previously been marked as dirty. This process is run by the microprocessor of the controller 14.
Typically, when cleanup takes place, the dirtiest block of the array is chosen for erasure. This allows the smallest amount of valid data to be moved from the block being erased to another block of the array. The process is essentially similar to that by which data is written by the host except that the header of a sector is not completed until the valid data has been moved. The controller 14 picks a block of the array to clean up. It finds another block of the array having free space. For each valid sector on the block being erased, the controller writes a header on the block containing the free space which header includes only a pointer to the position for the data for that sector. The controller 14 then writes the valid data from the old sector on the block being cleaned up. When the data has been written, the controller completes the header with the logical sector number and the valid indication from the old header, and invalidates the old header. This delay in completing the header allows changes which occur during the period in which the cleanup write operation is taking place to be taken care of without any loss of data. For example, a power loss leaves data available at the old position even though the write is not completed. The controller then updates the table 17 for the sector and goes to the next valid sector on the block being cleaned up.
Once all of the valid information has been written to another block(s) and the new physical addresses have been recorded in the lookup table 17, the block from which the information was read is erased. It is then placed back in operation as an entirely clean block of free space. In order to allow this cleanup operation to occur, some number of blocks must be kept in reserve to be used when cleanup is necessary. In one arrangement in which the present invention is utilized, fourteen blocks of the 240 blocks available are used to provide sufficient space for both continuing write operations and for cleanup operations. The cleanup process is described in detail in U.S. patent application Ser. No. 07/969,760, entitled A Method Of Cleaning Up A Solid State Memory Disk Storing Floating Sector Data, S. Wells, filed on Oct. 30, 1992, and assigned to the assignee of the present invention.
As will be understood from the above discussion, it is only sectors which are marked dirty which are erased. Sectors are marked dirty only when revised information is written to a sector or when the cleanup process moves valid data from a sector during the cleanup process. Sectors are not marked dirty when an operating system using a process such as the DOS "delete" process marks a table such as the file allocation table kept by DOS to indicate that the file has been deleted. Consequently, data cannot be written to space held in sectors of the array which have been marked free by the host in the file allocation table until the block on which those sectors reside has been erased. When the user desires to remove the data from the array, all that has occurred using the prior art "delete" process is that the file allocation table kept by the host operating system has been marked to indicate that the space is free; however, the sectors in the block of flash memory are still marked valid and cannot be overwritten.
The sectors allocated to the file which has been "deleted" by the operating system continue as valid sectors within the flash EEPROM memory array. It is not until the host attempts to write to these supposedly free sectors that they are marked dirty. Consequently, the data in each of these sectors will continue to occupy space in the array which might be otherwise used; and the cleanup process will continually move these valid sectors from block to block with other valid sectors.
There are two consequences of the cleanup process moving the data about as though it were useful data. First, moving the data takes time and lengthens the cleanup process. Second, files become more fragmented as they are moved from block to block during the cleanup process; and this slows the initiation of the cleanup process making it less efficient.
The second consequence is not self evident. Data is written to the blocks of the flash EEPROM memory array sequentially. Thus, when a file is written to the flash EEPROM memory array, the sectors of that file are initially arranged in physical sequence on the block or blocks to which the file is written. The sectors of a file are gradually distributed over different blocks (fragmented) as the cleanup process occurs. The cleanup process only cleans up a block when it contains a large amount of invalid data. If all of the sectors of a file in a flash EEPROM array were to lie in sequence and were marked dirty as soon as the operating system deleted the file in the file allocation table, then all of those sectors would probably be concentrated on one or more blocks of the array. This would cause the particular block to be cleaned up rapidly. This has not occurred. Instead, the sectors of a deleted file containing the otherwise useless but valid information remain valid; and are gradually scattered among the blocks of the array as the cleanup process occurs in response to other invalid sectors on the blocks. This causes the cleanup of blocks to occur much less efficiently.
This invention relates to a new process (referred to hereinafter as a deattaching process) which may be practiced to release the space in the array used by the data which it is desired to remove from storage but which has been left by a host system "delete" process. This process makes use of the "data not attached bit" discussed earlier which may be set in the header of a sector. The deattach process, in essence, rewrites the header of the valid sector containing the data to be deattached to a new position in free space in the array. The header of this new entry has the "data not attached" bit set, and the data is not transferred from the old entry as the new entry is written. Then the old sector entry including the data is invalidated, and the table 17 is updated to list the new physical position of the logical sector. When the cleanup process occurs (which will happen rapidly if a large amount of data is being deattached and sectors are being invalidated), the block on which the old sector was positioned will be erased. This will release for each sector so deattached on the block, space equal to the space occupied by the data which was stored.
The process of the present invention may be initiated in any manner by which a sector from which the data is to be deattached is presented to the microprocessor of the controller 14 along with the command "deattach." For example, the process might be initiated whenever a host command to delete a file stored in the array is run. The deattach process might as well be initiated by other processes to increase system efficiency.
When the deattach process occurs, it finds each sector to be deattached, writes the sector of the file to free space but without data attached, and marks the old sector as dirty. Marking the old sector dirty allows the cleanup process to cleanup the old sectors in which the data is stored. In view of the fact that the sectors of a file are originally written in physical sequence on blocks of the array, the cleanup process will occur immediately for any large files which are deleted by the host operating system and then deattached by the process of this invention since the logical sectors of such file will usually be positioned sequentially on a block or blocks of the array. This will have the effect of freeing the data space used by the files which are deattached and make the cleanup process operate much more efficiently.
FIG. 3 illustrates the details of the process in accordance with the present invention. The process begins with the command "deattach" being presented to the microprocessor of the controller 14 along with the logical sector number to be deattached. As is illustrated, this may occur after the user selects a command to initiate a process such as the normal DOS delete command (or similar commands of another operating system) in which the file allocation table is searched to determine the sectors allocated to the file (or files) to be deleted and marks those sectors as free in the file allocation table.
The process moves to carry out the individual steps of the deattach process described above. To accomplish this, the process causes the controller 14 to write the logical sector from which data is to be deattached "with no data attached." For each selected sector, the controller 14 searches the lookup table 17 for the physical position of the sector specified. When it finds the physical position, the controller 14 seeks the sector in the memory array. When the sector is found, the process marks the header of the old sector as invalid. Next the controller writes the sector in free space in the memory array as a header with the "no data attached" bit set. The data at the old entry position is not written to the new position of the sector. For each sector written with no data attached, the controller 14 then updates the table 17 with the new physical position of the sector. The process may be enhanced by compiling a list of sectors to be deattached in a table before commencing the process. In such a case, the writing of sectors without data attached may continue until all of the sectors in that table have been handled in this manner.
When any block containing the dirty sectors produced by the deattaching process becomes sufficiently dirty (immediately for large files), the cleanup process will write the valid data remaining on the block to free space and erase the entire block. This releases the space allocated to data in the dirty sectors produced by cleanup to free space.
As pointed out above, this process will enhance the efficiency and performance of operation of the cleanup process and thus the operation of the flash EEPROM memory array.
Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.
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Samsung Bada handset purportedly leaks
Samsung's Bada OS, freshly announced - though far from released - for mobile devices is reasonably interesting on its own, but we always prefer to have an inkling of hardware to go along with our software speculation. Happily that itch has been allegedly scratched this morning, with a render of what's purported to be the first Samsung Bada device.
Willeke at GSMHelpDesk has been slipped an image of this touchscreen handset, though there are no accompanying specifications to tell us what sort of experience we can expect. That leaves us arguing the aesthetics, and while the device pictured is reasonably inoffensive, it doesn't exactly distinguish itself from any other touchscreen-centric candybar. Perhaps there's a slide-out QWERTY keyboard waiting to wow us, but right now hardware controls look to be minimal.

subset: commoncrawl


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The American Bar Association (ABA) has concluded that a prosecutor who allows a debt collection company to use the prosecutor's letterhead to demand payment from borrowers violates Model Rules 8.4(c) and...more
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Nathan Dolinsky, 1971
Physical Details: Photographic print : 1 item : b&w ; 21 x 26 cm.
Creator: unidentified photographer
Description: Identification on verso (handwritten): Dolinsky, 1971.
Donated 1972 by Mrs. Virginia Downes, a friend of Dolinsky's.
Forms part of: Miscellaneous photographs collection,
Rights Statement: Current copyright status is undetermined
Citation: Nathan Dolinsky, 1971
Digital ID: 2529
- Dolinsky, Nathan
- Portraits
View all Image Gallery items from the Miscellaneous photographs collection


text: Healthy Recipes Drunken Prunes Recipe E-mail recipe Print recipe To save this recipe, register now! Quick Info: Servings Vegetarian Heart-Healthy Nutritional Info (Per serving): Calories: 135, Saturated Fat: 0g, Sodium: 2mg, Dietary Fiber: 3g, Total Fat: 0g, Carbs: 27g, Cholesterol: 0mg, Protein: 1g Carb Choices: 2 Recipe Source: Prep Time: 5 mins Cook Time: 17 mins Rest Time: 169 h Total Time: 169 h 22 mins Ingredients 2 teaspoon tea leaves, darjeeling 2 cup(s) water, boiling 1/2 cup(s) sugar, brown, light, packed 1 1/4 pounds plums, pitted, dried 1 cup(s) brandy, Armagnac or cognac 1 whole vanilla bean, cut in half Preparation 1. Stir tea and water in a small bowl; let steep for 5 minutes. Strain into a medium saucepan; stir in brown sugar. 2. Bring to a boil over high heat; boil until slightly thickened, about 2 minutes. Place prunes in a large bowl; stir in hot syrup. Set aside to cool to room temperature, about 1 hour. 3. Meanwhile, sterilize two 1-pint canning jars by steaming them upside down, their lids alongside, in a closed steamer for 10 minutes; or place in a large pot and cover by 1 inch of water and boil for 10 minutes. 4. Drain prunes, reserving liquid separately. Whisk Armagnac (or cognac) into the liquid. Pack each sterilized jar with half the prunes. Nestle half the vanilla bean in each jar. Pour 1/2 cup of the Armagnac mixture into each jar. 5. Seal and turn upside down to blend ingredients. Set right side up and store in the refrigerator for 1 week to plump. E-mail recipe Print recipe To save this recipe, register now!


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Four poems
Jonathan Swift 7 p.m., July 29
Author: IJSasson
Blog Creation Date: February 11, 2011
Entries: 2
Cocooned in our cars vs. riding the bus or trolley is truly an "autopia". Our little capsule allows us to ...
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text:
Machine vision methods for inspection of semiconductor die lead frames include the steps of generating a first image of the lead frame, generating a second image of the lead frame and any defect thereon, and subtracting the second image from the first image. The methods are characterized in that the second image is generated such that subtraction of it from the first image emphasizes the defect with respect to the lead frame.
1. A machine vision method for inspecting a substantially flat surface, the method comprising:
generating with a digital camera a first image of the substantially flat surface and a defect thereon;
generating with the digital camera a second image of the substantially flat surface and the defect thereon, such that the defect in the second image is of a different contrast polarity with respect to the substantially flat surface than the defect in the first image with respect to the substantially flat surface;
comparing, for the purpose of contrast enhancement of reflectivity features of the defect with respect to the substantially flat surface, each pixel of the second image to each corresponding pixel of the first image;
generating a third image representing results of comparing each pixel; and
isolating the defect using the third image.
2. A method according to
performing connectivity analysis on the third image to distinguish the defect from the substantially flat surface.
3. A method according to
detecting and tracking edges in the third image to isolate the defect.
4. A method according to
thresholding the third image to distinguish at least one of a defect and its edges from the substantially flat surface.
5. A method according to
determining an intensity threshold value that distinguishes at least one of the defect and its edges from the the substantially flat surface.
6. A method according to
generating a threshold image from at least one of the first and second images, the threshold image having pixels representing local threshold intensity values; and
using the threshold image to distinguish, in the third image, at least one of the defect and its edges from the substantially flat surface.
7. A method according to
8. A method according to
9. A method according to
normalizing at least one of the first and second images before comparing.
10. A method according to 9, wherein the normalizing step includes the steps of
determining distributions of intensity values of each of the first and second images;
generating a mapping function for matching extrema of those distributions; and
transforming the intensity values of at least one of the first and second images with that mapping function.
11. A method according to
generating the first and second images by illuminating the substantially flat surface with different respective emission sources.
12. A method according to
13. A method according to
generating the first and second images by illuminating the substantially flat surface with emissions in different respective wavelengths.
14. A method according to
generating the first image includes the step of illuminating the substantially flat surface with a light source selected from the group of light sources including a direct light source and a grazing light source; and
generating the second image includes illuminating the substantially flat surface with the other light source in that group.
15. A method according to
registering the first and second images with one another before comparing.
This is a continuation of U.S. patent application Ser. No. 09/184,407 filed Aug. 25, 1998, now issued as U.S. Pat. No. 6,298,149, which is a continuation of U.S. patent application Ser. No. 08/621,189 filed Mar. 21, 1996, now abandoned.
This application is related to U.S. Pat. No. 6,259,827, entitled MACHINE VISION METHODS FOR ENHANCING THE CONTRAST BETWEEN AN OBJECT AND ITS BACKGROUND USING MULTIPLE ON-AXIS IMAGES, issued Jul. 10, 2001, the teachings of which are incorporated herein by reference.
This application is related to U.S. Pat. No. 5,949,901, entitled SEMICONDUCTOR DEVICE IMAGE INSPECTION UTILIZING IMAGE SUBTRACTION AND THRESHOLD IMAGING, issued Sep. 7, 1999, the teachings of which are incorporated herein by reference.
The disclosure of this patent document contains material which is subject to copyright protection. The owner thereof has no objection to facsimile reproduction by anyone of the patent document or of the patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all rights under copyright law.
The invention pertains to machine vision and, more particularly, to methods for inspection of leads on semiconductor die packages (or lead frames).
At the heart of an integrated circuit is a semiconductor die. This is a wafer of semiconducting material (e.g., silicon) with hundreds of thousands or millions of electronic circuit components etched into its layers. To enhance processing speed and reduce power consumption, the dies are made as small as possible, e.g., less than a square-inch in area and several mils thick. To facilitate handling, the dies are glued into supporting frames, i.e., lead frames. In addition to providing stability, these frames have large conductive leads that can be soldered to other circuit components, e.g., on a printed circuit board. The leads are typically connected to corresponding pads on the die via a process called wire bonding, wherein a small conductive thread is bonded to each lead and its corresponding pad. Once a semiconductor die and its frame are assembled, they are typically packaged in a ceramic or plastic, forming an integrated circuit.
Inspection of the lead area of the semiconductor die packages is important in the semiconductor industry. Such inspection typically involves checking the leads on the package; both before and after the die is bonded to the package.
The most common defect in assembly is the deposit of unwanted adhesive on the leads. This is sometimes referred to as an AOL defect. Since the adhesive is conductive, it can effectively "short circuit" the semiconductor die's electronic functions.
The inspection of semiconductor packages for adhesive on leads has proven to be a vexing machine vision problem. This is a result of the complexity of the "background," i.e., the lead pattern which must be inspected in order to find the defect. This is further complicated by the decreasing size, and increasing number, of leads, as well as by the limited resolution of the cameras typically used for inspection. In this regard, it will be appreciated that while there are a variety of lead configurations, there are two basic types: etched leads and flying/free leads. The former are rigid and are etched onto a substrate, while the latter are mechanically pressed but non-rigid.
The prior art suggests the use of a technique referred to golden template comparison (GTC) to inspect the package leads. GTC is a technique for locating objects by comparing a feature under scrutiny (to wit, a lead frame) to a good image—or golden template—that is stored in memory. The technique subtracts the good image from the test image and analyzes the difference to determine if the expected object (e.g., a defect) is present. For example, upon subtracting the image of a good lead frame from a defective one, the resulting "difference" image would reveal an adhesive blotch that could be flagged as a defect.
Before GTC inspections can be performed, the system must be "trained" so that the golden template can be stored in memory. To this end, the GTC training functions are employed to analyze several good samples of a scene to create a "mean" image and "standard deviation" image. The mean image is a statistical average of all the samples analyzed by the training functions. It defines what a typical good scene looks like. The standard deviation image defines those areas on the object where there is little variation from part to part, as well as those areas in which there is great variation from part to part. This latter image permits GTC's runtime inspection functions to use less sensitivity in areas of greater expected variation, and more sensitivity in areas of less expected variation.
At runtime, a system employing GTC captures an image of a scene of interest. Where the position of that scene is different from the training position, the captured image is aligned, or registered, with the mean image. The intensities of the captured image are also normalized with those of the mean image to ensure that variations illumination do not adversely affect the comparison.
The GTC inspection functions then subtract the registered, normalized, captured image from the mean image to produce a difference image that contains all the variations between the two. That difference image is then compared with a "threshold" image derived from the standard deviation image. This determines which pixels of the difference image are to be ignored and which should be analyzed as possible defects. The latter are subjected to morphology, to eliminate or accentuate pixel data patterns and to eliminate noise. An object recognition technique, such as connectivity analysis, can then be employed to classify the apparent defects.
Although GTC inspection tools have proven quite successful, they suffer some limitations. For example, except in unusual circumstances, GTC requires registration—i.e., that the image under inspection be registered with the template image. GTC also uses a standard deviation image for thresholding, which can result in a loss of resolution near edges due to high resulting threshold values. GTC is, additionally, limited to applications where the images are repeatable: it cannot be used where image-to-image variation results form changes in size, shape, orientation and warping.
GTC is typically used to inspect only etched lead configurations, where it can be effectively used if the lead count is not high. Where that count is high, the frequency of etches results in a large area being effectively masked by the high standard deviation at the lead edges. GTC has not proven effective in inspections of flying/free configurations. Moreover, it is limited in that it requires excessive memory or processing time in instances where the package under inspection is rotated.
Blob analysis is also used to inspect etched lead configurations, as well as free-flying lead configurations. However, this analysis technique is only effective if the lead count is not high.
An object of this invention, therefore, is to provide improved methods for machine vision and, more particularly, improved methods for inspecting leads on semiconductor die packages or lead frames.
A further object is to provide such methods that can be used to identify defects such as adhesive blotches on those leads.
Yet another object is to provide such methods that can be used in inspecting the full range of die packages, including both etched lead packages and flying/free lead packages.
Yet still another object is to provide such methods that do not routinely necessitate alignment or registration of an image under inspection with a template image.
Still yet a further object of the invention is to provide such methods that do not require training.
Still other objects of the invention include providing such machine vision methods as can be readily implemented on existing machine vision processing equipment, and which can be implemented for rapid execution without excessive consumption of computational power.
The foregoing objects are among those achieved by the invention which provides, in one aspect, a machine vision method for inspecting leads on semiconductor die package, or lead frame. The method includes the steps of generating a first image of the lead frame (including, its leads and other structures—together, referred to as the "lead frame" or "background"), generating a second image of the lead frame and any defects thereon (e.g., excessive adhesive), and subtracting the second image from the first image. The method is characterized in that the second image is generated such that subtraction of it from the first image emphasizes the defect with respect to the background.
In related aspects of the invention, the second step is characterized as generating the second image such that its subtraction from the first image increases a contrast between the defect and the background. That step is characterized, in still further aspects of the invention, as being one that results in defect-to-background contrast differences in the second image that are of opposite polarity from the defect-to-contrast differences in the first image.
In further aspects, the invention calls for generating a third image with the results of the subtraction, and for isolating the expected defects on that third image. Isolation can be performed, according to other aspects of the invention, by conventional machine vision segmentation techniques such as connectivity analysis, edge detection and/or tracking, and by thresholding. In the latter regard, a threshold image—as opposed to one or two threshold values—can be generated by mapping image intensity values of the first or second image. That threshold image can, then, be subtracted from the third image (i.e, the difference image) to isolate further the expected defects.
Still further objects of the invention provide for normalizing the first and second images before subtracting them to generate the third image. In this aspect, the invention determines distributions of intensity values of each of the first and second images, applying mapping functions to one or both of them in order to match the tails of those distributions. The first and second images can also be registered prior to subtraction.
According to further aspects of the invention, the first and second images are generated by illuminating the lead frame with different respective light or emission sources. This includes, for example, illuminating it direct, on-axis lighting to generate the first image, and illuminating it with diffuse, off-access or grazing light to generate the second image.
Additional aspects of the invention provide methods incorporating various combinations of the foregoing aspects.
These and other aspects of the invention are evident in the drawings and in the descriptions that follow.
A better understanding of the invention may be attained by reference to the drawings in which:
FIG. 1 depicts a machine vision system for practice of the invention;
FIGS. 2A-2B depict illumination arrangements for generating images analyzed in accord with the invention;
FIGS. 3A-3C depict sample images (and their difference images) generated by the lighting arrangement shown in FIG. 2A;
FIG. 4 depicts a methodology for semiconductor die lead frame inspection according to the invention.
FIG. 1 illustrates a system 5 for inspecting semiconductor die lead frames in accord with the invention. The system 5 includes a capturing device 10, such as a conventional video camera (such as the Sony XC75 camera with COSMICAR lens 50 mm lens) or scanner, that generates an image of a lead frame 1. Image data (or pixels) generated by the capturing device 10 represent, in the conventional manner, the image intensity (e.g., color or brightness) of each point in the scene at the resolution of the capturing device. The lead frame is illuminated by on-axis light 7 and ring light 8 for generation of multiple images that facilitate identification of defects in accord with methods discussed herein.
The digital image data is transmitted from capturing device 10 via a communications path 11 to an image analysis system 12. This can be a conventional digital data processor, or a vision processing system (such as the Cognex 5400) of the type commercially available from the assignee hereof, Cognex Corporation, programmed in accord with the teachings hereof to perform image segmentation. The image analysis system 12 may have one or more central processing units 13, main memory 14, input-output system 15, and disc drive (or other mass storage device) 16, all of the conventional type.
The system 12 and, more particularly, central processing unit 13, is configured by programming instructions according to the teachings hereof for image segmentation, as described in further detail below. Those skilled in the art will appreciate that, in addition to implementation on a programmable digital data processor, the methods and apparatus taught herein can be implemented in special purpose hardware.
FIG. 2A illustrates an arrangement of light sources according to the invention for on-axis and diffuse (or grazing) light illumination of lead frame 20. The arrangement includes lighting sources 22 and 24 positioned for illuminating lead frame 20. Lighting source 22 provides direct, on-axis lighting via reflection off a half-silvered, partially transparent, angled one-way mirror 28, while lighting source 24 provides diffuse, off-access lighting, or grazing light. Images of the illuminated frame 20 are captured by camera 26 through mirror 28.
Lighting source 22 is of the conventional type known in the art for on-axis illumination of objects under inspection in a machine vision application. A preferred such light is a diffused on-axis light (DOAL) commercially available from Dolan Jenner. The source 22 and mirror 28 are positioned to cause potential defects on the lead area of the frame 20 (e.g., adhesive patches) to appear as dark features against a light background.
Lighting source 24 is also of a conventional type known in the art for use in providing diffuse, off-axis light or grazing light in machine vision applications. One preferred source 24 is an arrangement of several point light sources, e.g., fiber optic bundles, or line lights, disposed about element 20. Another preferred such lighting source 24 is a ring light and, still more preferably, a ring light of the type disclosed in commonly assigned U.S. Pat. No. 5,367,439. The lighting source 24 is positioned to illuminate the lead area of the frame 20 in such a way to cause potential defects thereon (eg., adhesive patches) to appear as light features against a dark background.
Other lighting sources known in the art can be used in place of on-axis source 22 and ring light source 24 to illuminate a surface under inspection. Considerations for selection and positioning of the sources 22, 24 are that expected defects on the lead frame appear differently (if at all) with respect to the background when illuminated by each respective source 22, 24.
More particularly, the lighting sources 22, 24 are selected and positioned such that the subtraction of an image captured by camera 26 when the lead frame is illuminated by one of the sources (e.g., 22) from an image captured by camera 26 when the lead frame is illuminated by the other source (e.g., 24) emphasizes defects on the leads, e.g., by increasing the contrast between the defects and the background (i.e., the remainder of the surface).
Put another way, the lighting sources 22, 24 are selected and positioned in such a way that an image generated by camera 26 when the lead frame is illuminated by one source has an defect-to-background contrast of an opposite polarity then the defect-to-background contrast of an image generated by camera 26 when the lead frame is illuminated the other source.
Thus, for example, in a preferred arrangement to detect adhesive on lead (AOL) defects on the lead frame 20, the on-axis lighting source 22 is selected and positioned (in relation to frame 20 and mirror 28) to cause a defect to be dark on a light background (e.g., "negative" defect-to-background contrast polarity), while the diffuse ring light 24 is selected and positioned to make the same defect appear light on a dark background (e.g., "positive" defect-to-background contrast polarity).
FIG. 3A similarly depicts an image generated by camera 26 when a lead frame 20 with AOL is illuminated by ring light or grazing light source 24. As shown in the illustration, the ring/grazing light reveals the adhesive as light patches 60, 62 on a dark background.
FIG. 3B depicts an image of the type generated by camera 26 when the same lead frame is illuminated by on-axis lighting source 22. As shown in FIG. 3A, the on-axis lighting reveals adhesive 60, 62, on the leads as dark patches on a light background.
FIG. 3C reveals a result according to the invention of subtracting the images generated by camera 26 under these two separate lighting conditions. Put another way, FIG. 3C represents the result of subtracting the image of FIG. 3B from the image of FIG. 3A. In FIG. 3C, the adhesive on the lead frame 20 is revealed as very light patches against a very dark background. (Note that this figure shows the output of the subtraction after remapping step 114, described below.)
FIG. 4 illustrates a method for inspecting semiconductor lead frames according to the invention. In step 100, the method acquires an image of the lead frame with lighting source 24 or other grazing light. Likewise, in step 102, the method acquires an image of the lead frame with on-axis light source 22. Though these images can be acquired at any times—though not concurrently—they are typically acquired at about the same time. This reduces the risk that the lead frame will be moved between acquisitions and, thereby, removes the need to register the images.
In the discussion that follows, the image acquired in step 100 is referred to as "Image 1," while the image acquired in step 102 is referred to as "Image 2." Although the discussion herein is directed toward subtraction of Image 2 from Image 1, those skilled in the art will likewise appreciate that Image 1 can be subtracted from Image 2. Preferably, Image 2 is subtracted from Image 1 in instances where the object is lighter than the background in Image 1, and where object is darker than the background in Image 2. Conversely, Image 1 is preferably subtracted from Image 2 in instances where the object is lighter than the background in Image 2, and where object is darker than the background in Image 1.
In optional step 104, the method registers the images to insure alignment of the features therein. Though not necessary in many instances, this step is utilized if the lead frame or camera is moved between image acquisitions. Image registration can be performed, for example, by a two-dimensional cross-correlation of images, in the manner disclosed in Jain, Fundamentals of Digital Image Processing. (Prentice Hall 1989) at Chapter 2, the teachings of which are incorporated herein by reference.
In steps 104 and 106, the method windows Images 1 and 2. These steps, which are optional, reduce the area (or pixels) of the respective images under consideration and, thereby, reduce processing time and/or computational resources. These steps can be performed by selecting the relevant subset of the pixel array of each image.
In steps 108 and 110, the method normalizes the (windowed) images. These optional steps, which compensate for overall differences in image intensity, can be performed by any technique known in the art. Preferably, however, normalization is global, using a map derived from the global statistics of the (windowed) images. The map is defined to match the extrema (or tails) of the statistical distributions of both images.
In step 112, the method generates a difference image, Image 3, by subtracting Image 2 from Image 1. This subtraction is performed in the conventional manner known in the art. Objects in Image 3, i.e., the "difference" image, can be isolated by standard machine vision segmentation techniques such as connectivity analysis, edge detection and/or tracking, and by thresholding.
In step 114, the method maps Image 3 to remove any negative difference values (i.e. negative pixel values) resulting from the subtraction. It also can be used to normalize (or rescale) the difference image to facilitate later stages of processing. This step, which can be performed in a conventional manner known in the art, is optional.
In step 116, the method performs morphology on the difference image. Morphology, which is well known in the art, is a technique for eliminating or accentuating data in the difference image, e.g., by filtering out of variations due to video noise or small defects. This can be performed, for example in a manner disclosed by Jain, supra, at Chapter 9.9, the teachings of which are incorporated herein by reference.
In step 118, the method thresholds, or binarizes, the image to distinguish or isolate defects of interest—e.g., images of adhesive patches—from the background. Thresholding can be performed in the conventional manner known in the art. Thus, for example, a single threshold intensity value can be determined from a histogram of Image 3. Preferably, however, the threshold intensity value is predetermined, i.e., based on empirical analysis of prior images.
In certain applications, use of a high global threshold intensity value will result in portions of the object of interest being interpreted as background and, therefore, will result in poor segmentation. Likewise, use of a low global threshold intensity value will result in background being interpreted as objects of interest. To overcome this, the method includes an optional step of thresholding using a threshold image generated by mapping Image 2; see step 120. That threshold image is made up of pixels representing local threshold values.
In instances where a threshold image is used, binarization step 118 involves subtracting the threshold image from Image 3, then, mapping positive differences to 1 (indicating object) and negative differences to zero (indicating background).
Following binarization, the method of step 122 conducts connectivity analysis to determine the properties of any defects in the binarized image. Those properties, which include size, position orientation, and principal moments, can be used to determine whether the defect necessitates rejection of the lead frame.
In further embodiments, the invention contemplates an image capture arrangement as shown in FIG. 2B. Here, rather than employing two lighting sources, a system according to the invention captures light reflected from the element 40 under inspection in two different wavelengths. For this purpose, the lead frame is illuminated by a single light source 42, which can be, for example, a white light. Reflections from the lead frame captured by camera 26 can be filtered to capture the differing wavelengths. Such filtering can be provided, e.g., by filters 48, 50, which are selected such that objects on the surface of element 40 appear differently (if at all) with respect to the background when the filtered light is captured by the camera 46.
In addition to capturing light of differing wavelengths, filters 48 and 50 can capture light of differing orientations. To this end, they can be polarizing lens of differing orientation for capturing light from source 42 (which may also be polarized) that is reflected off the lead frame.
The embodiments discussed above are drawn to the inspection of semiconductor die lead frames. It would be within the capability of one of ordinary skill in the art to apply these teachings to the inspection of semiconductor die surfaces without departing from the spirit and scope of the invention. Indeed, commonly assigned U.S. Pat. No. 5,949,901, the teachings of which are incorporated herein by reference, discloses the inspection of semiconductor die surfaces using the same techniques as those described herein.
Described above are machine vision methods meeting the objects set forth. These methods provide improved machine vision semiconductor lead frame inspection overcoming the deficiencies of the prior art segmentation techniques, such as GTC. For example, apart from instances where an illuminated object is moved between image captures, the method does not require registration of images prior to subtraction. Nor the method require training. Still further, the method is applicable to the wide range of repeatable and nonrepeatable images. Yet still further, the methods hereof permit inspection of the full range of lead frame types, including flying/free lead configurations, even where the lead count is high. Moreover, these methods do not consume excessive memory or processing time, even in instances where the package under inspection is rotated.
It will be appreciated that the embodiments described above are illustrative only and that additional embodiments within the ken of those of ordinary skill in the art fall within the scope of the invention. By way of example, although the discussion herein primarily refers to subtraction of Image 2 from Image 1, those skilled in the art will likewise appreciate that Image 1 can, alternatively, be subtracted from Image 2 with like success (albeit with a reversal of "polarity" in the resulting image).
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Active Questions
|Sex & Intimacy / 12:23 AM - Friday March 30, 2012
do women wear thongs when they play sports?
My gf asked me to post this question. She wears nothing but thong panties and wants to go play basketball with me. She was wondering if girls/women wear thongs when they play sports.
- Asked by An Intellectual Guy, Male, 26-28, Student
I think that if they didn't,
- Response by stanorocks, A Guy Critical, Male, 36-45, Denver, Therapist
NO! sweat will make you chafe in between the buttocks if you wear a thong. I dont know about gals with NO BUTT at all...
- Response by discotrash, A Career Woman, Female, 29-35, Las Vegas, Other Profession
My daughter , and now a grand daughter dose. They prefer thongs. But my other daughter hated them. They played soccer , volly ball and basket ball.
- Response by morningdust, A Creative, Female, 56-65, Self-Employed
as far as I am concerned she can wear only the thong if she wants
- Response by bigcurt, A Mr. Nice Guy, Male, 56-65, Pittsburgh, Self-Employed
I used to assist coach train all types of female athletes both high school college even intramurals including sports such as indoor outdoor volleyball weight traing lifting aerobics running and so on many occasions I see women (girls) practice even play in a halter top and thongs in all of those sports you have to signal by icq number (mine is 307761638) or three digit number (mine is 633) another sport that I used to coach is futevolei
- Response by caneira12, A Mr. Nice Guy, Male, 36-45, Boston, Self-Employed
I personally don't find thongs comfortable, and can't think of anything worse than trying to run while something migrates up my backside. Having said that, it's her butt, and if she wants to try it and see if she can get away with the chafing that seems sensible. There are quite a few women at the gym who wear thongs under their running pants to workout. If she's planning on wearing a gym skirt though, definitely go for a full knicker, not everyone wants to flash their backside, or be flashed by others!
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If it were me, I would make up my own mind about my panties. ijs
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I'm sure there are girls/women that wear thongs, go commando, wear underoos, or granny panties.
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Pair of pillows with a multicolor washed effect and block pattern. Down-blend insert.


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Dr. Shuly Rubin Schwartz is the Irving Lehrman Research Associate Professor of American Jewish History and Walter and Sarah Schlesinger Dean of Graduate and Undergraduate Studies at The Jewish Theological Seminary. Since 1993, under her leadership, enrollment at List College has more than doubled.
Dr. Schwartz's most recent book, The Rabbi's Wife: The Rebbetzin in American Jewish Life, won the 2006 National Jewish Book Award in the area of modern Jewish thought.
Dr. Schwartz lectures widely on American Jewish life, the Jewish family, and Jewish women's studies. Sample lecture topics include:
A third-generation JTS graduate, Dr. Schwartz received her BA from Barnard College and her MA and PhD from JTS. Read a more detailed bio on Dr. Schwartz.
Dr. Shuly Rubin Schwartz
(212) 678-8826
Dr. Shira Kohn is associate dean of graduate and undergraduate studies at JTS, and enjoys working with students in both The Graduate School and List College. Dean Kohn received her doctorate from New York University's Joint PhD Program in Hebrew and Judaic Studies / History, and wrote her dissertation on Jewish college sororities and their encounters with postwar political and social movements. She is coeditor (with Hasia Diner and Rachel Kranson) of A Jewish Feminine Mystique? Jewish Women in Postwar America (Rutgers University Press, 2010), which was a finalist for the 2010 National Jewish Book Award's Barbara Dobkin Award in Women's Studies. At JTS, Dean Kohn teaches courses in Modern Jewish History, including Gender and Modern Jewish History, Jews and the City, and American Jewish History. She also serves as MA advisor to students in the Jewish Studies and Modern Jewish Studies programs.
A native of Chicago, Dean Kohn earned a bachelor's degree in Jewish Studies from Ohio State University, and remains an enthusiastic fan of Buckeyes football and Graeter's ice cream.
Dr. Shira Kohn
(212) 678-8024
Aliyah Vinikoor is associate dean of List College, where she directs the JustCity Leadership Institute and the Fellowship in Jewish Social Entrepreneurship. As an academic advisor for List College students, Dean Vinikoor is always happy to help with everything from choosing classes, planning ahead for study abroad and Commencement, answering questions about List College academics, and much more. List College students benefit daily from her dedication, empathy, and expertise on curricular, administrative, and interpersonal issues.
In addition to her role at List College, Dean Vinikoor serves as director of The Graduate School's Jewish Professional Leadership Program, a dual-degree program in which students earn an MA in Jewish Studies at JTS and an MSW or MPA from Columbia University. Dean Vinikoor earned a bachelor's degree in History from Barnard College, and worked in book publishing for seven years before receiving a master's degree in social work from Hunter College. She joined JTS after having directed several youth development programs in the South Bronx and Brooklyn. Originally from Seattle, Washington, she is pleased to bring her extensive experience in and passion for Jewish leadership, education, and engagement in social justice to JTS.
Aliyah Vinikoor
(212) 678-8826
Dr. Brian Smollett is assistant dean of List College and assistant professor of Jewish Thought. He is coeditor of Reappraisals and New Studies of the Modern Jewish Experience: Essays in Honor of Robert M. Seltzer (Brill, 2014), and has taught history and Jewish studies at Binghamton University, Queens College, and Hunter College, where he helped to direct and expand the Jewish Studies program. Dean Smollett received his PhD in Jewish and European History from the Graduate Center of the City University of New York, specializing in modern Jewish thought and the history of nationalism; an MA with distinction in Jewish Studies from JTS; and an MA in Modern History and BA in Judaic Studies and Philosophy from Binghamton University. He is pleased to return to JTS and to support List College students in discovering and achieving their goals.
Dr. Brian Smollett
(212) 678-8826
The List College Board
In 1995, List College established a Board of Overseers to provide support for the college. Under the leadership of founding chairperson Rabbi Harold Kushner, a noted author, the board raised awareness of List College in the broader community, spearheaded the Career Development initiative, and assisted with mentoring and recruitment.
Our current board chairperson, Rachelle Kaiserman, has established a Board Scholarship Fund and works with board members to enhance the mentoring program for graduating seniors and recent graduates.
In 1996, the College and Board of Overseers launched the Links to Leadership program. Through leadership workshops, mentoring opportunities, and an annual retreat, Links to Leadership trains List College students to assume roles as the next generation of lay leaders in the Jewish community.


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Giugliano said he would recommend the Mediterranean diet for people with type 2 diabetes because in addition to being lower in carbohydrates, the diet seems to have an effect on insulin sensitivity beyond its carbohydrate composition.
More information
Learn more about diabetes and diet from the American Diabetes Association.
SOURCES: Dario Giugliano, M.D., Ph.D., professor, endocrinology and metabolic diseases, Second University of Naples, Italy; Carolyn Grubb, R.D., certified diabetes educator, Scott & White Specialty Clinic, Round Rock, Texas; September 2009 Annals of Internal Medicine
|Copyright©2009 ScoutNews,LLC.
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Ironman Texas training for Week #6 was certainly the first step in a new direction. The rubber met the road this week with a swing from fantastic to craptastic and back again a few times. I was emotionally and physically spent after this week and that let me know that we are about to get to work FOR REAL!
Numbers to date are:
- Swim: 29.6 miles (3% of total miles)
- Bike: 689 miles (76% of total miles)
- Run: 189 miles (21% of total miles)
- Total Miles: 907.6
- Swim: 19 Hours (24% of total hours)
- Bike: 36 Hours (45% of total hours)
- Run: 25 Hours (31% of total hours)
- Total Hours: 80.5 Hours


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The AMD Board has developed a set of Principles of Corporate Governance as a framework for its oversight activities devoted to protecting and advancing the long-term interests of shareholders and other stakeholders—including employees, customers, suppliers, creditors, and the communities where we operate.
View AMD's Principles of Corporate Governance.
The AMD Board will continue to assess the appropriateness and effectiveness of these principles and to update these guidelines periodically as needed.
AMD employees can report illegal activities, violations of the Worldwide Standards of Business Conduct or obtain guidance about AMD policies by calling the AMD AlertLine (1-800-381-6221). The AlertLine is toll-free, multi-lingual, accepts anonymous reports and is accessible 24 hours a day, seven days a week.
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Chris Hegarty, Nicky Law, Ian Black and Dean Shiels were on target at Ibrox where the hosts opened their League 1 campaign with a straightforward three points.
This followed on from last Saturday's cup defeat at Forfar and Wallace admitted: "We were all devastated in that dressing room last week but we knew we couldn't feel sorry for ourselves.
"It was actually quite good in a way that we had the Newcastle game a couple of days later because that lifted the spirits really quickly for us.
"We performed well on the night against top opposition (Tuesday's friendly at Ibrox ended 1-1) and that set us up for a good week.
"We were ready and we were buzzing come Friday and I think we have put a message out that we are ready to try to put a lot of goals past teams."


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Well, there goes Joe Biden again. Yesterday, he appeared in New Jersey to announce federal backing for a new tunnel. He said that it would be a great boost for automobile commuters — a statement that left the people actually working on the tunnel wondering how the cars would maneuver along those big, parallel steel rails running down the middle of the structure.
This is but the latest (if one of the milder) episodes of our vice president "just being Joe." The man's ability to shove both feet in his mouth and still keep spouting nonsense is beyond legend. Fortunately, most of Joe's blunders are harmless — inviting a handicapped man to stand up and wave to the audience, describing then-Senator Obama as "clean and articulate," etc. They're good for a laugh or two at his expense, but they're readily dismissible.
Others fall into the category of the classic definition of a gaffe — when a politician inadvertently says the truth. These are the remarks that make those around him wince and cringe, and even occasionally rebuke him. Examples include his zinging Chief Justice Roberts over the fumbling of Obama's oath of office, his stating that Hillary Clinton would probably be a better choice for veep than him, and his recent mocking of Obama's use of teleprompters.
Every now and then, though, Joe outdoes himself and says something that could cause genuine harm. During the initial stages of the Swine Flu (I'm sorry — "H1N1 Flu") outbreak, he stated that he was urging his family to avoid public transportation, especially air travel, to stay safe — advice that the perpetually struggling airlines did not need to hear. And he casually revealed the existence of a previously top-secret bunker under the Vice President's residence on the grounds of the Naval Observatory.
Perhaps his latest slip of the tongue was no slip and the government-owned General Motors will come out with new car models that can run on tracks.


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Hang tight!
Recipe by Mary Jo
"This recipe, adapted to use the traditional flavors of Classico® Pasta Sauce, was originally submitted by Allrecipes home cook Mary Jo."
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2 large
zucchini, thinly sliced
2 tablespoons
olive oil
1 large
onion, diced
2 cloves
garlic, minced
16 ounces
Classico® Tomato and Basil Sauce
1 cup
shredded mozzarella cheese
Very good! The only thing is to be sure that you get all the extra water off the Zucchini. Other than that, I baked it a little longer, about 30 minutes because I like the cheese a little crispy. I can't wait to eat the leftovers tomorrow!
Delicious! I added in some artichokes sliced up and some spinach as well it tasted just like a good pasta dish!
13 Ratings
this was really good. I made it exactly as instructed. Feels like something else good be added, but good nonetheless. Tastes almost like spaghetti.
This recipe is a great start! My only complaint is that it ended up WAY too watery after boiling the zucchini. Next time I'll make sure to dry the zucchini much better - but I will definitely make this again!
We LOVED this dish! I tweaked it, but not much and WOW, did we love the original recipe with a few modifications. I sliced the zucchini super thin and layed it out on the kitchen island on paper towels with paper towels on top covered with heavy pans on top of it to draw out the "water" from the zucchini. I added red pepper flakes and black pepper to the sauteed onions. Then I added prepared creamed spinach to the onion mixture. All in all, this tasted like true parmesan. Fantastic! Thanks for a great recipe, Mary Jo.
Has anyone besides me noticed there's no Parmesan in this? I added about 1/2 cup on top. While I was sauteeing the onion, I drained the zucchini in a collander, and then I pressed it with several thicknesses of paper towels. No excess moisture problem. While it's not the prettiest dish, it certainly tasted really good, and I'll definitely make it again.
Easy, quick, cheap, healthy-- what's not to love?
* Percent Daily Values are based on a 2,000 calorie diet.
Easy Zucchini Parmesan
Serving Size: 1/5 of a recipe
Servings Per Recipe: 5
Amount Per Serving
Calories: 183
Calories from Fat: 89
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|City Administration > Public Information Office
|Anaheim Mayor Curt Pringle to Host Restoring Community Conference
March 11 conference brings together leading thinkers in urban planning and public policy
ANAHEIM, CA - (March 1, 2010) - City of Anaheim Mayor Curt Pringle, in partnership with the Urban Land Institute (ULI) Orange County/Inland Empire, is pleased to host the second Restoring Community Conference on March 11. This unique forum gathers public sector officials, land use planning and real estate development professionals to present and discuss their thoughts and ideas related to building cities and community. The conference will be held at Disney's Grand Californian Resort and Spa, starting at 8 a.m. and concluding at 4:30 p.m.
The 2010 conference, "Creating Cities that Protect Private Property, House the Family and Foster Civic Culture," will offer thoughtful debate and viewpoints from nationally known speakers and panel discussion participants. The headlining speakers include: Joel Kotkin, presidential fellow in Urban Futures, Chapman University; Michael Barone, senior political analyst for the Washington Examiner and Fox News Channel contributor; and Caitlin Flanagan, award-winning journalist, author, social critic, and a contributing editor and book reviewer at The Atlantic Monthly. A full list of participants can be found at www.restoringcommunityconference.com.
"This year's program will challenge the current thinking in several areas of community planning," said Mayor Pringle. "Our speakers and panelists are experts in their respective fields, and I look forward to hearing their perspectives on how to effectively enhance a city without losing the critical spirit of community."
The conference will focus on trends in modern urban planning and how property rights, land use tools and even civic culture impact a community's ability to attract and retain families. Panel discussions will include focus on the meaning of family and community in the 21st century American city, community values vs. property rights, and housing the modern American family.
Disney's Grand Californian Resort and Spa is located at 1600 S. Disneyland Dr., Anaheim, CA 92803.
Complete details and ticket information for the Restoring Community Conference can be found at www.restoringcommunityconference.com
Media Contact: Ruth Ruiz 714.765.5060more city news
ABOUT ANAHEIM –The City of Anaheim, founded in 1857, is one of the nation's premier municipalities and is one of California's most populous and most visited cities. Anaheim covers 50 square miles with more than 351,000 residents and more than 2,900 City employees. The municipal corporation's annual budget is $1.7 billion. Anaheim supports a thriving business community with companies such as: Carl Karcher Enterprises, Inc.; L-3 Communications; Pacific Sunwear; and Disneyland Resort. Successful sports franchises call Anaheim home, including: Angels Baseball; Anaheim Ducks; the U.S. Men's National Volleyball Team, and the 2012 Olympic Games Silver Medal winning U.S. Women's National Volleyball Team. Anaheim also boasts world-class meeting and entertainment venues with: The Anaheim Convention Center, LEED-certified and the largest on the west coast; Honda Center; City National Grove of Anaheim; Anaheim GardenWalk; Angel Stadium of Anaheim; and ARTIC (Anaheim Regional Transportation Intermodal Center). In addition, Anaheim embraces its vibrant cultural arts community, including the world-renowned Anaheim Ballet. Annually, Anaheim welcomes more than 20 million visitors to the City, truly making it where the world comes to live, work and play. For more information, please visit www.anaheim.net.
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|New Hampshire is selected as one of five states for a national education initiative called SWIFT (School-wide Integrated Framework for Transformation)
|Sites from CCSSO's Innovation Lab Network (ILN) in Kentucky, New Hampshire and Wisconsin were awarded Next Generation Learning Challenges (NGLC) Wave IV grants, aimed to accelerate educational innovation to improve college and career readiness for all students.
|Schools in MA, NH, and ME receive $195,000 in grants through the Harvard Pilgrim Health Care Foundation's Healthy School Food Champions program.
|Drawn to the Music is a collaborative arts project combining reading classic stories, listening to great music and creating original illustrations in response.
|Institutions of Higher Education (IHE) Network
|Monarchs Education Day
|Navy National Defense Cadet Corps (NNDCC) Program
|NHPTV PBS Kids Writers Contest
|Real World Design Challenge (RWDC)
|The State of NH Robotics Education Fund
|Sanborn Regional School District in Kingston Receives Magna Award
The mission of Special Olympics New Hampshire (SONH) is to provide year-round sports training and athletic competition in a variety of Olympic-type sports for children and adults with intellectual disabilities (ID), giving them continuing opportunities to develop physical fitness, demonstrate courage, experience joy and participate in a sharing of gifts, skills and friendship with their families, other Special Olympics athletes and the community.
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