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October 3, 2013
Lake George Village Zoning Board of Appeals members (left to right) Ron Mogren, Tom Sullivan and Mike Ravali listen to hotel owner Salim Amersi present a proposal Oct. 2 to demolish the main three-story building at his Surfside on the Lake resort and replace it with a six-story structure that includes 60 rooms atop a two-story parking garage.
Stories this photo appears in:
Surfside's six stories slammed
There was considerable opposition early this year when the village board adopted a new zoning code that allowed buildings as tall as 72 feet high in selected spots in Lake George Village, but generally not on the east side of Canada Street near the lake. And now that a lakeside resort owner has asked for a variance to also build six stories, the outcry is more vocal.
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Note: as of November 17, 2009, employees of DHHA are no longer required to sign Associate Member Practice Agreements and are therefore not UPI members.
New faculty members with clinical responsibilities will be contacted by UPI to sign the MPA. New faculty members that do not have clinical responsibilities will also be required to sign an MPA, which will be included with their letter of offer.
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Ever since we moved into our new digs, I've been wanting to find appropriate furnishings that reflect our lifestyles. You see, both my husband and I are working professionals. He owns his own architecture firm and I'm a fashion designer. Although both fields are often considered on the same level in terms of how design-forward they are, we actually both have relatively divergent tastes in what we find aesthetically pleasing. He likes bright module furniture that can be assembled with no screws while I prefer the avant garde kinds with sleek and modern straight edges.
What we both can agree upon is that we need a contemporary bathroom design. Contemporary vanities are just more in tune to what we find attractive. The difficult part is seeing eye to eye on the more specific features of the vanity. I decided that the only way to settle it was to go online to find a store that carries the bathroom vanity that fits us perfectly.
At Premiere Vanities, they have a fantastic selection of all different kinds of bathroom vanities. It was here that I spotted the bathroom vanity of my dreams. It's a contemporary glass top double bathroom vanity. The square-ish porcelain sink basins sit above the natural stone countertops. All the little touches such as the faucet and legs are made out of a shiny steel. My favorite part, by far, is the tempered glass windows on the cabinets. It's just so elegant! I showed my husband the bathroom vanity later and to my surprise, he loved it! I think we've finally found a common ground.


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Our outcomes laboratory provides opportunities for research and training at the undergraduate, medical student, graduate student, and postdoctoral fellow levels. The scope of work for laboratory members includes learning and applying methods in epidemiology, biostatistics, data systems analysis, computer analytic code writing, and use of neuro-imaging software in concert with our retrospective brain tumor databases, national outcomes databases, and prospective quality-of-life brain tumor databases. Members of the lab are expected to produce meaningful manuscripts that significantly contribute to the literature, in addition to writing relevant book chapters and grants for future work. Members of the lab are also exposed to work from associated laboratory effort, including exposure to our skull base laboratory, basic science stem cell laboratory, and historical Harvey Cushing Archives project.
Post-Doctoral Training
We currently have positions available for highly qualified post-doctoral scientists interested in brain tumor clinical research. Interested applicants should have excellent skills in biostatistics, epidemiology, and the design of clinical trials to participate in projects aimed at making progress towards understanding and treating brain cancers. Please send your CV and references to Dr. Alfredo Quiñones-Hinojosa (firstname.lastname@example.com).
Graduate Student Training
Excellent dissertation project opportunities exist in our laboratory for clinical brain cancer research. Students currently enrolled in the any of the Johns Hopkins University graduate programs are welcome to plan research rotations within our laboratory. Students in the MD/PhD program or graduate programs of Neuroscience, Public Health, or other programs are welcome to discuss research opportunities in the laboratory.
Neurosurgery and Neurooncology Laboratory Research Fellows
Our laboratory provides opportunities for clinical fellows seeking a research project in brain cancer clinical research. The Johns Hopkins Department of Neurosurgery provides a two-year research opportunity for residents and this laboratory provides one of many flexible environments for ground-breaking research in neurooncology. Also at Johns Hopkins, in combination with the NIH, is an NIH-funded training grant, Research Training in Neurooncology, which provides a means for clinical fellows to gain new experiences in clinical care and laboratory research.
Past members in our laboratory have been supported by the following fellowships and awards:
- ABTA Medical Student Summer Fellowship - Application due in January
- Howard Hughes Medical Institute Fellowship - Application due January 11th
- Doris Duke Clinical Research Fellowship - Application due January
Other opportunities supported by our laboratory include:
- Medical Student: CNS Medical Student Summer Fellowship in Socioeconomic Research - Application due February 1st
- Postdoctoral Fellow: CNS Cushing Fellowship - Application due November 30th
- Postdoctoral Fellow: CNS Dandy Fellowship - Application due November 30th


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(Source: FameFlynet Pictures)
2002 - 2002
Famke Janssen has said that she and Affleck, seven years his senior, were "just friends" but multiple sources told...
Famke Janssen Wall
Famke Beumer Janssen (born November 5, 1964) is a Dutch actress and former fashion model. She is best known for her roles in 'GoldenEye,' 'Nip/Tuck' and as Dr. Jean Grey/Phoenix in the 'X-Men movies.' Janssen is also a UNODC Goodwill Ambassador for Integrity. Find Famke Janssen news, videos, and pictures here.
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Landlord / Tenant Court Proceedings are referred to as Summary Eviction Proceedings.
Jurisdiction for Landlord / Tenant Summary Proceedings in New York City.
There are two (2) types of Landlord/Tenant Proceedings
Landlord / Tenant Proceedings in New York City
There is a whole body of law that covers Landlord Tenant Issues in New York.
In New York City, there are many apartments that are regulated by laws known as Rent Stabilization or Rent Control. These laws have statutory protections and rules that apply to both landlords and tenants.
Landlord / Tenant Court Proceedings are referred to as Summary Eviction Proceedings.
Summary Proceedings are intended to be an expedited court action. This means there are statutory procedures in place whose purpose is to achieve a final court order faster in a landlord / tenant dispute than in other legal lawsuits.
Jurisdiction for Landlord / Tenant Summary Proceedings in New York City
The New York City Civil Court hears Summary Eviction Proceedings and sets up a Special Part, known as the Housing Part, (Housing Court (or) the Landlord-Tenant Court) to hear such proceedings.
There are two (2) types of Landlord/Tenant Proceedings
Nonpayment Proceeding
If a Tenant is not paying the monthly rent as required by their lease.
The tenant must be in possession of the Apartment in order for the Landlord to commence a summary nonpayment proceeding.
If the Tenant is no longer the tenant, and has moved out, the Landlord must commence what is called a plenary action. The Housing Court does not have jurisdiction.
Holdover Proceeding
Commenced by a Landlord if a Tenant is violating specific terms of the lease (ex. Subletting without permission of the Landlord; Causing a Nuisance; Violating a No-Pet Clause in the lease).
Both types of Proceedings have "Pre-Notice Requirements" (notices that must be served to the tenant before it can be bought to Court). After the Notices are properly served, and the time requirements have expired, then a Notice of Petition and Petition are served upon the tenants. The Notice of Petition / Petition are the equivalent of what is commonly known as the Summons and Complaint in other legal proceedings.
The majority of New York City is apartment living, and as a result there are many legal issues Landlords and Tenants encounter every day. This is why there is an entire body of law and a separate part of the New York City Civil Court devoted entirely to Landlord / Tenant issues and disputes.
If you have any questions or require legal assistance on any Landlord / Tenant issue, please call the Law Office of Paul R. Kenney, LLC.
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As the title says. I would like a script that tells windows that the next boot should be into safe mode or atleast that the F8 menu should be presented next boot.
Booting into WinRE(Launch startup repair...) is problably even more un-doable.
I looked over bcdedit options but did'nt see anything like this.I know msconfig has an option for safe boot but it's gui only.
Currently if i wan't to boot into safe mode or launch WinRE then i have to forcefully restart my pc first for those options to be presented during boot(F8 does not bring up the safe mode option under normal conditions).
Im using Windows 7 x64.


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Brand new iPhone 5S? Want to protect that beautiful piece of hardware but still want to show off its shiny gold or silver backing? Then hook yourself up with not one, but two protective, minimalist cases that won't hide your phone's backside. After you're covered, plug in a sexy new pair of earbuds, put on your favorite song, and rock out.
Coming at ya from one of the hottest names in smartphone accessories is the id America iPhone Bundle, including the Ice and Dry Ice iPhone 5/5S cases and the New Spark In-Ear Headphones.
- ICE: A two-piece crystal clear polycarbonate case that gives you reliable protection while still preserving the look and feel of your iPhone.
- DRY ICE: A two-piece soft-grip polycarbonate case that features a "frosted" glass finish and improved grip from the soft rubber coating.
- New SPARK In-Ear Headphones: High-definition in-ear headphones that deliver full, resonating bass, intense mid-range, and clear, defined treble sure to bring a smile to any audiophile's face. With precision acoustics, unique, modern design, and precise ergonomic fit, these headphones come ready to play.
So why do we love it?
All three of these products look, feel, and perform like they should cost way more than they do. When we find companies that take pride in their offerings and stay competitive with pricing, it's difficult not to endorse them, and that's exactly what id America has done here.
Compare the new SPARK headphones with the higher priced Klipsch S4 earbuds or Bose ie2 earbuds (id America told us to) and we think you'll agree it's at or above the bar set by those two huge-name brands.
Similarly, we looked at the Incase Snap Case, priced higher than the Ice and Dry Ice cases, and if there was any apparent difference, we didn't see it.
To learn more about this iPhone 5/5s accessory bundle click the button below for more information. Right now iJailbreak is able to offer the bundle for only $57.99, which is 46% off its retail price.
Note: Only available to customers in the continental United States. The sale price includes shipping and all sales are final.


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For those people who are allergic to cow's milk, a solution may be on the way. Researchers from New Zealand have produced transgenic cows that are devoid of a common allergen.
Beta-lactoglobulin (BLG) is a protein that is found in cow's milk but not in human milk. It is one of the components in milk that people could be allergic to. The functions of BLG remain unknown, and it has been generally believed that it a dispensable component of milk which doesn't greatly alter its nutrition besides adding to its protein content. Scientists have now produced a transgenic cow that has as much as a 96% reduction in the amount of BLG.
Silencing a Gene Instead of Removing It
Earlier attempts to engineer this reduction in BLG involved removal or modification of the cow's BLG gene in its genome. This, however, proved a very difficult process. The current method works around this difficulty using another approach. To understand this approach, let's revisit how a protein is produced in the body. The gene for the protein is encoded in the cow's DNA. This gene is first processed into an intermediate molecule called RNA, which is then processed into the complete protein.
The research team has added silencing sequences of DNA to the cow's genome. These sequences are called miRNAs (short for micro-RNAs) and when expressed in the cell (by processing of their sequences), bind to the BLG RNA. This binding prevents the BLG protein from being produced. Moreover, these 'silencing sequences' have been inserted in such a fashion that these miRNAs are only produced when the cow is lactating. This is to minimize possible side effects. A cow cell nucleus was modified thus, and inserted into a cow egg cell, fertilized and implanted into a cow. A healthy female calf was born. This calf, strangely, had no tail. Further study is required to find out if BLG is in any way connected to tail growth in cows.
Other Allergenic Proteins Could Also Be Thus Removed
In the United States, 2 to 3 percent of infants are allergic to cow's milk proteins. A significant proportion of these infants could benefit from hypoallergenic milk. Other proteins present in cow's milk, such as casein, are also responsible for a significant proportion of allergies. This result highlights the potential of transgenics in coming up with solutions. Do note that lactose intolerance is induced by a different component of milk—a sugar called lactose—and is not the problem that this project addresses.
You can read about this research here.


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Very few Spaniards celebrate turning 19 by having a kick-about with some 100 youngsters on a muddy pitch in the freezing cold rain in Allerton, South Liverpool.
But for Reds star Suso this was the case on Monday afternoon when he enlisted the help of countryman Dani Pacheco to open the Liverpool FC Foundation Football College.
Based at Wyncote Sports Ground and equipped with top-of-the-range facilities supplied by the University of Liverpool, the new college will be open to boys and girls aged between 16 and 19.
Students will work under the guidance of experienced staff from Liverpool's Academy and coaches from the Sport Art Learning and Training (SALT) college, to hone their football skills as well as gain academic qualifications.
And birthday-boy Suso witnessed first-hand, the fine work being carried out at the college, when he and Pacheco joined the students for training drills and then a five-a-side match.
"It has been a great experience today," Suso told Liverpoolfc.com. "I think it is really nice for the youngsters to see us here and we have definitely had a nice time joining in with their coaching.
"I hope all the lads have enjoyed themselves."
Pacheco said: "It's good to come here and see the boys training and it's good that we can help motivate them.
"To see them enjoying their football is great and there is plenty of quality here. The lads are all committed to the course and it's great to see them getting opportunities like this."
The basis for the LFC Foundation Football College was SALT, a scheme which offered youngsters the chance to take advantage of a different approach to secondary education and began with bases in Knowsley and Halton.
The brainchild of David Rowe and David MacDairmid, SALT recognised the importance of engaging local youngsters in something that would make a difference to their lives.
Now, in partnership with the LFC Foundation and University of Liverpool, the new football college gives young people the opportunity to gain level 1, 2 and 3 qualifications in maths, English, ICT and PSD as well as in sport.
Students also have the chance to gain invaluable experience as part of a two-week involvement in some of the LFC Foundation's community programmes and have opportunities to test themselves in teams that participate in national league and cup competitions.
"The idea is to engage local youngsters and give them an opportunity through football," said MacDairmid. "The club has a great image in this city and so we aim to harness that to attract youngsters who may be not have been engaged in education or employment.
"We get them involved in something worthwhile and give them opportunities to progress in life.
"The support we have had from the club and Pete Sampara at the University of Liverpool has been excellent and without their support, we would not be where we are today."
After joining in a short coaching session with the students and their mentors, it was time for Suso and Pacheco to take part in a question and answer sitting with the college's A-level group.
As well as the Spaniards, Academy manager Frank McParland, head of education and welfare Phil Roscoe and first-team coach Mike Marsh were also on hand to field questions from the inquisitive youngsters before Pacheco presented presented Suso with a birthday gift to round the afternoon off.
"I was lucky enough to play for Liverpool's first-team when I was younger but when I was aged 16, 17 or 18, there were no courses like this available to others," said Marsh in response to one youngster's question.
"So if I was to give any advice to young people today, it would be for them to get qualified in what it is they want to do.
"People like Dave Rowe and Dave MacDiarmid, here at the LFC Foundation Football College, will help young people become qualified.
"There is no doubt that courses like this help youngsters get on the road towards where they want to be."
To get in touch with the football college, email contactus@salteducation and follow @saltliverpool for more details.
Buy your tickets for the Europa League tie against Young Boys now>>
Tagged: LFC Foundation , Suso , dani pacheco , football college , pacheco
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Herd wants more offense
HUNTINGTON -- Following Tuesday's initial Marshall University spring football practice, many of the questions surrounding the Thundering Herd offense centered on one general theme.
How does a team that put up so many points and yards in 2012 improve on one of the more successful offensive seasons in recent Thundering Herd history?
The question appeared to almost surprise quarterback Rakeem Cato, who started rattling off several different items the Herd is focused on for 2013.
"We've just got to keep going hard and bring our A-game every day," Cato said. "Don't get big-headed. It was one season and that season is out of the way. This is a new year and we've got to keep going on."
While the up-tempo scheme will remain intact under offensive coordinator Bill Legg, every offensive spot will be learning their discipline under a new coach in 2013.
In addition to his duties as offensive coordinator, Legg will take over coaching quarterbacks for Tony Petersen, who left for Louisiana Tech.
Cato will not only have a new coach, but several new targets after the graduation of impact seniors Aaron Dobson, Antavious Wilson and Andre Snipes-Booker.
Now, names like Shawney Kersey, Davonte Allen and Devon Smith will become more prevalent, along with Cato's former high school teammate and favorite target from 2012, Tommy Shuler.
Shuler returns after an All-Conference USA season at wide receiver when he broke the Marshall season reception mark with 110 for 1,138 yards and six touchdowns.
The receivers will have a new coach in former NFL wide receiver Mike Furrey, who comes to Marshall after being the head coach at Kentucky Christian.
Shuler said he's eager to learn under Furrey.
"I feel like he's going to push me harder just because he knows what I've got to do to get to the next level," Shuler said.
The three-headed freshman monster at running back -- Conference USA Freshman of the Year Kevin Grooms, Steward Butler and Remi Watson -- all will learn under new running backs coach Thomas Brown, who owned his own chunk of success as a running back at Georgia.
The trio accounted for more than 1,600 yards and 18 touchdowns in 2012.
Marshall tight ends will have a new coach in Todd Hartley, who moves over to the offensive side from safeties and Alex Mirabal takes over the offensive line with Legg's switch to quarterbacks.
Junior center Chris Jasperse said the entire unit is focused on refining its skills -- whether it be blocking for the run a bit better to be a more balanced offense or simply taking care of things a bit better to translate close losses into victories. That was a problem in 2012 with four of the losses by a score or less.
"Last year's offense, we did well, but not as good as we could," Jasperse said. "There were a lot of times late in the game when the ball was in our hands and even though we put a lot of points up, we couldn't finish. In order for us to win, it has to be offense and defense together.
"It doesn't matter if we put up 80, the other team could still score 81 without the other side. At the same time, if our defense holds them to seven, we won't win if we don't finish. We have to finish. We do that, and we'll have a successful year."
The Herald-Dispatch welcomes your comments on this article, but please be civil. Avoid profanity, obscenity, personal attacks, accusations of criminal activity, name-calling or insults to the other posters. Herald-dispatch.com does not control or monitor comments as they are posted, but if you find a comment offensive or uncivil, hover your mouse over the comment and click the X that appears in the upper right of the comment. If you do not want your comment to post to your personal Facebook page, uncheck the box below the comment.


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A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
1. A nonvolatile memory comprising:
an array of memory cells wherein wordlines within each memory cell are divided into a plurality of byte-wordlines; and
a plurality of byte-wordline decoders formed in an undivided triple well and located outside of said array of memory cells and connected to said byte-wordlines by a plurality of metal lines wherein said array of memory cells and said plurality of byte-wordline decoders are located on a single chip.
2. The memory according to
3. The memory according to
4. The memory according to
5. The memory according to
6. The memory according to
7. The memory according to
8. The memory according to
This is a division of patent application Ser. No. 10/223,208, filing date Aug. 19, 2002, now U.S. Pat. No. 6,862,223 A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divide-Well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout, which claims priority to Provisional Patent Application Ser. No. 60/394,202, filing date Jul. 5, 2002, A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write No Disturb And Divide-Well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder, assigned to the same assignee as the present invention, which are herein incorporated by reference in their entirety.
Co-pending U.S. patent application Ser. No. 09/852,247 to F.C. Hsu et al filed on May 9, 2001 and Ser. No. 09/891,782 to F.C. Hsu et al filed on Jun. 27, 2001.
(1) Field of the Invention
The present invention relates to a novel combination nonvolatile memory and a novel embedded memory. The nonvolatile memory is comprised of three key memories: ROM (Read-Only-Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) and FLASH. The embedded memory is comprised of the combination of the above three nonvolatile memories, SRAM, CPU, and shared buses of data, address, and control signals.
(2) Description of the Prior Art
ROM data can only be altered at the manufacturing site by changing the costly photo mask sets, while both data of EEPROM and FLASH is allowed to be in-system flexibly changed at user's site at lower cost and faster throughput than ROM. The main differences in product specification requirements between FLASH and EEPROM are not the write scheme nor write speed but the write size and endurance cycles. Endurance cycle stands for the number of successful program and erase cycles when changing FLASH or EEPROM data. Write operation in the present invention means an erase is commonly performed first and then followed by a program operation.
For example, both Flash and EEPROM memories can perform on-chip erase and program operation without relying on an external high-voltage power supply. In other words, a single low-voltage VDD supply is sufficient for in-system data reprogramming for both memories. Typically, only two preferred erase schemes such as edge-FN tunneling or channel-FN tunneling are extensively employed in both FLASH and EEPROM memories. Traditionally the program schemes are more available than the erase schemes. Besides FN-tunneling, CHE (Channel-Hot-Electron) and SCHEI(Source-side Hot-Electron-Injection) are the dominant schemes for 1Tr-ETOX(Electrically-Tunneling-Oxide) and 1.5Tr split-gate flash memory respectively. The technology that uses FN-tunneling erase schemes includes 1Tr-NAND FLASH from Toshiba and Samsung, 1Tr-AND from Hitachi, 1Tr-Dinor from Mitsubishi, 1Tr-OR from Aplus and EEPROM of 2Tr-FLOTOX. The major product specification differences between FLASH and EEPROM are the write-size and P/E cycles. For example, FLASH typically only performs page (128 B) or block (64 KB) erase and page (128 B) or byte (1 B) program, while EEPROM requires byte (1 B) erase and byte (1 B) program, causing large overhead in the cell array area. The EEPROM data change size is down to the level of one single byte, much smaller than FLASH erase size. The EEPROM cell structure and program erase scheme are designed for highly reliable FN-channel erase and FN-channel program to achieve high P/E cycles. Furthermore, the data change rate of EEPROM is much higher than FLASH, thus P/E cycles of more than 500K and write speeds of less than 10 mS are strictly requirements in EEPROM. In contrast to EEPROM, today's majority of leading FLASH cells, cell operating schemes, process and its associated array architectures are neither optimized for the schemes of FN-channel erase and FN-channel program nor for meeting a byte operation product specification.
Traditional FLASH memory is less flexible than EEPROM in erase size, but 2Tr-FLOTOX EEPROM suffers a big penalty in cell size and cell array area. There are two disadvantages that cause this larger cell size and cell array area of 2Tr-FLOTOX EEPROM. One is the non-scalable cell structure due to a requirement of extremely high program voltages of 15V in the bitline. The other disadvantage is the requirement of flexible byte erase and byte program, which results in an unique area consuming cell array architecture-divided wordline and divided bitline in units of bytes. The unique byte-array organization allows EEPROM cell to perform FN-channel erase and FN-channel program for highly reliable P/E cycles without disturbing the remaining bytes either in the same selected wordline or the same selected bitlines. Since the cell structure and P/E scheme of traditional 2Tr-FLOTOX EEPROM technology is not scalable as compared with its FLASH counterpart, the highest density of EEPROM technology available in 2002 is only 1 Mb made of 0.25 um, while FLASH is 1 Gb made of 0.12 um. The density of EEPROM is about 1000 times behind FLASH in the nonvolatile market.
In conclusion, there is a strong market need for faster byte-erase and byte-program (less than 10 mS), higher P/E cycles (more than 500K) and the larger density (more than 1 Mb) at a lower manufacturing cost. e.g. A demand for low-cost FLASH-based EEPROM to offer comparable PIE cycles like EEPROM on the units of byte.
Recently, several FLASH-based EEPROM cells of prior art were disclosed claiming to have high cell scalability and highly reliable P/E cycles with the same P/E schemes of FN-channel-erase and FN-channel program. These recent prior arts intend to replace the un-shrinkable 2Tr-FLOTOX EEPROM cell and technology. Although the proposed FLASH-based EEPROM cell sizes are indeed being improved to be smaller than their FLOTOX counterparts to achieve the single-byte erase and program, the cell arrays turn out to have larger overhead than FLOTOX-array. For example, in Toshiba's disclosed 3Tr-NAND and 4Tr-NAND (as well as other prior art), the cell array is divided into a vertical triple-well for each single byte pitch. These are disclosed in Toshiba's U.S. Pat. Nos. 6,370,081 and 6,400,604. As a consequence, the total die area of Toshiba's proposed FLASH-based EEPROM still has a very large overhead. This overhead is drastically increased as the cell geometry is shrunken smaller and smaller.
Other patents disclose FLASH or EEPROM memories. These include Infineon's U.S. Pat. No. 6,307,781 to Shum, U.S. Pat No. 6,212,102 to Georgakos et al, and U.S. Pat. No. 6,266,274 to Pockrandt et al, U.S. Phillips' U.S. Pat. No. 6,174,759 to Verhaar et al and U.S. Pat. No. 6,326,661 to Dormans et al, and Aplus' U.S. Pat. No. 5,748,538 to Lee et al and co-pending U.S. patent applications Ser. Nos. 09/852,247 filed on May 9, 2001 and Ser. No. 09/891,782 filed on Jun. 27, 2001, herein incorporated by reference.
The present invention overcomes all the above said drawbacks in 2Tr-FLOTOX-EEPROM, Toshiba's 3Tr-NAND and 4Tr-NAND and other similar FLASH-based EEPROM technologies. A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during PIE operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
The present invention has been made with consideration of the above said drawbacks, and has as its object the provision of a new nonvolatile cell structure, cell operating schemes and conditions, cell process and cell array architectures. These are designed to replace traditional byte-erasable and byte-programmable 2Tr-FLOTOX EEPROM memory cell, Toshiba's 3Tr-NAND and 4Tr-NAND cells, Infineon's newly 2Tr cell and other similar FLASH cells. Furthermore, the same EEPROM cell structure, cell operating schemes and conditions and process can be extended to integrate FLASH or ROM or both with EEPROM for a monolithic combo nonvolatile memory.
An object of the present invention is to provide a unified, highly-scalable nonvolatile cell structure and process made of BN+ S/D(source/drain) for integrating large-size erase FLASH, single-byte erase EEPROM and photo-mask programmable ROM into one monolithic nonvolatile memory.
Another object of the present invention is to provide a combo monolithic nonvolatile memory comprised of FLASH and EEPROM. The FLASH part allows page (128 B) and block (64 KB) erase, while the EEPROM part supports single byte (1 B) and page (128 B) erase through the use of the same cell structure and same P/E schemes. FLASH can be used to store either program code or program data but EEPROM is dedicated for data storage.
Another object of the present invention is to provide a combo monolithic nonvolatile memory comprised of ROM and EEPROM. ROM data can only be altered by photo mask changes at the manufacturing site, while EEPROM part similarly supports single byte (1 B) and page (128 B) erase at the user site.
Still another object of the present invention is to provide a monolithic nonvolatile memory that employs the unified cell program and erase scheme of FN-channel erase and FN-channel-program for both FLASH and EEPROM in one chip.
Yet another object of the present invention is to provide a nonvolatile cell that is comprised of 3Tr BN+ S/D as derived from FLASH OR-array proposed by the same inventors of the present invention for zero disturb during byte-erase and byte-program operations.
Yet another further object of the present invention is to provide a nonvolatile cell that is comprised of 2Tr BN+ S/D as derived from FLASH OR-array proposed by the same inventors of the present invention for minor bitline disturb and zero wordline disturb during byte-erase and byte-program operations to further reduce cell and array size.
Still another object of the present invention is to provide a novel zero-disturb row-decoder scheme and unique layout technique that horizontally outputs a plurality of metal lines connecting to the selected wordline in units of bytes in BN+ cell array, to completely remove the vertically divided triple well on a byte basis in Toshiba's byte-writable EEPROM array comprising either 3Tr-NAND or 4Tr-NAND cell structures as well as other similar byte-writable arrays.
Yet another further object of the present invention is to provide a novel zero-disturb column-decoder scheme and unique layout techniques that vertically output a plurality of metalline buses connecting to the selected wordline in units of bytes in BN+ cell array to completely eliminate the vertically divided triple well on byte basis in Toshiba's 3Tr-NAND or 4Tr-NAND cell structures as well as other similar byte-writable cell arrays.
A further object of the present invention is to provide novel schemes of zero-disturb column-decoders, row-decoders and unique layout techniques that output a plurality of metalline buses running vertically or horizontally, connecting to the selected wordline in units of bytes in Toshiba's 3Tr-NAND or 4Tr-NAND arrays to completely eliminate Toshiba's and other's vertically divided triple well for byte-writable arrays.
Still another object of the present invention is to provide novel schemes of zero-disturb column-decoders, row-decoders and unique layout techniques that output a plurality of metalline buses running vertically or horizontally, connecting to the selected wordline in units of bytes in 1Tr-ETOX array to completely eliminate any divided triple well for byte-writable arrays.
A further object of the present invention is to provide novel schemes of split operating voltages of zero-disturb column-decoders, row-decoders and unique layout techniques that output a plurality of metalline buses running vertically or horizontally, connecting to the selected wordline in units of bytes in Toshiba's 3Tr-NAND and 4Tr-NAND arrays to completely eliminate their vertically divided triple well for byte-writable arrays. The split operating voltages of the present patent can further reduce P/E program voltages from 20V to +/−10V.
Still a further object of the present invention is the layout of the peripheral (insert) circuits right underneath of the aforesaid area occupied by a plurality of either horizontal or vertical metal buss lines generated from the novel row-decoder or column decoder of the present invention.
Yet another object of the present invention is provide a set of flow-charts that clearly explain the operations of byte-erase and byte-program based on the cell schemes of FN-channel erase and FN-channel program like a traditional 2Tr-FLOTOX EEPROM cell.
The present invention will become more fully understood from the detailed description given subsequently and the accompanying drawings, flow-charts and diagrams that are given by way of illustration only, and thus are not limited to the present invention.
The present invention is a novel combo nonvolatile semiconductor memory and embedded memory that employs several new schemes of byte-wordline decoders and unique layout techniques associated with an unified, highly-scalable BN+ S/D (Source/Drain) cell architecture with the same process for integrating FLASH, EEPROM and ROM into one monolithic chip. The present invention will be described below in detail with reference to the accompanying drawings.
In program operation, cell's drain voltage requires more than 15V with gate WL at ground level and source floating. 15V drain and channel voltage is coupled from bitline BL via the n-channel select transistor with gate SG tied to 17V and source line SL in floating state to avoid current leakage. The write schemes used in FLOTOX cell are both FN-channel erase and FN-channel program in units of bytes that achieves more than 500K P/E cycles.
Several drawbacks of FLOTOX technology include its non-scalable cell structure which requires 15V–17V in bitline during program operation. Such a high voltage requirement in bitline will drive the cell's junction breakdown higher and channel length larger, which is not suitable for technology below 0.25 um.
In addition, the overhead increase in cell array due to the requirement of divided-wordline (not shown in
In summary, traditional a 2Tr-FLOTOX cell is non-scalable and a byte-wordline has more overhead as technology advances. There is a strong need in finding a new flash-based technology to provide a new decoder scheme and a highly scalable memory cell with a requirement of lower bitline breakdown voltage to replace the expensive FLOTOX cell in higher density and fast speed EEPROM market.
The big challenge in finding an alternative low-cost, highly scalable flash technology to replace the costly non-scalable FLOTOX EEPROM is not obvious and straightforward. Firstly, the Flash-based EEPROM cell has to offer byte-write, e.g., byte-erase and byte-program without any disturbance to the remaining bytes. Secondly, it has to achieve the comparable or better P/E cycles of 500K than FLOTOX. Thirdly, it has to be highly scalable both in cell size as well as cell array overhead. Lastly, which write scheme in the past decade to use from today's varied flash technology is arguable. That explains why today's leading EEPROM technology is still using FLOTOX while FLASH has its own unique technology trend.
The recent Smart card and Smart card business evolution has reached a turning point. A high demand for a sophisticated and secure Smart card market has driven the technology for fast 32 b CPU plus 4 Mb higher density ROM and 4 Mb EEPROM. The die size of the advanced embedded Smart card has to be squeezed into a limited area of less than 25 mm2 to avoid a die crack. Therefore, a flash-based, highly scalable cell and decoder scheme to offer write in units of byte as traditional FLOTOX EEPROM cell does become urgent. Recently, a proposed flash cell technology that uses write scheme of FN-channel erase and FN-channel program has been identified to be a FLOTOX cell replacement. The numbers of transistors of a unit cell are either two or three, with different advantages and disadvantages. In our study, FN-channel erase and FN-channel program as FLOTOX's write schemes are the most critical criteria for selecting the right flash-based EEPROM cell technology. There are several important players such as Infineon and Toshiba already selecting Flash-based EEPROM based on the aforementioned schemes.
As indicated in Table 2, it shows the 2Tr-NOR, nonvolatile floating-gate cells and n-channel select transistors formed in the divided triple P-well as Toshiba's ideas. This conclusion was based on the fact that different P-well voltages of +3V and −3V have to be coupled to selected and non-selected cells respectively as shown in the above Table 2. The cells of divided triple P-wells will suffer the drawback of big P-well spacing, thus increasing the penalty of cell array size. In addition, the unselected cells suffer disturbance during repeated program and erase operations. Consequently, the endurance of program and erase cycles will be drastically reduced although Infineon claims the disturbance is minor.
In summary, this 2Tr-NOR cell of prior art has a smaller cell size than the counterparts of Toshiba or FLOTOX but still suffers from a large cell array overhead due to the requirement of divided triple P-wells and area of byte-wordline decoders.
For example, zero bitline voltage is coupled to the cell that requires program and about +5V to bitline for those cells requiring program inhibit. All cells' Vt are decreased after erase operation. The program cell's Vt will be increased and any unprogrammed cells' Vt will remain the same as the erased Vt cells without disturb. The gate (WL) of selected nonvolatile cells are coupled with −20V for FN-channel erase to expel electrons out from floating gates.
The details of the potentials of the select gates of SG1 and SG2, bitline BL, sourceline SL, and wordline WL in the above described erase, program and read operations are shown in the following Table 3. Since the cells are not formed in the triple wells, the divided well spacing is not required in the present invention. If the EEPROM cells of the present invention are made the same as the FLASH cells of the present invention, then the EEPROM cells can be formed in a large triple well without any divided well as shown in
In summary, there is no need to erase and program ROM cell electrically. The cell size of ROM is much smaller than FLASH and EEPROM because no high-voltage operation is required in the ROM application. The Boron implant can be performed after Poly2 deposition to shorten the through-put. For a combo nonvolatile memory comprised of ROM, FLASH and EEPROM, the three cell arrays are all NOR-type, thus achieving faster speed than NAND.
The previous paragraphs were focused on cell structures, cell write schemes, erase sizes, P/E cycle requirements and comparisons between prior arts and the present invention. The next paragraphs will center on the detailed description of cell arrays of all prior art and the present invention as related to EEPROM technology.
In byte-erase operation, a single byte of eight cells will be selected to perform fast FN-channel erase in 5 mS with very small current consumption. The selected byte-wordline WLK of eight cells will be coupled to around 17V and the drains and sources of eight selected cells will be held at the ground level. Assuming BYTE 0 is selected for erase, the voltages of BL0 through BL7 will be biased at ground level and WL0 is coupled to 17V. The positive high-voltage 17V on the Poly2-gate and 0V in the channel-regions of eight selected floating-gate transistors will establish a sufficient electric field, thus inducing a tunneling effect to increase the Vt of all eight cells selected by byte-wordline WL0 in BYTE0. In order to have 17V on WL0, an equivalent or higher voltage has to be applied to GWL0 with BG voltage coupled to a voltage (˜18V) one Vt higher than 17V to avoid the Vt drop due to the n-channel pass-gate.
In byte-program operation, the selected erased byte of eight cells with initial Vts at high state (˜3V) will be selected to perform FN-channel program in 5 mS with very low current consumption. In contrast to erase operation, the selected gate WL0 of eight cells will be coupled to around 0V and the drains and sources of the eight selected cells will be held at either ground level or 15V depending on the data. If the selected cells are to be programmed to low Vt, then the corresponding bitline voltages have to be coupled to 15V. If the cells' Vt is intended to remain high, then the corresponding bitline voltages have to be held at ground level without causing tunneling effect. Both channel-erase and channel-program have a low operating current of around 10 pA per cell.
During BYTE0 program and erase operations, the remaining bytes of BYTE1 to BYTE K are all held at ground level to avoid any bitline and byte-wordline disturb. If more numbers of bytes are to be selected for erase in the same wordline of WL0, then the corresponding GWLK has to be coupled to 17V as WL0 with common gate voltage BG held at 18V.
In one-page program operation, the selected BG is coupled to 18V and the rest of the BGs are held at ground level to eliminate bitline high-voltage disturb to the non-selected bytes of EEPROM cells located in different wordlines. In the array layout, the pass-transistors used to couple the high-voltage to the selected byte-wordlines are laid out with eight cells and divided bitline transistors in a very crowded, tight-pitch array area. When technology advances to small geometry, the penalty of the pass-transistors becomes a large overhead to EEPROM memory.
There are two main disadvantages of FLOTOX EEPROM. The first is the high-voltage bitline voltage of 17V required for program operation, which drives the breakdown voltage of cell's junction and punch-through voltage of cell's channel-length, making it unscalable for technology below 0.25 um. Secondly, the very high breakdown device of 18V for byte-wordline pass-gate transistor drives the cell array layout overhead drastically higher. The FLOTOX cells are not formed in the triple well but on P-substrate. The cell operating scheme uses FN-channel-erase and FN-channel program for superior P/E cycles.
In conclusion, there exists a strong and urgent market need for highly-scalable FLASH-based cell and technology to achieve comparable performance to traditional FLOTOX technology.
Aplus has pending patents of 1Tr-OR BN+ S/D FLASH cell and array, Ser. Nos. 09/852,247 and 09/891,782. Unlike Hitachi's 1Tr-AND approach, it has a 3-step scheme of FN-channel erase, FN-channel reverse program and FN-channel program, with a relaxed metal bitline pitch one half of Hitachi's counterpart. The same process and 1Tr-OR BN+ S/D cell reconfigured in series with two n-channel transistors to become a 3Tr-OR cell for byte-writable EEPROM memory is disclosed in figures of
Referring to
The byte-wordline decoders are not shown in
The wordlines of WL0 to WLm run in the x-direction without any divided byte-wordlines. In other words, the array is configured into many divided blocks. Each block contains a plurality of wordlines and sub-bitlines and sourceline of BN+ layer. The global bitline is metal1, which is used to connect the sub-blocks of the memory array like BN+ S/D 1Tr-NOR ROM. Between the respective sourcelines and bitlines, spacing has to be maintained to avoid any malfunction of program and read operations; the details of the array architecture can be referred to in Aplus' U.S. Pat. No. 5,748,538 listed above. Aside from FLASH cells, there are no additional peripheral transistors physically placed in the cell array. This array allows single-page program and read.
When the number of available metal lines is limited, the room for more outputs from byte-wordline decoders can be expanded in the x-direction to allow more vertical metal lines to connect to more byte-wordlines in the y-direction. By adding just one additional n-channel transistor with drain connecting to global vertical line of GWL, source connecting to respective byte-wordline and gate connecting to SB K, one more byte-wordline can be selected with negligible overhead. The 3Tr-OR EEPROM cells in the whole cell array are formed in the P-substrate without any triple wells in this example. The details of operation will now be described with reference to
Assuming BYTE 1 is selected for data change and four (4) metal lines are available in this process, then eight cells in BYTE1 have to be erased first. In this situation, WL2 has to be coupled with a erase voltage Verase associated eight bitlines held at ground level. Verase varies from −15V to −20V depending on the flash cell structure and coupling ratio between Poly2 and Poly1. In order to have Verase on WL1, GWL has to be coupled with Verase and SB1 coupled with Verase+Vt. The rest of signals of SB0, SB2 to SBK are grounded to float the byte-wordlines of WL1, WL3 to WLK. In addition, SG21 and SG22, the rest of signals of SG11, SG12, SG31, - - - , SGK1 and SGK2 have to be coupled to ground to shut the non-select n-channel transistors off from causing any bitline current leakages. For byte-program, two different voltages, 0V and Vinhibit, are required in eight bitlines of BL0 to BL7. 0V on bitline is to program, while Vinhibit on the bitline is to inhibit programming. The Vinhibit voltage is around 5 volts. The cells' drains of 0V are cells that are selected to be programmed to high Vt of more than 4V typically. The cells' drains of Vinhibit are cells selected not to be programmed and Vts stay as low as 1V. In order to have Vinhibit for program inhibit, the gate voltage of SG11 has to be coupled with more than Vinhibit +Vt which is at least 6V. Since a total of four metallines are available, three metallines can be used to connect the byte-decoder outputs to the respective byte-wordlines.
Typically, metal1 (M1) is reserved for bitline connections running vertically from the bitline column decoders at the bottom of the array to the selected cells in the y-direction (not shown in this figure). Since four metal lines of M1, M2, M3 and M4 are available in this example, another three metal lines not used for bitline connections can now be used for byte-wordline connections. In an eight bitline pitch area, total metal lines of twenty-four of M2, M3 and M4 can run down the array for byte-wordline connections. In this case, a total of 24 byte-wordlines can be connected successfully by twenty-four metal lines generated from top byte-wordline decoders. The twenty-four wordlines are eight M2 lines, eight M3 lines and eight M4 lines taking the room of a byte-wide pitch with the assumption all metal layers having same layout pitch.
Furthermore, if the global metal line of GWL is M4 (top metal layer), then another three metal lines of M3, M2, and M1 can use this area to connect to three additional byte-wordlines. Therefore, in total, (nine (9) M1 pitch for one line of GWL and eight lines of BL0 to BL7), twenty-seven (27) byte-wordlines can be connected by four metals (M2,M3 and M4) technology.
The following Table 4 lists the outcomes of the connection of the number of byte-wordlines and number of metal lines in a nine-bitline pitch of 3Tr-OR array. The major difference between the two equations of 9�(N−1) and (N−1)+8N is with and without the layouts of the EEPROM cell below the connecting metal lines.
From market surveys, the number of metal lines available in embedded NVM system is greater than four. For example, there are a total of six metal lines available from TSMC's embedded Flash technology. The increase is metal line cost is preferable than having a layout with large overhead waste for triple-well spacing as proposed in Toshiba's approach of 3Tr-NAND or 4Tr-NAND.
The other advantage of the present invention is the layout of connecting peripheral devices by metal1 only. By placing the aforementioned metal lines below, more area is saved. The figures of
The size of each byte-wordline decoder will be proportionally increased when the required number of outputs is increased. More metal layers available will increase the number of outputs with big savings in the array area as density increases. In one cell's height of three wordlines' pitch, all different layers of metal lines of different outputs generated from each byte-decoder can be stacked together in 3rd dimension, e.g. z-direction, and then connected to WL0, WL1, - - - and WL K, the respective byte-wordline in x-direction of cell array. When the number of available metal lines is limited, additional byte-wordline decoders have to be inserted in the cell array to allow metal layers to reach far-end byte-wordlines in the x-direction. This will increase the array area.
The height of each 3Tr-OR cell has a dimension of three wordline pitch. Therefore, this embodiment is less powerful in terms of metal connections as compared with the scheme of eight-bitline pitch as disclosed in
Now, the details of cell operation are described here with reference to
In program operation, the voltage of WL K will be at +20V and the bitlines' voltages are held at 5V or 0V depending on the data pattern. For those cells requiring high-Vt (>4V), 0V bitline is applied. On the contrary, for those cells requiring low Vt, the program inhibit voltages have to be applied selectively. The erase and program operations are performed by using the schemes of FN-channel erase and FN-channel program within 5 mS. In this example, all EEPROM cells are formed on P-substrate or in one large Triple-well. No divided triple wells are required. The following Table 6 and Table 7 show the details of the aforementioned operating voltages of each node in program and erase operations when EEPROM cells are formed in one large triple well.
The erase voltage of −20V is just an example. The required erase voltage of byte-wordline with respect to P-Well or P-substrate is subject to the thickness of inter-poly oxide, the thickness of tunneling oxide and the coupling ration from Poly2 to Poly1 floating-gate. The FN-channel tunneling effect will be induced when the applied electric field between Poly1 and P-well exceeds 10 MV/cm. The erase operation is to remove electrons from the floating-gate thus decreasing the cell's Vt. In contrast, the FN-channel program operation is to inject electrons from channel region back to floating-gate to increase the cell's Vt by applying +20V on Poly 2 gate and holding the cell's channel region at ground of the selected byte-wordline.
Traditionally, a 1Tr-ETOX flash array (Intel) only allows either FN-edge erase or FN-channel program in a block size of 64 KB. After erase operation, the cells' Vt in the selected block will be decreased to below 1.5V. The current for FN-edge erase is about 10 nA per flash cell, while FN-channel erase consumes less than edge-erase at about 10 pA per cell. During CHE program, around +5V is applied to the drains and about +10V to the gates (wordline) of the selected cells. Typically, the number of selected cells for CHE program is eight. Because a high-current pump is very noisy and area consuming, it is not recommended to have a simultaneous program of greater than eight bits. The eight selected program cells are not physically adjacent but actually dispersed in a long selected wordline. For FN-edge erase, the cells' gates of selected block are applied with about −10V and the cells' deep-source node is held at +5V. After 300 mS erase operation, the cells' Vt will typically be decreased to below 1.5V. The following Table 8 shows the traditional ETOX cell's program and erase operation. Dispersed 8 means the eight program cells are dispersed in a single wordline, making the cell suitable for byte-erase and byte-program without disturbance.
In contrast to the conventional block-erase 1Tr-ETOX array,
With reference to
Assuming WL0 is selected for byte-erase, then a negative high-voltage of −15V has to be coupled to WL0. The P-well of byte-wordline decoders on top of the array has to be biased at ground level with SB0 at 0V and GWL at −15V. The rest of WL1 to WLk has to coupled to ground with SB1 to SBK at −15V. Each byte-wordline requires a n-channel pull-down device to discharge them to ground. This n-channel device has to be formed in the same triple well on top and is not shown over here for simple drawing. As a consequence, only the selected byte-wordline, WL0, is erased and the rest of the byte-wordlines are not disturbed in the erase operation in units of bytes. For programming eight consolidated bits by CHE, the selected byte-wordline is coupled to +10V. The rest of byte-wordlines of WL1 to WLK are held to ground without causing any bitline leakage. The bitlines of MBL0 to MBL7 are either coupled to 5V or ground for programming or program-inhibit respectively. Since only one single byte-wordline gets erased each time, there is no over-erase issue in this 1Tr-OR EEPROM array of the present invention. Because the CHE program for EEPROM cells and FLASH cells are the same, the details are not further explained here for concise description.
In conclusion, the large FLASH cells' Vts for conventional code market can be very effectively controlled in a very tight distribution for both programmed cells and erased cells in a units of big block by using "3-step write" schemes as proposed in Aplus' pending patent with outcomes predicted in figures of
The operation of
Now, the detailed Write flow will be described here with reference to
In the flow path that requires a erase-verify, then an iterative series short pulses of erase and verify are performed. The number of short pulses required depends on the allowed erase and program time. The pulse voltage is preferred to be increased from initial voltage and then increased by step of 0.5V, instead of applying a high negative voltage of −20V in the beginning. For better P/E quality for better endurance cycles, more pulses are better. Due to built-in page buffers and circuits of byte-flags, the data can be flexibly erased in units of bytes, e.g., single byte, multiple bytes and a page that contains 128 B or 256 B. The specification of erase time for single byte, multiple bytes or a page is the same around 5 mS in conventional EEPROM. The width of erase pulse can be set 1 mS or 100 uS depending on a cell's characteristics. For 1 mS pulse width, a total of 5 pulses can be applied for tight-Vt erase below 1V or 0V depending on which Vt scheme is employed. After the completion of each successful erase pulse, an erase verify is performed by reading out and verifying the data via on-chip sense amplifiers. If the cells' Vts of erased bytes cannot meet the Vt requirement, then the additional erase pulses have to be continuously applied one by one for further erase. Erase will only stop when the erased Vt meeting the pre-determined specification.
In the flow path that does not require an erase-verify, then a single long pulse of erase and a single verify is performed. The allowed single pulse of erase and program is around 5 mS time. Similar to the non-erase-verify case and thanks to the built-in page buffers and circuits of byte-flags, the data can be flexibly erased in units of bytes, e.g., single byte, multiple bytes and a page that contains 128 B or 256 B. The specification of erase time for single byte, multiple bytes or a page is the same around 5 mS in EEPROM of the present invention. After the completion of each successful erase pulse, an erase verify is skipped on those erase bytes. If the cells' Vts of erased bytes cannot meet the Vt requirement, then the part becomes junk. Erase will only stop when the allowed erased of 5 mS is expired. Regardless of decision of erase or not, only those cells all pass the erase Vt specification will then be continued to perform the program and program verify operations as indicated in
Similarly, the preferred flow of a detailed program operation of the present invention is proposed in
In conclusion, the cells following the write flows of
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
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In just a few weeks, the entire gang is returning to East Great Falls, Michigan for American Reunion. That can only mean one thing — Stifler's mom will be on the hunt. In honor of cinema's most esteemed MILF, we've decided to take a look at some of Hollywood's real-life MILFs. We would scream at their framed portraits all night long.
Elizabeth Hurley has been a screen hottie ever since she bet on black in Passenger 57. Since that debut she has gone on to become a successful actress, model, entrepreneur, and mother of one. She also claims to have not watched television since 1979. That explains why she agreed to appear on Gossip Girl.
A mother of two in real life, Mary Louise Parker is best known for her role on Showtime's Weeds where she deals pot and gets naked. Perhaps she's a method actress? Dear Lord, it would be phenomenal if she were a method actress.
This mother of four is recently single and likely to be ready to mingle. Soon she'll be looking for the perfect partner to play dress up with. If the idea of this gorgeous German model playing dress up turns you on, I should make it clear that I'm referring to her dressing up as a snake slinking through an apple, an alien, and the Hindu goddess Kali as she has done over the past few years on Halloween. If that still turns you on, ewww.
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DALLAS — A government review finds that the merger of American Airlines and US Airways would reduce competition on more than 1,600 routes traveled by more than 53 million passengers.
That's a greater loss of competition than occurred with the 2010 merger of United Airlines and Continental Airlines, an analyst for the Government Accountability Office told a U.S. Senate panel on Wednesday.
Antitrust regulators at the Justice Department are reviewing the proposed American-US Airways deal, which also faces a vote by US Airways shareholders and would need approval by the federal judge overseeing American's bankruptcy case.
American and US Airways executives have defended their merger by noting that they overlap on only 12 nonstop routes.
But the GAO also considered connecting routes — those with at least one stop. GAO analyst Gerald Dillingham told a Senate aviation subcommittee that if the merger is approved, competition would decline because there would be one less airline flying those connecting routes.
There is at least one other airline on most of those 1,665 routes, Dillingham said, including low-cost airlines on 473 of them.
US Airways Group Inc. CEO Doug Parker, who will lead the combined company if the merger is approved, told the Senate panel that the deal would be good for consumers by creating a bigger airline with service to more locations than either American or US Airways can offer on their own. It would be the world's biggest airline.
"A broader airline network is better for passengers because it gives them more choices, a wider variety of services, and more competition on more routes," Parker said. He added that it would create a more powerful competitor for United and Delta, which are much bigger than No. 3 American or No. 5 US Airways.
US Airways and American Airlines parent AMR Corp. announced the proposed merger in February and hope to complete it in August or September.
Sen. Jay Rockefeller, D-W.Va., chairman of the Senate transportation committee, said in a statement that Congress "must make sure that the advantages of a strong aviation sector benefit more than just shareholders."
Congress has no role in approving or rejecting the merger, although lawmakers can try to influence the Justice Department's decision. At Wednesday's hearing, much of the discussion revolved around the fate of Reagan National Airport near Washington, where the combined American and US Airways would operate about two-thirds of the flights although carrying only half the passengers.
The Justice Department could require the merged company to give up some takeoff and landing slots at National, but Parker warned that could prompt the new American to reduce flights between Washington and smaller cities. JetBlue Airways, Southwest Airlines and others could be interested in gaining slots at the airport.
Review: American Airlines-US Airways merger would curtail competition on 1,600 routes
DALLAS — A government review finds that the merger of American Airlines and US Airways would reduce competition on more than 1,600 routes traveled by more than 53 million passengers.
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Court Weighs Nature Of Lab Evidence
Professor Jeffrey L. Fisher is quoted in a USA Today article about the Supreme Court case Melendez-Diaz v. Massachusetts:
The Supreme Court heard arguments Monday in a case that could have great impact because of prosecutors' widespread reliance on forensic evidence. The justices appeared open to ruling that lab workers must be available for cross-examination when states introduce drug, blood or other forensic reports at trial.
"Introducing forensic laboratory reports (without live witnesses) is the modern equivalent of trial by affidavit," said Stanford University law professor Jeffrey Fisher, representing Luis Melendez-Diaz, who was convicted of cocaine trafficking. Fisher challenged a Massachusetts policy, similar to others nationwide, that allows forensic analysts to submit certificates — here, a report on the authenticity and quantity of cocaine seized — without testifying.
Fisher said the prosecution should bear the burden of putting on witnesses for its assertion of the facts. "We would vigorously oppose any attempt to shift the burden on the defense to call witnesses like that," Fisher said.


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Blue Mountain Vineyards presents live music by Dave Turner from 2-5 p.m. Sunday, June 16, as part of their Sangria Sundays.
The afternoon of music and wine tasting is a great outing for Father's Day. Snacks will be available for purchase and outside picnic food is welcome, according to Blue Mountain's website.


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Sunday, 2nd August 2015
Note to Members: Login to access the member to member discount page and to book events
Membership is for all employees within the member business
Any problems, contact us and we will assist you
West Kent Chamber of Commerce and Industry (WKCCI) is a non profit organisation representing all sectors of the West Kent community. With varied membership and expertise in all business areas the Chamber attracts employers of all sizes.
Since the foundation of the Chamber as the Tradesmen's Association in 1858, it has been actively engaged in local business activities, connecting and educating members, and providing a forum for addressing the needs of the West Kent business community.
The mission of the West Kent Chamber of Commerce & Industry (WKCCI) is to make West Kent a better place in which to live, work, do business, visit and to study. WKCCI carries out its mission by providing indispensable services to its members.
Every business needs to link with the local community to provide services, clients and employees. WKCCI links its members with the people, products, and services necessary to succeed.


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Noscendi Nilum Cupido: Imagining Egypt from Lucan to Philostratus
Walter de Gruyter, Dec 6, 2012 - History - 390 pages
What significations did Egypt have for the Romans a century after Actium and afterwards? How did Greek imperial authors respond to the Roman fascination with the Nile? This book explores Egypt's aftermath beyond the hostility of Augustan rhetoric, and Greek and Roman topoi of Egyptian "barbarism". Set against history and material culture, Julio-Claudian, Flavian, Antonine, and Severan authors reveal a multivalent Egypt that defines Rome's increasingly diffuse identity while remaining a tantalizing tertium quid between Roman Selfhood and foreign Otherness.
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BMW 535i GT: New Single Turbo VALVETRONIC N55 Engine
New single turbo with twin-scrolls extends the torque band with 400 Nm of peak torque reached at 1,200 rpm
Here's a detail of the new BMW 535i Gran Turismo that deserves to be duly noted.
The 535i GT features BMW's new TwinPower Turbo with High Precision Injection and VALVETRONIC technology, a single turbo with twin-scrolls that puts the squeeze on the 3.0 liter straight-six gasoline engine, internally referred to as the N55 over at BMW.
This engine, as opposed to the twin turbochargers of the N54 version, is a first for BMW, coupling that single twin-scroll turbo with High Precision Injection and the variable valve management of the VALVETRONIC system. The 4.4 liter V8 that goes into the 550i GT still gets a twin-turbo but that 4.4 liter may be getting this new tech-upgrading for the upcoming X5M/X6M versions.
Distinguishing the N55's performance from its predecessor includes a broadening of the torque band, the 400 Nm now peaking pretty early at 1,200 rpms, and extending all the way to 5,000 rpms. The N55 also has a map-controlled oil pump which helps conserve energy, a first for a turbocharged engine, and the improved engine management gives it a better fuel economy and CO2 emission rating than the N54.
Naturally, speculation goes to the obvious next step, that BMW will introduce VALVETRONIC and High Precision (Direct)-Injection on a twin-turbo version of this 3.0 liter straight-six and dial the horsepower up to 360.
Sounds good.
World debut: TwinPower Turbo, High Precision Injection and VALVETRONIC in a new straight-six gasoline engine.
The history of BMW's modern turbo engines going back to the year 2006 is characterised by spectacular power and exemplary efficiency. And now BMW is opening up a new chapter in this history, the straight-six gasoline engine powering the BMW 535i Gran Turismo consistently continuing the process of optimising engine power while at the same time reducing both fuel consumption and CO2 emissions on an engine of this calibre.
The 3.0-litre power unit, for example, is yet a further result of the BMW EfficientDynamics development strategy, offering a range of highlights in technology never seen before on any other engine - highlights created in the context of BMW EfficientDynamics and now ideally matched for optimum driving dynamics and economy all in one.
The new straight-six is the world's first engine to combine turbocharging, direct gasoline injection and fully variable VALVETRONIC valve management developed by BMW. The turbocharging process follows the twin-scroll principle already applied successfully by the BMW Group and now further enhanced consistently for use in a particularly powerful and sporting straight-six.
The combination of this turbocharger technology with High Precision Injection and VALVETRONIC exclusive to BMW exceeds even the response and efficiency of the BMW Twin Turbo power unit launched back in 2006.
Response even better than before, fuel consumption even lower.
VALVETRONIC has already proven its qualities in numerous BMW engines the world over as a particularly effective technology providing even greater efficiency. The big advantage of VALVETRONIC is the infinite control and adjustment of valve stroke on the intake valves, making the throttle butterfly used in former times superfluous. VALVETRONIC reduces throttle losses in the charge cycle process to an absolute minimum and optimises engine response since the air mass required to control the combustion process is masterminded in the engine itself and not outside the power unit with the usual "dead" volume. This ensures particularly efficient use of the energy contained in the fuel, developing a very muscular torque curve and giving the engine optimum response.
In particular, the better response of a VALVETRONIC engine results from the fact that underpressure under part load is only approximately 50 millibar, while on a conventional engine up to 800 millibar of underpressure has to be set off.
On the BMW 535i Gran Turismo the VALVETRONIC functions have been optimised again by a new adjuster complete with a fully integrated sensor serving above all to make the adjustment process even faster than before. Indeed, the inertia factor on the new adjuster is only one-tenth the figure on the former model, serving to further improve engine response.
Responding smoothly, directly and immediately to the gas pedal, the new straight-six is clearly the leader in its class also in this discipline. Maximum torque of 400 Newton-metres/295 lb-ft, for example, comes at just 1,200 rpm.
Apart from the optimised VALVETRONIC control unit, the newly developed turbocharger also contributes to this superiority, ensuring a particularly spontaneous build-up of power since the ducts of three cylinders at a time are separated from one another both in the exhaust manifold and the turbocharger.
In practice, this means particularly low exhaust gas counter-pressure at low engine speeds, the double ducts then enabling the flow of gas to build up greater dynamism in the exhaust manifold and powerfully drive the turbocharger blades even at low engine speeds. Twin-scroll technology thus combines the benefits of two turbochargers within one system. And now this principle adapted to the BMW straight-six with its high standard of technology marks the ongoing, consistent development of BMW's turbocharged engines.
High Precision Injection with new injector nozzles.
The VALVETRONIC system is fully integrated in the cylinder head. This intelligent and extremely compact arrangement allows a direct combination with High Precision Injection with its injection nozzles placed in the middle between the valves and, therefore, in the immediate vicinity of the spark plug in the cylinder head.
High Precision Injection in the new six-cylinder delivers fuel through innovative multi-hole valves at an injection pressure increased once again in large areas all the way to 200 bar. This ensures extremely precise dosage of the fuel injected as well as a particularly clean combustion process. And last but not least in this context, the direct injection of fuel serves to cool the fuel/air mixture and increase the compression ratio to a higher level than in a turbocharged engine with manifold injection - an advantage contributing once again to the greater power of the straight-six.
Displacing 2,979 cc, the new power unit delivers maximum output of 225 kW/306 hp. It therefore offers all the torque and muscle of a significantly larger eight-cylinder, but comes with much lower weight and significantly lower fuel consumption and emissions. It is indeed far lighter than a comparably powerful eight-cylinder and remains even 4 kilos lighter than the straight-six turbocharged engine already well-established in the market.
The BMW 535i Gran Turismo accelerates from a standstill to 100 km/h in 6.3 seconds and reaches an electronically limited top speed of 250 km/h or 155 mph. The unusually good balance of performance and fuel consumption is clearly expressed by average fuel consumption in the combined EU cycle of just 8.9 litres/100 kilometres, equal to 31.7 mpg imp. And the CO2 rating of the BMW 535i Gran Turismo is just 209 grams per kilometre.
The BMW 535i Gran Turismo, like the other two model variants, comes as standard with a wide range of BMW EfficientDynamics technology. Supplementing the excellent efficiency of the respective engine and the eight-speed automatic transmission, features such as Brake Energy Regeneration, on-demand management and operation of ancillary units including the electrical coolant pump, the electrical power assistance pump and the detachable a/c compressor, as well as consistent lightweight engineering, optimised aerodynamics including active management of air flaps, and tyres with reduced roll resistance, ensure optimum fuel economy and emission management at all times.
The power unit of the BMW 535i Gran Turismo is the first turbocharged engine to feature a map-controlled oil pump which, taking up less energy, makes a further contribution to motoring efficiency. Yet a further point is that the new straight-six power unit with turbocharger, High Precision Injection and VALVETRONIC, does not require sulphur-free fuel and may therefore be used without problems the world over. The final point is that the engine naturally fulfils both the EU5 emission standard in Europe and the ULEV II standard in the USA.


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About three weeks ago the Russians were accused of dispatching two large landing ships full of marines to Tartus. As it turned out, that was a false alarm: one of the ships at the center of the media firestorm never left port and the other carried out a normal training mission in the Black Sea before quietly returning to base a few days later. After a few days of hemming and hawing, and after a number of high profile conservatives angrily berated Barack Obama over the non-event, everyone calmed down and things went back to normal.
I was extremely skeptical about the entire matter not because of the moral uprightness of the Russian government, despite its embrace of a position which trumpets "sovereignty" it's pretty clearly not above meddling in the internal affairs of other countries, but because of the story's reliance on a single unnamed source, because escalating the conflict is clearly not in Russia's national interest, and because intervention in Syria would be flatly contrary to all of Russia's previous diplomatic activity.
Now comes a situation that is more confusing and bizarre by several orders of magnitude. Russia has recently been pivoting in an anti-Assad direction, saying that it would suspend arms sales and holding talks with the Syrian National Council. Although the arms sale suspension hasn't yet been confirmed, if true it would be a pretty dramatic change for a government that has loudly and persistently insisted that its arms sales are nothing to apologize for.
Yet almost at the same time that Russia was making these concessions, a number of media reports have emerged that indicate that Russia is sending a sizable a flotilla of ships drawn from the Baltic, Northern, and Black Sea fleets to Syria. Since these media reports all seem to be based off of an Interfax report that quotes a single nameless "military-diplomatic" source, and since Interfax screwed up the last story on Russian naval deployment to Syria pretty badly, a little bit of caution would seem to be in order. I would like to see confirmation (from the Russians, from a media outlet, from the US government, from someone) that these ships are, in fact, heading for Syria before I put on my outrage hat.
However, assuming that the Russians actually are dispatching naval forces to Syria, what are they sending? Different reports give differing numbers, but from what I can gather the following ships are involved: the destroyer Admiral Chabanenko, the frigates Yaroslav Mudry and Smetlivy, and three large landing craft carrying a contingent of marines. It is worth noting that the landing craft in question, while they have not been named in any of the reporting, are very clearly not the landing craft from the Black Sea fleet that were at the center of the controversy in late June but totally different ships from the Northern Fleet.
By American standards this task force is not at all impressive. By the greatly diminished standards of Russian naval operations, however, this is actually a pretty significant force. Two of the ships in question, the Admiral Chabanenko and the Yaroslav Mudry, are two of the newer and most capable members of the Russian fleet, coming into service in 1999 and 2009 respectively. The Smetlivy, on the other hand, is absolutely ancient having first entered service all the way back in 1969 (frankly speaking, it's a miracle the thing is still afloat).
What makes the entire situation even more bizarre is that most of the ships involved (the Admiral Chabanenko and the three landing craft) will take several months to reach Syria since they are leaving from Severomorsk. These ships will thus have to take an extremely lengthy and circuitous route even to get into the Mediterranean, let along to get all the way to Syria. Given the rapidity with which the situation in Syria is changing, and the increasing fragility of Assad's regime, it's likely that by the time the Russian ships arrive in Tartus Assad will already have been deposed. If Russia was genuinely interested in providing some kind of naval assistance to its Syrian ally, or in conducting some sort of an evacuation, using ships from the Northern Fleet makes absolutely no sense: Russia has ships in the Black Sea that are much closer and that could be on station in a matter of days. Part of what gave the story in late June credibility was the fact that the ships in question were both based in the Black Sea and, if needed, could be in Syria in less than a week.
So what's actually going on? Well (with the stipulation that I personally find the dispatch of any Russian military forces near Syria to be imbecilic and unjustified) it would seem clear that the Russian ships don't have any sort of urgent and time-sensitive mission since most of them are not going to arrive until some time in late September or early October. And since none of the warships ships in question are designed for supporting land operations, they're small anti-submarine and anti-ship frigates and destroyers, it seems hard to see how they could play any sort of military role in Syria's increasingly bloody civil war even if that was their goal.*
What I would guess is going on is a typically Russian, and typically clumsy, attempt to show the flag and to demonstrate to the West, and to everyone else with interests in Syria, "we're here, we matter, and you need to take our opinion into account." I would have recommended they put out a press release, as it would save on time, money, and effort, but then they didn't exactly ask for my opinion. Since Russia recently took a number of steps that will be reasonably interpreted as being anti-Assad, I also think it's likely that the Russian defense establishment (which has very close connections with the Syrian military) wanted to ensure that Russia wasn't seen as overly weak and conciliatory. So while this story will no doubt be yet another in a long line of Russian PR disasters, the actual real world impact will be so muted as to be unnoticeable. While Russia can play a blocking role and prevent Western countries from getting UN approval for a military intervention, it's ability to influence the reality on the ground in Syria is essentially nonexistent. Sending a flotilla of aging transport ships and a few destroyers to Tartus isn't going to change that.
* The landing craft, it's true, are carrying a contingent of marines, but what possible impact could 1,000 troops have on a large scale civil war? The Russians aren't always the most clear-headed people in the world, but committing 1,000 troops without air cover in an environment like Syria is level of stupidity and recklessness that verges on the suicidal


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Hang tight!
Recipe by Jennifer Hanson
"This quick and easy dish even gets picky kids to try broccoli!"
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2 (14 ounce) bags
frozen broccoli florets
1 cup
melted butter, divided
1 teaspoon
seasoned salt
2 cups
What a way to put silk stockings and high heels on broccoli! The croutons (I pulsed them in the food processor to rough crumbs) add great flavor and the broccoli (I used fresh and blanched it for just a couple of minutes) stayed a vibrant green. Since my croutons already had sufficient butter in them I didn't add the second drizzle of butter the recipe called for. Rich and flavorful, this dressed up broccoli is worth the extra preparation it requires.
Not sure what I did wrong but this was just blah.
10 Ratings
Great way to takes plain 'ol broccoli to a whole new level! I used a steam in bag of broccoli and cut the amount of butter in half. Next time I might add a little grated Parmesan cheese or shredded cheddar, but honestly this was great as is and perfect for a last minute side dish!
I used fresh broccoli, blanched it for about 3 minutes and proceeded from there. I couldn't see drowning this healthy vegetable in all that butter so I just dotted the spears with it. Since the recipe name is broccoli with buttery crumbs, that is what I used. I seasoned my homemade crumbs with garlic powder and some grated provolone, sprinkled that over and dotted that with butter. Then baked as directed. This was delicious, the broccoli was tender crisp and we will be having this again. Thanks, Jen
I made this even easier by using a frozen steamable bag of broccoli (I knocked a minute off the microwaving time to ensure a bit of bite). I also couldn't make myself use 1/2C butter (I halved the recipe), so I used a bit less than 1/4C and it was plenty. I may try to use even less next time just to save some calories. We only had seasoned croutons and they added some nice flavor. I used GOYA Adobo Seasoning for the seasoned salt. THANKS for the recipe!
This was really good. I just made enough for myself in a very small baking dish. I used frozen broccoli florets that I microwaved first for a few minutes. I also crushed the herbed croutons a bit so they would be more crumb-like and not chunks, topped with a bit of parmesan cheese and garlic powder and baked it for 12 minutes. I'm sure using buttery round crackers in place of the croutons would work just as well. Like a veggie comfort food!
* Percent Daily Values are based on a 2,000 calorie diet.
Broccoli with Buttery Crumbs
Serving Size: 1/8 of a recipe
Servings Per Recipe: 8
Amount Per Serving
Calories: 260
Calories from Fat: 214
Hard to believe, but many kids will be back in school at the end of the month. Get ready.
You won't believe all the things you can do with cauliflower. It's a great low-carb option.
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See how to make a simple broccoli side dish with garlic and cashews.
Watch Chef John make an easy, healthy broccoli side dish.
See how to make a classic, creamy and cheesy broccoli casserole.


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This is a Sponsored post written by me on behalf of Quaker Oats for SocialSpark. All opinions are 100% mine. With Summer coming on full speed ahead, and The Boy playing T-ball for the next month, Hubby and I are quickly reminded of how much we have let go of ourselves and gives us the […]
Nutritious "Cheat Treat" with @Quaker Soft Baked Bars
June 6, 2012 By
A World without Malnutrition – Future Fortified Campaign through GAIN
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NORTHRIDGE, Calif. --- The Cal State Northridge women's soccer program recently held its annual alumni reunion at Matador Soccer Field, bringing together a host of current and former Matador talent. Over 35 former players joined the current squad for a friendly contest and also enjoyed some time to catch up on life outside the pitch.
"It was great to see such a great group come back and interact with the current team," head coach Keith West said. "This upcoming season will be my seventh and it's remarkable to see how some of these young women have grown and developed into professionals in an array of fields."
Among those in attendance:
Nalena Betancourt*
Rachel Gillis
Lelah Pate*
Rebecca Hidalgo
Shannon Esparanza-Devos*
Leah Elliot
Casey Dodd
Tryna Tafoya*
Farryn Townley*
Susie Mischenko*
Kelley Ross
Sonia Espitia*
Jasmine Pratt
Kristy Krohn*
Erin Kelly
TinaMarie Lutizetti
* Denotes All-Big West honoree
The current squad of Matadors, those preparing for the 2012 fall varsity season, includes 2011 Big West Goalkeeper of the Year Cynthia Jacobo and All-Big West Second Team selections Melissa Fernandez and Katie Russ.
Jacobo became just the third Matador in school history to receive a player of the year award after being named Goalkeeper of the Year in 2011. The junior from Arleta, Calif., started 18 matches in net in 2011, posting a 1.47 goals-against-average, 60 saves and a .698 save percentage.
She added four shutouts during the year and appeared to save her best performances for conference competition. This year she was 4-3-1 with a 1.41 GAA, 32 saves and a .744 save percentage. For her career, Jacobo is 14-6-1 (.690) with 12 shutouts against league opposition in the regular season.
A formidable force on defense, Russ earned Second Team honors for the first time in her career. She had a goal and an assist while appearing in 18 matches. She scored her second career goal in the Matador's first-ever victory at LMU and assisted on Farran's game-winning goal against Long Beach State.
Fernandez finished the 2011 season with a career-high four goals and 12 points. She added four assists to raise her career total to 10, tying her for the fifth-most in school history. Fernandez also led the squad with 53 shots on the year, the third-most in school history for a single season.
"We have a great schedule planned for 2012 and I think our fans and this school should be excited for another great season of Northridge soccer," West said.


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July 30, 2015
Beginning Monday, August 6, 2012, the signal crew for TxDOT's Bryan District will upgrade the traffic signal at the intersections of US 79 and Hackberry and US 79 and Brazos in Hearne, Texas. They will be upgrading and replacing the cabinet and controllers for these signals.
Motorists who travel through this intersection should expect to encounter workers. While this work is completed, motorist should treat these intersections as four-way-stops while the traffic lights are off. Portable stop signs will be in place while work is done on the signals.
The cost to upgrade each signal is approximately $4,000.00 Tout hopes to have both signals done on Monday but if time does not allow they will finish this on Tuesday. Tout appreciates everyone's patience during this signal upgrade.
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Bizarre Mussels
My dad gave me a two-pound bag of frozen mussels he purchased at Walmart for three bucks. I have no idea what to do with them seeing as how they're not fresh: they're frozen, pre-cooked, and in their shell. Am I the only one that thinks this is bizarre?
I've never been one to waste food and I'd like to try them, I'm just worried about over heating them and making them rubbery because- as I said- they're already cooked. Pasta applications with white wine, butter, and tons of garlic came to mind, but I don't know if that will work with these.
Any ideas?
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2:58 pm
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Malls On The Decline Find New Ways To Stay Relevant
By editor
Originally published on Fri August 15, 2014 7:14 pm
Shopping malls are a part of American culture — people go to malls to socialize, eat and, of course, buy. But as purchases are increasingly just a click away online, malls have been losing money.
NPR's Sonari Glinton has been reporting a series on shopping malls across America, and he joins Here & Now's Robin Young to discuss why some malls are doing better than others, and the creative new ideas that some malls are adopting to attract customers.
- Sonari Glinton, NPR business reporter. He tweets @Sonari.
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Avuá Cachaça: New Craft Distilled Cachaça Hits the USA
You may know cachaça as the base of the Caipirinha, that effortlessly thirst-quenching Brazilian answer to the gin and tonic. But the distilled sugar cane spirit, frequently lumped in with rum, is beginning to come into own. We're excited to share the most interesting bottles that have crossed our desk in a while. More