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A Visit with Wounded Warriors in San Antonio, Texas
Joining Forces is a national initiative that mobilizes all sectors of society to give our service members and their families the opportunities and support they have earned. Get involved at JoiningForces.gov.
Continuing the Joining Forces kick off tour this week, the First Lady and Dr. Biden visited several wounded warriors and their families at Brooke Army Medical Center in San Antonio, Texas -- one of the nation's premier medical centers serving our troops and their families. "I think we leave here more inspired, because of the resilience and strength we see in our Wounded Warriors and their families," Dr. Biden said after meeting with soldiers and their families.
They personified both the sacrifice of war on those who fight them on our behalf and their families as well as the extraordinary strength of America's military families. Some wounded warriors will return to the front lines and military service. Others may not, but still have a lifetime of skills, strength, and commitment to service to contribute to our country. From ensuring they have the care, support and services they need to expanding opportunities for meaningful careers and active roles in our communities, all segments of our society can work together to express our debt of gratitude to the military families who serve and protect us by supporting and engaging them.
Trooper Sanders is deputy director of policy to the First Lady
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Best Italian Restaurant (Not Cheap) St. Louis 2003 - Giovanni's on the Hill
5201 Shaw Ave.
St. Louis, MO 63110
Readers' Choice: Tony's
Giovanni Gabriele's restaurant is one of those places you go to when you're in the mood to dress up and splurge. Once the valet whisks your car away, the doorman will point to the beautiful dining room where the host will greet you and lead you to your table. Your path is lit by the soft glow of antique chandeliers; the table is set with crystal stemware and hand-painted china. Tuxedoed waiters see to your every need. Like all restaurants of this caliber, what is served on your china starts out as the freshest raw materials available that day: fish is flown in daily; the veal is milk-fed, prime grade; the carpaccio's raw beef melts in your mouth; the desserts are house-made. You may be tempted to dismiss the pasta dishes, but that would be a mistake. The farfalle with cream sauce and salmon is a signature dish. Tagliatelle with mussels is superb, with a reduction of mussel broth, garlic, tomato, red pepper and rich olive oil. Risottos include lobster, truffle and mushroom and are prepared the way risotto ought to be: beginning with high-quality Arborio rice sautéed in butter, then slowly cooked by adding a stock, ladle by ladle, until the liquid is absorbed. No shortcuts here. It makes all that dressing up worth the effort.

subset: commoncrawl


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A science blog with Eric Berger
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Faster-than-light neutrino observation far from confirmed
Yesterday it became widely known that scientists in Italy believe they have observed faster-than-light neutrinos, a discovery which would force a rewrite of our modern conception of physics. But there remains deep skepticism about this. Since then the paper with the relevant results has emerged online, and there will be a technical conference about it […] [Read More]


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The Miss America Pageant (beauty contest, hosted by Bert Parks)
(ABC Weekend Special, 1954 - 1965; NBC Weekend Special, 1966 - 1996; ABC Weekend Special, 1997 - 2004) [Although this pageant was not a weekly series, it appeared regularly enough during the 1950s and 1960s to be a part of the cultural landscape; Along with boxing and roller derby and other "spectator sports", "Miss America" became another reason to justify the cost of buying a TV set; It had begun as a promotional event at Atlantic City, New Jersey way back in the "Roaring Twenties" -- 1921 to be exact; It had been an attempt by Atlantic City merchants to keep tourists from leaving that seaside resort after the traditional Labor Day end of summer; It is sometimes described as "the oldest beauty contest in the U.S.", although there were quite a few in that era. Subsequently, pageant organizers stressed that it was more than just "beauty"; the contestants were judged on "talent" too -- and served as "role models." Whatever, the first televised contest aired on September 11th, 1954 when Lee Meriwether was crowned Miss America for 1955. After the first 10 years on ABC, it lasted for 30 years on NBC, but switched back to ABC. After 2002, pageant organizers began to have trouble convincing ABC it was worth keeping on the air. Some notable personalities made their debut on the national stage via the "Miss America" pageant after appearing on it, including TV hostess Bess Myerson (winner 1945), actress Lee Meriwether (winner 1955), actress Susan Anton (contestant 1969), TV host Phyllis George (winner 1971.) The pageant switched networks in 1966 to take advantage of "Living Color" on NBC and that was the first year it was broadcast in color; Amid controversy, aging M.C. Bert Parks was replaced in 1980 by TV Tarzan actor Ron Ely; then in 1982, actor & TV host Gary Collins became the official pageant M.C.; In 1992, Regis Philbin and Kathy Lee Gifford co-hosted the show replacing Collins; Bert Parks passed away in 1992, some 10 years after he was replaced as M.C. After 83 years, the TV pageant itself became a victim of the times; It found no major broadcast network willing to air it, after ABC announced it was dropping the show for low ratings, following the 2004 broadcast. Finally, in 2005, after cruel tabloid headlines proclaimed "Miss America Can't Get a Date" and "There She Goes...Miss America", the Country Music cable TV network agreed to air it -- but only after organizers agreed to move it to January (perhaps so it wouldn't get in the way of the Fall TV season "ratings sweeps" period.) Also, talk was, it may move away from Atlantic City (perhaps to the Country Music capital of Nashville for its first cable broadcast in 2006.)]


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An instrument for positioning a cardiac valve prosthesis in a vessel includes a wire element to slidingly guide the valve prosthesis towards an implantation site and an expandable element coupled to the wire element. The expandable element is expandable in the vessel to position the wire element in association with the implantation site. A method for positioning a cardiac valve prosthesis includes securing a delivery instrument at an appropriate location at the implantation site and delivering the valve prosthesis to the implantation site using the delivery instrument.
1. A device for use in positioning a cardiac valve prosthesis at an implantation site having an aortic valve annulus, the device comprising:
a wire element operable to facilitate advancement of the valve prosthesis; and
an expandable element coupled to the wire element, the expandable element including at least three substantially longitudinal band elements formed of a superelastic material and having a cage-shaped expanded configuration, the expanded configuration operable to axially secure the wire element with respect to the implantation site in the vessel, while not occluding blood flow through the vessel;
an abutment element configured to limit advancement of the prosthesis, the abutment element coupled to the wire element and disposed at a location proximal to the expandable element such that during use the abutment element operates to axially align the prosthesis with the aortic valve annulus; and a filter element couple to the wire element at a location distal to the abutment element, the filter element configured such that it is permeable to blood flow;
wherein the expandable element is disposed in a symmetrical fashion about the wire element, configured such that during use at least a portion of the wire element is generally positioned along a central longitudinal axis of the vessel.
2. The device of
3. The device of
4. The device of 3 wherein the expandable element is made from a superelastic, self-expanding material and has a generally cage-like configuration.
5. A device for use in positioning a cardiac valve prosthesis in a vessel, the device comprising a wire element coupled to an expandable element, wherein the expandable element includes at least three substantially longitudinal band elements formed from a superelastic material, the band elements defining an expanded configuration operable to axially secure the wire element with respect to an implantation site in the vessel, while not occluding blood flow through the vessel, the wire element further having an abutment element configured to limit advancement of the prosthesis and disposed at a location proximal to the expandable element, such that during use the abutment element operates to axially align the prosthesis at the implantation site the wire element further having a filter element coupled to the wire element at a location distal to the abutment element, the filter element configured such that it is permeable to blood flow.
6. The device of
7. The device of
8. The device of
9. The device of
10. The device of
11. The device of
12. The device of
13. The device of
This application is related to co-pending U.S. application Ser. No. 11/612,972, entitled "Device for In Situ Axial and Radial Positioning of Cardiac Valve Prostheses," U.S. application Ser. No. 11/612,980, entitled "Instrument and Method for In Situ Deployment of Cardiac Valve Prostheses," and U.S. application Ser. No. 11/612,968, entitled "Device for In Situ Positioning of Cardiac Valve Prostheses," all of which were filed on even date herewith and are hereby incorporated by reference.
The present invention relates to instruments for the in situ positioning of implantable devices. In particular, the invention relates to the in situ positioning of expandable prosthetic cardiac valves.
Recently, there has been increasing consideration given to the possibility of using, as an alternative to traditional cardiac-valve prostheses, valves designed to be implanted using minimally-invasive surgical techniques or endovascular delivery (so-called "percutaneous valves"). Implantation of a percutaneous valve (or implantation using thoracic-microsurgery techniques) is a far less invasive act than the surgical operation required for implanting traditional cardiac-valve prostheses.
These expandable prosthetic valves typically include an anchoring structure or armature, which is able to support and fix the valve prosthesis in the implantation position, and prosthetic valve elements, generally in the form of leaflets or flaps, which are stably connected to the anchoring structure and are able to regulate blood flow. One exemplary expandable prosthetic valve is disclosed in U.S. Publication 2006/0178740 A1, which is incorporated herein by reference in its entirety.
An advantage of these expandable prosthetic valves is that they enable implantation using various minimally invasive or sutureless techniques. One non-limiting exemplary application for such an expandable valve prosthesis is for aortic valve replacement. Various techniques are generally known for implanting such an aortic valve prosthesis and include percutaneous implantation (e.g., transvascular delivery through a catheter), dissection of the ascending aorta using minimally invasive thoracic access (e.g., mini-thoracotomy), and transapical delivery wherein the aortic valve annulus is accessed directly through an opening near the apex of the left ventricle. Note that the percutaneous and thoracic access approaches involve delivering the prosthesis in a direction opposing blood flow (i.e., retrograde), whereas the transapical approach involves delivering the prosthesis in the same direction as blood flow (i.e., antegrade) Similar techniques may also be applied to implant such a cardiac valve prosthesis at other locations (e.g., a pulmonary valve annulus).
For the implantation of cardiac valve prostheses, it is important to check in a precise way the positioning of the various parts of the valve prosthesis. This applies to both axial positioning, to ensure that the prosthetic valve is positioned properly with respect to the valve annulus, and angular positioning, to ensure that the prosthesis may optimally engage the Valsalva sinuses, thus ensuring that the prosthetic valve leaflets are located with respect to the valve annulus at positions essentially corresponding to the positions of the natural valve leaflets.
There is a need in the art for delivery and implantation instruments capable of delivering an expandable prosthetic valve to a precise location associated with a corresponding valve annulus. There is a further need for instruments adapted to carefully control expansion of the valve to prevent the valve from misaligning during valve expansion.
The present invention, according to one embodiment, is a device for use in positioning a cardiac valve prosthesis in a vessel. The device comprises a wire element to facilitate advancement of the valve prosthesis, the wire element including an abutment element configured to limit advancement of the prosthesis and an expandable element coupled to the wire element, the expandable element including an expanded configuration operable to axially secure the wire element with respect to an implantation site in the vessel, while not occluding blood flow through the vessel. The expandable element is disposed in a symmetrical fashion about the wire element, such that at least a portion of the wire element is generally positioned along a central longitudinal axis of the vessel.
The present invention, according to another embodiment, is a method of implanting a replacement aortic valve prosthesis at an implantation site. The method includes advancing a positioning instrument having an expandable element and a wire element through an aortic annulus to an anchoring position distal to the Valsalva sinuses, deploying the expandable element to secure the positioning instrument to the aortic wall, while not occluding blood flow through the aortic arch, advancing the aortic valve prosthesis over the wire element to a reference point coupled to the wire element, such that the prosthesis is in a desired position with respect to the aortic annulus, and expanding the aortic valve prosthesis, such that the prosthesis anchors to the aortic annulus and the Valsalva sinuses.
While multiple embodiments are disclosed, still other embodiments of the present invention will become apparent to those skilled in the art from the following detailed description, which shows and describes illustrative embodiments of the invention. As will be realized, the invention is capable of modifications in various obvious aspects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive.
While the invention is amenable to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the invention to the particular embodiments described. On the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
Without limiting the scope of the invention, the description that follows makes reference to an instrument employed for the implantation of a cardiac valve prosthesis destined to replace an aortic valve. It will be apparent that the instrument of the present invention may likewise be employed in connection with implantation of valve prostheses at different locations (e.g., pulmonary valve or mitral valve).
The prosthesis V is configured to be positioned with the annular inflow portion IF in correspondence with the aortic annulus A and the annular outflow portion OF located in the ascending line of the aorta AO, in a fluidodynamically distal position with respect to the Valsalva sinuses VS. The prosthesis V is provided with anchoring formations (not shown) that connect in a bridge-like fashion the annular end portions IF, OF. The anchoring formations are configured to extend into the Valsalva sinuses to anchor the valve prosthesis V in the implant position, thus helping to longitudinally secure the prosthesis V. By extending into the sinuses of Valsalva VS, which form a three-lobed cavity downstream the valve annulus, the anchoring formations (e.g., three formations disposed at roughly 120� angles from each other over about the circumference of the prosthesis V) also ensure the appropriate angular positioning of the valve prosthesis V, so that the prosthetic valve leaflets will be at angular positions corresponding to the angular positions of the natural valve leaflets with respect to the valve annulus.
The prosthesis V shown in
As shown in
With respect to axial positioning, once the element 12 is disposed at a given axial position along the ascending line of the aorta, and thus at a given position with respect to the aortic annulus, the expandable element 12 serves as a reference point. The prosthesis V may thus travel along the guide wire 10 to locate it at a desired axial position, before it is anchored at the desired location with respect to the valve annulus. The present invention thus allows for precise positioning of a prosthesis V, by providing a guide for advancing the prosthesis to the implantation site.
Several variations of the expandable element 12 are contemplated. In one embodiment, once expanded, the element 12 does not undesirably obstruct blood flow (represented by the arrow designated BF in
In one exemplary embodiment, the expandable element 12 is a completely "apertured" structure, namely a structure that in its expanded position is traversed by passageways through which blood can readily flow. Alternatively, the non-obstructive effect can be achieved by ensuring that the element 12 has an expansion cross-sectional radius which is smaller than the cross-sectional radius of the treated lumen. In this embodiment, general centering the guide wire 10 with respect to the implantation lumen will be accomplished by the element 12 "floating" in the blood flow and will not require the expandable element 12 to apply any radial pressure against the lumen wall. This embodiment may be helpful in at least some patients suffering from degenerative diseases, as the lumen wall may be fragile and therefore susceptible to be damaged by pressure.
In one embodiment, the guide wire 10 has a stiffness sufficient to cause its length extending from the expandable element 12 towards the valve annulus to remain approximately in the center of the body lumen throughout. A distal portion of the guide wire 10, for example, has a stiffness sufficient to hold and retain its shape.
The embodiments of
In this embodiment, the wall of the tubular element includes a plurality of slits extending in a substantially longitudinal direction defining therebetween wire-like or band-like portions of the tube wall. According to one embodiment, these longitudinal slits are formed from a microtube using a laser cutting technique. The microtube can be of the type normally used for producing angioplasty stents (e.g., a hypotube).
These band-like expandable elements 12 may be deployed, for example, by manipulating a proximal control means 13, of a known type in the catheter art, to effect a relative movement of the guide wire 10 and the sheath 11. The sheath 11 may be advanced distally towards the expandable elements 12 to reduce the distance between the distal end of the sheath 11 and the distal end of the guide wire 10, thereby deforming the tubular elements and causing the wire-like or band-like wall elements between the slits to protrude outwardly of the guide wire 10 to form a radially expanded element 12 as desired. The further that the sheath 11 is advanced towards the distal end of the guide wire, the further that the tubular elements protrude radially.
The tubular element can be comprised of any metal material approved for use in the biomedical field, such as for instance steel, and in that case the expansion to form the expanded element 12 is positively determined by sliding the sheath 11 over the guide wire 10. The tubular elements may also be formed for example of any known polymer material approved for human implantation.
The cage-like structure constituting the expandable element 12 is shown
According to one embodiment, the cage-like structure includes at least three such elements. In other embodiments, the cage-like structure includes at least five or six such elements.
According to one exemplary embodiment, as shown in
As illustrated in
The expandable element 12 is then expanded so that the marker 16, and thus the guide wire 10, substantially maintain the desired axial position. In the embodiment shown in
Positioning and securing the expandable element 12 and the guide wire 10 facilitates positioning the valve prosthesis V at the desired position with respect to the implantation site (e.g., aortic valve annulus). The results in terms of accuracy already achieved in positioning of the instrument will thus be exploited for the purpose of positioning of the valve prosthesis V.
During an implantation procedure, the valve prosthesis V is advanced longitudinally over the guide wire 10 (see
For instance, instead of a single marker 16, the guide wire 10 may include multiple markers 161, 162, etc. defining a graduated scale along the guide wire 10. The operator will thus be able to position the marker 160 on the valve prosthesis V in alignment with one particular marker in the scale, in view of specific requirements arising at the time of implantation.
In a complementary and dual manner, it is possible to provide multiple markers on the prosthetic valve V. These markers can be provided, rather than on the cardiac valve prosthesis V, on the respective deployment instrument, for instance on either or both the deployment elements 100, 200 mentioned above. Providing the markers on the prosthesis V allows the operator to check over time the positioning of the valve prosthesis V.
At this point, by realizing that the prosthesis V can no longer be advanced over the guide wire 10 because of the mechanical co-operation of deployment element 200 against the abutment element 17, the operator will know that the prosthesis V has reached the desired position. The operator can thus proceed to deploy the annular inflow and outflow portions IF, OF of the prosthesis V without having to worry about the axial (and radial) positioning of the prosthetic valve. The operator will thus be able to concentrate on other issues related to implanting the prosthesis, such as the appropriate angular positioning of the prosthesis V, by making sure that the protruding parts of the prosthesis V are angularly positioned in correspondence with the Valsalva sinuses and correctly extend into the Valsalva sinuses the prosthesis V is deployed.
A micrometric adjustment mechanism (of a type known by itself) actuatable from the proximal extremity of the instrument can be associated to the abutment element 17 for regulating in a precise way, if necessary, the position of the element 17 with respect to the guide wire 10 and/or the expandable element 12. This adjustment feature may turn out to be advantageous in certain situations where the expandable element 12 must be expanded and thus deployed in a different position with respect to the originally anticipated position. In this case, adjusting the position of the abutment element 17 makes it possible to position that element at the position where it would be disposed had the expandable element 12 been positioned in the anticipated way.
Various modifications and additions can be made to the exemplary embodiments discussed without departing from the scope of the present invention. Accordingly, the scope of the present invention is intended to embrace all such alternatives, modifications, and variations as fall within the scope of the claims, together with all equivalents thereof. This is particularly true as regards the possible combination, within a single implantation kit, of the instrument described herein with a deployment instrument described in the co-pending patent application already referred to in the foregoing.
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Arizona State Sun Devils
ASU coach: Pac-12 scheduling does Sun Devils no favors
The good news is every Pac-12 basketball game can be seen on TV (as long as you get the Pac-12 Network, of course).
The bad news, though, is that games will be on at somewhat random times on somewhat random days.
Gone are the days of Thursday/Saturday combinations, as they have been replaced by games on Tuesdays, Wednesdays, Thursdays, Fridays, Saturdays and Sundays.
It can lead to some strange scheduling, and ASU coach Herb Sendek is not particularly fond of it.
This week, his team is playing at Colorado late Wednesday night ahead of a Sunday game at Utah.
"Forgive me for being a crybaby, but the schedule makers did us no favors," Sendek told the Dan Bickley Show with Vince Marotta on Arizona Sports 98.7 FM Tuesday. "The next two weeknights we play at 9:00, we just did that a week ago against Oregon State. So three consecutive weeknight games at nine at night...and then we play with three days in between, so we're on the road from today to Sunday night.
"And then the last week in the season, we play a Tuesday/Saturday."
That will be a road trip at the Oregon schools, with Oregon on Tuesday and Oregon State Saturday. But prior to the first of those two, ASU will be playing Saturday night against California. That means they'll have all of two days off between games, meaning schedules are shuffled to make it work.
"You have to practice on Sunday and so our guys' schedules have really taken a hit," he said. "We have some extended road trips and a lot of late-night games at 9:00, which I think are very difficult for everybody."
It's something every team in the conference has to deal with, at least to some extent, so it's not as though the Sun Devils are alone in having to "suffer" through the scheduling quirks. And if it is the only way to ensure every game is on television, perhaps it's a necessary evil.
But that does not make it any easier to deal with.
"They tell you when to play and what time to play," Sendek said of the TV contracts.
So, the Sun Devils play late. And they play early. And they play on random days each week. Wherever they're scheduled, they'll be.
College basketball, ladies and gentlemen.
"There's so many unique variables to college basketball that I think lend to the fact that every night we see games and there's so much parity," he said. "Look at what Duke is doing this week -- it was because of inclement weather -- but they played Saturday against Maryland, they play tonight against Georgia Tech, they play North Carolina Thursday and they play Syracuse Saturday."
That's more NBA than NCAA, but it's the way it is. And some wonder why teams struggle at certain points in the season.
"These are human beings and it's really unique to our sport, and I think it helps make it exciting at times, but it can make it very challenging on the student-athletes at the same time."


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Hairy Chested Stud Erin Hart Seduces a Dilf to Come Back to His Studio for Sex.
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ARM's stiff upper lip trembles at Chipzilla's Medfield
- By Joel Hruska on January 17, 2012 at 4:20 pm
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Last Thursday, near the end of CES, ARM's CEO Warren East lashed out at the idea that Intel's Medfield would win the company much mobile business. While he admitted that Intel would "get a few smartphone design wins," East dismissed the idea that the x86 CPU manufacturer could ever lead in power efficiency.
"They [Intel] have taken some designs that were never meant for mobile phones and they've literally wrenched those designs and put them into a power-performance space which is roughly good enough for mobile phones," he said.
"Wrenched." "Roughly good enough." These are the words of a CEO who's floundering after being caught off-guard. Read some of the company's previous blog entries on the subject, and it's clear that ARM wasn't expecting Intel to actually field a competitive design.
The word "competitive" is often defined in terms of performance, but if Medfield's benchmarks were the CEO's chief concern, he'd have simply pointed out that the upcoming bumper crop of Krait, Cortex-A15, and quad-core A9 processors will give Medfield a serious run for its money. Instead, we got aggressive verbiage on how Intel couldn't "really" compete with ARM.
Medfield is unsettling because it slashes power consumption, obviates the need for additional microprocessors (down to three chips from five), and integrates additional functions on-die. After Moorestown's debut and flop, ARM appears to have made the same mistake AMD did after Prescott — it assumed Intel was stymied and would remain that way for the foreseeable future.
All figures are approximate, but the platform-level power savings speak for themselves
East states that he views Intel as a serious competitor, but it's clear that the company never expected Chipzilla to come tromping into handsets at 32nm. The fact that the company has done so is evidence that it's time to reevaluate the factors that conventional wisdom state will hurt Intel's chances in the handset space.
Forget about RISC vs. CISC
In an ARM blog entry from last January, Professor David Patterson, one of the pioneers of RISC, wrote that ARM and MIPS "have 40% – 50% better energy per MHz and their size is a factor of 3X to 4X smaller than x86." He followed that up with "Computer architects I know believe that the… x86 instruction set… is the technical reason behind the doubling of power, price, and area, and factors of two will matter for a long, long time."
Patterson isn't wrong in stating that x86 compatibility carries a penalty in terms of die size and power consumption, but the impact of that penalty has been decreasing with each and every process generation. Exact info for Atom isn't available, but the slide of AMD's Bobcat, above, highlights how much silicon is devoted to x86 decoding. Even at 40nm, it's just a fraction of the total die — Bobcat spends much more die space on branch prediction and its FPU. Atom's relative distribution will be different, given that it lacks Bobcat's out-of-order execution, but x86 decoding simply doesn't consume die size the way it did even 10 years ago.
The other problem with focusing too much on ARM's purported efficiency advantage is that it misses the larger picture. A smartphone isn't just a CPU; it's a camera, a data storage device, a video/audio playback engine, and a cellular phone, with WiFi capability thrown in for good measure. Screen size (and type of screen) impacts power consumption very nearly as much as CPU type.
The size and power consumption difference between an ARM core and an x86 core is just one part of the overall equation. Many of the factors that impact power consumption are tied to the design of the SoC — a concept Jon Stokes, writing for Ars Technica, nicknamed "macroarchitecture." A modern smartphone SoC is a sophisticated hub for an array of integrated cores, caches, I/O blocks, memory controllers, and modems. Effectively managing the power consumption of these separate blocks is key to keeping device power low.
Next page: It's all about process
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Marc Guillot Puig
¿ Do you have some problem with ARM to be so biased ?.
ARM hast not been standing still, expecting that Intel would never improve. BIG.Little architecture will be something very hard to catch for Intel, even with far better foundry process (something ARM can't do nothing about).
Joel Hruska
Intel's response to big.LITTLE is that they don't need it. We will see if this turns out to be true — it's certainly possible. It comes down to the ability to customize the underlying silicon, which is something Intel can do far more than the ARM vendors can.
The big.LITTLE approach makes sense, given the realities of production at the big foundries. It's not a bad strategy — but that doesn't mean Intel can't match it. The question is whether or not Intel can match the power consumption curves ARM vendors hit with big.LITTLE through the use of a single CPU core.
He is dedsetmad
" can't do nothing about)." My God son, where did you learn to speak….if someone "can't do nothing" then "they CAN DO something"! If you are going to speak a certain language, learn how to use it.
Marc Guillot Puig
¿ Why don't wait to see if real life Medfield is half as good as some interested Intel benchmark says, before announce ARM inevitably death ?.
Intel has a very large history promising astonishing Atoms that never materializes (Atom always remembers me their GPU efforts).
Joel Hruska
"ARM" is not the problem — at least, not really. The bigger question is whether or not ARM's foundry partners can keep pace with Intel. Regardless, no one is forecasting ARM's death, least of all me.
Joel Hruska
"ARM" is not the problem — at least, not really. The bigger question is whether or not ARM's foundry partners can keep pace with Intel. Regardless, no one is forecasting ARM's death, least of all me.
http://twitter.com/Obdurodon Jeff Darcy
What's missing from this article is any mention of power gating. ARM is way ahead of Intel in this area, and the effect is even greater when all of the A/V and I/O parts of a modern SoC are considered. Even if the on-demand performance is equivalent the ARM part can spend most of its time with more than half of its pieces powered down, with significant effect on battery life and therefore market appeal. Medfield would need to have *at least* twice the raw performance of equivalent-generation ARM to overcome that, and it's nowhere close. How could a serious article on the subject not even address the issue?
Joel Hruska
Because I've already addressed it.
For Extremetech: http://www.extremetech.com/computing/112851-intel-medfield-x86-smartphones/2
and in more detail, for Hot Hardware:
If you want information on how Medfield's power consumption lines up against current shipping solutions, you can also check Anandtech:
Your statements regarding ARM being "way ahead of Intel" as far as their expertise in power gating are no longer correct. Medfield's most important achievements are in this area, and it's actually the bigger problem for ARM designs going forward as we move to smaller process geometries. Performance, as I note, is not so much the issue.
http://www.facebook.com/people/Soren-Kay/100001270456452 Soren Kay
"Warren East lashed out at the idea"He did not "lash out" nor is he scared. If anything he sounds confident as he should be. ARM has all the advantages on their side except process technology and that can't last forever nor is that gap increasing like you said.
Glenn Scott
And then the 800lb gorilla entered the cage :)
This is the exact same talk that was put forward when Microsoft made a little gaming console called the Xbox.
Marc Guillot Puig
The 800lb gorilla has been trying to enter in this cage for 4 years.
I will believe it when I see it.
But Joel Hruska do not write a sentence about Suvolta Powershrink tech which ARM have co-development with and that ARM have signed joint-venture with UCSD/MIT in development of energy boosting in efficiency.
One of Suvolta founders is a former Intel Fellow researcher.
http://janneman27.wordpress.com Jannie Kirsten
Is it just me or does the left hlf of the AMD "Core Floor Plan" look a lot like North-America?
Jeremy Thomson
It galls me, as an ARM fanboi since the archimedes, but I wonder if ARM have awoken a sleeping giant. Sure the x86 is kludge cubed that can trace the instruction set back to 8080, the most inelegant, inefficient POS that I never wan't to write assembler on ever again. And that counts for nothing because Intel have always had the best silicon process. With the best silicon even a 486 throwback can be competitive.
I sure hope Sumsung, TSMC and Global Foundries can compete with Intel on silicon process, but I doubt it. Intel has been winning with great silicon and mediocre design for a long time.
Is great design and great silicon too much to hope for?
The 800lb gorrila is Medfields price ? yes it "might" be competitive on performance and maybe even wattage, but Arm SoC tend to be sub $20 . Atoms are normaly at least twice that Of course Intel can price its Medfields that low , but does it make any money at that price? In a year or 2 the increased performance will be good enough to start harming sales of I3 etc. Can t see Intel shareholders being too impressed with falling margins . Does Intel really want to be in a low margin arms race with Samsung, Qualcomm etc ?
Joel Hruska
Intel can subsidize lower prices on Medfield to launch the part, then introduce higher prices when/if they establish a leadership position in performance and power consumption.
yes I know that is the plan , but its not gunna happen till at least 14 nm.. Being in an arms race with 4 or more different competitors won't be easy for Intel and the main problem is the size of each atom core , Medfield on a smaller node is similar size to Tegra 3 – around 80mm2- and that has 5 cores . So to increase Medfields to compete with A15 without increasing mhz by 50% (eats battery) then more core s need to be added, so the die will get bigger by prob 15mm2. I expect the first A15 SoC to be around 50mm2 with 2 A15 and maybe an A7, which will be half the Intel 2 core Medfield . Of course when the new OOO Atom appears at 14 nm then its game on . But I still can t see it being more than 15 % better than Arm at that time, and will have cost Intel billions in R&D and not made them a penny
Joel Hruska
Comparing SoC to SoC isn't an accurate way to measure die size. Tegra 3 is 5 cores, but it's 5 cores + additional hardware. Ditto for Medfield. The latter has a 256K SRAM that also pumps up die size (I don't think Tegra 3 has an analog.
It's definitely true that Saltwell (the CPU inside Medfield) is larger than any single ARM9 core. Is Saltwell bigger than NV's five A9 cores? Probably not.
Also, remember that the difference between process shrinks is squared, not linear. 22nm isn't 78.5% the size of 28nm — it's 61% as large.
yes i know its cores plus other stuff , thats why tegra 2 to tegra 3 increased from 55mm2 to 80 ish mm2 on the same node , the 3 extra 5mm2 cores added 15 mm2 and the bigger GPU about 5mm2 and other stuff about 5mm2 to make it 25mm2 bigger . I think Saltwell is about 15mm2 per core at 32 nm process and was approx 25mm2 at 45nm. So on an equal process is at least 4 times the size of Arm A9. A15 at 32 mn will be about 4 to 5mm2. An A7 approx 40% the size of an A9 and will be about 1 mm2 , ( ARM claims a single Cortex A7 core will measure only 0.5mm2 on a 28nm process), but i don't think that includes everything . How big do you think the Saltwell core is ?
What Intel should do if they want to enter this phone SoC market is set up a new company , think toyota – lexus , so as not to confuse with Intel and X86 . Then manufacture Arm IP like Qualcomm or even Arm chips . With its manufacturing lead it would wipe the floor with Samsung, Qualcomm etc. Forcing x86 in this space is like fighting with a huge monkey on your back and if you do get it to work it harms you main cash cow . Silly Idea . . Maybe the OoO atom won t be anything to do with X86? because legacy code in this market isn t needed and just holds you back. No one is gunna want to pay £100 per program as in Wintel world for a phone app when Arm android apps are £10 . So being X86 is no benefit , best start afresh if ya a new comer . Of course its slightly different in tablets , but there will be Arm Android tablets at £200-£300 and Arm Windows Tablets at £400 and X86 Intel / AMD windows tablets at £500 . All will be different and in no way compatible with each other
Joel Hruska
I think you're flat wrong regarding x86 being a huge monkey. There's no evidence it'll harm Intel's margins or ability to compete, as I've discussed at length.
There's no evidence Intel is pursuing a non-x86 strategy in this space.
While you're correct about different price points for different hardware, both Microsoft and Intel have gone to great lengths to ensure cross compatibility. Apps written for Windows 8 will run on ARM or x86. Intel has been working extensively with app developers to ensure that x86 versions of apps are available as well, with a goal of 90% compatibility by product launch.
Finally, there's no evidence that anyone is talking about $100 x86 apps versus $10 ARM apps. Again, there's a price differential to be negotiated — but others have noted the price difference between regular video games vs. portable video games (as an example) in the past. Such differences must be addressed regardless.
To be competive in this market means selling your SoC for around $20 , Intel won t be making 60% at that price . Arn't desktop Aoms at least twice the price at similar die size ?
Arm A9 cores are similar performance to Atom at similar clock speeds , and this is with a core 3 or more times smaller , so your saying X86 is efficient ?
The only way Intel is able to compete with year old Arm designs is with a superior manufacturing process , Atom X86 at 45 nm was a failure in smartphones
Intel prob won't ditch X86 in the smartphone market , (loss of face) but on an equal playing field , its not helping much either. Stick with X86 and you need your manufacturing process to be able to see the lead runners in front , get rid of that monkey off ya back and see how much faster you could run . Intel making Arm A15s on a 22 nm process would kill the rest tomorrow As would a compleatly new ground up legacy free design, but that would take 2 years or more . Can t really see any advantage of X86 arch in this new market with no legacy code . If X86 wins the smart phone , it will be inspite of X86 not because of it .
And the faster and more capable Atom is made the less people will need to spend extra on I3 etc . An I3 is just about fast enough for 80% of the world at the mo , so of course the accelerated road map for Atom now is gunna hurt their margins, Thats unless smartphone-tablet Atom will be completely split from desktop I3-I5 and run compleatly different code …. in which I see no benefit to X86 on Atom ? It seemed till last year it was slowly letting Atom die , n was gunna phase it out as I3 got more power efficient . Intel have got there self between a rock n hard place by getting into an arms race . They ve managed to keep AMD at bay with a better CPU and process , can t say it having only one advantage will work against Samsung and Qualcomm .
we ve no real idea how the tablet market will go , but microsoft arn't used to selling office for £10 and giving windows away for free like Android . so maybe thats why there saying locked boot loaders on windows tablets ?
Joel Hruska
You're over-focusing on the x86 vs. ARM angle. At the end of the day, what manufacturers care about is the size, performance, and power consumption of the entire phone. Obviously, yes, SoC parts play into that, and CPU architecture plays into *that*, but the choice of uarch isn't the deciding factor you're making it out to be.
One of the major points of my article is that this isn't about "x86 vs. ARM." It's about Intel's ability to execute a roadmap vs. GloFo and TSMC. It's about total device power consumption. There are a myriad of factors that you're glossing over when you turn it into a uarch debate.
http://profiles.google.com/northox Danny Fullerton
How much time will it take before we see Asians being accused
of stealing Intel's secret sauce and then selling us our own innovations?
The last chart here is a tell-tale sign of the danger:
1980s: PCs competing against systems with superior custom chip architectures. Intel beat them all with bruteforce.
1990s: x86 competing against more advanced RISC architectures in workstations and servers. Intel beat them all with bruteforce.
2000s: x86 competing against more advanced HPC setups. Intel beat them all with bruteforce.
x86 is by no means an elegant architecture, but the sheer scale of Intel's operation allows them to build incredibly advanced chips, and at very competitive prices. Mostly because of Intel's advantages in manufacturing, with smaller feature sizes, and better integration between chip design and manufacturing…
But also because Intel can churn out new architectures faster than anyone.
ARM is now facing an opponent with advanced SIMD instructions and HyperThreading technology.
And although Atom is not an out-of-order architecture, Intel obviously has the technology.
It was a deliberate decision not to include it in the Atom line (the extra cost in die-size and power consumption was probably not worth the performance gains). At some point they will probably decide that the time is right to add OoO to the Atom line.
It will be interesting to see how ARM will pick up the competition. They aren't doomed yet, but as we've seen with AMD, it's incredibly difficult to keep up with Intel once they get going.
Albert Bertilsson
I was convinced that x86 was the inferior design when compared to the beautiful 68k. I laughed at the 286 trying to run a multitasking OS… A few years later there was the 386, the 486 and the Pentium, and everything else seemed slow… I think the few people I knew running macs where the last ones taunting Intel (was it Power that ruled the world?).
Then Apple started using Intel and all the others vanished… I don't see much difference when comparing that with today. There is very little "secret sauce" in this, a slightly more clever branch predictor, a bit more efficient power gating, mixed core types… Any of the large design companies can invest the research to do it with varying results.
Finally: True game changers are rare, if one appears it puts both camps at square one. And if Intel is truly interested they do have some cash.
The only thing speaking against Intel would be being fat and happy. That gave AMD an opportunity they took and continued to execute well on from time to time.
Its great to see an article not totally biased against intel in the SOC space for once…
ARM is scared, their CEO just blowing off intel with "they cant do it", and "wrenching" in things not meant for low power? has this guy ever design anything? (out of order execution wasnt a traditional low power design feature either and they wrenched it in there lol)
Intel finally coming back one year later driving down power significantly and this is all the guy has to say? they must be scared…
Obviously intel was catching up since they have always designed for performance, but intel has pioneered power gating and other power features in their client space for years (obviously all power numbers are relative to the space and just needed to scale into another design)
What people do not realize is Patterson is wrong saying that x86 is the problem, its a much more powerful ISA and the decoding logic only costs a tiny bit more over a direct risc, and in most cases the decode time of an x86 instructions is the SAME as ARM. (Everyone got that?)
Owning the whole ISA and CPU design gives intel the ability to add and modify instructions, embedd certain features such as security, and change the organizational hierarchy of SOC blocks better for performance.
Not to mention they have their own custom fabs and can better tweak the process…
Honestly ARM should be scared.
P.S – no fanboy blabber these are facts.
Joel Hruska
I'd be exceedingly careful of statements like this: in most cases the decode time of an x86 instructions is the SAME as ARM. (Everyone got that?)
The eggheads at RealWorldTech recently had a major discussion on precisely this point. Bottom line — comparing instructions isn't very possible. Even decode times aren't very comparable because the contents of an instruction can vary from uarch to uarch. P4 and Sandy Bridge both decode x86 instructions into microinstructions, for example, but the microinstructions themselves are not comparable — and that's within x86.
I'm leery of calling Patterson wrong — something about the fact that he helped *invent* RISC, and I'm a journalist ;) I think his statements are true, but focusing on them misses the larger picture. It's a given that the CPU is only one component that draws power within a smartphone. Now consider that the *difference* between x86 and ARM in terms of power draw is an even smaller part of the total. That's the overall point I'm driving at. Does it matter? Yes. But it's going to matter less with every passing year.
There is nothing to be careful about… I am not talking about eggheads at some RealWorldTech website, lets just say Im a RealWorld Engineer working in these areas….
Yous splitting hairs about the exact contents of the risc like decoded instructions. yes P4 and P6 are different microarctectures, P4 stopped being used when the first Core 1 line came out. No matter how you slice it CISC CPU's decode the cisc instructions to risc like ones to execute, has been this way since the end of like VAX vector super computers..
x86 is the ISA and seperate from the microarchitecture, you cannot compare internal micro architectural design details between projects that are like 10 years apart and expect them to be the same…
Its a qualitative not quantitative comparison of the effort to do this CISC-RISC conversion. Which is the only difference if your strictly comparing the ISA, not even discussing the added benefits of cisc such as code size and some perfomance instructions. Reltativly speaking this "ISA" conversion loss would have been a power issue many years ago but not with current technology. It can even be oberserved with performance checking and thermal imaging under workloads that comparitavly speaking they are no longer hot spots… In most instances the decode is the same as a RISC/ARM instruction but there is those special cases where x86 has added some performance or power related instruction.
Just because Paterson says something doesnt make it law i have seen him speak on simmilar topics at conferences. Its just his opinion ok and most real engineers would agree.
But The Point you are driving is NOT Valid. The power descrepancy in ANY intel product and ANY ARM product (yes i said ANY even core i7) has nothing to do with the ISA used, differences between RISC and CISC or whatever you want to call it…. The instruction set and the microarchitecture are two different things… Its simple from both companies inceptions intel went for high performance and ARM went for low power for embedded.. Intel spent years innovating for performance in speed and power (this isnt as obvious since this space had a higher power envelope to begin with be relativly speaking yes). Not really sure what ARM was doing for those decades (adding modest improvements till recently), and now intel has been optimizing architectures for low power and is already starting to have comparable power/performance.
Just so its clear im not trying to be a smartass but you cannot say the main difference in power between two modern CPUs is the instruction encoding used… you can cram two of the same tests into those CPUs and they might be a different language or run at different speeds, but you cannot blame your power consumed on this.. its a NON factor…
experimentally you guys can try and find density of the design and compare whats going on in the decoder and see if that isnt a rounding error… lol
Joel Hruska
Allow me to quote:
"So don't compare one ARM instruction to one x86 instruction.
They are very different. An ARM instruction is closer to
the old-style uops (and by "old-style" I mean the ones that
Intel used to produce that didn't have read-modify-write
versions: the uops in Core 2+ are rather closer to the
real x86 instructions).
The "uops per instructions" on x86 (again, older x86)tended to be in the 1.2-1.7 range on spec, according to somepapers (again, they are now much closer to 1:1, but that'sbecause the modern Core2+ uops are actually more powerfulthan ARM instructions are). "
If you'd like to argue the point, I suggest you hop over to http://realworldtech.com/forums/index.cfm?action=detail&id=125194&threadid=125178&roomid=2 and take it up with Linus Torvalds. I believe his bona fides as a "real world" engineer should pass muster. Having read that entire thread, I'll take his word for it. ;)
Reading articles and stating someone elses opinions does not mean you know what you are talking about…
uops are not the same as the Cisc instructions, i didnt realize intel published their decoding and UOP documents for public use? Some uops are just close to the x86 instruction in the sense that 1 cisc translates to one uop, instead of multiple instructions.
Most people have not designed a Microprocessor, have you? we are talking about the power with respect to CISC to RISC decoding.
The whole arguement is based on the fact that the ISA is the reason for the power gap. This is wrong since after decode the instructions executed are simple RISC type instructions… So the only point of interest would be the power consumed by the decoding logic Which is insignificant!!! Most power is consumed in scheduling, especially now that ARM has out of order execution in their microarch..
The Power gap which is small now can be observed as coming from muliple areas, not the x86 decode.
Joel Hruska
You seem to be attributing arguments to me that I'e never made. You say "
The whole arguement is based on the fact that the ISA is the reason for the power gap"
Except I'm not arguing the origin of the power consumption discrepancy. All I did was state that 1) The amount of die space devoted to the x86 decoder is small and getting smaller and 2) Even if RISC is more power efficient, the CPU is only one component of an entire smartphone.
Finally, 3) You can't compare x86 uops to ARM uops.
I'd be interested to know what parts of the CPU are responsible for the relative difference in power consumption between x86 and Cortex-A9, but I made no statements implying that I did.
Yeah that guy seems pretty smart and all, but he's being a real asshole.
Sorry it was Patersons quote who said architects believe the ISA is even an issue anymore for power consumption problems.
you cant compare the Uops, but you can compare the power consumed by the decoding of the CISC instruction. The only thing left to do is compare the average power consumed in similar platforms, one optimized for x86 and one for ARM, which is what is already being done.
http://pulse.yahoo.com/_DYIS2XDY3RNU53CEMESBDTAEMM Mike
Great article. You nailed it.
http://society50.com wmac
Added to the ARM problem is the difficulty of maintenance and development of software for so many different ARM architectures. In Intel Camp we will have x86 for lower end and x64. I really think ARM has made a mess here.
Joel Hruska
This is not an issue. Only two ARM architectures (ARMv7 and, eventually, ARMv8) are in use.
http://society50.com wmac
Then I did not properly understand the discussion in this page: http://stackoverflow.com/questions/4381102/differences-between-arm-architectures-from-a-c-programmers-perspective
I thought I should recompile every time (to guarantee best binary compatibility).
Joel Hruska
In Android, code is written either in Java (runs using Dalvik) or the Android NDK. There's also an x86 flavor of the NDK.
The original NV Tegra used an ARM11 MPCore but aside from that it looks like everything is ARMv7-based. That means there shouldn't be much of an issue.
I'm assuming that ARMv8 is designed as a superset of ARMv7 and that the chip handles fallback to the other architecture gracefully, just like the x86-64 chips could run in either mode without a problem.
http://society50.com wmac
Joel, thank you very much for clarifying. I appreciate very much.
Joel Hruska
In Android, code is written either in Java (runs using Dalvik) or the Android NDK. There's also an x86 flavor of the NDK.
The original NV Tegra used an ARM11 MPCore but aside from that it looks like everything is ARMv7-based. That means there shouldn't be much of an issue.
I'm assuming that ARMv8 is designed as a superset of ARMv7 and that the chip handles fallback to the other architecture gracefully, just like the x86-64 chips could run in either mode without a problem.
"Literally wrenched…?"
Joel Hruska
Yes. LITERALLY.
I was at Intel HQ. We SAW the wrenches.
Like that one.
http://profile.yahoo.com/5HUKM6ETOKSBNRNAODIGVQX4NA fiber geek
These power comparisons are misleading. Video is probably running on a HW accelerator. The power is still very high. Competitive video playback numbers for 720p are less than 700mW even in 45nm. At 28nm going to production by 2H 2012 it could be half of that. Browsing talk and standby are more related to how Intels modem team has architected it. Talk etc depends on PA and RF power.. Nothing to do with processor at all since modem is a seperate chip in this phone. Apples to apples comparisons have to be made in real CPU to CPU metrics.
May I add that the intel modem chips use ARM?
Joel Hruska
Intel hasn't publicly released any information on what specific IP blocks are in the SoC as far as video acceleration, so I can't comment on that. You are correct that video playback power use is significantly higher on Medfield than other parts.
It's standby, talk, and browser power consumption are all much more competitive.
http://society50.com wmac
wrong post
Joel Hruska
Intel hasn't publicly released any information on what specific IP blocks are in the SoC as far as video acceleration, so I can't comment on that. You are correct that video playback power use is significantly higher on Medfield than other parts.
It's standby, talk, and browser power consumption are all much more competitive.
Joel Hruska
Intel hasn't publicly released any information on what specific IP blocks are in the SoC as far as video acceleration, so I can't comment on that. You are correct that video playback power use is significantly higher on Medfield than other parts.
It's standby, talk, and browser power consumption are all much more competitive.
Joel Hruska
Intel hasn't publicly released any information on what specific IP blocks are in the SoC as far as video acceleration, so I can't comment on that. You are correct that video playback power use is significantly higher on Medfield than other parts.
It's standby, talk, and browser power consumption are all much more competitive.
Joel Hruska
Intel hasn't publicly released any information on what specific IP blocks are in the SoC as far as video acceleration, so I can't comment on that. You are correct that video playback power use is significantly higher on Medfield than other parts.
It's standby, talk, and browser power consumption are all much more competitive.
Joel Hruska
Intel hasn't publicly released any information on what specific IP blocks are in the SoC as far as video acceleration, so I can't comment on that. You are correct that video playback power use is significantly higher on Medfield than other parts.
It's standby, talk, and browser power consumption are all much more competitive.
He is dedsetmad
Yeah, I agree.
The article in a nutshell says that Intel will be a strong competitor because of it's process technology lead will overcome x86's architectural inefficiencies.
That may be, but let's also ask why Intel has such a process tech lead in the first place? It's because of it's virtual monopoly over PCs allow it to spend the billions in needs to develop modern fabs. Let's see if they can keep that up when they are selling chips for $20 for cellphones instead of $300 for PCs


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what is LOCI??? Wierd that I dont know since I am a mich student. Only UG.
Well he's had it in for me ever since I kinda ran over his dog... Well, replace the word "kinda" with "repeatedly" and the word "dog" with "son."
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