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A method of testing a digital integrated circuit for faults. A plurality of n check points l1, l2, . . . , ln are established to define a test sequence. A set of m references r1, r2, . . . , rm are predefined, corresponding to the signatures which the circuit would produce at the corresponding check points in the absence of any faults. A test sequence is applied to the circuit and an output signature si is derived from the circuit at the corresponding check point li. The output signature is compared with each member of the set of references. The circuit is declared "good" if the signature matches at least one member of the set of references, or "bad" if a signature matches no members of the set of references. Testing proceeds in similar fashion at the next check point, until the circuit has been tested at all check points.
1. A method of testing a digital integrated circuit for faults, said digital integrated circuit comprising one or more inputs and one or more outputs, wherein the state of said one or more outputs of said digital integrated circuit is responsive to signals at said one or more inputs, said method comprising the steps of:
(a) providing a means to apply a sequence of test vectors to said one or more inputs of said digital integrated circuit;
(b) providing a means to generate a signature si determined by a sequence of states of said one or more outputs of said digital integrated circuit;
(c) selecting a sequence of test vectors;
(d) establishing a plurality of n check points l1, l2, . . . , ln, where n>1, in said sequence of test vectors;
(e) defining a set of m reference vectors, r1, r2, . . . , rm, where m>1, said set of m reference vectors corresponding to signatures produced by said digital integrated circuit at said check points l1, l2, . . . , ln in the absence of any faults in said digital integrated circuit,
(f) applying said sequence of test vectors to said one or more inputs of said digital integrated circuit to cause said one or more outputs of said digital integrated circuit to pass through a sequence of states of said one or more outputs;
(g) at each check point li, where l≦i≦n, of said plurality of n check points:
(i) deriving a signature si from a sub-sequence of states of said one or more outputs of said digital integrated circuit said sub-sequence of states ending at said check point li ;
(ii) comparing said derived signature si with reference vectors from said set of m reference vectors;
(iii) rejecting said digital integrated circuit if said derived signature does not match any of said set of m reference vectors; and
(h) passing said digital integrated circuit if each derived signature si matches at least one member of said set of m reference vectors.
2. The method of claim 1 wherein said means to generate a signature si representative of a sequence of states of said one or more outputs of said digital integrated circuit comprises a data compactor and said step of deriving a signature si from said sub-sequence of states of said outputs of said digital integrated circuit at said check point li comprises compacting a vector corresponding to said sub-sequence of states of said one or more outputs of said digital integrated circuit in said data compactor.
3. The method of claim 2 where m=n.
4. The method of claim 2 where m>n.
5. The method of claim 2 where 1<m<n.
6. The method of claim 2 where m=1 and n is greater than 1.
7. A method of testing a digital integrated circuit for faults, comprising the steps of:
(a) establishing a plurality of n check points l1, l2, . . . , ln, where n>1 in a test sequence;
(b) defining a set of m references, r1, r2, . . . , rm, where m>1, said set of m references corresponding to signatures produced by said digital integrated circuit at said plurality of n check points l1, l2, . . . , ln in the absence of any faults in said digital integrated circuit;
(c) applying said test sequence to said digital integrated circuit;
(d) for each check point li, where 1≦i≦n, of said plurality of n check points:
(i) deriving a signature si from said digital integrated circuit at said check point li ;
(ii) comparing said derived signature si with members of said set of m references;
(iii) rejecting said digital integrated circuit if said derived signature does not match any of said members of said set of m references; and
(e) passing said digital integrated circuit if each derived signature si matches at least one member of said set of m references.
8. The method of claim 7 where m=n.
9. The method of claim 7 where m>n.
10. The method of claim 7 where 1<m<n.
11. The method of claim 7 where m=1 and n is greater than 1.
12. A method of testing a digital integrated circuit for faults, said method comprising the steps of:
(a) selecting a sequence of test vectors to apply to said digital integrated circuit;
(b) breaking said sequence of test vectors into a plurality of n sub-sequences, each of said plurality of n sub-sequences terminating at one of a plurality of n check points l1, l2, . . . , ln ;
(c) defining a set of m references r1, r2, . . . , rm corresponding to signatures produced by said digital integrated circuit at said plurality of n check points l1, l2, . . . , ln in the absence of any faults in said digital integrated circuit;
(d) applying said sequence of test vectors to said digital integrated circuit and, at each check point li, where 1≦i≦n, of said plurality of n check points:
(i) deriving a signature si from said digital integrated circuit at said check point li ;
(ii) comparing said derived signature si with said set of m references to determine whether or not said derived signature si matches any member of said set of m references;
(iii) passing said digital integrated circuit if, at all of said plurality of n check points, said derived signature si matches at least one member of said set of m references; and,
(iv) rejecting said digital integrated circuit if, at any of said plurality of n check points, said derived signature si matches no members of said set of m references.
13. The method of claim 12 where m=n.
14. The method of claim 12 where m>n.
15. The method of claim 12 where 1<m<n.
16. The method of claim 12 where m=1 and n is greater than 1.
17. The method of claim 12 wherein said sub-sequences are not all identical.
18. The method of claim 12 wherein said sub-sequences are not all equal in length.
This application pertains to the testing of large scale digital integrated circuits for detection of circuit faults. A "fuzzy" multiple signature analysis approach eliminates the need for strict one-to-one correspondence between each signature obtained from the circuit under test and a reference signature. Signatures obtained from the circuit under test need only correspond to any one of a set of reference signatures.
Built-In Self-Test ("BIST") is an increasingly popular means of testing large scale digital integrated circuits ("ICs") for circuit faults. A test pattern is generated on the IC to be tested; and, output data obtained by subjecting the IC to the test pattern is evaluated on the IC itself. The output data evaluation generally consists of (i) data compaction, whereby the output sequences produced by the circuit under test ("CUT") are compacted into a single signature of a few bits, and (ii) comparison of the signature with a predetermined fault-free signature to determine whether the CUT is good. However, due to the information loss through data compaction, some error responses may be mapped to the fault-free signature, thus causing some faulty circuits to escape detection. This problem is called aliasing. Usually, fault coverage before compaction can be detected by fault simulation. But, fault coverage after data compaction can usually only be estimated since exact fault simulation is not computationally feasible for large circuits. Although many probabilistic techniques have been developed, they can not be used with confidence for a specific CUT because of statistical uncertainties.
At least two kinds of signature analysis have been proposed: single signature ("SS") analysis and multiple signature ("MS") analysis (see: Bardell, P. H., McAnney, W. H. and Savir, J., "Built-In Test for VLSI: Pseudorandom Techniques", John Wiley & Sons, Inc., 1987). In the SS scheme, only a single final signature is checked at the end of a test session. In the MS scheme, however, in addition to the final signature, some intermediate signatures are checked as well. The MS scheme is known to significantly reduce aliasing. Recently, it has been shown that, besides reducing aliasing, checking multiple signatures has many other advantages over the SS scheme. For example, by checking multiple signatures, exact fault coverage after data compaction can be easily computed for large CUTs by fault simulation. Average test time can be greatly reduced by checking multiple signatures since a faulty CUT's testing session can be terminated as soon as any incorrect intermediate signature is detected. Fault diagnosability also improves with multiple signatures.
A major problem with MS schemes is that they require complex implementation and large associated hardware overhead. In "A Multiple Signature Scheme for BIST", Proc. Cdn. Conf. on VLSI 1991, the present inventors proposed a multiple signature compaction scheme for BIST. By sharing some of the circuitry required by standard single signature BIST schemes, the scheme achieves very small aliasing at the expense of small silicon area. Unfortunately, the scheme's silicon area requirements increase with test length. This makes the scheme less attractive as CUTs get larger and require long test sets. The present invention provides a new output data compaction scheme for BIST which is simple to implement and requires little hardware overhead, even compared with SS schemes, and yet has all the advantages of conventional MS schemes.
In accordance with the preferred embodiment, the invention provides a method of testing a digital integrated circuit for faults. A plurality of n check points l1, l2, . . . in are established at specific points within the test output sequence. A set of m references r1, r2, . . . , rm are predefined. This set of m references includes at least all of the signatures which the circuit would produce at the corresponding check points in the absence of any fault or faults. A test sequence is applied to the circuit and an output signature si is derived from the circuit at the corresponding check point li. The output signature is compared with each member of the set of references. If the signature does not match any member of the set of references, the circuit is declared "bad" and testing may be terminated. If the signature matches any member of the reference set, testing proceeds in similar fashion to the next check point. The circuit may be declared "good" if the signature corresponding to each of the pre-defined check points matches at least one member of the reference set.
FIG. 1 is a block diagram representation of a conventional prior art multiple signature compaction scheme having a parallel comparator.
FIG. 2 is a block diagram representation of a multiple signature data compaction scheme in accordance with the present invention.
FIG. 3 depicts a three bit signature observer for use with references 111, 110 and 100.
FIG. 4 is a graph illustrating the aliasing performance of the invention.
FIG. 5 is a graphical comparison of the silicon area overhead requirements of a multiple signature data compaction scheme in accordance with the present invention with those of conventional single and multiple signature schemes.
FIG. 6 is a graphical comparison of the silicon area overhead requirements of a multiple signature data compaction scheme in accordance with the present invention with those of a conventional multiple signature scheme.
FIG. 7 is a schematic diagram of a detector circuit for detecting a Pass/Fail signal produced by a signature observer.
FIG. 8 is a block diagram of a hardware model used to study the fault coverage performance of a multiple signature data compaction scheme in accordance with the present invention.
FIG. 9 is a block diagram of a hardware model used to verify the performance of the invention.
FIG. 10 is a block diagram of a two stage linear feedback shift register for checking two signatures.
1.0 Conventional Signature Analysis
1.1 Single Signature Schemes
In BIST with signature analysis, to compact an output sequence, the sequence is shifted bit by bit into a signature analyzer implemented by a linear feedback shift register ("LFSR"). At the end of the test session, the contents of the LFSR form the signature. Denoting the output sequence length by l and the number of the LFSR stages by k, under the assumption of the equally likely error model of Bardell et al (supra) the aliasing probability Pal is: ##EQU1## Assuming l>>k yields Pal ≈2-k. This asymptotic result is well-known, and is also true for unequally likely error models.
1.2 Multiple Signature Schemes
Assuming the equally likely error model, it has been shown that if two signatures are checked, i.e., an intermediate signature after the first l1 bits of the sequence have been shifted into the signature analyzer, and a second signature at the end of the sequence of length l, then the aliasing probability is: ##EQU2##
Assuming l>>k yields Pal (2)≈2-2k. It is easy to prove that Pal (n)≈2-nk if n signatures are checked at positions l1, l2, . . . , ln, respectively, and assuming k<<l1 <l2 < . . . <ln =l, where li is the position of the ith signature. These positions are called "check points". Assume the n signatures generated by the LFSR at the check points l1, l2, . . . , ln are s1, s2, . . . , sn, i.e., the ith signature si is checked after li bits of the sequence have been shifted into the LFSR. Once the check points are fixed, by logic simulation, one can easily determine the n corresponding fault-free signatures or references, r1, r2, . . . , rn. When testing the CUT, the ith signature si is compared with its corresponding reference ri at the ith check point. Thus, in this prior art scheme, the signatures and references must correspond on a one-to-one basis for a CUT to be declared good. Such a one-to-one correspondence between specific references and signatures at specific check points makes conventional multiple signature ("CMS") schemes complicated and expensive to implement.
FIG. 1 illustrates an implementation of such a prior art CMS scheme. As shown, in addition to a read only memory ("ROM") for storing the n references, extra circuitry is required for generating ROM addresses and comparing ROM output with the signatures from the LFSR. Usually, such extra circuitry requires more silicon area than the ROM itself. This is because implementing the address generator requires a form of counter, which is area-consuming compared to combinational circuits and ROM cells. Also, comparing the references with the signatures requires either a parallel comparator or a serial comparator with some kind of parallel to serial converter to convert each k-bit reference into a serial k-bit sequence. A parallel comparator or a parallel to serial converter also takes considerable silicon area if k is not very small. Furthermore, connections among these functional blocks can also take much area.
2.0 Fuzzy Multiple Signature Analysis
As mentioned above, the complexity of checking multiple signatures is mainly due to the need for one-to-one correspondence between the references and signatures. Removal of this strict requirement significantly simplifies the data compactor. This essential concept, which underlies the present invention, is referred to as a Fuzzy Multiple Signature ("FMS") scheme since it consists of checking multiple signatures, without requiring one-to-one correspondence between each reference and signature.
2.1 Basis
Like the CMS scheme, the FMS scheme also checks n signatures at check points, l1, l2, . . . , ln. But, unlike the CMS scheme where a signature si is compared with a specific reference ri at check point li, in the FMS scheme, each signature si is compared with the whole set of references r1, r2, . . . , rn. A signature si is considered good if it matches any of the references in the reference set. Therefore, in the FMS scheme, for a CUT to be declared good, it suffices that the signature obtained from the LFSR at each check points corresponds to any of the references r1, r2, . . . , rn. Thus, in the FMS scheme, the requirement for the one-to-one reference-to-signature correspondence is removed. This "fuzziness" introduced by allowing a multiple reference-to-signature correspondence may result in a small increase in aliasing compared to the CMS scheme for given k and n. But, this can be easily compensated for by the reduced complexity of the FMS scheme compared to the CMS scheme. Otherwise, the FMS scheme has all the advantages that the CMS scheme has over SS schemes.
2.2 Implementation
Since one-to-one correspondence between references and signatures is unecessary, implementing the FMS scheme is very simple. As shown in FIG. 2, the FMS scheme requires a Signature Observer ("SO") and a LFSR. The LFSR collects signatures. The SO checks each signature, and generates Pass/Fail signals. At each check point, if the signature generated by the LFSR matches any of the references, the SO outputs a Pass signal, say logic 0. Otherwise, the SO outputs a Fail signal, say logic 1. The Fail signal can be fed to a test controller to terminate the testing and declare the CUT as faulty. If the SO outputs Pass signals at all of the predetermined check points, the CUT is declared good. The SO is a k-input, 1-output combinational circuit which outputs a 0 when its input vector belongs to the reference set, and outputs a 1 otherwise.
Assume n=k=3, i.e., to check three 3-bit signatures. If the references are r1 =111, r2 110, and r3 =100, denoting the three bits of the references by b1, b2, and b3, respectively, the function of the SO can be described as:
Pass/Fail=b1 b2 b3 +b1 b2 b3 +b1 b2 b3 =b1 b2 +b1 b3 = (3)
Thus, the SO can be implemented with two 2-input NAND gates as shown in FIG. 3.
In general, to check n k-bit signatures, the SO can be easily implemented with a k-input, 1-output, m-cube programmable logic array ("PLA"), or other non-PLA-type logic structures. However, logic minimization can be used to reduce the area of the SO, as illustrated in Example 1. Furthermore, the number of references m that need to be included in the set of references can be reduced using the techniques described below, thereby reducing the hardware requirements of the SO.
2.3 FMS Aliasing Performance Analysis
Assume the compaction of a l-bit random sequence into a k-bit signature, and r1 to be the only valid reference. The total number of sequences (including the fault-free one) that map to r1 is 2l-k. If it is assumed that distinct references r1 and r2 are both acceptable, then the total number of sequences that map to either r1 or r2 is 2ū2l-k since the sequences that map to one will not map to the other. Thus, assuming that m distinct references, r1, r2, . . . , rm are acceptable, the total number of l-bit sequences that map to any one of the m references is mū2l-k. Excluding the fault-free sequence, the number of aliased error sequences for such case is thus mū2l-k -1. Since there are 2l -1 possible error sequences, assuming all are equally likely, the aliasing probability when m distinct references are acceptable at a single check point is: ##EQU3##
Assuming l>>k yields Pal ≈m2-k.
The FMS scheme checks n signatures at check points l1, l2, . . . , ln against a set of m references, with m≦n because there can be at most n distinct references if n signatures are checked. However, some references may happen to be, or be made identical, thus making m<n. Using the arguments presented above in Section 1.2 for the aliasing probability of CMS schemes, the following aliasing probability results for the FMS scheme: ##EQU4## where li is the ith check point.
Assuming li >>k yields:
PFMS ≈[m2-k ]n (6)
Clearly, for fixed k and n, the best-case aliasing occurs for m=1. The worst case aliasing occurs when m=n, for which PFMS ≈[n2-k ]n.
The following analysis assumes the worst-case scenario (i.e., m=n). To study the aliasing performance of the FMS scheme a "FMS scheme equivalent length" Le FMS is defined as a figure of merit. For a given aliasing probability in the FMS scheme, define Le FMS to be the length of a LFSR that yields the same aliasing probability in a SS scheme. Ideally, Le FMS should be as large as possible to minimize aliasing. Assume Le FMS to be a continuous variable. Since PSS ≈2-k and PFMS ≈[n2-k ]n, then
2-L.sbsp.e.spsp.FMS ≈[n2-k ]n (7)
Solving for Le FMS yields:
Le FMS =n(k-log2 (n)) (8)
In comparison, the equivalent length of a CMS scheme is Le CMS =nk; while that of a SS scheme is Le SS =k. Thus, Le FMS =Le FMS -nlog2 (n) for given n and k.
Assuming k=16 and n=4, Le SS =16, Le CMS =64, and Le FMS =64-4ū2=56. Thus, PCMS =2-64, PFMS =2-56, and PSS =2-16. Here, the aliasing probability of the FMS scheme is 2 orders of magnitude greater than that of the CMS scheme, but still 12 orders of magnitude smaller than that of the SS scheme.
With the CMS scheme, the equivalent length increases linearly with both k and n. With the FMS scheme, however, the equivalent length increases linearly with k but not with n. For fixed k, as n increases, Le FMS peaks and then decreases. When n=2k, Le FMS =0. FIG. 4 shows an example of the Le FMS as a function of n for k=8, k=9, k=12 and k=16.
3.0 Comparative Evaluation of the FMS Scheme
The aliasing performance and hardware requirements of the FMS scheme will now be compared with those of the SS and CMS schemes, respectively. The worst case of the FMS scheme, i.e., m=n is again considered, and no logic minimization is performed for the SO's function.
3.1 FMS vs. SS
To achieve an aliasing probability of 2-k, the SS scheme requires a k-bit LFSR. To achieve the same aliasing probability, the FMS scheme only requires a (k/n+log2(n)) bit LFSR plus the silicon area for the signature observer. For the following more detailed area comparisons, a PLA implementation of the SO is assumed. Since each PLA input variable corresponds to two lines in the AND plane of a PLA, and since the drivers in the PLA take an area of about 8 cubes, the normalized area of a k-input, s-output, n-cube PLA is (n+8)ū(kū2+s) units. Area estimate comparisons are based on the actual layout of a PLA and a 16-bit LFSR, using the Cadence™ automatic place and route tool, and 3 um double-metal CMOS technology. The LFSR was built with static standard cell D flip-flops, and measured about 1.38ū106 um2. Actual layout revealed that a 12-input, 4-output, 64-cube PLA takes about the same area as a 16-bit LFSR. According to the above analysis, this PLA requires an area of (64+8)ū(12ū2+4)=2016 units. Therefore, it is assumed that a PLA of 2016 units corresponds to the area of a 16-bit LFSR. The following example illustrates the comparison of the FMS and SS schemes.
If k=9 and n=32, PFMS =[32ū2-9 ]32 =2-128. In this case, the required hardware is a 9-stage LFSR, and a 9-input, 1-output, 32-cube PLA to implement the SO. The PLA requires (32+8)ū(9ū2+1)=760 units of area, which is about 37.7% of the size of a 16-bit LFSR, or about the size of a 6-bit LFSR. Thus, the total area overhead for the FMS scheme to achieve PFMS =2-128 is approximately the area of a 6+9=15 bit LFSR. In comparison, a SS scheme would require a 128-bit LFSR to achieve PSS =2-128. More examples are summarized in FIG. 5, where the area for achieving a given aliasing probability is given in terms of equivalent LFSR sizes. As shown in FIG. 5, with the FMS scheme, small aliasing can be obtained against very small hardware overhead compared to what is required in the case of a SS scheme.
To simplify the comparison of the FMS and CMS schemes, for the CMS scheme assume a PLA is used to implement the ROM and comparator functions while the address generator is implemented using a log2 n-bit counter if n signatures are checked. To check n k-bit signatures with the CMS scheme, the PLA has k+log2 n inputs, 1 output and n cubes. The PLA's inputs are the k-bit signature from the LFSR (as in the FMS scheme) and a log2 n-bit index from the counter. Here, one need only measure the area overhead beyond that required by a SS scheme (in other words, the area of the LFSR is not measured, since it is the same for both the FMS and CMS schemes). Thus, the area overhead of the CMS scheme consists of the PLA and the counter. For the FMS scheme, the area overhead is simply a k-input, 1-output, n-cube PLA that implements the SO if n k-bit signatures are checked. The area overhead of the FMS and CMS schemes will now be compared, given a desired aliasing probability.
From the analysis in Section 2.2, for a given signature length k, checking n signatures in the FMS scheme achieves the same aliasing probability Pal as checking n-n/klog2 n signatures in the CMS scheme. Thus, given k and a desired Pal, the number of signatures required can be determined for the FMS and CMS schemes respectively. Then, using a calculation similar to that used in Section 3.1, the area required for the FMS and CMS schemes, respectively can be determined.
FIG. 6 illustrates the area overhead of the FMS and CMS schemes for k=8 and k=12. In FIG. 6, the area overhead is given in terms of equivalent LFSR sizes. From FIG. 6, when k=8, the FMS scheme requires less area overhead, compared to the CMS scheme, as Pal >2-120. When k=12, and for Pal greater than 2-500 approximately, the FMS scheme requires less area overhead than the CMS scheme. If k=16, for Pal greater than about 2-1000 approximately, the FMS scheme requires less overhead also. For a fixed k, when Pal is smaller than a certain value, the area overhead of the FMS scheme becomes higher. This is because the aliasing probability of the FMS scheme is not a linear function of n when k is fixed (see FIG. 4).
4.0 Observation and Control
4.1 Test Result Observation
Two different cases are considered for observation of the test results. First, if there is a Pass/Fail pin available, a "zero" detector may be used, as shown in FIG. 7, to detect the Pass/Fail signal output by the SO. Prior to testing a CUT, the "zero" detector is preset to "1", thus setting the Pass/Fail pin to 0. When a signature is checked, the controller temporarily sets the chk signal to 1. This sensitizes the "zero" detector to the SO output. Once a Fail signal (a "1" at the SO output) is detected, the detector outputs and keeps a Fail signal, "1", at the Pass/Fail pin. The "zero" detector can be shared by all self-testable blocks on an IC chip. When shared, the detector outputs and keeps a Fail signal if any of the self-testable blocks is found faulty. This Fail signal can be used to terminate testing, thereby reducing test time.
In the second case, where a specific protocol for control and observation of BIST is available (see, for example, Scholz, H. et al., "ASIC Implementations of Boundary-Scan and BIST," Int. Custom Microelectronics Conf., London, UK, Nov. 1988, pp. 43.0-43.9) the test result of each self-testable block may consist of a single-bit flag stored in a status register. Once a faulty signature from a self-testable block is detected, the flag for the block is set. The status can be accessed through the IEEE 1149.1 Test Access Port. In this case, the flag can be used as the "zero" detector discussed above for the first case.
4.2 Control Implementation
The controller required for the FMS scheme is the same as for the CMS scheme. It will be shown that the hardware overhead of the FMS scheme's controller can be made as small as that required for the control of a SS scheme. For the control of a SS scheme, an on-chip counter or LFSR (which may be simultaneously used for pseudo random pattern generation) is required to count the applied test vectors. When the final count is reached, a decoder detects this final count and generates a signal to stop the test and perform final signature evaluation.
For the control of the FMS scheme, three possible cases are considered, depending on the scheduling of the check points. In the first case, the check points are arbitrary, i.e., the test length between check points li and li+1 can be arbitrarily selected. To control the FMS scheme, like the SS scheme, an on-chip counter is required to count the applied test vectors. When a check point is reached, a decoder detects the corresponding count and outputs a chk signal to enable the evaluation of a signature. Unlike a SS scheme's controller where the decoder detects only the final count, the decoder in this case must decode all the counts corresponding to the check points, and is thus considerably larger. This is the worst case in terms of hardware overhead among the possible implementations of the FMS scheme's controller.
In the second case, the scheduling of the check points follows a regular equidistant pattern, i.e., the test length between li and li+1 is constant for all i. A convenient constant is 2q, where q is an integer. To control the FMS scheme in this case, the counter required in the SS scheme is simply split into two smaller ones, say C1 and C2. C1 is a q-bit counter which counts the test length between two adjacent check points i.e., 2q. C2 counts the number of signatures to be checked. Assume the final count to be 0 for both C1 and C2. Every time C1 decrements to 0, a decoder decodes the 0 and generates the chk signal to enable the evaluation of a signature. If the signature is incorrect testing can be terminated and the CUT declared faulty. Otherwise, C2 is decremented by 1, and testing continues. When both C1 and C2 reach the 0 state, the test is complete. The hardware requirement of the controller in this case is almost the same as that for the SS scheme since the total length of C1 and C2 is the same as that of the counter used in the SS scheme, and the total complexity of the two decoders to decode the 0's from C1 and C2 is the same as that of the decoder in the SS scheme. This is the best case in terms of hardware overhead among the possible implementations of the FMS scheme's controller.
The third case lies between the first two, i.e., the check points are selected such that the test length between two adjacent check points, li and li+1, is variable but constrained to values of 2qi, where qi is an integer. In this case, counters C1 and C2 can again be used to count the applied test vectors. C1 must be of length qs, where qs =min qi. Two decoders are required. One decodes the 0 state from C1, while the other decodes the counts of 2qi-qs from C2, i=1, . . . , n-1. Every time C1 reaches 0, and C2 reaches 2qi-qs, i ε (1, . . . , n-1), a signature is checked. The hardware overhead in this case is between that of the first two cases, since the decoder for C1 detects only one count, but the decoder for C.sub. 2 has to detect n counts corresponding to the check points.
The foregoing assumes a counter for controlling the FMS scheme. A LFSR random pattern generator can be shared as a counter to count the applied test vectors, e.g., as in the BIST controller of the Intel 80386 (see: Gelsinger, P. P, "Built In Self Test of the 80386," Proc. ICCD, 1986, pp. 169-173). The FMS control implementation described above applies equally well to the case where the conventional counter is replaced by a LFSR-type counter. The split of the LFSR into two smaller LFSR-based counters, C1 and C2, will not affect the randomness of the input pattern generator if concatenable polynomials are used (see: Bhavsar, D. K., "Concatenable Polydividers: Bit-sliced LFSR Chips for Board Self-Test," Proc. Int. Test Conf., 1985, pp. 88-93).
5.0 Fault Simulation Experiments
To study the fault coverage performance of the FMS scheme, exact fault simulation of the ISCAS'85 benchmark circuits (see: Brglez, F. and Fujiwara, H., "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN," Proc. IEEE Int. Symp. Circuits and Systems, 1985, pp. 151-158) were performed with output data compaction. FIG. 8 depicts the hardware model used, where "IPG" is an input pattern generator implemented with a LFSR, "ODC" is a output data compactor, and "MINSR" is a multiple input nonfeedback shift register that performs space compaction. Single stuck-at faults were assumed. In the case of the SS scheme, an 8-bit primitive LFSR was used as the data compactor. For the FMS scheme, 8 signatures were checked at equidistant check points, and each was generated by the 8-bit LFSR, i.e., k=8 and n=8. In terms of fault simulation time reduction, the equidistant check point scheduling is the worst of the control strategies described in Section 4.2. But the area requirement for the control of the FMS scheme in this case is the same as that required for a SS scheme. The corresponding hardware overhead in addition to that required for the SS scheme is about the size of a 2.16-bit LFSR. The total silicon area of the FMS scheme in the experiments is thus about equivalent to that of a 10.16-bit LFSR, as opposed to an 8-bit LFSR for the SS scheme.
Table 1 shows the exact fault coverage before signature analysis (the "NC" column), and the coverage with the SS and the FMS schemes, respectively for a test length of 1,024 random vectors. In all cases, the coverage of the FMS scheme is either the same or very close to that of the no-compaction case, and higher than that of the SS scheme.
TABLE 1______________________________________Circuit No. Fault-Coverage (%)Name Fault NC FMS SS______________________________________C432 562 99.24 99.244 99.11C499 732 98.90 98.907 97.95C880 1171 95.64 95.645 95.38C1355 1820 98.64 98.640 98.13C1908 2015 94.65 94.615 93.69C2670 2781 82.65 82.659 82.05C3540 4035 93.45 93.451 93.33C5315 5982 96.23 96.230 96.17C7552 8408 93.01 93.010 n/a______________________________________
Table 2 shows the CPU time required to perform the above fault simulations. From Table 2, the CPU time required to perform the fault simulations with the FMS scheme is always close to that of the no-compaction case, which constitutes a lower bound (see: Lambidonis, D., Agarwal, V. K., Ivanov, A. and Xavier, D., "Computation of Exact Fault Coverage for Compact Testing Schemes," Proc. ISCAS, June 1991, pp. 1873-1876). In the case of the SS scheme, however, the fault simulation time is always one order of magnitude longer. In Table 2, the column "Time Savings" shows the CPU time saved from using the FMS scheme rather than the SS scheme. Here, the number of test vectors simulated is small, and the check point scheduling is the worst case in reducing fault simulation time. If longer test length, larger circuits, and optimal scheduling of the check points were considered, the fault simulation time saved from using the FMS scheme rather than a SS scheme would be even much more significant.
TABLE 2______________________________________Circuit No of Fault Simulation Time TimeName Faults NC FMS SS Sav______________________________________C432 562 2.25 6.96 48.90 85.77%C499 732 3.70 11.32 72.64 84.42%C880 1171 14.30 34.26 191.37 82.10%C1355 1820 29.39 64.54 380.36 83.03%C1908 2015 63.66 108.00 465.29 76.79%C2670 2781 202.5 361.37 124 70.91%C3540 4035 268.2 420.38 1823. 76.95%C5315 5982 419.8 841.02 499 83.15%C7552 8408 126 1865.72 n/a n/a______________________________________
6.0 Multiple Signature Analysis with a Single Reference
6.1 Basis of the Scheme
Usually, checking n signatures requires n references. These references must be somehow stored in a ROM as in the CMS scheme, or built in the SO as in the FMS scheme. However, if all the references are made identical, say all equal to 0, then only one reference needs to be stored. Thus, the hardware requirement for checking identical multiple signatures can be as small as that for any single signature scheme, and is independent of the number of checked signatures. The control of the signature checking does not result in extra hardware overhead to the conventional BIST controller if the check points are equidistantly scheduled. Having one constant reference signature for all check points is a fundamental aspect of the invention. A technique for achieving identical reference signatures that does not entail any hardware overhead nor any circuit modification will now be discussed.
6.2 Achieving Identical Reference Signatures
Assume a set of random vectors is applied to a fault-free CUT such that a fault-free sequence of length l results. Assume the checking of n k-bit signatures at the predetermined check points l1, l2, . . . , ln (these check points can be arbitrary). For a fault-free sequence, if it is assumed that each of the sequence bits is statistically independent and equally likely to be 0 or 1, then the probability for each signature to be equal to a given value, say equal to 0 . . . 0, is 2-k. Thus, for such a arbitrary fault-free sequence, the probability that all signatures be identical and equal to a specific value is 2-nk. If the value of the single reference is unrestricted, i.e., the signatures are allowed to be any one of the 2k possible values as long as they are identical, then this probability becomes 2-(n-1)k. This probability is very small for practical values of n and k. Thus, in general, it is unlikely that the n signatures would be identical.
However, if there exists a choice of many different fault-free sequences, which is possible by applying different sets of random vectors to the CUT, then the probability that one of these sequences yields n identical signatures at the predetermined check points can be very high. As shown above, given one sequence, the probability is 2-nk+k. Given a choice between two sequences, the probability that at least one of the two yields n identical signatures follows a geometric distribution, i.e., the probability is 2-nk+k +(1-2-nk+k)2-nk+k. Given L possible fault-free sequences, the probability that at least one of the sequences yields n identical k-bit signatures is: ##EQU5##
The probability CL,n,k is a measure of confidence of finding at least one sequence from L sequences that yields n identical signatures. Obviously, CL,n,k →1 as L→∞. Therefore, n identical signatures can be highly probable if L can be made sufficiently large. The feasibility of this scheme rests upon how efficiently the L fault-free sequences can be obtained, as well as how large L must be, as discussed below.
6.3 Sequence Generation and Selection
As shown above, L will in practice tend to be large. Thus, successful implementation of the invention depends on the efficiency of generating the fault-free sequences by logic simulation, and of searching the sequences for one that yields identical signatures. Techniques for these tasks will now be described.
6.3.1 Efficient Generation of Fault-Free Sequences
A simple way to generate L fault-free sequences is to apply L different sets of random vectors to the CUT and choose the set of random vectors that generates n identical signatures as the test vector set. To generate L sequences, one may try L input pattern generator ("IPG") LFSRs with different feedback polynomials, or try L different seeds of the IPG LFSR. However, both of these methods imply simulating the CUT L times, each for l test vectors. Thus, the corresponding time complexity is O(lL) (disregarding the dependency of the simulation on the CUT parameters), which may become unacceptable for large l and L. A more efficient technique is presented next.
First, consider the case where the P-to-S converter in FIG. 9 is such that every input pattern to the CUT results in a single bit output, i.e., l patterns yield l output bits. Denote the fault-free output sequence by b1, b2, . . . , bl. Shifting the IPG LFSR one more time, which is equivalent to simulating the CUT for a total of l+1 test vectors, yields one more output bit bl+1. From the (l+1)-bit sequence, there exists two possible sequences of 1 consecutive bits. One is the sequence b1, b2, . . . , bl. The other is b2, b3, . . . , bl+1. These two sequences are very unlikely to be the same since the probability for the two sequences to be identical is extremely small (approximately 2-l). Clearly, shifting the IPG LFSR L-1 more times, i.e., simulating the CUT with a total of l+L-1 test vectors, yields l+L-1 output bits, b1, b2, . . . , bl+L-1. Such a l+L-1 bit sequence yields the choice of L fault-free sequences of length l. The time complexity of this generation technique is only O(l+L), which is simply a linear increase in the necessary time to generate a single l-bit fault-free output sequence.
The above method for generating fault-free sequences can also be applied to the case where the P-to-S converter is a scan chain. With a scan chain of length m, each input vector yields m output bits to compact. In this case, the IPG LFSR requires only (l+L-1)/m shifts to generate L fault-free sequences. Thus, the sequence generation time complexity is only O({l+L}/{m}) if the P-to-S is a m-stage scan chain.
6.3.2 Adequate Sequence Selection
As shown above, a fault-free sequence of length l+L-1 yields a choice of L sequences of length l. Each of the latter sequences is actually a subsequence of the (l+L-1)-bit sequence. Given a (l+L-1)-bit fault-free sequence, an efficient algorithm to search for an adequate subsequence of length l that yields identical signatures is now presented.
The following example shows the basic concept of the way in which an adequate sequence can be selected.
Example: Use the 2-stage LFSR shown in FIG. 10 to check 2 signatures. Assume the initial state of the LFSR is (00), l=8, and L=4. If l1 =4, and l2 =l=8, i.e., check a signature after every four bits being shifted into the LFSR. Given the (l+L-1)-bit sequence to compact as:
1 1 1 1 0 1 0 1 1 0 0
the eleven transient LFSR states after every shift are shown below:
(10 ) (01) (00)(10) (11) (11) (0) (00) (10) (11) (01)
An examination of the transient states shows that starting with the seed (01) the 8-bit subsequence (1 1 0 1 0 1 1 0) would yield two identical signatures at l1 =4 and l2 =8. The value of the signatures is (11). The eight transient LFSR states, starting with seed (01), when the subsequence (1 1 0 1 0 1 1 0) is applied are shown below:
(00) (10) (11) (11) (01) (00) (10) (11)
In the above example, all the transient LFSR states are pre-calculated and stored. Storing these states may require a large memory space. An efficient searching algorithm which is based on a similar idea as shown in the example, but which avoids the requirement of storing these transient states, will now be described. Assume the (l+L-1)-bit fault-free sequence is M=b1, b2, . . . , bl+L-1, where b1 is the first bit to compact. To simplify the algorithm, denote the initial seed to the signature LFSR by s0. The searching algorithm is shown in the following pseudo-procedure:
______________________________________search.process(M, L, n, k, l1, l2, ..., ln)seed = s0 = 0; l0 = 0; for(i=1 to n) do initialize the signature LFSR with seed; j = i - 1; calculate the signature si by shifting the sequence bits blj+1, blj+2, ..., blj+li into the LFSR; seed = si ; endoffor i = 1; while((the signatures s1, s2, ..., sn are not identical)&&(i ≦ L)) do for(j = 0 to n) do initialize the signature LFSR to the value of sj ; calculate a new sj by shifting bit bi+lj into the signature LFSR; endoffor i = i + 1; endofwhile if(i > L) then print "fail to find an adequate sequence"; else print the results i, the value of the signa- tures, and the signature LFSR seed that results in the identical signatures, i.e., s0 ;endofsearch.______________________________________
This search is very fast, and takes little memory. For example, when l=216 and L=22 20, the search takes only a few seconds on a Sun SparcStation™ 2.
6.4 Feasibility and Aliasing Performance of the Scheme
The magnitude of L required to ensure certain confidence for successfully using the invention (i.e. the amount of CPU time overhead required to implement the invention) is now discussed.
6.4.1 Required L vs. Aliasing Performance of the Scheme
Given n, k, and a desired confidence C of success in finding an adequate sequence, the required L can be obtained by solving Equation 10 with CL,n,k =C. Some results are shown in Table 3:
TABLE 3______________________________________L C (%)______________________________________2nk-k+1 86.472nk-k+2 98.172nk-k+3 99.97______________________________________
From Table 1, if nk-k=16, L=217 is required to ensure 86% confidence, and L=218 is required for a confidence of 98%. With nk-k=16, some examples of n, k, and corresponding aliasing probability Pat, are shown in Table 4.
TABLE 4______________________________________k n Pa1______________________________________1 17 2-172 9 2-184 5 2-208 3 2-2416 2 2-32______________________________________
From Tables 3 and 4, if L=217, one has 86% confidence of finding five identical signatures each of length 4, which corresponds to an aliasing probability Pal =2-20 ; or, with the same confidence, one can find two identical 16-bit signatures thus Pal =2-32. If L=218, the confidence goes up to 98%.
C, L and k are directly related to the desired confidence, allowed CPU time overhead, and affordable hardware area, respectively. Given C, L and k, the expected number of identical signatures can be found by solving Eqnuation 10 for n. In terms of these parameters, the aliasing probability is: ##EQU6## 6.4.2 CPU Time Overhead
The CPU time required to implement the preferred embodiment involves two aspects. One is the effort in generating the L fault-free sequences; the other is the effort spent in searching an adequate sequence among the L sequences. With the algorithm presented above, the searching requires only a negligible amount of CPU time. Thus, the major CPU time required is that of generating the L fault-free sequences, which is in fact the CPU time required for simulating the fault-free CUT to get L-1 extra output bits. Disregarding the dependency of the simulation on the CUT parameters, the required CPU time for obtaining L-1 extra output bits is proportional to L. Similarly, the CPU time for simulating a CUT to get a l-bit fault-free sequence is proportional to l. Thus, the CPU time overhead is L/l relative to the effort required to generate an l-bit fault-free output sequence by logic simulation.
Assuming an output sequence length l=220, which is not too long in practice, especially when a scan chain is used, yields 12.5% CPU time overhead for L=217, and 25% overhead for L=218. For example, with 25% CPU time overhead, there is over 98% confidence of achieving Pal =2-20 with k=8, or Pal =2-32 with k=16. Such percentages of CPU time overhead are acceptable in practice. For example, it takes only 0.2 minutes to simulate a 40,000 gate fault-free CUT with 220 test vectors. Thus, in this case, L=218 means only 3 seconds of extra CPU time. When only a fault-free sequence is required, simulation techniques based on higher-level circuit descriptions, e.g., functional or behavioral level descriptions, can be used, thus making the simulation process much faster. In some cases, if some "proven" fault-free circuits ("golden circuits") are available, the required fault-free sequence can be obtained by running these circuits.
The CPU time overhead can be further reduced by combining the logic simulation for fault-free sequence generation with the searching for identical signatures, i.e., generating a fault-free sequence and concurrently determining whether any of its subsequences generated so far yields n identical signatures. Once such a subsequence is found, the process terminates. In this case, the average CPU time overhead can be significantly reduced, since the average number of extra output bits that must be generated is much smaller than L. This average number is 2k-k, which is the mean value of a random variable characterized by a geometric distribution with parameter 2-nk+k [10]. For the cases shown in Table 4, where nk-k=16, the average CPU time overhead can be reduced to 6.25% from 12.5% or 25%.
6.5 Special Case: k=1
A special case arises for k=1, which yields Pal =2-n if n 1-bit signatures are checked. In this case, the hardware requirement is only a 1-stage LFSR. Moreover, the storage of the single reference required in the general case can be avoided if the state of the 1-stage LFSR at each check point is directly used as a go/nogo signal. The case where k=1 can be considered as a minimal hardware requirement for signature analysis.
When Pal =2-n is desired, from Table 3, L=2n is required to ensure 86% confidence, or L=2n+1 for a confidence of over 98%. Theoretically, with a 1-stage LFSR, the invention can achieve arbitrarily small aliasing if L is sufficiently large. Assuming k=1 and l=220, achieving the typical aliasing probability of 2-16 requires 6.25% CPU time overhead for 86% confidence, or 12.5% overhead for 98% confidence. Similarly to the discussion above, the average CPU time overhead in this case is only 3.125%.
7.0 Experimental Results for Achieving Identical References
To verify the feasibility of the invention, 150 experiments on the ISCAS'85 benchmark circuits (Brglez et al, supra) were performed. In the experiments, a multiple input nonfeedback shift register ("MINSR") was used as the P-to-S converter shown in FIG. 9. The signatures are checked at equidistant check points. This makes the corresponding hardware requirements for the control of checking multiple signatures as small as that for the control of any single signature scheme. In the experiments, for each given set of n and k, three trials were performed with each of the circuits. Table 5 shows the experimental results when nk-k=16:
TABLE 5______________________________________ Log2 of the number of extra output bitsCircuit n = 17, n = 9, n = 5, n = 3, n = 2,Name k = 1 k = 2 k = 4 k = 8 k = 16______________________________________C432 15.79 14.94 16.19 15.87 17.01C499 14.07 15.29 15.72 14.65 15.08C880 16.49 16.15 14.46 15.61 16.27C1355 14.07 15.29 15.72 14.65 15.08C1908 15.86 15.57 16.36 15.81 16.08C2670 16.95 15.36 15.64 16.21 14.06C3540 15.46 14.50 17.22 15.08 17.26C5315 14.38 17.21 16.49 16.68 15.60C6288 16.79 15.35 15.64 16.23 15.34C7552 16.98 16.87 16.67 16.50 15.72averages 15.68 15.65 16.01 15.73 15.75Average = 15.76______________________________________
As shown in Table 5, to find 17 identical 1-bit signatures, yielding Pal =2-17, requires the generation of 215.68 extra output bits on average. To find 2 identical 16-bit signatures thus yielding Pal =2-32, requires 215.75 extra output bits on average. Theoretically, the average number of extra output bits that must be generated is 2nk-k =216. In comparison, the last row of Table 5 shows that the average number of the required extra output bits over the 150 experiments is 215.76. This result is very close to the theoretical expectation. If l=220, 216 extra output bits translates into a CPU time overhead of only 6.25%, and 215.76 represents a CPU time overhead of 5.29%.
8.0 A General Technique to Reduce m
The foregoing techniques for generating fault-free sequences can be used not only to select an adequate sequence but also to reduce the number of references in the FMS scheme, i.e., to make 1<m<n, as will now be explained.
The FMS scheme eliminates the one-to-one correspondence between the references and the checked signatures. This makes it possible to can use fewer references than signatures, i.e., m<n. In this case, n-m of the n references used in the conventional case are made identical. To do so, the techniques described above for fault-free sequence generation can be used. A suitable technique for adequate sequence selection will now be described. Assume the (L+l-1)-bit fault-free sequence to be M=b1, b2, . . . , bl+L-1, where b1 is the first bit to compact. To simplify the algorithm, denote the initial seed to the signature LFSR by s0. For given m and n, the searching algorithm is as follows:
______________________________________search.process(M, L, m, n, k, l1, l2, ..., ln)seed = s0 = 0; l0 = 0;for(i=1 to n) do initialize the signature LFSR with seed; j = i-1; calculate the signature si by shifting the sequence bits blj+1, blj+2, ..., blj+li into the LFSR; seed = si ; endoffor i = 1; while((the number of identical signatures is smaller than n-m)&&(i ≦ L)) do for(j=0 to n) do initialize the signature LFSR to the value of sj ; calculate a new sj by shifting bit bi+lj into the signature LFSR; endoffor i = i + 1; endofwhile if(i > L) then print "fail to find an adequate sequence"; else print the results i, and s0, s1, s2, ..., sn ;endofsearch.______________________________________
9.0 Augmentation of the FMS Scheme's Reference Set
It is possible to use the FMS scheme while making the reference set also include members that do not correspond to any of the reference signatures that would produced at the n check points by a circuit in the absence of one or more faults. This insertion of such extra "dummy" members into the reference set could could lead to a situation wherein m would exceed n. There could be situations in which such augmentation of the set of references would result in a preferred implementation of the SO.
10.0 Alternatives to LFSRs for Computing Signatures
The previous sections have all assumed that the structure which computes the signatures from a CUT would be a LFSR. However, there exist many other known structures for compacting CUT test output responses, e.g., cellular automata, counters (ones, edges, transitions) etc. The latter alternative structures may be linear or non linear and circuit specific or independent. The FMS and similar reference signature schemes described in the preceding sections can be applied regardless of the type of compactor used to generate the signatures. The above analysis has assumed LFSRs, which are currently the most commonly used type of compactors for testing digital integrated circuits. Nevertheless, alternative compactors may be preferred in some applications.
As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.
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This Agreement of Partner Expulsion is entered into among the partners of a partnership whereby the majority of the partners agree to expel an existing partner. This agreement is used to set out the terms and conditions of the partner's expulsion in the event the original partnership agreement does not provide for terms relating to the expulsion of a partner. It contains essential information relating the purchase of the expelled partner's interest, indemnification and a noncompetition agreement. This document contains standard clauses as well as opportunities to customize the agreement to fit the needs of the parties.
This Agreement of Partner Expulsion is entered into among the partners of a partnership whereby the majority of the partners agree to expel an existing partner. This agreement is used to set out the terms and conditions of the partner's expulsion in the event the original partnership agreement does not provide for terms relating to the expulsion of a partner. It contains essential information relating the purchase of the expelled partner's interest, indemnification and a noncompetition agreement. This document contains standard clauses as well as opportunities to customize the agreement to fit the needs of the parties. AGREEMENT OF PARTNER EXPULSION THIS AGREEMENT OF PARTNER EXPULSION (the "Agreement"), is made as of the ____ day of __________, 2_____. B E T W E E N: (hereinafter referred to as "Partner A") OF THE FIRST PART, -and- (hereinafter referred to as "Partner B") OF THE SECOND PART, -and- (hereinafter referred to as "Partner C") OF THE THIRD PART WHEREAS Partner A, Partner B and Partner C commenced doing business in a partnership (the "Partnership") under the business name ____________________ (the "Business"), having its principal place of business at __________________________ [Instruction: insert street address, city, and state] pursuant to a Partnership Agreement dated the ___ day of ___________, 2____ (the "Partnership Agreement") a copy of that agreement is attached as Exhibit _________; AND WHEREAS Partner A and Partner B are desirous of expelling Partner C from the Partnership; AND WHEREAS the Partnership Agreement fails to provide for provisions relating to the expulsion of a partner; AND WHEREAS Partner A and Partner B have mutually agreed to expel Partner C from the Partnership and Partner C has agreed to be expelled from the Partnership pursuant to the terms and conditions contained herein. © Copyright 2013 Docstoc Inc. 2 NOW THEREFORE THIS AGREEMENT WITNESSES that in consideration of the covenants and agreements herein contained, the parties hereto covenant and agree with each other as follows: 1. RECITALS The above recitals are true in all respects and form an integral part of the Agreement as if they had been recited again herein. 2. EXPULSION OF PARTNER A. Partner A and Partner B hereby acknowledge and agree that effective immediately, Partner C shall cease to be a partner of the Partnership upon the execution hereof this Agreement, after which Partner C shall: i. Have no authority to enter any obligation on behalf of the partnership. ii. Have no right to participate in the management and conduct of the Partnership's business. iii. Be relieved of the duty of loyalty and care to the Partnership and the partners therein with respect to any matter arising after __________ [Instruction: insert his or her] expulsion. B. Partner A and Partner B hereby mutually agree that the Partnership shall continue in full force and effect with the expulsion of Partner C on the same terms and conditions contained in the Partnership Agreement. 3. STATEMENT OF DISSOCIATION The partnership shall prepare a statement of dissociation stating that Partner C is expelled from the partnership on the expulsion date and shall file the statement in the office of the Secretary of State [Instruction: add if appropriate, "and record a certified copy of the statement in the county recorder's office in each county where the Partnership owns real property.] Immediately after filing, the partnership shall provide a copy of the statement of dissociation certified by the Secretary of State to Partner C. 4. SALE AND RELEASE OF PARTNERSHIP INTEREST A. Partner A, Partner B and Partner C hereby agree that Partner A and Partner B shall purchase from Partner C his/her _______ (___%) percent of partnership interest in the Partnership for the sum of __________ ($______) Dollars (hereinafter "the buyout price") and upon Partner C receiving such sum, hereby sells, transfers and releases to Partner A and Partner B his/her partnership interest in the Partnership, all of Partner C's rights and interests in the assets and good will of the Business. B. Partner C hereby releases Partner A and Partner B and their respective spouses from any and all manner of claims and causes of action which he/she may now have or in the future have against Partner A, Partner B or the Partnership, and their heirs, successors or assigns in respect of the Partnership or the Business or otherwise and shall deliver releases to Partner A and Partner B in the form attached hereto as Schedule "A." © Copyright 2013 Docstoc Inc. 3 5. OFFSETS Any amounts owed by Partner C to the Partnership shall be deducted from the buyout price determined in accordance with Paragraph 4.A. 6. RELEASE OF LIABILITIES Partner A and Partner B hereby assumes all outstanding liabilities of the Business and agrees to indemnify and save Partner C harmless from all claims and causes of action which may be brought against _________ [Instruction: insert him or her or it] in respect of any outstanding liabilities of the Partnership and or Business but, only to the extent that such liabilities and creditors have been disclosed to Partner A and Partner B prior to the execution of this Agreement and are reflected in the financial statements and accountings of the Partnership. 7. INDEMNIFICATION The Partnership shall indemnify and hold harmless Partner C against all Partnership liabilities whether incurred before or after the expulsion date. Indemnification shall not extend, however, to any Partnership liability incurred after the expulsion date that results from Partner C entering a transaction with a third party under the circumstances specified in Corporations Code Section 16702. [Comment: this Corporations Code Section is valid only for California. If you are using this form in any other state you should determine which statute is particular to your state.] 8. NONCOMPETITION AGREEMENT [Comment: this section is optional] In consideration of the payment of the buyout price, Partner C agrees that after the expulsion date ___________ [he or she or it] shall not, either directly or indirectly, carry on or engage in, either as owner, part-owner, manager, operator, employee, salesman, agent, or other participant, a business similar to that carried n by the Partnership in _________ [Instruction: specify location, e.g. Los Angeles County, CA] for so long as the Partnership, or any person deriving title to the good will of the business from the Partnership, carries on a like business in that county. 9. DISCLOSURE A. Access to Partnership Books and Records. Until payment of the buyout price in accordance with Paragraph 4.A. is made, and thereafter for so long as is reasonably necessary, the Partnership shall provide Partner C, or _________ [Instruction: insert his or her or its] legal representative, access to books and records pertaining to the period during which ___________ [he or she or it] was a partner. This right of access shall include the opportunity to inspect and copy books and records during ordinary business hours. The partnership may impose a reasonable charge for copies. © Copyright 2013 Docstoc Inc. 4 B. Supporting Documents. The partnership shall furnish Partner C with the following documents within ________ ( ) days of the date of this Agreement: i. A statement of partnership assets and liabilities as of the date of expulsion; ii. The latest available partnership balance sheet and income statement; if any; and iii. An explanation of how the amount of the buyout price for Partner C's interest was calculated. 10. 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This Agreement shall be governed in accordance with the laws of the State of _____________ applicable therein. G. This Agreement may be executed in several counterparts, and in that event, each counterpart shall be deemed to be a complete original and be enforceable without reference to any other counterpart. All counterparts taken together shall constitute one and the same document. H. Any modification of this Agreement will be effective only if it is in writing and signed by the party to be charged. This Agreement shall be read with all changes in gender, number and grammar as may be required by context. I. The language contained herein shall be deemed to be that approved by all parties hereto and no rule of strict construction shall be applied against any party hereto. © Copyright 2013 Docstoc Inc. 5 J. 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June 27, 2013
Marion Jones Bowling
DURHAM - Mrs. Marion Jones Bowling, age 98, died Tuesday evening at her home.
Born July 23, 1914 in Lawrenceville Virginia, she was the daughter of the late Lambert Charles and Lilly May Amis Jones. A resident of Durham for most of her life, she was the oldest living member of Watts Street Baptist Church, where she had belonged to Circle 3. She was also a member of the Croasdaile Country Club, the Croasdaile Garden Club, and the Croasdaile Women's Golf Association. Her husband, Dr. Howard X. Bowling, died December 30, 1970.
Surviving are two cousins, Betty Amos Gallop of Virginia Beach, Virginia, and Thomas Tilley of Durham. In addition to her husband and parents, she was also preceded in death by her sister, Roselyn Lawrence.
Funeral services will be held Friday at 11 a.m. at Watts Street Baptist Church, Rev. Diane Hill officiating. Burial will be in Maplewood Cemetery. The family will receive friends at the church from 10 to 11 a.m.
Pallbearers will be Mike Curry, Josh Curry, Thomas Tilley, Mike Salguero, Kenton Cobb, and Jeff Jeffrey.
In lieu of flowers, memorials may be made to the church, 800 Watts Street, Durham, North Carolina 27701
A special thanks is extended to her home caregivers, Rilla and Peggy, Thomas and Frances Tilley and Mike and Odessa Curry for their help given and kindness shown to Mrs. Bowling.
Howerton and Bryan is assisting the family with arrangements.
Online condolences may be submitted to http://www.howertonbryan.com/, select obituaries.
Dr. Emmett Mason Partin
DURHAM - Dr. Emmett Mason Partin, 81, passed peacefully from this life to his eternal life on Monday, June 24, 2013 at Duke Medical Center. Emmett was born to the late Kenneth and Rachel Blackwood Partin on August 1, 1931.
Emmett was keen on education and personal development and, in his late thirties, chose to pursue his doctorate in Spanish/Education at the University of Pennsylvania in Philadelphia. He was conferred his PhD by the University in 1973, after having published his book and abstract, "The life, educational ideas, and work of Jose' Vasconcelos (1882-1959)". Dr. Partin's work on Vasconcelos was a multi-lingual, pervasive, and unique contribution to the fields of linguistics and Hispanic education in its day. Emmett was a Professor at Temple University and the University of Pennsylvania and later employed by the State of Delaware in the court system.
Emmett is survived by his nephew, Daniel Keith Ollis and wife, Sharon Renee, of Durham; his niece, Donna Ollis Quintana and husband, Glenn Gilbert, of Concord; and his brother-in-law, Carroll C. Ollis of Durham; grand-nieces, Lauren Quintana, Kathleen Quintana, Kristin Mcghee; and grand-nephew, Seth Mcghee.
The family will receive friends 11 a.m.-12 p.m. Friday at Lakewood Baptist Church, 2100 Chapel Hill Road, Durham, where funeral services will follow at 12 noon. Rev. Johnny Hewett will officiate. Interment will be held at Maplewood Cemetery in Durham. Dr. Partin's arrangements are being cared for by Hall-Wynne Funeral Service, Durham. Share your condolences at www.hallwynne.com.
Douglas "Doug" Clark Sanford
DURHAM - Mr. Douglas "Doug" Clark Sanford, 66, of 300 Cascade Falls Lane, #106, died Friday, June 21, 2013 at the VA Medical Center. His service will be conducted at 1 p.m. on Friday, June 28, at Bell Yeager FWB Church, 128 E. Cornwallis Rd. Interment will follow in Glennview Memorial Park.
The family will receive friends on Friday at the church from 12-1 p.m., one hour prior to the service. There is a public viewing at Burthey Chapel on Thursday from 1:30-8:30 p.m.
Arrangements by Burthey Service.
James (Jim) Edward Orbich Sr.
PITTSBORO — James (Jim) Edward Orbich Sr., 68, of Pittsboro, NC, went to heaven on June 25, 2013. Jim was born on October 10, 1944 in Washington, PA to the late Joseph and Cecelia (Calasky) Orbich. He married Judith (Sherbondy) on November 23, 1963, who preceded him in death on October 26, 1984.
One of his biggest joys of life was his grandkids. When he was in better health, he loved taking them on special trips. Once he was unable to travel, he loved spending time and talking with his family. He will be deeply missed and never forgotten. We are at peace knowing he will no longer suffer and is in a better place. At his request, there will be no service.
He is survived by his children, Kimberly Kay of Chicago, IL, James and his wife, Andrea, of Pittsboro, NC, Pamela of Troutman, NC; grandchildren, Kristie Kay, Tommy and his wife, Brittany, Travis, Jacob, Luke; great grandchild, Parker; sisters, Valerie (Leo) Steiner, Audrey (Peter) Pollice, Madeline (John) Chopp, Joanne (Richard) Szyjko, Janice (Dale) Hawkins; sisters-in-law, Janet (James) Gibson, Margaret Orbich; and many nieces and nephews.
He was preceded in death by his wife, parents, brothers, Joseph and Edward; sisters, Irene Trnavsky and Connie Zigler; brothers and sisters-in-law, John and Susan Sherbondy, Peter Pollice, Matthew Trnavsky and Harry Zigler.
Dr. William Phillip (Phil) Webster, DDS, MS
CHAPEL HILL - Dr. William Phillip (Phil) Webster, DDS, MS, passed away at his home on June 21.
He was born in Mt. Airy, N.C., April 26, 1930.
"Dr. Phil" retired in 1991 as Professor Emeritus in the Schools of Dentistry and Medicine at the University of North Carolina in Chapel Hill. He has been a resident of Punta Gorda since 2001. He was a master farmer, an inveterate optimist, and a lover of offshore sailing. He was a teacher, practitioner and researcher. Some of his distinguished accomplishments include forming the dental clinic at the North Carolina Memorial Hospital and starting the two-year postgraduate program to give dentists intensive hospital-based training in treating persons who have a combination of medical and dental problems. At his retirement celebration one of his colleagues acknowledged Phil by saying he had made more significant, unique and novel contributions to biomedical science than most distinguished professors. One of his first accomplishments was the registry of all hemophilic patients in North Carolina, southern Virginia, eastern Tennessee, and most of South Carolina. As a dentist with an exhaustive knowledge of coagulation and bleeding disorders, he knew all the hemophilic patients in the states mentioned above and they knew him. This logically led to the establishment of one of the largest and best known Comprehensive Hemophilia Diagnostic and Treatment Centers in the U.S. The center is well known all over the world. He was a member of many distinguished dental societies, and served as chief consultant to the North Carolina Chief Medical Examiner. He also served on many national and international advisory committees concerning blood coagulation. He made 28 presentations to national and international meetings regarding hemophilia and published more than 100 abstracts, book chapters and articles. He oversaw more than 3.8 million dollars worth of research funds.
He is survived by his loving wife, R. Ellen Brown; his twin brother, Dr. Paul D. Webster III; paternal half-sister, Paula Graham; four sons, Chris G., Mark A., Ronnie M. and Phil, 12 grandchildren, as well as three great grandchildren. He was preceded in death by his parents, Paul D. and Edith Gilbert Webster; and his first wife, Marlene Martin Webster.
A celebration of life will be held at a future time in the Chapel Hill, N.C. area. Arrangements are by Royal Palm Memorial Gardens in Punta Gorda. Gifts in memory of William P. Webster can be made to the Medical Foundation of North Carolina, Inc., Attn: Brock Matthews, Director of Development, 880 Martin Luther King Jr. Blvd, CB #7565, Chapel Hill, NC 27514. Please write "UNC Hemophilia Treatment Center Fund" in the memo line and Phil's name.
Wanda Brown Allen
TIMBERLAKE - Wanda Brown Allen passed away Sunday, June 23, 2013 at Hospice at the Meadowlands. She was born in Durham Co to the late Charles and Bessie Brown. She was preceded in death by a granddaughter, Lauren Gower.
Shortly after graduating from Northern High School in 1966, she married William Allen and they had a son William Allen Jr. (Butch). She worked several places including West Durham Lumber Co. and Durham County Tax Office. She retired from the tax office on disability in the late 90's and lived with her son for many years. After having a stroke in 2009, she lived with Kenny and Sandra Senter who cared for her.
She is survived by her son, Butch and wife, Margaret; two grandchildren, Melissa and Breanna Johnson; brother, Joseph Brown and wife, Melissa.
A graveside service will be held 3 p.m. on Friday at the New Mausoleum at Woodlawn Memorial Park. Family will receive friends at the mausoleum prior to the service beginning at 2 p.m.
The family is being assisted by Clements Funeral Service, Inc. in Durham. Online condolences may be made at www.clementsfuneralservice.com.
Pecolia Smith Blackwell
HURDLE MILL — Mrs. Pecolia Smith Blackwell, age 94, of Hurdle Mills, NC, passed away on Sunday, June 23, 2013.
Mrs. Pecolia Smith Blackwell is survived by six children, Catherine B. Vincent (husband, Nathaniel) of Hurdle Mills, NC, Rubie B. Barnes (husband, Jerry) of Hurdle Mills, Howard B. Blackwell of Hurdle Mills, NC, Danny K. Blackwell (wife, JoAnn) of Glen Burnie, Maryland, Donald D. Blackwell of Hurdle Mills, NC and Patricia B. Ramsey of Hurdle Mills, NC; and one daughter-in-law, Linda Gant Blackwell of Hurdle Mills, NC
Mrs. Pecolia Smith Blackwell is also survived by five sisters, Eliza S. Jones of Goldsboro, NC, Lillie Mae Tapp of Greensboro, NC, Synobia Gilmore of Greensboro, NC, Hassie M. Torain-Hester of Sedalia, NC, and Hattie Eva Vanhook (husband, Lawrence) of Cedar Grove, NC. She is also survived by 15 grandchildren, 36 great grandchildren, and two great-great grandchildren in addition to a host of additional relatives and friends
The funeral service will be conducted Friday, June 28th at 2 p.m. at Lattisville Grove Missionary Baptist Church in Hurdle Mills, NC. The service will be conducted by Rev. George Crews III, and the burial will follow in the Union Grove Baptist Church Cemetery in Hurdle Mills, NC.
Visitation will be Thursday at the Hester, Whitted and Daye Funeral Home from 1 p.m. until 7 p.m. The wake will be at the church Friday from 1 p.m. until 2 p.m. Hester, Whitted and Daye Funeral Service is in charge of the services for Mrs. Pecolia Smith Blackwell. Funeral information can be accessed and online condolences can be sent to the family via the internet at HWDFuneral.com.
Treva King Crissman
SANFORD — Treva King Crissman, 92 of Sanford, died Tuesday, June 25, 2013, at Brookshire Nursing Center in Hillsborough, NC.
Mrs. Crissman was born on March 18, 1921 in Moore County to the late Charles Clifford King and Mae Fergerson King. She was a member of Pocket Presbyterian Church. Mrs. Crissman was preceded in death by her husband, Glenn Crissman; sisters, Zelda Blue and Shirley Quinn; and brothers, Blain King and Richard King.
Surviving relatives include her daughter, Sally C. Sloan and husband, Wayne of Durham; a sister, Betty Prim of Carthage; and two grandchildren, Shelia Duncan and husband, James, and Larry Sloan Jr and wife, Jan; and five great grandchildren.
A funeral service will be held Friday, June 28, 2013, 11 a.m. at Pocket Presbyterian Church with Rev. David Dudley presiding. Burial will follow in church cemetery. The family will receive friends following the service in the church fellowship hall.
Condolences may be made at www.bridgescameronfuneralhome.com.
Arrangements by Bridges-Cameron Funeral Home, Inc.
Benjamin Gibbs "Beno" Philpott
LEXINGTON - Mr. Benjamin Gibbs "Beno" Philpott, 60, died Wednesday, June 26, 2013 at the Hinkle Hospice House.
A memorial service will be held at 11 a.m. Friday, June 28 at Grace Episcopal Church, by the Revs. Dr. Tom King and Bonnie Duckworth.
The family will receive friends following the service in the Church Undercroft.
Mr. Philpott was born June 13, 1953 in Davidson County to James Alvin Philpott Sr. and Helen Gibbs Philpott. He was a 1971 graduate of Lexington High School, a 1975 graduate of Washington and Lee University and a 1978 graduate of the Washington and Lee School of Law. He served as Editor of the Washington and Lee Law Review and was a member of Phi Kappa Sigma. A retired attorney, Mr. Philpott was a member of the Davidson County Bar Association, a former member of Lexington Kiwanis Club and former President of the Davidson County Museum of Art. He was a member of Grace Episcopal Church, where he served as a Junior Ward of the Vestry and volunteered with the youth. He was renowned for his singular golf swing.
He is survived by his wife, Deirdre Gordon Philpott of the home; his son, Harry Westall Philpott of Lexington; his brother, James Alvin Philpott Jr. and wife, Judy, of Lexington, KY; his sister, Martha Philpott King and husband, Tracy, of Durham; and many nieces, nephews, family and friends who loved him dearly.
In lieu of flowers, memorials may be made to the Davidson County Library, 602 S. Main Street, Lexington NC 27292, Grace Episcopal Church Youth Programs, 419 S. Main Street, Lexington NC 27292, Cancer Center of Lexington, P O Box 1817, Lexington NC 27293 or to Hospice of Davidson County, 200 Hospice Way, Lexington NC 27292.
Online Condolences may be made at www.davidsonfuneralhome.net.
Sarah Frances Crosby Reeves
SANFORD - Sarah Frances Crosby Reeves, of Sanford, NC, passed away on Wednesday June 26, 2013. She lived a life of extraordinary love, grace, and determination and will leave behind many friends and family who are better people for having had the good fortune of knowing her.
Sarah Frances was born May 29, 1919 to the late David and Pearl Myers Crosby of Chester, SC. After winning the Miss North and South Carolina Pageant in high school, she graduated from Brenau University in Gainesville, GA in 1939. Her interest in the promotion of higher education began at Brenau. She served as a longtime Trustee at both at Brenau and Methodist University.
While taking graduate-level courses in Theatre at the University of North Carolina, Chapel Hill, she founded the UNC chapter of Alpha Delta Pi Sorority. She also met Charles M. Reeves Jr., of Sanford. Their marriage of 55 years began in 1940. Shortly thereafter, they moved to New York City so that she could pursue a career in film and radio and modeling, a career cut short in 1942 when her husband left to serve in the US Navy through the end of World War II.
In 1950, she and Charlie moved to Reeves Ridge Farm where she lived the rest of her full and varied life. Farming included her legendary "egg route," raising chickens, ducks, geese, one goat, pigs, horses and cattle, above all, lovingly tending to her family. She also became very involved in the community, supporting land conservation, the arts, and education in Sanford and across the state.
Throughout her life, she had great passion for the arts. Mrs. Reeves was a long-time trustee for the North Carolina Museum of Art and received appointments to the North Carolina Arts Council. She served on the North Carolina Symphony Board and was president of the Art Society of the North Carolina Museum of Art. She was also active in the Suzanne Reeves Literary Club, the Lee County Historical Society, the North Carolina Museum of History Associates. She was an active member of Saint Luke United Methodist Church.
Mrs. Reeves was widowed in 1995 and remained on the farm until her death.
Though she became blind some 15 years ago, she continued to feed her mind at every opportunity. She read voraciously and challenged all who visited her to speak their minds with candor and defend their beliefs without reservation. She was gracious in sharing her own love of life with all who came through her door.
Survivors include four children and their spouses, Terry and Sarah Reeves of Raleigh, David and Lou Reeves of Hendersonville, Suzanne and Frank Brooks of Raleigh, and John and Margaret Reeves of Durham. Surviving grandchildren and spouses include Jimbo and Elizabeth Parrott, Dave Reeves, Josh and Hillary Parrott, Rachael Reeves, Sarah Madeline Reeves, Caroline Reeves, Rebekah Reeves, and Mercer Reeves, as well as six great-grandchildren.
The family is indebted to the devoted care of Sharon Bush-Todd, Donecia Hart, Ethel Peakes, Michelle Donaldson, Becky Johnson, Ron Kelly, and James Todd.
In lieu of flowers, the family wishes that memorials be sent to Saint Luke United Methodist Church, 2916 Wicker St., Sanford, NC 27330; Boys and Girls Club of Sanford, PO Box 227, Sanford, NC 27331; or the charity of your choice.
The memorial service will be held at Saint Luke United Methodist Church on Friday June 28, 2013 at 11 a.m.
Online Condolences may be at www.rogerspickard.com.
Arrangements are by Rogers-Pickard Funeral Home.


text:
VU Women lose the battle of the boards in overtime loss at Cincinnati StateFebruary 2, 2013
CINCINNATI, Ohio – Despite a 20-point, 17-rebound performance by freshman Ashley Hawkins, the Vincennes University Women's Basketball Team dropped a 73-65 overtime decision at Cincinnati State Saturday afternoon.
Rugged interior play led to Hawkins going to the line 16 times and she hit 14 of her free throw attempts. Fourteen of her 17 boards were on the defensive end.
VU (8-15) also got 12 points from sophomore Zhanna Chukhrii and nine each from freshmen Shelby Parmer and Chelsea Jellison. Freshman Deborah Martin had eight points.Cincinnati State's Desiree Ash had a game-high 24 for the host Surge.
The Trailblazers won the battle behind the arc as Jellison drained three treys and Chukhrii had a pair of 3-pointers. Freshman Maggie Snider added a 3-pointer as well, as VU outshot Cincinnati State 6-2 from long range. But the Surge outrebounded the Trailblazers 47-37 (including 24 offensive rebounds for Cincinnati State) and went 23-for-34 at the line while VU was 17-for-23 at the stripe.VU will be idle until Saturday, Feb. 9, when the Trailblazers head to Olney Central for a 6:30 p.m. (Vincennes time) game that will be followed by the VU Men's Basketball Team taking on Olney Central at 8:30 p.m.


text:
Large beach house,steps to beach and restaurants
|Per week:
|$1,300 - $1,850
|Pets allowed:
Bedrooms: 4
Bathrooms: 2
Sleeps: 8
Type: Home
Pets allowed: Yes
Internet: Yes
The house is a "Key West" style home with beautiful lush landscaping. Enjoy the tropical paradise of your private garden with your own putting green, and driving cage in your own backyard. The home has two bedrooms upstairs with queen-size beds in each. There are two bedrooms downstairs with two twin-size beds in one and a fun bunkbed with desk in the "kids room". Of course, there are games, video games, and DVDs for the kids to enjoy. Each bedroom has their own TV for their personal viewing. The living room has vaulted ceilings, new stylish décor and a new 57-inch TV. Enjoy cooking in our remodeled kitchen wih it's maple cabinets and slate countertops.
It is a two minute walk to the beautiful white sands of Indian Rocks beach and two blocks from the IRB boat ramp and dock leading to the Intracoastal Waterway. It's also one block from the IRB city hall, library and city park where you'll find lighted tennis courts, basketball court, skateboard park, and playground equipment. Many great restaurants and bars within walking distance.
About the owner
Owner Profile
Availability Calendar
|Jun 01 2014
|Aug 16 2015
|1 Week
|Aug 17 2014
|Dec 13 2015
|1 Week
|Feb 01 2015
|Apr 30 2016
|1 Week
|May 01 2015
|May 31 2016
|1 Week
|Check In: 4 p.m. Check Out: 10 a.m.
|Lodging tax: 12%
|Deposits: Security Deposit: $300
|Payment Options: Cashier's Check, Mastercard, Money Order, PayPal, Personal Check, Visa
- 2 Queen Beds
- 4 Twin Beds
- 1 Crib
- Air Conditioning
- Bikes
- Heating
- Parking Included
- Balcony
- Deck
- High Speed Internet
- Patio
- Beach Chairs
- Full Kitchen
- Linens Provided
- Pet Friendly
- Beach Towels
- Hardwood Floors
- Outdoor Shower
- Alarm Clock
- DVD Player
- Microwave
- TV (Cable/Satellite)
- Blender
- Dishwasher
- Oven
- Telephone
- Ceiling Fan
- Hair Dryer
- Radio
- Toaster
- Charcoal Grill
- Ice Maker
- Refrigerator (Full)
- Coffee Maker
- Iron
- Stove
- Washer/Dryer
- Bicycling
- Restaurant
(<1 mile)
- Kayaking
(1 mile)
- Shopping Area
(5 miles)
- Basketball Court
(<1 mile)
- Tennis
(<1 mile)
- Sailing
(1 mile)
- Grocery Store
(6 miles)
- Beach
(<1 mile)
- Boating
(1 mile)
- Miniature Golf
(3 miles)
- Golf
(8 miles)
- Ocean
(<1 mile)
- Canoeing
(1 mile)
- Parasailing
(3 miles)
- Casino
(10 miles)
- Park
(<1 mile)
- Fishing
(1 mile)
- Aquarium
(4 miles)
- Amusement Park
(25 miles)
- Playground
(<1 mile)
- Jet Skiing
(1 mile)
- Live Entertainment
(5 miles)
- Zoo
(25 miles)
Reviews (17)
Reviews for this vacation home rental in Indian Rocks Beach, Florida
Anissa Patrick
Dayton, Ohio
Perfect choice
June 12, 2015
We are so glad we chose this home for our stay in Florida. We traveled with our parents who are older and don't ever go anywhere. They both felt very comfortable and loved the home. The decor is impeccable! You will love being so close to the beach and the warmth of the home as well. We will be back!
Inna Isakovich
IRB House
April 17, 2015
The property offers all you might need for large family (or two) with 4 bedrooms, large dining area, fully equipped kitchen etc. The property located in very private neighborhood just couple minutes walk from the beach. Highly recommended!
Deanna Larson
Rhode Island
winter respite
March 14, 2015
The location of the house was within a few short blocks of a beautiful white sand beach. The deck was surrounded by lush green palms that provided a cool breezy spot out of the sun. We had plenty of space for 4 people to have individual time as well as togetherness. Thanks for a fun vacation.
Ken Gaines
Erie, PA, USA
Very Comfortable and Accomodating
January 5, 2015
We arrived later than expected but were still met by Randy the owner. After being assured that we could gain entry Randy left. Everything that we needed for a good time (even for infants) was somewhere in the house. The house was secluded and private while in the midst of a pleasant neighborhood but very near one of the many public beach access points.
Janet Permar
Peachtree City, GA USA
Home away from home
December 11, 2014
My family enjoyed this lovely home for the three nights we were there. The house is in a great area, close to the beach, dining, and, important for us, an Episcopal Church. The owners were wonderful to deal with, and the house was beautifully decorated, clean, and inviting. Would recommend to anyone....and hope to return.
George & Dawn Campbell
Awesome House!
August 18, 2014
We loved our stay at your house! This was our first time to rent a house vs a hotel & we will definitely be renting again. I loved the privacy of the landscaping & the space of the house inside was great! Everyone had plenty of room to move around & I was surprised how well stocked the house was with towels, toys, books & even laundry soap! It's all those little things that add up & made our stay wonderful! Thanks again, Dawn
sheri mims
Live Oak, fl
Ultimate in living away from home
June 10, 2014
Our stay at this house was a blessing. Even though it is a 2-3 min walk to beach. It don't matter the comfort of this home is amazing. The owners are amazing too. What you see in pics is exactly what you get. And you don't need anything for beach, chairs ,toys, bikes,umbrellas whatever it's there for you and it's totally fenced with a lil putting range adult or kids. What a pleasure this property is. Baby equipment too car seats cribs ect. Love this place and the memories of it. Don't have to worry about only 1 car parking friends can visit without having to find parking. So much more. Warning- Don't risk saying no to this property. No more searching for me from now on for indian rocks beach stay. All beaches are convenient at this location.
Luc Laroche
Caledonia, ont canada
Indian rocks beach (great vacation)
March 19, 2014
This home was everything it said it would be. Large private home an oasis of pleasure!
Donald Kessler
Somerset, KY
Awesome Home Indian Rocks, close to Beach!
October 18, 2013
This home is immaculate inside and out. 4 Bedroom, 2 bathroom home that provides an amazing family vacation spot. We loved the putt putt golf in the back yard and the beautiful landscaping. Highly recommend this if you needing a place in this area
Jim & Marilyn I.
St. Cloud, FL USA
Do NOT overlook this one!
August 1, 2013
You will not be disappointed staying in this lovely home. It is very tastefully decorated, is fully equipped with anything you could possibly need., and only 2 blocks to the beach. All the lush landscaping truly makes it feel like a private retreat..
Todd Hampton
Gainesville Ga
July 29, 2013
We enjoyed our stay very much. We are from the area and have a lot of family that was able to come visit. Very nice kitchen and living area. It was close to the beach and restaurants. The house looks to be set up for families with young children. Looks to be a lot of activities for kids.
jacqueline hansen
April 8, 2013
The perfect place to relax and enjoy. Quiet residential street just steps away from the beach. A hidden gem.
Gail Gagnon
Toronto, Ontario, Canada
Gagnon Family Spring Training Vacation
March 31, 2013
We rented this beautiful home for our home base to attend the Toronto Blue Jays spring training games. The house was more than what we expected. We had plenty of room for 7 people. Many amenities including a laundry room. Very close to the beautiful beach, 2 short blocks away. Many fine restaurants, Guppys, Keegan's and TJ's to mention a few within walking distance. The only thing disappointing to us was the BBQ. We love to BBQ but it was too small and charcoal therefore never used by us. Overall all was great and we would not hesitate to rent again.
Chicago, IL
Wonderful & Luxurious Home
July 15, 2009
While I'm sure there are other great homes one the beach, this home is gorgeous and affordable to rent. We thoroughly enjoyed our time there. The house is just as beautiful as your photos show it to be. It had all the accommodations necessary and then some. We enjoyed playing put-put in the backyard and the beach umbrella was quite handy. I called it my dream beach house. Ha! We really appreciate you sharing this gorgeous house with us and I hope to return again! (PS- Check out the guest book at the house, the restaurants/bars people suggest are GREAT!)
Dawn Reublin
Lake Mary, FL
Wonderful Beach House!!
May 28, 2009
We stayed at this beach house for the Memorial Day Weekend. It was just a short walk to the beach. You enter the house, and there is just this relaxing sensation. You can tell the owners really care about their house. It was wonderful! I would highly recommend this house if you are looking for something quite. We hope to stay there again.
Orlando, FL
Great Vacation Home!
May 24, 2009
Our stay in this home was absolutely wonderful! The home is comfortable and spacious....it truly felt like a 'home away from home.' With small children, I often have a hard time finding vacation rentals that can accomodate us but this home was definitely kid-friendly and had just the right set-up to meet our needs. The outside shower was great and the upstairs patio made for a great place to eat amongst the beautiful gardens. Every room has a tv which was definitely a plus....especially with kids who all want to watch something different. :) The beach access featuring restrooms and showers was very close and the area had many attractions for people of all ages to enjoy! We really couldn't have been happier! Thanks Maria!
Matthew Cotter
Tampa, FL
Great house, great deal
January 7, 2009
Our family spent a wonderful Christmas holiday at this beautiful home at Indian Rocks. My parents and their friends walked for miles each morning on the beach and we all met many friendly locals at the surrounding restaurants. From this location we easily made day trips to Clearwater, St. Pete and Tampa. All in all, we came away very happy indeed.
The was a pleasure staying at this house. Close to beach and convenient to other attractions. We fell in love with the house and didn't want to leave. The putting green was a nice touch. We definitely will be staying at this house again. Thank you so much. It was absolutely fabulous.
-jessica, plant city, FL (firstname.lastname@example.com)
Beautiful home - very inviting and spacious. Appealed to the entire family-even the kids. Great location and so close to the beach. We had a wonderful time and will be back!
-Claudia Ellett, Decatur, GA (cpe67@hotmail)
Fantastic vacation rental - great location near the beach, extremely nice furniture, well kept, etc. Great communication with owner. Highly recommended for a relaxing FL vacation.
-Stu, New Rochelle, NY
First class accomadations in quiet, residential neighborhood. All the amentities in a beautiful home. About a short block to the beach. Highly recommended! Would definitely rent again next Spring break!
Anonymous, Indian River,MI
Stayed here in early March and the house was as breath-taking as the sunset. Very short walk to the beach. It makes for a great quiet laidback vacation. Wish I owed the house, my wife wants one just like it. I will be back. Larry
-Larry Knight, Dayton, OH (firstname.lastname@example.com)
My brothers and I just finished a week in Tampa and resided in this wonderful home. It was a very roomy, classy place and we all had a great and comfortable stay. The attention to detail and the quality of furnishings is incredible. May I recommend you treat yourself to something special while in Tampa and stay at this home just a few yards from the beach.
-Jeff KNIGHT, Louisville, Ky (jknight@premierhomecareinc)
Great furnishings, multi-car parking and views of the sunset from the back deck made this an enjoyable getaway. Very easy, short walk to the beach. We look forward to returning.
-Geoff Yothers
Fantastic! The place really exceeded our expectations. The perfect accomodations to get away and just relax. Everything we needed was there or was close by. Very classy and comfortable decor.
-Roger, Arlington VA
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