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Showing 1-24 of 40 items found in Sports & Gaming
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Airtastic Playland
A fun and exciting play land offering 10 inflatable play structures, four party rooms and two age-appropriate play areas.
All Spoked Up
All Spoked Up has the best variety of kids, cruisers, road, mountain, fixed gear and BMX bicycles, along with the highest quality and best price service/rep.
Aurora Skate Center
Skate to the sounds of Top 40 music. The skate center also features special live organ music dance sessions.
Blackberry Oaks Golf Course
This 18-hole course is par 72.
Buena Vista Golf Course
Buena Vista is a par 32, nine-hole golf course with a driving range, pro shop and snack bar. Open seven days a week during the season, weather permitting.
Chasers Laser Tag
Join in a game of state-of-the-art laser tag.
Chicago Golf and Tiki Tees
Located at 210 SOUTH POINTE COURT, DeKalb Illinois 60115. Chicago Golf and Tiki Tees course commands some of the finest views of Dekalb open space and trails. The facility features a challenging 9-hole championship golf course. Its beautiful, mature and lush foliage and trees complement the manicured greens, tees and fairways. Combined with its exceptional course design, golfers of all skill levels return time and again to play. There is also a Club House, Tiki Bar for outdoor events, and indoor banquet hall for up to 160 guests.
Country Lanes
Good old-fashioned family fun.
Edgebrook Golf Club
This public course has tree-lined fairways and a hilly terrain. There is a creek and lake that come into play on six holes, and out-of-bounds stakes on just about every hole.
Fox Bend Golf Course
Fox Bend offers a challenging and scenic tour of streams, ponds, willow trees and elevation changes. This highly regarded course has played host to several tournaments and qualifiers.
Fox River Games Paintball
Bring a group of friends to play a round of paintball at Fox River Games. Open play or "walk-on" play is recreational play for all ages (age restrictions) and skill levels. Play as an individual or play in groups. Typically we are open every weekend Saturday and Sunday and during the summer we operate on Wednesdays and Fridays too. Please check our website for our operating schedule and specific hours of operation.
Funway Entertainment Center
Illinois' largest family entertainment center. Year round: bowling, bumper cars, roller skating, arcade, lazer tag and Rock-n-Roll mini golf. Seasonal: western trails miniature golf, go-karts, batting cages, soccer cages, jumpshot, Water Wars and bumper boats.
Hollywood Casino Aurora
Hollywood Casino Aurora has all of the newest and hottest slots. Denominations ranging from 1 cent to $100 including multi-denomination machines. One blockbuster hit after another, plus find all traditional favorites, popular themes and progressive machines that deliver big pay outs, plus the best variety of table games and Poker Room.
Kane County Cougars Baseball at Fifth Third Bank Ballpark
Minor league, Class A, Chicago Cubs affiliate. Games and events April-Sept. 14,000 seats, parking for 10,000. Easy access from I-88. Perfect for concerts, corporate outings and more.
Luigi's Pizza and Fun Center
Enjoy the fun here that includes laser tag, an arcade room and great pizza.
Mill Creek Golf Club
This 18-hole championship golf course, featuring wildflowers and elevated tees, offers spectacular views of the Fox Valley region.
Naperbrook Golf Course
Naperbrook Golf Course is an 18-hole links-style course featuring rolling hills, native prairie grass and an ever-present breeze. The course offers a ten-acre driving range, separate teaching tee, 10,000 square-foot practice green and versatile clubhouse.
NIU Convocation Center
Northern Illinois University's 10,000 seat Convocation Center is a $36 million multipurpose facility that hosts a variety of events such as concerts, family shows, theatrical productions, commencement ceremonies, job fairs, trade shows and NIU Huskie Division I athletic events (basketball, volleyball, track, gymnastics and wrestling). The NIU Convocation Center hosted a total of 200+ events per year.
Northern Illinois University
Come tour the Northern Illinois University, catch a show preformed by their Theatre or Dance department, or explore one of their Art Galleries. There is much to do on campus including their new Anthropology Museum, an Observatory, the Huskies Den or take in a game! Their Museums are free to visit, some fees may apply for shows or School of Music Concerts. There is never a dull moment on campus!
Northern Illinois University Convocation Center
Northern's 10,000 seat Convocation Center is a $36 million multipurpose facility that hosts a variety of sporting events and live entertainment. The Convo features a NCAA-level indoor track, large-scale event/activity space, a full basketball court, an additional practice gym, and storage facilities. The Convo generally hosts athletics such as basketball, volleyball, track, gymnastics and wrestling. Meetings, conventions, and concerts are also popular events at the Convo.
Northern Illinois University Sports (NIU Sports)
The Northern Illinois University Huskies play in the MAC Conference and have a diverse athletic department. Their many sports teams include: Men's football, baseball, basketball, golf, soccer, tennis and wrestling, while their women's teams include: Basketball, cross country, golf, gymnastics, soccer, softball, tennis, track & field and volleyball.
Oak Club of Genoa
This picturesque, 18-hole watered course winds through wooded and lowland areas along the meandering Kishwaukee River. Oak Club is rated among the region's top 20 courses by Chicagoland Golf.
Ogee Golf & Country Club
Ogee features a nine-hole course.
CITY:Paw Paw
Penny's Place
Blackhawk Restaurant Group has created four brands in Illinois--- all with the same contemporary style, comfortable design, and tempting menu-- but each with its own unique personality. We offer a warm, contemporary and comfortable setting for adults to enjoy smaller plates, sweet treats, gourmet coffee and tea, along with beer and wine. We are your neighborhood place to play Illinois' newest slot and video poker games. Come in and experience a new kind of fun!


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Aldi, the discount supermarket chain, says it is hiring across the state and will interview manager trainee candidates on Jan. 30 at its Halfmoon store.
The jobs pay $25 an hour, the company said. The event runs from 7 a.m. to 7 p.m. at the store at 1681 Route 9.

subset: commoncrawl


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Thursday, October 3, 2013
The public will get a chance next week to express what should or should not happen to Goat Island — the roughly 30-acre island in the Sampit River between Front Street and East Bay Park.
SGA Architecture, the design firm selected to develop the plan for the island, will hold a public hearing Tuesday.
The meeting will "allow the local community to present ideas to be considered for the master plan," the notice states. "Presenters may wish to bring photographs or sketches to illustrate proposed concepts, but anything left with the reviewers will not be returned."
SGA's task is to provide a land-use plan to property owner Jerry Blackmon who has said he may donate 20 of the 30 acres if he likes what will be done with the island.
The 20 acres or so to be donated is estimated to be worth about $900,000, and such a plan should be a positive for the city and the land owner, who has asked for assurances the municipality will not seek commercial development of the acreage, such as condos, which he seems not interested in having on Goat Island.
The property does not have water, sewer or electricity, so such development would be costly.
Soils maps show five acres are wetlands and five acres could have walking trails, nature watch platforms and picnic areas.
It could be a good buffer to minimize the visual effects of commercial operations located to the south.
The meeting begins at 5:30 p.m. Tuesday at Georgetown City Hall.
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Traditionally, a DJ's mixer has been the nerve center of his rig, and its power and flexibility has grown over the years as DJ culture has moved more and more to the forefront of the music scene. We've come a long way from the early days of mixers cobbled together from what you could find a your local electronics store, that were basically nothing but two faders for the left and right turntables and, if you were lucky, a crossfader for quick cuts. Modern DJ mixers have added massive amounts of EQ, heavy-duty DSP for a huge bank of FX, even software control that ties into packages like Traktor or Serato. So what used to be a simple choice has gotten much more complex.
DJ mixers can be mostly broken down into two categories: scratch (or battle) mixers, aimed at DJs with serious turntable skills who practice techniques like scratching, beat juggling and drumming and club mixers aimed at DJs who work more with segues, beat-matching and harmonic mixing. Many modern mixers also have built-in loop sampling and triggering for doing live, on-the-fly remixing.


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The Tyler 5 Piece Nursery Set is the perfect solution for parents looking for stylish and affordable furniture for their baby's nursery. The set features a 4-in-1 convertible crib , with a toddler conversion rail included, an open changer that comes with a changer pad, and a 3 drawer dresser that is perfect with the collection. The crib will grow with your child, easily converting into a toddler bed, day bed and full-size bed (rails sold separately). The 3 drawer dresser and changer provide ample storage for your baby's things.
Crib, Changer, Dresser
Toddler Rail included
4 Level Mattress support
Available in Espresso and White
Crib Specs:
Assembled dimensions: 56.625 x 29.625 x 42.375"
Interior crib dimensions: 52.5 x 28.125"
Assembled weight: 42.5 lbs
Slat strength: 135 lbs
* Made in Taiwan
Changer Specs:
Assembled dimensions: 35.875 x 17.125 x 39.125"
* Made in Taiwan
Dresser Specs:
Assembled dimensions: 33.5 x 17.625 x 29.625"
* Made in Taiwan


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Anthony Schultz
Transmission: Spring 2013April 25, 2013
Jump into Spring with a new Transmission. A montage of pure street skating for Spring 2013 featuring Jimmy Carlin, Schultz, Dicola, & Frecks.
Active Behind The CatalogMarch 26, 2013
Active Ride Shop goes behind the catalog in Miami, FL with $lave Rider Anthony Schultz & Insight Flow Anthony Pshebelski.
Double Rock: Prime CutsMarch 06, 2013
Thrasher Double Rock montage featuring $lave riders Pat Burke & Anthony Schultz.
Afternoon in the Park: Anthony Schultz | TWSJanuary 14, 2013
Anthony was the kid that ripped around the local park when he was just 14 with a deep bag of tricks, nailing everything he tried. Now he's all grown up and can leap tall grass gaps with a single bound. Watch him do his thing one afternoon in our park.


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Later this summer, our girls will be going on a trip with their grandparents. We will be separated for eleven days, which is a lot of time when you are 5 years old. And when you are the mother of two five year olds. (And especially when you are the grandparents of two five year olds.)
While our girls are super excited about their trip and talk about it endlessly, there is a tiny bit of anxiety at the thought of such a long separation. One girl in particular has been asking if she can take a picture of us with her. She is worried she will forget what we look like.
Angel Child, Dragon Child is about a Vietnamese family who immigrate to the United States, but have to leave their mother behind for lack of money for her fare. Ut is given a gift by her mother -- her picture hidden inside a small matchbox. It is a way for Ut to remember her mother until she can be brought to the U.S. I bet you can guess how the book ends.
But onto to the matchbox photo project...
This was a fun and easy craft to complete with my girls. Simply cover an empty matchbox in decorative paper using a glue stick. We took a selfie on my phone for one matchbox and printed out a previously taken photo of their dad for the other box. My computer has an option to print photos in a "contact sheet" form, which turned out to be the perfect size. We cut the photos to fit and glued them to the inside of each matchbox. One of my girls wanted to add ribbon, so we used packaging tape to stick a small pull tab to the inside of one box.
When it's time for my girls to leave on their trip, I'll be sure to tuck a little gift inside. Cash, candy, or maybe a little pebble with a red painted heart on it.


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Various venues
Until Sat Jan 3
Time Out rating:
Not yet rated
Time Out says
Thu Jan 3 2013
Calling all princess fans: Rodgers & Hammerstein's Cinderella is coming to Broadway this winter for the first time (it was originally written for television and aired in 1957 starring Julie Andrews). Expect songs "In My Own Little Corner" and "Ten Minutes Ago," as well as a few modern twists—after all, this version of the classic tale was imagined by playwright Douglas Carter Beane, the creative mind behind Broadway's Xanadu and Sister Act. Popular Great White Way actress Laura Osnes (South Pacific, Anything Goes) plays the title role and we hear that princess parties will be offered in conjunction with the show. Ages 4 and up.
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Good morning to you! I thought it would be fun to start off the week with a bang. Well now not literally a bang but you know what I mean. Do you remember my latest makeover giveaway not that long ago? Well it turns out that the winner of the makeover has decided to take a break from blogging so she ended up not doing her makeover.
With that said, It's makeover giveaway time again! The latest makeover I have worked on was last week when Operation Beautiful received a face lift in anticipation of the "Book" launch that is coming out in August.
Now onto the details
I wanted to create a little more excitement on how to enter into this contest instead of just the traditional – sign up thru RSS. I have come up with a number of ways you can enter into this contest in hope of winning the makeover. The different ways are listed below.
How To Enter:
- Become a new email subscriber and automatically get an entry on draw date. Note that only verified subscribers count (you will receive a verification email). (+1 entry)
- Leave a comment listing your "FAVORITE" Olympic sport. (+1 entry)
- Post on your "FACEBOOK" page.
- Tweet about the giveaway and include @zestycook and the link to the giveaway in the tweet. (+1 entry)
- Earn an extra chance to win by linking back to this post on your own blog (if you have one). (+1 entry) (please email me if you link back)
The Rules:
- Please only 1 comment entry / person (please enter a valid email address). Your email will be kept private and never given/sold to third parties.
- The winners will receive 10 hours of Blog Consulting/Design Makeover. ( It usually turns out to be a few more hours but I am more than happy to fulfill the obligation.
So let me know what you think and tell me your favorite Olympic sport in the comments below! A random generator will be used to pick the winner. Contest will end at 5pm EST March 5th, 2010.
Now I hope you have a great start to the week and get really excited about the giveaway. Past makeover giveaways have a been a huge success so I would like to keep the tradition going. I will be keeping tabs and dropping reminder hints over the next week or so to enter but until then have a fantastic Monday.
Take care


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The Clean Water Act requires state adoption of water standards
for designated uses, such as for drinking water, fishing,
protection of aquatic life, swimming, irrigation or industrial
purposes. Total Maximum Daily Load (TMDL) studys are to
be conducted if water segments/bodies fail to meet one
or more standards due to pollutants such as nutrients and
pesticides. A TMDL study identifies both point and nonpoint
sources of pollutants and uses monitoring and computer
modeling to determine how much each pollutant source must
reduce its contribution to assure the water quality standard
is met.
Voluntary programs and existing federal, state, and local
authorities can be used to implement TMDLs. A Region 7 EPA
web site further summarizes the TMDL
issues for the Heartland Region. State administered TMDL
programs are also Web accessible (Kansas, Nebraska, Iowa, Missouri).
Return to top of
A cooperative program consisting of the
USDA Cooperative State Research, Education, and Extension
Service and the Land Grant Colleges and Universities.
- a Regionally-Based National Network -
The USDA is an equal opportunity provider
and employer. Partners in the Heartland Regional Initiative
are also equal opportunity providers and employers.
- This
material is based upon work supported by the National
Institute of Food and Agriculture, U.S. Department of
Agriculture, under Agreement No. 2008-51130-19526.
- This
material is based upon work supported by the National
Institute of Food and Agriculture, U.S. Department of
Agriculture, under Agreement No. 2008-51130-19526.
Photograph by Tom Schultz, Department of
Natural Resource Ecology and Management, Iowa State University
Web site by Iowa State University Extension
IT :: Login


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The formula of geological blocking often used to estimate coal reserve is defective in evaluation of precision because the premise to use its formula is that the parameters
U.S. Coal Reserves 2005 U.S. Demonstrated Coal Reserve Base (millions of tons) The U.S. Demonstrated Coal Reserve Base is an estimate of the tonnage of economically
The reserve life is an estimate based only on current production levels and proved reserves level for the countries shown, In the Kingdom of Coal; An American Family .
This additional tonnage has been included in the mine plan as 'Run of Mine' but is not included in the coal reserve estimate. The company delayed completion of its PFS in
The updated study confirms Titan's coal proven reserves stands at 5 million metric tons (MT) which is just a fraction of the whole 123 million MT resource and reserve figure
Traditional procedures and methodologies used to estimate the coal reserve base have utilized historical mining recovery factors and applied them throughout coal regions to
The Coal Reserve estimate for Vlakvarkfontein was prepared by Mr. JJ Lotheringen Pr Eng (Ukwazi). Mr. Lotheringen is a member in good standing of the Southern African
2009-10-9 · currentestimate The status and/or impact of the modifying factors on the Coal Reserves A declaration as to whether or not the Coal Reserve estimate is JORC
Australia-listed Gloucester Coal on Thursday upgraded the reserve estimate for its Middlemount joint venture coal project in the state of Queensland by 68% to 96 million
Mr Barker accepts responsibility and accountability for the Underground Coal Reserve estimate documentation under the Code. Refer to detailed Doyles Creek JORC •
Germany: In 2004, without explanation, Germany downgraded its estimate of proven hard coal reserves from 23 billion tons to 0.183 billion tons,
1 WESTERN CANADIAN COAL CORP. Management's Discussion and Analysis The following information, prepared as of February 14, 2008, should be read in conjunction
(SAMREC) Code, the new coal reserve estimate by the end of 2001 comes to 34.4 billion tons or 62% of the previous amount. Given the present rate of output of297 Mt
What is so important about the maiden 274 million tonne thermal coal JORC Reserve is that it is amendable to open pit mining. The estimate, which was prepared by Echelon
Bandanna release new coal reserve estimate Thu, 2 Feb 2012 9:45am BANDANNA ENERGY LIMITED (BND) BROADCAST INFORMATION Dr Ray Shaw PDF Download
" Initial Coal Reserve estimate in upper (P1) seam of 26.3 Mt Mine plan currently allows 10 year life and sales at approximately 2Mt pa DFS on track for completion in June
COAL RESERVE EVALUATION The coal reserves and coal resources on tracts of land are often placed as collateral for loans or a part of a mining venture which requires
Gloucester Coal Ltd has upgraded its coal reserves and resource estimates. Gloucester has increased its reserves estimate around 31 per cent, from 57.2 million tonnes (mt)
Future coal production, peak coal, logistic model, historical reserve and resource assessments 2 1 Introduction There are generally two different points of view on coal in
Its reserve is equal to ten times China's current says the production potential of Xinjiang's unexplored coalfields is too large to estimate. Zhang says Xinjiang coal
The total Mineral Reserve Estimate is 20.7 M proven t (Mt) of Product (Low Ash) Coal. Mineral Reserve estimate considers only the first phase of the project development
• Contains "Coal reserve estimate for areas with high potential for coal development" at 762 million tons of coal • At 16 millions tons of production per year, this reserve
Caution: coal reserve estimates affected by static terms like "today's technology" and "economically recoverable" may not apply tomorrow. Original Coal Resources
years' worth at current production rates. So it would seem we're immune from any disruption that might occur in the coal market. This reserve estimate, however, is


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Fresh off teammate Aleksandra Wozniak's win to put Canada up 1-0 at the Fed Cup, it was up to Eugenie Bouchard to keep the momentum going. The two Montrealers were hoping for a sweep on Saturday and after Wozniak's win over Serbia's Vesna Dolonc, Genie was hoping for the same success. She got it.
Facing Jovana Jaksic, Bouchard rolled, winning the match 6-1, 6-0 and giving Canada a 2-0 over Serbia in their first-round tie in the World Group II.
The action continues on Sunday as Serbia will need to win all three of their matches to defeat Canada. It definitely will not be easy as Bouchard starts off the day against Vesna Dolonc while Aleksandra Wozniak will face Bouchard's Saturday victim, Jovana Jaksic.
Should Serbia win both singles matches, they could take their first-round matchup over the Canadians in the doubles draw against Gabriela Dabrowski and Sharon Fichman. Against the duo, the Serbs will go with the team of Aleksandra Krunic and Nina Stojanovic. But one step at a time.
Up 2-0, the Canadian women have control over Serbia but are expected to take this duel one match at a time.
We will see what happens on Sunday in Montreal.


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Teresa Rodríguez is co-anchor of Univision's primetime award-winning weekly newsmagazine, "Aquí y Ahora" (Here and Now). As one of the country's leading Hispanic female journalists and the first Hispanic female to host a national newscast, the 20-year veteran delivers award-winning investigative and consumer news coverage on a number of important issues facing U.S. Hispanics, and conducts high-profile interviews, including former heads of state, newsmakers, politicians and celebrities. In addition to her role on "Aquí y Ahora," she also hosts a special weekly segment on Univision's national newscast "Noticiero Univision" (Univision Nightly News) titled "Primer Plano" (Foreground), which offers an in-depth analysis on national and international issues. Rodríguez has been honored with numerous awards for excellence in journalism, including 11 Emmy awards for her outstanding work on television specials, investigative reports and features.
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Mike Portnoy
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Gold Member
Join Date: Oct 2005
Location: Lancaster CA
Posts: 1,298
Re: Mike Portnoy
Being a guitar player for nearly 20 years, I used to not appreciate MP. The drum tracks for DT didn't allow me to listen to the music with out it sounding off time and lacking normal structure. It sounded very mechanical. I didn't realize just how much talent it took until recently.
During my guitar days, I would listen to (and still do) to many of the shreading, technical guitarists of the 80's. Namely Paul Gilbert, Yngwie Malmsteen, Vinnie Moore, Steve Vai, Jason Becker, Marty Friedman and many others.
People who were not musicians, specifically guitarists, could not truly understand the natural gifts that these people had to be able to play like that. I practiced for 20 years and still cannot even come close to those guys.
I took up drumming about 2 years ago after working with drum machines. Due to my understanding gained for the instrument while programming, it made sense to give it a try.
I do not play the guitar (except to goof around) any longer and now appreciate playing the drums. Therefore, I now am amazed by Portnoy. I have one of his instructional dvds and can watch it over and over. He is now my Yngwie and Paul Gilbert.
My friends who are not musicians do not care for DT at all. They just cannot get into it although they love heavy metal and hard rock. But my musician friends and brother, who has been studying Petrucci for 3 years, love them for what they are able to do. I now listen to them almost every day, and enjoy them thoroughly.
I know that I don't have the natural talent to be a great musician. It just isn't in my genes. I do enjoy learning what I can from the masters and trying to incorporate just a bit into my playing.
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After today's session, one participant made an insightful observation: the process I teach for making effective data visuals is very similar to the editing process for the written word. When I paused to think about it, the parallels are striking. Here is a sample:
- Make your point crystal clear. When possible, state it up front.
- Remove things that are ancillary or detract/distract from the core message.
- If you can say the same thing with fewer words (or visuals!), do so.


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Additionally through our J1 waiver blue print we are able to minimize the amount of time it takes to file your J1 waiver application to claim one of the 30 opportunities.
When you retain our firm we will prepare all the required documents and respond to all requests made by the government to remove one more headache from your busy day:
We file a fully prepared J1 waiver application that fulfills the State Health Departments requirements.
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What happens when a woman who's ignoring you watches you get into a Lamborghini?
Gold digger prank
Recent Headlines
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Blagojevich Wants Full Court Appeal
Blagojevich is hoping the full court will overturn more counts.
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Shooting Death Victim's Brother Charged with Murder
The Sangamon County State's Attorney has charged the older brother of a Springfield teenager shot and killed last week with murder.
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Most of the state's been getting a break from heavy rain over the past few weeks, but that could be a problem pretty soon.
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Illinois' economy is still steadily growing.
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Ill. Senate Taking Up Plan to Spend $5B in Federal Money
The Illinois Senate is expected to vote on the measure today.


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- Filed Under
STARKVILLE - Mississippi State fans can still expect to see John Riek's debut in a Bulldog uniform on Dec. 16.
But not anytime sooner.
Bracky Brett, MSU's associate athletic director for compliance, said Wednesday there has been no change in the Riek case. Riek, the 7-foot-2 center from the Sudan, was suspended for nine games by the NCAA to settle his off-season amateurism inquiry. The suspension was to only include regular season games, not exhibitions. ...


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VIEWS: 9 PAGES: 20 POSTED ON: 7/19/2011 Public Domain
Secure Spread Spectrum Watermarking for Multimedia Ishani Vyas CS590 Winter 2008 Agenda To explain about watermarking characteristics How to insert watermark in spread spectrum Structure of the Watermark Experimental Result Characteristics of Watermarking Unobtrusive Perceptually invisible or presence should not interfere with work being protected Robust Difficult to remove. May be removed sufficient knowledge of the process of insertion. Available of Partial Knowledge-Result in degradation in data fidelity. Watermark should be robust to Common Signal Processing-should be retrievable even if its operations are applied to the data. For example D/A&A/D conversion,resampling ,requantization. Common geometric distortions (image and video data)- Watermarks in image and video data should be immune from geometric image operations such as rotation, translation, cropping and scaling Collusion and Forgery- Watermark should be robust to collusion by multiple individuals who each posses a watermarked copy of data. Cont Watermark should be robust to combining copies of same data set to destroy the watermarks Universal – apply same digital watermark algorithm to all three media under consideration. Unambiguous- Retrieval of the watermark should unambiguously identify the owner. Why need of Spread Spectrum watermarking The previous methods have not explicitly identified the perceptually most significant components of a signal as the destination for the watermark. Key insight of this paper is that the watermark must be placed in perceptually significant regions of the data despite the risk of potential fidelity distortions. Apply watermarking in significant spectral components of a signal. How common signal transformations, (i.e compression, quantization and manipulation) affects the frequency spectrum of a signal. Watermark should be embedded in the data`s perceptually significant frequency components. But how to insert watermark into significant components of frequency spectrum without any distortions. Watermarking in frequency domain Lossy compression is an operation that usually eliminates perceptually non-salient components of an image or sound. To preserve watermark in the face of such an operation, watermark must be placed in the perceptually significant regions of the data.Data loss usually occurs among the high frequency components . Geometrics distortions specific to image and video.(Rotation,scaling ,translation,cropping)- minimum 4-9 points between the original and the distorted watermark image..Again loss of data at high frequency spectral regions of the image. Common signal distortion(D/A&A/D, resampling ,requantization, including dithering and recompression and common signal enhancements to image contrast/or color) Spread Spectrum coding of watermark How to insert the watermark into most significant region of an spectrum without such alteration become noticable. Structure of Watermark Experimental Result Watermarked image Experiment 1:Uniqueness of Watermark Experiment 2:Image Scaling Experiment3: JPEG coding distortion Experiment 4:Dithering Distortion Experiment 5:Clipping Experiment 6:Print ,Xerox or scan Experiment 7:Attack by watermarking watermarked image Experiment 8:Attack by collusion
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Good grades, extensive research experience, clinical exposure, superb references are not enough, good GRE's are often an essential ingredient in making a competitive graduate school application. If you haven't done well on standardized tests in the past, consider enrolling in the Stanley Kaplan or Princeton Review course.
It's more than a little troubling isn't it...psychologists who teach all about reliability and validity place so much weight in this course when there are so many "false negatives"! No! You shouldn't have to take this type of course. But, if I were you, I would!
Students with higher scores are far more likely to obtain interviews, and if accepted, funding! Every year, this question comes up in my summer course, "Research internship in Clinical Psychology". Having spent anywhere between $30,000 to $100,000 for their education, students refuse to fork over the last $800 to take one of these courses. What we are talking about here is spending another 1-2% more on your college education in the name of making a competitive graduate school application.
If your record is as good then with strong board scores, you may be able to gain admission into some of the very best schools in the country. However, if your GRE's are low, you will be denied an interview at any school which uses cut-offs! To my way of thinking, not addressing this possible deficit in an application, is akin to shooting one's self in the foot. Also, regarding the financial considerations, the higher your scores the more likely you are to successfully compete for fellowships. Your scores could make all of the difference. Thus, it could be a very cost-effective decision to take the course in the long-run.
If you do decide to take the course, it is important that you do it at a time when you can devote yourself fully to it. I would strongly discourage anyone from taking it during the semester. Seriously consider taking it in the summer or during a year off.
While I am on this important topic, I should mention that if you do score badly, there are ways around this. I promise to write a column on this important topic. If you do not score well, do not give up hope. There are things that you can do to obtain admission to graduate school. Also, when you become a faculty member, please fight to have the ludicrous amount of weight given to these scores changed.
Lynn Friedman, Ph.D. 5480 Wisconsin Avenue, Chevy Chase, MD, 20815 (301)656-9650
Page designed by:
Cristina Garza


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Updated: 08/18/2014 11:54 PM
Created: 08/18/2014 11:12 PM WNYT.com
By: Steve Flamisch
GREEN ISLAND – Robert Coffey, Christopher Cosgrove, and village police officer William Rice reunited Monday for the first time since the incident that brought them together.
On June 20, a vehicle rear-ended Rice's parked patrol car, crushing vertebrae in his neck. Then, the other driver allegedly attacked Rice and tried to grab his gun.
Coffey, who was on business at the time, and Cosgrove, who was driving home from work, stopped their cars and ran to the officer's aide.
"The subject was on top of Mr. Rice," said Coffey, who is also a volunteer firefighter in Ballston Spa. "He asked for help, and we pulled him off and put him on the ground."
Cosgrove recalled, "The guy was just kind of yelling, 'Shoot me. Shoot me. Shoot me,' and wanted to go to the mental health facility. I kind of said, 'We'll get you there. Just stay calm.'"
The alleged attacker, James Knowles of Troy, is charged with assault and reckless endangerment. He is out on $10,000 bail, a spokeswoman for the Albany County District Attorney's Office said.
Rice, a married father of seven who also works for the Albany County Sheriff's Department, is back on light duty while still undergoing medical treatment. He thanked Coffey and Cosgrove.
"It was nice of them to stop and help," Rice said. "I really appreciate what they did. It was a busy day that day -- a lot of people on the road -- and it's funny that, out of all that, only two people stopped."
At Monday night's meeting of the Green Island Village Board, Mayor Ellen McNulty-Ryan recognized Coffey and Cosgrove, telling them the village will be forever grateful.
"It really could have turned out differently, so I can't thank you enough for what you did," she said. Then, turning to hug Rice, she added, "And I'm really glad you're here."


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What is rickets?Rickets is a disease in children that causes the bones to develop softer than normal, resulting in muscle and bone weakness and deformity. Rickets is impaired mineralization of the growth plates of bones. The most common cause of rickets is a lack of vitamin D.
Bone Conditions Spotlight
Rickets is uncommon in the United States, but its incidence is increasing. Children at risk for developing soft bones typically possess one or more risk factors associated with low vitamin D and calcium levels. Darker skinned children require more sunlight to make vitamin D and are more at risk if sunlight exposure is limited, such as during the winter months. Children who are lactose intolerant, strictly breastfed, or have a genetic disorder affecting the absorption of vitamin D, are also at risk for rickets.
Rickets is caused by faulty mineralization in the bone-building process. Because vitamin D, calcium, and phosphorus are needed to build strong bones, a lack of these substances will affect the bones. Multiple factors can affect vitamin D levels, including the environment, genetics and diet. The environment can play a role in vitamin D deficiency because sunlight is responsible for the production of vitamin D in the body. Genetic disorders affecting vitamin D absorption can also cause rickets. Not consuming enough milk and dairy products, which are high in vitamin D and calcium, is also associated with developing rickets. Other less common causes of rickets are liver and kidney diseases and cancer.
The signs and symptoms of rickets can be constant or occur periodically. Rickets varies among individuals. Some children with rickets have mild symptoms, such as muscular discomfort, while others may have severe bowing of bones and frequent bone fractures. Fortunately, rickets can be treated with nutritional supplementation to resolve vitamin D, calcium, and phosphorus deficiencies. Lifestyle changes can reduce the risk for rickets and include receiving adequate sun exposure, eating a well-balanced diet that includes milk and dairy products, and taking all medication or supplements as prescribed.
In some cases, rickets can lead to serious bone fractures and should be treated. Seek immediate medical care (call 911) if your child's rickets includes serious signs and symptoms, such as deformity or dislocation of the joint, extensive swelling, numbness, bone protruding through the skin, or severe pain.
Seek prompt medical care if your child is being treated for rickets but mild symptoms, such as numbness, swelling, or trouble moving, recur or are persistent.
What are the symptoms of rickets?
Rickets causes softened bones and may result in a number of symptoms. The symptoms can vary in intensity from person to person.
Common symptoms of ricketsYour child may experience rickets symptoms daily or just once in a while. At times any of these common symptoms can be severe:
- Bone deformities, such as bowed legs, abnormally shaped skull, outwar... Read more about ricketssymptoms
What causes rickets?
Rickets is caused by a dysfunction in the bone-building process in children. Because vitamin D is needed to build strong bones, any disorder that affects vitamin D levels in the body will affect development of the bones. The environment can play a role in not having enough vitamin D, as sunlight is responsible for the production of vitamin D in the body. Not consuming enough milk and dairy prod... Read more about ricketscauses
How is rickets treated?
Treatment for rickets begins with seeking medical care from your child's health care provider. To determine whether your child has rickets, your health care provider will ask you and your child questions, request a sample of your child's blood, and possibly request diagnostic testing. It is important to make sure your child follows the treatment plan for rickets precisely and takes all the medi... Read more about ricketstreatments


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How to get the contents displayed inside MAC Native Dialog into a Java componet/Image
Hi All,
I am working on a java application which communicates with C++ dynamic
library. The library returns the output (in the form of textual & Picture information)
on a native MAC dialog (DialogPtr -- An opaque type that represents a dialog in MAC) which I am creating using "Resorcerer" software for
MAC. The library is purely developed using C++.
My requirement is to get the native dialog output on any of the Java
component (JPanel or JFrame etc).
The similar C++ library also exists in my project for Windows OS. We are using VC++ for reading the DLL. The library is written in the similar fashion for Windows OS also. For Windows, we are passing
CImage.getDC() : CImage is an Image class similar as BufferedImage for java. "getDC()" method returns the Handler for Device Contenxt (HDC).
By passing the above value, we are able to get the whole information of Native Dialog onto the CImage object and then we are displaying the CImage on a MFC dialog.
This is the reason, I am looking for similar solution for MAC C++ Library. This library is also drawing the information using HDC (representing CGraphPtr for MAC) on the Native Dialog.
Is there any way to get that information on any of the java component/image object?
Is there any way to map the native dialog to any of the Java AWT/swing
component directly on MAC?
Or is it possible to get the information which is displaying inside the
native dialog to be directly displayed on JPanel?
Or can we import the content of native dialog on some java Image object so
that I can draw that image on a JPanel?
Any workaround/help in this regard will be of great help for me.
Provide me any links/URLs which I can go through to solve this issue.
Thanks & Regards,
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One of the most important tools in my electronic arsenal is Microsoft® OneNote™. OneNote is an easy-to-use electronic notebook system. Heavy in features, OneNote is totally integrated with Microsoft Office. It typically can be purchased for about $100, if it … Continue reading
Monthly Archives: January 2011
Welcome 2011! This New Year the battle for the tablet computer will be joined. It has been reported that over 60 different tablet concepts are in development for 2011. If the past is any indication, advances in tablet computer technology short term should … Continue reading


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Gold Medal, Flash, Meteorite, Vapor
New bareMinerals High Shine Eyecolors!
bareMinerals High Shine Eyecolors ($16.00 for 0.05 oz.) just saw the release of six new shades: Gold Medal (pale gold), Flash (iced lilac), Meteorite (iced mocha), and Vapor (gunmetal gray), which are shown in this post, along with Ice (frosted pink) and Rose Gold (antique golden mauve).
I love the texture and color pay off of this product, but I still find the packaging a huge let down. I first reviewed these here. These apply really smoothly with insane pigmentation and a fun, foil-like finish. These wear well alone (eight hours, no creasing) as well as over a base, with other shadows, or over other eyeshadows.
- Gold Medal is a muted, antique gold with a metallic finish.
- Flash is a softened lilac with a silvery-white sheen.
- Meteorite is a cool-toned brown with subtle burgundy tones.
- Vapor is a bluish gray with a smooth, metallic sheen.
These are beautiful from first swatch to application, but there is a major drawback to this product line. The applicator/tube is a total no-go! However they managed it, when you pull the applicator out of the tube (which is a large sponge-tipped applicator), it also pulls a ton of product onto the edges. In essence, it pulls out far too much product on the applicator itself as well as leaves a lot along the rim of the tube (which just falls on your floor, lap, or wherever!).
I would recommend dumping the color into a jar or else cutting the applicator off — because it seems like the larger sponge-tip does pull much of the excess to the rim, so if you just snipped it off entirely (and used a separate brush to apply), you could leave it in the tube. (Ironically, they tout the applicator as a "convenient, quick-draw wand [that] allows for easy, on-the-go application.") I wouldn't recommend any kind of QUICK-DRAW with this unless you wanted it all over your sink.
The Glossover
bareMinerals High Shine Eyecolors for Summer Review, Photos, Swatches
|It's such a great product bottled in such a horrific way. There's just not that much excess product in the tube that you'd want to risk wasting it with the current packaging. The colors are amazing, as is the formula itself!
|Login or Register to be able to add this to your Vanity or Wishlist! Plus rate and review!


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UNH compiled 97 points in the men's giant slalom and 647 points overall to place behind Dartmouth College (725 points), Middlebury College (697) and University of Vermont (664) in the 11-team event.
Cremeno recorded the fastest time of 56:09 seconds on the second run of Friday's GS at Dartmouth Skiway to climb to second place overall in 1 minute, 54.65 seconds. McNamara completed his runs in 58.17 and 56.64 for a mark of 1:54.81 in sixth place and Ford captured eighth place in 1:55.25.
In Saturday's Nordic competition at Dartmouth XC Center, three women finished in the top 10 of the 15K mass start classic and the Wildcats took second place as a team with 91 points. Marlijne Cook (
In the men's 20K mass start classic competition, UNH took 15th, 16th and 19th place. Rody Lageson (St .Paul,
Back on the slopes of Dartmouth Skiway, the UNH women's alpine team placed four finishers in the top 15 of Saturday's slalom. Veronique Archambault-Leger (
McNamara led the men's alpine team in the slalom with a time of 1:36.76 to take 11th place. Ford followed in 13th place at 1:36.96 and Cremeno was 15th in 1:37.24
In Friday's Nordic races, Wright recorded the top Wildcat finish in sixth place of the women's 5K freestyle; she crossed the finish line in 14:34.8. Katie Miller (
McGuffin led the UNH men's Nordic contingent in the 10K freestyle in seventh place with a time of 25:49.7. Lessard was the next Wildcat to cross the finish line with a mark of 26:44.1 for 19th place and Lageson completed the scoring in 29th.
Archambault-Leger had once again finished as the top 'Cat in Friday's women's giant slalom. She was timed in 2:00.33 to take sixth place overall. Farrell and Capaul also scored for the Wildcats in 17th (2:01.92) and 19th (2:02.09) place, respectively.


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SANDY, Utah – Officials are investigating reports of hazing incidents in the Jordan High School wrestling team.
Canyons School District spokesperson Jennifer Toomer-Cook says that district officials received a tip for allegations about possible hazing incidents in the wrestling team from the parent of a student last week.
They won't say what kind of hazing or how many students may have been involved, but in accordance with policy, they turned the matter over to the Sandy City Police Dept., who is now investigating.
"They are in the early stages of taking a look at the allegations are and seeing if there are any criminal acts involved with the allegations and talk the individuals involved," said Sandy Police Sgt. Jon Arnold. "Hazing is not something that's taken lightly. It's something we need to investigate, especially if there are things that rise to a criminal act."
There is no timetable for how long the police investigation will take and no word from district officials about whether any students have been suspended or kicked off the wrestling team.


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UNHInnovation Blog
UNHInnovation Blog
Jul 11, 2014
Latest NHIRC Funded Project - Turbocam Partners with the University of New HampshireNew Hampshire Innovation Research Center (NHIRC) is excited to share that Turbocam Energy Solutions, LLC, a Dover-based affiliate of Turbocam International, is collaborating with researchers from the University of New Hampshire to evaluate the feasibility of replacing forging and casting with an additive manufactured alloy. This new technology could reduce energy use by 50... Read more
Jun 24, 2014
Seeking Partners to Commercialize One-Step Process for Synthesizing QuaterryleneWhat is Quaterrylene? Quaterrylene is an aromatic hydrocarbon (essentially a small piece of graphene) with many applications in organic photovoltaics, organic thin-film transistors, and organic light emitting diodes due to its photophysical and semiconducting properties. Despite the unique value of quaterrylene, the current availability of quaterrylene is limited.... Read more
Jun 10, 2014
Welcoming Cassie Simmons and Andrew Schmid to UNHI!UNHInnovation (UNHI) has worked with the UNH School of Law since 2010 to bring law school student interns into our office to gain technology transfer experience within a higher education setting. This year, we are very pleased to welcome Cassie Simmons and Andrew Schmid to the office. Andrew and Cassie started on June 2, 2014 and will work with us over the course of the next year. Both interns... Read more
Jun 05, 2014
Understanding The Right of PublicityWhat is the Right of Publicity? The right of publicity is an intellectual property (IP) right that many people do not know about or do not understand. This is in large part because of its recent origin and the rights afforded to individuals vary by state. The right of publicity is a right that all people have to control the commercial exploitation of their images or personas, i.e., name,... Read more
May 23, 2014
UNHInnovation Launches New Website to Centralize Commercialization of UNH AssetsThe University of New Hampshire has launched a new website, http://innovation.unh.edu, as part of an ongoing effort to open its doors to the business community and underscore its active role in technology-based economic development. "We are excited for this next step in rolling out the UNHInnovation initiative," said Marc Sedam, executive director of UNHInnovation. "We began the website redesign... Read more
- Previous Posts
- 3 of 16
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Would like to start a small racing program for low income kids in my neighborhood. I don't have the financial means to purchase equipment or the expertise in racing. Do you think sponsors and a coach can be found? What I do have is a love of cycling and the belief that these children can benefit in all aspects of their lives from the experience.
Appreciate your thoughts


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A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory resources without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find arrays for each process. The arrays are then listed in a graphical user interface (GUI). The GUI allows the designer to create memory resources, specifying the type of memory, the packing mode, etc. The designer can then drag and drop the array variables listed in the GUI onto the memory resources. Upon completion of modifying the memory allocation, the designer saves the changes illustrated in the GUI and such changes are effectuated by automatically updating the synthesis intermediate format.
1. A method of allocating memory in a behavioral synthesis tool used to design an integrated circuit, comprising:
reading a source code description associated with the integrated circuit into the behavioral synthesis tool, the source code description having at least one array;
storing the source code description as a data structure within the behavioral synthesis tool; and
using a graphical user interface to map the array to a memory to be used by the integrated circuit by modifying the data structure within the behavioral synthesis tool.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
using the graphical user interface, creating a memory resource to be used by the integrated circuit; and
using the graphical user interface, creating an association between an array with the memory resource using a drag-and-drop operation.
11. The method of
12. The method of
13. The method of
14. A computer-readable medium having computer-executable instructions for performing the method of
15. A synthesis tool that allows for interactive memory allocation in the design of integrated circuits, comprising:
a source code description file that describes functionality of an integrated circuit;
memory that stores an intermediate database associated with a source code description file of the integrated circuit; and
a graphical user interface that allows a designer to interactively allocate memory for the integrated circuit by modifying the database and without modifying the source code description file.
16. The tool of
17. The tool of
18. The tool of
19. A behavioral synthesis tool, comprising:
means for generating a synthesis intermediate format associated with a source code description of an integrated circuit; and
means for allowing a user to interactively modify memory allocation by modifying the synthesis intermediate format.
20. The behavioral synthesis tool of
21. The behavioral synthesis tool of
22. A method of allocating memory in a behavioral synthesis tool used to design an integrated circuit, comprising:
displaying, in a graphical user interface, array variables associated with a source code description of the integrated circuit;
displaying, in the graphical user interface, memory resources associated with the integrated circuit; and
assigning the array variables to the memory resources using the graphical user interface.
23. The method of
24. The method of
25. The method of
26. The method of
27. The method of
28. The method of
29. The method of
This Application claims priority to provisional application No. 60/257,923, filed Dec. 21, 2000, and entitled "Techniques for Rapid Implementation of High-Performance FPGAs from Algorithmic C Specifications."
The present invention relates generally to behavioral synthesis tools for creating integrated circuits, and more particularly relates to behavioral synthesis tools that allow for interactive memory allocation during the design of integrated circuits.
The design of complex computer hardware no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL) that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (such as clock period, number and type of data path elements, and desired number of clock cycles). Behavioral synthesis tools convert the HDL program into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
In HDL source code, arrays provide a powerful and convenient method for modeling the behavior of memories. That is, behavioral descriptions are used to manipulate groups of data in an abstract manner using arrays. These arrays are, under the control of the designer, mapped to memory. Behavioral synthesis tools automatically construct the logic to control the memory, freeing the designer to explore architectures using different memories with different characteristics (e.g., synchronous versus asynchronous, single port versus dual port), and make intelligent decisions about an appropriate implementation for a design.
An example HDL source code is shown in Table 1 below that declares three variables, a, b, and c, that are arrays. Each array contains 1024, 8-bit words. The code first declares a "subtype" to define the type of each element in the array. The code then defines a "type" to represent the array itself. Finally, the variables are declared, each variable representing an array.
Generally, the variables are accessed using loops, such as the loop shown below in Table 2. For variables that are mapped to a memory, a read or write of a variable corresponds to a memory read or write that will be implemented in hardware. When an array is mapped to memory, each element in the array is mapped to a memory location. For example, a(0) maps to address 0, a(1) maps to address 1 and a(1023) maps to address 1023, etc.
To map variables to a memory, the designer must specifically assign the variables to a memory in source code and specify the type of memory and other memory parameters (e.g., packing mode). This is accomplished using a set of HDL attributes or directives. For example, Synopsis® (tools use a "pragma" statement.
There are essentially three types of packing modes: explicit (also called absolute), packed (also called compact), and base aligned. In the explicit packing mode, the array indices are taken as exclusive addresses. Using the packed packing mode, the array indices are packed to eliminate gaps in the memory. In the aligned packing mode, the array indices are generally shifted by a power-of-two number. The aligned packing mode typically reduces the amount of hardware needed for memory address calculation (for example, by eliminating an adder or subtractor), but usually requires more memory.
After the designer designates the type of memory and packing method in the HDL source code (using pragma statements or other directives), the designer runs the source code through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the speed and area of the circuit to determine whether the current memory allocation is acceptable. If the memory allocation is not acceptable, the designer must return to an editor, re-edit the source code to change the memory allocation, and run the source code through the synthesis tool again. Such a technique for modifying the memory allocation is time consuming and inefficient. Moreover, the designer cannot easily visualize how the memory is allocated while modifying the source code.
It is desirable, therefore, to provide a synthesis tool that allows a designer to modify memory resources more quickly and simply. It is further desirable to allow a designer to readily visualize a memory map of the circuit after the designer allocates memory resources.
The present invention allows a designer to interactively change the memory allocation in an integrated circuit design without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the memory allocation easily and see the results of the new allocation without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view a memory map of the circuit to better determine whether the memory allocation is acceptable. Additionally, the designer can execute an area-versus-speed analysis, and, if the analysis is not satisfactory, the designer can further modify the memory allocation using the GUI.
In one aspect, a source code file having a description of the hardware is read into a database within the synthesis tool. The synthesis tool analyzes the source code file and generates a data structure associated with the source code file. The designer can then invoke a GUI that lists the variables from the source code, together with the size of the variables, current memory allocation for the variables, and packing mode. The designer can then interactively create new memory resources and drag and drop the variables onto the memory resources to allocate the memory interactively and without having to change the source code file.
In another aspect, the designer can interactively change other parameters associated with the memory resources, such as the memory type, packing mode, etc. Thus, rather than having to change the source code file, the designer can select a memory resource in the GUI and change these memory parameters interactively and dynamically.
In yet another aspect, the designer can view a graphical representation of a memory map that illustrates the mapping of variables to memory addresses. If the designer is dissatisfied with the memory layout, the designer can interactively modify the memory allocation to find a more satisfactory solution.
Further features and advantages of the invention will become apparent with reference to the following detailed description and accompanying drawings.
FIG. 1 is a block diagram of a system for allowing interactive memory allocation.
FIG. 2 is a detailed diagram illustrating a design flow for creating an integrated circuit using the system of FIG. 1.
FIG. 3 is an example graphical user interface for allowing a user to interactively allocate memory.
FIG. 4 is a flow diagram of a method for modifying memory allocation interactively using the graphical user interface of FIG. 3.
FIG. 5 is a flow chart of a method for displaying a memory map based on the desired memory allocation.
FIG. 6 is an illustration of a graphical user interface displaying a memory map.
FIG. 7 is an illustration of a graphical user interface wherein the user dynamically creates a new memory resource.
FIG. 8 is an illustration of a graphical user interface showing that the memory resource of FIG. 7 has been created and a variable assigned to the memory resource.
FIG. 9 is an illustration of a graphical user interface wherein the parameters associated with the memory resource of FIG. 8 are dynamically changed.
FIG. 10 is an illustration of a graphical user interface showing a memory map for one of the memory resources of FIG. 9.
FIG. 11 is an illustration of a graphical user interface displaying a memory map for another memory resource of FIG. 9.
FIG. 12 is an illustration of a data structure for a memory resource object.
FIG. 13 is an illustration of a data structure for a type of memory module.
FIG. 14 is a flowchart showing the translation of a design statement into an intermediate format.
FIG. 15 is a flowchart showing a reconfiguration of the intermediate format of FIG. 14 for a compact packing mode.
FIG. 1 shows a system 10 for generating an integrated circuit. A designer typically creates a behavioral description of an integrated circuit by generating source code file 12 using a separate editor (not shown). The source code is described generically as HDL and may be written in C, C++, VHDL, Verilog, etc. Once the source code 12 is complete, a behavioral synthesis tool 14 reads in the source code file 12 and allows a designer to evaluate and modify the circuit architecture early in the design process. In particular, the source code 12 is read into an intermediate database 16 that holds the behavioral description as a data structure. This data structure, called a synthesis intermediate format (SIF), is modifiable by the user through a graphical user interface (GUI) 18. The GUI 18 allows the designer to interactively and dynamically modify the memory allocation in the data structure. Additionally, the designer may also quickly evaluate the area and latency associated with different memory architectures. Once the designer is satisfied with the architecture, the RTL code is generated as shown at 20. Further processing is then performed on the RTL code to ultimately generate the integrated circuit. The behavioral synthesis tool 14 may be executed on any desired general purpose computer having a monitor for displaying the GUI and having any desired user input, such as a mouse, keyboard, etc.
In previous systems, in order to change the memory allocation, the designer was required to reload an editor and modify the source code 12 directly. The designer would then have to reload the source code into the behavioral synthesis tool and generate the RTL code in order to evaluate the resulting architecture. The system 10, on the other hand, allows the designer to modify the intermediate database 16 using the graphical user interface 18. Thus, the designer does not have to edit the source code to modify the memory allocation.
FIG. 2 shows a more detailed flow chart for generating an integrated circuit according to the invention. In process block 30, the designer develops the source code as already described. In process block 32, the behavioral synthesis tool 14 (see FIG. 1) reads the source code into the intermediate database 16 and generates a data structure that is changeable by the designer. When generating the data structure, the synthesis tool performs an analysis of the source code. For example, the synthesis tool searches for operators, signals, and variables in the source code and generates the data structure based on these HDL statements. Additionally, the synthesis tool searches for directives and uses the directives as defaults for the memory allocation in the data structure.
At this point in the flow, the memory allocation information is stored in the intermediate database independently, meaning the information is not yet fully integrated into the SIF. This allows the designer to interactively change the memory allocation and control when such changes are applied to the SIF. The memory allocation information is stored as a set of resources for the design wherein each resource represents a memory resource that may potentially be present in the final integrated circuit design. The resource data structure may be organized in many different ways. One possible organization is to have the following fields:
A unique identification # for the resource
A type of memory to be used for the resource
A list of variables mapped to the resource
A packing mode for the resource
A flag indicating whether the resource is external to the design
Turning briefly to FIGS. 12 and 13, the resource data structure is shown in FIG. 12. FIG. 13 shows a similar illustration for memory module type data structure wherein width represents the module word width, size represents the number of words the module can store, port names represent the read/write ports that exist on the module, area is the area of the memory module, and delay is the time it takes for that module to read or write memory.
The data structure has sufficient information to fully describe the memory resource characteristics. Using this information, the actual memory instance can be created by applying the information to the intermediate data structure at a later point in the design flow.
Returning to FIG. 2, in process block 34, the designer can interactively change he memory allocation for variables that are in the source code. That is, the source code includes variables representing arrays that are associated with memory storage (although in some cases arrays are not mapped to memory). There may be many different memories from which the designer can choose. Memory can vary in size and type (e.g., dual port memory, single port memory, etc.). Thus, in process block 34, the designer can choose which memories to use, the variables associated with those memories, the packing mode, etc. Other features of the GUI are described further below.
After the memories are properly allocated, the designer can perform an initial check to analyze the area and timing of the circuit (process block 36). This may be done, for example, by displaying an area versus latency graph that gives the designer some immediate feedback on whether the memory allocation is satisfactory. If the designer is unhappy with the area or timing, the designer can return to process block 34 to further modify the memory allocation, as shown by arrow 38. On the other hand, if the designer is satisfied with the memory allocation, the RTL code can be generated and simulated (process blocks 40 and 42). Finally, an RTL synthesis tool can perform RTL synthesis (process block 44) and the gate level design can be verified and analyzed (process block 46).
Further details are now given on how the memory allocation is applied to the SIF. After the designer is satisfied with the memory allocation, the designer directs the GUI to apply the memory allocation information to the SIF. Thus, at this point any changes the designer has made to the memory allocation are reflected in the database by modifying the independent set of resources and their field information. Applying this information to SIF involves several steps:
1. Create a memory data object representing each memory resource. This involves determining the size of the memory based on the variables mapped to the memory and the size of the variables, along with the packing mode. Also, since the original variable index may get mapped to a different memory address (based on the packing mode and the order of variables on the memory), offsets are computed for each array/index.
2. Transform all read/write accesses to any of the variables mapped to the memory resource into corresponding read/write(s) to the created memory data object in step 1. Transforming includes modifying the SIF appropriately to reflect the mapping of the original array index to the actual memory address location. This mapping is dependent on the ordering of the variables and the packing mode used. An appropriate offset is inserted for each array index access. This offset insertion is also known as address calculation. For absolute packing mode, no address calculation is needed and the original index is used as is for addressing the memory. Typically, for compact packing mode, an addition/subtraction operation may have to be inserted in SIF for address calculation from the original index (depending on whether the offset is positive/negative). Expression "Addr=idx−29" in box 164 of FIG. 10 gives an example of a subtraction being introduced as part of the address calculation for a compact mode. Finally, for base_aligned packing mode, usually, no real address calculation operation needs to be inserted, but some transformation of the original index should be performed in terms of rewiring (i.e., some high-order bits may be ignored from the index and some other high-order bits may be appended). The SIF is modified to reflect this address calculation transformation from the original array index before accessing the memory. Logical expressions relating Addr and idx in box 170 of FIG. 11 illustrate the address calculation taking place in base_aligned mode.
After these two steps are completed, the memory allocation information is fully integrated into the SIF, and further steps in the design flow include these memories as part of the actual design to be generated. For example, the RTL code is generated using the information integrated into the SIF.
FIG. 14 shows an example SIF representation for a design statement "A(i)*B(i)" before applying memory allocation information to the SIF. If the memory allocation chosen implies the arrays A and B were mapped to one memory resource (mem_ab) with compact packing mode, then FIG. 15 represents the SIF after applying memory allocation information to the SIF (assuming array A has 8 elements).
FIG. 3 shows an example of the user interface 50 for allowing the designer to modify memory resources interactively and dynamically. The user interface includes an upper pane 52 and a lower pane 54. The upper pane has a list of processes and variables accessed within those processes. These processes and variables represent the current memory allocation stored in the database 16 and are represented as graphical objects. When the synthesis tool 14 generates the data structure stored in database 16, the source code directives regarding variables and memory allocation are identified and are used as default settings for memory allocation. Using the GUI of the present invention, a designer may choose to create the source code with no directives indicating memory allocation. In such a case, the designer interactively specifies the memory allocation via the GUI.
However, in the illustrated example, the designer did include directives in the source code that are used as default settings. For example, the synthesis tool 14 identified a process entitled "Main" (shown at 56) in the source code. The array variables associated with that process are shown at 58 and include variables A, B, and C designated as "vara", "varb", and "varc". The variables are shown using a hierarchical structure at 59 typical of Windows applications. The hierarchical structure is a tree structure wherein the processes are shown at the top level and variables are shown as the leaves or sub-levels. Box 57 currently has a minus sign shown therein, which means the leaf variables associated with that process are displayed. The box 57 may be selected using a mouse pointer. If so, the minus sign is replaced with a plus sign and only the top level processes are shown. Adjacent to each variable is the array indices associated with that variable. For example, vara is an array having indices (1:6), meaning it has 6 elements in the array. The upper pane 52 also includes sub-panes entitled "size" 60, "resource" 62, "module" 64, and "packing mode" 66. The size sub-pane 60 provides the array size for each variable. For example, vara is a size 6×8 meaning it has 6 words, each 8 bits in width. The resource sub-pane 62 provides a symbolic name of a resource associated with the variables. In this case, "mem_resa" is a memory resource used for all the variables. The module sub-pane 64 provides the actual memory type for the resource mem_resa. The packing mode sub-pane 66 shows the current packing mode used for each of the variables. In the current system, there are three possible packing modes called absolute, compact, and base-aligned. Additional packing modes can be added to the system. In the current example, each of the illustrated variables is assigned a base-aligned packing mode as can be seen from the packing mode sub-pane 66. Any of the sub-panes may be removed or additional sub-panes may be added.
The lower pane 54 is used by the designer to change the memory allocation of the circuit. Thus, lower pane 54 includes details of a desired (potential) memory allocation. For example, a memory resource sub-pane 70 shows that there is currently one memory resource (i.e., mem_resa) allocated in the system. Each of the 3 variables currently assigned to that memory are shown by the hierarchical structure at 72. In the hierarchical structure the memory resources are shown at the top level and variables are shown as the leaves. Box 74 can be toggled (similar to box 57) to show only the top level of the hierarchy or the top level and leaves. The lower pane 54 also has a "size" sub-pane 76 showing the current size of the memory, mem_resa. For example, mem_resa is shown as being a size "36×8" meaning the memory contains 36 words, each 8 bits wide. A "module" sub-pane 78 shows the type of memory associated with the memory resource. An "external" sub-pane 80 shows whether the memory will be within the integrated circuit or outside of the integrated circuit. A "packing mode" sub-pane 82 provides the packing mode associated with this memory similar to packing mode pane 66. Finally, an "address range" sub-pane 84 shows the actual addresses that the variables are stored in memory (addresses are shown in hexadecimal format). Any of the sub-panes may be removed or additional sub-panes may be added.
Three buttons located between the upper and lower panes 52, 54 include a "new resource" button 86, a "delete resource" button 88 and a "view address mapping" button 90. The new resource button 86 is used to interactively create new memory resources, as is described further below. The delete resource button 88 is used to delete current resources identified in the memory resources pane 70. The view address button 90 provides a visual view of the variable mapping of a currently selected memory resource.
Three buttons are located at the bottom of the lower pane 54 and include an "OK" button 92, a "cancel" button 94 and a "reset" button 96. The OK button is used to save the memory allocation settings found in lower pane 54 to the data structure. The cancel button 94 exits the user from the window 50 without any changes to the stored memory allocation settings. The reset button 96 is used to erase the current settings in the lower pane 54 so that the designer can start anew.
FIG. 4 shows a flow chart of a method that further illustrates some of the features of the user interface of FIG. 3. In process block 110, the behavioral synthesis tool reads in the source code file. In process block 112, the behavioral synthesis tool searches through the source code to find different processes and array variables accessed within those processes. In process block 114, the processes and variables accessed within those processes are listed in the upper pane 52 of the user interface (see 56 and 58 in FIG. 3) in a hierarchical fashion so that the designer can immediately associate the variables with the processes. Additionally, the array size and current memory mappings (obtained from the source code) are also displayed in the upper pane 52. In process block 116, the user interface lists the current memory resources and variables associated with the memory resources as indicated in FIG. 3 in memory resource pane 70. The designer may also create new memory resources that were not identified in the source code file, as further described below.
In process block 118, the designer can drag and drop variables onto memory resources using a user input device (e.g., mouse, keyboard, etc.). For example, if the designer selects varc from the list of variables 58, the designer can drag that variable to the memory resource pane 70 and drop varc onto a desired memory resource. The size of the memory resource shown in the size pane 76 is updated automatically to ensure that the memory size is sufficient to handle the size of the variable. The designer can also change the memory resource parameters, such as the type, packing mode, etc. In process block 120, if the designer selects the OK button 92, the data structure stored in the intermediate database 16 (FIG. 1) is automatically updated to reflect the changes made by the designer.
FIG. 5 shows a flow chart of a method for visually displaying to the designer a memory mapping associated with the memory allocation window 50. In process block 130, the behavioral synthesis tool determines the variables associated with the memory. These variables are obtained from the memory resources pane 70 (FIG. 3). In process block 132, the behavioral synthesis tool automatically calculates address ranges associated with the variables based on the current packing mode identified in the packing mode sub-pane 82. The various addresses are automatically updated in the address range sub-pane 84. If the designer selects the View Address Mapping button 90 (FIG. 3), then a memory map illustrating the address ranges associated with the variables is displayed together with unused memory locations (process block 134). Logic may also be shown indicating how the addresses are calculated, as described further below.
FIG. 6 shows an example of such an address map being visually displayed as described in FIG. 5. The designer first selects a memory resource in the lower pane 54, which causes the resource to be highlighted as shown at 140 in FIG. 6. Then the designer selects the View Address Mapping button 90 and a sub-window 142 is displayed. The sub-window 142 graphically shows the designer the memory mapping for the highlighted resource, in this case mem_resa. As can be seen, the memory map graphically illustrates where the variables are located in memory and where unused addresses are located, such as that shown at 144. The actual memory addresses are shown at 146 and the corresponding array indices of the variables are shown at 147, adjacent the actual memory addresses. It should be noted that the base-aligned packing mode causes the variables to be stored in memory such that they can be addressed simply without the need for complex hardware (such as an adder or subtractor). Using this packing mode, a single array (such as varb) may be divided up with unused memory addresses dividing the array, such as at 148.
FIG. 7 shows an example of moving the varc variable to a new memory resource called memres0. First, by selecting the current memory resource for varc, a sub-window is displayed as shown at 150. The designer can then select "New Resource", which causes the sub-window 152 to be displayed. This sub-window includes a name field 154 wherein the designer can enter a name for the new memory resource. With the proper name inserted, the OK button 156 is selected to create the new memory resource. This new memory resource is used to interactively modify the memory allocation of the integrated circuit.
FIG. 8 shows the user interface after memres0 is created. Notably, in the memory resources pane 70, the hierarchical display of memory resources shows two top-level memory resources and, at a sublevel, variables associated with each memory resource. For example, vara and varb are shown as included under mem_resa and varc is shown under memres0. Because memres0 was just created, it does not have a memory type associated with it (see Module pane). Additionally, the external pane is shown having memres0 to false and the packing mode to absolute (as defaults). At this point, the designer is investigating different potential memory layouts that are displayed in the lower pane 54. It is not until the designer selects the OK button 92, that the data structure stored in database 16 is updated.
FIG. 9 shows that the designer has assigned a memory type to memres0 as indicated at 160. Additionally, the external parameter has been changed to "true" and the packing mode to "compact". As shown in the address range pane 84, the address is automatically calculated based on the packing mode and the size of varc. Those skilled in the art will recognize that the memory resource memres0 was not defined in the source code file 12. Instead, the memres0 was created interactively by the designer. The designer can readily move variables between resources in pane 70 using drag and drop operations. For example, the designer can drag vara in pane 70 to memres0. This operation would cause the GUI to automatically delete vara from its association with mem_resa and automatically associate vara with memres0.
FIG. 10 shows a memory map window 162 for varc. First the designer selects memres0 as the desired memory to view the memory map, then the designer selects the View Address Mapping button. The memory map window 162 is then generated and displayed. The memory area taken by varc is shown as a graphical representation by block 164. The array indices are shown at 166 and the actual corresponding memory addresses are shown at 168 adjacent the array indices so that a one-to-one mapping between the array indices and the actual memory addresses can readily be seen. Additionally, logic is shown at 169 to indicate how the addresses are calculated.
FIG. 11 shows a memory map window 170 for mem_resa. The packing mode is base aligned and, consequently, the arrays are automatically organized in memory so that they may be easily addressed. Memory location 0 is unused as seen by a graphical representation of an empty block at 172. The vara variable starts at actual address 0001 and stops at address 0006. Another empty block shown at 174 separates vara from varb. In the base-aligned packing mode, an individual array may be divided up as shown by empty block 176.
Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles.
For example, although a particular GUI was shown, the user interface can be modified to illustrate the variables and resources in a different way. The particular user interface used is not important to the invention.
Additionally, the data structure stored in database 16 can be structured in a wide variety of ways. The particular data structure used is not important to the invention.
Moreover, although the description focuses on arrays, variables that are associated with single registers in an integrated circuit may also be modified using the GUI.
Although a particular data structure is illustrated, those skilled in the art recognize that a wide variety of data structures may be used.
In view of the many possible embodiments to which the principles of our invention may be applied, it should be recognized that the illustrated embodiment is only a preferred example of the invention and should not be taken as a limitation on the scope of the invention. Rather, the scope of the invention is defined by the following claims. We therefore claim as our invention all that comes within the scope of these claims.
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Allama Iqbal Open University is going to start the technical course in the city which gives practical expertise to the students. The students, who are getting education in these technical courses, should attend these technical workshops. The University administration will also start the MBA, MA classes and for other subjects or disciplines in the region. The University is going to establish the study centers to facilitate the local students.
The Director of Regional Services and Dean Faculty of Social Sciences, Prof Dr Rashid A Naeem, examined the workshop of master classes in the Allama Iqbal Open University regional office in Gujranwala. He also visited the under construction departments of the regional office at this occasion. Various other officers like Regional Director Gujranwala and Assistant Regional Director were also present on the occasion.
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