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A two-level storage system selectively enables early discard of data from an upper level either immediately or at the end of a predetermined sequence of operation. A copy of data in such upper level is discarded immediately while altered copies of data are discarded at the end of the predetermined sequence of operations. Error conditions inhibit discarding altered data.
1. A data store system having a backing store and a cache, first means for transferring data between said cache and said backing store, second means for transferring predetermined data between said data store system and a host, chain means for indicating an end of chained sequences of operations in said data store system,
the improvement comprising:
first means coupled to said second transferring means for receiving from a host and storing a given indication that predetermined data transferred to a host from said cache can be quickly discarded, and that other data stored in the cache and transferred to a host is not to be quickly discarded,
second means coupled to said cache for indicating data stored in said cache as being different from corresponding and supposedly identical data stored in said backing store,
third means coupled to said second transferring means for being responsive to first predetermined data being transferred from said cache to said host for effectively erasing the first predetermined data from said cache, and
fourth means coupled to said second transferring means and to said chain means for being responsive to second predetermined data being transferred from said cache to said host during a given chained sequence of operations and to said indication of said end of chained sequences for effectively erasing said second predetermined data from said cache.
2. The system set forth in claim 1 further including in combination:
sixth means for listing all of said second predetermined data and being connected to said fourth means for identifying said second predetermined data.
3. The system set forth in claim 2 wherein said data store system is peripheral to the host and said backing store includes a plurality of addressable disk-type data storage apparatus.
4. The system set forth in claims 1 or 3 further including a single electronic bus connecting said cache to said first and second transferring means, switching means for selectively activating either said first or second transferring means to transfer data over said single electronic bus.
5. The system set forth in claims 1 or 3 further including a microprocessor having a control memory with a plurality of addressable control registers and containing microcode logic for operating said system, said microprocessor being connected to all of said means and for controlling same in accordance with said microcode logic, said first means for receiving being predetermined ones of said addressable control registers and said microcode logic for selectively logically coupling said first means for receiving to others of said means.
6. The system set forth in claim 5 further including a random access memory having a multiplicity of addressable storage registers, said cache being a first predetermined set of said addressable storage registers,
a second predetermined set of said storage registers for containing a directory for said cache, said directory consisting of a plurality of data block identification cache address indications and said second means, and
said microprocessor capable of accessing said directory to access said cache.
7. The system set forth in claims 1 or 3 further including error means coupled to said cache and to said second transferring means for indicating an error related to said second predetermined data and seventh means coupled to said error means and to said fourth means and being responsive to said error indication to inhibit said fourth means response to said end of chained sequences indication whereby data stored in said cache is not stored in said backing store.
8. The machine-implemented method of operating a cache connected to a backing store and containing blocks of data corresponding to data stored in blocks in said backing store,
including the automatic machine executed steps of:
identifying a first and second set of data blocks in said cache respectively as being identical to and modified from corresponding blocks of data in said backing store,
transferring predetermined ones of said blocks of data from said cache to a unit other than said backing store in a sequence of block transfers,
effectively erasing from said cache any of said predetermined ones of said blocks of data which are in said first set immediately upon said transfer, and
effectively erasing from said cache any of said predetermined ones of said blocks of data which are in said second set immediately after completion of said sequence of block transfers.
9. The machine-implemented method set forth in claim 8 further including,
receiving a read and discard signal for certain ones of said blocks of data stored in said cache, and
effectively erasing only those predetermined ones of blocks of data which are also said certain ones of blocks of data and maintaining all of said predetermined ones of blocks of data in said cache other than said certain ones.
10. Data processing apparatus adapted to be connected to a digital processor and having a storage controller, a cache and a backing store, the cache being controlled by said storage controller which maintains addressability of data stored within the cache by pages of such stored data, a directory account of the pages stored within the cache that have been changed (page change account) and has a given page replacement protocol for controlling the transferring of data between the cache and backing store,
characterized in that:
said controller having first means for being responsive to a specific processor command to observe a second different replacement protocol from said given replacement protocol;
said controller having second means for being responsive to read-and-discard command (RAD) signals received from a connected digital processor for indicating that said digital processor has completed reading of a specific page of data stored in the cache;
said controller having third means for being responsive to said page change account and said received RAD signals only when operating in response to said specific processor command to effectively delete read but unchanged pages of data from said cache and to retain changed pages of data in said cache; and
said controller having fourth means for being responsive to a termination of the said specific processor command to store said retained pages of data in said backing store.
11. Data processing apparatus as claimed in claim 10 in which said storage controller is arranged to respond to said specific processor command as the first command of a chain of commands only for the duration of such chain.
12. Data processing apparatus as claimed in claims 10 or 11 wherein said storage controller for maintaining addressability of data stored in said cache has a directory, in which directory, changed status of said stored pages of data are stored and, in addition, having a logical device control block for each logical device of said backing store and having a discard list of temporarily retained but changed pages of data; and having means for storing in the appropriate logical device control blocks, respectively.
13. Data processing apparatus as claimed in claims 10 or 11 further including error detecting facilities effective, in the event of a detected error, to inhibit rapid discard of the corresponding page(s) of stored data were discard otherwise logically appropriate.
The present invention relates to data processing, particularly, to control of a data buffer memory or cache connected to a backing store.
Buffer memories have been used for years for enhancing operation of memory systems. When such a buffer becomes large and is extremely fast, such that the relatively low-performance of a backing store is substantially masked from a using unit, such a buffer has been referred to as a cache. For cost control purposes, it is desired to minimize the size of a buffer memory, particularly when so-called caching characteristics are desired. To date, the contents of a cache are determined by several automatic mechanisms which are usually based upon algorithms of diverse types. A first mechanism is the promotion of data from the backing store to the cache. The purpose of the data promotion is to ensure that the data in the cache is the most likely to be used next by the using unit, such as a central processing unit. With only a data promotion mechanism, the cache would soon fill up, preventing further data from being promoted from the backing store. To ease this problem, replacement algorithms have been designed with mechanisms implementing those algorithms replacing data in the cache with new data being promoted from the backing store. With this combination of data promotion and replacement, the cache is always full of data. Optimizing caching characteristics, i.e., maximizing the so-called device characteristic masking feature of the caching function, requires a relatively large cache. Further, the replacement algorithm may require that data be transferred from the cache to the backing store before new data can be promoted. This action results in a performance degradation. Accordingly, it is desired to provide a caching or buffering function which tends to maximize the caching characteristics with a smaller cache than would be required with the usual data promotion and replacement control mechanisms. Some prior cache mechanisms are next described.
U.S. Pat. No. 4,048,625 shows a first-in, first-out (FIFO) buffer which invalidates data areas upon readout. Data validation in the buffer occurs independently of error conditions. Also, invalidation occurs irrespective of whether data was modified while it was in the buffer.
Lang et al., U.S. Pat. No. 3,845,474 shows invalidating cache data when a first processor reads it when the data is in a so-called "communication table". That is, data accessible by another processor which can change such data independent of the cache-running processor is invalidated.
Chang et al., U.S. Pat. No. 4,197,580 shows a cache having a validity bit for each cache area; upon readout, the validity bit may be reset, i.e., data becomes invalid.
In general, a dual-copy philosphy is used in many cache-backing store situations. That is, a main memory will have one copy, and the cache will have a second copy. Generally, in a processor cache, the data is usually not destroyed as it is read except as set forth in Lang, et al. above.
According to the invention, a storage system has a backing store and a cache or buffer. The data storage system can receive from a using host a read and discard (RAD) indicator. Means are responsive to the RAD indicator to effectively erase the data in the cache that has been read by a host or other using system. Unless such data has been modified, that is, the data in the cache is different than the data in the backing store, then means are responsive to an end of operation signal (end of a chaining operation, for example) to destage the modified data (in accordance with a least-recently used algorithm or immediately) that was read from the cache by the host to the backing store and then effectively erasing the data from the cache. Erasure of such data from the cache is preferably achieved by destroying the addressability of the data in the cache, i.e., erase a directory entry that directs accesses to the appropriate cache area for the data.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
FIG. 1 is a diagrammatic showing of a storage system connected to a host which employs the present invention.
FIG. 2 is a diagrammatic showing of a preferred embodiment of the invention illustrated in FIG. 1 and as it is practiced with a DASD (Direct Access Storage Device) storage system.
FIG. 3 is a diagrammatic showing of interaction on microcode controls usable in the FIG. 2 illustrated embodiment.
FIG. 4 is a flow chart showing the operations of the FIG. 2 embodiment as performed by the microcode of FIG. 3 in practicing certain aspects of the invention.
FIG. 5 is a flow chart similar to the FIG. 4 flow chart showing other aspects of the present invention as practiced in the FIG. 2 illustrated embodiment.
Referring now more particularly to the drawings, like numbers indicate like parts and structural features and functions in the various diagrams. FIG. 1 shows a storage system 10 attached to a plurality of hosts 12, such as central processing units, communication systems, and the like. A storage director 11 within storage system 10 provides for data transfers between the backing store 13 and the host 12 via input/output connection 14. Backing store 13 preferably consists of a plurality of disk-type data storage apparatus as indicated in more detail in FIG. 2. Backing store 13 can also consist of random access memories, so-called bubble memories, magnetic tape recorders, unit record equipment, optical storage devices, and the like. Interconnection 14 is a computer input/output connection such as used on IBM computers. A description of such interconnection is found in publication no. GA22-6974-4 entitled, "IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturer's Information" (OEMI) available from International Business Machines Corporation, Data Processing Division, 1133 Westchester Avenue, White Plains, N.Y., 10604. This interface is widely used in the data processing art and is well-known.
Each host 12 operating with storage system 10, when using the above-described interconnection, provides for chains of peripheral operations which constitute a single sequence of operations. FIG. 1 illustrates a chain of operations 15 consisting of a plurality of peripheral commands represented respectively by the plurality of horizontal lines. Each sequence of operations preferably operates with a buffer within storage director 11 represented in FIG. 1 by a plurality of allocated buffer segments 16. Storage director 11 responds to the chain 15 peripheral commands through its command decode 17 which then activates a buffer control 18 for transferring data signals between a host 12 and a buffer allocated segment 16, as well as between backing store 13 and such allocated buffer segment 16. A channel adaptor 19 intercepts the commands from host 12 and supplies them to command decode 17. Data signals are transferred directly to buffer segment 16, as will become apparent and as widely practiced in the data processing art.
Each of the allocated buffer segments 16 are addressible registers (not shown) within predetermined address ranges of a relatively large buffer, such as a memory in the megabyte capacity range. To effectively access buffer segments 16, a directory 20 is maintained within storage director 11 for pointing to the areas within allocated buffer segment 16 that contain data signals corresponding to what is termed a "logical device". Each segment can contain data relating to one logical device. That is, each host 12 can access storage system 10 through certain address codes. Each address code corresponds to a so-called logical device. The rest of the desciption of this specification assumes that one logical device has been indicated by a host 12; it is understood that a plurality of logical devices can be identified in an interleaved manner by host 12 such that highly multiplexed data processing operations can occur between hosts 12 and storage system 10.
Returning now to directory 20, a column of entries 21 contain the identification of the blocks of data signals, preferably blocks of fixed size, that are stored in buffer segments 16. For purposes of simplicity, these are labeled A through H for the logical device being discussed. Within each directory 20 register is an address in column 22 which identifies the area of buffer segment 16 where the corresponding data is stored. In a preferred embodiment, each identified area has a fixed number of addressible storage registers, such as capable of storing 500 bytes, 1 kilobyte (KB), 2 KB, 4 KB, etc. For example, data block A is stored at address X1, data block B at address X5, and so forth. A third column 23 contains a single bit position for each of the data blocks identified in the directory for indicating whether or not an access to the buffer segment 16 resulted in a change in the indicated data block. For example, directory 20 shows that data block A has not been changed, i.e., the image of data stored in buffer segment 16 is identical to the same block of data stored in backing store 13. On the other hand, data block B is indicated as having changed data, i.e., a binary 1 occurs in column 23 indicating that a host 12 accessed allocated buffer segment 16 and altered the data block B from that data that was promoted from backing store 13. This means that the image of data block B in the allocated buffer segment 16 is different than the block B stored in backing store 13.
Data blocks A through H can be a sequence of data blocks that are logically contiguous. Storage of such sequential contiguous data blocks within an allocated buffer segment 16 can be fragmented as indicated by the addresses in column 22. The data blocks A through H are shown as being stored at 24 in a first-allocated buffer segment 16. It is to be understood that the indicated segment 16 is a logical segment and physically may be distributed throughout the actual memory for performance, integrity, and other purposes, as is known in the data memory management art. Associated with each block of data 24 can be a bit indicated in column 25 corresponding to the bits in column 23, i.e., whether or not the data is actually altered. In a preferred form of the invention, only column 23 occurs. Other control features in directly 20 and within allocated buffer segment 16 may be provided which are not pertinent to an understanding of the present invention.
This description assumes that the data blocks A through H are already resident in allocated buffer segment 16. This means a prior chain of commands (not shown) indicated to storage system 10 that there was a likelihood that the data blocks A through H of backing store 13 would likely to be used in the immediate or near future. Accordingly, data promotion controls 27, which can be of a known type, cause the storage director 11 to access backing store 13 for the purpose of transferring data signals from the backing store 13 to allocated buffer segment 16. Such data promotion controls are not pertinent to an understanding of the present invention and, hence, will not be further described. It should be noted that there is co-action between the buffer control 18 and data promotion controls 27, as is known in the caching art.
For practicing the present invention, some additional controls are added to storage director 11. Since storage system 10 is addressed through logical devices, a logical device control block (LDCB) is provided for each logical device. A set of registers 30 contain the signals of the LDCB. LDCB contains all of the control information necessary for storage system 10 to operate with the logical devices in responding to hosts 12 requests. Note that the logical device can be compared to an access path from host 12 to backing store 13 as modified by the caching function of buffer segment 16. Bit position 37, the RAD bit, is an important aspect of LDCB for practicing the present invention. Bit 37, when set to the active condition for a logical device, signals the storage director 11 to discard data from cache that was read to host 12 as quickly as possible. A second control in storage director 11 is discard list 31 which is an addressible set of registers containing an indentification of those data blocks in allocated buffer segments 16 which are to be discarded at the end of the present sequences of operation, i.e., at end of chaining when using the above-described interconnection 14. As an alternative, the modified data indicated in block 31 can be destaged to the backing store upon completion of the sequence of operations (at the end of chaining). There is one list in item 31 for each logical device.
A first command within chain 15 can be a mode set command. Such a mode set command 33 can contain a "RAD" bit position 34 indicating read and discard. When bit 34 is set to the active condition in a given mode set command directed toward a given logical device, command decode 17 responds as indicated at 35 to transfer the bit 34 to bit position 37 within LDCB 30 for the given logical device. If there are a plurality of logical devices, then there are a plurality of registers 30 and a corresponding plurality of RAD bits 37. The transfer of RAD bits from a peripheral command by a storage director to a designated register is well-known in the art and not detailed further for that reason. The transfer is indicated in FIG. 1 by line 36.
Following a successfully executed mode set peripheral command, subsequent commands within a chain 15 may cause the transfer of data signals from the allocated buffer segment 16 to host 12. In this instance, command decode 17 responds to a peripheral read command 38 for the given logical device to access directory 20 for identifying the location of the data in allocated buffer segment 16, all as indicated by numeral 40. For example, when data block B is to be read, then address X5 is transferred to buffer control 18 as indicated by numeral 40. Similarly, when data block C is addressed, then address X7 is transferred to buffer control 18 for accessing the data. Once the allocated buffer segments 16 are accessed, data transfer to host 12 occurs. Upon the completion of each read peripheral command, which accounts for transfer of a single block of data, the contents of RAD bit 37 is transferred to buffer control 18, as indicated by line 41. When a data block, such as data block C which was not modified, is transferred to host 12, then buffer control 18 immediately deletes entry C from directly 20 as indicated by line 42. This action destroys the addressability of data block C contained in allocated buffer segment 16, thereby freeing the address X7 for reallocation. On the other hand, peripheral command 43 causes director 11 to transfer data block B contained in allocated storage segment 16 at address X5. Since RAD 37 is set to the active condition and data block B has been altered by a previous sequence of operations (not shown), then buffer control 18 supplies a signal over line 44 to logic AND circuits 45 to transfer the identification of data block B to discard list 31 for the addressed logical device. AND circuits 45 are enabled by the signal on line 41 representing the contents of bit 37, while buffer control 18 transfers the signal designation of data block B to list 31. A list 31 is accumulated for each logical device during each chain 15 to be used as next described.
Chaining is indicated in the interconnection 14 by a so-called SUPPRESS OUT signal being supplied by the host 12 to storage director 11 at ending status time. In FIG. 1, this is indicated by arrow 50 which continues through the various peripheral commands of chain 15 until 51 whereupon SUPPRESS OUT is not supplied when ending status is required for indicating the end of the chain. This condition is detected by the channel adaptor 19 using known circuits. An electrical indication of end of chain is supplied over line 52 to activate logic AND circuits 53 which are also co-activated by RAD bit 37 to pass the list of data blocks to be discarded for the addressed logical device from list 31 as received over line 54. The data blocks being discarded are identified to buffer control 18 over lines 55. The readout of the list 31 is under a sequence control within buffer control 18 (not shown in FIG. 1). Discarding of the modified blocks at the end of the chain is achieved by erasing the entries in directory 20, such as erasing data block B entry.
It may be desired that the modified block be destaged or transferred to backing store 13. Destaging is preferably in accordance with a least-recently used algorithm (LRU). In this instance before the directory 20 entries corresponding to the discard list indicated data blocks are erased, the data is transferred asynchronously from allocated buffer segment 16 to backing store 13.
FIG. 2 illustrates a version of the FIG. 1 storage system that is a preferred embodiment of the invention. Channel adaptor 19 consists of a plurality of individual channel adaptors which respectively receive access requests from hosts 12, one channel adaptor per set of logical devices. No limitation thereto is intended. Data transfers between backing store 13 and host 12 proceed through the channel adaptors 19 as next described. A bus 60 extends from channel adaptors 19 to multiple double-throw electronic switch 61 which selectively makes bus connections directly to backing store 13 or to a cache or buffer memory within storage director 11 via bus 64. A microprocessor 62 controls switch 61 as indicated by dash line 63. For transfer of data signals directly between backing store 13 and channel adaptors 19, bus 65 extends from electronic switch 61 to a second multiple double-throw electronic switch 66 which is also controlled by microprocessor 62 as indicated by dashed line 67. Switch 66 connects bus 65 to data circuits 68 which in turn are connected to backing store 13 via one or more device adaptors 72. The data circuits 68 and device adaptors 72 can be those circuits used in the IBM 3830 storage control unit or the IBM 3880 storage director. From the above, it is seen that host 12 can access data directly from backing store 13 or via the above-described allocated buffer segments 16.
The preferred embodiment of the backing store 13 is a plurality of direct access storage devices (disk-type storage apparatus) 75 and 76 respectively accessible through storage director 11 via a pair of controllers 73 and 74. Such controllers and direct access storage devices can be similar to the IBM 3350 disk storage apparatus or other disk storage apparatus.
Switches 61 and 66 are connected to a memory 78 via buses 64 and 70, respectively, through buffer access circuits 77. Buffer access circuits 77 are those circuits usually employed for accessing a random access memory of the semiconductor type. Memory 78 contains the allocated buffer segments 16, which form a cache, as well as directory 20. Memory 78 is preferably of the semiconductor type having a storage capacity in the megabyte range. Microprocessor 62 controls buffer access circuits 77 by supplying address signals over an address bus 79. Microprocessor 62 also has a plurality of addressible registers 81 for storing control signals as is common practice in the microprocessor art. Further, control memory 82, another semiconductive type of random access memory, contains microcode control programs which determine the logic of operations of storage director 11. That is, the microcode or microprogram within control memory 82 constitutes a logic module defining the electronic operations of the director. Additionally, control memory 82 contains control tables used by the microcode in microprograms, such as LDCB 30 and discard list DL 31. Alternatively, registers 81 could contain LDCB 30 and DL 31. The operation of the invention within the FIG. 2 illustrated embodiment is best understood by referring to FIGS. 3 through 5.
FIG. 3 shows the broad operational relationships between two major sections of microcode stored in control memory 82. Native microcode 55 is that microcode found in the above-referred-to IBM 3830 or 3880 storage control devices. That is, this microcode enables direct transfer of data between channel adaptors 19 and devices 75, 76 which are shown as direct access storage devices. Included in this microcode is the microcode logic for decoding commands as indicated by a numeral 17 in FIG. 1. The arrangement is such that the native microcode 55 will refer received commands to buffer microcode 57 for determining whether or not memory 78 and its associated allocated buffer segment 16 are to be used in a given data transfer command, i.e., a read command which transfers data from backing store 13 to hosts 12 or a write command which transfers data from hosts 12 to backing store 13. Communication between the two sets of microcode logic modules is indicated by double-headed arrow 58. Such linkage can be any known microcode linkage as is widely practiced in the microcode art. Microcode can be in the form of firmware or can be loadable code signals from a tape or disk record. Microprocessor 62 communicates with all elements of the storage director 11 as indicated by the microprocessor connection 56 of FIG. 3. Connections 56 consist of input and output registers (not shown) of microprocessor 62 as is widely used for that type of computer device.
In the preferred mode of operation all of the peripheral commands used with the IBM 3830 and IBM 3880 are decodable by the native microcode 55. The buffer microcode 57 includes that microcode for controlling buffer access circuits 77, i.e., directory look-up and the like. Since such microcode logic is well-known, i.e., programmed access control of memories is well-known, this aspect of the buffer microcode 57 is not described.
FIG. 4 illustrates the response of buffer microcode 57 logic to a decoded commands relating to mode set and read. The command is decoded at 17. Some non-pertinent functions are performed at 90 relating to analysis of the decoded command. Included in the analysis of the decoded command referred to the buffer microcode 57 by the native microcode 55 includes decoding a mode set command for the addressed logical device is analyzed at 91. If a mode set command has been received from host 12, then at 92 LDCB 30 bit 37 is made equal to the RAD bit 34 of that mode set command. For purposes of discussion, assume that the RAD bit 34 is set to unity. Since mode setting provides but a set-up of control indicia within storage director 11, ending status is set as usual at 93. Some later described ending functions are performed for presenting status to the host.
If at 91 the received command is not a mode set command, then path 94 is followed to step 95 wherein whether or not the command is a read command is examined. If it is not a read command, then the procedures of the present invention are not invoked and microprocessor 62 follows path 96 to other microcode logic steps not pertinent or an understanding of the invention. For a read command, some non-pertinent steps are performed at 97 for initializing storage director 11 for the read command use of memory 78. At 98 microprocessor 62 determines whether or not the requested data block is stored in an allocated buffer segment 16. This action is achieved by scanning directory 20 to see if there is an entry in directory 20 identifiable with the requested data block identified in the received read command. If the data is not in the memory 78, then the data must be promoted from backing store 13 to the memory 78 requiring action indicated in FIG. 1 by the data promotion controls and as indicated in FIG. 4 by line 99. If the requested data block is residing in memory 78, then at step 101 microprocessor 62 again examines to see if the received peripheral command is a read command. If not, path 102 is followed for other actions not described. For a read command, at step 103 microprocessor 62 sets switch 61 to the illustrated position of FIG. 2 for transferring data signals from memory 78 through a channel adaptor 19 to host 12. This transfer occurs automatically using automatic data transfer techniques. The address of memory 78 containing the requested data block is first fetched from directory 20 and transferred over address bus 79 to buffer access circuit 77 which includes automatic data transfer capability. Upon completion of the data transfer to host 12, microprocessor 62 examines the automatic data transfer circuit (not shown) within buffer access circuit 77 to see if an error occurred in the transfer. If an error had occurred at step 104, then error status is set at step 105 in a register 81 for reporting to host 12, as later described. When no error occurs, at step 106 microprocessor 62 examines directory 20 to see if the block contained in the buffer has been modified (BMOD). If there is no modification, i.e., column 23 indicates 0 for the requested data block, then at step 107 the entry in directory 20 is deleted as indicated by DELE DIR-E. If there was a modification, such as indicated for block B of FIG. 1, then microprocessor 62 accesses DL 31 and adds the block identification to the discard list in DL 31 for the addressed logical device. Then ending status for the read command is set at 109.
Housekeeping functions following the execution of the above-described command begin at 112. First, at 113 error status is checked. If an error was reported at 105, then at 114 RAD bit 37 of the logical device that was addressed in the read command is examined. If the read and discard bit is active, then the discard list in DL 31 is erased at 115 such that the data in the allocated buffer segment 16 that was unsuccessfully transferred to host 12 is not deleted or made unaddressible. Otherwise, no such action is taken as indicated by line 116. Ending status is supplied to host 12 at step 117 following the procedures set forth in the OEMI manual for interconnection 14 mentioned above. Then microprocessor 16 proceeds to other microcode logic modules as indicated at 118.
FIG. 5 shows the operations of the microprocessor 62 upon detecting the end of a chain at 52. First at 120 RAD bit 37 of LDCB 30 is examined. If it is a 0, then no action need be taken with respect to practicing the present invention. Accordingly, non-pertinent code is executed at 122. On the other hand, if RAD 37 is set to unity for the addressed logical device, then at 121 DL 31 is accessed to identify those entries in directory 20 that have to be deleted. Then microprocessor deletes those entries making the corresponding data unaddressible. As mentioned earlier, when data in a cache is modified by a host 12 it may be desired to update the backing store 13 to reflect those changes. In this instance, prior to deletion of the directory 20 entries, the data blocks identified in DL 31 are first transferred from allocated buffer segment 16 to backing store 13 in accordance with an LRU algorithm. In either event, the modified data contained in allocated buffer segment 16 is effectively deleted or erased from the allocated buffer segment by destroying the addressability to that data by erasure of the directory 20 entry.
From all of the above it is seen that the integrity of data in a buffer is maintained while data is rapidly discarded from the buffer for making prespace within the buffer for promotion of data. This action eliminates the destate or demotion requirements usually imposed upon buffer systems by known replacement algorithms. Accordingly, the early deletion of data based upon an intent signal supplied by host 12 that the data can be discarded whether altered or not provides for reducing the required size of allocated buffer segment 16 for achieving caching properties by the buffer.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention:
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The Margarita Hotel offers 12 double rooms, air-conditioning, a swimming pool, sauna, wireless Internet, a restaurant and a parking lot.
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michala / February 8, 2013
If you've watched even one episode of Family Guy, then you probably know who Quagmire is. In an episode from season 10, entitled "Meg & Quagmire", Meg turns 18 and Quagmire tries to date her. I'm not really sure of his exact age in the show, but he is obviously as old as her Dad, so it's creepy. The reason I'm bringing this up is because in this episode they show a lot of Quagmire's House.
The makers of Family Guy know what is takes to create the home of a Creeper. It's the perfect mix of a vintage porn set, the 70's, a strip club, and Gigolos. To enhance his Creeper status, Quagmire has an obnoxious catch phrase, wears a Hawaiian shirt, and (as shown below) sometimes a gold chain.
None of these things are acceptable for you to attract a decent lady. Please assess yourself, and adjust as needed.
Heartshaped bed and mirror on the ceiling:
I can't find the episode on Fox, Netflix instant, or Hulu. So here is a link to a (questionably legal?) site FamilyGuyEpisodes.
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CONTACT: Inquiries: email@example.com; Public Relations: Merle Goertz (West Coast), (604) 688-2349
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HEALTH CARE: HEALTHCARE HOUSEKEEPER 96 bed inpatient mental health facility looking for a full time housekeeper.More info
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Brocton on the brink of winning Midland Combination title
Posted: April 14, 2014|
Pershore Town 3 Brocton 4
TWO late goals including a stoppage time winner saw Brocton come from behind to pull off a dramatic victory by the odd goal in seven on Saturday and now they are on the brink of lifting the championship trophy.
Title rivals in the Midland Combination Premier, Bromsgrove Sporting, who has been awarded team of the month for March, suffered their second defeat of the week going down 3-2 at home to Studley.
That outcome leaves the Badgers needing just two points from their remaining four games to lift the Premier title and they could be celebrating on Tuesday night when they visit Coventry Copsewood.
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Prior to the kick off at Pershore, visiting keeper Adam Whitehouse was withdrawn due to a bruised hand so Ashley Lunn was installed for his first senior game.
Lunn was soon into the action and needed to be quick off his line to deny the in-rushing Pershore centre forward when Levi Bailey's headed back pass lacked pace.
Good play on the right by Paul McMahon and Sam Bell gave an opportunity to Gary Fife but the striker missed out.
Pershore's attacking threat was mainly through Mark Owen who was becoming a worry to the Brocton central defenders. Bell and McMahon appeared the most effective Brocton forwards and created a chance on 21 minutes but a low cross from Bell eluded all the forwards.
In the next attack Andy Bourne provided a short pass to Seb Hamilton and then onto the lively McMahon who lifted the ball over the advancing Matt Oliver in the Pershore goal, to register Brocton's first goal on 23 minutes.
At this stage Brocton looked comfortable but as in recent matches they lost concentration and Pershore started to gain confidence.
On 38 minutes Scott Walsh hit a low shot from the edge of the Brocton area to equalise. The spirited Pershore side then grabbed their second goal through the experienced Mark Owen on 42 minutes to send them in 2-1 up at the interval.
The second half started with Brocton slow to react and a mistake by the defence gave Owen an easy opportunity which he took within two minutes of the re-start giving the home side a two goal advantage. This injected more pace and urgency into Brocton's play and Bell hit the bar on 47 minutes as the away side started to apply pressure which was eventually rewarded by a Bourne goal on 65 minutes to make it 3-2.
The Pershore goal was now under siege with Bailey heading over and Ashley Phillips shooting wide following his introduction for McMahon.
Brocton were now piling on the pressure needed if they were to get anything from the game. Both Fife and Bell had shots deflected in the melee of players packed into the Pershore penalty area.
Brocton's forwards looked over anxious as the time started to tick away and manager John Berks shuffled his pack by bringing on Charlie Jones and Richard Allen to reshape the side to give a new emphasis on attacking play.
Under extreme pressure Pershore eventually allowed Fife enough space to get a shot on 88 minutes which he hit beyond the Pershore keeper from eight yards. This was followed by a hand ball appeal which was not given but the following attack, now into added time gave Seb Hamilton an opportunity and he coolly slotted the ball past keeper Oliver for a dramatic last gasp winner.
The result leaves Brocton on the brink of winning their first League Championship since 1977-78 when they won the Cannock Chase League for the sixth time.
Brocton: Ashley Lunn, Dave Ablewhite, Levi Bailey, Dean Crowley, Jamie Evans, Sam Bell, Andy Bourne, Gary Fife, Dan Lomas, Paul McMahon, Seb Hamilton.
Used substitutes: Richard Allen, Charlie Jones Ashley Philips.
This Saturday Pilkington XXX are the visitors to Silkmore Lane for Brocton's last home Premier Division fixture while the reserves are away to Cadbury Athletic where they will look to follow up Saturday's emphatic 3-0 win at Continental Star with another away day success(both games kick off at 3pm.


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Museum of Science+IndustryGetting Here5700 S. Lake Shore DriveChicago, IL 606371 (773) 684-1414
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Discussion in 'AS Roma' started by Andreas, May 3, 2012.
totti has just missed a pen and missed the rebound, that was a bad miss from him!!
Totti missed a pk, damn it.
Damn Totti missed the penalty.
he could have scored on the rebound too.
how was that a penalty??
how did Totti miss on the rebound? lol
Rebound was a much worse miss then the pentaly itself.
It was one of those open nets were he was are already thinking how to celebrate the 500th game
OMG, Totti isn't gonna hit anything tonight.
looks like carizzo is having totti's number today, sadly
had no idea marco motta was at catania
If I was on the bench, I'd sub Totti on half time. He was awful.
sure why not. fans wont like it. but who cares, LE is gone this summer anyway
Unfortunately this season has shown that Totti can't handle playing every 3-4 days. We really need to break our dependence on him this summer.
Actually, except for the double miss, Totti has been quite mobile, opening up spaces and giving good passes...so if I were the coach, I'd sub Borini for Lamela
Should play Lamela, and prepare him for the future.
We've had some good link up play between Totti-Ozzy-Borini but that's the only good thing I've seen so far. Marquinho seems a little awkward but he already looks much better then Angel at LB.
We need a goal.
He made the best move of the game that should have been finished of at the start. But the miss is messing with his mind, trying to hard to score a screamer to make up for it. However, given its his 500th Seria A game, it would be a disgrace to sub him at half time like this. Give him at least until the 60th min, a chance to settle on the pitch
F*** Carizzo the Laziale scum actually...If not for him, we would have been at least 2 goals ahead
btw, lobont pulled some big saves.especially that one that counted offside on catania
i am glad that totti missed the penalty. It would be a disgrace to win with a bs penalty
it would be a more disgrace if we fail to qualify for EL due to this miss though
we shouldn't be desperate and hope for a win in this manner
Totti goaaaaaaaaaaaaaal
sub him now then if you want He deserves that for being a champion!!
Separate names with a comma.


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Gate practice every Tues. & Thurs. 6-8pm, $4 fee, Cancellations posted on Facebook & sent via Text
Winchester Weather
Thursday 07/30 60%
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Mixed clouds and sun with scattered thunderstorms. High 88F. Winds WNW at 5 to 10 mph. Chance of rain 60%.
Friday 07/31 0%
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Saturday 08/01 0%
Generally sunny. High 89F. Winds WSW at 10 to 15 mph.
Getting StartedSo you want to start racing BMX? First off don't worry worry about the equipment, we have you covered (in most areas) and can provide loaner equipment till you decide if this is for you. A new bike is not necessary to get started....
Our yearly Virginia State Qualifier race is quickly approaching and we wanted to pass along a few details about the week. Thursday we will be hosting a Dominique Daniels Skills Clinic, Saturday will be the Warnicke Double Points Race followed by a Pool Party (all are invited) at the Jim Burnett Park (just a short.. read more →
On August 21st from 5:30 to 8:30pm we will have the pleasure of hosting a Dominique Daniels BMX skills clinic (register at the track, $35 per rider). If you aren't familiar with her she's the 2008, 2009, 2010,2011, 2012 National USABMX Women's Pro Champion and the first Lady to go from #1 amateur to #1 Pro Champion In the.. read more →
Carley Young Clinic and Lessons This coming week Pro Rider Carley Young will be visiting Winchester BMX and will be offering private lessons and a group clinic. Private lessons will be held Thursday (6/12/14) and Friday (6/13/14), all lessons are one hour long and will be $40, to sign up for private lessons please VISIT THIS.. read more →
We are happy to announce new colors have arrived for our 2014 Winchester BMX jerseys. We are retiring the silver version and have 3 new colors to choose from: blue, orange and green. You can place your order at the registration building ($58). read more →


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Updated: 06/18/2013 5:05 PM KSTP.com
(AP) NEW YORK - Former New York City Mayor Ed Koch meticulously planned his own funeral, but his tombstone has the wrong birth date.
NBC 4 New York (http://bit.ly/11kapIO ) reported Monday that the headstone lists his birth year as 1942 instead of 1924.
The engraver, Tommy Flynn, of Flynn Funeral and Cremation Memorial Services, says it was "an inadvertent error" and that he feels "terrible." He says he'll correct it.
Koch was buried in Trinity Church cemetery in Washington Heights after dying of congestive heart failure in February at 88.
The Democratic mayor is credited with helping save New York from its economic crisis in the 1970s and leading it to financial rebirth.
(Copyright 2013 by The Associated Press. All Rights Reserved.)


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Scarlets centre Jonathan Davies hailed 'massive' for Wales
Posted: November 21, 2012|
SCARLETS centre Jonathan Davies has been hailed as a "massive" player for Wales as he makes a welcome return from injury for Saturday's Millennium Stadium showdown against the All Blacks.
Davies has missed Wales's opening two autumn defeats against Argentina and Samoa because of the groin problem he picked up in the Scarlets' Heineken Cup defeat in Clermont at the start of October.
However, after coming through a fitness test this week the 24-year-old comes straight back into a side desperate to atone for two woeful displays that have led to the Grand Slam winners dropping to eighth place in the IRB world rankings.
Wales have missed Davies's dynamic midfield presence during the autumn series, managing just one line break in two morale-sapping losses.
And with the dark shadow of the world's leading rugby nation looming large over Warren Gatland's side, Davies's return has been heralded as a much-needed shot in the arm.
"Jonathan is key to our defensive system and he is a massive player for us," said defence coach Shaun Edwards.
"You always want your most experienced players available when you are playing against the All Blacks."
As well as Davies, hooker Matthew Rees has overcome his calf problem to start at hooker with regional rival Ken Owens, one of the few to make an impression against the Samoans last weekend, again named on the bench.
Rhys Priestland and George North make up the rest of the Scarlets contingent in the starting XV with Tavis Knoyle, Aaron Shingler and Scott Williams among the replacements.
Rob McCusker misses out with a foot injury that could see him miss the Heineken Cup games with Exeter.
While all eyes will be on Cardiff this weekend, the Scarlets return to RaboDirect Pro12 action on Sunday (5.15pm) when they take on Munster at Cork's Musgrave Park.
The West Walians will be aware they haven't beaten the Irish province since the 2007 Heineken Cup quarter-final at Stradey Park.
And head coach Simon Easterby has demanded improvements in the wake of a mixed opening two rounds of the LV= Cup.
"These last two weeks have served a purpose for us," admitted Easterby, in the wake of his side's hard-earned 22-16 victory over the Blues on Saturday.
"The first 50 minutes against Worcester was excellent and the second half against the Blues was good, but it was nowhere near where we want it to be and we are going to have to be a lot, lot better against Munster.
"The pleasing thing is that we came out of it with the right result." The Scarlets could again have full-back Liam Williams available.
Williams was released from the national squad last week and turned in a man-of-the-match display against the Blues.
"Obviously, I would love to be involved against the All Blacks and wear that Welsh jersey with pride," he said. "But if not selected I will hopefully come back and look forward to a trip to Cork with the Scarlets."
The Scarlets will continue to assess injuries to wing Kristian Phillips (groin), centre Gareth Owen (knee) and No. 8 Kieran Murphy — who all came off against the Blues.
Wing Morgan Stoddart is expected to return after being rested for the last two matches.


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Joe is the managing member of Peiffer Rosca Wolf Abdullah Carr & Kane, A Professional Law Corporation. His practices consist of representing individuals and institutions that have been harmed by investment banks and brokerage firms, prosecuting ERISA class actions, and representing victims of labor trafficking and those who have suffered catastrophic injury. He has co-authored a treatise Litigating Business and Commercial Tort Cases, which is published by Thompson West.
Alan is a securities lawyer and a member of the firm. He teaches Securities Regulation at the Cleveland-Marshall College of Law, Cleveland State University and is a speaker and author on attorney ethics and professionalism. Alan focuses his legal practice on complex commercial and financial litigation and arbitration, particularly in the areas of securities and investment fraud.
Mr. Wolf has developed a national reputation as a leading appellate and civil rights litigator. He successfully argued a case in the United States Supreme Court, Safford Unified School District No. 1 v. Redding, 557 U.S. 364 (2009), that defined the scope of the Fourth Amendment regarding strip searches in public schools.
David has gained extensive trial and litigation experience over the course of his career. He practiced as an Assistant District Attorney ("ADA") for Orleans and Jefferson Parishes for nearly a decade. David currently focuses his law practice in the areas of product liability, wrongful death, human rights, whistleblower, personal injury, employment, and select criminal defense matters.
Daniel represents a diverse client base in a variety of commercial disputes and arbitration. Daniel currently represents investors, and municipalities in FINRA arbitration proceedings. Together with Joe Peiffer, he also serves as co-counsel in several ERISA and antitrust class action lawsuits and represents individuals in litigation involving pharmaceutical products, labor exploitation, fraudulent investments, and wrongful death.
Jason J. Kane is a securities attorney practicing out of the firm's Upstate New York office. He has extensive experience representing investors in Financial Industry Regulatory Authority ("FINRA") arbitrations and New York State Courts. Jason has strong ties to the Upstate New York region having been born and raised in Syracuse, New York. In 2007, after passing the New York State bar exam, Jason moved to Rochester, New York to begin his legal career.
James Booker is an associate in the law firm of Peiffer Rosca Wolf Abdullah, Carr & Kane, A Professional Law Corporation. His focus is on securities arbitration as well as class actions cases involving investment fraud and employment disputes.
Tracey Cowan's practice centers on civil rights law and general civil litigation. Prior to working at Peiffer Rosca Wolf, Tracey was an associate in the San Francisco office of Bingham McCutchen. There, her practice focused on complex civil litigation and competition matters, as well as civil rights issues concerning California State prison reform.
Bonnie Jones began her career as a Legal Assistant nearly forty years ago, assisting in various types of litigation through the years, primarily with the same group of attorneys in New Orleans, her home town. Her current position with the Firm includes the roles of Paralegal and Administrator. Bonnie and her husband, Phil, are the parents of five grown children, who are all very successful in their respective careers. In addition to her career, Bonnie is involved in her community, having chaired numerous fundraising events over the years.
Colleen M. Werberig, RP is Chief Paralegal of the Securities practice of the Firm. She works out of the Upstate New York office. She is a Registered Paralegal having been recognized in 2000 by the National Federation of Paralegal Associations, Inc., earning the "RP" designation.
Berry Lohman is a Litigation Paralegal with Peiffer Rosca Wolf Abdullah, Carr & Kane, A Professional Law Corporation. Berry primarily focuses on Pharmaceutical Mass Torts. She previously worked for Ochsner Medical Center's Legal Department and received a Paralegal Certificate and Bachelor's Degree from Louisiana State University.
Lori is a Senior Research Analyst with Peiffer Rosca Wolf Abdullah Carr & Kane, A Professional Law Corporation. She graduated the Iasi Law School in Romania, with a focus on European and Comparative Law in 2008. She heads the investigative research team in the Firm's securities practice. Lori has strong research skills and a passion for investigation. Much of her work is focused on identifying individuals and entities that assist in the perpetration of fraudulent investment ("Ponzi") schemes.
Tien Le is a Legal Assistant with Peiffer Rosca Wolf Abdullah Carr & Kane, A Professional Law Corporation. Based in our San Francisco office, Tien focuses on our practices concerning civil rights, student loans, and appellate advocacy.


text:
Here is an antidote to savor when overcome with gloomy thoughts about the nation's future. When this year's Nobel Prizes for physics, chemistry, medicine and economics were handed out, American academics won nine awards compared to one each for Britain and Belgium. The rest of the world got zero for science.
U.S. higher education has its shortcomings, but it still has the capacity to produce new discoveries and new technology to strengthen the nation's medical system and economy while providing new jobs to its progeny. As Bret Stephens noted in The Wall Street Journal, since 2000, Americans, including immigrants from other nations, have won 21 of 37 physics Nobels, 18 of 33 in medicine, 22 of 33 in chemistry and 27 of 30 in economics. An impressive record indeed.
The Nobel Prize for Chemistry this year was awarded for the development of computer models that can predict chemical reactions for creating new drugs and other uses. The winners were Martin Karplus of Harvard University, Michael Levitt of Stanford University and Arieh Warsel of the University of Southern California.
The Nobel Prize for Medicine was awarded to James E. Rothman of Yale University, Randy W. Schekman of the University of California at Berkeley and Thomas C. Sudhof of Stanford. Their research into the role of vesicles in cell structure leads to a better understanding of neurological and immunological diseases and diabetes.
The Nobel Prize for Economics was shared by Eugene Fama and Lars Peter Hansen of the University of Chicago and Robert Shiller of Yale for work showing that asset price trends cannot be reliably predicted in the short term but can be predicted over longer terms. Their work has led to the rise of index funds as investment vehicles and to the creation of the widely used Case-Shiller index for measuring trends in real estate prices.
The Nobel Prize for Physics, perhaps the most prestigious Nobel science award, went to Peter Higgs of Britain and Francois Englert of Belgium for their simultaneous but separate 1964 papers on how subatomic particles get their mass. Last year the CERN particle physics accelerator laboratory near Geneva confirmed their theory by discovering the long-elusive particle known as the Higgs Boson, or so-called "God particle."
Two non-scientific Nobels are awarded, for literature and contributions to world peace. Avoiding the often-repeated criticism that recent choices in literature have been obscure and unreadable, the Swedish Academy this year awarded the literature prize to the highly accessible Canadian author Alice Munro, whom the Academy rightly hailed as a "master of the contemporary short story."
The Norwegian Nobel Committee, following a recent pattern of promoting international organizations instead of heroic individuals, passed up the sentimental favorite, 16-year-old Pakistani school-girl and Taliban opponent Malala Yousafzai, and gave the Peace Prize to the Organization for the Prohibition of Chemical Weapons (OPCW), which has been assigned the yet-to-be-accomplished task of removing chemical weapons from Syria. It has been reasonably suggested that the Norwegian committee was again betting on the outcome.
Hopefully, it will turn out to be more prescient than in the 2009 Peace Prize awarded to President Barack Obama.
And maybe the OPCW's work in Syria will belatedly help validate Mr. Obama's credentials in the peace-making realm.
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text: OAKLAND -- A quick injury roundup because the A's 19-inning victory on Monday night took its toll. Outfielders Coco Crisp (hamstring) and Chris Young (quadriceps) are out of the lineup against the Angels and could be out a few days. Manager Bob Melvin said the A's are in wait-and-see mode on both players with the hope that they can avoid the disabled list.


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|193 posts found
I'm not against P2P and I'm not against F2P I like all models(to some extent).
But I hear it tossed around a lot, that P2P games make more money and get more updates and are hence better. If this is true, why are almost all the P2P games going F2P? Do they just hate money?
Even Rift, which was every P2P die hard's anthem. "Look at Rift! That game pumps out so much content because it is P2P!" well...they went F2P. Were they tired of making all that money?
Other than WoW, Eve is one of the only hold outs with a sub. But even that game allows players to basically buy in game currency through the plex system. (buy tons of plex and sell it all in game) so it's not a pure P2P game with everyone equal regardless of money spent.
I am just curious what the reasoning here is. The P2P games are better, because they make more money, yet they all have to go F2P. Something feels off...
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Joined: 11/22/05
"what a boring life, HATING everything" -Gorilla Biscuits
Never really heard it argued that they make more money (not to say it doesn't happen) I just don't think it's all that common. Most want subs simply because it costs less to have everything a game offers ( if it's based solely on a sub model). Even Hybrids like TOR etc.. Are better experiences (for the buck) with a sub over what it costs without.
For every minute you are angry , you lose 60 seconds of happiness."-Emerson
It is a sign of a defeated man, to attack at ones character in the face of logic and reason- Me
Uhh, games eventually get old and start losing subscribers. The publishers make a big "Hoo-Hah" press release about going F2P and then all the grabasses who never paid any attention to the game before start trampling the elderly and small children to play yet another free game. They then leach off of that sucker until they're bored or until another game they never tried goes F2P and the cycle starts all over.
Hard Core Member
Joined: 11/15/09
The only luck I had today was to have you as my opponent.
wow isn't. eve isn't.
it's the bad p2p games that go f2p. not all of them.
Personally, I just think there are too many MMOs and not enough players to sustain most games. MMOs are so different from every other genre, the games are made and then new ones come out but the only ones don't go away. The old MMOs are still trying to keep their players faithful to them, and the new ones are trying to lure them away.
I think back to the old days and how people were more committed to their MMOs but were we really? Or was it just a lack of choice?
I recall playing Meridian 59 with my brothers, and we were hardcore about that game. We loved it to death and had no intentions of quitting. But then EverQuest was coming out, we read the articles and saw the screenshots. So we hopped on board the EverQuest mobile! Then I believe it was another couple years or so until Asherons Call came out and my brothers and I decided to try that, and then Anarchy Online etc etc.
I think WoW and EverQuest 2 were the last two MMOs I actually spent more than a year on respectively.
The point of all this rambling, is back then MMOs took a long time to come out. We didn't have a new game every few months to try out and convert to. I think about the last year or so and I've had GW2, TSW, Defiance, Dragon's Prophet, Neverwinter, Marvel Heroes, and FFXIV beta all installed on my computer and launched/beta'd to different degrees. That's more MMOs than my first TEN years of MMO playing combined!
Originally posted by Robokapp
So in your opinion, WoW and Eve are the only two good P2P MMOs ever made? And since you hate all F2P MMOs... is it your opinion that WoW and Eve are the only two good MMOs ever made, period?
Novice Member
Joined: 1/03/08
From what I've seen, F2P does make more money on less people. I'm not saying a F2P game with 5m players would make less money than P2P. There is a number where the number of players has reach to break even between F2P and P2P.
IE. Less than 500k the game would be better off F2P than P2P, but over that its more a question of what the Dev wants to do. Wow has an item shop, while very limited and silly expensive it is there. And the money they made from the like 5 mounts they have on there likely would buy them a very nice castle on a hill somewhere.
The freemium model of EQ2 is the only one that bothers me. A vast majority of the new art assets for armor and weapons are on the marketplace instead of being available VIA in game means. This is the only thing that worries me about EQN is that it will be a freemium model like EQ2 and have a cash shop where all the decent looking stuff ends up.
So your sub may get you bonus xp or no queue time but the cool looking gear is all on the item shop. Sony has actually shown this plan with PS2 actaully, with the only difference between a Sub and a Free is bonus xp and no server queues.
Elite Member
Joined: 9/27/11
World > Quest Progression
IMO it's because most titles are more of the same. While subs do give you a sustained income better suited to execute projects (content) you actually have to get people to pay for them. Why pay for game A if game B looks and tastes similar without an upfront cost? Many players don't anymore due to how many are free(ish) and so you see more F2P conversions. IMO these conversions are a way to get your core base that used to just pay 15.00 a month paying more so that others can play for free while keeping the doors open. I'm concerned that as new F2P(ish) titles come out like EQN that the "whales" (see above) will move towards new waters and leave old titles to close or tighten the cash shop grip.
Novice Member
Joined: 8/06/03
All you are going to get in this thread are armchair economists and doomsayers.
Mmorpgs are notorious for keeping their numbers veiled either in terms of population (active accounts, forum accounts, registered accounts) or profit (other than quarterlies dependent upon knowledge of investment/upkeep).
Sometimes games fold even when they are turning a profit for various reasons such as occupying a valuable spot in some perceived gaming real estate or genre branding. I suppose if another project needs team members and the speculation is high on the new venture then they might even scrap the old for team resources. Hard to say what the monetary implications are for some of these decisions.
The mmo world seems primed for a massive shake-up in my opinion which is worthless as I sit in this armchair (babbling as I take a break from reviewing a project set)
Elite Member
Joined: 9/27/11
World > Quest Progression
Originally posted by pfcgriff
They have talked about putting cosmetics in the game as recipes, not sure if they have actually done it though. My worry for EQN is that there will be no sub option... at which point SoE could pull what NC pulls where you get changed more than a sub to enjoy the game. I was also bothered by the cosmetic cost even with a sub with EQ2. It's been topped by the RNG lock boxes and reagent needs of other MMOs.
Apprentice Member
Joined: 11/22/05
I wouldn't say it's even just the bad ones. It's the mediocre ones that can't stay a float as p2p. These games that can't keep people playing for more than a month or two at a time don't really keep people longer as f2p. they just don't have the pay barrier that kept people from playing when they were p2p.
They still have the same turn over but they get way more people trying it. Way more people spending small amounts and people come and go and come back more often.
A good game keeps it's players, it doesn't matter what it's pay model is. f2p does however have the ability to earn more per month from a player than p2p does.
Hard Core Member
Joined: 11/15/09
The only luck I had today was to have you as my opponent.
Originally posted by Fendel84M
no, in my opinion wow and eve are some good mmo's. you asked why all are going f2p, i gave you two examples that aren't.
I don't hate f2p mmo's, just the cash shops. I play a f2p mmo in my eve browser while mining. I think they're great temporary distractions, much like addictinggames.com games are - which are also f2p but without the cash shop. yet not MMOs.
so in your opinion, are all p2p mmo's going f2p like your title says ?
Advanced Member
Joined: 6/13/12
Because they don't make more money.
Hard Core Member
Joined: 6/06/12
We live in a fantasy world, a world of illusion. The great task in life is to find reality.
Originally posted by Fendel84M
Theres only 1, maybe 2 P2P games that make more money then if they go F2P. Wow and Eve. The market share is not large enough to support so many P2P games. Just like in in 1999 when only 3 major games were P2P, the same holds true today in 2013.
Elite Member
Joined: 6/01/04
Originally posted by Fendel84M
Well back then each game was built differently than the next. Sure, some of the basics were the same, but DAoC went with RvR, AO was sci-fi with a unique character build system (also the first use of instances and flying mounts), AC was more sandbox type progression than the others, etc.
Then WoW came out. It was new, it was a bit more polished at launch than any of the other games that came before it and it was made by a company that was known for quality games (at one point). It grabbed almost the entire genre. It pulled in players who may have never touched an MMO otherwise.
And then it started.
MMOs began popping up everywhere, Imports from the east, Movie IPs, etc. Everyone saw WoW and said "We can do that too!"
Players began bouncing around from game to game. New MMOs would launch with a million box sales and finish out the month with less than 200k subscribers. No one wanted to pay for a game they were pretty much already playing, or the games launched in such a disastrous fashion it just scared people away. Players were scattering out across an expanding ocean of new games, thinning the populations of already existing games. It became harder for developers to keep people subbed.
So you are pretty much correct in the 'too much supply, not enough demand' area. But it goes a bit deeper in that a lot of the supply fell short on bringing anything new or worthy to the genre.
Also, I do want to apologize in advance. If this seems a bit all over the place it's due to the fact I am riding a pretty big sugar high atm. The girlfriend is trying a ton of different frosting recipes for a family event and I am the default taste tester. I may just end up in a diabetic coma by sunrise today...
Advanced Member
Joined: 2/02/07
Most of my posts get deleted.
Games aren't about the games anymore, it's about how much you can make off of it. F2P offers more to the company than a sub can.
Originally posted by salsa41
Apprentice Member
Joined: 10/18/05
P2P games can make the most money, but you make more if you make a cheap level game like farmville, advertise it as full P2P game, then reduce it to what it is (a low budget F2P) then you make more money add the cost to make the cheap game in itself
More like ask yourself this, make a farmville F2P with a low budget of lets say $50,000 and make $150,000 off it, Or make a $50 million P2P and make $150 mil off it.
Alot easier and less risky to make a farmville than to make a WoW
And where is the market going? its not going to put the millions to make lets say SWTOR right the first time, why instead you can make a low budget game that is compatable for your cell phone, tablet, and low end laptop, make it F2P and make a little cash with lower risk, as opposesd to alot cash P2P with a high risk, high budget game.
Im afraid after all the milltions spent on SWTOR, nobody is going to invest on a large budget game in a long time
Gold spammers and Farmville in a round bout way runied gaming for now, suprised that businesses did jump on the F2P garbage concept years eariler.
Hard Core Member
Joined: 5/20/07
I got so much trouble on my mind Refuse to lose.
Several reasons:
1. P2P model is outdated. - You can not charge subscription for a similar game that competitors give for free(ish). This is simple rule of market.
2. Subscription makes more money if you have enough subscribers. - Simply there is profit line where P2P game makes less money than F2P
Said that. I dont think F2P is here to stay either.
I think market is moving towards B2P as model that makes more logic both for player and publisher.
Elite Member
Joined: 3/24/05
Originally posted by Lobotomist
Well even if they do they will still have a cash-shop, that is simply to good of a way to get money for them to pass up. I think that the current F2P model will stay around for a good amount of time actually and become more and more common. Maybe even to the point of moving in to single player games.
When do the good fight turn bad, Smedley is a good example.
This have been a good conversation
Originally posted by Robokapp
You said the bad P2P games go F2P, the only P2P games that haven't gone F2P(I believe) are FFXI, WoW, and Eve. Oh! And Ultima Online. So that's 4 that I can think of. Based on your statement every other P2P game was bad, so it went F2P.
And it's not really a matter of opinion. It does seem like all P2P games are going F2P. I'm still on the fence about F2P, I think some games have taken things a bit too far with their cash shops.


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A national wholesale retail chain is set to open its first store in East Tennessee one month from today.
Costco is expected to open on November 9 in Farragut, at the corner of Lovell Rd. and Kingston Pike.
If you want to be ready to shop as soon as the doors open, you can go ahead and buy a membership now.
"We're finishing construction in the next three weeks, we've started on Sunday signing members up. We have a great grand opening offer that we hope everybody's going to take advantage of," said Todd Galanti, the warehouse Manager.
If you're interested in a membership, trailers are set up in the parking lot where employees will help you sign up now.


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A local non-profit organization, the Mercy Project, is trying once again to break the official Guinness World Record for the longest baseball game this weekend.
The game started at 7:30 Thursday evening and is scheduled to end at 9:30 Saturday night at American Momentum Ballpark in Bryan. The group says 56 players from across Texas will participate.
The ultimate goals of the event are to create awareness about the plight of child slaves around the world and raise money that will directly help children in slavery in Ghana, Africa. The Mercy Project estimate the event will raise more than $40,000 to fund its charitable projects.
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The 2012 Kentucky volleyball season started off with a bang Friday night. In UK's first match of the Kentucky Classic, UK got through two tough sets, then handled North Carolina in the third to claim match No. 1 with a 3-0 sweep.
Kentucky clearly looked like the superior team athletically on the floor, but North Carolina, a team receiving votes in the coaches' poll, showed that it was no pushover. North Carolina used a multitude of different shots, taking advantage of a sluggish UK defense early. But not to be phased by UNC's craftsmanship; UK kept its poise and fought back with each Tar Heel run through the first two sets.
"Very happy with that win," said Kentucky head coach Craig Skinner. "Obviously with the first match of the season you don't know what to expect. Our concentration at the end of game's one and two I think were the difference in that match and us being able to perform when the match is close is a good sign early."
Early on, it was the Lauren O'Conner show for UK. The sophomore outside hitter came up with several huge shots in the first two sets in clutch situations to extend runs or pull UK back into the set. She looked virtually unstoppable. O'Conner finished set one with six kills on 11 attempts, hitting .545 to lead Kentucky to a tight 25-23 set one victory.
Set two was just as tight, but a couple of new faces to the starting lineup made the biggest contributions at the middle position.
Junior middle blocker Alexandra Morgan had a flawless second set, banging out five kills on eight attempts, hitting .625 for the set. Morgan had not seen much playing time at all in her career, but throughout the summer and preseason, she has become a revelation of sorts for a team in desperate need at the middle position.
"(Morgan) is really good in tight situations and she performs under pressure and we saw that tonight," said Skinner. "She is very dynamic off of one foot and probably one of the best slide-attackers overall that we have had in the program. She is a very physical and dynamic blocker and her numbers were very good tonight and the good thing is she will only continue to get better."
But you need two middles to play the game, and freshman Sara Schwarzwalder fit the bill. Skinner said he's really liked what he's seen out of the rookie so far in preseason, but an injury late in camp had held her out of several practices and limited her in the Blue/White scrimmage. Missing so much time as a freshman, Skinner wasn't quite sure what he was going to get out of her, but he had enough faith to stick her in the lineup to get her feet wet.
She pulled through big time. Rarely did she look like a freshman out on the court in front of a raucous opening night crowd at Memorial Coliseum. She was vocal and took control when she needed to, and when the opportunities came, she made the most of them. She kicked in four kills of her own on her way to a .667 hitting percentage for the set as UK took set two over UNC in another close one, 25-22.
Schwarzwalder wasn't the only freshman seeing action Friday night, however. Shelby Workman came off the bench and was dynamic in the back row as Skinner opted for offense over defense. While Workman was potent from behind the stripe, she more than held her own passing and defending. She finished with just one kill, but recorded five digs on the night.
The performance from the youngsters has Skinner encouraged about what they can bring to the table.
"They are both very physical and skilled players and they certainly didn't play like they were freshman tonight and that is a huge advantage for us," said Skinner. "Sara (Schwarzwalder) driving hard in the middle and getting up and getting a couple of blocks and Shelby (Workman) the way she passed and swung out of the back row that is a weapon we didn't have last year. (We definitely) benefit from it and I am proud the way they stepped in their first match."
Kentucky blew it open in set three, getting out to an early 9-3 lead. After pushing it to 14-6, Kentucky cruised comfortably to a 25-14 victory in the third set to take the match in straight sets. It marked the first time since 2007 that UK opened up the season with a 3-0 sweep.
It was an impressive performance by Kentucky who had a big crowd behind their backs. A crowd of 1,621 showed up on opening night at Memorial Coliseum to root on the Big Blue, one of the largest attendance numbers for an opening game in Skinner's tenure.
The fan support is something that Skinner, who wins his opener for the seventh time in his eight years at UK, believes his team feeds on when the going gets tough. He's hoping for a similar showing Saturday night.
"Great crowd, great energy and very knowledgeable and that is a sign of our program continuing to get better," said Skinner. "You see a lot of people you have never seen before in the stands, it's a huge advantage for us and I hope they come back tomorrow."
Kentucky (1-0) will have a double header tomorrow in the final day of the Kentucky Classic. They will face Lipscomb in the morning session, scheduled for 11 a.m. at Memorial Coliseum. In the night cap, Kentucky will host Long Beach State who beat Lipscomb in the early match on Friday, at 8 p.m., potentially looking for the Kentucky Classic title.


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Carry the Love of Jesus to the Little Ones
One young boy came the child development center every day to have something to eat. It was quickly discovered though that he was seeking something more.
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Metro Manila, seen as a "land of opportunities," has lured many people from different provinces to work and live here. About 35 percent of the families live in informal slum areas that are unfit for settlement, such as in low-lying flood plains, on riverbanks, near highways and railroads, and on dumpsites.
Life in El Salvador
El Salvador is the smallest country in Central America. Located between Guatemala and Honduras, it possesses 21,041 square kilometers (about the size of Massachusetts) and is tropical, with an average temperature of 30° to 35°C (80°to 95°F). The land is mostly mountains covered with tropical rainforest, with its highest peak being El Pital at 8,957…
Why Do Child Development Centers Close?
We partner with more than 5,000 churches worldwide to implement our sponsorship program. And last year, 95 centers closed, about 1.7 percent of the centers open at the time. The number of child development centers that close each year varies. They close for a variety of reasons, and each case is different.
UPDATED: Mar. 6, 2010 – This downloadable PDF lists all the child development centers in Haiti and categorizes each center as: not directly affected, moderately affected or significantly affected.
Six child development centers and one child survival program previously designated as not directly affected have recently reported several children and siblings of sponsored children as…
Images of Child Development Centers in Haiti
UPDATED: Jan. 29, 2010 – List of child development centers affected by the Haiti earthquake
Here is a Google Earth image showing the approximate location for the earthquake's epicenter in relation to our child development centers.
The image is just intended to give perspective not definitively identify where all the centers are located. However, there…
Frequently Asked Questions
Does my Compassion child attend school at Compassion's child development center?
I like to listen. My wife will tell you I'm not very good at it. But I really do like to listen to the way people say things … and the meaning behind certain words or phrases. I recently tried an experiment. I paid close attention to some of the things we say around the…


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Cooking and Baking
What to do with defrosted scallops?
In an effort to clear some space in my chest freezer, I removed a bag of frozen scallops and have thawed it. The ingredient list on the bag just lists scallops, nothing else, but they still look a bit "wet". I was going to just do a simple saute with them, but now I'm not so sure. What would you do with them, Serious Eaters? And, no, I'm not going to throw them out and drive to the store for fresh ones :)
Talk is closed, but that doesn't mean the conversations have to stop!
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Sarah Medina
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8 U.S. Code § 1731 - Implementation of an integrated entry and exit data system
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(a) Development of system
In developing the integrated entry and exit data system for the ports of entry, as required by the Immigration and Naturalization Service Data Management Improvement Act of 2000 (Public Law 106–215), the Attorney General and the Secretary of State shall—
(1) implement, fund, and use a technology standard under section 1379 of this title at United States ports of entry and at consular posts abroad;
(2) establish a database containing the arrival and departure data from machine-readable visas, passports, and other travel and entry documents possessed by aliens; and
(3) make interoperable all security databases relevant to making determinations of admissibility under section 1182 of this title.
(b) Implementation
In implementing the provisions of subsection (a) of this section, the Immigration and Naturalization Service and the Department of State shall—
(1) utilize technologies that facilitate the lawful and efficient cross-border movement of commerce and persons without compromising the safety and security of the United States; and
(2) consider implementing the North American National Security Program described in section 1751 of this title.
Source(Pub. L. 107–173, title III, § 302,May 14, 2002, 116 Stat. 552.)
References in Text
The Immigration and Naturalization Service Data Management Improvement Act of 2000, referred to in subsec. (a), is Pub. L. 106–215, June 15, 2000, 114 Stat. 337, which amended section 1365a of this title and enacted provisions set out as notes under sections 1101 and 1365a of this title. For complete classification of this Act to the Code, see Short Title of 2000 Amendment note set out under section 1101 of this title and Tables.
Abolition of Immigration and Naturalization Service and Transfer of Functions
For abolition of Immigration and Naturalization Service, transfer of functions, and treatment of related references, see note set out under section 1551 of this title.
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