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A virtual memory unit has a plurality of directory and buffer store levels for storing page descriptor information. The memory directories and a least recently used (LRU) device constructed from the same type of standard cache address directory part include parity error detection circuits. The virtual memory unit further includes a state machine for defining sequential states used in generating control signals for directing the memory unit's operation in translating virtual addresses into physical addresses. Programmable control circuits which generate the required input data and control signals applied to the directories and LRU device for reading and updating their contents further include the retry facilities which, in response to certain types of error situations, alter state machine sequencing to again try the virtual to physical address translation with a fresh copy and the LRU replacement operations in a way to improve robustness.
1. A virtual memory unit (VMU) including:
a set associative memory having a plurality of parallel addressed levels for storing information pertaining to a number of predetermined sets of address translations, each level having a buffer store having a plurality of locations for storing descriptor information for performing address translations and a directory circuit having address and data inputs for receiving address and tag portions respectively of a common input virtual address, said directory circuit including a random access memory (RAM) containing a plurality of storage locations for storing address tags for designating which predetermined set of address translations is actually stored in corresponding locations of said buffer store of said each level containing said descriptor information, a comparator for generating match output signals for indicating detection of a true comparison indicative of a match between the address tag contents of said directory RAM storage locations specified by said address portion of said input virtual address and said tag portion of said virtual address and error detection circuits for detecting an error in said address tag contents of one of said directory locations producing said match output signals;
a least recently used (LRU) device having a number of addressable storage locations for storing level information for said plurality of levels used for generating signals for indicating a next level in said buffer store of one of said plurality of levels in said next level into which descriptor information is to be written;
state machine apparatus for generating a plurality of states for sequencing said VMU through a series of operations for translating said input virtual address into a physical address; and
control means coupled to said state machine apparatus, to said LRU device and to said set associative memory, said control means generating control signals for accessing and updating said descriptor information contents of said set associative memory and said level information contents of said LRU device in addition to generating hit output signals for signalling detection of a hit condition, said control means including retry means coupled to said error detection circuits, said retry means causing said state machine apparatus to alter said plurality of states and said control signals applied to said LRU device as a function of whether said match was detected by said comparator of said directory circuit of one of said plurality of levels and which one of said plurality of levels detected said match, said plurality of states and said control signals being altered for recovering from said error which is transient in nature.
2. The apparatus of claim 1 wherein said control means includes logic means which in response to said error signal detected by said error detection circuits of said directory circuit of one of said plurality of levels on one of said plurality levels and said match on another one of said levels generates signals for inhibiting said retry means from initiating a retry operation and for causing said LRU device to carry out level replacement in a normal manner.
3. The apparatus of claim 1 wherein said control means includes logic means which in response to said match output signals indicating that no match was detected on any of said plurality of levels and that said detection circuits of said directory circuit of one of said plurality of levels detected an error on one of said levels, generates signals for causing said LRU device to store information in one of said number of addressable storage locations for indicating that said one level is the least recently used level making said one level a next candidate for replacement.
4. The apparatus of claim 1 wherein said programmable control means includes logic means which in response to signals from said error detection circuits of said directory circuit of said plurality of levels that a plurality of said levels detected errors, generates signals for causing signaling of an absence of said hit condition on said plurality of said levels and invalidating one of said plurality of levels thereby causing said other levels to have corresponding locations within their buffer stores replaced with fresh copies of descriptor information fetched from memory.
5. The apparatus of claim 1 wherein said VMU further includes error management means coupled to said control means and to said error detection circuits of said directory circuit of each of said plurality of levels, said error management means including programmable control means coupled to said state machine apparatus and to said error detector circuits, said programmable control means monitoring occurrences of said error and upon detecting occurrences of more than one error during the same translation sequence defined by said state machine apparatus sequencing through a predetermined sequence of states, generating an unusual event signal for indicating detection of a transient fault within said VMU.
6. A method for ensuring robust operation of a virtual memory unit (VMU) having a multilevel set associative memory having first and second inputs for receiving address and tag portions of input virtual addresses, said memory having a plurality of buffer stores corresponding in number to a number of ways of performing address translations for storing descriptor information for performing said address translations and a corresponding number of directories, each directory having a plurality of storage locations for storing tags designating which address translations are actually stored in corresponding locations within a corresponding one of said buffer stores, a corresponding number of comparator circuits, each comparator circuit for generating match output signals for signalling true comparisons indicative of matches between the tags contained in said plurality of storage locations of an associated directory specified by said address portions of said virtual addresses and a corresponding number of error detection circuits, each error detection circuit for detecting errors in said tags contained in said plurality of storage locations of said associated directory which produced said match output signals, said VMU further including a least recently used (LRU) device having a plurality of addressable storage locations for storing level information used for generating LRU signals for indicating those levels into which new descriptor information is to be written during level replacement operations, said method comprising the steps of:
(a) generating signals corresponding to a plurality of states by a state machine element used for sequencing said VMU through a series of operations for translating said input virtual addresses into physical addresses;
(b) generating control signals by control circuits coupled to said state machine element, said associative memory and to said LRU device for updating the descriptor information of said associative memory and said level information of said LRU device in addition to generating hit output signals for signalling detection of a hit condition; and,
(c) retrying operations during said translating by altering generation of said signals in step (a) when errors are detected by one of said number of error detection circuits so as to enable recovery from transient faults.
7. The method of claim 6 wherein said method further includes the step of:
(d) generating signals by said control means in response to said error signal being detected on one of said multilevels and when a true comparison corresponding to a match is detected by one of said error detection circuits on another one of said multilevels for inhibiting said retry means from initiating a retry and for causing said LRU device to carry out level replacement in a normal manner.
8. The method of claim 6 wherein said method further includes the step of generating signals by said control means in response to said match signals indicating that no true comparison representative of no match was detected on any of said levels and that one of said detection circuits detected an error on one of said levels, for causing said LRU device to store information in one of said plurality of storage locations for indicating that said one level is the least recently used level making said one level a next candidate for replacement.
9. The method of claim 6 wherein said method further includes the step of generating signals by said control means in response to signals from a plurality of said error detection circuits that a plurality of said levels detected errors, for causing signalling of an absence of said hit condition on said plurality of said levels and for invalidating one of said levels thereby causing other levels to have corresponding locations within their buffer stores replaced with fresh copies of descriptor information fetched from memory.
10. The method of claim 6 wherein said method further includes the step of:
monitoring the occurrences of errors detected by said number of error detection circuits; and,
signalling the detection of an unusual event for indicating the occurrence of a transient fault when more than one error is detected to occur during execution of the same translation operation by said VMU.
1. The patent application of Richard A. Lemay, Steven A. Tague and William E. Woods entitled, "A Virtual Memory State Machine," filed on Oct. 5, 1990, bearing Ser. No. 07/593,903, which is assigned to the same assignee as this patent application.
2. The patent application of George J. Barlow, James W. Keeley, Richard A. Lemay, Jian-Kuo Shen, Robert V. Ledoux, Thomas F. Joyce, Richard P. Kelly and Robert C. Miller entitled, "Recovery Method and Apparatus for a Pipelined Processing Unit of a Multiprocessor System," filed on Oct. 5, 1990, bearing Ser. No. 07/593,498, which is assigned to the same assignee as this patent application.
3. The patent application of Forrest M. Phillips entitled, "Least Recently Used Replacement Level Generating Apparatus," filed on Sep. 1, 1989, bearing Ser. No. 07/402,192, issued as U.S. Pat. No. 5,125,085 on Jun. 23, 1992 and which is assigned to the same assignee as this patent application.
4. The patent application of Robert V. Ledoux, Richard P. Kelly and Forrest M. Phillips entitled, "Ring Reduction Logic Mechanism," filed on Mar, 31, 1989, bearing Ser. No. 07/332,258, issued as U.S. Pat. No. 5,117,491 on May 26, 1992 and which is assigned to the same assignee as this application.
5. The patent application of Forrest M. Phillips, Thomas F. Joyce and Ming-Tzer Miu entitled, "Apparatus and Method for Address Translation of Non-Aligned Double Word Virtual Addresses," filed on Jan. 5, 1989, bearing Ser. No. 07/294,528, issued as U.S. Pat. No. 5,051,894 on Sep. 24, 1991 and which is assigned to the same assignee as this application.
1. Field of Use
The present invention relates to data processing systems and, in particular, to cache memory systems.
2. Prior Art
It is known to provide parity check circuits for detecting errors in the addresses and information read from the directory or cache store during a read cycle of operation to generate signals which simulate a condition that the requested information was not stored in cache store although it was stored and read out. This causes a backing store cycle of operation to be initiated for read out of a correct version of the actual requested information from a backing store containing error detection and correction (EDAC) circuits. This system is disclosed in U.S. Pat. No. 4,084,236 which issued on Apr. 11, 1978.
While the above system improves the reliability of the information being provided, it presumes that the states of the cache address directory circuits are faulty. In other words, it is not very fault tolerant.
Faults are generally classified in terms of their duration, nature and extent. The duration of a fault can be transient, intermittent or permanent. A transient fault, often the result of external disturbances, exists for a finite length of time and is nonrecurring. Thus, the ability to retry or recover from such transient faults becomes important for a system to be fault tolerant.
This is particularly important in cases where the cache unit is utilized as part of a virtual memory unit, responsible for translating virtual addresses into physical addresses. Accordingly, it is a primary object of the present invention to provide a virtual memory unit which is more resilient to various types of error conditions.
It is a further, more specific object of the present invention to provide a virtual memory unit which incorporates resiliency features without increasing the complexity of the unit.
The above and other objects of the present invention are achieved in a preferred embodiment of a virtual memory unit (VMU). The VMU includes a plurality of directory and buffer store levels for storing quadrant, segment and page descriptor information. The memory directories which store page descriptor information and an associated least recently used (LRU) device are constructed from the same type of standard cache parts which include parity error detection circuits. These circuits operate to detect errors in the directory addresses being accessed. The VMU further includes a state machine for defining sequential states in generating control signals for directing the VMU in translating virtual addresses into physical addresses. The state machine is implemented as disclosed in the referenced related copending patent application entitled, "A Virtual Memory State Machine."
Programmable control circuits which generate the required input data and control signals applied to the directories and LRU device for reading and updating their contents further include retry facilities. The control circuits, in response to certain types of parity error conditions, alter state machine sequencing and mode of operation to again attempt a virtual address translation with a fresh copy of the descriptor fetched from memory and alter the LRU device replacement operation in a way which improves the VMU's robustness.
For example, when the VMU detects a hit condition on one level and a parity error is detected on the other level, no retry is initiated. Also, the LRU device is permitted to carry out replacement in a normal manner, since the level which reported the problem becomes the next candidate for replacement.
Another situation or mode is when neither level reports a hit indicating that the descriptor is missing and one of the levels detects a parity error. The control circuits, instead of replacing an arbitrary location depending on the state of the LRU device (the previous LRU information), the VMU substitutes its knowledge of which level had the parity error and causes the LRU device to make that error reporting level the one which is least recently used and the next candidate for replacement.
The present invention operates in a different fashion in the situation where multiple levels (i.e., two in the preferred embodiment), report parity errors. The VMU selects one of the levels for immediate replacement and the other level during a later translation attempt.
Finally, the case of a double hit is treated as if both levels had signalled misses. The control circuits cause one level to be invalidated, while the other level is replaced with a fresh copy of the descriptor obtained from memory in the manner previously described.
The above different modes of operation enable the VMU to establish different categories of error situations which are responded to so as to eliminate the effects of transient faults. In the situations where a second error is detected during the execution of a command, this is detected and reported as an unusual event (UEV) condition indicative of a persistent error.
The novel features which are believed to be characteristic of the invention both as to its organization and method of operation, together with further objects and advantages, will be better understood from the description in the following section when considered in connection with the accompanying drawings described in this section. It is to be expressly understood, however, that each of the drawings is given for the purpose of illustration only and is not intended as a definition of the limits of the present invention.
FIGS. 1a through 1c illustrate in block diagram form, a virtual memory unit (VMU) which incorporates the present invention.
FIG. 2 is a block diagram of the page descriptor section of FIG. 1.
FIGS. 3a and 3b are flow diagrams used in describing the operation of the present invention.
The VMU 40 translates virtual addresses received from one of the main units (A-unit) of a central processing unit (CPU) of a system into physical addresses for fetching instructions from an I-cache unit and operands from an E-cache unit. For further information regarding this system, reference may be made to the referenced related patent applications. FIGS. 1a through 1c are block diagrams of the virtual memory unit (VMU) 40 which incorporates the present invention. As seen from FIGS. 1a through 1c, VMU 40 includes a number of different functional areas or sections. The sections include an input register section 40-2, an access check section 40-4, an ALU section 40-6, a page descriptor (PD) associator section 40-8, a segment descriptor (SD) section 40-10, a FIFO section 40-12 and an error management unit 40-200. Additionally, VMU40 has a VMBUS section 40-14, a pointer (PTR) bus section 40-16, an exception vector generator section 40-18, a status section 40-19 and a control logic section 40-30.
The input register section 40-2 includes the virtual address (VAR) input clocked registers which store or capture the input address, control and command signals applied by the A-unit 20-4 at the beginning of each cycle. These registers include a 2-bit position ring number (RN) register 40-20, a 30-bit position virtual pointer register 40-22, a 4-bit position control register 40-24 and a 9-bit position (includes parity) command register 40-26. Address and command parity are checked at the beginning of each command sequence.
The ring number contents of register 40-20 are applied as an input to access check section 40-4, FIFO section 40-12 and control logic section 40-30. The current pointer contents of virtual pointer register 40-22 are applied as an input to ALU section 40-6, PD associator section 40-8, SD section 40-10 and FIFO section 40-12 via PTR bus section 40-16. The contents of control register 40-24 and command register 40-26 are applied as inputs to control logic section 40-30. Also, the contents of register 40-24 are also applied as an input to access check section 40-4.
The access check section 40-4 performs the various access and security monitoring functions. These include read and write access checks when required, access checking for read-modify-write (RMW) operations, ring bracket checks for E-cache address pointers and gate bracket security checks for call instructions. The type of access check performed is specified by the control code passed to VMU40 by the A-unit with the virtual address pointer. For operand access checking, the read (R) and write (W) permission bits with the segment descriptor access check word (SD ACW) may be checked, the ring brackets R1, R2 may be checked and traps (access fault) may be issued.
As shown in FIG. 1a, section 40-4 includes a security monitor block 40-40 and a 5-bit position latch 40-42. The security monitor block 40-40 includes a PAL device which receives the ring number signals (VRN0-1), control signal READOK derived from A-unit signal A-SNOK indicating the virtual address pointer is within the range of the current procedure segment, and segment descriptor access check word (SD ACW) signals from SDASM section 40-10 via VMBUS section 40-14.
The security monitor PAL generates as outputs, effective ring number signals V-REF, effective ring bracket signals R1 and R2, and an access fault signal (ALARM). The effective ring bracket signals R1 and R2 are applied as inputs to latch 40-42, along with the privileged (PR) bit obtained from the SD ACW word. The R1 and R2 ring bracket signals and the PR bit are passed along to I-cache 60-2 together with the page frame number (PFN). The PFN is obtained from the page descriptor for the associated virtual address pointer if paged or generated by VMU40 if unpaged. The access fault signal (ALARM) is one of the status signals which is applied as an input to the control logic section 40-30.
The ALU section 40-6 performs the required arithmetic operations for carrying out address development and boundary/size checking functions. As shown, section 40-6 includes an A input multiplexer 40-60, a B input multiplexer 40-62 and an adder 40-64. The section 40-6 further includes a pair of output registers corresponding to a PTR1 register 40-66 and a STAR register 40-68 arranged as shown. The PTR1 register 40-66 connects to the PTR bus 40-16 while the STAR register 40-68 connects to VMBUS 40-14.
The adder 40-64 is controlled by a PAL device 40-69 which receives signals from control logic section 40-30 as described in greater detail herein. The adder 40-64 generates a carry out signal CN12 for indicating an overflow condition at a 1024 word boundary. This signal is applied as an input to one of a group of PAL devices of status section 40-19 which results in the generation of a signal SIZEOK. The SIZEOK signal is applied as another one of status signals to control logic section 40-30 along with signal CN12. The multiplexers 40-60 and 40-62 provide 32-bit operand signals as inputs to adder 40-64 from the PTR bus 40-16 and VMBUS 40-14 for extracting and scaling the various fields required by the virtual to physical address translation procedures or rules. Additionally, multiplexer 40-62 provides as B operand inputs, constants having the values 0, 1 and 8 as indicated.
PDASM section 40-8 includes a two-level set associative cache memory which is used to store and retrieve 20-bit page descriptors used by the virtual memory system. These descriptors, which are stored in level 0 and level 1 memory chips 40-80 and 40-82, are replaced on a least recently used basis by signals generated by least recently used (LRU) generator 40-84. Along with each 20-bit descriptor, a modified (M) bit is stored. The M bit outputs from chips 40-80 and 40-82 are applied as status input signals to control logic section 40-30. The LRU generator 40-84 includes address comparator chips 40-86 and an LRU chip 40-88. The chips 40-86 generate hit signals MATCH-0A, 0B, 1A AND 1B for indicating whether either level contains the page descriptor corresponding to the virtual address being translated. LRU chip 40-88 is used to store replacement information for ensuring that the least recently used information is replaced. For further details regarding the operation of LRU 40-84, reference may be made to the related patent application of Forrest M. Phillips entitled, "Least Recently Used Replacement Level Generating Apparatus."
As shown, the cache memory level 0 and 1 chips 40-80 and 40-82 connect to a pair of data buses PD0DAT and PD1DAT which receive data from a pair of input data registers PD0DAT2 and PD1DAT2, respectively. The PD0DAT2 and PD1DAT2 registers connect as inputs to the VMBUS section 40-14, as shown.
Section 40-8 includes a plurality of PAL devices 40-89 which generate chip enable and read/write control signals for cache memory chips 40-80 and 40-82, in addition to a pair of mutually exclusive register enable signals D for registers 40-22 and 40-66, as shown. The PAL devices 40-89 receive control signals from control logic section 40-30 as described in greater detail herein.
The section 40-10 stores the segment descriptors (SEG DESC) and quadrant descriptors (DSPT) and a descriptor segment base register (DSBR) in a RAM 40-100. A segment descriptor RAM 40-100 which can be viewed as a single level cache has sufficient capacity for storing all of the required number of segment descriptors. More specifically, SDRAM 40-100 includes locations for storing descriptor segment page table pointers (DSPT), also known as quadrant descriptors, and a descriptor segment base register (DSBR) value used for generating addresses for referencing main memory to fetch required quadrant and segment descriptors in response to a miss condition. The SDRAM 40-100 also includes circuits for detecting a quadrant descriptor hit (QDHIT). A PAL device 40-104, in response to signals from control logic section 40-30, applies read/write control signals to SDRAM 40-100.
Section 40-10 also includes a comparator chip 40-102 which is connected to receive segment number signals from PTRBUS 40-16 and a segment valid bit signal SDVBIT from VMBUS 40-14. Comparator chip 40-102 generates a segment descriptor hit signal SGHIT for indicating the presence of the segment descriptor in SDRAM 40-100. A PAL device 40-108 generates a quadrant descriptor hit signal QDHIT, as shown.
The SGHIT and QDHIT signals are also applied as status inputs to control logic section 40-30. Section 40-10 also includes a segment address SAD register 40-106 which is constructed from PAL devices. The register 40-106 can be clocked early in a cycle with address signals from either PTR bus 40-16 or A-unit, in response to GOTO signals received from control logic section 40-30, as discussed later herein.
Section 40-12 provides the E-cache with signals from one of four sources as directed by control signals F from control logic section 40-30. As shown, section 40-12 includes a 4-way multiplexer 40-120, 32-bit output latch 40-122 which connects to a V-PTR interface bus and a 16×37 bit FIFO buffer circuit 40-124 for storing information received from latches 40-122 when the E-cache signals that it is busy as indicated by the state of E-cache ready signal EC-RDY.
Multiplexer 40-120 has as inputs, the current input pointer and ring number from register 40-20 and PTRBUS 40-16, the output of PDASM level 0 RAM 40-80 and the least significant ten bits of the current pointer from PTRBUS 40-16, the output of PDASM level 1 RAM 40-82 and the least significant ten bits of the current pointer from PTRBUS 40-16 and the VMBUS 40-14. In addition to receiving information from one of the sources selected by multiplexer 40-120, latch circuits 40-122 also receive a 5-bit E-cache command (C), generated by control logic section 40-30, in response to the required operation. The 5-bit command is applied to the E-cache as the 4-bit VECTL and 1-bit BIU command inputs of FIG. 1b.
Section 40-14 includes the VMBUS which receives 32-bit input data from the E-cache data bus EC-BUS via input register 40-140 enabled by a signal E received from control logic section 40-30. This path is used in response to a read descriptor request made by VMU40 when missing descriptors are required to be fetched from main memory. The VMBUS also receives status signals from section 40-19. The VMBUS, as mentioned, provides data to the different VMU sections, such as sections 40-8, 40-10 and 40-12. Section 40-16 includes the PTR bus which receives the current virtual address 40-22 or pointer 1 from A-unit 20-4.
An exception vector generator section 40-18 includes a number of PAL devices which, in response to signals from control logic section 40-30, generate a 5-bit code VECT identifying the type of exception which occurred during normal processing. It identifies both VMU exceptions and trap codes passed to the VMU40 by A-unit 20-4. The VECT code is deemed valid when the VMU40 sets a VECT valid indicator signal V-INT to a binary ONE or active state.
A status section 40-19 stores indicator information in a status register 40-194 for signalling error checking violations which result in certain traps or page faults, in addition to VMU status information. The error checking indications include gate permit OK, gate bracket OK and gate SIZEOK signals, process and segment boundary violation signals, and write and read permission signals. The VMU status information signals include paged segment signal, security alarm signal, and READOK, WRITEOK, SIZEOK and read/write bounds OK signals. As shown, section 40-19 includes a group of PAL devices 40-190 which, in response to carry out signal CN12 and STATE signals from section 40-30, generate SIZEOK signal, in addition to the other status signals mentioned.
An error management section generates certain status and unusual event (UEV) signals for reporting purposes. Section 40-20 includes a plurality of PAL devices. As shown, these devices receive signals STATE, CMD, QDHIT, SEGHIT, PDHIT and parity error signals, in addition to a syndrome register reset signal. The PAL circuits of block 40-200 generate an output error signal ACDERROR which is forwarded to certain unusual event (UEV) logic circuits and a signal VMUERRORSTATUS which is stored in a syndrome register, not shown. The equations for these signals are given in the Appendix.
Section 40-30, in response to the 8-bit VMU command signals from the A-unit applied via command register 40-26 and status signals applied from the different VMU sections, generates the necessary subcommand signals required for carrying out the operation specified by the A-unit. The section 40-30 employs a state machine concept. As shown, section 40-30 includes a state control unit 40-32 which generates signals STATE0-5 specifying the current state and signals GOTO0-5 specifying a next state. The signals GOTO0-5 are applied as inputs to a clocked PAL device 40-36 which generates output register enable signal E which is applied to registers 40-140, 40-68, 40-194 and 40-100. Both sets of signals are applied as inputs to the PAL devices which comprise a subcommand generator block 40-34. The block 40-34 provides as outputs, subcommand signal groups corresponding to outputs A through M. As shown, outputs A through M are either used directly or applied to PAL devices shown as distributed throughout the VMU sections. These PAL devices form part of subcommand generator block 40-34. These PAL devices, as well as the PAL devices included in block 40-34, are for the most part distributed throughout VMU40. For further information regarding section 40-30, reference may be made to the referenced related patent application titled, "A Virtual Memory State Machine."
FIG. 2 shows in greater detail the PDAM section 40-8 of FIG. 1a constructed to include the retry mechanism of the present invention.
As seen from FIG. 2, the PDAM section 40-8 includes replacement level generator LRU 40-88, PDAM control circuits 40-89 and two directories 40-86a and 40-86b for associated RAM sections 40-80 and 40-82, arranged as shown. Each of the directories is constructed from two standard 2K×8 cache address comparator chip parts, such as SN74ACT2152, manufactured by Texas Instruments Inc. The part includes a high speed 2K×9 static RAM array, a parity generator, a parity checker, and a 9-bit high speed comparator circuit. A first group of pins are reset, read, write and select pins, respectively (i.e., RESET, R, W and S), each activated by a low (0 V) voltage signal. A second group of pins are RAM address input pins, while a third group of pins are data input pins. One output pin is a match pin, while a further output pin is a parity error pin. Since each directory includes two such parts, there are two pairs of match and parity error output pins. The match pins provide the sets of match signals MATCH0A, 0B and MATCH1A, 1B, as shown. The parity error pins provide the sets of error signals PARERR0A, 0B and PARERR1A, 1B. The sets of parity error signals are ORed together by OR gates 40-87a and 40-87b to generate as outputs signals PDPER0 and PDPER1. The signals, along with the match signals, are applied as inputs to the control circuits 40-89.
The directories 40-86a and 40-86b store address information specifying where the page descriptors are stored in their respective RAMS 40-80 and 40-82. These circuits, in response to a request for page descriptor data, cause control circuits 40-89 to generate a page hit signal (PHIT0 or PHIT1) when the requested descriptor information is detected to reside in one of the RAM sections 40-80 or 40-82. As shown in FIG. 1, the hit signals contribute or form part of the mux selection signals F applied to multiplexer 40-120.
As shown in FIG. 2, LRU generator 40-88 also utilizes the cache address comparator part 74ACT2152. The LRU generator 40-88 provides other circuits within the PDAM section 40-8 with the level number of the cache RAM level which was least recently accessed by a member of the same set of addresses to which the input address applied to section 40-8 belongs. If the applied input address is the first occurrence of a member of its set (i.e., data was not written into the location), then level 0 is assumed to be the least recently used.
The LRU generator 40-88 records which one of the two levels was most recently accessed by any range or set of addresses. When addressed by a particular address set, LRU generator 40-88 generates the output signal RPLAHIT which is used to establish the least recently used level which should be updated for that address set when there is a miss indicating that the information specified by the address is not stored in either RAM section 40-80 or 40-82.
The signal RPLAHIT is applied as an input to the control logic circuits of block 40-89 where it is complemented and then stored for an upcoming write cycle. Circuits of block 40-89 also receive STATE signals, system clock signal $VT3+00 defining the third clock phase of a four-phase system cycle of operation, the MATCH signals MATCH0A, 0B, MATCH1A, 1B, parity error signals PDPER0 and PDPER1 from directories 40-86a and 40-86b, a signal XLATETRY derived from decoding the STATE and CMD inputs indicating that an attempt to translate a virtual address is in progress and a signal PDDBLH which registered detection of a double hit condition. The circuits of block 40-89 generate the required control signals, in addition to replacement address tag signal RPLADT, as explained herein.
Address signals PTR05-09, and 14-19 are applied to the corresponding input address pins designated as A0-A10. All address signals with the same value applied to inputs A0-A10 are members of the same set. All of the input data pins (D0-D6) are connected to ground, while pin D7 is connected to receive signal RPLADT from control circuits 40-89. The read (R) pin is connected to receive a positive or +V voltage level which inhibits a read from taking place during normal operation. The select (S) pin is connected to receive a low or zero volt level which enables the chip for operation. The write (W) pin is connected to receive write signal RPLAWRT. The match pin generates output signal RPLAHIT, while the parity error (PE) pin generates output signal RPLAPE. LRU generator 40-88 is reset by applying a low active signal to the RESET input of the LRU 2152 chip. As mentioned, this is done during system reset.
As explained herein, the LRU generator 40-88 is normally written only during cycles which produce "hits." This allows the LRU generator 40-88 to record the last level or most recently accessed level for a particular address-set. During the write cycle, the LRU-tag data, including the state of signal RPLADT, is written into the generator's internal RAM. The tag address applied to the data input pins of LRU 40-88 corresponds to ZEROS being applied to the first seven inputs and the state of signal RPLADT being applied to the eighth input. The state of signal RPLADT is written in accordance to the equation for this signal set forth in the Appendix.
LRU write cycles occur when the cache directory is not being written (i.e., the directory is being interrogated) when a "hit" occurs in either level of the cache memory. If the "hit" occurs in level 0 of the cache, then the LRU records into the addressed location, a high level or binary ONE RPLADT signal as input data. If the "hit" occurs in level 1 of the cache, then the lRU records into the addressed location, a low or binary ZERO level RPLADT signal as input data.
It will be noted that the occurrence of a parity error on level 1 causes LRU 40-88 to record the same higher level as if there was a hit on level 0. Also, the simultaneous occurrence of a hit on levels 0 and 1 are treated as if the hit occurred on level 1.
LRU generator 40-88 performs an interrogate cycle when neither the READ (R) nor the WRITE (W) input pin is active, and its Chip Select (S) input pin is active. In this mode, the generator 40-88 uses the address on its address input pins to read out the contents of its internal RAM. The internal RAM contains a parity bit and any RPLADT values previously stored during previous write cycles. The value read out of its internal RAM is compared to the RPLADT value currently applied to its data input pins. If a match occurs, the LRU generator 40-88 forces the MATCH output pin to an active or binary ONE state.
Simultaneously, the parity of the stored data is checked, and any errors in the stored data are reported by error management unit 40-200 in a syndrome register, not shown, when the parity error output (PE) pin is forced to an active state.
The LRU interrogate cycles occur only during cache "miss" cycles. That is, LRU generator 40-88 is written during cache "hits" and is interrogated during cache "misses".
The control circuits 40-89 generate the required control signals for processing requests. These signals are distributed to different parts of the PDAM section 40-8. As shown, these signals include an LRU tag signal RPLADT which is generated during an interrogation cycle, a replacement address write signal RPLAWRT for recording the last level accessed for the specified address set, cache page data level 0 and 1 write signals PD0WRT and PD1WRT for writing data into PD cache RAM sections 40-80 and 40-82, respectively, page descriptor level 0 and level 1 hit signals PHIT0 and PHIT1, and a valid bit signal VLDBIT for indicating when descriptors stored in RAM sections 40-80 and 40-82 are valid.
As shown, the circuits include a plurality of programmable array logic (PAL) circuit elements which include register storage. The PAL circuits of block 40-89 receive a clear signal, the state signals STATE0-5 from the state machine circuits 40-32, in addition to the match and parity error signals mentioned. Also, the circuits 40-89 receive the sets of input signals from PTRBUS 40-16. The PAL circuits are constructed from standard circuit parts and generate the indicated output signals, according to the Boolean expressions given in an appendix section included herein.
With reference to FIGS. 1a through 3b, the operation of the preferred embodiment will now be described. The circuits of PDAM section 40-8 upon power-up are cleared to their initial states in response to a clear signal. The state machine 40-32 tries to remain in the state A0 executing a virtual to physical translation every clock or cycle of operation on behalf of the system which includes the VMU 40 of FIGS. 1a through 1c. One of the normal types of exceptions to this occurs when the page descriptor associative memory PDAM section 40-8, which operates as a translation localized mechanism for speeding up the translation does not have the descriptor required stored in the more rapidly accessible memory (40-80, 40-82), thus forcing a page descriptor miss sequence of states to be executed beginning with state P0. The process performed by executing these states is to compute the address of the page descriptor needed for the translation, fetch it from main memory, verify that it is an appropriately numbered page within the segment and make certain when it is read that it is a valid page descriptor (valid bit set). If the valid bit is off or not set, the VMU40 signals the operating system with a page miss which fetches the requested page from backing store.
On the page descriptor miss flow of FIG. 3b, the VMU 40 normally sequences through states P0, P1, P2, some number of P3 states while waiting for a memory read, P4, to load the associative memory with the translation data corresponding to the page descriptor from memory, and returns to state AP which again attempts to translate the address.
As seen from FIG. 3a, state AP is very similar to state A0 and is used when VMU 40 failed to complete the translation the first time. The PDAM section 40-8 tries again to complete the translation. If it succeeds, the state machine 40-32 returns to state A0 for the next transaction. There are variations for the different cases, such as double word fetches, missing segment descriptors, etc.
In order to achieve the desired hit rate on the associator of the PDAM section 40-8, a two-level set associative cache type implementation was chosen similar to that disclosed in the previously mentioned related patent application of Forrest M. Phillips. For a given set of page and segment numbers, there are two places where a translation can be stored. Thus, up to two members of the set will be known to the hardware relative to what the translation is and if the reference is being made to either of the two translations, the VMU does not have to access main memory for the page descriptor.
When the VMU 40 references a third member of the set, a decision must be made relative to storing the third member. This is determined by the LRU 40-88 which indicates one of the two levels was most recently the target of a successful translation (provided a translated address). By remembering that level number, it is possible to direct the replacement of the other level (least recently used) when it becomes necessary to replace one of the two level numbers. This type of LRU operation utilizes a 2152 directory chip which is described in the referenced related patent application.
The present invention is directed to the operation of the PDAM section 40-86 two-level directories which contain parity detection circuits when such circuits report having detected a parity error. Several different modes of operation are possible. The above described the sequence of states when no parity error was detected on either level during the translation operation.
Another situation which is handled in the same fashion is when one level signals that it has the translation needed, while the other level signals that it has detected a problem or parity error. Since the level which reported the problem will be the next candidate for replacement, no special action is required. The only valid copy of the translation was found and is provided by VMU 40.
The case of one level simultaneously reporting both a hit and a parity error is not explicitly handled as all failure modes; to create such a combination would require two simultaneous transient failures or a solid failure of the parity check circuit. The preferred embodiment of the present invention uses criteria which only requires attempts to cure failures that could be caused by a single transient error.
Another case is when neither level reports a hit indicating that a page descriptor is missing and one level detects a parity error. Instead of replacing an arbitrary level depending on the LRU (the previous LRU information), the VMU40 substitutes its knowledge of which level had the parity error to make that level the one which is least recently used and the next candidate for replacement.
When both levels report a parity error, one of the levels is selected for immediate replacement similar to the last case. Since success in this repair now leaves them set in the state described in the first case, VMU 40 operates to replace the other level during a later translation attempt.
Finally, in the case of a double hit, this is treated as if both levels signalled a miss and, while one level is invalidated, the other is replaced with a fresh copy of the descriptor obtained from memory.
The above modes of operation are illustrated in the equations in the Appendix and the sequence of states indicated in flow charts of FIGS. 3a and 3b. One of the PALs of block 40-84 generates the write signals for the two-level directories (PD0WRT and PD1WRT), in addition to the write signals RPLAWRT and RPLADT for LRU chip 40-88. Signal RPLADT is the data signal applied as the replacement value to be written into the LRU. Signal RPLAWRT is the signal which conditions the LRU chip to perform the write instead of a compare operation. The signals PD0WRT and PD1WRT correspond to mutually exclusively generated write pulses which are applied as inputs to directories 40-86 and associated RAM chips 40-80 and 40-82 of PDAM section 40-8.
Another one of the PALs of block 40-84 generates valid bit signal VLDBIT which corresponds to the tenth bit which is appended to the address tag value written into level 0 or level 1 RAM data. This additional bit of data is used for indicating that the address being written into the directory is valid. That is, the operating system software may determine that the data stored in PDAM section 40-8 no longer matches the data stored in the main memory page tables (e.g. due to process swaps, interrupts or a page frame replacement algorithm reaches this conclusion). To improve system performance in this situation, all of the locations of the cache directory chips are cleared to ZEROS by their respective pins. This cleared state indicates to the VMU state machine that both levels for all sets do not match. Since a tag derived solely from the address may contain all ZEROS, an additional tag bit, valid bit, has been added. In practice, the valid bit is derived from the software controlled valid (V) bit of the page descriptor V bit (i.e., signal VMUBUS00) during PDWRT time of state P4. Although signal VLDBIT is written during state P9, and in the case of a double hit leading to state P0, the value written is known a priori. In the case of state P9, the signal VLDBIT is forced on during the creation of a pseudo page descriptor for unpaged segments, and it is cleared during state P0 to allow the invalidation of level 1 in the case of a double hit condition. This PAL forces the same valid bit to a known state during the LRU comparison phase where a translation is attempted to be located so it will match the recorded valid bit and not match a valid bit previously left cleared.
Referring to the equation for the signal RPLAWRT in the Appendix, it is seen that this signal is generated during the third time interval T3 of a four-phase clock signal. The signal XLATETRY denotes one of the states in which a virtual address to physical address translation is being attempted. The XLATETRY signal results from combining signals which indicate the state of the VMU 40 and the type of command being executed (i.e., whether or not a translation is to be performed in contrast to just passing on the virtual address as data, etc.). The three OR terms of the equation, PDHIT, PDPER0, and PDPER1 indicate that an entry will be written into the LRU directory chip when the VMU 40 is trying to translate an address and either a hit is detected on one of the two levels or one of the two levels reported a parity error.
The immediately preceding equation for signal RPLADT defines what is to be written into the LRU directory chip 40-88. It is seen that in the presence of state derived signal XLATETRY (e.g. A0), if a hit was detected in level 0 (PDHIT0=1) and no hit in level 1 (PDHIT1), signal RPLADT is a binary ONE. That is, a hit was detected in level 0 (most recently accessed), and therefore, a binary ONE should be written into the associated LRU location as the least recently used level. Therefore, during a replace cycle, when a ONE is later compared to the ONE written into that location, there will be a match or a ONE as an output indicating that level 1 is the one to be replaced. The signal PDPER1 indicates that when level 1 detects an error, signal RPLADT is again forced to a binary ONE causing level 1 to be replaced.
Summarizing the first two cases, if a normal hit was detected in level 0 and no parity error, a binary ONE is written into the LRU. If there is no hit detected on level 0 but a parity error was detected in level 1, a binary ONE is also written into the LRU which designates level 1 for replacement which occurs very soon.
The next line of the equation defines the state of signal RPLADT for use and modify cycles corresponding to states U0 and M0. During these operations, the use and modify bits of the page descriptor are updated. This involves the process of refetching the page descriptor and replacing the entry which detected the hit because the VMU 40 command in register 40-26 called for a memory write and the M bit of the level that detected the hit was off indicating that the corresponding M bit in the main memory copy of the page descriptor is off. This is a case where the VMU40 is not getting a new descriptor from main memory but is modifying an existing page descriptor and, therefore, wants to write into the same level that produced the hit. Therefore, the hit signal PDHIT1 is used to generate signal RPLADT, which is the opposite from the first case.
The last term defines states P4 and P9 which are the only states during which new data is being written into the PDAM section RAMs and directories. In this case, the data input to the LRU 40-88 should be a binary ONE so that when it is compared and the output is a ONE, the entry is written into the level 1 RAM. In the case of an "LRU miss", the entry is written into level 0.
The equations for signals PD0WRT and PD1WRT define the time when the directories 40-86 and RAMs are written. At time 3 (T3), during state P4 or P9, level 0 will be written if there is no replacement hit (!RPLAHIT) and level 1 will be written if there is a replacement hit (RPLAHIT). The remaining term for signal PD1WRT is the special double hit invalidate case. An invalid page descriptor is written into level 1 during state P0, which is not a normal write state, if a double hit was detected (i.e., PDDBLH) by another PAL circuit. Signal PDDBLH indicates that during XLATETRY, all four match output signals MATCH0A, 0B and MATCH1A, 1B were binary ONES.
The double hit detection case takes advantage of a special term in the equation for signal VLDBIT in the Appendix. Signal VLDBIT is true or active in states other than P4 and P0. In the case of a write during state P0, which occurs only when a double hit has been detected, signal VLDBIT is forced to a binary ZERO to invalidate the entry which is not being replaced. As seen from FIG. 3b, the sequence of states that pass through state P9 does not involve physical page descriptors from memory but are used for operations that build a pseudo page descriptor for unpaged segments so that the same mechanism can be used for translating only segmented virtual addresses into physical addresses.
The operations of the VMU 40 are audited by states and error reporting circuits of block 40-20. When VMU 40 performs a translate try operation, the occurrence of a double hit or page descriptor parity error is stored along with other types of errors.
When either a page descriptor parity error and no hit or double hit error is detected, this causes one of the PAL circuits of block 40-20 to generate a signal STRIKE2 noting the occurrence of the error during the first translation try operation. When VMU 40 gets to state AP, another XLATETRY state, and that yields another parity error without a hit or a double hit error, VMU 40 indicates that it is unable to continue (i.e., it is broken) by signalling an unusual event (UEV) condition. If the translation is successful, VMU 40 sequences back to state A0. At this time, the STRIKE2 signal is cleared. Thus, a UEV condition is signalled only when the execution of a single command or transaction results in two such errors.
It will be appreciated that there are other errors associated with other units which are similarly retried (e.g. quadrant, segment directories). If two transient errors occur within the same translation sequence, this results in the UEV condition being signalled. Another case is where the VMU40 translates a virtual address for a double word read command which crosses a page boundary. This requires two separate translations because the two physical addresses may not be contiguous, although they are logically adjacent. The VMU40 sequences through a first sequence of states that performs the translation try on the first address. The VMU40, upon successfully completing the first translation, performs the translation try on the incremented virtual address. If two parity errors occur during this operation, this is also reported as a UEV error condition.
If the LRU 40-88 generates a parity error, it is not considered a fatal error, since it only indicates that the LRU mechanism could be operating as a single level set associative memory. There is no retry, but the error is reported for error logging purposes.
From the above, it is seen how the apparatus of the present invention, upon detecting certain types of error conditions, treats each such type of error as a complete miss in the descriptor RAM (e.g. page, segment, quadrant), fetches a fresh copy of the descriptor from main memory and retries the operation with the fresh copy. The conversion of the specific error into a miss automatically initiates the retry state sequence. If the retry still results in an error, or if two errors are detected during the execution of the same command, the VMU signals that it is unable to continue.
The invention maximizes the effective use of states for detecting such errors, correcting or altering the state of the LRU mechanism for avoiding any repetition of certain errors and for retrying certain types of errors. This reduces considerably the complexity of the VMU design, in addition to facilitating the detection of errors. Additionally, it maximizes the use of common sequences of states. For a summary of the various states, the Appendix may be consulted. Additionally, the referenced patent applications may also be consulted.
__________________________________________________________________________APPENDIX__________________________________________________________________________I. SUMMARY OF STATES A0 = initial state for all VMU operations. A0, AP, AQ, AS = translate (first) virtual address to physical address, check validities, permissions, rings, etc., prepare to check next virtual address (i.e., VAPLUS1). A1 = process the second word of unaligned double words for commands which can be executed within two cycles (class b). L0, K0 through = access local VMU resources K7 (DSBR, DSPTN, descriptor directory, status, etc.). M0 through M3 = mark page descriptor as modified. P0 through P4 = retrieve missing page descriptor. P6, P8, P9 = create pseudo page descriptor for unpaged segment Q0 through Q4 = retrieve missing quadrant descriptor (D SPT). S0 through S9 = retrieve missing segment descriptor U0 = mark page descriptor as used. V0, VM, V1, V2 = signal V-INT to CPU. X0 through X2 = security check for second word of a page crossing double word.II. LOGIC EQUATIONSThe symbols define the following: $ denotes state code # = or & = and T3 is a clock time = inversion .D = registered (clocked) value. 1. PHIT0 = PDHIT0 & !PDHIT1 where PDHIT0 = MATCH0A & MATCH0B; PDHIT1 = MATCH1A & MATCH1B; PDHIT = PDHIT0 # PDHIT1 ; 2. PHIT1 = PDHIT1 & !PDHIT0; 3. RPLADT = PDHIT0 & !PDHIT1 & (XLATETRY) # PDPER1 & (XLATETRY) # PDHIT1 & ($U0 # $M0) # ($P4 # $P9) 4. RPLAWRT = T3 (XLATETRY & (PDHIT # PDPER0 # PDPER1) # T3 & ($U0 # $M0) 5. PD0WRT = T3 & ($P4 # $P9) & !RPLAHIT; 6. PD1WRT = T3 & ($P4 # $P9) & RPLAHIT # T3 & $P0 & PDDBLH 7. VLDBIT = !($P4) & !($P0) # VMBUS00 & !($P0) 8. PDHIT = MATCH0A & MATCH0B # MATCH1A & MATCH1B 9. PDDBLH.D = MATCH0A & MATCH0B & MATCH1A & MATCH1B & XLATETRY # PDDBLH & !XLATETRY10. STRIKE2.D = STRIKE & XLATETRY # STRIKE2 & !STATEA0 & !RSTSYND where STRIKE = DSPTHIT & (SDPE # SEGHIT & PDERROR)11. VMUERROR.D = !RSTSYND & (STATEBAD # FULLERR #!STATEA0 & XLATETRY & STRIKE & STRIKE2 #XLATENOW & (STRIKE #!DSPTHIT #!SEGHIT #!PDHIT) #VMUERROR)12. ACCERR.D = !RSTSYND & (STATEBAD #!STATEA0 & XLATETRY & STRIKE & STRIKE 2 #XLATENOW & (STRIKE #!DSPTHIT #!SEGHIT #!PDHIT) #VMUERROR) #ACDERR)__________________________________________________________________________
where XLATENOW is active or a binary ONE in those states in which the virtual to physical translation can proceed without further information (e.g. state A1).
While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the spirit of the invention as set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.
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The triple jump, judo, and slalom-canoeing may not receive the same attention as basketball, gymnastics, and the 100-meter dash in the coming days, but some of the U.S. Olympians participating in lower-profile events in London are helping to raise the profiles of communities across America.
Take Team USA triple jumper Amanda Smock. She's not as well-known as swimmer Michael Phelps or soccer goalie Hope Solo, but just about every one of the 3,599 residents of Melrose, Minn., can recite her story.
"We're really proud of Amanda and her accomplishments representing the city of Melrose," city Administrator Michael Brethorst told National Journal Daily. "This is pretty unique for us to have an athlete of her caliber to come out of our community."
"For me to have my roots in a small town means more and more as time goes on," Smock told InForum, North Dakota's top news website. "To instantly have the population of Melrose all behind me is cool. I feel like if I grew up in Minneapolis, I would get lost in the shuffle."
To recognize Smock's accomplishments, Melrose is hosting a silent flag auction throughout the Summer Games consisting of 23 Olympic flags signed by the city's favorite daughter. The proceeds will go the town's parks program.
The enthusiasm for Smock does not stop there. Visitors to Melrose, about equidistant between Minneapolis and Fargo, N.D., will most likely see many residents wearing "Team Smock" T-shirts.
"Team Smock is just like her local fan club," Brethorst said. "Yesterday, I even saw one of my fellow council members wearing one. We're pretty excited."
Before leaving for London to train, Smock rode in Melrose's Riverfest parade, signed autographs, and mingled with the residents.
"She thought it was a great idea, but then she thought, 'Oh my gosh, what if no one comes?' " Smock's mother, Beth Theischafer, told InForum. "I said, 'Amanda, everybody I know wants to talk to you.' "
Residents of Drums, Pa.—situated 2,500 feet above sea level next to Sugarloaf Valley in eastern Pennsylvania, with a population of roughly 9,000—are just as proud of their Olympian, canoer Casey Eichfeld.
At only 22, Eichfeld is in his second Olympics this summer, following his participation in the 2008 Beijing Games, and this has only raised the town's excitement level.
Drums may not be throwing him a parade, but "I have a small army coming" to London," Eichfeld told the Standard Speaker newspaper in Hazleton, Pa.
"Maybe there are athletes out there who want to come to the Olympics just to solely compete in the Olympics," Eichfeld told NBC. "But I think each and every one of us up here wants medals, you know?"
Eichfeld began learning how to canoe when he was just 18 months old, according to his father, Steve, in an interview in the Standard Speaker.
"I had a rope tied to his boat and he watched what I was doing," the elder Eichfeld explained. "He had an interest in paddling around gate poles. I set up courses in six inches of water and let him navigate. He took to it."
Eichfeld has relocated to Charlotte, N.C., where he works and trains. His "army" consists of friends and family from all over the U.S., but you can bet that the mountain town of Drums will be tuned into the London Games when the slalom-canoe races are held this week.
Not all the small-town Olympians on Team USA started their athletic careers there. The story of Nick Delpopolo, a gold-medal hopeful in Olympic judo, actually begins in Niksic, Montenegro.
Delpopolo (born Petra Perovic) lived in a small, dilapidated orphanage in the former Yugoslavia until he was 21 months old, when he was adopted by Dominic and Joyce Delpopolo of Westfield, N.Y., on the Lake Erie shore. At the age of 5, Delpopolo was introduced to judo, and eventually he made the decision to move across the state to Glenville, just north of Albany, to focus full-time on his sport at the Jason Morris Judo Center.
"Ever since that day, it's been my passion," Delpopolo, 23, told the Times Union in Albany. "It's mostly what I think about. It begins my day, it ends my day: What am I going to do today for judo? At the end of the day, did I do enough? Did I train hard enough? Did I do my mental work? Did I focus properly? Did I eat properly? The whole day's based around judo and training, and now the Olympics."
And so people in two suburban communities on opposite sides of New York will be connected during the Olympics—watching a sport that the average American may never think about except when watching an action movie.
This article appears in the July 30, 2012 edition of NJ Daily.

subset: commoncrawl


text:
Seventeen rescue robots are competing in Florida this weekend, where their task is to clear away debris, break through walls and climb ladders -- a test run for their use in future disaster scenarios. But the humanoid figures are still a little shaky on their feet.
"Atlas" is attached to a hook, like a piece of meat, with his metal limbs dangling limply from his torso.
Suddenly the 150-kilogram (330-pound) robot comes to life. The hydraulic system whines, an orange light starts blinking on the robot's head and a laser scanner shaped like a tin can rotates in its face. The knees begin to bend slowly, as Atlas cautiously places his two flat feet onto the ground.
But now the device begins to falter. Atlas completes three triple steps in slow motion until he reaches a ramp. Behind a Plexiglas wall, researchers watch as the robot scans the obstacle with its laser.
Finally, Atlas hazards to take one step up the incline, followed by a second and a third. But he makes his fourth step at a dangerously crooked angle, puts weight on the poorly placed foot and falls down. A safety cable cushions the robot's fall, and in the end Atlas is hanging from a hook once again.
Is this what the beginning of a new era looks like? The researchers working on the Atlas project believe it is.
Responding to Disasters
The robot was developed by Boston Dynamics, which was recently purchased by Google. It is still being tested, but will have its big debut at the end of this week, when it will be expected to demonstrate what it can do at a competition in Florida. Embarrassing glitches like a misstep can't happen there.
"Mistakes are part of the learning process," says Jesse Hurdus, project director of the ViGIR robot team. "Vi" stands for Virginia and "G" for Germany, because German experts from the Technical University of Darmstadt are part of the team.
"Competitions inspire us, and they force us to tackle concrete problems," says Oskar von Stryk. The 49-year-old German robotics expert is attending a training camp in a warehouse on the outskirts of Christiansburg in the US state of Virginia.
The disaster at Japan's Fukushima nuclear power plant marked the beginning of the "Robotics Challenge." Developers were rankled by how helpless robots were as they wandered through the radioactively contaminated reactor building. As they swerved around aimlessly in the steam, cables broke and the operators lost contact with the robots.
It was a disgrace, and strategists with the US government's Defense Advanced Research Projects Agency (DARPA) were determined that it would not happen again. They compiled a list of eight tasks that robots would have to master in the future to be capable of performing well in disaster response.
The tasks required in those situations, such as shutting valves, connecting hoses and removing debris, seem relatively straightforward, and yet they are hopelessly overwhelming to any conventional robot. At next weekend's competition, it will become apparent whether the world's top teams have managed to teach these abilities to their creations.


text:
FIG. 1 is a front perspective view of a portion of a frame for a respiratory mask according to our design;
FIG. 2 is a front view thereof; and,
FIG. 3 is a bottom view thereof.
The dashed lines shown in FIGS. 1–3 disclose unclaimed subject matter, are for environmental purposes only, and thus form no part of the claimed design.


text:
Fall 2002 Colloquia
Monday, September 9, 2002
Dr. Claudia Johnson, Indiana University
"Evolution of the Cretaceous reef ecosystem, and thoughts on the future history of reefs"
4:00 pm, GY143
Monday, September 16, 2002
Dr. Greg Ludvigson, Iowa Geological Survey, University of Iowa
"Continental isotopic records of global change in the Cretaceous greenhouse world"
4:00 pm, GY143
Thursday, September 19, 2002
Dr. George Christidis, Technical University of Crete, Department of Mineral Resources Engineering, Chania, Greece
"Assessment of bentonite deposits: A challenge for the Resources Geologist"
4:00 pm, GY143
Monday, September 23, 2002
Dr. Qizhi Chen, Department of Geological Sciences, Indiana University
"Present-Day Tectonics of the Tibetan Plateau Measured by GPS"
4:00 pm, GY143
Monday, September 30, 2002
Alan Hoffmeister, Department of Geological Sciences, Indiana University
"Quantitative Analysis of Patterns in Drilling Predation in the Fossil Record"
4:00 pm, GY143
Monday, October 7, 2002
Dr. Thomas Armbruster, University of Bern, Switzerland
MSA Distinguished Lecturer
"Natural zeolites: from structure to application"
Thursdsay, October 10, 2002
J. Janine Barnard, International Exploration Ventures, Marathon Oil Company, Houston, TX
"From Education to Exploration: What to Expect of Your First Few Years in the Oil Business"
Sponsored by the AAPG Visiting Geologist Program
4:00 pm, GY143
Friday, October 11, 2002
Friday Brown Bag
Tim Lyons, University of Missouri, Columbia
"Sulfate Concentrations in the Precambrian Ocean as a Cause and Consequence of Biospheric Evolution"
12:20 P.M. in Geological Survey S201
Tuesday, October 14, 2002
"Cr Isotopes and the Fate of Hexavalent Chromium in the Environment"
Tom Johnson, University of Illinois
Note talk is on Tuesday and in room S201
4:00 pm, S201
Thursday, October 31, 2002
Darren Gröcke, Royal Holloway University, UK
and Stuart Robinson, Oxford University, UK
"Ocean-atmosphere interactions and understanding the global carbon cycle: the importance of terrestrial carbon-isotope stratigraphy"
4:00 pm, GY143
Friday, November 1, 2002
Friday Brown Bag
Stuart Robinson, University of Oxford, UK
"Carbon-isotope stratigraphy of the Triassic-Jurassic boundary extinction event: evidence for a major carbon-cycle perturbation"
12:20 P.M. in Geological Survey S201
Monday, November 4, 2002
Dr. Tim Filley, Purdue University
"Dynamics of Terrestrial Carbon Cycling in Forest Ecosystems"
4:00 pm, GY143
Monday, November 11, 2002
Dr. Dorothy Merritts, Franklin and Marshall University
"Rapid uplift and surface deformation at the Mendocino triple junction, the northern terminus of the San Andreas fault"
4:00 pm, GY143
[CANCELLED] Monday, November 18, 2002
Dr. Isabel P. Montanez, Univ. of California, Davis
"Stable isotopes of fossil soil minerals and organic matter as environmental dipsticks: An application to Late Paleozoic equatorial Pangean climate"
4:00 pm, GY143
[CANCELLED] Tuesday, November 19, 2002
Brown Bag
Dr. Isabel P. Montanez, Univ. of California, Davis
"Evolution of C and Sr Isotope Composition of Cambrian Oceans: Constraining Tectonic Events and Biogeochemical Perturbation"
12:20 pm, Patton Conference Room (S201)
Monday, December 2, 2002 4:00 pm, GY143
Denis Cohen, Yale University
"Understanding how glaciers slide: Measurements beneath 700 ft of ice"


text:
By Donna MilesAmerican Forces Press Service
WASHINGTON, April 18, 2011 President Barack Obama today presented the prestigious Commander in Chief's Trophy to the U.S. Air Force Academy's football team, marking the first time since 2002 that the trophy will return to Colorado Springs, Colo.
Obama joked with the team, accompanied by Air Force Chief of Staff Gen. Norton A. Schwartz and Air Force Academy Superintendent Lt. Gen. Michael C. Gould, about the honor of outperforming the U.S. Military Academy and breaking the U.S. Naval Academy's seven-year winning streak.
"Until this year, no one on this team knew what it felt like to beat Army, to beat Navy, to visit the White House, and to earn football bragging rights over the other branches," Obama told the Falcons during the ceremony in the White House Rose Garden. "Now you know the feeling."
Obama praised the Air Force as not just a good service academy team, but "a good team -- period." He recognized its 350 rushing yards against the University of Oklahoma, its bowl game win against Georgia Tech and its 9-4 finish in what Coach Troy Calhoun called the toughest schedule a service academy ever played.
"Of course, I hear the victory that was sweetest of all was finally beating that Navy team," the president said. "I'm told that as soon as the final whistle blew, the loudspeakers started blasting Etta James singing 'At Last,'" drawing laughter from the group. "The entire cadet wing -- usually some of the most disciplined young men and women you'll ever see -- just rushed the field and sang the alma mater with the team."
While the Air Force's football team has much to be proud of, Obama said what truly sets them apart is that its members aren't defined just by being football players.
"They're airmen first," he said. "And more important than any bowl game or trophy is the commitment they've made to serve this country."
That's why, the president said, while nearly every other Division I team was working out and running through practice drills, "these players were scattered around the world learning the skills they needed long after they take off their jerseys and hang up their helmets."
Quarterback Tim Jefferson was at Dover Air Force Base, Del. learning about C-17 aircraft, Obama noted. Tight end Josh Freeman was training in Japan. Cornerback Reggie Rembert was getting up every morning at 3 to take summer classes, command a squadron of 127 freshman cadets and organize practices for players who were still in town.
Being away from their teammates meant players had to come up with creative ways to stay in shape, the president said. "The conditions weren't always ideal," he said. "But as Coach [Troy] Calhoun, a former Falcon himself, said, 'The good ones will find a way.'"
"This team found a way," Obama said. "And now that the season is over, these seniors will have to adjust to a very different life as they become part of the finest military that the world has ever known. It won't always be easy… But cadets know that what's expected of them is to do whatever it takes."
As they begin their military careers, Obama told the players he knows they'll draw on the camaraderie, work ethic and brotherhood they built as members of the Air Force football team and students at the Air Force Academy.
"As president, I have no greater honor, no greater responsibility, than serving as your commander in-chief," Obama told the cadets. "And as all of you begin your service to our nation, I want you to know that we are going to do everything in our power to help you succeed and help you come home safe. You all make us incredibly proud."
Calhoun echoed Obama's praise for the team's accomplishments, noting its senior-year players are preparing to graduate about a month from now.
That day, as they graduate from the Air Force Academy, the players "will have an opportunity to be a part of the finest team there is -- and that is to lead, to be an [Air Force] officer for the United States of America," Calhoun said.
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Musicians' egos
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Join Date: Mar 2010
Posts: 81
Re: Musicians' egos
Originally Posted by
Tommy Two-Shoes
a lot of the big headed musicians I've met tend to be the types who play at home in their bedrooms, can play their parts very well, but never have a successful band. I don't really get it. I think everyone definitely has a level of ego in their playing, I think it's healthy to know and be able to tell people what you can do (and, just as importantly, what you can't)
Generally though, the musician big egos I've met tend to not have had much experience playing with other musicians. I think doing that enough times really brings people down a notch.
I've noticed the same thing. It kind of makes sense; of course you're going to think you're pretty great, if you've never left your bedroom and played with anybody better than you. Usually these are the kids who spend hours and hours learning Dream Theater songs note-for-note to post on YouTube, but if you ask them to improvise a 12-bar blues they are suddenly at a loss for what to play. They haven't yet learned the distinction between playing your instrument, and playing music.
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U.S. Navy Capt. Bruce H. Lindsey, commanding officer aboard the aircraft carrier USS Carl Vinson, holds the national flag during a burial at sea in the Pacific Ocean, Dec, 27, 2010. Carl Vinson and Carrier Air Wing 17 are on a deployment to the U.S. 7th and U.S. 5th Fleet areas of responsibility.
U.S. Navy photo by Petty Officer 3rd Class Travis K. Mendoza
2010 Imagery Year in Review - These images are the highlights of the past year's events produced by the Defense Department's military and civilian photographers and posted on Defenseimagery.mil site.
DOD Photographers
Operation Welcome Home volunteers and eager family members greet U.S. military members at the Baltimore-Washington International Thurgood Marshall Airport, Md., Dec. 22, 2010. The troops returned to the United States for the holidays after months of service abroad.
DOD photo by Army Sgt. 1st Class Michael J. Carden
U.S. Navy Seabees secure and fortify a combat outpost in Diwar, Afghanistan, Dec. 19, 2010. The Seabees, assigned to Naval Mobile Construction Battalions 40, 18 and 26.
U.S. Navy photo by Chief Petty Officer Michael B. Watkins
U.S. Ambassador to Afghanistan Karl Eikenberry and U.S. Navy Adm. Mike Mullen, chairman of the Joint Chiefs of Staff, conduct a press conference in Kabul, Afghanistan, Dec.17, 2010.
DOD photo by U.S. Navy Petty Officer 1st Class Chad J. McNeeley
U.S. Navy Petty Officer 2nd Class Ahkyi Derricks, right, talks with U.S. Navy Seaman Christopher Dipasquale as they prepare a helicopter for launch aboard the aircraft carrier USS Carl Vinson off the coast of southern California, Dec. 10, 2010. The USS Carl Vinson crew is training for a deployment to the western Pacific Ocean.
U.S. Navy photo by Petty Officer 2nd Class James Evans
U.S. Army Spc. Erik Martin uses a footbridge to cross a river during a dismounted patrol in Khwazi village, Afghanistan, Dec. 14, 2010. Martin is a member of the Zabul Provincial Reconstruction Team.
U.S. Air Force photo by Staff Sgt. Brian Ferguson
U.S. Army Gen. David Petraeus, commander of NATO's International Security Assistance Force, shakes the hand of an Afghan National Civil Order Police patrolman in Kabul, Afghanistan, Dec. 14, 2010. Petraeus visited leaders there at the conclusion of the order's three-day leadership seminar.
U.S. Army photo by Pamela Smith
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Release DateTBA 2013
StudioParlay Films
Cast and Crew
DirectorRoger Donaldson
ProducerMatthew Metcalfe, Chris Curling
ScreenwriterGlenn Wilhide, Roger Donaldson
- Kirsten Dunst
- Orlando Bloom
- Dominic Cooper
- Anil Kapoor
A cautionary tale about greed and ambition that takes place in the exuberant months leading up to the Dow Jones all-time stock market high. Fortunes, both big and small are put at risk as people around the globe gamble that the financial market's meteoric rise will continue. In New York, a hedge fund manager has everything he wants - money, sex and power, but he wants more. In London, a young couple just want to buy their first home, but it seems impossibly out of reach. In Mumbai, a cop fights against corruption between property speculators and his colleagues. These stories will all dramatically collide in a world where the fortunes of individuals are interwoven with the lives of others across the globe they have never even met.
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Create memories to last a lifetime, then memorialize them in a unique way. This beautifully constructed Black Memory Tray by the Paper Studio is the perfect way to display specific moments.
Featuring 8 sections for divided decorations, this memory tray is great for displaying photos, artist trading cards, and mementos. Add ribbon, scrapbook paper, buttons, stickers, gems, Spare-Parts, punch outs, washi tape, and so much more (all sold separately) to make this memory tray unforgettable.
Hanging Hardware: 1 - Sawtooth Hanger
Memory tray can be displayed on a wall or with a stand (sold separately).
We have a 3-5 day in-house process. There will be an additional 1-7 days for delivery.
**During peak Holiday Seasons (Mother's Day & Christmas) it can take an additional 1-2 business days to get your order shipped.
We do not accept International orders online.
To place an order with an International billing or shipping address:
You will need to order by calling 405-745-1275. Customer Service is available Monday - Friday 8:00-5:00 CST.
Your order will need to ship to a US Destination, such as a freight forwarder. By doing so your order will be eligible for our US shipping rates which often include free shipping.
If you would like for us to ship your order directly to you, you will be charged the actual postage amount. That amount is calculated once your order is picked, packed and ready to ship. International shipping address are excluded from all shipping discounts. All orders shipped to an International location are charged the actual cost of shipping.
Please note that this policy does not include Military Addresses, Guam, Puerto Rico & the US Virgin Islands. We will accept and ship orders to these destinations.
Expedited shipping is unavailable at this time.
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7600 A SW 44th St
Oklahoma City, OK 73179
If you wish to exchange an item(s) you ordered for a new one:


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Templates for Official Web Pages
In order to present a consistent image on our web site and reinforce Mississippi State's brand, we have created templates which incorporate a standard header and footer. All Mississippi State units which use our main web server, Archive, are encouraged to use these templates. Units which use other web servers should contact the university webmanager for alternative arrangements.
At the bottom of this page are links to the templates in two versions: one for HTML pages and one for PHP pages.
Office of the President
The Executive Council
Alumni and Friends
Your content should be placed between the <div id="content"> and </div> tags. Please do not modify the templates, style sheet file, or the header and footer "include files" or copy them to a new location. This will allow many pages to be modified at once when the need arises in the future.
These templates will accommodate a wide variety of page designs in the area between the standard header and footer. Your page will expand to fit the width of the browser window, so the width of your design will not be limited by the template. In fact, you can put just about any design element in the template. Unless your content includes graphics wider than (about) 670 pixels, your page should print without clipping off the right edge.
Since the templates, themselves, incorporate all the elements required by university policy, once you add the page maintainer information file (See the notes in the template and page maintainer information file.), you will be in compliance with policy.
In order to minimize the possibility of e-mail addresses on your pages being harvested by spammers, we recommend that you use our "spamfoiler" facility. This will result in a form being displayed where the user can fill in his or her return address and a comment or question. The links in the standard footer to Customer Service and Page Maintainer use the Spamfoiler.
Color palette
The two colors used in the template are maroon (#660000) and khaki (#e2e2cf). You are encouraged to adopt a color palette for your page which works with those colors.
Overriding styles
The default color of the section between the header and footer is white. You may override that by embedding a stylesheet for the content div in the head section of your page. For instance:
#content {background-color: #e2e2cf;}
If your design requires a specific page width, you may specify that with, for instance:
#container {width: 670px;}
If you see no header or footer and no error messages, your page probably has its permissions set incorrectly. If it is an HTML page, it must be world executable. See the comment in the HTML template.
If you see error messages instead of the header and footer, your page cannot find the include files. Depending on where your files are stored on Archive, you may need to create a symbolic link for them. If so, telnet to your web directory and issue the command:
ln -s /data/WWW/data/web/ web
If the Page Maintainer link doesn't show up in the footer, your page is not finding the pm_info_html.txt or pm_info_php.txt file. Make sure you have put it in your root level directory and changed <script type="text/javascript" src="http://www.msstate.edu/web/templates/pm_info_html.txt"> or "include("/data/WWW/data/web/templates/pm_info_php.txt");" to point to it.
If you are still having trouble, contact the university webmanager.
The Templates
Right click on the links and Save Target/Link As... for both template and page maintainer info file to your highest level directory. Get both sets if you have a mix of HTML and PHP pages. There is additional information in the comments within the files.


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Valle lifts Herd to sweep of UCF
ORLANDO -- Jazmine Valle delivered an RBI single in the top of the eighth inning to lift Marshall to a 5-4 victory over UCF and sweep of Saturday's Conference USA doubleheader at UCF Softball Complex. The Thundering Herd won the opener, 3-1.
The Knights (18-17, I-8 C-USA) scored twice in the fifth and once in the sixth to take a 4-3 lead. Marshall got that run back in the top of the seventh on a single by Alysia Hively, double by Raquel Escareno and error by the UCF third baseman that allowed Hively to score.
In the eighth, Bri Anna Hope ripped a double to left. Katalin Lucas executed a sacrifice bunt to get Hope to third and she came home on the hit by Valle.
Andi Williamson came on the fifth for the Herd, gave up two runs but still got the win. The right-hander (18-11) went the distance in the opener to get a sweep as well. The Herd's two-run sixth proved big. Lucas had an RBI double and the second run got in on an error.
UCF's Mackenzie Audas started both games for the first time in her career and the sophomore became the first Knight since Lindsay Enders in 2005 to pitch two complete games on the same day in a doubleheader.
This was the final regular-season meeting between the two schools. UCF is headed to the Big East next season. The Knights lead the all-time series 16-13, but Marshall took the last six.
The Herd extended its winning streak to eight. Marshall returns home this week for games against Wright State and Memphis. The Herd and Wright State meet in a doubleheader at 2 p.m. Tuesday at Dot Hicks Field. Memphis is in Saturday and Sunday for a C-USA series. Saturday's twinbill starts at 1 p.m. The finale next Sunday begins at noon.
TALLAHASSEE, Fla. -- Crystal Walker set a school record in winning the long jump in the 34th Florida State Relays held over the weekend. The senior's jump covered 6.27 meters (previous mark was 6.25 by Sikeetha Shepard-Hall in 2006). Walker had one of 12 personal bests for the Thundering Herd. Only five events were completed Saturday due to bad weather.
Shyra Molton, Walker, Delkira Maybin and Moriah Njoku ran 46.40 to place fifth in the 4x100 relay. That time is second best in school history. Vanessa Jules won the high jump (1.68 meters).
Julia Galloway placed fourth in the 10,000 in 40:19.82 for a personal best. Kelley Mortakis took fifth in the 5,000 in a personal-best 18:16.26. Amanda Hottenstein was fourth in the hammer (46.24 meters) and Amanda Kennedy was fourth in the javelin (42.65 meters).
The Herd will return to action April 6 at the Ohio Team Challenge in Athens.
RADFORD, Va. -- Eric Escobedo had a two-run single to highlight a 5-run first inning and Marshall held on to edge Radford, 5-4, in the second game of Saturday's doubleheader. The Highlanders (12-10) won the opener, 8-3.
Chase Vogelback also had an RBI in the big first inning for the Thundering Herd (10-12).
The Highlanders struck for two in the fourth and two in the ninth to make it close. Alexander Lee belted a two-run homer in the fourth. Josh Reavis and Josh Gardiner each delivered RBI singles in the ninth, but Josh King, who allowed the two runs, retired the Jeff Kemp on an infield fly and Ryan Burgess on a grounder to the mound. Radford stranded seven runners over the final three innings.
Sunday's finale in the four-game series was canceled. The Herd will return to action Tuesday against Kentucky in Lexington. Game time is 6:30 p.m.
GREENVILLE, S.C. -- Marshall is tied for 19th place with Temple after two rounds in the Furman Intercollegiate being played on the par-72 Furman University course. The Thundering Herd shot 298 Saturday for a 36-hole total of 608.
Nathan Kerns leads Marshall with 146 after posting a 72 Saturday. Other Herd scores are Brian Anania, 72 -- 150; Jeremy Rogers, 75 -- 155; Tas Sipowski, 79 -- 157; and Logan Lagodich, 80 -- 160. Jake Miller, competing as an individual, carded a 79 for 165.
Virginia Tech shot 286 for a 566 total and 4-shot lead over North Florida. Western Carolina is third at 576.
Virginia Tech's Trevor Cone and Iowa State's Scott Fernandez are tied for the individual lead at 137. Cone shot 69 Saturday and Fernandez had 68. Western Carolina's J.T. Poston is a shot back going into Sunday's final round.
LAS VEGAS -- Marshall takes on SMU on Sunday at 4 p.m. The Thundering Herd edged UNLV, 4-3, on Saturday.
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