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A method and apparatus for configuring and/or initializing memory devices. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.
1. A method comprising:
assigning device identification numbers to groups of a plurality of memory devices based at least in part on memory device sizes by:
assigning a set of lowest identification numbers to memory devices having a largest supported size; and
assigning subsequent identification numbers to remaining memory devices having smaller sizes;
programming registers in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to a memory controller for all of the plurality of memory devices.
2. The method of
initializing the memory controller;
initializing a plurality of memory controller configuration registers.
3. The method of
initializing a plurality of memory controller configuration registers.
4. The method of
updating a group attribute register for each device in a selected memory module.
5. The method of
initializing a group boundary address register;
initializing a group architecture register;
initializing a RDRAM timing register;
initializing a RDRAM control register;
initializing a RDRAM power management register; and
initializing a RDRAM initialization control register.
6. A method comprising:
assigning device identification numbers to groups of a plurality of memory devices based at least in part on memory device sizes by:
determining device size information for each of a plurality of memory modules;
selecting a selected memory module based on its device size;
assigning device identification numbers to at least one group of devices on the selected memory module; and
repeating selecting a next selected memory module and assigning device identification numbers until all devices have device identification numbers;
programming registers in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to a memory controller for all of the plurality of memory devices.
7. The method of
initializing a plurality of memory controller configuration registers.
8. A system comprising:
a processor;
a memory controller coupled to processor, the memory controller having a plurality of control registers and a serial interface circuit;
a memory bus having a plurality of memory devices coupled thereto, the memory bus being coupled to the memory controller;
an additional memory device coupled to the memory controller, the additional memory device being accessible to the memory controller prior to initializing the plurality of memory devices, the additional memory device containing a plurality of instructions which, if executed by the system, cause the system to perform operations comprising:
assigning device identification numbers to the plurality of memory devices based at least in part on memory device sizes by:
assigning a set of lowest identification numbers to memory devices having a largest supported size; and
assigning subsequent identification numbers to remaining memory devices having smaller sizes.
9. The system of
initializing the memory controller;
initializing a plurality of memory controller configuration registers.
10. The system of
battery backed lip memory to store a plurality of powerdown restore values.
11.The system of
restoring the plurality of powerdown restore values upon exit of a low power state.
12. The system of
storing said plurality of powerdown restore values in the battery backed up memory prior to starting normal operation after initial system reset.
13. The system of
an input device to receive computer instructions from a computer readable medium.
14. The system of
updating a group attribute register for each device in a selected memory module.
15. The system of
programming register in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to the memory controller for all of the plurality of memory devices.
16. An article comprising a machine readable medium having stored thereon a plurality of instructions which, if executed by a machine, cause the machine to perform operations comprising:
assigning device identification numbers to the plurality of memory devices based at least in part on memory device sizes by:
assigning a set of lowest identification numbers to memory devices having a largest supported size; and
assigning subsequent identification numbers to remaining memory devices having smaller sizes;
programming registers in each of the plurality of memory devices to equalize a sum of a device response time and a propagation delay from each memory device to a memory controller for all of the plurality of memory devices.
17. The article of
initializing the memory controller;
initializing a plurality of memory controller configuration registers.
18. The article of
initializing a memory controller;
initializing a plurality of memory controller configuration registers;
assigning serial identification numbers to a plurality of memory devices which are coupled to the memory controller.
19. The article of
restoring the plurality of powerdown restore values upon exit of a low power state.
20. The article of
restoring the plurality of powerdown restore values upon exit of a low power state.
21. The article of
updating a group attribute register for each device in a selected memory module.
This application is a continuation of application Ser. No. 09/186,051 filed on Nov. 3,1998, now U.S. Pat. No. 6,226,729. This application is related to an application Ser. No. 09/186,042 now U.S. Pat. No. 6,173,345 (Docket No. P6626), entitled "A Method And Apparatus For Levelizing Transfer Delays For A Channel Of Devices Such As Memory Devices In A Memory Subsystem," application Ser. No. 09/186,050 now U.S. Pat. No. 6,378,056 (Docket No. P6628), entitled "A Method And Apparatus For Configuring A Memory Device And A Memory Channel Using Configuration Space Registers," and application Ser. No. 09/186,050 now U.S. Pat. No. 6,230,274 (Docket No. P6639), entitled "A Method And Apparatus For Restoring A Memory Device Channel When Exiting A Low Power State," all of which are filed concurrently herewith.
1. Field of the Invention
The present disclosure pertains to the field of data processing systems. More particularly, the present disclosure pertains to initializing or configuring memory devices in a memory channel.
2. Description of Related Art
Memory devices and memory subsystems typically have certain initialization steps and/or register values that need to be programmed prior to normal operation. Recommended steps and values are often detailed in a memory specification provided to system designers who design other system hardware interfacing with the memory devices. If initialization routines are further optimized, however, initialization may conclude more quickly, advantageously allowing other system processing to commence sooner.
One channel (i.e., a bus configuration) which requires a significant amount of initialization prior to proper operation is a Rambus™ Direct Rambus Dynamic Random Access Memory Channel (a Direct RDRAM™ Channel). This channel is described in detail in documentation available from Rambus Corporation of Mountain View, Calif. RDRAM memories and memory controllers interfacing with a Rambus channel have various registers that need to be set through the initialization process.
It is clear from Rambus documentation that a number of initialization operations must be performed prior to using a Rambus channel. In general, the memory controller reads all the read-only registers in all RDRAMs, processes this information, and then writes all the read-write registers to place the RDRAMs into the proper operating mode. DeviceID and TRDLY registers are important read-write registers that respectively set the device address for memory transactions and the delay value for memory read data.
A unique serial device identification value may be set for each RDRAM on the channel by looping through the entire serial chain and assigning sequential serial identification numbers (see, e.g., p. 28 of the Direct RDRAM™ 64/72 Mbit Data Sheet). A second ID value simply referred to as a device ID allows memory accesses through the Rambus channel during normal operation. A unique device ID also needs to be set for active devices on the channel; however no specific technique for assigning device IDs is described in the literature.
Additionally, RDRAMs can execute refresh, precharge, current calibration, current sampling, and various other functions (see, e.g., pp. 8-9 of the Direct RDRAM™ 64/72 Mbit Data Sheet). While these commands are generally discussed in the Direct RDRAM™ 64/72 Mbit Data Sheet, a complete initialization sequence may not be provided. Additionally, details of initialization and/or configuration of specific memory controllers may not be available. Thus, the prior art may not provide an adequate or complete method and apparatus for configuring a set of memory devices in a memory channel.
A method and apparatus for configuring and/or initializing memory devices is disclosed. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings.
FIG. 1 illustrates one embodiment of a system using configuration registers in a memory controller to designate initialization operations for memory initialization.
FIG. 2 illustrates a flow diagram of programming and executing initialization operations in one embodiment of the system of FIG. 1.
FIG. 3 illustrates one embodiment of a memory control hub that performs memory initialization according to values loaded into control and data registers.
FIG. 4 illustrates a flow diagram for a memory device core initialization operation.
FIG. 5 illustrates one embodiment of a system implementing an initialization flow shown in FIGS. 6-9.
FIG. 6 illustrates a flow diagram of one embodiment of an overall initialization sequence for the memory subsystem of the system shown in FIG. 5.
FIG. 7 illustrates one embodiment of a serial device identification process.
FIG. 8A illustrates one embodiment of a first portion of a group device identification process.
FIG. 8B illustrates one embodiment of a group device assignment process (e.g., block 820 in FIG. 8A).
FIG. 8C illustrates one embodiment of a second portion of the group identification process from FIG. 8A.
FIG. 9 illustrates one embodiment of a memory device core initialization process.
FIG. 10 illustrates one embodiment of the process of returning from a suspend-to-RAM power management state.
The following description provides a method and apparatus for initializing a memory device and a memory channel. In the following description, numerous specific details such as register names, memory types, bus protocols, specific types of components, and logic partitioning and integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures and gate level circuits have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement the necessary logic circuits without undue experimentation.
Using the presently disclosed techniques, efficient and flexible memory initialization may be performed. Control and data registers may be programmed, thereby causing a memory control hub (MCH) to perform initialization operations (IOPs) according the values loaded in the registers. Since the registers may be programmed by software such as a basic input/output system (BIOS), the initialization may be altered with relative ease.
FIG. 1 illustrates one embodiment of a system utilizing registers to perform memory initialization. The system includes a processor 195 and a memory subsystem 104 that are coupled to a memory control hub (MCH) 100. Also coupled to the MCH 100 is a secondary bus 180 having coupled thereto an input device 190 and a non-volatile memory 185 containing BIOS routines. In some embodiments, either or both of the non-volatile memory 185 and the input device 190 may be coupled to the MCH 100 by a second control hub (not shown).
In the illustrated embodiment, the memory subsystem 104 includes three memory modules 160, 170, and 175 coupled to the MCH 100 via a serial bus 142 and a memory bus 132 (also referred to as a channel). Each memory module may contain a set of individual memory devices. For example, the memory module 160 includes at least memory devices 160, 161, and 168. In one embodiment, the memory devices 160, 161, and 168 are Rambus DRAMs (RDRAMs), the memory modules are Rambus In-line Memory Modules (RIMMs), and the channel operates according to protocols defined for RIMMs and RDRAMs.
The MCH 100 includes a control register 112 and a data register 114 which may be used for initialization purposes. An initialization control circuit 120 executes initialization operands (IOPs) which are programmed into the control register 112. The control register 112 typically includes other fields to specify information about initialization operations, and some of the operations specified by the IOPs involve data exchange with devices in the memory subsystem (e.g., writing and reading of memory device control registers or otherwise generating control signals).
A serial interface circuit 140 generates serial command and data sequences on the serial bus 142. Some of the commands executed by the initialization control circuit 120 send commands and/or data to the memory subsystem via the serial bus 142. Control registers, including device registers for identification numbers, may be read and written via the serial interface circuit 140.
A memory interface circuit 130 translates memory data to and from data packets which are exchanged with the memory subsystem. In one embodiment, the memory interface circuit is a Rambus ASIC Cell (RAC) functioning substantially as described in the "Direct RAC Data Sheet" available from Rambus Corporation of Mountain View, Calif. Briefly, the RAC converts the Rambus Signal Level (RSL) signals on the channel (bus 132) to signals which can be processed by other portions of the MCH 100. Similarly, the RAC converts the memory controller signals to RSL signal which can be processed by memory devices on the Rambus channel.
A sequence of initialization events for the system of FIG. 1 is illustrated in FIG. 2. As the system is reset or turned on, the BIOS typically performs various initialization operations. In block 200, the BIOS reaches the memory configuration portion. Depending on the type of memory and the intended mode of usage, initialization operations will be selected (block 205) by the BIOS in a particular sequence. More details of one embodiment of an initialization sequence for a system utilizing RDRAMs are discussed with respect to FIGS. 5-9.
As indicated in block 210, data (if any) for the particular initialization operation is stored in the data register 114, and the initialization operand itself with other control information is stored in the control register 112. In some embodiments, the BIOS may perform this function by writing to peripheral component interconnect (PCI) configuration registers. Alternatively, other registers may be used, or general purpose memory locations either within or without the MCH may be the control register. In fact, the control register may be any storage location accessible to the MCH prior to memory initialization that is capable of storing sufficient bits for IOPs and any other needed control information.
The initialization operation may commence automatically when the proper initialization operation and/or control information are programmed into the control register 112. For example, the execution of the initialization operation indicated in block 215 may be accomplished by setting an initiate initialization operation (IIO) bit when the initialization operand is loaded into the control register 112. The IIO bit may be a field of the control register 112 so the same register write transaction may set the IIO bit and provide the IOP.
Completion of the initialization operation may be signaled in any manner sufficient to alert or inform the BIOS that the initialization operation is complete. For example, the MCH may automatically clear the IIO bit when the initialization operation completes. If the BIOS polls the IIO bit, it may determine when the initialization operation completes as indicated in block 220. If the initialization operation has not completed, the BIOS may continue polling the IIO bit. If the initialization operation has completed, the BIOS may select the next initialization operation in the initialization sequence in block 205.
The input device 190 may either accept program instructions from a computer storage device 192 (e.g., an optical or magnetic disk or other storage device) or from a network or communications interface 194. BIOS code (i.e., computer instructions) causing the system to implement the disclosed techniques may be programmed into the non-volatile memory 185 in several ways. The BIOS may be programmed when the system is manufactured or may be later delivered via a computer readable medium through the input device 190.
In cases where the BIOS is later delivered, the instructions may be delivered via a computer readable medium. With an appropriate interface device 190, either an electronic signal or a tangible carrier is a computer readable medium. For example, the computer storage device 192 is a computer readable medium in one embodiment. A carrier wave 196 carrying the computer instruction is a computer readable medium in another embodiment. The carrier wave 196 may be modulated or otherwise manipulated to contain instructions that can be decoded by the input device 190 using known or otherwise available communication techniques. In either case, the computer instructions may be delivered via a computer readable medium.
FIG. 3 illustrates additional details of a memory controller hub (MCH) 300. Details of specific register names, locations, sizes, field definitions, and initialization operations are given for one embodiment below. Other embodiments will be apparent to those of skill in the art. Several of the operations below invoke specific commands defined by Rambus in the 64/72-Mbit Data Sheet and the Direct RAC data sheet. These defined operations are operations that the Rambus RAC itself sends to RDRAMs when appropriate control signals are sent to the RAC. As detailed below, this embodiment of the MCH 300 invokes known RAC commands by previously unavailable hardware and in new methods or sequences.
In this exemplary embodiment, the MCH 300 includes a RAC 330 and a serial interface 340. The serial interface 340 uses clock (SCK), serial frame (CMD), and bi-directional serial I/O pins (SIO0 and SIO1) to read and write RDRAM configuration registers as well as to perform other IOPs. The MCH also includes a device register data (DRD) register 314. The DRD register 314 is at address offset 90-91h in PCI configuration space, the default value is 0000h (16 bits), and the register is a read/write register. The fields of the DRD register are shown in Table 1.
The MCH 300 also includes a RDRAM Initialization Control Management (RICM) Register 312. The RICM Register is at address offset 94-96h in PCI configuration space, the default value is 000000h (24 bits), and the register is a read/write register. The fields of the RICM register for this embodiment are set forth in Table 2.
Also illustrated in FIG. 3 is an initialization control circuit 320 which includes an RDRAM IOP execution circuit 325. Details of the various IOPs executed by the control circuit 320 are illustrated in Table 3. In Table 3, the broadcast address (BA) field (bit 19) and the SDA field (bits 8:4) are listed either as one of the following:
NE: This field has no effect on the initialization operation
0: This field is to be set to 0 for this initialization operation.
1: This field is to be set to 1 for this initialization operation.
x: This field should be programmed as appropriate for the particular initialization operation.
Details of operations conducted by one embodiment of the initialization control circuit 320 in response to receiving the RDRAM Core Initialization IOP (10000b) are shown in FIG. 4. In block 400, a broadcast powerdown exit command is issued on the bus. Next, as per block 405, the sequence indicated by blocks 410 to 470 is repeated sixteen times for bank addresses zero to thirty-one. These numbers may be appropriate for a memory subsystem having one hundred and twenty-eight current calibration levels and up to thirty-two banks. In other embodiments, a different number of repetitions may be used if, for example, a larger or smaller number of current calibration levels are available. Similarly, differing numbers of banks may be available in different systems.
In block 410, no operation is performed to ensure that the powerdown exit is complete and that the refresh operation (REFA command) is properly performed in block 415. In block 420, another no operation command is executed, followed by two more refresh operations (REFA) in blocks 425 and 430. Three more no operation commands are executed in block 435, allowing sufficient time to pass before a refresh precharge (REFP) command occurs. After another no operation command in block 445, another refresh precharge (REFP) command is executed in block 450.
A calibrate (CAL) command is next executed in block 455. This command calibrates (drives) IOL current for the presently indicated device. As indicated in blocks 460 and 465, this operation may be repeated twice. Then, as indicated in block 470, a sample (SAMR) command is executed. The sample command updates the IOL current for the presently indicated device. Until all sixteen repetitions for the thirty-two banks are performed, this process is repeated.
With the above initialization operations, a system may be initialized. For example, the system shown in FIG. 5, which implements a Rambus Direct RDRAM channel, may be initialized. In this system, a memory controller 500 (also referred to as a memory control hub or MCH) orchestrates initialization activities. The memory controller also initiates specific ROW/COLUMN packets on the channel. A serial interface 540 may be used to communicate with devices on the channel. For example, clock (SCK), serial frame (CMD), and bi-directional serial I/O (SIO0 and SIO1) pins may be used to read and write RDRAM configuration registers as well as to perform other IOPs.
The memory controller includes a Rambus ASIC Cell (RAC) 530, a control circuit 520, and a variety of registers. The registers include a initialization registers 515, which are used to initialize the system memory, and powerdown restoration registers 510. The powerdown restoration registers contain timing and other information crucial to operating the memory channel. In other words, the powerdown restoration registers are simply registers that need to be restored after powering down the memory controller 500 in order to resume accesses to the memory channel. The registers may be PCI configuration registers.
The memory channel includes RIMM modules 560, 565, and 570 that are connected to the MCH 500 by a control and data bus 532 and a serial bus 542. The control and data bus 532 may be terminated by a resistive termination 533, and a Direct Rambus Clock Generator (DRCG) 580 may be provided at the far end of the channel from the MCH 500 to provide clock signals over signal lines 582.
Additionally, the system includes an Input/Output control hub (ICH) 505 which couples the MCH to a secondary bus 506 and may contain a second serial interface circuit 544 for interfacing with a second serial bus 546. A serial presence detect (SPD) memory 572 (a non-volatile memory such as an electrically erasable and programmable read only memory) for each module may be read via the serial interface 544 according to a serial presence detect protocol. The SPD memory 572 may provide information such as timing information, device organization, and device technology about each particular memory module. More details of the SPD protocol are discussed in the "Serial Presence Detect Application Brief" as well as the Direct Rambus™ RIMM™ Module and the 64/72 Mbit Direct RDRAM™ data sheets available from Rambus.
In one embodiment, the serial bus 546 is an I2C bus such as a system management bus (SMBus). This embodiment includes clock (SMBCLK) and data (SMBDATA) signals that follow the industry defined System Management Bus (SMBus) protocol as defined in the System Management Bus Specification, Revision 1.0, available from the Smart Battery Implementer's Forum on the Internet at http://www.sbsforum.org.
The ICH has general purpose outputs (GPOs) which are used to control various system functions such as setting the frequency of the DRCG 580. A non-volatile memory 585 containing the BIOS may be coupled to the secondary bus 506, as well as a battery backed-up random access memory 590. The battery backed-up memory 590 may store powerdown restoration configuration values 592 for the MCH powerdown registers 510 so the MCH can resume accessing the RDRAM channel without performing the full initialization sequence detailed below.
Briefly, the initialization process may be summarized as follows. After power up reset, the configuration information from Serial Presence Detection (SPD) data on the RIMMs in a channel is read. For example, a storage device, SPD memory 572, stores configuration information for the RDRAMs 573, 574, 576, and 577 on the RIMM 570. The memory controller configuration registers are programmed with the appropriate values from the SPD information, and then the RDRAM device IDs are programmed such that each RDRAM device can be uniquely identified and accessed by the memory controller. Once a device has been initialized, it can be used.
Each RDRAM device has two identification numbers that are used to uniquely select a device on the channel, the Serial Device ID, and the Group Device ID. These two IDs are used for distinct operations on the RDRAM channel. The serial device ID is used to select devices when the memory controller is sending initialization operations on the SCK, SIO, and CMD signals of the RDRAM channel. The group device ID is used by the memory controller to select a device when sending ROW packets and COLUMN packets on RQ[7:0] signals of the RDRAM channel. Both the serial device ID and the group device ID are programmed after reset and before devices may be individually addressed by initialization operations (IOPs) and ROW/COLUMN packets, respectively.
Looking at the initialization process of the Rambus channel in more detail, a particular sequence may be followed to achieve correct operation of the RDRAM devices on the channel. FIG. 6 illustrates a flow diagram for proper channel initialization in one embodiment, and Table 4 enumerates some of the variables used in this initialization flow.
In block 602, system reset occurs. The MCH resets all its state machines and prepares for initialization. In block 604, memory module configuration of the system is verified. The BIOS reads SPD data to determine the memory configuration. If only RIMMs are present, the RDRAM initialization sequence may proceed with block 608. If mixed memory modules are present, an error is posted to the user and the system is halted as indicated in 606.
The clock generator is started in block 608. This operation may be accomplished by software querying the SPD data of every RIMM module present on the motherboard and determining a channel frequency at which all RIMMs may operate. The DRCG 580 may be set to the proper frequency by a general purpose output (i.e., GPOx as shown in FIG. 5) from the ICH 505. In one embodiment, the BIOS waits at least 5 ms between this step and the MCH RAC initialization.
As indicated in block 610, the MCH RAC is next initialized. The channel clock from the DRCG should be stable prior to MCH RAC initialization. The MCH RAC initialization is accomplished by executing the MCH RAC initialization IOP. The RAC initialization IOP performs basic initialization to prepare the internal RAC of the memory controller for normal operation.
In one embodiment, the BIOS provides a time out of 5 ms for the IIO bit to clear after the MCH RAC initialization IOP. If the IIO bit is not cleared by the MCH after 5 ms, the BIOS should report the error, and the channel is unusable. An additional 5 ms delay may be added after the MCH clears the IIO bit due to completion of the MCH RAC initialization IOP. This allows sufficient time for the MCH clocks to stabilize and lock. Also in some embodiments, a bus in the RAC may need to be cleared before other operations commence. This may be accomplished by executing the MCH RAC Control Register Load IOP (DRD=00000h). It may also be possible to perform the RAC initialization at a later point in the initialization sequence in some embodiments.
As indicated in block 612, a number of MCH configuration registers may next be initialized. In one embodiment, the paging policy register RMC idle timer (PGPOL RIT) field (MCH 052h [2:0]) is set to 001b to ensure no pages are closed during channel levelization (discussed below). The PGPOL RIT field sets the number of host bus clocks that the memory controller will remain in the idle state before all open pages are closed, and a value of zero indicates that there will be an infinite latency before the memory controller starts closing pages.
Additionally, in some embodiments, operating pools may be used to group RDRAMs based on defined RDRAM states. In order to reduce operating power, the RDRAM devices may be grouped into two operating pools called "Pool A" and "Pool B." In one embodiment, up to eight devices may be in Pool A at a time. In this embodiment, up to four out of eight devices in Pool A may be in Active Read/Write or Active states at a time, and the devices in Pool A are in either Active Read/Write, Active, or Standby states.
The maximum number of devices in Pool A is programmable and is specified by a PAC field of the RDRAM power management register (RPMR) register (MCH 053h). All devices that are not in Pool A are members of Pool B. All devices in Pool B are either in the Standby or Nap state. The state of the devices in Pool B is specified by a PBS field of a DRAM control (DRAMC) register (MCH 051h). In one embodiment, the RPMR register is set to 00h, selecting a pool A of 1 device only, and Pool B operation is set for standby operation (MCH 051h [6]=0).
Next, as indicated in block 614, additional channel initialization may be performed. This may include performing an SIO (serial interface) reset using the SIO reset IOP, and allowing sufficient delay for completion of the SIO reset sequence. Additionally, other registers which may need to be initialized for proper operation may be set at this point. For example, in some embodiments, a Test77 register may need to be written to with a zero value after the SIO reset as specified on page 37 of the Direct RDRAM 64/72 Mbit Data Sheet (execute a Broadcast SIO Register Write IOP: TEST77, DRA=4Dh, DRD=0000h).
As indicated in block 620, serial device identification values (IDs) may be assigned next. In general, the software uniquely identifies each device on the channel to allow initialization operations to be targeted at individual devices. The serial device ID for each RDRAM is stored in the RDRAM INIT register (index 21h) in bits 4-0. After SIO reset, the default value of the serial device ID is 1Fh in all RDRAMs on the channel. Also, after reset, the Serial Repeater (SRP bit (RDRAM 021h [7]) is set to 1, enabling each RDRAM to propagate SIO data received on SIO0 to the RDRAM's SIO1 pin, passing the SIO packet to the next RDRAM device. Since all devices have the same serial device ID after reset, an individual device may not be accessed prior to assigning unique serial IDs.
Further details of the serial device enumeration performed by one embodiment are shown in FIG. 7. In block 700, the variable SerialIDCount is initialized to zero. Next, as indicated in block 705, the SIO repeaters of all devices on the channel are disabled (Broadcast SIO Register Write IOP. INIT, DRA=21h, DRD=001Fh). This operation causes all serial device IDs to be set to 01fh. The SIO repeater bit is set to zero, so only the first device on the SIO channel can be accessed.
Starting with block 710, the process loops through all devices on the channel and assigns a unique ID to each. The serial ID of the current device is set to SerialIDCount and the SIO repeater bit is enabled (SIO Register Write IOP: INIT, SDCA=1Fh, DRA=21h, DRD=0080h +SerialIDCount). Next, whether the device is actually present and functioning in the system is tested as indicated in block 715. The RDRAM INIT register is read to determine if the same value which was just written is properly read back out (SIO Register Read IOP. INIT, SDCA=SerialIDCount, DRA=21h).
If the data matches (as tested in block 720), serialIDcount is incremented (block 725), and the serialIDCount is checked to see whether a maximum number of devices (e.g., thirty-two) have been given IDs (block 730). If the serialIDCount still indicates a valid serial ID, the next device is identified in block 705.
If the serialIDCount exceeds the maximum permissible value, or if the data did not match in block 720, then the last device has been given an ID, and a variable tracking the total number of devices may be set to the serialIDCount as indicated in block 735. Finally, to disable any additional devices beyond the last permitted device, the SIO repeater of the RDRAM with the highest serial ID is disabled as shown by block 740. Accordingly, any additional devices (i.e., improperly functioning devices or devices beyond the maximum, e.g., thirty-two) do not receive commands and therefore should not respond. As an additional check, the SPD information on the RIMMs may be examined to determine if the final device count is correct.
Returning to FIG. 6, after the unique serial IDs have been assigned and the SIO output of the last device disabled, group IDs are assigned based on memory device size as indicated in block 630. In one embodiment, the MCH supports up to thirty-two RDRAM devices and eight groups. Each group has up to four devices and has a group boundary access register (GBA) to define the group ID and the upper and lower addresses for each group. Thus, each GBA register may be programmed with a group ID and a nine bit upper address limit value. Unpopulated groups may have a value equal to the previous group and a group size of zero.
Additionally, the flowchart in FIGS. 8A-8C illustrates one embodiment of the process of enumerating group device IDs indicated in block 630. As indicated in block 800 in FIG. 8A, a number of variables are initialized. Variables SerialIDCount, GroupDeviceIDCount, RIMMCount, RIMMDeviceCount, and RIMMDeviceConfigNo are initialized to zero. A DRAMConfigIndex variable is initialized to a value indicating the largest core technology supported by the MCH.
As indicated in block 805, data is read from the SPD memory of a module (module number RIMMCount) identifying the core technology of that module. This information may include the number of rows per device, the number of columns per device, the number of banks per device, and whether the banks are dependent or independent. Next, as indicated in block 810, the RIMMDeviceConfigNo is set by translating the core technology value read from the SPD into a value in a Group Architecture (GAR) register equivalent value.
Next, as indicated in block 815, the RIMMDeviceCount variable is set to the number of devices indicated by the SPD memory for that RIMM. Thereafter, the device IDs may be assigned and associated register values set as indicated in block 820. Further details of the process indicated in block 820 for one embodiment are shown in FIG. 8B.
In general, the enumeration process adds the number of RDRAM devices on a RIMM to the first Serial ID and then counts down until the RIMM is finished. Therefore, as indicated in block 822, whether RIMMDeviceConfigNo equals the DRAMConfigIndex is tested to determine whether group device IDs have been assigned for all devices in a particular core technology. If they are unequal, all devices for that core technology have group IDs, so the SerialIDCount is set to SerialIDCount plus RIMMDeviceCount (as indicated in block 830) and the process returns to FIG. 8A as indicated in block 832. Additionally, if RIMMDeviceCount is zero (as tested in block 824) or MemberCount is zero (as tested in block 826), there are no more devices to give group IDs and the process returns to FIG. 8A as indicated in block 832.
If RIMMDeviceCount and MemberCount are not zero, a GroupDeviceIDCount is assigned to be the group device ID of the RDRAM with the serial ID equal to the present value of SerialIDCount as indicated in block 828. Next, the current group boundary address register (GBA) is updated to reflect the addition of the new device to this group as indicated in block 830. This may be accomplished by adding a value indicative of the device size to the previous value stored in that GBA register.
Next, the GroupDeviceIDCount is compared to four (the maximum number of devices per group in one embodiment) in block 832. If the group is full, the MCH Group Architecture Register (GAR) for that group is updated as indicated in block 834. The GAR is updated to properly indicate the group configuration (i.e., the number of banks and the DRAM technology (size)). In block 836, SerialDeviceIDCount is incremented, MemberCount is decremented, GroupDeviceIDCount is incremented, and RIMMDeviceCount is decremented. The process then returns to block 824.
Returning to FIG. 8A, if either RIMMDeviceCount or MemberCount is zero, RIMMCount is incremented as indicated in block 850. If RIMMCount is less than a maximum RIMMCount, as tested in block 855, then the process returns to block 805. If the RIMMCount has reached the last RINM, the process continues in FIG. 8C as indicated by block 860.
Turning to FIG. 8C, if MemberCount is zero (as tested in block 865), the device ID enumeration process ends. If, however, MemberCount is not zero, the next MCH group is selected to start enumerating the devices in the next DRAM technology as indicated in block 870. GroupDeviceIDCount may be updated by adding three and performing a logical AND operation of the resulting value and 0FFFCh.
If GroupDeviceIDCount is a maximum number devices allowed in the channel (e.g., thirty-two as tested in block 872), then the group ID enumeration process ends. If, however, fewer devices have been given group ID numbers, the DRAMConfiglndex is set to the next smallest core technology supported by the MCH as indicated in block 874. If the DRAMConfigIndex indicates that there are no smaller core technologies supported (e.g., DRAMConfigIndex is zero as tested in block 876), then the ID enumeration process ends. If there are more core technologies, serialIDCount and RIMMCount are reset to zero, as indicated in block 878, and the process returns to block 805 in FIG. 8A.
The psuedo-code below indicates operations that may be used to perform the group ID enumeration indicated by block 630 of FIG. 6 in one embodiment.
630. Enumerate MCH device groups.
630.1. Loop through RIMM SPD memory and group the devices on the RIMMs.
The largest technology devices must be grouped in the lowest groups, with the technology size decreasing as the group #s increase.
630.1.1. Set MemberCount=MemberMax
630.1.2. Set SerialIDCount=0. This is the Serial Device ID counter
630.1.3. Set GroupDeviceIDCount=0. This is the Group Device ID counter
630.1.4. Set RIMMCount=0. This is the RIMM counter
630.1.5. Set RIMMDeviceCount=0. This is the counter for the # of devices on a RIMM.
630.1.6. DRAMConfiglndex=Largest technology supported by MCH
630.1.7. Compute RIMM #RIMMCount's core technology
6126.96.36.199. RIMMDeviceConfigNo=core technology read from RIMMs SPD.
630.1.8. RIMMDeviceCount=# of RDRAM devices in RIMM
#RIMMCount, read from the RIMM's SPD EEPROM.
630.1.9. Assign group device IDs and program MCH GAR and GBA registers for RIMM.
630.1.630.1. If RIMMDeviceConfigNo!=DRAMConfigIndex,
break to 630.1.10
6188.8.131.52. If RIMMDeviceCount=0, break to 630.1.10
622.214.171.124. If MemberCount=0, break to 630.1.10
6126.96.36.199. SIO Register Write IOP. DEVID, SDCA=SerialIDCount, DRA=40h, DRD=GroupDeviceIDCount.
622.214.171.124. Program MCH GBA[GroupDeviceIDCount SHR 2]=MCH GBA[GroupDeviceIDCount SHR 2−1]+RIMM #RIMMCount device size.
6184.108.40.206. If GroupDeviceIDCount AND 011b=0
6126.96.36.199.1. Program MCH GAR[GroupDeviceIDCount SHR 2]=RIMMDeviceConfigNo
622.214.171.124. Increment GroupDeviceIDCount
6220.127.116.11. Increment SerialIDCount
6220.127.116.11. Decrement MemberCount
6220.127.116.11. Decrement RIMMDeviceCount
6188.8.131.52. Go to step 618.104.22.168
630.1.10. Increment RIMMCount
630.1.11. IfRIMMCount<RMMMax, go to step 630.1.7
630.1.12. If MemberCount=0 then break to step 10
630.1.13. Select next group for next RDRAM technology.
6126.96.36.199. GroupDeviceIDCount=(GroupDeviceIDCount+011b) AND 011b
630.1.14. If GroupDeviceIDCount=32 then break to step 10
630.1.15. DRAMConfigIndex=next smallest DRAM technology
630.1.16. If DRAMConfigIndex=0, then break to step 10
630.1.17. SerialIDCount=0
630.1.18. RIMMCount=0
630.1.19. Go to step 630.1.7. This will begin searching the RIMMs for the next smallest RDRAM technology.
Returning to FIG. 6, after the group IDs have been assigned, the individual RDRAM devices may be brought out of powerdown mode and put into fast clock mode for normal operation as indicated in step 640. The individual RDRAM timing registers in the MCH and RDRAMs may be programmed. The REFB and REFR RDRAM control/ registers may also be initialized (Broadcast SIO Register Write IOP. REFB, DRA=41h, DRD=0000h; Broadcast SIO Register Write IOP. REFR, DRA=42h, DRD=0000h).
The RDRAM devices may be reset by executing a Broadcast Set Reset IOP, followed by an appropriate delay (e.g., 32 us), then executing a Clear Reset IOP, also followed by an appropriate delay (e.g., 4 us) to allow for the reset operation to complete. The RDRAMs are brought out of powerdown by executing a broadcast RDRAM power down exit IOP, and the fast clock mode is entered by executing a broadcast RDRAM Set Fast Clock Mode Initialization IOP.
Thereafter, the RDRAM cores may be initialized as indicated in block 642. Further details of one embodiment of the RDRAM core initialization are shown in FIG. 9. As indicated in block 900, the RDRAM devices are prepared for current calibration by writing an intermediate value to the appropriate RDRAM registers (Broadcast SIO Register Write IOP. CCA, DRA=43h, DRD=0040h; Broadcast SIO Register Write IOP. CCB, DRA=44h, DRD=0040h). Forty hexadecimal may be an appropriate intermediate value in an embodiment that has one hundred and twenty-seven possible current calibration levels. Starting at this intermediate value limits the total number of calibration cycles needed since the calibration value could only be off by approximately half than the full range of calibration values.
Next, precharge operations are performed on each bank of each RDRAM device. To perform the precharge operations, the MCH counts up through the banks by two, first precharging odd banks, and then even ones. A bank index is set to zero in block 905. A broadcast precharge IOP is then executed as indicated in block 910. The bank index value is incremented by two as indicated in block 915, and the broadcast precharge is repeated for even banks until the bank index is found to be equal to a maximum number of banks (e.g., thirty two) in block 920.
Once the maximum number of banks is reached, the bank index is set to one (as indicated in block 930), and all odd banks are precharged. Once the bank index exceeds the maximum number of banks, the RDRAM Core Initialization IOP is executed six times as indicated in block 940.
Returning to FIG. 6, after the initialization of the RDRAM cores in block 642, the channel may be levelized as indicated in block 644. This process involves equalizing the sum of the RDRAM read response time and a propagation delay from the RDRAM to the MCH for all RDRAMs. In other words, once the channel is levelized, all RDRAMs will provide data at the memory controller in the same number of bus cycles.
The following psuedo-code indicates a sequence of steps that may be performed in one embodiment to implement the levelization process indicated in block 644. 644. Levelize the Rambus channel
644.1. Phase 1: Determine MCH tRDLY field value.
644.1.1. SerialIDCount=MemberMax
644.1.2. MchTrdly=0
644.1.3. Program MCH RDT:TRDLY field=MchTrdly.
644.1.4. Compute the 32 bit address to test the RDRAM device for levelization.
6220.127.116.11. SIO Register Read IOP. DEVID, SDCA=SerialIDCount, DRA=40h
6188.8.131.52. The DRD (MCH 090h [15:0]) now contains the RDRAM's Device ID
6126.96.36.199. DeviceTestAddress=MCH GBA[(DRD SHR 2)−1]
SHL 23+((DRD AND 011b)*device size in bytes (from GAR[DRD SHR 2])
644.1.5. Do QWORD write operation to address DeviceTestAddress with TestPattern.
644.1.6. Do QWORD read operation to address DeviceTestAddress
644.1.7. If data read !=TestPattern
6220.127.116.11. Increment MCH RDT:TRDLY field.
6184.108.40.206. If MCH RDT:TRDLY field<=4 then break to step
644.1.8. Else (if data read=TestPattern)
622.214.171.124. MchTrdly=data read from MCH RDT:TRDLY field
618.104.22.168. if MchTrdly=4 then break to step 644.2
644.1.9. Decrement SerialIDCount
644.1.10. If SerialIDCount>=0 then go to step 644.1.3
644.2. Phase 2: Determine the RDRAM's levelization timing values
644.2.1. SerialIDCount=MemberMax
644.2.2. Compute the 32 bit address to test the RDRAM device for levelization.
6220.127.116.11. SIO Register Read IOP. DEVID, SDCA=SerialIDCount, DRA=40h
618.104.22.168. The DRD (MCH 090h [15:0]) now contains the RDRAM's Device ID
622.214.171.124. DeviceTestAddress=MCH GBA[(DRD SHR 2)−1]
SHL 23+((DRD AND 011b)*device size in bytes (from GAR[DRD SHR 2])
644.2.3. Do QWORD write operation to address DeviceTestAddress with TestPattern.
644.2.4. Do QWORD read operation to address DeviceTestAddress
644.2.5. If data read=TestPattern then break to step 644.2.8
644.2.6. If TCDLY field of RDRAMs<Max TCDLY (from SPD)
6188.8.131.52. increment the RDRAMs TCDLY registers (TDAC & TRDLY) according to the TCDLY support table.
622.214.171.124. Break to step 644.2.3
644.2.7. Mark the RDRAM device to be disabled.
644.2.8. Decrement SerialIDCount
644.2.9. If SerialIDCount>=0 then go to step 644.2.2
After levelization completes, one embodiment stores a number of powerdown recovery memory initialization values in the battery backed-up memory 590 of FIG. 5 as indicated in block 646. Notably, this operation may be performed at any other stage after the appropriate values have been determined by the initialization routine. The values are saved to preserve the initialization information determined by the initialization process to this point.
When a low power state (e.g., suspend-to-RAM) is entered by the system, power to the MCH may be removed. Thus, if the initialization information is not preserved, the entire initialization process may have to be repeated. Storing key initialization information to a non-volatile memory may advantageously speed wake-up from such a low power state. The difficulty of storing such information is increased by the fact that the memory subsystem will not be functional until these values are restored.
Any non-volatile memory which can be written to may be used to store the appropriate initialization information; however, a battery backed-up memory is present in many computer systems and therefore may be a convenient choice. In one embodiment, the registers below are stored in the memory 590.
MCH Group Architecture (GAR) registers (040-047h): These registers indicate device configuration for each group such as the number of banks and the DRAM technology (size).
MCH RDRAM Timing Register RDT (050h): This register defines the timing parameters for all devices in the channel.
MCH DRAM Control (DRAMC) register (051h): This register includes the Pool B Operation Select (PBS) bit, a memory transfer hub presence bit (MTHP), which specifies an operational mode of the MCH, and an Aperture Access Global Enable bit which prevents access to an aperture from any port before the aperture range and translation table are established.
MCH Page Policy (PGPOL) Register (052h): This register specifies paging policy attributes include a DRAM Refresh Rate (DRR) and a RMC Idle Timer (RIT). The DRR field adjusts the DRAM refresh rate and the RIT field determines the number of host bus clock cycles that the memory controller will remain in the idle state before all the open pages are closed.
MCH RPMR (053h): This register includes a Device Napdown Timer (DNT) field, an Active Devices in Pool A (ADPA) field, a Device Napdown Enable (DNE) field, and a Pool A Capacity (PAC) field. The DNT field specifies the number of host clocks the memory controller is idle before the least recently used device in Pool A is pushed out to Pool B. The ADPA field defines the maximum number of RDRAM devices in Pool A that can be in Active Read/Write or Active state at a time. The devices in Pool A that are not in Active Read/Write or Active state are in standby state. The DNE bit (when set to 1) enables the channel inactivity counter to count continuous inactivity time. When the counter value exceeds the threshold specified by DNT, the least recently used device from Pool A is pushed to Pool B. The PAC field defines the maximum number of RDRAM devices that can reside in Pool A at a time. Devices that are not part of Pool A belong to Pool B.
MCH Group Boundary Access (GBA) registers (060-6Fh): The GBA registers contain a group ID and a value indicating the upper address limit for the group.
MCH Configuration Registers MCHCFG (0BE-BFh): These registers contain the Rambus Frequency & DRAM Data Integrity Mode fields.
Also, at this point powerdown configuration options may be programmed. In one embodiment, the self refresh and low power self refresh options are set (for each SerialIDCount: SIO Register Write IOP. INIT, SDCA=SerialIDCount, DRA=21h, DRD=400h (LSR, if SPD supports)+200h (PSR)+80h (SRP)).
Normal operation may start, as indicated in block 650, after a few more registers are programmed for normal operation. The page policy register is set to operate normally (PGPOL RIT field (MCH 052h [2:0]) to 001b) since the page closing timer was effectively disabled for levelizing, and the power management features are enabled at this point via the RPMR register (MCH 053h). If the Pool B Select bit (MCH 051h [6]) is configured for NAP operation, a broadcast NAP entry IOP may be executed to put all devices to the NAP state. In the same I/O instruction that sets the IIO bit, set the IC bit in RICM also to one so that normal operations of the MCH may commence.
After normal operation continues for some time, the system may enter a low power state due to system inactivity or for another reason, as indicated in block 1000 of FIG. 10. One state which the system may enter is a suspend-to-RAM (STR) state in which the MCH loses values stored in its registers. After entering the STR state, an event which causes the system to exit STR may be sensed as indicated in block 1010. Accordingly, the BIOS powers up the MCH and other system components. The configuration registers of the MCH may be automatically reset to a default value in this process.
Accordingly, to again access memory devices on the memory channel, at least some of the configuration register values are needed. The BIOS may cause the ICH 505 to access the battery backed-up memory 590 and restore the registers listed below (saved in block 646 of FIG. 6).
MCH GAR registers (040-047h)
MCH RDT (050h)
MCH DRAMC (051h)
MCH PGPOL (052h)
MCH RPMR (053h)
MCH GBA registers (060-6Fh)
MCH Configuration Registers MCHCFG (0BE-BFh)
After restoring values to these registers, the MCH can once again access items stored in memory when the STR state was entered, including such items as the processor context if saved. The memory devices perform self-refresh in the STR state so other data is not lost.
Next, the clock generator is started as indicated in block 1040. The proper Rambus channel frequency is read from the MCH MCHCFG register (MCH OBEh [11], which was restored in block 1030). After the clock is allowed to stabilize, the MCH RAC is initialized as indicated in block 1050. This may be accomplished by executing the MCH RAC Initialization IOP. Additionally, the DRD register may be loaded with 0000h and the MCH RAC control register load IOP executed to initialize a bus in the RAC (as discussed with respect to block 610).
Next, current calibration is performed as indicated in block 1060. This may be performed as discussed with respect to block 642 and FIG. 9. In the final iteration indicated by block 940, however, the IC bit in the RICM register may be set, allowing normal operations to immediately commence once the current calibration has completed.
Thus, the resume from STR sequence may be substantially faster than the entire initialization sequence required when the system is first powered up since channel levelization, SPD querying, ID assignment, and a number of other initialization operations may be avoided.
In conclusion, a method and apparatus for initializing a memory device and a memory channel is disclosed. While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art upon studying this disclosure.
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In its over 100-year history, the Ignatian Literary Magazine has had many names and titles. The original Ignation, released in 1910, served as a literary journal, alumni magazine, and sports report for the university. In 1924, the Ignatian changed directions to become USF's annual yearbook, known as The Don. In the 1930s and 40s, The Don became the San Francisco Literary Quarterly (SFLQ), publishing writings by faculty, staff, and students. In 1960s, a magazine called The Gaviota replaced the SFLQ. During this time, the magazine moved off of the USF campus after the publication's editors felt that their freedom of expression was being threatened.
After a hiatus in the 1970s, USF's student newspaper, The Foghorn, collected and occasionally published student work in a special section. In 1988, the Ignatian was revived due to student interest and renewed ASUSF funding, though it appeared in a newspaper format for several years.

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The Breaking Bad star told Details that he was one of the lucky attendees at the Prince of Brunei's 25th birthday celebration six years ago. At the lavish event, the actor was treated to a ride on the prince's hovercraft among other treats. But the night managed to get even better when Paul met – drumroll – Michael Jackson.
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Play: Psychoanalytic Perspectives, Survival and Human Developmentby Perroni; Emilia
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Is play only a children's activity? How is the spontaneous play of adults expressed? What is the difference between play and game? What function does play have during war? Play:Psychoanalytic Perspectives, Survival and Human Development explores the importance of play in the life of the individual and in society. Most people associate psychoanalysis with hidden and negative instincts, like sexuality and aggressiveness, very seldom with positive urges like the importance of love and empathy, and almost never with play. Play, which occupies a special place in our mental life, is not merely a children's activity. Both in children and adults, the lack of play or the incapacity to play almost always has a traumatic cause this book also shows the crucial importance of play in relation to the survival in warfare and during traumatic times. In this book Emilia Perroni argues that whether we regard play as a spontaneous creation or whether we see it as an enjoyable activity with defined rules (a game), that it is impossible to conceive human existence and civilization without it. The papers collected in this book are the results of the research offered on the subject of play by several Israeli therapists from different psychoanalytic schools Freudian, Jungian, Kleinian, Winnicottian and Self-Psychology. Other contributions are from Israeli researchers and academics from various fields such as literature, music, art, theatre and cinema, contemporary psychoanalysis and other disciplines. Play: Psychoanalytic Perspectives, Survival and Human Developmentoffers new ways to think about, and understand, play as a search for meaning, and as a way of becoming oneself. This book will be of interest to psychoanalysts, researchers, therapists, parents, teachers and students who are interested in the application of psychoanalytic theory to their fields including students of cultural studies, art, music, philosophy. Emilia Perroni is a clinical psychologist, supervisor at the School of Psychoanalytic Psychotherapy at the University of Tel Aviv and the Bar Ilan University. She has a private practice in Jerusalem and in Tel Aviv. She is a member of the Israeli Association of Psychoanalytic Psychotherapy, the Israeli Association of Psychotherapy, she is an Associated-Member of the Israeli Institute of Jungian Psychology, and Research Fellow at the Van Leer Institute in Jerusalem.


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India's Position in International Climate Negotiations
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This paper examines the relationship between disaster risk reduction (DRR) and emerging climate change adaptation (CCA) and how these two agendas are influenced by different governance systems, accountabilities and social contracts in Zambia, Uganda,... More on «Towards 'Good Enough' Climate and Disaster Risk Governance»
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This issue of the Central Asia-Caucasus Analyst includes articles on 1) Russia's preparation of the annexation of the Georgian breakaway region Abkhazia; 2) the new agreement allowing US and NATO forces to stay in Afghanistan beyond 2014; 3) the Indi... More on «Central Asia-Caucasus Analyst, Vol 16, No 22»
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Sep 2014
The US-India Relationship
Author: John M Bryson, Barbara C Crosby, Melissa Middleton Stone, David M Sarcone, Chandrashekhar Dasgupta, Jeffrey D McCausland, Vijay Kumar Singh, Jack Clarke, Richard Matthew, Stephen Blank, Leif Rosenberger, Andrew Salamone, Rahul S Madhavan, Namrata Goswami, Ivan Welch, Dhanasree Jayaram, Krishnappa Venkatshamy, Michael D Beevers, Rajesh Chakrabarti, Santosh Srinivas, Lalitha Vaidyanathan, Julie Vastine, Todd Camp, Khanjan Mehta, Michael J Fratantuono
Publisher: Strategic Studies Institute of the US Army War College (SSI)
This book features a number of papers from a workshop on collaboration between governments, militaries, profit and non-profit organizations, and intergovernmental organizations, particularly in relation to sustainable development and US-India relatio... More on «The US-India Relationship»
Sep 2014
Klimawandel: Alle triffts, die Armen stärker
Publisher: Swiss Federal Department of Foreign Affairs (FDFA)
Diese Ausgabe der Zeitschrift "Eine Welt" der Direktion für Entwicklung und Zusammenarbeit (DEZA) beinhaltet unter anderem Artikel zum Thema 1) Klimawandel und dessen Auswirkungen auf Armut und Entwicklungsbemühungen; 2) die Aktivitäten der DEZA bei ... More on «Klimawandel: Alle triffts, die Armen stärker»


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WBGO Travel: Newport Jazz Festival 2014 Day Trips
January 8, 2014. Posted by Brandy Wood.Add new comment | Filed under: anat cohen, Bobby McFerrin, brian blade, BRIC, Cécile McLorin Salvant, David Sanborn, dee dee bridgewater, Dr. John, gary burton, george wein, gregory porter, Jazz Alive, jazz at lincoln center, Lee Konitz, miguel zenon, Newport Jazz, Newport Jazz Festival, njpac, Ravi Coltrane, Robert Glasper, SF Jazz Collective, WBGO Travel, wynton marsalis
WBGO Travel invites you to hop aboard the bus from either New York City (Jazz at Lincoln Center, 10 Columbus Circle), Brooklyn (BRIC House, 647 Fulton St. at Rockwell Place), New Jersey (NJPAC, 1 Center Street, Newark) or Boston (Berklee School of Music, 1140 Boylston Street) for a direct ride to the front gate of the 60th Anniversary of the Newport Jazz Festival in Newport, Rhode Island on Friday, August 1, Saturday, August 2 or Sunday, August 3. This excursion includes: round trip bus travel from departure location directly to the festival gate, general admission ticket to the festival for the full day plus access to the WBGO Shade Tent on the festival grounds. Bus will have wifi, restroom and reclining bucket seats.
The full lineup is listed below, and includes exciting artists such as Wynton Marsalis and the Jazz at Lincoln Center Orchestra, Gregory Porter, Anat Cohen, Ron Carter, Dr. John, Gary Burton with Julian Lage, Robert Glasper, Trombone Shorty, Darcy James Argue, Lee Konitz, Dave Holland's Prism and Cecile McClorin Salvant.
Buses have varying departure times, please check below for specific times from your departure location. At the end of each day, buses leave from the front gate of the Newport Jazz Festival. Return times leaving festival are as follows: Friday 6PM, Saturday & Sunday 7PM.
Details of RT New York City (Jazz at Lincoln Center) to Newport trip:
• Friday – board the bus at 6AM at Jazz at Lincoln Center (10 Columbus Circle NY, NY) located at The Time Warner Building at the front circle. Bus will depart promptly at 6:30AM.
• Saturday or Sunday – board the bus at 5AM at Jazz at Lincoln Center (10 Columbus Circle NY, NY) located at The Time Warner Building at the front circle. Bus will depart promptly at 5:30AM.
• This location only will have an extra drop in Harlem on the way back to Jazz at Lincoln Center.
Details of RT Brooklyn (BRIC House) to Newport trip:
• Saturday or Sunday – board the bus at 5AM at BRIC House located at 647 Fulton St. at Rockwell Place. Bus will depart promptly at 5:30AM.
Details of RT New Jersey (NJPAC) to Newport trip:
• Saturday or Sunday – board the bus at 5AM at NJPAC located at 1 Center Street, Newark. Bus will depart promptly at 5:30AM.
• Parking will be available at Military Park Garage.
Details of RT Boston (Berklee) to Newport trip:
• Friday – board the bus at 8:30AM at Berklee School of Music located at 1140 Boylston Street. Bus will depart promptly at 9AM.
• Saturday or Sunday – board the bus at 7:30AM at Berklee School of Music located at 1140 Boylston Street. Bus will depart promptly at 8AM.
Line up for the festival*:
Friday, August 1, 2014, 11:30 am – 6:00 pm
Fort Adams State Park, 90 Fort Adams Drive, Newport, RI 02840
Jon Batiste & Stay Human
John Zorn's Masada Marathon: Dave Douglas, Marc Ribot, Cyro Baptista, Mark Feldman, Erik Friedlander, Ikue Mori, Greg Cohen, Joey Baron, Kenny Wollesen & many others
Miguel Zenón Big Band
Darcy James Argue's Secret Society
Snarky Puppy
Cécile McLorin Salvant
Rudresh Mahanthappa – Charlie Parker Project, A World Premier
Amir ElSaffar Quintet with Ole Mathisen, John Escreet, Francois Moutin & Dan Weiss
Mostly Other People Do The Killing: Steve Bernstein, Jon Irabagon, Dave Taylor,Brandon Seabrook, Ron Stabinsky, Moppa Elliott & Kevin Shea
Berklee Global Jazz Ambassadors
University of Rhode Island Newport Jazz Big Band
Saturday, August 2, 2014, 10:30 am – 7:00 pm
Fort Adams State Park, 90 Fort Adams Drive, Newport, RI 02840
Jazz at Lincoln Center Orchestra with Wynton Marsalis
Trombone Shorty & Orleans Avenue
Dave Holland Prism with Kevin Eubanks, Craig Taborn & Eric Harland
Gregory Porter
Robert Glasper Experiment
SF Jazz Collective: Miguel Zenón, Avishai Cohen, David Sanchez, Robin Eubanks, Warren Wolf, Edward Simon, Matt Penman & Obed Calvaire
Cécile McLorin Salvant
Brian Blade & The Fellowship Band with Jon Cowherd, Chris Thomas, Melvin Butler & Myron Walden
Pedrito Martinez Group featuring Ariacne Trujillo with Alvaro Benavides & Jhaire Sala
Dick Hyman, Howard Alden & Jay Leonhart
Kurt Rosenwinkel Quartet
Newport Now 60 Band: Anat Cohen, Karrin Allyson, Randy Brecker, Mark Whitfield, Peter Martin, Larry Grenadier & Clarence Penn
Umbria Jazz presents Stefano Bollani & Hamilton de Holanda
Symposium on Jazz
And More …
Sunday, August 3, 2014, 10:30 am – 7:00 pm
Fort Adams State Park, 90 Fort Adams Drive, Newport, RI 02840
Bobby McFerrin spirityouall
David Sanborn & Joey DeFrancesco with Billy Hart & Warren Wolf
Dr. John & The Nite Trippers
Gary Burton New Quartet with Julian Lage, Scott Colley & Marcus Gilmore
Vijay Iyer Sextet with Graham Haynes, Mark Shim, Steve Lehman,Stephan Crump & Marcus Gilmore
Danilo Perez Panama 500 with Ben Street, Adam Cruz & Roman Diaz
Django Festival All-Stars featuring Samson Schmitt, Ludovic Beier, Pierre Blanchard, DouDou Cuillerier & Brian Torff
Ron Carter Trio with Russell Malone & Donald Vega
Lee Konitz Quartet with special guest Grace Kelly
Ravi Coltrane
The Cookers: Gary Bartz, Billy Harper, Eddie Henderson, David Weiss, George Cables, Cecil McBee & Billy Hart
Mingus Big Band
The Brubeck Brothers
George Wein & Newport All-Stars with Anat Cohen, Howard Alden, Randy Brecker, Lew Tabackin, Jay Leonhart & Lewis Nash
And More …
*Schedule Subject to Change Visit newportjazzfest.org for most up to date listing.
Rates & Reservations:
Same Day Round Trip from NYC, NJ & Brooklyn
WBGO Member price per person: Friday - $185, Saturday/Sunday - $225
Non-Member price per person: Friday - $205, Saturday/Sunday - $245
Student price per person: Friday - $145, Saturday/Sunday - $165
(must show valid student ID at festival gate)
Round Trip from Boston
WBGO Member price per person: Friday - $145, Saturday/Sunday - $185
Non-Member price per person: Friday - $165, Saturday/Sunday - $205
Student price per person: Friday - $120, Saturday/Sunday - $140
(must show valid student ID at festival gate)
Bus cancellation policy:
Until May 15 – guest will receive a full refund, less a $25 processing fee.
Until June 20 – guest will receive a 50% refund.
Until July 14 – guest can transfer their package to another guest, no refund after this date.
For questions or reservations call 973-624-8880 x269 or email firstname.lastname@example.com. Please indicate departure city.Get your WBGO Folding ChairIf you do not have a chair that meets the regulations of the Festival, we will have some onsite for purchase. If you advise us by reply email or phone that you are interested we will have it for you when you arrive for $30. Should you purchase it onsite it will be $40.
Dimensions are : 29"H x 19" W x 19" L. Seat to floor is approx. 18" H. Weight limit – approx. 250 lbs. It folds and fits into a carrying case with a strap, they are lightweight and easy to move about. Available in red or blue. There is limited availability!
WBGO part of Endless Arts Month in Newark
October 1, 2012. Posted by Brandy Wood.Add new comment | Filed under: concerts, Democracy of Jazz, Endless Arts October, Jazz Alive, Newark Arts, Newark CVB, njpac, wbgo
Did you know that WBGO is Newark Public Radio? It's not just the station's corporate name, it is part of everything we do. We are proud to be the community radio station for New Jersey's largest city.
This month, WBGO and other Newark arts organizations are teaming up to showcase the amazing cultural richness that exists in Newark. This effort, spearheaded by the Newark Convention & Visitors Bureau is called Endless Arts October.
WBGO activities during Endless Arts October include our partnership with the TD James Moody Democracy of Jazz Festival, The WBGO Kids Jazz Concert Series, Too Heavy for Words, a gallery exhibit at the station featuring works by four New Jersey photographers, which will be part of Newark Art's Open Doors celebration, and of course, our ongoing, award-winning jazz and news programming.
Take a look at the Endless Arts October guide below and start planning your visit to WBGO's hometown!Open publication - Free publishing - More arts
JazzSet Presents Randy Weston's African Rhythms
October 14, 2011. Posted by Becca Pulliam.Add new comment | Filed under: Jazz Alive, JazzSet, njpac, Randy Weston
Listen to JazzSet Sunday, October 16, at 6 p.m. for NEA Jazz Master Randy Weston and African Rhythms, in concert from last winter at the New Jersey Performing Arts Center. And if you miss Sunday's broadcast, there's a rebroadcast on Wednesday at 6:30 p.m.
As always, you can visit our show page and hear this week's show any time on demand.
Click here to hear a 30-second preview from host Dee Dee Bridgewater:
Weston, who turned 85 in April, is having a banner year. He was awarded a Guggenheim Fellowship. He received honors from the King of Morocco at FIAF (photo above) in New York, and more honors this past weekend from The Jazz Ministry of Saint Peter's Church at All Night Soul . Weston made appearances in support of his memoir, African Rhythms, published by Duke University Press in late 2010.
And tonight at Bethany Baptist Church in Newark, Weston will be honored yet again, sign copies of his book, and perform. It's part of a special Jazz Vespers Service with Carla Cook and Houston Person from 4 to 10 p.m.
Stay tuned to JazzSet -- for future broadcast, we are recording Roy Haynes and his Fountain of Youth Band this weekend at the Kennedy Center in Washington, D.C.


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Hello and welcome to Deluxemodern Design | Brand + Styling Studio!
We design creative, stand-out brands that are anything but boring, and are known for our ultra-chic logo design, branding, marketing, and photo styling. We work with companies and individuals to bring their full brand vision to life: including interior design and styling, social media, packaging and marketing. We have been in business since 2006, and have loved (almost) every minute of it. Please take a look around our portfolio, blog, brand packages and design shop – and of course if you have a project we can help you with, we'd love to work with you!


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Posted at: 04/19/2013 10:59 AM
By: The Associated Press
WATERTOWN, Mass. (AP) - State police say officers are going door-to-door, but the Boston Marathon suspect is still on the loose.
Col. Timothy Alben of the Massachusetts State Police said Friday afternoon that officers would go street to street as the manhunt for the bombing suspect continues.
Gov. Deval Patrick urged residents to continue staying indoors.
A pair of brothers is suspected of killing a Massachusetts Institute of Technology police officer late Thursday, then stealing a car at gunpoint.
The suspects' clashes with police began hours after the FBI released photos and videos of them.
Monday's bombings killed three people and wounded more than 180 others. Twenty-six-year-old Tamerlan Tsarnaev was killed overnight.
His 19-year-old brother, Dzhokhar is on the loose. (Copyright 2013 The Associated Press. All rights reserved. This material may not be published, broadcast, rewritten or redistributed.)


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|Comfort Inns The Meadowlands hotels are listed below. Search for cheap and discount Comfort Inns hotel rooms in The Meadowlands, NJ for your family, individual or group travels. We list the best Comfort Inns The Meadowlands hotels & lodging so you can review the The Meadowlands Comfort Inns hotel list below to find the perfect place.
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Select an edition for more focused local news coverage when you visit NOLA.com.
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To Ruffenuff,
I do not believe the Hornets were off as much as the Rockets are playing some of the best basketball any team has played in the NBA this year. They are toying with teams on a nightly basis. Remember, they won 10 in a row on the road. Games have not been close. The key is McGrady and Yao along with a great supporting cast. They play the best defense in the West. It took a while for the team to gel as they added quite a few players in the offseason and they just recently decided on the rotation and recently jettisoned the players that were not fitting in. Wells and James should help the Hornets but it will take a while.


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alot of the events talked about in the destructors relate to the life of adolf hitler eg: in the book the children burn things which show that hitler burnt people alive. i need more xamples like this from the life of hitler. to show that this story is a political allegory. i need it fast plz
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First off, Irish last names are messed up. You can blame the English for this. In the seventeenth century the English invaded and colonized Ireland. In order to bend the Irish to their rule, the English made Gaelic sounding names illegal. Anglicising of Irish last names led to some confusion. The Mac, Mc and O were dropped along with other changes. The name MacAodhagain (Egan) became Keegan. The name MacMathghamhna (MacMahon) became Vaughan. Many other Irish last names were changed during this period.
In the nineteenth century these discriminatory laws began to ease up. The native people began to show their individuality by adding back the prefix Mac and O to their Irish last names. They added them to the anglicised form of their name. Thus Donnell became O'Donnell from the old Gaelic O'Domhnaill. Many, many others followed this same pattern.
The following list will give the modern Irish last names, the Gaelic equivalent, the meaning and their county of origin. This list will begin with the most common Irish last names on down.
One other thing before I start. Irish family groups are called septs not clans.
On to the Irish last names list.
1. Murphy (o Murchadha) "sea warrior" There were several septs in Tyrone, Slingo, Wexford and some in Cork.
2. Kelly (o Ceallaigh) "bright headed" This sept came into being in a least seven different places on the island. The two largest being in Galway (once called Ui Maine) and Meath. Others are from Dublin, Kildare, Roscommon, Antrim and Derry.
3. O'Sullivan (o Suilleabhain) "hawk eyed" Tipperary was the original territory of this sept. As they grew they moved into Cork and Kerry.
4. Walsh (Breathnach) "Welshman" There is no common ancestor for this family. The name was used for the hundreds of Welshmen that came with the Normans in the 12th century. The name appears mostly in Mayo. Other large numbers can be found in Galway, Cork, Wexford, Waterford and Kilkenny.
5. Smith (Mac an Ghaghain) "son of the smith" Other forms of this name include MacGowan and O'Gowan. The MacGowan sept originated in County Cavan. They can also be found in Leitrim, Donegal and Sligo.
6. O'Brian (o Briain) "high, noble" This sept is primarily from Clare and Limerick.
7. Byrne (o Broin) "raven" This sept started out in Kildare. They were driven south to Wicklow by the Anglo-Normans in the 11th century.
9. O'Connor (o Conchobhair) "hero, champion" This name was most predominate in the counties in western Ireland. Today this sept is most common in Kerry, with
10. O'Neill (o Neill) "from Niall of the Nine Hostages" This sept was divided into two main branches. The senior branch from County Tyrone is considered extinct. The junior branch is from Counties Antrim and Down.
11. O'Reilly (o Raghallaigh) I can't find a meaning for this name. The O'Reilly sept centered around County Cavan. Their influence extended into Meath and Westmeath also.
12. Doyle (o Dubhghaill) "dark foreigner" This sept is assumed to be descended from Norsemen. This explains their high concentration on the southeast coast especially in Wexford.
13. McCarthy (Mac Carthaigh) "loving person" This sept is most prevalent in County Cork. The famous Blarney Castle was built by the McCarthys. Cormac McCarthy lived in the castle at the time he was avoiding submission to Queen Elizabeth's rule. He did so by writing evasive answers to her letters demanding he submit. Thus began the legend of "kissing the Blarney Stone". Doing so would endow a person with the gift of evasive and eloquent speech.
14. Gallagher (o Gallchobhair) "lover of foreigners" They were one of the main septs of Donegal. They were marshalls in the amry of the O'Donnells.
15. O'Doherty (o Dochartaigh) "hurtful" This sept originated in County Donegal.
16. Kennedy (o Cinneide) "helmet headed" This sept started out in County Clare. Later the O'Briens and MacNamaras forced them to Tipperary where the name is still popular today.
17. Lynch (o Loinsigh) "mariner, seafarer" This sept settled in Clare, Slingo and Limerick. There was also a branch in Donegal.
18. Murray (o Muireadhaigh) "lord, master" Most of this sept is of Scot descent. They settled in the counties of the northwest in the Province of Ulster. There was one important sept from County Roscommon.
19. Quinn (o Cuinn) "wisdom, chief" County Tyrone is the place of origin of one of the septs of this name. It is still very common there today. Counties Clare, Antrim and Longford are other places this sept came from.
20. Moore (o Mordha) "noble" This sept was centered in County Leix or Laois as it is called today.
22. O'Carroll (o Cearbhaill) "valorous in battle" The two most important septs were from Tipperary and Offaly. Other
23. Connolly (o Conghaile) "fierce as a hound" There are three distinct septs of the name from the Counties of Cork, Meath and Monaghan.
24. Daly (o Dalaigh) "assembles frequently" This sept originated in County Meath.
25. O' Connell (o Conaill) "strong as a wolf" The O' Connells were strong in the Province of Munster. The sept was also found in Counties Galway and Londonderry.
Now for some of my family names.
Duff (o Dufaigh) "dark, black" This sept was found mostly in Louth, Monaghan and Armagh. The name is believed to be derived from the Name Duffin.
Leech (o Laoghogh) "physician" The sept may have originated in Donegal and Londonderry. Today this name is found mostly in Galway and Clare.
Keenan (o Cianain) "ancient, enduring" This sept came from the Counties of Fermanagh, Monaghan and Louth. My Great Grandfather came from County Down to the U. S. in 1883.
Kerrigan (o Ciaragain) "black" There are two main branches for this sept. One from County Donegal the other from County Mayo. My Great Grandmother came to America in 1896 from County Westmeath.
O'Donnell (o Domhnaill) "world mighty" The stronghold of the O'Donnell sept was in County Donegal. Two minor septs were in Counties Galway and Clare.
The above is obviously a very short list of Irish last names. Use the search box below for more names.
One last note if you are interested in your family crest. I hate to break it to you. But, there is really no such thing as a family crest for your family's Irish last name. They are awarded to people on an individual basis. They can be passed down from father to son. They are not awarded to a "family name" as a whole. A Grant of Arms can still be granted by the Chief Herald at the National Library of Ireland.
With that being said a family crest with Irish last names still makes a cool looking decoration, even if it was only awarded to a possible ancestor with your Irish last name.
Top of Irish last names page.
Back to Irish Names page.


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I have 2 gorgeous fully Pedigree
POLISH Dwarf babies for sale
Father is 100% out of show rabbits through Drew lines
$25 includes pedigree rabbit food and hay to start you out
[email removed]
Or text me 313-815- 1445
Jul 14 -
Detroit :
New Baltimore - Other pets
Beautiful Black Baby Lionheads for sale. Also Netherland Dwarfs for sale as well. Both parents are here to see. Bunnies are hand raised indoors and are very friendly and love to be cuddled. Our bunnies do not bite! Call or text today to see them. 248-345-4817
Jul 9 -
Detroit :
Livonia - Other pets
We have several beautiful Netherland Dwarf bunnies for sale. These make wonderful pets, and are also fully pedigreed so could be used for breeding, show or 4-H. They stay very small, weighing 2 - 2.5 pounds full grown. We've got bucks and does available. Prices vary according to color and type. We also have feed, bedding and other supplies for sale. Call or text for more info! :)
Jul 2 -
Dayton :
Miamisburg - Other pets
I have a couple ready and some litters on the way. Lots of colors to choose from. Show and pet quality rabbits. I am a member of the ANDRC, ARBA and OSNDRC. If interested contact me at 440-228-291one. I can send more pictures and answer any questions you may have.
Jun 28 -
Cleveland :
Madison - Other pets
Need to find a new home for my male lioness dwarf bunny. Inside family pet. He's cream/tan with grey patches through him. Very pretty. He's handles daily with kids and other animals. Only selling bc when I bought him very young at Easter I was told he was a girl and turns out he's definitely a boy. And I can't have two males in the same home. They are starting to get irritated with each other ...
Jun 17 -
Northeast Ohio :
Hubbard - Other pets
We currently have several junior rabbits that are available for deposit. We've got more litters of Holland Lops and Netherland Dwarfs on the way as well. We carry a wide variety of colors in both breeds. These rabbits are great for 4-H, breeding, or show! Call or text Mandy for more info.
Pic #1
Blueberry Hill's Marty
Black tort Holland Lop doe
(Galaxy x Danielle)
Ready to go ...
Jun 15 -
Dayton :
Miamisburg - Other pets
We'll be sending text message alerts for your subscription to


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Fates Warning
Progressive Metal legends FATES WARNING will be releasing 3 CD/DVD deluxe reissue of their critically acclaimed 1997 release 'A Pleasant Shade of Gray' October 2nd on Metal Blade Records.Read More
The Black Dahlia Murder
The Black Dahlia Murder have partnered with Revolvermag.com to exclusively debut the scathing, new track, 'Receipt,' from the band's new full-length album 'Abysmal,' which comes out on September 18th.Read More
Between the Buried and Me
Between the Buried and Me have debuted at #1 on the Hard Music Billboard Chart, as well as the iTunes Metal Chart, Vinyl Chart, Amazon Hard Rock Chart, and Amazon Metal Chart, with their latest release Coma Ecliptic.Read More
Progressive metal act Redemption have completed recording a new album and signed with Metal Blade Records! New music and more details will be released in the coming weeks.Read More
Don Jamieson
Comedian and That Metal Show co-host Don Jamieson will be hanging out with fans at the Rockstar Energy Drink Mayhem Festival on July 21st in Holmdel, NJ.Read More
Cattle Decapitation
As the official deployment of Cattle Decapitation's 'The Anthropocene Extinction' draws ever closer, today Vice Magazine's mega music portal, Noisey, premieres the official 'making of' documentary.Read More
Act of Defiance
Act of Defiance's highly anticipated debut offering simply delivers 100% in-your-face, uncompromising heavy metal. The group has partnered with Loudwire.com to exclusively debut the new track, 'Refrain and Re-Fracture'.Read More
New Releases
Upcoming Releases
Latest News
THE OCEAN's "Collective Oblivion" triple DVD now slated for December 10 release in North America
- October 31st, 2013 – THE OCEAN's highly anticipated triple-DVD...Read More
TÝR announce North American tour with Children of Bodom
- October 29th, 2013 – TÝR will be joining Children of Bodom on their...Read More
BATTLECROSS to tour with Killswitch Engage and Trivium in the UK
- October 29th, 2013 – BATTLECROSS have announced they will join...Read More
SISTER launches video clip for 'Sick'!
- October 29th, 2013 – After the release of their Metal Blade debut...Read More
ARTILLERY launches lyric video for 2nd single 'Wardrum Heartbeat' exclusively through Metal Hammer Germany!
- October 28th, 2013 – In collaboration with Metal Hammer Germany,...Read More
DEMONICAL stream "King of All" on DecibelMagazine.com
- October 28th, 2013 – Metal Blade Records will be releasing another...Read More
NOCTUM'S Final Sacrifice Available Tomorrow!
- October 28th, 2013 – "Word along the highway to hell is that...Read More
NOCTUM'S Final Sacrifice Streaming in Full at Bloody-Disgusting
- October 25th, 2013 – "Word along the highway to hell is that...Read More


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» Book now «
Number of rooms: 56
Check-in from: 13:00 - 00:00
Check-out: 00:00 - 12:00
Services / Facilities
24 hour service, Airconditioning, Balcony, Bar, Breakfast, Breakfast in the Room, Car Rental, Elevator, Exchange service, Express Check-In/Check-Out, Family Rooms, Fax machine, Free Wi-Fi Internet Access Included, Garden, Heating, Internet access, Ironing Service, Laundry, Luggage Storage, Newspapers, Non-Smoking Rooms, Parking, Room service, Safe in the reception, Ticket Service, Tour Desk, Wi-Fi/Wireless LAN
Valldoncella, 5, Barcelona, 08001
These are general hotel policies for Husa Meson Castilla. Cancellation and prepayment policies vary by room type. Please check the room conditions when selecting your room above.
Euro/Mastercard Visa American Express Diners Club
Cancellation Policy: If cancelled up to 1 day before the date of arrival, no fee will be charged.
If cancelled later or in case of no-show, the first night will be charged.
Children and Extra Bed Policy: All children are welcome.
All children under 1 year stay free of charge when using existing bedding.
All children under 2 years stay free of charge for cots.
Extra beds are not available.
Maximum capacity of babycots in a room is 2.
Deposit Policy: No deposit will be charged.
Groups: When booking more than 10 rooms, different policies and additional supplements may apply.
VAT and city/tourist taxes: VAT is included.
Service charge is included.
City/tourist tax is not applicable.
Internet: No internet access available.
Meal Plan: Buffet breakfast is not included, breakfast menu is available and costs vary.
Parking: Private parking is possible on site and costs EUR 23.20 per day.
Pets: Pets are allowed on request. No extra charges.
The hotel reserves the right to pre-authorise credit cards prior to arrival.


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Veterans home passes inspectionAugust 19,2013Staff Report
BENNINGTON — The Vermont Veterans Home has passed an inspection by agents of the Centers for Medicare and Medicaid Services and is no longer in danger of losing its certification to receive Medicare and Medicaid funding, according to the home's administrator Melissa Jackson.
A number of deficiencies had been identified at the home in recent months and it was scheduled to lose its ability to accept Medicare and Medicaid, its main source of funding, on Aug. 26.
On Aug. 8, Sen. Bernard Sanders, I-Vt., hosted a meeting in Montpelier which brought together members of the administration of Gov. Peter Shumlin, administrators, employees from the home and CMS to look at ways to prevent an interruption in the home's funding.MORE IN This Just InFarmer Olympics Full StoryBROC receives Full StoryArt donated Full Story
- Most Popular
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- RICHARD'S POOR ALMANACK: On this day in 1472, Orkney, Shetland islands put up as collateral by Norway to Scotland in lieu of dowry for MARGARET OF DENMARK on her marriage with JAMES III, king of Scotland; 1962, JOHN GLENN first American to orbit Earth.
- TOMORROW'S HEADLINES TODAY: City mayoral candidates debate campaign issues; Hartford, Conn., woman still missing; Neal Goswami reports attempts to legislate suicide; local woman loses 100 pounds through TOPS program.
- RICHARD'S POOR ALMANACK: On this day in 1878, JOHN TUNSTALL murdered near Lincoln, New Mexico, by the outlaw JESSE EVANS; in 1930, ELM FARM OLLIE first cow to fly in aircraft, first to be milked airborne; 1955, nuke test WASP; '79, snow in Sahara.
- TOMORROW'S HEADLINES TODAY: Rutland Herald News Editor Alan J. Keays and staff writer Gordon Dritschilo discuss stories planned for the February 18, 2015, edition of the newspaper: Winter budgets maxed, legal marijuana, Springfield bank job, USPS slowdown
- RICHARD'S POOR ALMANACK: On this day in 1249 AD, ANDRE of LONGJUMEAU is dispatched by LOUIS IX of France to meet the KHAGAN, ruler of the Mongol Empire; in 1804, during 1st Barbary War, STEPHEN DECATUR scuttles the pirate-held USS Philadelphia in Tripoli.


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VH1's Behind The Music kicks off a new season of storytelling this Sunday with Behind The Music: Train, and for this 15th Anniversary round we hope to do you even better by taking you Behind The Song, as well. Posted as an online exclusive ahead of each full episode, Behind The Song will dig deep into the story behind the celebrated artist's biggest hit or most monumental song. First up, we have Behind The Song: Train's "Drops of Jupiter," the song that "was the spark that got us global."
Deep into recording their sophomore album and still without a single, Train's lead singer Pat Monahan was struck by a dream about his late mother. "She was swimming through the planets and came to me with drops of Jupiter in her hair," says Monahan, who woke up with the "back in the atmosphere" line running through his head and the single that would launch Train to multi-platinum status well in the works. From his bed to the studio, the song picked up that "bounce, more of a potentially pop radio sound," Monahan says, and before they knew it, Train was picking up Grammys ("We were nominated for a Grammy. A few Grammys. Like, five.") and performing in front of the likes of Bono. "'Drops of Jupiter' was definitely a gift," Monahan says.
Be sure to tune-in when Behind The Music: Train premieres on Sunday, September 16 at 9/8c on VH1.