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Published or Revised January 02, 2014
This list represents some of the most common questions about attending the Texas Institute of Jewelry Technology.
You need only apply to Paris Junior College. Begin with our page for new and prospective students.
We offer five-semester AAS degrees in horology technology (watchmaking) and jewelry technology, both are 72 credit hours.
We also offer a two-semester certificate course in bench technician (jewelry repair) for 29 credit hours. We suggest that students attending the jewelry programs also take the gemology courses. A gemology certificate is 17 credit hours. Other certificates include a one-semester casting certificate in jewelry (16 credit hours), three-semester (41 credit hours) certificate in fine mechanical watch repair, and four-semester certificates in jewelry technology or horology technology (53 credit hours.
Our newest program, CAD/CAM jewelry design, is a one-semester certificate with 16 credit hours.
A complete semester-by-semester listing of courses can be found in our catalog (PDF).
You can enter the Jewelry Technology program three times per year: the spring semester, extended long summer, and the fall semester.
Your toolkit will be issued to you on the first class day. It includes all the books and supplies. Check the Tuition & Fees page for the latest cost information.
Room and board cost the same for out-of-state students as for in-state students. Current rates are listed on our Student Housing On Campus page.


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In Defence of Dogs: Why Dogs Need Our UnderstandingPaperback
List price $15.61
You save $4.66 29% off
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Dispatched in 3 business days
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- Publisher: Penguin Books Ltd
- Format: Paperback | 352 pages
- Dimensions: 128mm x 196mm x 22mm | 222g
- Publication date: 5 July 2012
- Publication City/Country: London
- Sales rank: 10,408
Product description
What would dogs ask for, if they knew how? In the "Sunday Times" bestseller "In Defence of Dogs" John Bradshaw, an anthropologist at Bristol University who has been at the centre of the latest research into what makes dogs tick, gives us the answers. Overturning the most common myths about dogs' emotions and behaviour, this book shows how we should really treat our pets, and stands up for dogdom: not the wolf in canine clothes, not the small furry child, not the trophy-winner, but the real dog, who wants to be part of the family and enjoy life - mankind's closest friend. This is the real science that every dog lover needs to know.
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Author information
John Bradshaw is a biologist who founded and directs the world-renowned Anthrozoology Institute, based at the University of Bristol. He has been studying the behaviour of domestic dogs and their owners for over 25 years, and is the author of many scientific articles, research papers and reviews, which have not only shed new light on the dog's abilities and needs, but have also changed the way that dogs are understood and cared for all over the world.
Review quote
A revelation - a major rethink about the way we understand our dogs ... there is no doubt about it - Professor John Bradshaw is a dog's best friend -- Kate Kellaway Observer Every dog lover, dog owner or prospective dog buyer should read this book. It will change how you feel about dogs and, likely enough, how you treat them, too -- James McConnachie Sunday Times A must-read for dog lovers everywhere Independent Essential reading for anyone who wants to understand the complicated psychology behind the growl, the rising hackles and the wagging tail -- Roy Hattersley Daily Telegraph Scholarly yet passionate ... nothing less than a manifesto for a new understanding of our canine friends ... fascinating -- Chris Cox Guardian A lovely and clear-headed book on all things dog-emotion, mind, and breed. John Bradshaw's authority and experience are matched by the thoughtfulness and humanity of his writing. Read this before you bring a dog into your life. -- Alexandra Horowitz author of 'Inside of a Dog' [A] wonderful, reassuring, and encouraging book ... distinguishes canine science from canine folklore -- Jonathan Mirsky Literary Review Truly fascinating ... rich in ideas and counter-ideas, and will reward anyone who respects animals ... enlightening ... Bradshaw's years of knowledge and his clear passion for dogs both shine through The Sunday Business Post Authoritative, wise and, in its sharp appreciation of the cost of dogs of living with us, rather moving -- Robert Hanks Independent The most fantastic book ... required reading for dog lovers everywhere Observer A well-grounded overview of the Canis family's evolutionary journey...this is what makes the book so appealing. He does more than simply lay out interesting theories; he uses science to advocate for a better life for companion dogs. The Bark A wonderfully informative, quietly passionate book that will benefit every dog whose owner reads it Economist Wonderfully humane, calmly-written and curiously moving ... [a] lovely book, illuminating for everyone who has or is thinking of having a dog -- Michael Bywater The First Post By giving the reader an overview of mankind's relationship with both dogs and wolves, [Bradshaw] also shows us ourselves -- Bella Bathurst Observer One may feel fully confident when reading [this] ... Bradshaw makes deft work of summarising important and novel insights on dog evolution Times Higher Education An alternative to conventional, dominance-based approaches to understanding dogs (Cesar Millan's methods, for example) in an informative...guide to how canine biology and psychology determine behavior... Bradshaw's book is useful to those looking to further their understanding of dog behavior and clarify common misconceptions Publisher's Weekly Both an interesting armchair read and an important primer for any dog owner Science Focus In Defence of Dogs provides an extensive insight into the minds of man's best friend - a must for all owners. John Bradshaw [is] a pioneer Big Issue

subset: commoncrawl


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Part of getting your body sexy and strong is challenging your entire body to perform dynamically. Squat Swings will get your legs and back and arms super toned. The Elevated Push-ups work your chest and will sculpt your core and shoulders. Sit-ups are easy when done alone, but when you couple them with full-range weighted presses, you will be sure to define your sexy and strong back. Lastly, Side Plank with the Rotations, force you to engage your trunk and obliques while pulling dynamically on all of your core muscles that wrap your waist-line! Enjoy!
- emily
8-10 lb. weights
1. Squat Swings – 15 reps
2. Push-Up w/Elevated Leg – 8 to 10 reps
3. Seated Sit Up – 8 to 10 reps
4. Side Plank w/rotation – 8 to 10 reps on each side
Plyometric HIIT Workout
Shock your body and get out of your "old gym" routine with this Plyometric High Intensity Interval Training (HIIT) Workout. Beginner Boot Campers do 2-3 rounds, Experienced Boot Campers do 3-4 rounds, Advanced Boot Campers do 4-5 rounds!
Happy Training!
- emily
stop watch
no weights
Exercises: Time Frame – 50 seconds work to 10 seconds rest (50:10)
- High Knees
- Mountain Climbers
- Burpees with Push-up
- Superman Push-up
Killer Core Workout
This workout is designed to push the average Boot Camper a little harder than the last Killer Core Workout Video. The side planks are now weighted, mountain climbers have a twisted added, the Russian twists can be done with added weights, and the side plank hops will definitely get your heart rate up, up, up!
Here's to your tight abs!
- emily
stop watch
1 weight (5-10lb)
Exercises: Time Frame – 60 seconds each exercise, 3 rounds total
1. Side Plank with Weight
2. Mountain Climbers with Twist
3. Russian Twist
4. Side Plank Hop
Bye-Bye Back Fat Workout
Say bye-bye to those folds under your sports bra or heart-rate monitor! Get ready to show off your sculpted shoulders and lean back in your favorite racer-back tank! They are not shown in the video, but the sprints in-between your strength exercises are designed to help you burn those extra calories away, so be sure to complete each set!
Post your results!
- emily
resistance bands (optional)
Exercises: Perform 15 – 20 reps of each exercise, 3 – 4 rounds total
- Lat Pull Down
- 30 yard sprint (15 yards down & 15 yards back)
- Supermans with Lat Pull
- 30 yard sprint (15 yards down & 15 yards back)
- Rear Deltoid Lifts
- 30 yard sprint (15 yards down & 15 yards back)
Apple Bottom Workout
Fit into your Apple Bottom skinny jeans with this ultimately challenging workout! Apply a combination of plyometric jumping, one-legged balancing, and dynamic kicking to get the perfect tight Apple Bottom you want! If your legs are super fatigued, then go for a light jog 5 or 10 minutes after the workout.
Be Healthy, Be Fit, Be You!
- emily
stop watch
no weights
Exercises: Time Frame – 45 seconds of work, 15 seconds rest (4-5 rounds)
- Side Hopping Lunges
- Single Leg Hip Raises
- Squat w/Front Kick
Beg for Mercy (level 2) – Advanced Cardio
Exercise Program*
1. Tuck Jumps 50 seconds Keep head and chest up, get your knees up to your chest!
2. Burpees w/Push-up 50 seconds Jump high and go back-to-back without stopping!
3. Inclined Push-up with Side Knee 50 seconds Make sure lower back does not arch, pull knees toward arm pits.
* rest 10 seconds between each exercise, perform 3 – 4 rounds of the exercises
Boot Camp Plyometrics
Exercise Program*:
1. Jump Lunges 45 sec. Swing arms up as you jump, land with back knee low to ground.
2. Burpees 45 sec. Jump high and go back-to-back without stopping!
3. Side Squat Touch 45 sec. Keep chest up, use your legs to get low, reach long when you jump.
* rest 15 seconds between each exercise, perform 3 – 4 rounds of the exercises


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Real Housewives of New York
Aviva Drescher Calls RHONY Co-Stars "Pent Up Cougars" Who Drink Too Much
While watching the most recent episode of The Real Housewives of New York (Season 5, Episode 13: "Pirate Booty Call"), Aviva Drescher was busy live-tweeting the episode, and calling out Ramona Singer and Sonja Morgan for their "immature, selfish," and "appalling" behavior in St. Barts.
As soon as the first argument began, with Sonja attempting to have a serious conversation with Heather Thomson about her toaster oven, Ramona began adding her opinions to the mix. Aviva tweeted, "How can @iamHeatherT. Get one word in???"
But Aviva's ire grew from there. As we saw, Carole Radziwill invited her boyfriend Russ Irwin to stay for the night at the ladies' St. Barts compound. When Ramona complained that she thought the trip was a "girls' trip," Aviva really lost her cool.
"Ramona berated @CaroleRadziwill about seeing her boyfriend ???" Aviva tweeted. "Its Carole's trip and she hadn't seen her bf in months! Terrible!"
And when Ramona and Sonja feigned surprise that Aviva would be joining them on the St. Barts trip with her husband Reid, "Samonja" (as LuAnn de Lesseps and Heather called them) tried to figure out how to make Aviva understand that it was a girls' trip. But Aviva was having none of it.
"Who would ever ask their friends husband to leave a house? Or consider it???? Awful!" she tweeted. "Believe me - Reid wasn't interested in hanging out with these pent up cougars," she added.
On her Bravo blog, Aviva continued the same sentiment, describing what she was watching as "Women abusing themselves with alcohol and god knows what else. Women behaving like mean teenagers thinking only of themselves and bullying others whenever they get the chance."
Do you agree with Aviva's harsh critique of the other ladies?
The Real Housewives of New York airs Mondays at 9 p.m. ET/PT on Bravo.
Source: BravoTV, @AvivaDrescher, @AvivaDrescher, @AvivaDrescher, @AvivaDrescher
Molly Friedman is an editor at Wetpaint Entertainment. Follow her on Twitter @MollyFriedman.
Get all the latest RHONY news! Like us on Facebook and follow us on Twitter @RHONYWetpaint.


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OSHA 29 CFR Part 1926.650-.652 Subpart P-Excavations:
OSHA's excavation standard contains many different requirements as well as several appendices that can be confusing at first glance. The following information summarizes the main requirements in order to help contractors prepare the job site for OSHA inspections.
Prior to digging, the contractor shall locate and identify all underground utilities such as sewer, telephone, fuel, electric, water lines, etc. that may be encountered during the excavation.
The contractor must designate a competent person or qualified person to assess the excavation and determine that it is safe for project personnel to enter and work.
All surface encumbrances such as signs, trees, fences, poles, sidewalks, etc. that create a hazard to employees must be removed or supported during the excavation.
All excavating must maintain a minimum of 10 ft. from overhead power lines rated 50 kV or less, with 0.4 inches of clearance added for every kV over 50.
Support systems shall be provided to ensure the stability of adjacent structures endangered by excavation operations.
If excavation is over 5 ft. deep, a protective system such as a trench shield shall be used to prevent a cave-in.
The contractor must provide a safe means of entering or exiting any excavation over 4 ft. deep.
A means of egress from a trench such as a ladder, ramp, or stairway shall be located within 25 ft. of workers.
In excavations over 4 ft. in depth, the potential for the accumulation of hazardous gases or vapors must be realized.
Shielding systems shall be installed and removed in a manner that protects employees from cave-ins, structural collapses, or from being struck by members of the support system.
Shielding systems shall be installed in a manner to restrict lateral or other hazardous movement of the shield in the event of a sudden collapse.
The bottom of the shielding system can not be positioned greater than 2 ft. above the bottom of the excavation.
Shielding systems and their components shall not be subjected to loads which they are not designed to withstand.
Shielding systems and their components shall be securely connected to prevent predictable failures.
The removed spoil shall not be stockpiled closer than 2 ft. from the excavation's edge.
Backfilling shall progress together with the removal of support systems from excavations.
Any excavation left unattended must be barricaded, fenced or otherwise protected against accidental entry by pedestrians.
Employees exposed to vehicular traffic must wear a high-visibility vest, and the excavation must be protected from traffic.
If employees must cross over an open excavation a safe means must be provided so that the employees do not have to jump across the trench.
No workers shall enter or work in excavations where standing water is visible unless adequate protection is used.
No employee shall be permitted underneath loads handled by lifting or digging equipment.
If the competent person finds evidence of a hazardous situation that may result in a cave-in, protective system failure, a hazardous atmosphere, or other hazardous conditions, exposed employees shall be removed from the hazardous area until the necessary precautions have been taken to ensure safety.
P.O. Box 96, Walpole, MA 02081
800.997.5283 617.464.4111


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This year's Grammy announcements have been made, and Fall Out Boy is pissed. At Ashlee Simpson, that is. According to a report in the New York Daily News, a source says that the band is blaming Ashlee and Pete's relationship for the lack of nominations the band received for this year's Infinity on High.
"Grammy voters are fed up with Ashlee after she was caught lip-synching. Her relationship with Pete has definitely affected public opinion of the band," a source told OK! magazine. "They think everything Ashlee touches is poison, and they really want her to stop touching Pete!" It's not the first time a Simpson sister has ruined an artist's career — has anyone seen Nick Lachey doing anything other than chugging beers and opening presents on the cover of People?


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bump, still need help from someone
Ok thanks nightstah.
I still have no idea what to change the .ini type file to though. Any ideas (I don't want to filddle around without knowing what I'm doing- might mess something up!)?
Last edited by supashaka; 02-03-2014 at 10:36 AM.
bump, still need help from someone
There is only one ini file that may need changed, that being the wiiflow.ini. Find the line that says data_on_usb=no and change to data_on_usb=yes.
As far as everything else, it should run properly by just copying it all over from sd to usb (make sure you keep the same file structure). After copying, press the 1 button while in the HBC and change from SD to USB. That's pretty much it.
Actually nighty you could use wbfs2fat and convert your drive in real time. I used it on 2 of my buddies Wii HDDs (I modded theirs around the same time as mine back in 09....wbfs only at that time) and it worked brilliantly. Shocked the hell out of me how fast it was too.
Python? Not sure what that is. All I remember is that it was an exe file with a few other config files. I downloaded it and ran it without having to install anything.
And sorry to the OP for hijacking your thread. Llaffer is probably about to infract me for it, considering that's the kind of mood he has been in as of late


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Lately I've been in a bit of a dark and emotional place, entirely self-inflicted I might add.
You see, I write dark/horror fiction. It's my favourite genre, and one I love to read. But when you get into a book like "The Handmaid's Tale" or some Edgar Allen Poe, you spend a few days in that headspace. When you are writing said genre and descend headlong into constructing a dark, oddly terrifying world that you have to live in for a while (at least in your head), OMFG, it really affects your mood. Just ask husbando.
So to celebrate the many dark spaces in my brain at the moment, I bring you 6 things that cheered me up this week (somehow 6 seems like an appropriate number).
1. Watching the live stream of Bastille at Coachella. OK, Dan Smith takes self-deprecation and lack of self-confidence to a whole new level, but he's a masterful storyteller with a beautiful voice. OK. Crushing a little bit. I cranked their live gig up on Saturday on our big in-lounge screen. Oddly, some of his music is very haunting & melancholy, but hell, watching them live made me wickedly happy.
2. My 8 year old daughter Scout drew me this little somethin' somethin' while I was having a writer's blocky type meltdown thingie wotsit. This child is a keeper.
3. Having a girlie's drink with one of my bestest buddies. A belly laugh can be all you need to sweep one out of a funk. I laughed 'til I cried, we talked silly girly crushes and got our cathartic on. HELLS yes. Girlfriends rock.
4. Melbourne International Comedy Festival. I took a girlfriend to see Three Stuffed Mums at the festival, which was really quite hilarious. I must be in a pretty black place though, because, whilst it was funny, it also made me a bit depressed. I love being a mum, but I also want to 1) retain my pelvic floor 2) do more than just be a mum and 3) not have to ever smell teenage boys.
5. Game of Thrones "Honest" Trailer. OK, it's puerile, amateur and is probably only going to appeal to the diehard geeks out there (and those who have already seen S3), but I really did wet myself. So much for that pelvic floor.
You're welcome.


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Takes you through the process of making a Drupal website that automatically tailors and sizes content for a wide range of displays, from desktops to mobile devices.
Create and edit custom themes in Drupal 7 and migrate existing themes built in Drupal 6.
"My colleagues and I decided to start our own graphic design business, but had no knowledge of how to build a credible website. Having learned After Effects through lynda.com in prior years, I logged on to learn HTML, CSS, and Dreamweaver. Finally we have a site that looks as good as the company we're trying to be." —John T.
more from our members »


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Health Matters
In current times, many may think I'm referring to a Facebook status, but I'm not. The Centers for Disease Control and Prevention recommend all people know their HIV status. Living with HIV infection has changed dramatically since the 1980s when the virus was making headlines. HIV testing should be considered part of an individual's routine blood work during his or her yearly physical.
At the end of 2009, about 1.1 million people were living in the United States with the HIV infection. About 18 percent of those people did not know they were infected with HIV. When considering race and ethnicity, African Americans are most affected by HIV. In 2010, African Americans made up approximately 12 percent of the U.S. population, but accounted for 44 percent of all new HIV infections. The Hispanic/Latino population is also strongly affected. In 2010, Hispanic/Latinos made up approximately 17 percent of the U.S. population, but accounted for 21 percent of all new HIV infections. When we look at HIV by transmission type, men who have sex with men (MSM) are most at risk. MSM accounted for 63 percent of all new HIV infections, even though they made up 2 percent of the population. Heterosexual contact accounted for 25 percent of all new infections, while persons who used IV drugs accounted for 8 percent and MSM and also used IV drugs accounted for 3 percent of new infections.
When a person is aware of their HIV status, some important things can happen. When a person is newly diagnosed, it allows the person the opportunity to seek care. We are fortunate to live in an area with great resources for the treatment of HIV. Individuals who are receiving treatment with HIV medications, often called ART (antiretroviral therapy), live long healthy lives. Advances in HIV treatments from pharmaceutical companies have led to the development of many drugs that do not have the harsh side effects that many HIV medications did in the mid 1990s. Often individuals who are receiving HIV care routinely and are taking their medications as directed will be less likely to transmit the virus to someone else. Another important thing that happens when a person knows their HIV status is they can take the necessary precautions to prevent the spread of the virus to others.
HIV is not an infection we can count on specific people to treat. It takes all of us. It takes doctors, pharmaceutical companies, insurance companies, case managers, community programs, the media, every individual and many more.
We encourage all people to talk to their medical care provider about HIV testing and we encourage all people to know their status. Anyone who would like to be tested for HIV can be tested at the Lee County Health Department for free and confidentially. For questions regarding HIV or to make an appointment for testing, individuals can call (919) 718-4640. All statistics were taken from the Centers for Disease Control and Prevention.


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Parents have different personalities and may have been raised "differently." Belinda palacios is here today to talk about ways to come together as a parental unit.
Belinda Palacios's Parenting Advice
Belinda Palacios's Parenting Advice
Belinda Palacios of Cal Farley's Boys Ranch talks about signs to look for and how to take action.
Synthetic drugs may be legal, but they're still dangerous.
Belinda Palacios of Cal Farley's Boys Ranch shares ways to help build positive relationships between family members.
With high school kids, graduation season and summer make for reasons to party, and all too frequently, parties mean alcohol availability.
Stay Connected - Call or Text Regularly - Don't Change Bedroom Immediately - Keep Kids Informed - Continue to Parent - Ask Questions
Belinda Palacios of Cal Farley's Boys Ranch shares information on getting through the transition.
Every child and teen is unique-- there's no formula to fixing problems.
This Week's Challenge: Talk to your kids about age appropriate responsibility and allow them to experience consequences when they fall short.
How Parents Can Teach Respect to Kids from the Start
Tips on Earning Trust and Forgiving
This Week's Challenge: If outburst occurs and after everyone has calmed down do not avoid the conversations; talk to your teen about what is going on.
For More Information Visit www.CalFarley.org
For more information, visit www.calfarly.org


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|The Twilite Dual Ball Vibrator is a strong vibrator that was designed for intense g-spot and clitoral stimulation. The Twilite Vibrator has three powerful speeds, and vibrates at an intense hum. Strong vibrations and uniquely placed balls make this vibrator perfect for simultaneous clitoral and g-spot sensations.
The Twilite Vibrator features two vibrating motors, one in each ball. This 9 inch vibrator has a slight curve, making it perfect for internal stimulation of your g-spot. When inserted, one of the vibrating balls will target your g-spot, while the other will massage your clitoris. The Twilite Vibrator can also be used as a personal massager. The strong vibrations relieve muscle tension and relax muscles.
This powerful three-speed vibrator features easy-to-use push-button controls and lots of reach. It takes 4 AA batteries and is made from hard plastic. You can use this vibrator with any type of lube.


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Annual Meeting
CCHA Grants
ACHA Awards
Meeting Minutes
CCHA Listserv
CCHA Request for Letter of Recognition
The Central College Health Association (CCHA) is a regional affiliate
of the American College Health Association (ACHA), which is a national
nonprofit organization serving and representing the interests of professionals
and students in health and higher education. CCHA's mission is to be the
principal advocate and leadership organization for college and university health
in Missouri, Kansas, and Nebraska. CCHA provides advocacy, education, and
services for its members to enhance their ability to improve the health of all
students and the campus community.
Latest News
Save the date for CCHA's 2015 Annual Meeting! March 23-25, 2015, University of Nebraska Kearney in Kearney, Nebraska.


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Wind: 0 mph
This past weekend, November 2 and 3, Mad River Valley girls' U-14 soccer played a very respectable four-game tournament at the Barrington Invitational Soccer Tournament in Barrington, Rhode Island.
Eighteen seventh- and eighth-grade girls from The Valley, along with four coaches and a supporting contingency of grandparents, parents, siblings, cousins and dogs, traveled the four-plus hours to join the annual tournament. The tournament, in its 33rd year, hosts boys' and girls' soccer teams for players in U9-U14 leagues from throughout New England.
John Stokes and Rob Rosen serve as head coaches of the U-14 girls' team, along with assistant coaches Andy McMahon and Liz Harris. The team is organized for a spring 2014 season, but coaches ran several fall practices leading up to this one fall tournament to get an early start on their spring season.
Saturday, November 2, on a mild fall day, the team won their first game 2-1 against Portsmouth, Rhode Island, with their first by forward Anna Duffy. Their second Saturday game ended in a 0-0 tie against East Lyme, Connecticut.
Sunday ushered in much colder temperatures and a first game against Barrington, Rhode Island. The teams were well-matched and the game remained scoreless in the first half, but Mad River Valley could not stop the Barrington team from scoring two consecutive goals in the last 10 minutes of the second half.
The team's second game on Sunday against Warren, Rhode Island, played out much like the day's earlier game. Though Mad River dominated much of the game and held a score of 0-0 into the half, Warren ably placed a single goal in the second half to win the game.
The Mad River Valley team played a solid tournament, particularly given that most of the opposing teams are year-round teams. With such ability this early in their season, expectations will be running high for the Mad River Valley team this coming spring.
Players at the tournament include Natasha Burbank, Shannon Cook, Kaia Cormier, Abbey Dooley, Anna Duffy, Meagan Filkowski, Anna Fortier, Eve Golden, Lauryn Green, Keara Hallam, Mary Harris, Posy LaBombard, Emma McGeorge, Kate McMann, Ciara Mead, Eleanor Reilly, Sophie Rosen and Kelly Tynan. Kyle Marie Hekeler and Lilianna Ziedins are also team members but were absent from the tournament.


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A switch. The switch includes a port card. The switch includes a network connected to the port cards. The network having transmitters and receivers that communicate with each other and have assignments between each other. The switch includes a fabric connected to the port card through the network to send and receive fragments of packets to or from the port card. The port card, fabric and network have a plurality of modes of operation. The switch includes a control mechanism connected to the transmitters and receivers which changes the assignments according to the mode. The control mechanism changes the mode and reuses the transmitters and receivers where they can be reused. A method for switching fragments of packets. The method includes the steps of assigning assignments between transmitters and receivers of a network. Then there is the step of transferring the fragments of packets between fabrics and port cards with the transmitters and receivers of the network. Next there is the step of changing a mode of the fabrics, port cards and networks. Then there is the step of changing the assignments of the transmitters and receivers according to the mode and reusing the transmitters and receivers where they can be reused.
1. A switch comprising:
a port card;
a gigabit network connected to the port card, the network having gigabit transmitters and gigabit receivers that communicate with each other and have assignments between each other, the network includes a mux structure that makes the assignments between transmitters and receivers;
a fabric connected to the port card through the network to send and receive stripes of fragments of packets to or from the port card, the port card, fabric and network having a plurality of modes of operation, the modes are 40 G, 80 G, 120 G, 240 G slow, 240 G fast or 480 G; and
a control mechanism connected to the transmitters and receivers which changes the assignments according to the mode, the control mechanism changing the mode and reusing the transmitters and receivers.
2. A switch as described in
3. A switch as described in
4. A switch as described in
5. A switch as described in
6. A switch as described in
7. A switch as described in
8. A switch as described in
9. A method for switching fragments of packets comprising the steps of:
creating assignments between transmitters and receivers of a network;
changing a mode of fabrics, port cards and the network no more than one step up or down in the mode sequence at a time where a node has to do with speed at which fragments are switched and each node has a speed, wherein the changing the mode step includes the step of changing the mode between 40 G and 80 G, or 80 G and 120 G, or 120 G and 160 G or 160 G and 240 G slow or 240 G slow 240 G fast;
changing the assignments of the transmitters and receivers according to the mode and reusing the transmitters and receivers; and
transferring the fragments of packets between fabrics and port cards with the transmitters and receivers of the network.
10. A method as described in
11. A method as described in
12. A switch comprising:
a port card;
a network connected to the port card, the network having transmitters and receivers that communicate with each other and have assignments between each other;
a plurality of fabrics, each of which is connected to the port card through the network to send and receive stripes of fragments of a packet to or from the port card, the port card, fabrics and network having a plurality of modes of operation where a node has to do with speed at which fragments are switched and each node has a speed, wherein the plurality of fabrics, each of which is connected to the port card through the network to send and receive stripes of fragments of a packet to or from the port card, the port card, fabrics and network having a plurality of modes of operation so data from the packets is distributed evenly across all fabrics so the switch adds bandwidth by adding fabrics and each fabric need not increase its bandwidth capacity as the switch increases bandwidth capacity; and
a control mechanism connected to the transmitters and receivers which changes the assignments according to the mode, the control mechanism changing the mode and reusing the transmitters and receivers.
13. A switch as described in
14. A switch as described in
15. A switch as described in
16. A switch as described in
17. A switch as described in
18. A switch as described in
19. A switch as described in
20. A switch as described in
21. A switch as described in
22. A switch as described in
The present invention is related to transferring fragments between port cards and fabrics. More specifically, the present invention is related to transferring fragments between port cards and fabrics with gigabit transceivers.
The switch originally was designed to have high-speed HSTL point-to-point connections between port cards and fabrics running at 250 MHz. This was proven to be too fast and signal integrity could not be guaranteed due to the long trace length that exist. A more robust method had to be devised. The new method uses a network of gigabit transceivers between port cards and fabrics. The gigabit network is comprised of gigabit transmitters and receivers that communicate with each other at up to 1.3 GHz. The interfaces to each transceiver are an 8-bit data bus running at 125 MHz. Since the frequency of operation was reduced by half, the bus widths had to be multiplied by two. This new method provides to be more robust and has better noise rejection since the gigabit transceivers use differential pairs to communicate with each other. Since these gigabit transceivers are replacing point-to-point buses and some buses are larger than 8 bits wide, multiple gigabit transceivers need to be used to make up these buses. The initial total number of gigabit transceivers required was as follows: 22 transmitters per Striper, 40 receivers per Aggregator, 52 transmitters per Separator and 28 receivers per Unstriper. For a 480 G switch, this would total to about (48 port cards)(4Stripers)(22)+(13 fabrics)(9 Aggregators)(40)+(13 fabrics)(9 Separators)(52)+(48 port cards)(4 Unstripers)(28)=4224+4680+6084+376=20364. This large number of gigabit transceivers proved to consume too much power and take up too much boards space. At an average of 0.29 Watts of power dissipation per transceiver, the total power dissipation would have been 5,905 Watts (20364)(0.029).
The present invention using the gigabit transceivers solves the following problems:
This optimization solves all the above problems by intelligently allocating gigabit transceivers to be re-used in modes where they can be re-used. This technique allows changes in the configuration of the switch (40 G, 80 G, 120 G, etc.) To alter the gigabit transmitter and receiver assignment to be un-synchronized as long as the switch configuration is changed up or down by one step in the configuration.
A switch which stripes data onto multiple fabrics and sends parity data to another fabric has been described in U.S. patent application Ser. No. 09/333,450, incorporated by reference herein. See also U.S. patent application Ser. No. 09/293,563 which describes a wide memory TDM switching system, incorporated by reference herein.
The present invention pertains to a switch. The switch comprises a plurality of port cards. The switch comprises a network connected to the port cards. Preferably, the network is a gigabit network. The gigabit network has transmitters and receivers that communicate with each other and have assignments between each other. Preferably, the transmitters and receivers are gigabit transmitters and gigabit receivers. The switch comprises a plurality of fabrics. Each fabric is connected to each port card through the gigabit network to send and receive fragments of packets to or from the port cards, the port cards, fabrics and network having a plurality of modes of operation. The switch comprises a control mechanism connected to the gigabit transmitters and gigabit receivers which changes the assignments according to the mode. The control mechanism changes the mode and reuses the gigabit transmitters and gigabit receivers where they can be reused.
The present invention pertains to a method for switching fragments of packets. The method comprises the steps of assigning assignments between transmitters and receivers of a network. Preferably, the network is a gigabit network. Preferably, the transmitters and receivers are gigabit transmitters and gigabit receivers. Next there is the step of changing a mode of the fabrics, port cards and networks. Then there is the step of changing the assignments of the transmitters and receivers according to the mode and reusing the gigabit transmitters and gigabit receivers where they can be reused. Then there is the step of transferring the fragments of packets between fabrics and port cards with the gigabit transmitters and gigabit receivers of the gigabit network.
In the accompanying drawings, the preferred embodiment of the invention and preferred methods of practicing the invention are illustrated in which:
Referring now to the drawings wherein like reference numerals refer to similar or identical parts throughout the several views, and more specifically to
Preferably, the network 14 includes a mux structure 24 that makes the assignments between transmitters 16 and receivers 18. The modes preferably are 40 G, 80 G, 120 G, 240 G slow, 240 G fast or 480 G. Preferably, the network 14 can support two modes simultaneously as combined modes. The combined modes preferably are 40 G/80 G, 80 G/120 G, 120 G/160 G, 160 G/240 G fast, 240 G fast/240 G slow, or 240 G slow/480 G.
Preferably, each port card 12 includes a striper 26 and an unstriper 28. Each fabric 20 preferably includes a separator 30 and an aggregator 32. Preferably, the assignments between transmitters 16 and receivers 18 communicate with each other at up to 1.3 GHz. Each transmitter 16 preferably takes in 8 bits of data and 2 bits of control and serially transmits the bits of data and control to the associated receiver. Preferably, each receiver recovers clock and data it receives by using an 8B/10B decoding protocol and provides 8 bits of data and 3 bits of control.
The present invention pertains to a method for switching fragments of packets. The method comprises the steps of assigning assignments between transmitters 16 and receivers 18 of a network 14. Preferably, the network is a gigabit network. Preferably, the transmitters and receivers are gigabit transmitters and gigabit receivers. Next there is the step of changing a mode of the fabrics 20, port cards 12 and networks 14. Then there is the step of changing the assignments of the transmitters 16 and receivers 18 according to the mode and reusing the gigabit transmitters 16 and gigabit receivers 18 where they can be reused. Then there is the step of transferring the fragments of packets between fabrics 20 and port cards 12 with the gigabit transmitters 16 and gigabit receivers 18 of the gigabit network 14.
Preferably, the changing of the assignments step includes the step of rearranging the mux structure 24 of the network 14 that makes the assignments between the receivers 18 and transmitters 16. The changing the mode step preferably includes the step of changing the mode between 40 G and 80 G, or 80 G and 120 G, or 120 G and 160 G or 160 G and 240 G slow or 240 G slow and 240 G fast. Preferably, the assigning step includes the step of assigning assignments between the receivers 18 and transmitters 16 to support two modes simultaneously as combined modes. The transferring step preferably includes the step of transferring with the transmitter 8 bits of data and 2 bits of control serially through a mux structure 24 to the receiver assigned to the transmitter.
In the operation of the invention, the switch uses a network 14 of gigabit transceivers that make the connections from port cards 12 to fabrics 20 across the backplane. The gigabit network 14 is comprised of gigabit transmitters 16 and receivers 18 that communicate with each other at up to 1.3 GHz by using differential pairs. Each gigabit transmitter 16 takes in 8 bits of data and 2 bits of control and serially transmits this data to a gigabit receiver that recovers clock and data and by using an 8B/10B decoding protocol, provides 8 bits of data and 3 bits of gigabit receiver that recovers clock and data and by using an 8B/10B decoding protocol, provides 8 bits of data and 3 bits of control. Between the transmitters 16 and receivers 18 exists a mux structure 24 that makes the assignment of transmitters 16 to receivers 18. The mux structure 24 can be configured by software control to re-assign transceivers based on the mode of the switch 10. The mux structure 24 utilizes built-in 2-to-1 muxes in each transceiver. The mux structure 24 could not be built entirely with 2-to-1 muxes since in some cases 3-to-1 muxes were required. Therefore, some additional external 2-to-1 muxes are required. The seven possible configurations are as follows 40 G, 80 G, 120 G, 160 G, 240 G slow, 240 G fast, 480 G. Since updates to the gigabit network 14 cannot be synchronized across the whole switch 10, it was decided to combine the switch 10 configurations in pairs so that at any particular time, the gigabit network 14 would support two configurations simultaneously. This can be done because pairs of configuration modes have transceivers that are common to both and can be shared. However, the switch 10 configuration is restricted to move up or down in capacity by one mode at a time. The combined modes that are supported as follows: 40 G/80 G, 80 G/120 G, 120 G/160 G, 160 G/240 G fast, 240 G fast/240 G slow, 240 G slow/480 G. 240 G fast and slow modes are described later.
The minimum requirement on the number of gigabit transceivers can be obtained by looking at the minimum number of independent channels that need to be supported by each ASIC. For the Striper 26 and Unstriper 28, 13 independent sources and destinations exist respectively, that need their own clock source in 480 G mode. The Striper 26 needs to source 2 routeward bits, 2 data bits and a back-pressure bit for a total of 5 bits per transmitter used. The Separator 30 needs to source 4 routeword bits and 4 data bits for a combined total of 8 bits per transmitter. Each transceiver can handle 8 bits of data so one transceiver per channel in 480 G mode is sufficient. This limits the reduction of gigabit transceivers to at least 13 per striper and unstriper since each gigabit transceiver provides only one clock source. A similar requirement holds true for the Aggregator 32 and Separator 30. The Aggregator 32 and Separator 30 require 24 independent channels in 480 G mode and therefore require a minimum of 24 gigabit transceivers each. After some analysis, it was shown that the original speedup of 2 on the egress of the switch was compromised in some modes. The speedup for 240 G mode was reduced to 1 and was not acceptable. To have a speedup of 2 in 240 G mode, one additional transceiver was required for the Unstriper 28. To make things symmetrical, an additional transmitter 16 was added to the Striper 26. 240 G mode was split into two modes. 240 G fast mode has a speedup of 2 and 240 G slow mode has a speedup of 1. 240 G slow mode needs to also be used since no common mapping of transceivers could be found from 240 G fast mode to 480 G mode. This is true since both modes use all 14 transceivers but have completely different mappings. This can be seen in the Appendix "BFS Backplane Optimization Worksheet". This shows how the gigabit transceiver assignments were derived. The original map was done for the Unstriper 28 and from this, it can be seen that in 240 G fast mode, all 14 transceivers were required. All other modes were assigned based on the 240 G fast mode and unused transceivers were re-used in modes that required them. The Striper 26 map is a subset of the Unstriper 28 map and both Aggregator 32 maps and the Separator 30 5-8 map are derived from the Separator 30 1-4 map. In the Appendix, the "BFS ASIC Backplane Connection Map" shows the final gigabit transceiver assignments. This is a summary of the mappings derived earlier. The document in the Appendix "Gigabit Signals", shows how the number of data bits per bus for each mode affect the number of gigabit transceivers used.
After this optimization, the total gigabit transceiver requirement is as follows: 14 transmitters per Striper, 24 receivers 18 per Aggregator, 24 transmitters per Separator and 14 receivers per Unstriper 28. For a 480 G switch, this would total to about (48 port cards)(4 Stripers)(14)+(13 fabrics)(9 Aggregators)(24)+(13 fabrics)(9 Separators)(24)+(48 port cards)(4 Unstripers)(14)=2688+2808+2808+2688=10992. This is a 46% reduction in the number of transceivers required. At an average of 0.29 Watts of power dissipation per transceiver, the total power dissipation will be 3,187 Watts (10992)(0.29).
The switch uses RAID techniques to increase overall switch bandwidth while minimizing individual fabric bandwidth. In the switch architecture, all data is distributed evenly across all fabrics so the switch adds bandwidth by adding fabrics and the fabric need not increase its bandwidth capacity as the switch increases bandwidth capacity.
Each fabric provides 40 G of switching bandwidth and the system supports 1, 2, 3, 4, 6, or 12 fabrics, exclusive of the redundant/spare fabric. In other words, the switch can be a 40 G, 80 G, 120 G, 160 G, 240 G, or 480 G switch depending on how many fabrics are installed.
A portcard provides 10 G of port bandwidth. For every 4 portcards, there needs to be 1 fabric. The switch architecture does not support arbitrary installations of portcards and fabrics.
The fabric ASICs support both cells and packets. As a whole, the switch takes a "receiver make right" approach where the egress path on ATM blades must segment frames to cells and the egress path on frame blades must perform reassembly of cells into packets.
There are currently eight switch ASICs that are used in the switch:
There are 3 different views one can take of the connections between the fabric: physical, logical, and "active." Physically, the connections between the portcards and the fabrics are all gigabit speed differential pair serial links. This is strictly an implementation issue to reduce the number of signals going over the backplane. The "active" perspective looks at a single switch configuration, or it may be thought of as a snapshot of how data is being processed at a given moment. The interface between the fabric ASIC on the portcards and the fabrics is effectively 12 bits wide. Those 12 bits are evenly distributed ("striped") across 1, 2, 3, 4, 6, or 12 fabrics based on how the fabric ASICs are configured. The "active" perspective refers to the number of bits being processed by each fabric in the current configuration which is exactly 12 divided by the number of fabrics.
The logical perspective can be viewed as the union or max function of all the possible active configurations. Fabric slot #1 can, depending on configuration, be processing 12, 6, 4, 3, 2, or 1 bits of the data from a single Striper and is therefore drawn with a 12 bit bus. In contrast, fabric slot #3 can only be used to process 4, 3, 2, or 1 bits from a single Striper and is therefore drawn with a 4 bit bus.
Unlike previous switches, the switch really doesn't have a concept of a software controllable fabric redundancy mode. The fabric ASICs implement N+1 redundancy without any intervention as long as the spare fabric is installed.
As far as what does it provide; N+1 redundancy means that the hardware will automatically detect and correct a single failure without the loss of any data.
The way the redundancy works is fairly simple, but to make it even simpler to understand a specific case of a 120 G switch is used which has 3 fabrics (A, B, and C) plus a spare (S). The Striper takes the 12 bit bus and first generates a checkword which gets appended to the data unit (cell or frame). The data unit and checkword are then split into a 4-bit-per-clock-cycle data stripe for each of the A, B, and C fabrics (A3A2A1A0, B3B2B1B0, and C3C2C1C0). These stripes are then used to produce the stripe for the spare fabric S3S2S1S0 where Sn=An XOR Bn XOR Cn and these 4 stripes are sent to their corresponding fabrics. On the other side of the fabrics, the Unstriper receives 4 4-bit stripes from A, B, C, and S. All possible combinations of 3 fabrics (ABC, ABS, ASC, and SBC) are then used to reconstruct a "tentative" 12-bit data stream. A checkword is then calculated for each of the 4 tentative streams and the calculated checkword compared to the checkword at the end of the data unit. If no error occurred in transit, then all 4 streams will have checkword matches and the ABC stream will be forwarded to the Unstriper output. If a (single) error occurred, only one checkword match will exist and the stream with the match will be forwarded off chip and the Unstriper will identify the faulty fabric stripe.
For different switch configurations, i.e. 1, 2, 4, 6, or 12 fabrics, the algorithm is the same but the stripe width changes.
If 2 fabrics fail, all data running through the switch will almost certainly be corrupted.
The fabric slots are numbered and must be populated in ascending order. Also, the spare fabric is a specific slot so populating fabric slots 1, 2, 3, and 4 is different than populating fabric slots 1, 2, 3, and the spare. The former is a 160 G switch without redundancy and the latter is 120 G with redundancy.
Firstly, the ASICs are constructed and the backplane connected such that the use of a certain portcard slots requires there to be at least a certain minimum number of fabrics installed, not including the spare. This relationship is shown in Table 0.
In addition, the APS redundancy within the switch is limited to specifically paired portcards. Portcards 1 and 2 are paired, 3 and 4 are paired, and so on through portcards 47 and 48. This means that if APS redundancy is required, the paired slots must be populated together.
To give a simple example, take a configuration with 2 portcards and only 1 fabric. If the user does not want to use APS redundancy, then the 2 portcards can be installed in any two of portcard slots 1 through 4. If APS redundancy is desired, then the two portcards must be installed either in slots 1 and 2 or slots 3 and 4.
To add capacity, add the new fabric(s), wait for the switch to recognize the change and reconfigure the system to stripe across the new number of fabrics. Install the new portcards.
Note that it is not technically necessary to have the full 4 portcards per fabric. The switch will work properly with 3 fabrics installed and a single portcard in slot 12. This isn't cost efficient but it will work.
To remove capacity, reverse the adding capacity procedure.
If the switch is oversubscribed, i.e. install 8 portcards and only one fabric.
It should only come about as the result of improperly upgrading the switch or a system failure of some sort. The reality is that one of two things will occur, depending on how this situation arises. If the switch is configured as a 40 G switch and the portcards are added before the fabric, then the 5th through 8th portcards will be dead. If the switch is configured as 80 G non-redundant switch and the second fabric fails or is removed then all data through the switch will be corrupted (assuming the spare fabric is not installed). And just to be complete, if 8 portcards were installed in an 80 G redundant switch and the second fabric failed or was removed, then the switch would continue to operate normally with the spare covering for the failed/removed fabric.
The chipset supports ATM and POS port cards in both OC48 and OC192c configurations. OC48 port cards interface to the switching fabrics with four separate OC48 flows. OC192 port cards logically combine the 4 channels into a 10 G stream. The ingress side of a port card does not perform traffic conversions for traffic changing between ATM cells and packets. Whichever form of traffic is received is sent to the switch fabrics. The switch fabrics will mix packets and cells and then dequeue a mix of packets and cells to the egress side of a port card.
The egress side of the port is responsible for converting the traffic to the appropriate format for the output port. This convention is referred to in the context of the switch as "receiver makes right". A cell blade is responsible for segmentation of packets and a cell blade is responsible for reassembly of cells into packets. To support fabric speed-up, the egress side of the port card supports a link bandwidth equal to twice the inbound side of the port card.
The block diagram for a Poseidon-based ATM port card is shown as in
At the inbound side, OC-48c or 4 OC-12c interfaces are aggregated. Each vortex sends a 2.5 G cell stream into a dedicated striper ASIC (using the BIB bus, as described below). The striper converts the supplied routeword into two pieces. A portion of the routeword is passed to the fabric to determine the output port(s) for the cell. The entire routeword is also passed on the data portion of the bus as a routeword for use by the outbound memory controller. The first routeword is termed the "fabric routeword". The routeword for the outbound memory controller is the "egress routeword".
At the outbound side, the unstriper ASIC in each channel takes traffic from each of the port cards, error checks and correct the data and then sends correct packets out on its output bus. The unstriper uses the data from the spare fabric and the checksum inserted by the striper to detect and correct data corruption.
The OC192 port card supports a single 10 G stream to the fabric and between a 10 G and 20 G egress stream. This board also uses 4 stripers and 4 unstriper, but the 4 chips operate in parallel on a wider data bus. The data sent to each fabric is identical for both OC48 and OC192 ports so data can flow between the port types without needing special conversion functions.
Each 40 G switch fabric enqueues up to 40 Gbps cells/frames and dequeue them at 80 Gbps. This 2� speed-up reduces the amount of traffic buffered at the fabric and lets the outbound ASIC digest bursts of traffic well above line rate. A switch fabric consists of three kinds of ASICs: aggregators, memory controllers, and separators. Nine aggregator ASICs receive 40 Gbps of traffic from up to 48 network blades and the control port. The aggregator ASICs combine the fabric route word and payload into a single data stream and TDM between its sources and places the resulting data on a wide output bus. An additional control bus (destid) is used to control how the memory controllers enqueue the data. The data stream from each aggregator ASIC then bit sliced into 12 memory controllers.
The memory controller receives up to 16 cells/frames every clock cycle. Each of 12 ASICs stores 1/12 of the aggregated data streams. It then stores the incoming data based on control information received on the destid bus. Storage of data is simplified in the memory controller to be relatively unaware of packet boundaries (cache line concept). All 12 ASICs dequeue the stored cells simultaneously at aggregated speed of 80 Gbps.
Nine separator ASICs perform the reverse function of the aggregator ASICs. Each separator receives data from all 12 memory controllers and decodes the routewords embedded in the data streams by the aggregator to find packet boundaries. Each separator ASIC then sends the data to up to 24 different unstripers depending on the exact destination indicated by the memory controller as data was being passed to the separator.
The dequeue process is back-pressure driven. If back-pressure is applied to the unstriper, that back-pressure is communicated back to the separator. The separator and memory controllers also have a back-pressure mechanism which controls when a memory controller can dequeue traffic to an output port.
In order to support OC48 and OC192 efficiently in the chipset, the 4 OC48 ports from one port card are always routed to the same aggregator and from the same separator (the port connections for the aggregator & Sep are always symmetric.). The table below shows the port connections for the aggregator & sep on each fabric for the switch configurations. Since each aggregator is accepting traffic from 10 G of ports, the addition of 40 G of switch capacity only adds ports to 4 aggregators. This leads to a differing port connection pattern for the first four aggregators from the second 4 (and also the corresponding separators).
The external interfaces of the switches are the Input Bus (BIB) between the striper ASIC and the ingress blade ASIC such as Vortex and the Output Bus (BOB) between the unstriper ASIC and the egress blade ASIC such as Trident.
The unstriper ASIC sends data to the egress port via Output Bus (BOB) (also known as DOUT_UN_bl_ch bus), which is a 64 (or 256) bit data bus that can support either cell or packet. It consists of the following signals:
This bus can either operate as 4 separate 32 bit output buses (4�OC48c) or a single 128 bit wide data bus with a common set of control lines from all Unstripers. This bus supports either cells or packets based on software configuration of the unstriper chip.
The Synchronizer has two main purposes. The first purpose is to maintain logical cell/packet or datagram ordering across all fabrics. On the fabric ingress interface, datagrams arriving at more than one fabric from one port cards's channels need to be processed in the same order across all fabrics. The Synchronizer's second purpose is to have a port cards's egress channel re-assemble all segments or stripes of a datagram that belong together even though the datagram segments are being sent from more than one fabric and can arrive at the blade's egress inputs at different times. This mechanism needs to be maintained in a system that will have different net delays and varying amounts of clock drift between blades and fabrics.
The switch uses a system of a synchronized windows where start information is transmit around the system. Each transmitter and receiver can look at relative clock counts from the last resynch indication to synchronize data from multiple sources. The receiver will delay the receipt of data which is the first clock cycle of data in a synch period until a programmable delay after it receives the global synch indication. At this point, all data is considered to have been received simultaneously and fixed ordering is applied. Even though the delays for packet 0 and cell 0 caused them to be seen at the receivers in different orders due to delays through the box, the resulting ordering of both streams at receive time=1 is the same, Packet 0, Cell 0 based on the physical bus from which they were received.
Multiple cells or packets can be sent in one counter tick. All destinations will order all cells from the first interface before moving onto the second interface and so on. This cell synchronization technique is used on all cell interfaces. Differing resolutions are required on some interfaces.
The Synchronizer consists of two main blocks, mainly, the transmitter and receiver. The transmitter block will reside in the Striper and Separator ASICs and the receiver block will reside in the Aggregator and Unstriper ASICs. The receiver in the Aggregator will handle up to 24(6 port cards�4 channels) input lanes. The receiver in the Unstriper will handle up to 13(12 fabrics+1 parity fabric) input lanes.
When a sync pulse is received, the transmitter first calculates the number of clock cycles it is fast (denoted as N clocks).
The transmit synchronizer will interrupt the output stream and transmit N K characters indicating it is locking down. At the end of the lockdown sequence, the transmitter transmits a K character indicating that valid data will start on the next clock cycle. This next cycle valid indication is used by the receivers to synchronize traffic from all sources.
At the next end of transfer, the transmitter will then insert at least one idle on the interface. These idles allow the 10 bit decoders to correctly resynchronize to the 10 bit serial code window if they fall out of synch.
The receive synchronizer receives the global synch pulse and delays the synch pulse by a programmed number (which is programmed based on the maximum amount of transport delay a physical box can have). After delaying the synch pulse, the receiver will then consider the clock cycle immediately after the synch character to be eligible to be received. Data is then received every clock cycle until the next synch character is seen on the input stream. This data is not considered to be eligible for receipt until the delayed global synch pulse is seen.
Since transmitters and receivers will be on different physical boards and clocked by different oscillators, clock speed differences will exist between them. To bound the number of clock cycles between different transmitters and receivers, a global sync pulse is used at the system level to resynchronize all sequence counters. Each chip is programmed to ensure that under all valid clock skews, each transmitter and receiver will think that it is fast by at least one clock cycle. Each chip then waits for the appropriate number of clock cycles they are into their current sync_pulse_window. This ensure that all sources run N* sync_pulse_window valid clock cycles between synch pulses.
As an example, the synch pulse window could be programmed to 100 clocks, and the synch pulses sent out at a nominal rate of a synch pulse every 10,000 clocks. Based on a worst case drifts for both the synch pulse transmitter clocks and the synch pulse receiver clocks, there may actually be 9,995 to 10,005 clocks at the receiver for 10,000 clocks on the synch pulse transmitter. In this case, the synch pulse transmitter would be programmed to send out synch pulses every 10,006 clock cycles. The 10,006 clocks guarantees that all receivers must be in their next window. A receiver with a fast clock may have actually seen 10,012 clocks if the synch pulse transmitter has a slow clock. Since the synch pulse was received 12 clock cycles into the synch pulse window, the chip would delay for 12 clock cycles. Another receiver could seen 10,006 clocks and lock down for 6 clock cycles at the end of the synch pulse window. In both cases, each source ran 10,100 clock cycles.
When a port card or fabric is not present or has just been inserted and either of them is supposed to be driving the inputs of a receive synchronizer, the writing of data to the particular input FIFO will be inhibited since the input clock will not be present or unstable and the status of the data lines will be unknown. When the port card or fabric is inserted, software must come in and enable the input to the byte lane to allow data from that source to be enabled. Writes to the input FIFO will be enabled. It is assumed that, the enable signal will be asserted after the data, routeword and clock from the port card or fabric are stable.
At a system level, there will be a primary and secondary sync pulse transmitter residing on two separate fabrics. There will also be a sync pulse receiver on each fabric and blade. This can be seen in
If the sync pulse receiver determines that the primary sync pulse transmitter is out of sync, it will switch over to the secondary sync pulse transmitter source. The secondary sync pulse transmitter will also determine that the primary sync pulse transmitter is out of sync and will start generating its own sync pulse independently of the primary sync pulse transmitter. This is the secondary sync pulse transmitter's primary mode of operation. If the sync pulse receiver determines that the primary sync pulse transmitter has become in sync once again, it will switch to the primary side. The secondary sync pulse transmitter will also determine that the primary sync pulse transmitter has become in sync once again and will switch back to a secondary mode. In the secondary mode, it will sync up its own sync pulse to the primary sync pulse. The sync pulse receiver will have less tolerance in its sync pulse filtering mechanism than the secondary sync pulse transmitter. The sync pulse receiver will switch over more quickly than the secondary sync pulse transmitter. This is done to ensure that all receiver synchronizers will have switched over to using the secondary sync pulse transmitter source before the secondary sync pulse transmitter switches over to a primary mode.
In order to lockdown the backplane transmission from a fabric by the number of clock cycles indicated in the sync calculation, the entire fabric must effectively freeze for that many clock cycles to ensure that the same enqueuing and dequeueing decisions stay in sync. This requires support in each of the fabric ASICs. Lockdown stops all functionality, including special functions like queue resynch.
The sync signal from the synch pulse receiver is distributed to all ASICs. Each fabric ASIC contains a counter in the core clock domain that counts clock cycles between global sync pulses. After the sync pulse if received, each ASIC calculates the number of clock cycles it is fast. (δ). Because the global sync is not transferred with its own clock, the calculated lockdown cycle value may not be the same for all ASICs on the same fabric. This difference is accounted for by keeping all interface FIFOs at a depth where they can tolerate the maximum skew of lockdown counts.
Lockdown cycles on all chips are always inserted at the same logical point relative to the beginning of the last sequence of "useful" (non-lockdown) cycles. That is, every chip will always execute the same number of "useful" cycles between lockdown events, even though the number of lockdown cycles varies.
Lockdown may occur at different times on different chips. All fabric input FIFOs are initially set up such that lockdown can occur on either side of the FIFO first without the FIFO running dry or overflowing. On each chip-chip interface, there is a sync FIFO to account for lockdown cycles (as well as board trace lengths and clock skews). The transmitter signals lockdown while it is locked down. The receiver does not push during indicated cycles, and does not pop during its own lockdown. The FIFO depth will vary depending on which chip locks down first, but the variation is bounded by the maximum number of lockdown cycles. The number of lockdown cycles a particular chip sees during one global sync period may vary, but they will all have the same number of useful cycles. The total number of lockdown cycles each chip on a particular fabric sees will be the same, within a bounded tolerance.
The Aggregator core clock domain completely stops for the lockdown duration—all flops and memory hold their state. Input FIFOs are allowed to build up. Lockdown bus cycles are inserted in the output queues. Exactly when the core lockdown is executed is dictated by when DOUT_AG bus protocol allows lockdown cycles to be inserted. DOUT_AG lockdown cycles are indicated on the DestID bus.
The memory controller must lockdown all flops for the appropriate number of cycles. To reduce impact to the silicon area in the memory controller, a technique called propagated lockdown is used.
The on-fabric chip-to-chip synchronization is executed at every sync pulse. While some sync error detecting capability may exist in some of the ASICs, it is the Unstriper's job to detect fabric synchronization errors and to remove the offending fabric. The chip-to-chip synchronization is a cascaded function that is done before any packet flow is enabled on the fabric. The synchronization flows from the Aggregator to the Memory Controller, to the Separator, and back to the Memory Controller. After the system reset, the Aggregators wait for the first global sync signal. When received, each Aggregator transmits a local sync command (value 0x2) on the DestID bus to each Memory Controller.
The striping function assigns bits from incoming data streams to individual fabrics. Two items were optimized in deriving the striping assignment:
These were traded off against additional muxing legs for the striper and unstriper ASICs. Irregardless of the optimization, the switch must have the same data format in the memory controller for both OC48 and OC192.
Backplane efficiency requires that minimal padding be added when forming the backplane busses. Given the 12 bit backplane bus for OC48 and the 48 bit backplane bus for OC192, an optimal assignment requires that the number of unused bits for a transfer to be equal to (number_of_bytes*8)/bus_width where "/" is integer division. For OC48, the bus can have 0, 4 or 8 unutilized bits. For OC192 the bus can have 0, 8, 16, 24, 32, or 40 unutilized bits.
This means that no bit can shift between 12 bit boundaries or else OC48 padding will not be optimal for certain packet lengths.
For OC192c, maximum bandwidth utilization means that each striper must receive the same number of bits (which implies bit interleaving into the stripers). When combined with the same backplane interconnection, this implies that in OC192c, each stripe must have exactly the correct number of bits come from each striper which has � of the bits.
For the purpose of assigning data bits to fabrics, a 48 bit frame is used. Inside the striper is a FIFO which is written 32 bits wide at 80–100 MHz and read 24 bits wide at 125 MHz. Three 32 bit words will yield four 24 bit words. Each pair of 24 bit words is treated as a 48 bit frame. The assignments between bits and fabrics depends on the number of fabrics.
The following tables give the byte lanes which are read first in the aggregator and written to first in the separator. The four channels are notated A,B,C,D. The different fabrics have different read/write order of the channels to allow for all busses to be fully utilized.
One Fabric—40 G
The next table gives the interface read order for the aggregator.
Interfaces to the gigabit transceivers will utilize the transceiver bus as a split bus with two separate routeword and data busses. The routeword bus will be a fixed size (2 bits for OC48 ingress, 4 bits for OC48 egress, 8 bits for OC192 ingress and 16 bits for OC192 egress), the data bus is a variable sized bus. The transmit order will always have routeword bits at fixed locations. Every striping configuration has one transceiver that it used to talk to a destination in all valid configurations. That transceiver will be used to send both routeword busses and to start sending the data.
The backplane interface is physically implemented using interfaces to the backplane transceivers. The bus for both ingress and egress is viewed as being composed of two halves, each with routeword data. The two bus halves may have information on separate packets if the first bus half ends a packet.
For example, an OC48 interface going to the fabrics locally speaking has 24 data bits and 2 routeword bits. This bus will be utilized acting as if it has 2�(12 bit data bus+1 bit routeword bus). The two bus halves are referred to as A and B. Bus A is the first data, followed by bus B. A packet can start on either bus A or B and end on either bus A or B.
In mapping data bits and routeword bits to transceiver bits, the bus bits are interleaved. This ensures that all transceivers should have the same valid/invalid status, even if the striping amount changes. Routewords should be interpreted with bus A appearing before bus B.
The bus A/Bus B concept closely corresponds to having interfaces between chips.
All backplane busses support fragmentation of data. The protocol used marks the last transfer (via the final segment bit in the routeword). All transfers which are not final segment need to utilize the entire bus width, even if that is not an even number of bytes. Any given packet must be striped to the same number of fabrics for all transfers of that packet. If the striping amount is updated in the striper during transmission of a packet, it will only update the striping at the beginning of the next packet.
Each transmitter on the ASICs will have the following I/O for each channel:
8 bit data bus, 1 bit clock, 1 bit control.
On the receive side, for channel the ASIC receives
a receive clock, 8 bit data bus, 3 bit status bus.
The switch optimizes the transceivers by mapping a transmitter to between 1 and 3 backplane pairs and each receiver with between 1 and 3 backplane pairs. This allows only enough transmitters to support traffic needed in a configuration to be populated on the board while maintaining a complete set of backplane nets. The motivation for this optimization was to reduce the number of transceivers needed.
The optimization was done while still requiring that at any time, two different striping amounts must be supported in the gigabit transceivers. This allows traffic to be enqueued from a striping data to one fabric and a striper striping data to two fabrics at the same time.
Depending on the bus configuration, multiple channels may need to be concatenated together to form one larger bandwidth pipe (any time there is more than one transceiver in a logical connection. Although quad gbit transceivers can tie 4 channels together, this functionality is not used. Instead the receiving ASIC is responsible for synchronizing between the channels from one source. This is done in the same context as the generic synchronization algorithm.
The 8b/10b encoding/decoding in the gigabit transceivers allow a number of control events to be sent over the channel. The notation for these control events are K characters and they are numbered based on the encoded 10 bit value. Several of these K characters are used in the chipset. The K characters used and their functions are given in the table below.
The switch has a variable number of data bits supported to each backplane channel depending on the striping configuration for a packet. Within a set of transceivers, data is filled in the following order:
F[fabric]_[oc192 port number][oc48 port designation (a,b,c,d)][transceiver_number]
The chipset implements certain functions which are described here. Most of the functions mentioned here have support in multiple ASICs, so documenting them on an ASIC by ASIC basis does not give a clear understanding of the full scope of the functions required.
The switch chipset is architected to work with packets up to 64 K+6 bytes long. On the ingress side of the switch, there are busses which are shared between multiple ports. For most packets, they are transmitted without any break from the start of packet to end of packet. However, this approach can lead to large delay variations for delay sensitive traffic. To allow delay sensitive traffic and long traffic to coexist on the same switch fabric, the concept of long packets is introduced. Basically long packets allow chunks of data to be sent to the queueing location, built up at the queueing location on a source basis and then added into the queue all at once when the end of the long packet is transferred. The definition of a long packet is based on the number of bits on each fabric.
If the switch is running in an environment where Ethernet MTU is maintained throughout the network, long packets will not be seen in a switch greater than 40 G in size.
A wide cache-line shared memory technique is used to store cells/packets in the port/priority queues. The shared memory stores cells/packets continuously so that there is virtually no fragmentation and bandwidth waste in the shared memory.
There exists up to 200 multiple queues in the shared memory. They are per-destination and priority based. All cells/packets which have the same output priority and blade/channel ID are stored in the same queue. Cells are always dequeued from the head of the list and enqueued into the tail of the queue. Each cell/packet consists of a portion of the egress route word, a packet length, and variable-length packet data. Cell and packets are stored continuously, i.e., the memory controller itself does not recognize the boundaries of cells/packets for the unicast connections. The packet length is stored for MC packets.
The multicast port mask memory 64 K�16-bit is used to store the destination port mask for the multicast connections, one entry (or multiple entries) per multicast VC. The port masks of the head multicast connections indicated by the multicast DestID FIFOs are stored internally for the scheduling reference. The port mask memory is retrieved when the port mask of head connection is cleaned and a new head connection is provided.
APS stands for a Automatic Protection Switching, which is a SONET redundancy standard. To support APS feature in the switch, two output ports on two different port cards send roughly the same traffic. The memory controllers maintain one set of queues for an APS port and send duplicate data to both output ports.
To support data duplication in the memory controller ASIC, each one of multiple unicast queues has a programmable APS bit. If the APS bit is set to one, a packet is dequeued to both output ports. If the APS bit is set to zero for a port, the unicast queue operates at the normal mode. If a port is configured as an APS slave, then it will read from the queues of the APS master port. For OC48 ports, the APS port is always on the same OC48 port on the adjacent port card.
The shared memory queues in the memory controllers among the fabrics might be out of sync (i.e., same queues among different memory controller ASICs have different depths) due to clock drifts or a newly inserted fabric. It is important to bring the fabric queues to the valid and sync states from any arbitrary states. It is also desirable not to drop cells for any recovery mechanism.
A resync cell is broadcast to all fabrics (new and existing) to enter the resync state. Fabrics will attempt to drain all of the traffic received before the resynch cell before queue resynch ends, but no traffic received after the resynch cell is drained until queue resynch ends. A queue resynch ends when one of two events happens:
1. A timer expires.
2. The amount of new traffic (traffic received after the resynch cell) exceeds a threshold.
At the end of queue resynch, all memory controllers will flush any left-over old traffic (traffic received before the queue resynch cell). The freeing operation is fast enough to guarantee that all memory controllers can fill all of memory no matter when the resynch state was entered.
Queue resynch impacts all 3 fabric ASICs. The aggregators must ensure that the FIFOs drain identically after a queue resynch cell. The memory controllers implement the queueing and dropping. The separators need to handle memory controllers dropping traffic and resetting the length parsing state machines when this happens. For details on support of queue resynch in individual ASICs, refer to the chip ADSs.
For the dequeue side, multicast connections have independent 32 tokens per port, each worth up 50-bit data or a complete packet. The head connection and its port mask of a higher priority queue is read out from the connection FIFO and the port mask memory every cycle. A complete packet is isolated from the multicast cache line based on the length field of the head connection. The head packet is sent to all its destination ports. The 8 queue drainers transmit the packet to the separators when there are non-zero multicast tokens are available for the ports. Next head connection will be processed only when the current head packet is sent out to all its ports.
Queue structure can be changed on fly through the fabric resync cell where the number of priority per port field is used to indicate how many priority queues each port has.
The following words have reasonably specific meanings in the vocabulary of the switch. Many are mentioned elsewhere, but this is an attempt to bring them together in one place with definitions.
Although the invention has been described in detail in the foregoing embodiments for the purpose of illustration, it is to be understood that such detail is solely for that purpose and that variations can be made therein by those skilled in the art without departing from the spirit and scope of the invention except as it may be described by the following claims.
Patent Citations
Referenced by
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text:
Master of Science in Computer Science
The Masters program in computer science at Jackson State University is currently evolving to meet the needs of the diverse population in the surrounding urban area.
Program Educational Objectives
The objectives of the Department of Computer Science are:
• To afford students the opportunity for in-depth study of Computer science concepts and theories.
• To keep abreast of, and expose students to, state-of-the-art, as well as state-of-the-practice, computer applications and technologies.
• To engage faculty and students in meaningful computer science research, and computer science applications research and development.
• To promote professional development and growth of students and faculty.
Student Outcomes
The curriculum can be geared to:
• Provide training for those preparing to enter fields where a substantial working knowledge of computers is required.
• Provide additional training to people already working in the field, and/or
• Demonstrate professional competency in oral and written communication.
• Prepare students for study at the doctoral level.


text:
Hey: learn to use the "edit" button, as otherwise this appears a form of thread bumping and is against the rules.
Edit: try a channel install/wad from here.
how would i uninstall the forwarder and reinstall it ? i dnt understand iso 35 i just done dogeggs guide and redsteel 2 and monsterhunter fix?
Last edited by nightstah; 06-08-2010 at 05:36 PM.
yeah i sorry look for edit next time. yeah i got the channel wad already from download links in dogeggs guide. how would i go about it if do i need to uninstall the forwarder i mean im not sure how to do that bit? can install the ch wad ok but can i do it over the forward or have to uninstall that first m8?
You can uninstall the forwarder through wad manager (provided you have it somewhere from when you installed it before), it won't hurt anything as the homebrew app will still be there.
The channel wad also get's installed via the wad manager, but this will eliminate the dependency to the homebrew boot.dol. as now it will be a stand-alone guenuine channel.
yeah i done like you said m8 with the channel wad but flickers the tv even worse than the forwarder done any ideas?
Every loader i've ever installed (all channels) have done something simular,they start then go off,then start quickly in B&W then go off,then start in colour and are ok.I've never been really bothered about this and the wii is still running everything nicely,so as long as in the end the games run,(its just the loader takes an extra 3 secs to get it together),i would'nt really worry about it.
Oh yeh just to add,this also happens when i first start the wii,its like if the tv is trying to find the right video mode to set itself up in.
So i can't really say its just the loader channels that do this.
Last edited by skagg; 06-09-2010 at 08:42 AM.


text:
Raksha Bandhan
Friendship Day
Independence Day
Raksha Bandhan SMS
Holi is colorful,Diwali is lightful But Rakhi has made our relationship POWERFUL! Happy Rakshabandhan!
A Sister Smiles When One Tells One\'s Stories - For She Knows Where The Decoration Has Been Added. Happy Rakhi, dear Sis!
U are the1 who holds me in my bad times,dances with me in my happiness. I really love you, Sis! Happy Rakshabandhan!
Hey my sweet little pie, ur cute smile makes my day, ur small little hands take me out from all dangers of life. U r a little angel of my life, Happy Rakhi.
A sister is a gift to the heart, a friend to the spirit, a golden thread to the meaning of life! Wishing u a very Happy Rakhi.
We may look old and wise to the outside world. But to each other, we are still in junior school. Happy Raksha bandhan 2 u my lovely Sis!
I long for the day through the year that u so ceremoniously tie rakhi on my wrist& pray for my well being. Dear Sis, Happy rakshabandhan!
Do U know that,Fun as a triple scoops, Sweet as chocolates, Bright N cheerful as flowers, Its U, my Sis. Wishing u a very Happy Rakhi.
Warm vshes n love r sent ur way May gifts of happiness, frenship,peace n joy fil ur life. Hav a wonderful Rakhi!
Near or far wherever u r, my best wishes r with u,Tum Jiyo Hazaron Saal, May Success & Joy b yours every day! Happy Raksha Bandhan


text:
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text:
Getting Seniors Back on Their Feet
Accidents happen. Unfortunately, as we age, even minor accidents can have major consequences. Fragile bones caused by osteoporosis, combined with other medical conditions that place seniors at a higher risk of falls, make hip fractures both common and potentially life-threatening.
Each year, 1.5 million people in the United States suffer fractures because their bones have become weak. According to the U.S. Census Bureau, West Virginia has the second-oldest population of any state, resulting in an increased risk for falls and fractures,
The Senior Fracture Program at Cabell Huntington Hospital, led by medical director Frank Shuler, MD, PhD, and program coordinator Rebecca Edwards, RN, BSN, CNRN, works to ensure the best possible outcomes for hip fracture patients, using a unique approach that is equally based on leading-edge research and personal compassion. The program's coordinated care approach is the only one in the region.
"Falls and fractures in the elderly are serious, potentially life-threatening events, and our Senior Fracture Program is designed to achieve the best possible outcomes for bone fractures in elderly patients," said Dr. Shuler. "The Senior Fracture Program provides a comprehensive multidisciplinary approach that emphasizes quality management, timely operative treatment and standardization of protocols to improve our delivery of services and outcomes for hip fracture patients."
Hip fracture patients are assessed in the Emergency Department immediately, and taken to surgery within 24 hours. Research has shown that treating senior patients within 24 hours of a hip fracture results in a shorter length of stay, a faster recovery, fewer complications and an increased likelihood to return to pre-injury levels
of activity.
"When hip fracture patients come to us, it is a difficult time," Dr. Shuler said. "It's scary. I have seen in my own family the devastating consequences these injuries can have. My grandfather passed away from complications following hip fracture surgery. With this program, we want to put things in place that will provide the best possible care for our patients and their families."
Following surgery to repair the fracture, patients receive care from a multidisciplinary team of orthopedic surgeons, physicians, endocrinologists, nurses and other healthcare professionals with expertise in the care of seniors. These specialists work together to assess patients' bone health, establish a plan for pain management and rehabilitation based on each patient's individual needs, and educate patients and their families on ways to prevent future fractures.
Patients begin the rehabilitation process soon after surgery, reducing the risk of infections, blood clots and other complications.
What sets the Senior Fracture Program at Cabell Huntington Hospital apart is the dedication of its staff to patients and their families as soon as they arrive at the hospital – and even beyond the hospital walls.
As a liaison for patients and their families, Edwards not only cares for patients during their hospital stay, making daily visits to assess their progress and answer questions, but also follows up with patients and families after they return home.
"When patients are in the hospital, there's just so much for them to take in," Edwards said. "They're anxious about the surgery, and information is coming in from so many areas. The follow-up is very important. It helps us reinforce what they've learned and find out what their learning needs are outside the stress of the hospital setting."
Cabell Huntington Hospital's ongoing commitment to seniors through its Senior Services department also includes community outreach. Edwards visits local assisted-living facilities to educate seniors on bone health, osteoporosis and fall prevention.
"A lot of people aren't aware they have a bone health problem until they suffer their first fracture," she said. "As we increase community awareness and give people ways to prevent osteoporosis, we hope to ultimately prevent fractures from occurring."
To learn more about the Senior Fracture Program, call 304.399.1897.
To help keep your bones strong and slow down bone loss, you can:
• Get adequate calcium, Vitamin D and nutrients to support bone and muscle health.
• Exercise regularly to help maintain muscle strength and balance (check with your doctor first).
• Quit smoking and limit your alcohol intake.
• Talk to your doctor about evaluating your bone density and how you can improve it.
Learn more about bone health and avoiding falls on the Cabell Huntington Hospital website
(www.cabellhuntington.org) by clicking the white CHH logo in the top right corner of any page.


text:
Palladium Blanc HiSKU: #8072345
Product Information
- These Blanc hi-tops from Palladium® may not be as pure as the morning snow, but boy won't they make you look devilishly handsome!
- 100% two-tone faded cotton-canvas upper that's light on top and bold on the vamp for a unique look.
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- Five-eye lace up front with contrast metal eyelets for secure fit.
- Large woven Palladium label on the tongue and quarter.
- Secondary rubber logo patch on outer ankle.
- One-piece molded-rubber outsole with aggressive tread pattern for long-lasting durability.
- Imported.
- Measurements:
- Weight: 1 lb 5 oz
- Product measurements were taken using size 11, width M. Please note that measurements may vary by size.