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The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
1. A microprocessor system, comprising:
(A) an instruction fetch unit adapted to fetch instructions from an instruction store and to provide a predetermined plurality of said instructions to an instruction buffer; and
(B) an execution unit, coupled to said instruction fetch unit, adapted to execute said plurality of said instructions from said instruction buffer in an out-of-order fashion with respect to a predefined program order, said execution unit including a load store unit adapted to make load requests to a memory system out-of-order with respect to said predefined program order and store requests to said memory system in-order with respect to said predefined program order, said load store unit including
(1) an address path adapted to manage a plurality of addresses associated with said plurality of said instructions and to provide addresses to said memory system,
(2) a data path adapted to transfer load data from said memory system to said execution unit and to transfer store data from said execution unit to said memory system, and
(3) a load aligner, coupled to said data path, for aligning unaligned load data transferred from said memory system to said execution unit, said load aligner including a plurality of multiplexers and a select line coupled to each of said plurality of multiplexers for selecting bytes of said load data returned from said memory system, and a data buffer for storing said selected bytes of data.
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This application is a continuation of U.S. patent application Ser. No. 09/438,359, filed Nov. 12, 1999, now U.S. Pat. No. 6,434,693, which is a continuation of U.S. patent application Ser. No. 08/962,705, filed Nov. 3, 1997, now U.S. Pat. No. 5,987,593, which is a file wrapper continuation of U.S. patent application Ser. No. 08/789,620, filed Jan. 27, 1997, now abandoned, which is a continuation of U.S. patent application Ser. No. 08/307,042, filed Sep. 16, 1994, now U.S. Pat. No. 5,659,782, which is a continuation of U.S. patent application Ser. No. 07/954,084, filed Sep. 29, 1992, now abandoned.
The present application is related to the following applications, assigned to the Assignee of the present application: U.S. patent application Ser. No. 07/727,058, filed on Jul. 8, 1991, now abandoned, by Nguyen et al. and entitled "EXTENSIBLE RISC MICROPROCESSOR ARCHITECTURE", and to a continuation of the '058 application Ser. No. 07/817,809, filed on Jan. 8, 1992, now abandoned, which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates generally to the design of a superscalar microprocessor and, more particularly, to a system and method for handling load and store operations in a microprocessor that executes instructions out-of-order.
2. Discussion of Related Art
A major consideration in a superscalar Reduced Instruction Set Computer (RISC) processor is how to execute multiple instructions in parallel and out-of-order, without incurring data errors due to dependencies inherent in such execution. The simplest instruction issue policy for RISC processors, is to issue instructions in exact program order (in-order issue) and to write the results in the same order (in-order completion). Out-of-order completion is more complex than in-order completion, and improves performance of superscalar processors for the same types of operations. For instance, out-of-order completion is used to improve performance of long-latency operations such as loads or floating point operations. Any number of instructions are allowed to be in execution in the functional units, up to the total number of pipeline stages in all functional units. Instructions may complete out of order, because instruction issuing is not stalled when a functional unit takes more than one cycle to compute a result. Consequently, a functional unit may complete an instruction after subsequent instructions already have completed.
Consider the following code sequence where "op" is an operation, "Rn" represents a numbered register, and ":=" represents assignment:
Out-of-order completion yields higher performance, but requires more hardware, namely data dependency logic. Data dependency logic is more complex with out-of-order completion, because this logic checks data dependencies between decoded instructions and all instructions in all pipeline stages. Hardware must also ensure that the results are written in the correct order. In contrast, with in-order completion the dependency logic checks data dependencies between decoded instructions and the few instructions in execution, and results are naturally written in the correct order. Out-of-order completion also creates a need for functional units to arbitrate for result busses and register-file write ports, because there probably are not enough of these to satisfy all instructions that can complete simultaneously.
Moreover, out-of-order completion makes it more difficult to deal with instruction exceptions. An instruction creates an exception when under a given condition, the instruction cannot be properly executed by hardware alone.
In-order issue processors stop decoding instructions whenever a decoded instruction creates a resource conflict or has a true dependency or an output dependency on an uncompleted instruction. The processor is thus not able to look ahead beyond the instructions with the conflict or dependency, even though one or more subsequent instructions might be executable. A conventional solution is to isolate the decoder from the execution stage, so that it continues to decode instructions regardless of whether they could be executed immediately. This isolation is accomplished by providing a buffer (called an "instruction window") between the decode and instruction stages.
For look-ahead, the processor decodes instructions and places them into the instruction window as long as there is room in the window, and, at the same time, examines instructions in the window to find instructions that may be executed (i.e., instructions that do not have resource conflicts or dependencies). The instruction window provides a pool of instructions, thus giving the processor a look-ahead ability that is limited by the size of the window and the capability of the processor's Instruction Fetch Unit (IFU). This permits issuing of instructions out of order because instructions may be issued from the window with little regard for their original program order. The only constraints on the instruction issuer are those required to ensure that the program behaves correctly.
The issue constraints on any particular instruction are mostly the same as with in-order issue: an instruction is issued when it is free of resource conflicts and dependencies. Out-of-order issue gives the processor a larger set of instructions available for issue, improving its chances of finding instructions to execute concurrently. However, the capability to issue instructions out of order introduces an additional issue constraint, much as the capability to complete instructions out of order introduced the constraint of output dependencies.
To understand this, again consider the above example code sequence. The assignment of the third instruction cannot be completed until the second instruction begins execution. Otherwise, the third instruction might incorrectly overwrite the first operand of the second instruction. The result of the third instruction is said to have an "anti-dependency" on the first input operand of the second instruction. The term anti-dependency refers to the fact that the constraint is similar to that of true dependencies, except reversed. Instead of the first instruction producing a value that the second uses, the second instruction produces a value that destroys a value that the first one uses. To prevent this, the processor must not issue the third instruction until after the second one begins. Because the second instruction depends on the first, the third instruction also must wait for the first to complete, even though the third instruction is otherwise independent. Anti-dependencies are mainly of concern when instructions can issue out of order. An input operand of a stalled instruction can be destroyed by a subsequent instruction during normal operation. However, in scalar processors, instruction exceptions are sometimes handled by correcting the exceptional condition, then retrying the problematic instruction. If this instruction completed out of order, it is possible that, when it is retried, its input operands have been overwritten by subsequent instructions. This problem cannot occur in a processor that supports precise interrupts. The solution may require that the processor maintain copies of instruction operands to allow restart.
Two typical operations performed by program instructions are load and store operations. Generally, load and store operations read and modify memory locations, respectively. As with other program instructions, loads and stores can be executed out of order. Even though loads and stores can be decoded at the same time, only one load or store is conventionally issued per cycle. A load is typically given priority over a store to use the data-cache, because the load is likely to produce a value that the processor needs to proceed with computation. If a store conflicts with a load for the data-cache, the store is typically held in a store buffer until the store can be performed. Furthermore, a store is conventionally performed in program-sequential order with respect to other stores, and is performed only after all previous instructions, including loads, have completed. This preserves the processor's in-order state in the data-cache, because cache updates are not performed until it is absolutely correct to do so. The store buffer aids in keeping stores in the correct order and in deferring the completion of a store until previous instructions have completed.
Because stores are held until the completion of all previous instructions, and because loads produce values needed for computation in the processor, keeping loads in program order with respect to stores has significant negative impact on performance. If a load waits until all preceding stores complete, and therefore waits until all instruction preceding the most recent store complete, then all instructions following the load that depend on the load data also wait. To avoid this performance problem, a load is allowed to bypass preceding stores that are waiting in the store buffer, and the load data is allowed to be used in subsequent computation.
When a load can bypass previous stores, the load may need to obtain data from a previous store that has not yet been performed. The processor checks for a true dependency that a load may have on a previous store by comparing a virtual memory address of the load against a virtual memory addresses of all previous, uncompleted stores (virtual addresses are addresses computed directly by instructions, before address translation by a memory-management unit has been applied). For this discussion, it is assumed that there is a unique mapping for each virtual address, so that it is not possible for two different virtual addresses to access the same physical location. With this assumption, virtual-address comparisons detect all dependencies between physical memory locations. A load has a true dependency on a store if the load address matches the address of a previous store, or if the address of any previous store is not yet computed (in this case, the dependency cannot be detected, so the dependency is usually assumed to exist). If a load is dependent on a store, the load cannot be satisfied by the data-cache, because the data-cache does not have the correct value. If the valid address of a store matches the address of a subsequent load, the load is satisfied directly from the store buffer—once the store data is valid—rather than waiting for the store to complete.
As the foregoing discussion implies, loads and stores are performed in a manner that avoids anti- and output dependencies on memory locations. Loads can bypass previous stores, but a store cannot bypass previous loads, so there can be no antidependencies between loads and stores. A store is conventionally issued in program order with respect to other stores, so there can be no output dependencies between stores.
Conventionally, loads are performed at the data cache in program order with respect to other loads. Those skilled in the art have thought that there was little or no performance advantage in allowing loads to be performed out of order, because the data supplied to the processor by older loads is more likely to be needed in computation than the data supplied by new loads.
A more detailed description of some of the concepts discussed above is found in a number of references, including John L. Hennessy et al., Computer Architecture—A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990) and Mike Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, N.J., (specifically chapter 8, parts of which have been reproduced above) 1991) which are both incorporated by reference in their entirety.
The present invention provides a system for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. The present invention provides a microprocessor system for executing a program stream which includes an instruction fetch unit for fetching instructions from an instruction store and for providing a predetermined plurality of the instructions to an instruction buffer. It further includes an instruction execution unit, coupled to the instruction fetch unit, for executing the plurality of instructions from the instruction buffer in an out-of-order fashion.
The execution unit includes a load store unit adapted to make load requests to a memory system out-of-order and store requests in-order. Thus, the main purpose of the load/store unit of the present invention is to make load requests out of order whenever feasible to get the load data back to the instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns eight bytes of unaligned data. The load/store unit aligns the data properly before it is returned to the instruction execution unit (IEU). Thus, the three main tasks of the load/store unit are: (1) handling out of-order cache requests; (2) detecting address collision; and (3) alignment of data.
The load store unit includes an address path adapted to manage a plurality of addresses associated with the plurality of instructions being executed and address collision means for detecting and signaling whether address collisions and write pendings exist between each of the plurality of instructions being executed, wherein the load store unit performs the load requests if no address collisions and no write pendings are detected. The load store unit further comprising a data path for transferring load and/or store data to and from the memory system and the instruction execution unit, the data path configured to align data returned from the memory system to thereby permit data not falling on a cache quad-word boundary to be returned from the memory system to the instruction execution unit in correct alignment.
This invention is pointed out with particularity in the appended claims. The above and further advantages of this invention may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
FIGS. 7(a) through 7(h) illustrate an example of the operation of LSU 205.
Referring to
Host processor 105 executes software instructions which are stored at addresses, or locations, in main memory 160. These software instructions are transferred to host processor 105 sequentially under the control of a program counter. Oftentimes, some of the instructions require that host processor 105 access one or more of the peripheral I/O devices 135.
MCU 120 is a circuit whereby data and instructions are transferred (read or written) between CCU 110 (both D-cache 119 and I-cache 118 (read only)), IOU 150, and main memory 160. MCU 120 includes a switch network 145 which has a switch arbitration unit 132, a data cache interface circuit 117, an instruction cache interface circuit 112, an I/O interface circuit 155, and one or more memory port interface circuits 148 known as ports, each port interface circuit 148 includes a port arbitration unit 134.
Switch network 145 is a means of communicating between a master and slave device. The possible master devices to switch network 120 are D_Cache 119, I_Cache 118, or an I/O Controller Unit (IOU) 150 and the possible slave devices are memory port 148 or IOU 150, for example. The function of switch network 145 is to receive the various instruction and data requests from CCU 110 (i.e., I_Cache 118 and D_Cache 119) and IOU 150. These units may be referred to as bus requesters. After having received these requests, the switch arbitration unit 132 and the port arbitration unit 134 prioritizes the request(s) and passes them to the appropriate memory port (depending on the instruction address). The port 148, or ports as the case may be, will then generate the necessary timing signals, and send or receive the necessary data to and from external memory bus 162. An Instruction Fetch Unit (IFU) 106 and an Instruction Execution Unit (IEU) 107 are the principle operative elements of host processor 105. VMU 115, CCU 110, and MCU 120 are provided to directly support the function of IFU 106 and IEU 107. IFU 106 is primarily responsible for the fetching of instructions, the buffering of instructions pending execution by IEU 107, and, generally, the calculation of the next virtual address to be used for the fetching of next instructions. Simultaneously, instructions are fetched by IFU 106 from I_cache 118 via instruction bus 101. The instructions are placed in "buckets" or sets of four instructions. The transfer of instruction sets is coordinated between IFU 106 and CCU 110 by control signals provided via a control bus 102. The virtual address of an instruction set to be fetched is provided by IFU 106 via an IFU control and address bus 103 to VMU 115. Arbitration for access to VMU 115 arises from the fact that both IFU 106 and IEU 107 utilize VMU 115 as a common, shared resource. In the preferred embodiment of architecture 100, the low order bits defining an address within a physical page of the virtual address are transferred directly by IFU 106 to the CCU 110 via control lines 102. The virtualizing high order bits of the virtual address supplied by IFU 106 are provided by the address portion of the buses 103, 104 to VMU 115 for translation into a corresponding physical page address. For IFU 106, this physical page address is transferred directly from VMU 115 to the CCU 110 via the address control lines 111 one-half internal processor cycle after the translation request is placed with VMU 115.
The instruction stream fetched by IFU 106 is, in turn, provided via an instruction stream bus 108 to IEU 107. Control signals are exchanged between IFU 106 and IEU 107 via control lines 109.
IEU 107 stores and retrieves data from D_Cache 215 via a bidirectional data bus 112. The entire physical address for IEU 107 data accesses is provided via an address portion of control bus 113 to CCU 110. IEU 107 utilizes VMU 115 as a resource for converting virtual data addresses into physical data addresses suitable for submission to CCU 115. Unlike operation with respect to IFU 106, VMU 115 returns the corresponding physical address via bus 104 to IEU 107.
CCU 110 is used to serve as a buffer between host processor 105 and main memory 160. Generally, CCU 110 is a small, fast memory located close to host processor 105 that holds the most recently accessed code or data. CCU 110 performs the generally conventional high-level function of determining whether physical address defined requests for data can be satisfied from the instruction and data caches 118, 119 as appropriate. Where the access request can be properly fulfilled by access to the instruction or data caches 118, 119, CCU 110 coordinates and performs the data transfer via the data buses 101, 113. Where a data access request cannot be satisfied from the instruction or data cache 118, 119, CCU 110 provides the corresponding physical address to MCU 120 along with sufficient control information to identify whether a read or write access of main memory 160 is desired, the source or destination cache 118, 119 for each request, and additional identifying information to allow the request operation to be correlated with the ultimate data request as issued by IFU 106 or IEU 107.
A superscalar control block (not shown) determines when an instruction can be issued by performing a data dependency check and checking to determine whether the required functional unit 260, 262, 230 is available. Once the superscalar control block decides to issue an instruction, IBUS 225 retrieves (from register file 250, bypass data 280, 282, or immediate data 258, 259) the data required by the issued instruction. IBUS 225 is comprised of a plurality of multiplexers that select which data will be transferred to functional units 260, 262 and 230. IBUS 225 transfers the data to a pair of buses: an A bus and a B bus. The selected data is placed on either the A bus or the B bus by determining which functional unit 260, 262, 230 will be used by the instruction or is required by the operation of the instruction being executed.
Most instructions' inputs and outputs come from, or are stored in, one of several register files. In a preferred embodiment, each register file 250 (e.g., separate integer, floating point and boolean register files) has thirty-two real entries 254 plus a group of eight temporary buffers 252. When an instruction completes (the term "complete" means that the operation is complete and the operand is ready to be written to its destination register) its results are stored in a preassigned location in temporary buffers 252. The results are later moved to the appropriate places in real registers 254. This movement of results from temporary buffers 252 to real registers 254 is called "retirement." More than one instruction may be retired at a time. Retirement comprises updating the "official state" of the machine including the computer's program counter.
Instructions are sent to IEU 107 from IFU 106 through an instruction decode FIFO (first-in-first-out) register stack storage device (not shown) (referred to herein as an instruction window) in groups of four called "buckets." The bucket is broken up into four units: a load, a store, and two execute units. The bucket has been broken up into these four units since system 100 operates with instructions that can perform either a load, a store, an execute, or a combination of all three. Thus, the present invention provides a bucket that can handle all three situations.
IEU 107 can decode and schedule up to four buckets of instructions at one time. The instruction window stores 16 total instructions in four buckets. IEU 107 examines the instruction window; every cycle IEU 107 tries to issue a maximum number of instructions from the instruction window. Once all the instructions in a bucket are executed and their results are stored in the processor's register file 250, the bucket is flushed from the instruction window and a new bucket is stored in the instruction window.
Once the instruction is issued, the registers in register file 250 can be accessed. The temporary register 252 is accessed when an instruction, that had a data dependency on data produced from an earlier instruction, is executed. The data from register file 250 is transferred via data lines 254 to IBUS 225.
DAFU 230 calculates a 32-bit linear address for use by LSU 205. DAFU 230 supports many different addressing modes. DAFU 230 calculates the first and last address of the data which takes two cycles if the data crosses a quad-word boundary. Up to four components are added to form the address. These components are the segment base, a base register, a scaled index register, and a displacement value. The Segment Base contains the starting address of the desired memory segment. The base and index registers are any 32-bit register from the register file 250. The index register is scaled by multiplying it by 1, 2, 4 or 8. The displacement value is a constant value (immediate) given in the instruction. Any of these fields can be omitted giving maximum flexibility in address calculation.
The segment base comes from the Segment Register block 257. Segment base generator 257 produces a value that is indicative of how the data is partitioned in memory, and transfers this value to DAFU 230 via date line 266. The displacement comes from an immediate displacement buffer 255. Immediate displacement buffer 255 transfers immediate data via lines 265 to DAFU 230 and to IBUS 225 via data lines 258 and 259, respectively. DAFU 230 and VMU 115 provide LSU 205 with the addresses of any load and/or store requests. LSU 205 processes these requests and eventually returns any requested data to write bus 270. The write bus 270 is comprised of a set of multiplexers that select which data (e.g., data provided by LSU 205 or data provided by functional units 260 or 262) to latch into register file 250 based on a priority scheme. The data is transferred from write bus 270 to register file 250 via lines 275, 276. Data from load and/or stores are always given highest priority. Occasionally, when two instructions are issued back to back, and they depend on each other, IEU 107 would like to bypass storing the data into the register file 250 and latch it immediately into IBUS 225. This can be accomplished via data lines 280, 281. Consequently, the resources that are waiting for the data need not waste a cycle waiting for the data to flow through the register file 250.
Data from data lines 275, 276 is also provided directly to LSU data path 210 in case an instruction involves an execute operation and a store operation. After performing the load and execute operations, the data can be directly transferred to LSU datapath 210 in order to perform the store. This eliminates having to access the temporary register file 252 for the store data, which in turn increases instruction execution time. The main purpose of LSU 205 is to make load requests to CCU 110 out of order whenever feasible to get the load data back to IEU 107 as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. LSU 205 is divided into two parts: data path 210 and address path 220. The address path 220 interfaces with DAFU 230, VMU 232, and CCU 110 and the datapath interfaces with the writebus 270, CCU 110, DAFU 230, and IBUS 225. The three main tasks of LSU are: (1) out of order cache requests; (2) address collision detection; and (3) data alignment.
Each bucket of instructions can contain a load and a store to the same address (with some other operation in between), a load only, a store only, or no load and no store. Thus, LSU 205 has a selection of up to four loads and four stores to choose from. The instruction set used in the preferred embodiment of the present invention is a CISC instruction set which allows such complex operations as:
Only one address is needed for each instruction bucket and serves as both a load address and a store address. For each instruction bucket, two 32-bit addresses are stored in one of the address buffers 310-313: one for the first byte of the access and one for the last byte of the access. When the lower 12-bits are ready from DAFU 130, they are latched into a temporary buffer 305. The following cycle, when the upper 20 bits are ready from the VMU 115, all 32-bits are latched into the appropriate address buffer (i.e., Address1 or Address2). Address calculation is not done in instruction order, but instead is performed when the register dependencies have cleared. After translation of the address, a valid bit (not shown) is set in the instruction's address buffer 310-313 indicating that the address is valid. There are two reasons for keeping both addresses: address collision detection and cache request for page crossing.
The address utilized by LSU 205 is a physical address as opposed to the virtual address utilized by IFU 106. While IFU 106 operates on virtual addresses, relying on coordination between CCU 110 and VMU 115 to produce a physical address, IEU 107 requires LSU 205 to operate directly in a physical address mode. This requirement is necessary to insure data integrity in the presence of out-of-order executed instructions that may involve overlapping physical address data load and store operations. In order to insure data integrity, LSU 205 buffers data provided by store instructions until the store instruction is retired by the IEU 107. Consequently, store data buffered by LSU 205 may be uniquely present only in LSU 205. Load instructions referencing the same physical address as an executed but not retired store instruction(s) are delayed until the store instruction(s) is actually retired. At that point the store data may be transferred to the CCU 110 by LSU 205 and then immediately loaded back by the execution of a CCU data load operation.
As discussed above, address calculation by DAFU 230 occurs in one clock cycle and address translation by VMU 132 the next. If the address is for a load, then a cache request is made. If the address is for a store, then LSU 205 waits for the retirement signal to be sent before performing the store. A load request can be made to CCU 110 as early as the first cycle of the address calculation. The lower 12-bits of the address are sent to CCU 110 at this time and the upper 20-bits (which represent the page number) are sent to CCU 110 the following cycle after address translation.
When the load store address path 220 is free, an immediate request can be made to cache 110 via line 330. Since there are no pending load and/or store addresses currently in the load store address path 220, there is absolutely no danger of an address collision or a write pending. Thus, the request can be made immediately to cache 110.
Block 340, which includes a plurality of multiplexers, is used for selecting the address for the cache request from address buffers 310-313.
LSU 205 uses address buffers (i.e., reservation stations) 310-313 for making requests to cache 110. The four address buffers 310-313 (also referred to as reservation stations) correspond to the four buckets contained in the central instruction window (not shown). When IEU 107 requests the new bucket from the decode unit (not shown), one of the address buffers 310-313 is reserved. The address buffer 310-313 is assigned according to instruction number. An historical pointer is updated to indicate the youngest (or newest) instruction. At this time, it is known whether the instruction involves a load, a store, both, or neither, as is the size of the data involved in the load and/or store operation. Address buffers 310-313 are deallocated when the corresponding instruction is retired by IEU 107. Subsequent to deallocation, a new instruction bucket is received from the decode unit (not shown).
A load dependency (address collision) on a store must be detected in order to use load bypassing and out-of-order load execution. A load dependency is indicated by an address collision or a pending store address. A load dependency occurs when a load operation is requested at a memory location where an older instruction requested a store operation. The address collision detection requires the first address of the load to be compared against two addresses (the first and last) for each older store. This extra comparison with the last byte of the address is required since the store could cross a quad-word page boundary or be unaligned. Masking of the address bits is done depending on the size of the data to minimize false dependency detection. If the load data crosses a quad-word (64-bit) boundary, it is assumed in a preferred embodiment to have a load dependency since comparators are not available to check the second address of the load against the two addresses of each store. When a collision is detected, the load operation must wait until after the colliding store operation has been sent to CCU 110. A pending store address means that the address of the store is not yet valid, so a load dependency must be assumed until the time the address is known.
The first address 405, 406 for each load is compared against each other pair of addresses 407-418. The two compare results are ANDed with their valid bits 419-424, and then ORed together to produce an address match 430 a, 430 b, 430 c. Address match 430 is then ANDed with the instruction number compare 425-427 and the store bit 431-433 to produce the collision check 450 a, 450 b, 450 c. The instruction number compare 425-427 indicates the relative age between two instructions. For example, instruction compare 425 indicates the relative age between a first instruction in address buffer 310 and a second instruction in address buffer 311. If the second instruction is older then the first instruction then no collision exists. These three collision checks 450 are ORed together to yield an address collision signal 460 for the particular load being checked.
When detecting an address collision, the starting (first) address of each load is compared with the first and second address of each store. Since a load or store operation may be accessing anywhere from 1 to 10 bytes, some masking of the address is done to insure that a collision will be detected. This is done via signals 470-475. 0, 2, 3 or 4 of the least-significant-bits are masked out of both addresses before comparing them to each other. If the masked addresses match exactly (equal compare) then an address collision is possible. The number of bits to mask out (0, 2, 3, 4) depends on the operand size of the two instructions whose addresses are being compared, along with the two least significant bits of the first address. The two least significant bits of the first address must be used in order to limit the number of collisions which are detected incorrectly. The largest operand size is used with masking as follows:
By doubling the number of comparators used in hardware, this restriction could be removed. If the store address crosses a quad-word boundary then the collision would be detected.
The following examples show why masking is required. (All numbers below are in binary). Address2 of the load is not given since it is not used for collision checking.
The store instruction must be performed in program order with respect to all other instructions, not just other load and stores. A store request is issued to CCU 110 when a signal comes from IEU 107 to retire the store instruction. This signal indicates that all previous instructions have finished and they did not involve an exception or mispredicted branch. The store instruction cannot be performed any earlier since a store irrevocably changes the state of the machine and it is essential to verify that an exception or branch did not occur. The store is given priority over a load for using data cache 119 since delaying the store would also delay the retirement of the bucket and the acceptance of the next decoded bucket from the instruction decode unit (not shown).
Most load instructions can be issued out-of-order provided that the load is not dependent on a previous store. An exception to this is loads with side effects such as reads from memory-mapped I/O. The preferred embodiment of the present invention uses a memory-mapped input/output (I/O) subsystem. Some I/O devices change state when accessed by a read; for example, some FIFO buffers sequence to the next data item which results in some device-status registers clearing themselves. In this type of system, load bypassing is a dangerous operation. A bypassed load may be issued incorrectly, because of a mispredicted branch or exception. The bypassed load cannot be allowed to modify the system state incorrectly. The problem is solved by configuring the load store unit to make these type of requests in order.
The load/store unit also provides a mechanism for notifying cache 110 whether or not the data involved in the cache request is cacheable or not. It also allows the processor to notify cache 110 that this data should be write-through meaning it is cacheable, but should also write through to the memory immediately. External read accesses that change system states are a subset of these non-cacheable accesses, but the problem above is solved by making in-order requests in conjunction with notifying cache 110 that this data is not cacheable. Thus, rather than avoiding load bypassing altogether, the processor can prevent the bypassing of noncacheable loads. This permits most load operations to take advantage of bypassing, without causing incorrect operation for the occasional noncacheable load. This is also necessary to insure that no exceptions occur before the memory is changed. If a load does not have a dependency on a store then "load bypassing of stores" will occur.
Each load thus has associated with it two bits: page_cache_disable and page_write_through. These can come either from VMU 115 or IEU 107.
Store data can come from one of two place. First, it can be issued directly to LSU 205 on the integer data buses during 64-bit integer stores. The second way is by snooping the results of the integer and floating point functional units. This is done to support the common "execute-then-store" sequences where the result of an execution is the store data for the instruction. This allows the results of CISC instructions such as "[R2]<[R2] OR R4" to be stored without being explicitly issued to LSU 205.
LSU 205 can only make one request to CCU 110 per cycle and priority is given to store operations. Store operations are sent to CCU 110 as soon as the write control notifies LSU 205 that this instruction is ready for retirement. Next priority is given to the oldest load operation with a valid address in the address buffers 310-313 which does not have an address collision or pending write. Relative age between the instruction is determined by buffer location and the value of the buffer pointer. Finally, priority is given to a new load just arriving from DAFU 230. In this last case, address collision and pending write will not be checked until after the request has been made, and if necessary, the load request will be canceled.
Occasionally, a cache miss will occur. For a store, CCU 110 handles this situation and the miss is completely transparent to LSU 205. For a load, LSU 205 is notified of the cache miss and a delay is observed before the data is returned. LSU 205 then signals the IEU 107 that the cache miss occurred so that instructions waiting for this data can be canceled.
If the desired data crosses a cache line boundary, two or three cache accesses must be made for the load operation. These requests are made consecutively, one each cycle. In a preferred embodiment, a cache line is 8 bytes wide and aligned at address ending with 000. Three cache requests are only required for 80-bit data accesses beginning at an address ending in 111. A load aligner 550 (described below with reference to
Most load/store units zero-extend or sign-extend the data to fit the destination register. However, the preferred embodiment of the present invention preserves the initial value of the destination register and only changes a portion of it. This, of course, is relevant only for integer load data with a size of 8 or 16 bits. The initial contents of the register are sent to LSU 205 at the time of address calculation. The load data from data cache 119 is then merged with the initial data.
Data buffers 520-526 are provided for holding load and/or store data during data transfer to or from data cache 119. There is a one-to-one correspondence between each data buffer 520-526 and address buffers 310-313 (and in turn with the four instruction buckets). For each address buffer 310-313, there are two corresponding data buffers in LSU data path 210: one for integer load and integer store data (8 bytes) 520-526 and one for floating point load and store data (10 bytes) 540-546. The present invention has a separate LSU data path for floating point operations. The operation of floating point data buffers 540-546 is the same as those described in connection with the integer data path. Since an instruction is either integer or floating point, the two units are do not need to be physically connected. Only the operation of integer data buffers 520-526 will be described in detail below.
Control lines 581 and 587 are provided to control the data flow through multiplexers 560 and 565, respectively. Control lines 582 through 586 are provided to control data flow to/from data buffers 520, 522, 524, and 526.
During a load operation, data enters LSU data path 210 from data cache 119 via line 290. The load data enters align block 550 which aligns the data (as described below) and transfers the aligned load data to multiplexers 530-536. The aligned load data is then latched into one of the data buffer 520-526 depending on which instruction requested the data. During a store operation, the store data enters LSU data path 210 from IEU 107 via data lines 275, 276, 277 and is subsequently latched into the appropriated data buffer 520-526.
Once either the load and/or store data has been latched into data buffers 520-526, it can be forwarded to either data cache 119 via line 290 or IEU via line 292. All four data buffers 520-526 provide data to multiplexers 560, 565 which in turn select the appropriate data to be transferred out of LSU data path 210.
Oftentimes, the results of an instruction which includes a store must be stored into main memory 260. Thus, after the instruction executes the result is directly written via data lines 275, 276 to LSU data path 210 (as opposed to first storing the results in register file 250). LSU data path 210 holds the data in the appropriate data buffer 520-526 until it receives a retirement signal for the instruction.
Periodically, a particular instruction does not intend to store over an entire destination register. In this case, "merge data" is provided to LSU data path 210 via data line 282. For example, if an instruction only wants to store 8 bits to the destination register, but the instruction intends to preserve the remaining 24 bits in the register, a merge operation is performed. Thus, data line 282 would supply the initial value (i.e., merge data) of the destination register to LSU data path 210. The merge data (i.e., contents of the destination register) is latched into the appropriate data buffer 520-526. Next, the new (load) data returns from the cache via line 290(a) and enters align block 550. Align block 550 aligns the data and provides it to the multiplexers 530-536. The load data is then latched into the same data buffer 520-526 which is holding the merge data. Once all the data is assembled it can be transferred to the proper memory location (i.e., data cache 119 or register file 250).
Conventional load store units typically require addresses to be aligned to certain boundaries. For example, a 32-bit data access must have an address ending in 000. However, the computer architecture of a preferred embodiment allows unaligned accesses of 8, 16, 32, 64, or 80 bit data. Having unaligned addresses has the following effects: (1) extra hardware is required for detecting load dependencies on stores; (2) the data may cross a page boundary requiring two address translations; and (3) multiple cache accesses may be required for one load.
The load data returned from CCU 110 is 8 bytes long and must be aligned and placed in the proper position in the data buffer 520-526. Sometimes two or three sets of data must be returned before the complete load is ready (e.g., when more than one cache access is required). In addition, these sets of data may even be returned out of order, so special handling is required.
Integer data alignment is handled by using eight 8-input multiplexers (8 bits wide) with each corresponding to one byte of the data request. An 8 bit select line is used to determine which of the 8 bytes of data loaded from CCU 110 should be latched into the appropriate data buffer 520-526. Additionally, data buffer 520-526 are byte enabled to control which bytes can be overwritten.
Floating point data alignment works the same way as integer data alignment except that ten 8-input multiplexers are used.
LSU 205 does not support load forwarding. If a load is dependent on a store then that load must wait for the store data to be written to the cache before making the load request. However, there is nothing inherent about the design of the present invention that would discourage implementing a load forwarding mechanism. Those skilled in the art would readily be in a position to make the necessary hardware changes to implement load forwarding.
The preferred embodiment of LSU 205 supports a multi-processing environment. Each instruction can contain a lock or an unlock command in addition to a load and/or a store. These signals are sent to the cache which will lock the data and notify the memory and I/O subsystems to do the same. When lock or unlock commands are present in the instruction window, loads must be performed in order with respect to these instructions; i.e., a subsequent load can not be performed without first performing the load with the lock/unlock command.
Example of the Operation of LSU 205
Shown in TABLE A is a sample program that illustrates the operation of LSU 205. The program is written in Intel 486 notation. Three registers are used and they are labeled eax, ebx, and ecx. The data that is loaded and/or stored is assumed to be 32 bits in width. Brackets indicate an address location.
Before this code is executed, assume that the registers and memory contain the following values (all value are in hex):
Referring to FIG. 7(a) through 7(h), a representative illustration of LSU 205 is shown. Each figure represents a single cycle (e.g., FIG. 7(a) represents cycle 1 and FIG. 7(b) represents cycle 2). All four address buffers 310-313 are shown, along with their respective load 701, store 702, and valid bits 717. Furthermore, there is a collision bit 710, a pending bit 715, as well as an indication of the size 705 of the data requested. The current memory contents of addresses 0100 to 0107 and 1200 to 1207 is shown at reference number 780. Block 730 indicates the current cache request. Block 740 shows the data that has just been returned (if any) from CCU 110. Block 760 indicates the address being returned from VMU 115 and block 770 indicates the address being returned from DAFU 230. The load and store bits are set in order, while the addresses can be provided to LSU 205 out-of-order. Block 750 shows how returned data is physically aligned.
Referring to FIG. 7(a), the first instruction is "mov ebx, [ecx]". Initially, the address stored in ecx must to transferred to LSU address path 220. The address stored in ecx, namely 1201, is transferred from DAFU 230 to temporary address buffers 305. However, the entire address is not needed. Only the first twelve bits and the least significant three bits are transferred to temporary buffers 305 because the upper 20 bits are transferred to VMU 115 from DAFU 230. The load bit in bucket 0 is set to one since the mov operation involves a load. The requested data is 32 bits (as indicated by 011 in block 705).
Since this is the first set of addresses in LSU 205, the address information is immediately forwarded to CCU 110 along with an identification (id), as shown in block 730. LSU 205 uses the identification to determine which instruction the returned data is associated with. The temporary registers 305 are used while LSU 205 waits for an address being translated by VMU 115 to be transferred to LSU 205.
the second instruction "dec ebx" has been placed into the address buffer queue. Since the dec operation involves neither a load nor a store, load bit 701 and store bit 702 associated with address buffer 311 are both set to zero. An address calculation is not required for this instruction since neither a load nor a store is required.
Turning now to FIG. 7(b), the first byte of the address stored in ecx has now been placed in register address1 and the last byte of the address has been placed in address2. Both, of course, in address buffer 310. Both valid bits have been set since both registers (address1 and address2) contain valid addresses. Note that it is possible for address1 and address2 to be latched into the address buffers 310-313 at different times. This happens when there is a page crossing which requires two translations from VMU 115.
The third instruction is "or [eax], ebx." Information (sent by IEU 107) regarding the third instruction has been entered into the appropriate blocks corresponding to address buffer 312. Since the OR instruction requires a load and a store operation, both bits have been appropriately set to one. The data requested is 32 bits long, as indicated in block 705. Moreover, the address for the load/store associated with the third instruction is provided by DAFU 230, as shown in block 770. A cache request is made for this data, as shown in block 730.
In addition, during cycle two the data requested for the first instruction has been retrieved from the cache and stored in the data register 520. However, the returned data shown in block 730 is unaligned data. CCU 120 returned the block of data beginning at address 1200, but the instruction requested 32 bits of data starting at 1201. Consequently, the returned data must be aligned as shown in block 750. The returned data is shifted over by two bits by setting LD_ALIGN to 00000010, and then the first 32 bits of data are selected by BYTE_SEL.
Referring now to FIG. 7(c), the LSU 205 is provided with the next address by DAFU 230, as shown in block 770. The addresses associated with the third instruction are latched into address buffer 312. Both valid bits 717 are set. Since the first instruction has completed its operation (i.e., the data was returned from CCU 110 and forwarded to IEU 107) the valid bits have now been reset. (The bucket number has been reset to 4 only for illustration purposes. In a preferred embodiment, a pointer keeps track of the relative age of the instructions.) The third instruction, requires the fetching of the address stored in eax. Once the address enters LSU 205 a cache request can be performed.
In addition, information concerning the fourth instruction, namely the instruction is a load and the data being requested is 16 bits in width (indicated by a 010), has arrived from IEU 107, as shown in the appropriate blocks associated with address buffer 313. However, a store (namely, the third instruction) which is older than the fourth instruction exists. LSU 205 utilizes a pointer to determine which address buffer contains the oldest instruction information. Since this store exists, the write pending bit 715 associated with address buffer 313 is set. Consequently, a cache request cannot be generated for the fourth instruction at this time.
CCU 110 returns data to LSU 205 for instruction three, as indicated in block 740. Since the requested data started at address 100 the returned data does not need to be aligned. Only the first 32 bits are selected by BYTE_SEL, and the data is latched into data buffer 526.
Referring to FIG. 7(d), the addresses associated with instruction four are latched into address buffer 313 and the corresponding valid bits have been set. Next, an address collision operation is performed. Address1 from instruction four is compared with address1 and address2 of instruction three, which results in a determination that an address collision exists. As such, the collision bit 710 associated with address buffer 313 is set. Because of the presence of a collision, a cache request cannot be generated during cycle 4. However, even though a cache request cannot be performed, merge data arrives from IEU 107 for instruction four, as shown in block. The merge data is the data from register ebx.
Merge data is required since instruction four is only a 16 bit operation. The merge data is latched into data buffer 526.
Referring to FIG. 7(e), write A data (WRA_DATA) arrives from IEU 107. WRA_DATA represents the results of the OR operation from instruction three. This data is latched into data buffer 524. Also during cycle 5, the next bucket is retired, namely bucket 1, as shown in block 780. Specifically, the retire_next bit is set to one indicating that the next instruction can be retired and the retire_num bit is equal to one indicating that the instruction in bucket one should be retired. Note that the address collision still exists between instruction three and instruction four.
Referring to FIG. 7(f), the data in data buffer 524 has been ORed with the data in ebx to produce the value 87654321. During cycle 6, the third instruction is retired, as shown in block 785. The retirement of instruction three allows LSU 205 to reset the collision bit 710 associated with the fourth instruction. As shown in block 730, a cache request is made to store the value produced by the OR operation at memory location 00000100 (which is the address stored in register eax). As shown in block 780, the data has been stored to this data location.
Referring to FIG. 7(g), instruction four loads the data in memory location 0103 (i.e., the first 16 bits of register eax plus three). Consequently, a cache request is made for the load operation associated with instruction four, as shown in block 730.
Referring to FIG. 7(h), the requested (unaligned) load data returns from the cache, as shown in block 740. As shown in block 750, the data is then aligned by shifting the data over three bytes since the requested data started at address 0103 and not 0100. Since, only the first 16 bits are requested only the first two bytes are selected from the aligned data. The 16 bits are then latched into data buffer 526, which in turn gets transferred back to IEU 107 for storage in register ebx.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
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|Howard Johnson Troutville properties are provided below. Search for cheap and discount Howard Johnson hotel rooms in Troutville, VA for your upcoming meeting or individual travels. We list the best Howard Johnson Troutville hotels & lodging so you can review the Troutville Howard Johnson hotel list below to find the perfect place.
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Holiday Greetings
[ 12/20/2005 ] Hello Heartmongers, Just a quick note to say... "Happy Holidays and please don't choke on your food and die" Best of Love, everyday, Mike Hey Heartmongers and all of the ships at sea. Happy holidays!! (boy, is that the "politically correct" phase this month or not?? I didn't get the memo.) I'm looking forward to seeing everyone next year on the road. Well, actually it might be safer on the side of the road. Take care, love your family and friends and remember, stewed prunes taste much more like tomatoes than anchovies. Your pal, Slatts Bartock I'm a-wishin' everybody a fantastic and safe holiday season. Drive safe, call a cab, have a blast. Love, Ben Hey there Heartmongers!!! Hope your holidays rock! See you in the New Year ... Love, Debbie
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Blog History
Postcards From the Road
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Learn more about Ame Comi Heroine Power Girl Mini Figure:
Manufacturer: DC Direct
Mfg Part#: 30270
Sku: 226650950
Package Weight: 0.5 lbs
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|Powerful Power Girl Mini Figure! From Wave 3 of the Ame Comi Heroine Mini Figures line. Features a brand-new sculpt, display base, and 4-color window-box packaging. Power Girl is tiny, but mighty mighty cute, that is! Powerful Power Girl Mini Figure! They may be tiny, but they're mighty mighty cute, that is! The Ame Comi Heroine Mini Figures are here. Supergirl, Power Girl, and Hawkgirl make up the third wave in the super-cute line of mini figures affectionately known as "mini-comis." Based on the larger Ame Comi Heroine PVC statue line, these miniature Ame Comi figures are all brand-new sculpts! Packaged in a 4-color window box with J-hook, each non-articulated PVC 5-inch tall mini figure includes a display base. Here, Power Girl strikes a classic anime pose ready for your collection! Supergirl and Hawkgirl sold separately.


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HOME ActionSports Element Gear Element T-Shirts Element T-Shirts Long Sleeved $20 to $40 (30 items) Product ID: 774520
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You've chosen a solid path, friend. Finding a good-lookin' shirt like the Lane button-down by Element isn't easy to do, but hey — you've done it. This long sleeve shirt features an allover yarn dye stripe pattern, Element brand buttons, two front buttoned chest pockets and a small embroidered logo at the right hem. Congrats on your savvy style success.
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- Willamette
- Athletics
- News Archive
- 2013
- Bearcats Fall to La Verne
Men's Basketball | Saturday, November 16, 2013
Bearcats Can't Hold Halftime Advantage, Fall to La Verne
Manu, Hansen, Brown and Luedtke Reach Double Figures for Willamette
LA VERNE, CALIF. -- The University of La Verne trailed by two points at halftime, but connected on a three-pointer to open the second half and never looked back, as the Leopards defeated the Willamette University Bearcats, 70-64, on Saturday, Nov. 16 at La Verne's Sports Pavilion in La Verne, Calif.
La Verne improved to 2-0 on the year, having earned a 72-63 overtime victory against Pacific University on Friday, Nov. 15. Willamette dropped to 0-2.
The Leopards' Brett Stephan led all players in scoring with 27 points on 8 of 11 shooting, including a remarkable 5 for 7 on 3-point shots. Stephan was also 6 for 6 on free throw attempts. Ronn See added 15 points for La Verne, connecting on 9 of 10 attempts from the charity stripe.
Four Bearcats reached double figures. Avery Manu (Sr., W, Pocatello, ID/Highland HS) topped Willamette with 16 points, shooting an efficient 7 of 10 from the field. Alex Hansen (Sr., W, Reno, NV/Galena HS) provided WU with 11 points.
Alex Brown (Jr., F, Happy Valley, OR/Clackamas HS) and Brandon Luedtke (So., F, Meridian, ID/Mt. View HS) each scored 10 points, while Luedtke also added seven rebounds.
The Leopards scored the game's first basket on a three-pointer by Stephan and stretched their lead to as many as six, but Willamette rallied to take a 16-14 lead on a Hansen layup at the 8:53 mark.
La Verne tied the game twice in the final minutes of the first half, with Weston Newell knotting the score at 28 with just 46 seconds remaining in the half. With 8 seconds left, however, Luedtke scored after rebounding Brown's missed jumper, giving the Bearcats a 30-28 halftime lead.
Just over two minutes into the second half, however, another Stephan three-pointer gave the Leopards a lead they would not relinquish. A 9-2 spurt extended La Verne's advantage to 10, capped by Kendall McClain's three-pointer with 13:15 remaining.
Still, Willamette rallied. Seven quick points, including an old-fashioned three-point play from Luedtke, cut the Leopards' lead to 49-46 at the 11:42 mark, and the Bearcats narrowed the deficit to just a single point when Manu canned a jumper with 3:51 left.
Clinging to a 57-56 lead, La Verne's defense tightened, limiting Willamette to just a pair of free throws from Brown over the following 3:17. In the meantime, Stephan's jumper pushed the lead back to seven with 57 seconds remaining.
The Leopards connected on 5 of 6 free throws over the game's final 30 seconds to ice the contest.
The Bearcats shot a blistering 54.2% (13 of 24) in the first half, but cooled off considerably to 38.5% (10 of 26) in the second half. WU shot 40.6% (23 of 50) for the game. For the second straight matchup, Willamette struggled from beyond the arc, hitting just 1 of 9 attempts (11.1%).
The Bearcats did hit 81.0% of their free throw attempts (17-21).
La Verne connected on 46.3% of its shots (19 of 41), including 10 of 20 (50.0%) in the second half. The Leopards also hit 9 of 19 three-pointers (47.4%) and nailed a stellar 88.5% of their foul shots (23 of 26).
Willamette's pressure defense did force La Verne into 20 turnovers, though the Leopards also earned 14 assists. The Bearcats committed 18 turnovers against just 2 assists.
Willamette will host Claremont-Mudd-Scripps on Saturday, Nov. 23 at Cone Field House. Tip-off is set for 7 p.m. (PST).
University of La Verne 70
Willamette University 64


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Jeffrey Goldberg
Perhaps you've heard that Anne-Marie Slaughter, a former US State Department official, wrote an article recently for The Atlantic (the magazine I also happen to write for) about women who thought they could "have it all" learning the hard way that they cannot.
The reason I know Slaughter wrote this article is that it's the only thing anyone in that small slice of America who is in a position to have it all — that is, a financially rewarding and non-agita-inducing balance between career and family — has been talking about this past week, at least until the Supreme Court did a favor for the other 99 percent.
Slaughter's article is smartly written, and the plight she identifies is real: she raises a whole cluster of issues about how the American workplace is structured to thwart women who seek successful careers and also want to have a meaningful relationship with their children.
But Slaughter only nods in the direction of a few points I think she could address more deeply. The first is that professional women aren't the only group having difficulty keeping work and family in balance. Men, particularly those who value an active role in their family life, now face a set of choices their fathers and grandfathers didn't. This isn't to say the problems are equivalent; women are most often the parent of last resort. But men, too, are tortured by the lack of time at home.
The most chilling image in her article — at least from the perspective of a father who never feels he is spending enough time with his children — is this: "At the diplomat Richard Holbrooke's memorial service," Slaughter writes, "one of his sons told the audience that when he was a child, his father was often gone, not around to teach him to throw a ball or watch his games. But as he grew older, he said, he realized that Holbrooke's absence was the price of saving people around the world — a price worth paying."
She continues: "It is not clear to me that this ethical framework makes sense for society. Why should we want leaders who fall short on personal responsibilities?"
This anecdote stands out as a cautionary tale about the sacrifices men make for their careers. But it also suggests a certain level of naivete on Slaughter's part. Is it really possible to imagine Holbrooke, in the midst of negotiating an end to war in the Balkans, informing Slobodan Milosevic that he would like to postpone negotiations on account of a Little League game?
There are some jobs that demand a level of commitment that leads to subsidiary misery. Slaughter herself seemed unaware that it might have been difficult for her to run a division of the State Department while keeping her family in Princeton, New Jersey. I'm sympathetic to her ambition — as I am to men like Holbrooke — but some work-family balance issues simply cannot be fixed.
The other issue Slaughter mentions too fleetingly is that the problems of most professional-class women are ultimately caviar problems. The vast majority of American women must work in order to feed themselves and their children; they have little time to consider their own fulfillment. Not to mention the hundreds of millions of women around the world who spend their days trying to keep their families alive by gathering firewood and water, and by scraping together a dollar a day.
Of course, Slaughter — formerly of Hillary Clinton's State Department, which is trying to make the advancement of women's rights an integral part of American foreign policy — knows this better than anyone. I asked her by e-mail if she felt any frustration about the response to her article. After all, she's a staunch advocate of human rights and humanitarian intervention, and this article has gotten her more attention than anything she has said about the US responsibility to the women of Afghanistan.
"To say I am 'frustrated' about anything given the unbelievable response to my piece would be churlish indeed," she wrote me. But she added: "I wish I could get people so passionate about foreign policy. I think it's human nature, however, to respond much more intensely to something that touches your daily life.
"I do not think it is accidental that as more women rise in foreign policy, they feel much more strongly, not only about the abstract advancement of 'national interest' but about the lived reality of people's lives around the world, particularly women and children and communities. Indeed, I say something about that in the piece in terms of how our leaders will think about the impact of their decisions if they are fully engaged with family life at home."
If men are indeed scared to make foreign-policy decisions informed by humane instincts, then this is all the more reason to encourage Slaughter's campaign to get us to rethink the way we organize our professional lives.
The small tragedy is that, in real life, there may be no way for many of us to get home each night for dinner.
Jeffrey Goldberg is a Bloomberg View columnist and a national correspondent for The Atlantic.


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Dülp at the German blog Bolzplatz has an interesting post on Gladbach and the club's recent winter acquisitions. He's experiencing a crisis of faith in the club, seeing Meyer's recent moves as "Advocaat Reloaded." In other words, Meyer's calls for … Continue reading
Borussia Mönchengladbach Rank: 18th Preseason prediction: 12th What was I thinking? Gladbach entered the Bundesliga having won the 2. Bundesliga with the most prolific offense and third-stingiest defense. They featured a versatile, if somewhat inexperienced side headlined by Germany's next … Continue reading
0 – The number in Frankfurt's win column (still, and I'll keep on mentioning this until Frankfurt take note and do something about it) 5 – Difference in points between 1st (Hamburg) and 11th (Bayern). 6 – Number of goalscorers … Continue reading
It appeared inevitable and now it's been confirmed as Borussia Möchengladbach fired trainer Jos Luhukay today in their wake of their defeat to Köln (and their fourth straight). After seven games, six of which they've lost, Gladbach sit at the … Continue reading
0 – Number of wins by Frankfurt, the last remaining winless team 5 – Total number of shots by Gladbach in their 0-1 defeat to Hamburg 7 – Goals scored by Patrick Helmes this season, that's equal to or more … Continue reading
While this is expected to become a weekly column, I have decided to hand out the first Weekly XI based on the cumulative efforts of the first three weeks. I will use a 3-4-3 formation for my picks. Schober (S04) … Continue reading
Gladbach's victory over the stalwart's of the league, Werder Bremen, gave us a glimpse at a team that has been revitalized under Jos Luhukay and Christian Ziege, and could well be in for a bright future. The addition of Michael … Continue reading
Defender Marcell Jansen has transfered from Bayern München to Hamburg today. The 22-year old played 73 games over 3 seasons for Borussia Mönchengladbach before switching to Bayern. Now after only a single year and 17 games in Bavaria he has … Continue reading
1st Schalke What You Know: If baseball's Chicago Cubs had a baby with the Red Sox prior to 2004, Schalke would be the offspring. What You Don't: All things both good and bad must end. What to Expect: Yes, Campeones! … Continue reading
The Deutsche Presse Agentur released a poll yesterday about predictions for the upcoming season. Bayern Munich was the unanimous favorite of Bundesliga coaches to repeat as champions. The most common reason given was the quality of Jürgen Klinsmann's squad. What … Continue reading
The fixtures for the opening day of the 2008/2009 Bundesliga season have been announced. All of these matches will be played on Saturday, August 16: FC Bayern v Hamburg Schalke v Hannover Wolfsburg v Cologne Bayer Leverkusen v Borussia Dortmund … Continue reading
The 45th season of the Bundesliga has come to an end with comparatively little drama or theatrics. Bayern all but guaranteed itself the title with a busy summer in the transfer market, spending 70 million Euros on Luca Toni (the … Continue reading
Borussia Mönchengladbach, winners of the second division Bundesliga this year and now newly promoted to the Bundesliga, has announced that the club will be playing friendlies in the United States in July. Gladbach will play against FC Dallas and Colorado … Continue reading


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LOS ANGELES (AP) — Oprah Winfrey says she's "sorry" that a media frenzy emerged after saying she experienced racism during a trip to Switzerland.
"I think that incident in Switzerland was just an incident in Switzerland. I'm really sorry that it got blown up. I purposefully did not mention the name of the store. I'm sorry that I said it was Switzerland," Winfrey said Monday night at the Los Angeles premiere of "Lee Daniels: The Butler."
"I was just referencing it as an example of being in a place where people don't expect that you would be able to be there," she continued.
In a recent interview with "Entertainment Tonight," Winfrey recalled a clerk at an upscale Zurich boutique refusing to show her a handbag. Winfrey said she was told she could not afford the $38,000 purse.
"I'm in a store and the person doesn't obviously know that I carry the black card and so they make an assessment based upon the way I look and who I am," said Winfrey, who earned $77 million in the year ending in June, according to Forbes magazine.
"I didn't have anything that said `I have money.' I wasn't wearing a diamond stud. I didn't have a pocketbook. I didn't wear Louboutin shoes. I didn't have anything," said Winfrey on the red carpet. "You should be able to go in a store looking like whatever you look like and say, `I'd like to see this.' That didn't happen."
Swiss tourism officials and the boutique owner apologized for the incident last week, but Winfrey insists there's no need.
"It's not an indictment against the country or even that store," she continued. "It was just one person who didn't want to offer me the opportunity to see the bag. So no apologies necessary from the country of Switzerland. If somebody makes a mistake in the United States do we apologize in front of the whole country? No!"
"The Butler," which opens Friday, documents the civil rights movement through the story of a butler who served in the White House for seven presidents.
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Friday, March 21, 2014
Stratford bounced back from a loss in Game 1 of the series to edge rival Goose Creek 7-6 in eight innings on Thursday night at SHS.
Jamison Mobbs drew a bases loaded walk to force in the winning run for the Knights, who lost 3-2 a night earlier.
Stratford trailed 5-1 entering the bottom of the third but eventually caught the Gators in the fifth inning. Each team scored a run in the sixth inning, setting the stage for another tight finish.
Ty'Reik Faulks led off the bottom of the eighth with a single to right field and eventually moved to second on a groundout. Two walks later - one intentional - the bases were loaded for Mobbs with two outs.
Gators reliever Sean Freeland missed the strike zone on a full-count pitch and Faulks came home with the winning run. It was similar to Game 1 when the Knights loaded the bases in the bottom of the seventh with one out but struck out twice, allowing Goose Creek to escape with the victory. Game 3 is set for Friday night at GCHS. Mobbs and Isaac Greer had two hits each for the Knights. Mobbs finished with three RBIs. Justin Walker threw all eight innings to earn the win, scattering 10 hits and three earned runs. He walked three and struck out two. Freeland, who threw 1.2 innings and walked three batters, took the loss. Chris Singleton started on the mound and threw four innings, giving up two runs on one hit. Michael Cedotal relieved in the fifth and surrendered four runs on five hits. He walked two and fanned one. Two of the runs he allowed were unearned. The Gators made four errors in the game to Stratford's one. Tyler Rio and Bryce Jonason had two hits and drove in two runs apiece for the Gators. Kyle Moore and Singleton each chipped in two hits and an RBI.
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Programme Topics
Principles of organic and biodynamic agriculture
Explores the history and key concepts, including the farm as a self-contained organism, the importance of bio-diversity, and the crucial role of the soil in land management.
Botany and plant observation
Develops the valuable capacity of plant observation for selected agricultural and horticultural crops, including weeds, and what they can tell us.
BioDynamic preparations
The background, composition and influence of these preparations; their making, storage and application.
The Living Soil
From soil formation to the development and maintenance of dynamic and living soil fertility including application of soil fertility enhancement principles to a variety of land management situations.
The wider cosmos' rhythmic influences on life and physical processes. How working with these influences enhances the development and living quality of soil, plants and animals. Understanding and working with the BioDynamic Calendar.
Introduction to and practical application of organic and biodynamic methods over a wide range of farming and gardening situations, for example:
Common horticultural field crops – site selection; cultivation methods; selection and propagation of varietals; crop rotations; and pest, disease and weed management.
Orchards and vineyards – design of site; varietal selection; understorey management; fertility; pest and disease management.
Animal Management
A holistic exploration of the nature and needs of farm animals and the appropriate management techniques to enhance their health, wellbeing and integration into the farm organism. Includes animal health and pasture management within NZ organic and biodynamic certification standards.
Farm Integration – Water and Trees
Particular emphasis is given to the qualities of trees and their place, uses and management within the farm and in the wider environment and the management of water in the farm environment.
Standards and Conversion
History and role of the major NZ organic and BioDynamic standards. The certification process and conversion towards sustainable organic biodynamic methods. The application and completion of comprehensive documentation for certification of a chosen property.


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These periodicals are available in print in the Maryland Room. Information about some may be accessed online by clicking on the links below.
- Catoctin History
Fall 2002 (Vol 1) - present.
- Frederick County Genealogical Society (FRECOGS) Newsletter
- Frederick Magazine (including predecessor, Diversions)
1985 - present
- Maryland Cracker Barrel
1972 - present, with gaps
Maryland Room also has print index for 1971-2004.
- Maryland Genealogical Society Bulletin
1965 - present, nearly full run with early gaps.
- Maryland Historical Magazine
1906 (Vol. 1) - present
- Maryland Life
2005 - Present
- Maryland Magazine
1968 - January 1996
- Western Maryland Genealogy
1985 (Vol. 1) - 2003 (Vol. 19)(Ceased publication)
The Frederick County Genealogical Society Newsletter, Maryland Genealogical Society Bulletin, Maryland Historical Magazine, and Western Maryland Genealogy are indexed in PERSI, the Periodical Source Index. PERSI can be searched online at any branch of FCPL through Heritage Quest.
Selected articles of local interest from Frederick Magazine and Maryland Historical Magazine are indexed by Maryland Room Staff. Selected articles from both publications can be found in the Maryland Room Vertical File.
The Maryland Room also maintains a file of regional local history and genealogy newsletters. Many of these are also indexed in PERSI. Not all of these newsletters are found in the FCPL catalog. Please call the Maryland Room to confirm holdings of a particular title.
We also recommend consulting the Maryland Humanities Council's online "Maryland History and Cultural Bibliography" to identify articles, and books, relevant to your study of Maryland's local history and genealogy. The bibliography includes citations in the periodicals listed above, although it is not a complete index to any of them. Read the site's essays that relate to the topics that interest you. Originally a product of the Maryland Humanities Council, it is now housed at the University of Maryland, College Park. Consult the FCPL catalog to confirm whether or not any books or articles named in the bibliography are held in the Maryland Room.
Items that are not owned by the Maryland Room can sometimes be obtained through direct loan or interlibrary loan. Please speak with Maryland Room Staff to learn more about these loan options. Please be advised that not all Maryland public libraries take part in the direct loan program and that interlibrary loan can often take several weeks. Keep in mind that most local historical societies, the repositories most likely to have many small run newsletters, as well as limited edition local and family histories, do not take part in any type of loan program.
The Maryland Room staff can also advise on institutions likely to own whatever items you are seeking. It may benefit you to consult our "Historical Research Institutions in the Frederick Area" .


text: Blogs Tim Walker 21 April 2012 Vogue Today So popular is the photographer Tim Walker that his talk today at the Vogue Festival, in partnership with Vertu, had to be done twice - and even then people were queuing a good hour before it was meant to take place. But it was certainly worth the wait. Walker and long-term collaborator - and former Vogue fashion director - Kate Phelan opened up their photo album and invited us into their magical fashion world.SEE TIM WALKER'S PHOTOGRAPHY ARCHIVE The pair spoke of the importance of casting the right girl (one that can put up with the harsh reality of a shoot, as it happens), the location, making someone part of that location and turning it into a fashion photograph, and how really it's all about going with the flow. "Things aren't how you imagine them. That's how you get those great pictures. With all the artifice in fashion, I'm always looking to put the humanity back into it," said Walker - going on to recall how he and Phelan's first Vogue shoot in 1997 went from being the idea of a family minibreak at Glastonbury to mud hell, and being pelted with it by angry festival-goers. The pictures, of course, still turned out beautifully. "When I go to a location, I spend time working out how to compress it really. It's very pre-considered but then you do let go on the day," said Walker - and that's how the magic happens.SEE TIM WALKER'S PHOTOGRAPHY ARCHIVE


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Find hotels & motels in Bloomfield using the list below. Find cheap and/or discounted hotel rates in or near Bloomfield, NY for your business or personal leisure travel. We provide the best Bloomfield New York hotel rooms. Review the Bloomfield hotel list below to find the perfect lodging. We also have a map of the Bloomfield hotels.
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More awards for The Gardens Group
Posted: February 10, 2014|
Poundbury Gardens, part of The Gardens Group, has picked up the IFSE award for Catering Excellence, Best Restaurant in the Garden Centre Category for The Engine Room restaurant.
The Gardens Group was awarded as overall winner in the GCA Christmas Awards 2013, and the Apple Tree Farm Shop got a special mention. Mike Burks, MD of The Gardens Group, comments: "It was a great day at the GCA conference last week. We went to collect the Christmas award for Castle Gardens and at the same time found at that The Engine Room had won best restaurant and The Apple Tree Farm Shop got a great mention too, so it really was great news all round. Congratulations and thank you to the whole team."
The Awards were announced at the 2014 Garden Centre Association held in Blackpool last week.


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Games in which my obsession knows no bounds
I love having an obsession with a game. I like a lot of games, but there aren't many games that I just don't stop playing.
This list comprises games that I feel provide endless fun and enjoyment to me. That's what's important, right? Me?


text: Prev | Next U.S. gymnasts, from left to right, Gabrielle Douglas, Alexandra Raisman, Jordyn Wieber and McKayla Maroney watch the screen moments before the results were declared during the Artistic Gymnastic women's team final at the 2012 Summer Olympics, Tuesday, July 31, 2012, in London. Team U.S. won the gold medal. (AP Photo/Julie Jacobson) Gallery: Women's gymnastics Aug. 01, 2012 @ 10:04 AM 2012/The Herald-Dispatch The U.S. women won the gold medal in the Olympics in London on Tuesday. ()


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Click Here to Watch the Whole Video in HD at Naked Frat House
College was never like this! Naked beer pong ends with big bros getting sucked off by pledges. Fall rush means hot college guys getting hazed before they're admitted to the fraternity.
Clayton Archer Had Been Obsessing About This Cute Guy At the Coffee Shop for Months Now. He's Been There Dozens of Times and Drank Way Too Much Coffee Already, It's Time for Him to Finally Talk to Him and Say Hi.
Pixels: 320X240 | Bitrate: 350K
Pixels: 640X480 | Bitrate: 700K
This back and forth shit is annoying. Show it in order.


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Benito Capellan is serving 134 days of "shock" time at the Lubbock County Detention Center. It is part of his ten-year probation sentence he received after killing German study abroad student Britta Schnider in a drunk driving crash back in April of 2012.
Click here to read the full story.
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Remote school still feels safe
Sevier County Schools have installed new video intercom systems in an attempt to make the schools safer, but will the extra line of security make a difference at such remote schools like Jones Cove Elementary?
A considerable drive separates Jones Cove Elementary from any law enforcement agency in the county, so response time would be slow unless a unit was already in the area, though Sevier County Sheriff Ron Seals did say units from his office regularly patrol all zones in the county.
In any case, Principal Kim Conrad assured that, in the event of an emergency, everyone at her school will be prepared.
"(Law enforcement) will get here as quick as they can, but we have our plan in place and our students are aware of what to do in an emergency," Conrad said. "I'm sure that we will do all we can do. We have a great emergency plan and I think we are prepared as best as we can be."
She said the school performed an emergency drill Thursday, "and the students did great."
The intercom system, she said, adds yet another layer of security to an already efficient emergency plan, and, at the very least, it makes everyone feel safer.
"I absolutely love it, and I already feel more secure," Conrad said. "The students and staff feel more secure because it's easy to monitor who's coming to the building."
The intercom system, which was installed at Jones Cove Elementary on Tuesday, allows all school doors to be locked at all times.
After this first line of security, the school's resource officer is next. His post is situated at the intersection of the main hallway and the short corridor leading to the front doors, so he can observe the front doors and both sides of the hallway.
The school's secretary responds to the intercom, and either unlocks the front door if there are no issues or, if there are, summons the resource officer to answer the door.
So far, there have been no intercom-related issues at Jones Cove Elementary. Conrad said it hasn't discouraged anyone from coming to the school, and even if parents are in a hurry, the intercom system won't be a huge hindrance.
"It's almost like ringing a doorbell," Conrad said. "You're talking about five seconds, so even if a parent needs to rush in, you're talking about five seconds."
The parents, in fact, "have been really supportive of the intercom system," Conrad said.
"I've heard nothing but good comments from parents," she said. "Parents, staff and even students have commented on how much more secure they feel."
Sandy Hook Elementary School also had a video intercom system, which had just recently been installed before the shooting, according to a CBS New York article. But a heavily armed person with intentions to kill likely does not plan to follow the rules. Adam Lanza did not use the video intercom system at Sandy Hook Elementary; he blasted his way into the building.
So will a buzzer system really prevent a disaster like the shooting in Newtown, Conn.? Conrad doesn't know for sure, but she is confident that her staff will do whatever it takes to keep the school safe.
"There's always going to be that threat; it's always there, but we will do all we can to prevent it," Conrad said. "You can always tweak your plan, and that's what we've been doing. We continue to update.
"Yes, someone can shoot the door in, but that does give you a little time, and that gives us extra time to respond."


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St. Lucie County Fair has some unique things to offer
Tommy Utts, of Port St. Lucie, strolled into an animal exhibit and forgot all about the zebra there because it was the Patagonian cavy from Argentina that caught his eye.
"It looks like an oversized bunny rabbit with long arms and long legs. I've never seen anything like it. It's the oddest looking creature I've ever seen," said Utts.
In the same exhibit, Dan Lecluse, also of Port St. Lucie, could not help but notice the Scottish Highlander cow corralled in the hay. "It reminds me of the wild beasts shown in the 'Chronicles of Narnia' movies. It's the weirdest animal I've ever seen in a live setting," said Lecluse.
Donna Higgins of Fort Pierce found it strange to find camel riding at the fair.
"I brought my grandchild to ride and she absolutely loved it," said Higgins.
Of course, everybody knows that staying on the mechanical bull for eight seconds using only one hand is impossible, but to win 200 dollars, it's worth a try.
So what else makes this 47th annual event so different? It's not the Ferris wheels, the carousels, the bungee jumping, the horse shows, the pizza or even the world's smallest woman. It's not the hypnotic show that kept hundreds under the spell of laughter for an hour. What is it?
The general manager of the fair, Jeanne Keaton of White City believes what sets the St. Lucie fair apart from the others is that everybody comes to see people they have known from years back.
"This is the biggest class reunion in the county and you don't have to go to a school to enjoy it," said Keaton.
She said the camaraderie of the patrons — along with some strange food — has kept the fair alive.
"You name it, it's fried," said Keaton of the numerous menu items, such as fried cookies, fried bubble gum, deep-fried Oreo cookies and even deep-fried Snicker bars, that brings people back to the fair.
Marian Crofutt of Palm City said, "I have never seen blue candied apples. It's crazy, but they remind me of the wild and zany world of the Smurfs."
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