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By Rudi WilliamsAmerican Forces Press Service
WASHINGTON, March 1, 2005 About 100 family members from as far away as California gathered at Arlington National Cemetery here on Feb. 27 to remember the more than 400 Americans who lost their lives during the Gulf War and Operation Provide Comfort.
The gathering marks the 14th annual remembrance ceremony, which is sponsored by the White House Commission on Remembrance with cooperation from the Kuwaiti Embassy. The ceremony is held each year in Section 60 of the cemetery, where many Gulf War dead are buried.
"This event is one of the most important I attend each year. Each time I find myself deeply moved by the event itself and by the hard work sustaining it," Kuwaiti Ambassador Sheik Salem al-Sabah said during his keynote address.
The ceremony was highlighted by U.S. Army Band soloist Staff Sgt. Steve Cramer singing "Morning Has Broken" and "On Eagle's Wings," accompanied on the piano by Sgt. 1st Class Faffi Kasparian.
Family members of Gulf War casualties led the Pledge of Allegiance, and representatives from each military service read the roll call of families.
Kuwaiti children, escorted by representatives of countries who suffered casualties in the Gulf War, placed flags on a remembrance panel. Members of the Army, Air Force and Marine Corps Junior ROTC and Navy Sea Cadets placed roses at gravesites of those killed during the war.
Children, nieces and nephews of Gulf War casualties placed white roses at a memorial stone that reads: "They served with honor. The Persian Gulf 1990-1991. To the brave hearts who gave their lives. May we all know the peace for which they died. Dedicated by No Greater Love, Feb. 25, 1992."
An Army Band bugler and drummer decked out in Continental Army uniforms played "Taps" following the remembrance wreath laying.
"In our fast-paced society, young people sometimes say events less than 20 years ago are ancient history," Sabah said. "This happens far less in my part of the world, since Middle Easterners are rarely accused of having short memories."
He said Arabs think along the lines of William Faulkner, who wrote, "The past isn't dead. In fact, it isn't even past."
"As even casual visitors will tell you, when you make friends with someone from the Arab world, you probably have a new friend for life," the ambassador noted. "Friendships, once made, are deeply cherished.
"Nowhere is this more true than in the case of Kuwait's liberation," Sabah said. "In 1991, America led the international coalition that liberated Kuwait, and the Kuwaiti people will never -- can never -- forget it. Kuwait's government and its people will always remember how the U.S. armed forces reversed Saddam Hussein's aggression and restored Kuwait's rightful sovereignty."
Sabah noted that America and Kuwait were friends and partners before the 1991 liberation. "The Gulf War," he said, "a conflict in which Americans and Kuwaitis fought alongside each other and left blood on the battlefield propelled the U.S.-Kuwait relationship to a whole new level."
He said this was symbolized last year when the Bush administration designated Kuwait as a major non-NATO ally.
"Today, of course, we gather to honor those who served in the 1991 Gulf War and did not return," the ambassador continued. "We also gather to honor the families that loved and supported those who answered their country's call."
Sabah said it's chilling to imagine what the world might have been like if the U.S.-led coalition had not reversed Iraq's invasion of Kuwait.
"If Kuwait had been annexed and Iraq's ambitions left unchallenged, Saddam Hussein's million-man army would have likely continued its conquests," he noted. "The world's inaction in the face of such blatant aggression would have inspired other aggressors and fostered global anarchy.
"In this context, American sacrifices stopped the emergence of a darker, more dangerous world where 'might makes right' and international law is a nothing but a paper tiger," Sabah said.
He said that Saddam remained dangerous when the Gulf War's major land campaign ceased. "This required the continuing presence and vigilance of the U.S. military to ensure the region's stability and security," the ambassador said.
Despite being under America's watchful eye, Saddam's defiance continued throughout the 1990s. Then, in the post-Sept. 11 world, his noncompliance with the will of the international community had to be addressed, the sheikh noted.
Sabah went on to say that Saddam posed an ongoing challenge and the world community faced a choice. "I could either downplay the dangers or face them squarely," he said. "America's leadership and armed forces faced this challenge. And again, more sacrifice was required."
With Iraq's liberation, he said, a central Arab country has rejoined the international community. The Iraqi people can now decide their own destiny. With the completion of recent elections, this process is under way, the ambassador added.
"American leadership and sacrifices have restored freedoms to long denied Iraq's proud and gifted people," Sabah said. "But what sadly cannot be restored are the sacrifices made on behalf of these freedoms. Every sacrifice is important, but it's particularly tragic when someone pays the ultimate price while serving their country. And nothing anyone does or says can bring back a loved one who is no longer with us. But what we can do is honor the memories of the fallen.
"Let me assure you that your loved ones are remembered not only by Americans, but also in my country," Sabah said. "On behalf of Kuwait's people and government, I extend our deepest and most heartfelt gratitude."
Related Articles:Families of 1991 Gulf War Casualties Honored


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subset: commoncrawl


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Yay! More Monsters, Inc.! The prequel film, featuring how Mike and Sully became best friends, will be called "Monsters University" and is slated to be released 6/21/2013. I'm so excited for this and hope it's as funny, or even funnier, than the first movie! There were four trailers released, each with Mike saying something different in his sleep. This one is my favorite:
You are here: Home / For Everyone / Monsters University Debut Trailer
About TerriAnn van Gosliga
TerriAnn van Gosliga is the main writer at Cookies & Clogs and Driving Mamas. Born & raised in the SF Bay Area but loves to travel. She's been married to her best friend for 14 years, homeschools her 13-year-old daughter, and has an accident-prone lab mix dog.


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Spearfish, SD Antique Shop
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As you travel through life, angels can be your guardians and companions, whether you need comfort, guidance, or protection.
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An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
1. A computer system comprising:
a processor;
a memory system including a cache;
at least one bus coupled to the memory system and to the processor; and
an optimization logic that predicts a probability of an event in a memory subsystem wherein the optimization logic enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.
2. The computer system of claim 1 wherein the optimization logic comprises:
a plurality of comparators; and
a plurality of counters for tracking parameters coupled to the plurality of comparators which together predict the probability of an event in the memory subsystem wherein the parameters tracked include bus utilization and hit/miss occurrences for a portion of the memory subsystem.
3. The computer system of claim 1 wherein the memory subsystem comprises a main memory and the optimization logic dynamically enables a memory access mode to be one of page mode and single access mode base on a predicted probability of a second event.
4. A computer system comprising:
a processor;
a memory system;
at least one bus;
means for tracking behavior of a memory subsystem;
means for predicting the occurrence of an event in the memory subsystem based on the tracked behavior; and
means for dynamically adjusting a mode of operation of the memory subsystem responsive to the predicting means wherein the means for dynamically adjusting enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level, and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.
5. A method of dynamically adjusting characteristics of a computer system having a processor coupled to a memory subsystem including a cache, comprising the steps of:
recording information of prior activity of the memory subsystem;
predicting a probability of a cache hit on a next transaction with the cache;
enabling a tag array if the probability of a cache hit reaches a predetermined level;
enabling a data cache if the hit probability reaches a second predetermined level; and
enabling the data cache only if a hit actually occurs if the hit probability has not reached the second predetermined level.
6. The method of claim 5 wherein the memory subsystem comprises a memory organized in pages and wherein the method further comprises the steps of:
predicting a probability of a memory page hit on a next transaction; and
enabling RAS active mode if the probability of a page hit exceeds a predetermined level.
7. The method of claim 6 wherein the processor has an internal cache, and wherein the method further comprises tracking a ratio of bus cycles to bus cycles during memory accesses.
8. The method of claim 5 wherein the system has a plurality of levels of cache and wherein the method further comprises the steps of:
tracking a ratio of bus cycles to bus cycles during which a particular level of cache is accessed;
tracking a ratio of cache hits to cache misses for the particular cache level; and
setting the mode of the particular cache level operation based on the ratios.
9. The method of claim 5 wherein only a bank of the data cache containing the information is enabled responsive to a cache hit.
10. In a computer system having a CPU coupled to a memory by a bus, an apparatus for optimizing characteristics of a memory subsystem comprising:
means for recording behavior of the subsystem; and
means for dynamically enabling portions of the memory subsystem in response to the recorded behavior wherein a tag cache is enabled if the recorded behavior indicates a first probability of an event, a data cache is enabled if the recorded behavior indicates a second probability of the event and the data cache is only enabled if the event occurs if the recorded behavior does not indicate the second probability of the event.
11. The apparatus of claim 10 wherein the means for recording comprises:
means for tracking the ratio of bus cycles to bus cycles during which a portion of the memory subsystem is accessed.
12. The apparatus of claim 10 wherein the means for recording comprises first means for predicting a probability of a cache hit; and wherein the means for dynamically enabling comprises means for dynamically setting a mode of cache operation responsive to the predicting means.
13. The apparatus of claim 12 wherein the means for dynamically enabling further comprises:
second means for predicting a probability of a page hit in main memory; and
means for dynamically setting a mode of main memory operation responsive to the predicting means, second predicting means, and the tracking means.
14. The apparatus of claim 13 wherein the first and second predicting means comprise up-down counters coupled to comparators.
15. The apparatus of claim 12 wherein the dynamically setting means further comprises
first means for enabling the tag cache; and
second means for enabling the data cache.
16. The apparatus of claim 15 wherein the second enabling means can independently enable individual data arrays within the data cache.
The invention relates to power management in computer memory subsystems. More specifically, the invention relates to a method for intelligently balancing between the power consumption and performance of a computer memory subsystem.
For many years, memory caching has been a common way to improve a computer's performance characteristics. A cache memory is a block of very fast local storage memory usually made up of static RAM (SRAM) used by a microprocessor to hold copies of frequently used data or code. Modem computer systems typically contain one or more level of cache memory, which exist for the sole purpose of increasing the performance of the computer system. For computers with more than one level of cache memory, the level one (L1) cache memory is logically closer to the CPU than the second level cache memory (if it exists); the level two (L2) cache memory is logically closer to the CPU than the third level cache memory, etc. In most modem microprocessors, the L1 cache memory is typically on the same integrated circuit as the microprocessor, and is normally smaller and faster than an L2 cache memory, which may be located on a separate integrated circuit
In systems employing a level one cache memory, the primary level one cache memory filters most memory references from ever being seen by the rest of the memory subsystem. The size of the level one cache memory is limited (especially in cases where it is integrated with the CPU core) by silicon cost, electrical loading constraints, and available chip space. Thus, larger programs frequently result in CPU memory requests that must be serviced by the remainder of the memory subsystem. When a memory reference that cannot be serviced by the L1 is initiated, the L2 tag array identifies whether the data or code requested is available in the L2 data cache memory. When an L2 cache memory hit occurs, the memory reference is satisfied by the L2 cache memory data array. If an L2 cache memory miss occurs, main memory is accessed. Without a second level of caching, all memory accesses that result in L1 cache misses would go to main memory, which is quite slow in comparison with modern CPU execution speeds. By employing a second level of caching larger than the first, performance is significantly improved by reducing the number of accesses to main memory.
To minimize the time required to make the hit/miss decision, the memory chips comprising the cache memory tag array are kept in an active condition by holding the chip enable signals in the active state. In a similar manner, the chip select signals for the cache memory data array are activated immediately after a memory access is initiated, without waiting for the hit/miss decision from the tag array/cache memory controller. Power consumption when the chips are enabled is an order of magnitude higher than when the chip is not enabled for typical SRAMs, thus, maintaining the chip in the active condition results in a significant power penalty. It is important to note that some multi-way associative cache memory designs only activate a single cache way for each cache memory access. Only enabling one cache way lowers the total power consumed by the data cache memory array somewhat, since not all data cache memory chips are activated for every cache memory access. However, these designs are static in that they always wait to determine which way of the cache memory is being accessed before activating the data cache memory chips. Since this decision takes time to make, it impacts the access time requirements and, therefore, the performance of the cache memory chips.
The main memory is usually implemented using DRAMs. Accessing a specific memory location within a DRAM usually requires generation and presentation of the row address, a wait period for this address to be latched by the DRAM, and then presentation of the column address. Because providing the row address and waiting wastes a significant amount of time if multiple sequential accesses to a single row are requested, prior art systems employ page access mode wherein the row address strobe (RAS) is held active. Maintaining RAS active tells the memory that until RAS is de-asserted, no other row will be accessed, thus allowing accesses to multiple columns within the row at a significant time savings. Since this mode requires more of the DRAM chip to remain active, it also results in higher power consumption, as with SRAM, DRAM requires more power in the active state.
An alternate system employed where power consumption is a major concern is to deassert RAS after each access, effectively assuming that there will be no additional main memory accesses for some extended time period. While this may be an effective strategy for application workloads which have few accesses to main memory, it can significantly increase both the execution time and power consumption of applications which exhibit frequent main memory accesses. Each time the RAS signal is de-asserted, there is a set time period (RAS pre-charge time) which must elapse before RAS can be re-asserted. It also takes time to generate the row address and assert RAS. The combination of these two time penalties may result in significant degradation of performance for programs that have many successive main memory accesses. Repeated assertion and de-assertion of RAS can also result in a power consumption penalty, since more power is required to assert RAS separately for two cycles than to assert RAS once and hold it active for both cycles.
Significantly, the above prior art systems use cache memory and enhanced DRAM capabilities to improve performance without regard for power consumption. In view of the foregoing, it is desirable to find a way to improve the power consumption characteristics of the memory subsystems without significantly degrading performance.
The instant invention provides an apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
FIG. 1 is a block diagram of prior art systems employing one or more levels of cache memory.
FIG. 2 is a block diagram of a prior art system employing a cache memory including a memory controller logic.
FIG. 3 is a block diagram of one embodiment of a computer system incorporating the invention into the memory controller.
FIGS. 4a-c are state diagrams corresponding to selected system events tracked by the present invention.
FIGS. 5a-c are block diagrams of one embodiment of counters which can be employed in the invention to track the relevant events.
FIGS. 6a-c show modular incorporation of the invention in various system configurations.
FIGS. 7a-c are timing diagrams showing cache memory activity in active and event driven modes that occur in one embodiment of the present invention.
FIGS. 8a-b are matrices showing cache and main memory modes of operation based on tracked parameters in one embodiment of the invention.
FIGS. 9a and b are sample tables of the modes in which the invention might operate the memory subsystem for every state depicted in FIGS. 4a-c.
The present invention provides a method and apparatus for dynamically managing the power/performance characteristics of memory subsystems. For purposes of explanation, specific details are set forth to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art that the invention may be practiced without these details. Moreover, well-known elements, devices, process steps and the like are not set forth in order to avoid obscuring the invention.
FIG. 1 shows a prior art system implementing one or more levels of cache memory. Specifically, CPU 1 communicates with the first level of cache memory 3 via CPU local bus 2. The first level of cache memory 3 then communicates with a subsequent cache memory 5 via the cache local bus 4. Each level of cache memory communicates with the cache memory logically below in this same way until the final level of cache memory 6 then communicates with main memory 8 via the system bus 7. The prior art shown in FIG. 1 utilizes the cache memory subsystem as a means of enhancing speed of memory access, and makes no attempt to control the power consumption of either the cache memory or any memory subsystem.
FIG. 2 shows a prior art system employing a cache memory. More specifically, FIG. 2 shows the internal workings of a cache/memory controller situated between CPU 29 and main memory 25. The cache memory consists of a cache data RAM 21, a cache tag RAM 22, and cache control logic 27. When the CPU 29 requests data, the cache control logic 27 compares the address of the data in main memory which is provided by the CPU 29 along address bus 26 with the addresses stored in the cache tag RAM 22, such addresses corresponding to the data in the data cache memory 21. Based on this comparison, hit or miss decision 28 is made. If there is a cache memory hit, the requested data is sent from the cache data memory 21 along data bus 23 to CPU 29, and the cache memory controller terminates the main memory access which was simultaneously initiated by providing the address along address bus 26 which communicates with main memory 25. Conversely, if a cache memory miss occurs, the memory access proceeds uninterrupted and the main memory 25 provides the data to the CPU 29 along data bus 23. Further, depending on the cache memory replacement algorithm, such data may be added to that stored within the data cache memory 21. Significantly, the above routine applies regardless of the number of layers of cache memory between the CPU 29 and main memory 25.
FIG. 3 shows a computer system incorporating the instant invention into the memory subsystem controller 30. In the instant invention, the CPU 29 provides an address strobe 31 and a memory/IO access signal 32 to power optimization logic 40 of the memory controller 30. The power optimizing logic 40 is thereby able to track the total number of clock cycles elapsed versus the number of clock cycles in which off chip memory accesses occur, including accesses of either cache memory or main memory. Further, cache control logic 27 provides the hit and miss decision 28 to the power optimizing logic 40. The power optimizing logic 40 uses this information to predict the likely target of the next CPU memory request. Based on this algorithm, the power optimizing logic 40 enables or disables the chip select 39 of the cache tag RAM 22, as well as the chip select 36 of the cache data RAM 21. Finally, the DRAM controller 34 of the memory controller 30 provides the DRAM page hit and miss information 35 to the power optimizing logic 40. In view of this and the other above mentioned inputs, power optimizing logic 40 asserts or de-asserts the row address strobe (RAS) 37 (which is essentially the chip select for the DRAM), thereby keeping the DRAM's in the page mode (RAS asserted) or single access (RAS de-asserted) mode.
Now referring to FIGS. 4a-c which are state diagrams reflecting the tracking of three types of events: CPU bus utilization, cache memory hit probability, and probability of a page hit in main memory, respectively. Based on the state of these probabilities, the tag and data cache memories will be either in an "active mode" or an "event driven mode", and the RAS will be either active or inactive. Active mode refers to the condition where the necessary control signals are held continuously in the active state, and the corresponding memory component is in a high state of readiness. This effectively reduces the time required to accomplish an event, since there is no delay in driving these signals active. Event driven refers to the condition where the necessary control signals are not held active, but rather they are asserted and de-asserted as necessary based on the power/performance requirements of the memory subsystem. As conditions change, the power optimizing logic will automatically adjust the subsystem component modes to achieve the preferred power/performance trade-off.
In the active mode, the chip select for the tag cache memory is always enabled, and the chip select for the data cache memory is enabled immediately upon recognition of a memory cycle (i.e., before the hit/miss decision is made). While this enhances performance, it comes at the power penalty discussed above in connection with prior art systems. It is, of course, possible and, as discussed below, in some cases desirable to have the tag cache memory in an active mode and the data cache memory in an event driven mode.
If either the tag or data cache memory is in event driven mode, the chip select of the respective cache memory is disabled until a triggering "event" occurs. In the case of the tag cache memory, the event is any memory access (e.g. cache memory or main memory access). In the case of a data cache memory, the event is a cache memory hit in the particular data array. Since cache memories are implemented in SRAM, deasserting the chip select signal reduces power consumption an order of magnitude over the power consumed in cases where chip select is always asserted.
It will be noted that the page access mode of the DRAM in main memory functions similar to that of a cache memory. Thus, the instant invention is envisioned to include operating the DRAM in either event driven mode or active mode with the power/performance characteristic being optimized based on tracked criteria. An access to the main memory DRAM requires a row address and a column address. Each time RAS is asserted, the CPU must wait while the DRAM selects the correct row before the column address strobe (CAS) can be asserted and the data retrieved. This is known as the RAS access time. In the page access DRAM mode, RAS remains asserted between accesses to the DRAM. This improves performance where multiple memory accesses result in page hits because the column address can be directly applied to the DRAM. However, performance degrades in the event that accesses commonly result in page misses because of the time penalty required to de-assert RAS, wait out a RAS precharge time period, and then initiate a RAS/CAS access. It should be clear that the main memory power/performance trade-off is not dependent on implementing main memory in DRAM; any memory system having distinct levels of power consumption can be optimized employing the instant invention.
As a further consideration, continually asserting RAS represents a substantial power drain. However, there is also a power penalty paid if RAS is toggled with unnecessary frequency. This power penalty is the result of the fact that it requires more power on a clock by clock basis to assert RAS than to maintain RAS active once asserted. Therefore, in determining whether to have RAS active or inactive, one must evaluate the frequency of page hit, the frequency of off-chip memory access, as well as the system parameters which contribute to precharge penalty and the power penalty of switching discussed above. For example, if the power cost of running the RAS active is I unit/cycle, and the cost of asserting is 10 units, assuming a page hit is likely, it would be desirable from both a power and performance perspective to leave RAS active if a main memory access is likely to occur within the next 10 cycles. Conversely, if a main memory access is not likely to occur within the next 10 cycles, power can be saved by de-asserting RAS at a performance cost equal to the difference between the RAS access time and the CAS access time.
As mentioned earlier, three parameters, namely, Bus Utilization (BU), cache memory hit rate probability and DRAM page hit probability are necessary to design the power optimizing logic. The parameters can be tracked by using simple state machines, such as, for instance, those shown in FIGS. 4a to 4c. These state machines are used to predict the likely result of future accesses. FIGS. 4a to 4c illustrate state machines that track bus utilization, cache hit probability and the DRAM page hit probability respectively. Each one shows four states. For BU they are strongly idle, weakly idle, weakly busy, and strongly busy. For the cache memory and DRAMs they are strongly hit, weakly hit, weakly miss and strongly miss. The number of states may be arbitrarily selected based on the desired level of granularity in the parameter tracking. However, for the sake of illustration, the selection of four states is desirable. The strong idle state signifies that very few accesses are being made to the memory subsystem. The reason may be that the CPU itself is idle or the memory level (or levels) before the current one, if any, in the memory hierarchy is fulfilling most of the CPU's requests. The weakly idle state means that the number of accesses has increased but still are less than some predetermined threshold. The weakly busy state means that the number of accesses are now substantial but are not in a predetermined peak region yet. Lastly, the strongly busy state suggests that the number of memory accesses have entered the peak region. Selection of the transition points between states is discussed more fully below. The same reasoning applies to both the cache Hit/Miss situation and the DRAM Page Hit/Miss situation.
Each of these state machines are driven by a simple dedicated up/down counter. These counters are illustrated in FIG. 5a to 5c. The BU counter counts up for every bus clock during which an access is occurring to the associated memory sub-system. The idle bus clocks drive the counter down. The Cache Miss counter counts up whenever an access results in a miss to the cache memory and counts down if an access results in a cache memory hit. The DRAM Page Miss counter counts up if a page miss occurs and counts down if a page hit occurs.
It is desirable to use saturating counters. The upper limit on the count is determined by the number of bits used in the counter. For example a 4-bit counter will count from 0 to 15 and will saturate at 15 if counting upwards and at 0 if counting downwards. The output count of the counter is used to determine the current state of the state machines. The width of the counters (number of bits used) can be arbitrarily selected based upon different factors such as maximum access time and the workload characteristics on a given system. Transition points for the state changes (the count at which a particular state transition occurs) in the state machines are also decided by the type of power/performance tradeoffs desired in a particular system. For example, it may be decided based on the desired performance/power tradeoffs that if 70 to 100% of accesses result in the cache memory hit, then it is called strongly hit region, 50˜70% being weakly hit, 30˜50% being weakly miss and 0˜30% of hit rate being a strongly miss region. An example partitioning is discussed more fully below in connection with FIGS. 8a and b. It should also be noted that the state transitions on opposite direction between a pair of states need not occur at the same count but can occur on different counts, thereby introducing`hysterisis`. A person skilled in the area of instant invention should be able to comprehend the benefits of hysterisis.
Thus, a state machine and its corresponding counter make a module that monitors the desired parameter. These modules are illustrated in FIGS. 6a-c as circles 60-62. These figures show three type of systems: FIG. 6a is a generic multiprocessing system, FIG. 6b is a single CPU system with a serial cache memory and FIG. 6c shows a single CPU system with a parallel cache memory. The modules for measuring Bus Utilization are named as BUn, where n is a number and are connected to the bus they are monitoring, the ones for Cache Hit/Miss Probability are named CHMn and those for DRAM Page Hit/Miss are PMHn and these are also shown connected to their respective part of the memory hierarchy (cache memory or main memory).
In the FIG. 6a, each of the two CPUs have a BU module on its local bus which is also the bus for cache memory interface. Each of the cache memories have their own module for tracking Hit and Miss. The data from the BU1/2 and CMH1/2 are used for tuning the power/performance characteristics of the cache memories 1/2. The way to do this is explained later. This system has two main memories. Each one is separated from the system bus by buffers. Each one needs its own modules to track the BU and the Page Hit/Miss rate. For example, BU3 tracks the Bus Utilization at the port of Main Memory 1 and the PHM1 tracks its Hit/Miss rate. The data from these two modules is used to tune the power/performance characteristics of Main Memory 1.
FIG. 6b shows a single CPU system having a serial cache memory. The memory accesses for cache memory are tracked by BU1 and CHM1, while that for the Main Memory is tracked by BU2 and PHM1 modules. Note that if there were more levels of cache memories in this system, each cache memory level will have a BU and a CHM module. It should also be noted that each level in the memory subsystem, whether it is a cache memory or DRAM memory, can be independently power optimized with the help of the data tracked by its corresponding pair of modules.
FIG. 6c shows a cache subsystem in parallel with main memory. In this case, the main memory and the cache memory attach to the same physical bus. We can still have two BU modules where the BU1 will track total bus utilization and BU2 will track only the part of bus utilization that is used for accessing main memory. This can be achieved by simply enabling the upward counting of BU2 with a miss signal from the cache memory. An alternate way is just to have BU1 and not have BU2 at all. In this case, the bus utilization for the main memory port can be deduced from the BU1 count and the cache memory miss rate counted by CHM1. This saves one module (BU2) at the cost of increase in complexity of logic for optimizing the main memory; since three parameters: BU1, CHM1 and PMH1 must now be considered instead of two (BU2 and PMH1).
Management of cache memory power consumption is performed by selection of a high performance-high power mode or of a moderate performance-low power mode. The modes of operation are called "Active Mode" and "Event Driven Mode". FIGS. 7a-c are timing diagrams which will clarify the distinction between Active Mode and Event Driven Mode in the context of the Tag Cache memory and Data Cache memory. Event Driven Tag Cache memory is shown in FIG. 7a where the Tag:CS signal is asserted after the Address is decoded and determined to be a possible Cache memory access. Event Driven Data Cache memory is also shown in FIG. 7a where the Data:CS signal is asserted after the Tag:H/M (Hit/Miss) signal indicates an Cache Hit. Note that for Uncacheable cycles, neither Tag:CS nor Data:CS are asserted, thus saving power.
FIG. 7a shows the power consumption when both the Tag and Data cache memory are Event Driven. Note that the power consumption approaches zero when the chip select signals are inactive. When the memory bus is inactive (or idle), power use is minimized. However, performance may degrade in this mode as the Tag look up and Data access are serialized. FIG. 7b shows the power consumption when the Tag cache memory is kept Active, but the Data cache memory is Event Driven. There is good performance and good (but not optimal) power savings, the primary power savings benefit comes from the fact that the Data Cache memory is not accessed during Data Cache memory misses. FIG. 7c shows the best performance as both the Tag and Data Cache memories are always active. However, this solution has the highest power consumption as the Tag cache memory and Data Cache memory are both accessed in parallel before the Tag Cache memory "hit/miss" decision is made. The switching between modes can be performed by a variety of logic implementations added to existing memory control logic. From this disclosure, such would be clear to one of ordinary skill in the art
The above discussed systems show just some of the many possible ways to monitor the required parameters for memory subsystem power/performance optimization. For the sake of illustration, assume that the State Machines in FIGS. 4a-c are implemented using 4-bit saturating, up/down counters. Since a two dimensional matrix is formed using pairs of state machines, a 16�16 matrix describes the 256 possible combinations. FIGS. 8a-b retains the resolution of the 4-bit counters and partitions the matrix in a nonsymmetric fashion. Selection criteria of the modes of operation within each cell of the matrix is a function of the workload profile and decision to optimize for either power savings or performance. Note that the use of 4-bit saturating up/down counters is merely a simple and inexpensive technique of determining probabilities based on past history, yet provides ample granularity for a wide variety of applications. Other techniques to record recent histories and to determine probabilities can be used without departing from the scope or contemplation of the instant invention.
FIG. 8a describes one way of partitioning a Cache memory matrix: Cache memory Utilization and Cache memory Hit probabilities have both been partitioned into four categories, yielding a matrix of 16 cells. Each cell of the matrix represents a workload as determined by the statistics of recent Cache memory history. Based on that workload, the invention dynamically configures the operating algorithm of the Cache memory subsystem. When there is a "Strongly Busy" and "Strong Hit" condition, the implication is that there are many Cache memory requests and that there is a high probability that the requests will be serviced by the Cache memory. Under these conditions, it is advantageous to configure the Cache memory for high performance. Similarly, when there is a "Strongly Busy" and "Strong Miss" condition, the implication is that there are many Cache memory requests but that there is a high probability that the requests will be serviced by other memory agents. Under these conditions, it is advantageous to keep the Tag Cache memory Active (to quickly determine Cache memory hit/miss) and keep the Data Cache memory in the Event Driven mode. This allows fast Cache memory hit/miss determination and at the same time does not unnecessarily consume power by the Data Cache memory. Within the matrix, there are a pair of letters: the first of the pair (on the left) represents the operating mode of the Tag Cache memory and the second of the pair (on the right) represents the operating mode of the Data Cache memory. An "A" represents Active Mode and an "E" represents Event Driven Mode.
FIG. 8b describes one way of partitioning DRAM matrix: DRAM Utilization and DRAM Page Hit probabilities have both been partitioned into four categories, yielding a matrix of 16 cells. Each cell of the matrix represents a workload as determined the statistics of recent DRAM access history. Based on that workload, the invention dynamically adjusts the operating algorithm of the DRAM memory subsystem. When there is a "Strongly Busy" and "Strong Page Hit" condition, the implication is that there are many DRAM requests and that there is a high probability that the requests will be serviced from the current DRAM memory page. Under these conditions, it is advantageous to configure the DRAM controller to be in the Active Page Mode. Similarly, when there is a "Strongly Busy" and "Strong Page Miss" condition, the implication is that there are many DRAM requests but that there is a high probability that the requests will be serviced from another DRAM page. Under these conditions, it is advantageous to deassert the DRAM RAS# signal as soon as possible and initiate the "DRAM RAS# Precharge cycle. This allows optimizing the DRAM memory subsystem for performance. "RA" represents RAS# Active Mode (RAS# is kept active until a DRAM Page Miss occurs) and RA# represents RAS# Inactive Mode (RAS# is deasserted after every DRAM Access).
Selection of the operating modes for each cell is based on power/performance trade offs of existing memory technologies. The invention manages dynamic selection of the various operating modes based on real time workload statistics. Accordingly, the operating mode may be adjusted in response to each bus cycle. FIGS. 9a-b show one possible selection of modes for both the Cache memory and DRAM matrices. There are two examples given: one for a performance oriented system and one for a power savings conscious system. It is envisioned that a user would be able to choose between performance oriented and power savings oriented optimizations (e.g. close calls in the trade-off scheme will fall toward selected orientation).
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Therefore, the scope of the invention should be limited only by the appended claims.
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The landmark Supreme Court decision in Brown v. the Topeka Board of Education dealt with a school system in Kansas, but it affected the entire country, including southern Nevada. Former Senator Richard Bryan explains.
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What You Should Know
|Star Rating
|2 or More Patented Ingredients
|Less Than $5 Shipping
|Trial Offer
|Rejuval Skin (2014 Editors Choice)
|Facial Toner
|IQ Derma
|Daintree Naturopathic Skin
|Meaningful Beauty
Daintree Naturopathic Skin is an Australian cosmetic cream that is claimed to be the premier skin care product on the market. The company was launched in Australia in 1998 after solid research and development and claimed to be based on the findings of a combined team of Naturopaths, Microbiologists, Chemists and Botanists, all under the leadership of CEO and Founder Dr Robert Ippaso.
Daintree Naturopathic Skincare products are derived from the natural and pristine environment of the Daintree rainforest in Northern Queensland. It is claimed that this part of the world has some of the most diverse ecosystems, and contains plant life that may be helpful to treat skin disorders. The majority of Daintree Naturopathic products can be used on all types of skin. The products are heavily marketed as anti-aging agents and are said to reduce fine lines and wrinkles. Daintree markets its anti-aging creams in a five step skin care program. The program includes a day cream, a night serum, an eye and lip serum, a cleanser and a renewal cream. The end result is a skin that is healthy, radiant and has a luminous glow.
Product Details
The line of Daintree products include Balancing Softening Toner, Tinted Moisturizer, Deep Cleansing & Hydrating Miracle Facial Mask, Rich Moisturising AHA Creme, De-Line & De-Puff Soothing Eye Gel, Tonic Express 3-in1, Purifying 'Earth Mineral' Facial Mask, Healing/Hydrating Facial Moisturizer, Essential Multi-Defence Day Creme, Performance Eye Make-Up Remover and Night Therapy Creme.
Daintree products seem to feature the following ingredients in their formulations: Antioxidant Facial Exfoliator which contains Tropical Sugar Cane, Vitamin C, Vitamin E and Xanthan Gum; Milk Cleanser for Sensitive Skin, which may contain Jojoba Oil and Sesame Seed Oil; and Foaming Cleanser, which may contain Vegetable Glycerin and Fruiting Cassia.
The Good
- Daintree makes a variety of cosmetic products for different purposes.
- Limited ingredient list indicates all natural products.
The Bad
- No website.
- Expensive.
- No refunds.
- No testimonials.
- No complete list of ingredients for each product.
- May be difficult to get a hold of in the US.
The Bottom Line
To be fair to the Australian company, it is hard to market a product from Australia to North America. However, with the advent of the internet, Daintree could easily have created a website. The limited list of ingredients does not indicate anything special in Daintree products. There is no ingredient in the formulation that is known for its anti-aging effects. The products are pretty expensive and only available through some online dealers. For most consumers, it is hard to recommend Daintree products because the company has simply failed to list its ingredients. In fact, it appears that the company is not interested in promoting its product in North America. Further Daintree expects all consumers to buy the 5 product skincare program to achieve the best cosmetic results. This can be prohibitively expensive. There are many other decent and relatively inexpensive products available in North America that feature excellent ingredients to reverse aging. Until Daintree makes an effort to make a website and tell the consumer what the products contain, the America-based consumer is better off avoiding this brand of cosmetics.


text: Clearwater Christian College senior Tyler Spraul from Annandale, VA, was recently named the 2010 National Christian College Athletic Association (NCCAA) DII National Player of the Year for mens soccer. As team captain, Tyler was a key player for Clearwater, leading the Cougars to their 2nd straight NCCAA DII National Championship. During the three-day event held in Kissimmee, Florida, Spraul led the Cougars to 3 wins over Dallas Christian College, Providence College, and Ohio Christian University. He scored 3 goals and had an assist in the first round win over Dallas and scored the game-winning goal in the first half of the 2-0 win over Ohio in the championship match. Tyler was also named NSCAA/NCCAA 1st Team All-American, NCCAA South Region Player of the Year, and a Scholar Athlete. He led the Cougars in scoring with 18 goals on the season along with 4 assists. This is Sprauls second straight season to win 1st Team All-American, South Region Player of the Year, and Scholar Athlete. He also scored the winning goal in overtime in the 2009 National Championship win over Southeastern University. Tylers coach, James Whitaker said Tyler is well-deserving of this special honor. He has been a team leader and has been the backbone for both of our championship teams. He is one of the hardest working players Ive been around and a great example of what a Christian student-athlete should be about. Spraul is the son of Mike and Darla Spraul from Hendersonville, North Carolina and a 2007 graduate of First Baptist Christian School in Waupaca, Wisconsin. Print Article


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Budget public hearings in Bostic and Ruth
RUTH — Town Commissioners in Ruth are expected to adopt the proposed 2014-15 fiscal year budget when it meets at 5 p.m. Monday at town hall. The adoption will follow a public hearing on the budget.
There is no tax increase recommended.
The tax rate is $.26 per $100 property valuation.
No tax increase recommended
BOSTIC — Bostic Town Council will adopt its 2014-15 fiscal year budget when it meets at 6 p.m. Monday. The proposed budget reflects no tax increase.
The tax rate is $.26 per $100 property valuation.
The total budget is $760,051 and the public will have an opportunity to address the budget during a public hearing at the beginning of the meeting.
Council will discuss a proposed increase in the electric rates due to an increase to the Town. The increase will be either 3 percent or 4.3 percent.


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In This Issue:
- Fed "Reviewing" Banks' Trading in Physical Commodity Markets
- Senate Passes Student Loan Bill With House Expected to Follow Suit
- Senators Introduce 21st Century Glass-Steagall Act
- Regulators Push for Tougher Bank Capital Standards than Basel
- Senators Ask CFPB to Examine ATM-Style Pay Cards
- Banks Adding Risk Experts to Boards Per Dodd-Frank Rules
Excerpt from Fed "Reviewing" Banks' Trading in Physical Commodity Markets:
The Federal Reserve is "reviewing" a landmark 2003 decision that first allowed regulatedbanks to trade in physical commodity markets, it said, a move that may send newshockwaves through Wall Street. The one-sentence statement suggests the Fed is taking a much deeper, wide-ranging look at how banks operate in commodity marketsthan previously believed, amid intensifying scrutiny of everything from electricity tradingto metals warehouses.
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Shabbat for Families
How to make Shabbat your family's favorite day of the week.
By Sara Shapiro-Plevan
We Also Recommend
Preparing for and celebrating Shabbat can be a daunting proposition. There are so many things to do even just to prepare, and if you have children, the prospect of celebrating Shabbat (meant to be joyous and relaxing) for even one hour, let alone 25, can seem preposterous.
Don't give up. This day-long marathon can be packed with marvelous family traditions and special opportunities for fun. Instead of making a radical change in the way your family observes Shabbat, make it gradual. Try some of these tips below and make Shabbat a truly special day for your family.
Make It Easy
Cooking has been at the center of preparation for Shabbat for generations. For traditional Jews, who do not prepare food during the Sabbath, all meals must be prepared before candle lighting. Sometimes cooking for Shabbat seems totally overwhelming–even for those who are only preparing one meal.
Relax! Shabbat meals are family meals where something is different and special. But this doesn't mean that they have to be fancy. Instead of laboring, pick up a barbequed chicken and a few side-dishes from your local kosher market, or make something simple. If there's time, encourage your children to help choose the menu or prepare the meal by making salads, chopping vegetables or helping to make dessert.
At Home
Shabbat is a unique time of the week. For many families, it's the time when the white table cloth comes out, when Great-Grandma's silver candlesticks are polished and used for lighting candles, and when the entire family drinks out of goblets instead of glasses. Add to the atmosphere by using your finest china, silver and crystal (those lovely things that never seem to get used), and a lovely tablecloth. Pick up flowers on the way home. Open a bottle of wine to have with dinner, not just for kiddush. Set the table in advance so that everyone gets to enjoy the anticipation of the family meal. Invite another family over to join you, or other members of your family. Make sure that the kids participate by setting the table and making table decorations or place cards. The weekly ritual of a "fancy" dinner, even if the food is less than fancy, will make for great memories. The ambiance will make the entire experience worthwhile.
Did you like this article? MyJewishLearning is a not-for-profit organization.


text:
Heartland News Service
A Mingo man and coal miner was killed Friday morning in an accident at the Coal River Mining LLC Fork Creek mine #10 in Boone County.
Johnny Mack Bryant II, 35, of Lenore, was killed in the accident about 4 a.m., according to Public Information Specialist, Leslie Fitzwater.
Bryant was a move crew employee, Fitzwater said.
Fitzwater confirmed that Bryant was crushed by a piece of machinery.
The accident happened on the day the Upper Big Branch Memorial had its dedication ceremony in Whitesville. The memorial was constructed to remember The Upper Big Branch Mine disaster that occurred on April 5, 2010, and killed 29 miners.
Gov. Earl Ray Tomblin acknowledged Bryant's loss with a moment of silence at the dedication ceremony.
Also last week, a man was severely injured when the coal truck he was driving rolled over in Fayette County.
The accident happened just before 4 p.m., Wednesday, July 25, on Mammoth Coal property near Alloy. The driver, whose name has not been released, was trapped inside the truck for over an hour.
State Police from the Quincy detachment responded with county deputies. Troopers said the man was responsive, but appeared to be badly hurt. Firefighters and paramedics also responded to the scene.
Troopers are working to determine what caused the truck to roll over.


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CHATTANOOGA — A man was arrested for domestic assault after he beat his girlfriend's 7-year-old son with a Tiki torch.
Police responded to a call about 6 p.m. of a man beating a child with a stick. When officers arrived they located the boy and found that the child had bruises on his back, bottom and chest, according to a news release.
James Cooper, 28, told police that he was disciplining the boy for doing something wrong. According to the release, Cooper admitted to police that he spanked the child but didn't believe he left any bruises.


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Musical's Final Weekend of Performances Also Takes Place
State Agriculture Commissioner Darrel J. Aubertine today announced the following events running from May 3 – 5, 2013 at the New York State Fairgrounds:
There will be horses and alpacas on display at the New York State Fairgrounds this weekend.
The Empire State Arabian Spring Horse Show brings to the Toyota Coliseum the stately horses bred for centuries for their friendliness and courage. The event will feature All-Arabian and Half-Arabian horses from throughout the United States and Canada for a three-day dressage event. The show begins at 8 a.m. each day beginning Friday. Admission is free.
The 4-H Arena, in the meantime, will play host to the Pinto Horse Association of New York Spring Fling All-Pinto Horse Show. People will be able to see the horses, with their distinctive coats of two-toned large patches, as they take part in events designed to test the horse and rider's control, showmanship, and riding ability. The event begins at 7:30 a.m. Saturday and Sunday. Admission is free.
The Northeast Alpaca Expo will feature hundreds of alpacas, which will be judged on the quality of their thick coats. Alpacas are domesticated members of the camel family that are raised for their hair. Alpaca fiber goes into all kinds of clothing and bedding products. Judging begins at 8 a.m. Saturday. Organizers plan to use a small camera to show and listen to judges as they discuss the qualities of each entrant. Seminars on a variety of alpaca-related issues are also scheduled. Admission to the Exhibit Center event is free.
"Suds: The Rocking 60's Musical," completes its run in the Empire Theater, telling the story of a young girl's search for love through the music of the early rock n' roll era. Performances are Friday and Saturday at 8 p.m. and Sunday at 2 p.m. Tickets are $25 for adults, $23 for seniors and students. Group discounts are available through the show's website, thetalentco.com.
In addition to the annual New York State Fair, the Fairgrounds host dozens of agricultural events throughout the year, including some of the Northeast's most prestigious horse and livestock shows. The New York State Fair runs from August 22 – September 2, 2013. The Fair's theme is "Sharing the Bounty and Pride of New York."
The home of the Great New York State Fair is a 375-acre exhibit and entertainment complex that operates all year. A year-round schedule of events is available on the Fair's website. Find The Great New York State Fair on Facebook or follow NYS Fair on Twitter. Also, New Yorkers are invited to send their ideas on the Great New York State Fair at firstname.lastname@example.com.


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Saving Lipatti
Of all the well-known classical musicians active in the first half of the 20th century, which one profited the most from the invention of sound recording? Virtually every one made at least a few records, and most recorded extensively and representatively. Yet even legendary figures who became closely identified with the phonograph, like the singer Enrico Caruso and the violinist Fritz Kreisler, were known mainly for their public performances, not for their records. The notion that a classical performer might become famous by playing in a recording studio rather than before live audiences was unthinkable—until Dinu Lipatti came along.
Lipatti, who died of Hodgkin's disease in 1950 at the age of thirty-three, was acclaimed throughout the last years of his tragically brief life as a pianist of the very first rank. The composer Francis Poulenc spoke of his "divine spirituality," while Alfred Cortot, his best-known piano teacher, described him as "a second [Vladimir] Horowitz." Yet, outside his native Romania, Lipatti would no longer be remembered were it not for his recordings. His career was only just getting under way when World War II began, and by the time the war was over his illness had started to make it difficult for him to perform in public.
Fortunately, the English record producer Walter Legge made a heroic effort to document Lipatti's playing before it was too late, first in the London studios of HMV and later at a radio station near the pianist's home in Switzerland. Though Lipatti left behind not quite four hours' worth of studio recordings, most of them done between 1947 and 1950 (as well as several radio broadcasts later released on LP and CD), these were sufficient to secure his reputation as one of the 20th century's foremost pianists, and the first to be known primarily for his recordings instead of his concerts.
For all of his posthumous renown, few of Lipatti's admirers know anything about his life beyond the sketchy accounts included in the liner notes to his recordings. It is not generally appreciated, for instance, that he was also a composer whose small but beautifully crafted body of work was full of promise. Nor does the English-language literature on Lipatti contain a candid discussion of his conduct in World War II, or of his decision to emigrate to Switzerland shortly before Romania was occupied by the Soviet Union.
Above all, there has been no adequate consideration of Lipatti's place in the evolution of modern classical-music performance practice. Thanks to the dramatic story of his illness and death, he is remembered not as a historical figure but as a near-mythic one who made some of the most beautiful piano recordings of the century. Yet these recordings, powerfully compelling though they were and are, do not exist in a cultural vacuum. To the contrary, they were made by a profoundly self-aware artist who was in every sense a man of his time.
Lipatti's emergence as a world-class modern musician was all the more surprising in light of the fact that he was born into a provincial classical-music culture. The violinist-composer George Enescu (1881-1955), his godfather and teacher, was the first Romanian musician to become widely known in Western Europe, and the only one before Lipatti to have a major career. Lipatti's parents, however, were both serious amateur musicians—his father, a career diplomat, had studied violin with Pablo de Sarasate and Carl Flesch—and no sooner did his own youthful talent become apparent than they encouraged him to cultivate it.
He started improvising at the piano as a small child ( Lipatti's mother, a competent pianist, later told Walter Legge that "he could play the piano before he had learned to smile") and performed in public for the first time at the age of six. Five years later he became a full-time student at Bucharest's Royal Academy of Music, graduating in 1932. The following year he took part in the International Piano Competition in Vienna, whose jury included such distinguished artists as the pianists Wilhelm Backhaus and Alfred Cortot and the conductors Clemens Krauss and Felix Weingartner. Cortot resigned from the jury in protest when the other jurors denied Lipatti the first prize only because of his youth.
In 1934, Lipatti and his family moved to Paris, where he studied piano with Cortot and composition with Nadia Boulanger. He made his Paris debut the following February, and from then on was acknowledged as a musical master in the making.
Had Lipatti been a less remarkable pianist, it is possible that he would have won much wider recognition as a composer. At first he was heavily influenced by Enescu, one of the post-romantic modernists who, like Béla Bartók in Hungary and Ralph Vaughan Williams in England, believed that folk music could serve as the basis for a distinctively national style of classical composition. Then Boulanger introduced him to the Bach-based neoclassical modernism of Igor Stravinsky. Out of these two contrasting approaches, he forged a style that owed much to Enescu (and, later, Bartók) but was becoming increasingly personal in the handful of large-scale works he completed in the 40's, which Boulanger rightly saw as "proof of a real creative gift."
Not only was Lipatti a promising composer, but he could easily have made a name for himself as a critic. This he proved in a series of reviews published in 1939, the most provocative of which is an account of a Paris recital by Vladimir Horowitz:
So long as he was guided by his instinct as a musician, and by the sensitivity of his youth, Horowitz remained above criticism. Today, however, perhaps influenced by his relationship with [the conductor Arturo] Toscanini, he is trying to explore the works he is performing to make them interesting. In fact, he is trying to transform them. . . . Horowitz will be the most extraordinary pianist of all times the day he is content to accept himself as he is.
But, amazingly varied as were his gifts, in the end it was the piano that meant most to Lipatti. After 1939, he wrote nothing more for publication, and completed only four large-scale musical compositions (as well as two groups of art songs). When Boulanger warned him that he needed to devote more time to composition, he replied, "I know this very well, but I cannot tear myself away from the piano. If you only knew how much I love 'him.' "
By then Lipatti was on the verge of launching an international career. Instead, he returned to Romania in the summer of 1939, not long before war broke out. The best-known version of what happened next comes from Walter Legge, who notes that Lipatti stayed in Romania until 1943,
when, together with his fiancée Madeleine Cantacuzeno, he escaped from Bucharest, and by devious ruses and routes they arrived, via Stockholm, in Geneva with a joint capital of five Swiss francs.
All this is true—so far as it goes. But Legge fails to mention that, starting in 1941, Lipatti gave concerts in Germany, Italy, Austria, and other Nazi-controlled countries.
4 These appearances were not isolated events. Between 1941 and 1943, Lipatti had performed throughout the Axis (of which Romania was a part), and nowhere in the excerpts from his correspondence included in the English-language edition of his biography does he voice any doubts about the propriety of having done so.
Legge's misrepresentation of Lipatti's wartime activities was almost certainly deliberate. The producer was notoriously indifferent to the equivocal political histories of such German and Austrian musicians as Wilhelm Furtwängler and Herbert von Karajan, whom he made a point of recording for HMV after the war. Indeed, Legge went so far as to marry the German soprano Elisabeth Schwarzkopf, who had joined the Nazi party as a teenager. It would have been in character for him to cover up the awkward fact that another of his "discoveries" had played for Nazi audiences during the first part of the war.
As for whether Lipatti himself had any Nazi sympathies, this cannot be determined from the documents published in English. It should be noted, however, that not only did he settle in neutral Switzerland in 1943, but he was later befriended by such impeccably anti-Nazi émigrés as Artur Schnabel and Arturo Toscanini, who would have shunned him had they suspected him of being an outright Nazi collaborator (as the Frenchman Cortot had been). It seems at least as likely that, as he would claim in a 1947 letter to a Romanian friend, "I have never been mixed up in any kind of politics," and it appears that he remained in Switzerland after the war in order to avoid becoming entangled with Romania's newly installed Communist regime.
Whatever the truth of the matter, it is indisputable that Legge first heard about Lipatti from Francis Poulenc in Paris in 1944. Though the pianist had cut a few records with Boulanger for French HMV in 1937, his only recordings since that time had been made in Berlin, Bucharest, and Geneva, and were unknown elsewhere.
5 After hearing him play the Chopin E Minor Concerto, Legge signed Lipatti to a contract with HMV, and began recording him in 1946.
Recording made it possible for Lipatti to indulge to the fullest his perfectionism. "I do not want to give any more concerts—except as rehearsals for recording," he told Legge. "Let us give our lives to making records together." Alas, his recorded repertory was restricted by his fast-failing health, as well as (one suspects) by his producer's near-complete lack of interest in modern music. Only one 20th-century piece, a breathtakingly virtuosic 1948 version of Ravel's Alborada del gracioso, was released by HMV. What survives is a small but representative group of works by the composers whose music he played most frequently in concert after the war: Bach, Mozart, Schumann, Liszt, and Chopin.
The salient quality of these performances has been well described by Legge in his remarks about Lipatti's legendary 1950 recording of his signature encore, Dame Myra Hess's transcription for solo piano of Bach's "Jesu, Joy of Man's Desiring":
It is impossible to explain, to those who have not experienced the wonder of his playing of this piece, its rapt beauty and fascination. It was always the first encore he played, and for him it was a prayer and utterance of thanksgiving to God. The sound was not of this world, it hovered in space like some celestial blessing.
For once, what may seem poetic license is only the simple truth: Lipatti's performance of Bach's limpid meditation on a Lutheran chorale is a miracle of lucidity and balance. From Cortot, the greatest of French pianists, he had learned the secret of playing with a lambent yet full-bodied tone, and no matter how often one listens to his recording, to hear the familiar melody singing out through the serenely flowing triplets of the accompaniment is to be entranced anew.
Just as characteristic is his similarly celebrated 1948 recording of Chopin's Barcarolle, Op. 60. Unlike "Jesu, Joy of Man's Desiring," the Barcarolle was recorded by several major romantic-era pianists, including Cortot, Horowitz, Benno Moiseiwitsch, Vladimir de Pachmann, and Arthur Rubinstein, all of whom employ the freely flexible rubato heard in the recordings of classical musicians of the late 19th and early 20th centuries. To be sure, each rubato is distinctive: Cortot colors the essentially steady flow of his playing with engagingly impulsive fluctuations of tempo, whereas Horowitz tinkers with the underlying rhythmic pulse so much as to make it hard to follow. Nevertheless, all five pianists vary the pulse at will for expressive purposes, often to a degree that many of today's listeners would find obtrusive, even tasteless.
Lipatti's rubato, by contrast, is less explicit, consisting in the main of a discreet ebb and flow that he uses with great subtlety to sculpt Chopin's phrases. The pulse is always clear and coherent, thus creating the illusion of a single, unified arc of rhythm that sweeps the listener through the piece. This gives his interpretation a cumulative force that is absent from less rhythmically unified performances, and prepares the way for a climactic peroration that is appropriately grand but in no way grandiose.
After hearing Lipatti play a Chopin concerto, Toscanini told him, "At last we have a Chopin without caprices and with the rubato to my liking." Yet, though he had studied with Boulanger and played the music of Bartók and Stravinsky, Lipatti was not a "modern" pianist in the ordinary sense of the word.
7 While his rubato was much less capricious than Cortot's, it was free enough to make him ill at ease with the stricter, Toscanini-like style of the young Herbert von Karajan, with whom he recorded the Schumann Piano Concerto in 1948. "I did not count on an unexpected factor, a remarkable but superclassical conductor who, instead of helping my timid romantic élan, put a brake on my good intentions," he wrote in a letter to a friend. Nor was Lipatti a rigid textual literalist. As he explained in an unpublished note written shortly before his death:
Far from me is the thought of rendering predictable the anarchy and disdain for the primary laws which guide, along general lines, the coordination of any valid and just interpretation. But I find that one would commit a grave mistake by searching for useless details regarding the way in which Mozart might have played a certain trill or gruppetto. . . . Never approach a score with dead eyes or the spirit of the past because you might find yourselves only with Yorick's skull.
Thus it is perhaps more accurate to think of Lipatti's playing as a synthesis, a kind of halfway house between the golden-age romanticism of older pianists like Cortot and the cooler, more restrained neoclassicism of the 20's and 30's. Indeed, one might almost be tempted to call him a transitional figure were his playing not so fully realized on its own distinctively individual terms. The impassioned lyricism of his 1947 broadcast of Bartók's Third Concerto suggests that his way with 20th-century music would have been no less convincing than his playing of Mozart and Chopin.
But it was not to be. Though cortisone suppressed the symptoms of Lipatti's illness long enough for him to record in Geneva in July 1950 and to play a Mozart concerto with Karajan the following month at the Lucerne Festival, his condition thereafter deteriorated with shocking speed. In mid-September he gave a solo recital at the Besançon Festival in France, by which time he was so sick that he was unable to play the last of the Chopin waltzes he had programmed and had to substitute the less technically demanding "Jesu, Joy of Man's Desiring."
8 Ten weeks later he was dead, having spent the last hour of his life listening to a radio broadcast of Beethoven's F Minor String Quartet. "You see," he told his wife, "it is not enough to be a great composer. To write music like that you must be a chosen instrument of God."
Much of what has been said about Lipatti since then is but an echo of what the grieving Walter Legge wrote about him in 1951:
Dinu Lipatti had the qualities of a saint. The spiritual goodness of his nature, his modesty, his gentleness, his will's firm purpose, his nobility and loftiness of thought and action communicated themselves to all who met him, and to the remotest listeners in the halls where he played. His goodness and generosity evoked faith, hope, and charity in those around him.
No doubt this, too, is true—most of his friends and colleagues said more or less the same things about him. But it is not necessary to ascribe sainthood to Dinu Lipatti in order to marvel at the poetry of his playing. Had he not made records, it is unlikely that such fervent paeans to his artistry would have been taken seriously by later generations. Instead, we can hear for ourselves, and know that his untimely death robbed the world of a supremely great artist. Though he was no Franz Schubert, one can only recall the epitaph written by a friend of that great and short-lived composer: "The art of music has here entombed a rich possession, but far fairer hopes."
1 All of Lipatti's postwar studio recordings are available on five CD's. EMI Classics 66596 has works by Chopin, including the complete waltzes, the Barcarolle, and a nocturne and mazurka. EMI Classics 67003 offers Bach's B Flat Partita, Mozart's A Minor Sonata, two Scarlatti sonatas, and four Bach transcriptions (plus a 1950 broadcast of two Schubert impromptus). EMI Classics 67567 presents Chopin's B Minor Sonata, Liszt's Sonetto del Petrarca 104 and Ravel's Alborada del gracioso. EMI Classics 67775 contains the Schumann Piano Concerto, accompanied by Herbert von Karajan and the Philharmonia Orchestra (plus a 1950 broadcast of the Mozart C Major Concerto conducted by Karajan). EMI Classics 74802 has the Grieg Piano Concerto, accompanied by Alceo Galliera and the Philharmonia (plus a 1950 broadcast of the Chopin E Minor Concerto). Except as indicated, these CD's include all of the pieces mentioned in this article.
2 The only book-length study that has appeared in English to date is Lipatti (1971), by Dragos Tanasescu and Grigore Bargauanu, two Romanian musicologists. Not surprisingly, their discussion of the pianist's relations with the governments of Nazi Germany and postwar Romania is guarded to the point of euphemism.
3 In 1943 Lipatti recorded his own Concertino in Classic Style (1936), an attractive but derivative neoclassical exercise à la Boulanger, and a Sonatina for Left Hand (1941) in which he made highly original use of a compositional language derived from Bartók's third-period style. These performances, along with contemporary studio recordings with Enescu of the violinist's Second and Third Sonatas, are part of Enescu si Lipatti Interpreteaza Enescu si Lipatti (Electrecord EDC 430/431, two CD's), a Romanian import available through amazon.com. Most of Lipatti's other works have been recorded by Romanian artists, but none is currently available on CD.
4 Desmond Shawe-Taylor's entry on Lipatti in The New Grove Dictionary of Music and Musicians is similarly unforthcoming.
5 In 1937 Lipatti and Boulanger recorded seven Brahms waltzes for piano duet and the accompaniments to the Liebeslieder Walzer, Op. 52 (Pearl GEMM CD 9994). In addition to the wartime performances reissued on Enescu si Lipatti Interpreteaza Enescu si Lipatti, he also recorded Enescu's Third Piano Sonata (this performance is included on EMI Classics 67567).
6 EMI has also released a CD containing radio broadcasts by Lipatti of the Bach D Minor Concerto (played in the piano arrangement of Ferruccio Busóni), the Liszt E Flat Concerto, and Bartók's Third Concerto (EMI Classics 67572). Illness prevented him from recording Beethoven's "Waldstein" Sonata and Schumann's Symphonic Etudes, both of which figured prominently in his recital programs. (Lipatti played the "Waldstein" Sonata for the BBC, but no tape is known to exist.)
7 In his broadcasts Lipatti can occasionally be heard improvising brief preludes to the pieces he is playing, a 19th-century practice that also characterizes the live recordings of such turn-of-the-century pianists as Josef Hofmann.
8 This recital was broadcast, and an aircheck of the performance, originally released on LP in 1957, is now available on CD (EMI Classics 62820).


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1. Make a faux flower...
Reminds me of Wisteria
- film spools (about 6)
- Small flowerpot
- Dry foam (for bottom of flower pot)
- Artificial plant stem of your choice—try to make sure the leaves match well with the shape of the flower
- Grapevine wire
- Green covered florist wire
- Ribbon of your choice-for color of flower
- Moss
- Hot glue gun/ glue sticks
Use the florist wire to wrap each film spool. Leave enough wire to be able to use it to attach it to the stem later. Don't worry about how it looks, because you're about to cover it with ribbon.
Step Two:
Wrap each wired film spool with your ribbon. Make sure to glue at the start and the end of the ribbon; also, maybe a few spots of glue in between.
Step Three:
Bend your stem so that it's arched over at the top. Start attaching each spool at the top of the arch, going down, by wrapping the wire around the stem. Try not to use a lot of wire because it could build up and start looking a bit strange. Just cut off the leftover wire. Use the grapevine wire for extra support. You can wrap the entire stem with grapevine wire if you need to.
Step Four:
Place foam in the bottom of your flowerpot. Insert your stem in the middle and make sure it is stable.
Step Five:
Cover your foam with moss by gluing it down with your hot glue gun. The moss will probably add some much needed support as well. You can use it to take up space left in between the pot and the foam. Build up a good bit right around the base of the stem too.
2. Make some desk-top holders (a picture frame, a pencil holder). These are easy and fun crafts to make with kids...
The How-To
Supplies (picture frame):
- Plain picture frame
- Used film
- Film spools (maybe two or three)
- Hot glue gun/ glue sticks
Cover the entire frame with the film using the glue gun. Create folds using both sides of the film.
Step Two:
Decide where you want to place the film spools. Glue film around spool and then glue to frame. Use a little extra film so you can create some folds from the film glued to the spool.
Supplies (pencil holder):
- Eighteen film spools
- Used film (two rolls)
- CD (you don't need anymore)
- Glue gun/glue sticks
Glue first set of nine film spools standing up in a circle on the CD. Leave a space in between each spool.
Step Two:
Weave film in and out of the spools. Glue at the start and finish of the circle.
Step Three:
Glue next set of nine spools standing up directly on top of the first set.
Step Four:
Repeat step two.
3. Other ideas for things to make:
- A Necklace
- A Keychain
- Place card holders
4. Create a stacking game out of them
Do you have any other ideas? Share by leaving a comment.
- Melanie Payne


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Culture Bibliography
We Also Recommend
To go directly to a specific category, click below:
General Books about Jewish Culture
Theatre & Dance
The Blackwell Companion to Jewish Culture: From the Eighteenth Century to the Present, edited by Glenda Abramson, Dovid Katz, Nicholas de Lange (Blackwell Publishers, 1990).
The Jews: A Treasury of Art and Literature, edited by Sharon R. Keller (Hugh Lauter Levin Associates, 1992).
Jewish Art, by Grace Cohen Grossman (Hugh Lauter Levin Associates, 1995).
Jewish Texts on the Visual Arts, edited by Vivien Mann (Cambridge University Press, 2000).
Complex Identities: Jewish Consciousness and Modern Art, edited by Mathew Baigell and Milly Heyd (Rutgers University Press, 2001).
Reel Jewish, by Joel Samberg (Jonathan David Publishers, 2000).
American-Jewish Filmmakers: Traditions & Trends, by David Desser and Lester D. Friedman (University of Illinois Press, 1993).
Over the Top Judaism: Precedents and Trends in the Depiction of Jewish Beliefs and Observances in Film and Television, by Elliot B. Gertel (University Press of America, 2003).
Independent Jewish Film: A Resource Guide, by Janis Plotkin, et al (San Francisco Jewish Film Festival, 2000).
Ethnic Images in American Film and Television, edited by Randall M. Miller (Garland Publishers, 1987).
The Jewish Image in American Film, by Lester D. Friedman (Citadel, 1991).
Indelible Shadows: Film and the Holocaust, by Annette Insdorf (Vintage Books, 1983).
Bridge of Light: Yiddish Film Between Two Worlds, by Jim Hoberman (Museum of Modern Art and Schocken Books, 1991)
Visions, Images and Dreams: Yiddish Film Past and Present, by Eric A. Goldman (Ergo Media, Teaneck, 1979).
The Book of Jewish Food: An Odyssey from Samarkand to New York, by Claudia Roden (Knopf, 1996).
Sephardic Cooking, by Copeland Marks (Donald I. Fine, Inc., 1992).
Eat and Be Satisfied, by John Cooper (Jason Aronson, 1993).
Jewish Cooking in America, by Joan Nathan (Random House, 1998).
The Foods of Israel Today, by Joan Nathan (Knopf, 2001).
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