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These postings are provided "AS IS" with no warranties, and confer no rights. Use of included code samples are subject to the terms specified at Microsoft Information on Terms of Use
We have released Windows 7 & Windows Server 2008 R2 last year. One of the features that we had deployed internally was DirectAccess. You must have heard about DirectAccess many times during our New Efficiency and similar set of launch events. We have been telling Better Together story with Windows 7 & Windows Server 2008 R2.
From the blog topic you must have received some hint what am I going to cover in today's post. Exactly the same thing i.e. Connecting to your Office Corporate Network using TATA Photon+ and Reliance NetConnect. I believe that many users are connecting to the Internet by using various options such as ADSL, Wireless, ISDN etc. DirectAccess feature works well seamlessly for most of the connections such Wireless at home, hotel, airports etc. I will be covering about connectivity in India where we have some of the major players offering high speed CDMA broadband connection. These players are TATA Photon+ and Reliance NetConnect Broadband. Both of them offer up to 3.1 Mbps connectivity but anyways we won't go into that discussion. We will cover specifically connecting to CorpNet using TATA Photon+ and Reliance NetConnection because the very simple fact is that most of the users not able to use DirectAccess feature over these Internet Connection.
I have been on to DirectAccess pilot since long time and by the time I joined it's been an amazing experience connecting to CorpNet without going through standard VPN/RAS dialing process. But the sad part when I was not able to connect to my CorpNet using TATA Photon+ Card. I am using Tata Photon+ from last December but every time I was trying to connect to my CorpNet using DirectAccess there was no success and I was using regular RAS/VPN process. The same case happened even by trying out Reliance NetConnect Broadband. I tried different settings but no luck and then I decided to let it go. Later I got to know that most of colleagues are also facing similar problem and not able to leverage the DirectAccess feature.
So, last week I was travelling and by that time I decided to find a solid conclusion before quitting
and asking for the product group. And here it is how I found the solution to this problem and here are my findings.
Checking DirectAccess Status
Trying to connect to CorpNet Environment using TATA Photon+ Internet.
Here is the standard TATA Photon+ Dialer, I will click on Connect to get connected to Internet.
The Reliance Dialer looks exactly similar except the logo in the right corner. Basically the complete software is designed by HUAWEI Technologies Co., Ltd.
In the red box, it is the actual profile or the actual Dial Up Connection created by the Huawei Access Manager.
Let me try connecting to my computer in corporate environment, say aviraj-demo is my server in my Microsoft office environment. A minute after connecting to the internet, I will try to ping it and I get the reply in IPv6 format. It means by DirectAccess seems to be operational so far on my machine but not completely functional. Let's test it.
DirectAccess Attempt #1: Connecting to resources in my CorpNet
Now, that I can ping let me try accessing files on that server or try to take remote of that server.
Resource Output 1: Accessing internal site: http://sharepoint Status: FAILED
The does not open and it goes over the internet to search for this internal portal due to lack of connectivity.
Resource Output 2: File Share (start -> run -> \\aviraj-demo ) Status: FAILED
Resource Output 3: Remote Desktop Protocol – RDP (mstsc) Status: FAILED
TROUBLESHOOTING DirectAccess Using Windows 7 Built-in Troubleshooting Packs
I am getting Ping response but it seems I have not yet got complete CorpNet access due to authentication. Then I decided to run the Troubleshooting Option located in Network and Sharing Centre.
You can do that by clicking on Connection to a Workplace Using DirectAccess. I selected Automatic Repair check box.
After running this wizard I got the following result. This was not much help, I tried updating group policy assuming that something is missing but nothing worked.
TESTING OUTLOOK CLIENT CONNECTION…Hint for the solution!!!
Since I am connected to Internet, I decided to open up Outlook 2010 Client. As soon as clicked on Outlook 2010 here is the prompt I got.
Hmm, surprisingly instead of my own Domain\Alias i.e. fareast\i-aviraj I am prompted with something like internet. At this point I got that that every time I get connected to Internet I am prompted with my Alias so why every time when I get connected using TATA Photon+ I am prompted with internet.
Get DirectAccess Working – SOLUTION # 1: Using Huawei Dialer & Credentials Manager
Step 1: Get connected to the internet using the above stated process using TATA PHOTON+ Dialer or RELIANCE NETCONNECT BROADBAND DIALER.
Step 2: Go to Control Panel , double click on Credentials Manager
Step 3: Expand the first entry named *Session in the Windows Credentials with status Modified: Today
This is the exact reason, the DirectAccess in not fully functional. Every time you connect using HUAWEI Connection Manager, it creates this Windows Credentials named *Session with Persistence: Logon Session. Because of this Logon Session entry, it bypasses the default domain credentials and the dialer provided credentials are used for authentication and subsequently gets failed due to failure of authentication.
What is Logon Session?
logon session
A logon session begins whenever a user logs on to a computer. All processes in a logon session have the same primary access token. The access token contains information about the security context of the logon session, including the user's SID, the logon identifier, and the logon SID.
More to read http://msdn.microsoft.com/en-us/library/aa378338(VS.85).aspx
Step 4: Solving this issue and getting back to Domain Credentials
Click on Remove Credentials and click on Yes
Step 5: Success within a Minute. :)
The moment you delete it, wait for few seconds and try to open any internal website say http://msw. Within moments, you will be asked for the prompt you have been for since months over your High Speed CDMA Broadband Connection.
Voila!!! Success, this is what you have been waiting for since long time. DirectAccess over TATA Photon+ and Reliance NetConnect Broadband using HUAWEI Dialer.
Windows Needs your Smart Card Credentials
Double click on the Credential's icon in system tray, insert Smart Card in reader and Enter PIN
You will see your credentials getting verified.
We will test this solution if this really worked.
DirectAccess Attempt #2: Connecting to resources in my CorpNet…Post Applying Solution 1
Now that I have authenticated my credentials using Smart Card, I will check different resources.
Resource Output 1: Accessing internal site: http://sharepoint Status: SUCCESS
Resource Output 2: File Share (start -> run -> \\aviraj-demo ) Status: SUCCESS
This time I go to start run and enter the file share \\aviraj-demo and wait for the response.
While hovering on to the taskbar I see my mouse point showing busy icon, it means my explorer trying to connect to the remote resource. After a minute or so, after resolving the server name here my output.
Resource Output 3: Remote Desktop Protocol - RDP (mstsc) Status: SUCCESS
When Connected to Remote Desktop over DirectAccess
This is solution working with Dialer because many users are willing to use TATA/RELIANCE DIALER because it helps giving the signal strength by showing HSIA/CDMA Status. Secondly, it helps keeping track of usage by providing detailed stastics and real time speed in KB/s.
I hope this will surely help you experience DirectAccess over this high speed connection.
JUST REMEMBER, EVERY TIME YOU GET CONNECTED TO INTERNET USING TATA/RELIANCE DIALER, YOU NEED TO REMOVE *Session ENTRY FROM CREDENTIALS MANAGER TO GET YOUR DirectAccess WORKING.
Get DirectAccess Working – SOLUTION # 2: Using Windows Dialer instead of TATA/RELIANCE DIALER
Let's start by showing the same image…
As I said the red box indicates this is basically Windows Dial Up connection that get's dialed at the backend. Instead of using TATA/RELIANCE Dialer you can directly connect to the pre-configure Dial Up Entry from your network.
Step 1: open the HUAWEI DIALER and read the Profile Name: TATA Indicom (in this example) close the dialer.
Step 2: Click on the Network and Sharing Center Icon in system tray. You will see your profile. Click on this Profile name. In this example it is TATA Indicom. Click on Connect and click on Dial
Step 3: Once connected Go to Control Panel , double click on Credentials Manager. You will not find the Windows Credentials containing any *Session entry.
Try to access internal resource, within a minute you will be prompted for Windows Smart Card Credentials.
After then try using the same steps performed in DirectAccess Attempt #2.
I hope that this post has given you sufficient number of ideas about connecting to CorpNet. Many of customers would be benefitted by this and they can now leverage the same over high speed CDMA networks or similar types of connections. Meanwhile, I will try working finding the any other alternate solution that can help us avoid deleting the credential manager data manually.
I will be publishing a quick Screencast and will share it on http://edge.technet.com/people/aviraj
Quick Reminder: We are undergoing Blog migration to newer platform this week. User comments are disabled. Feel free to ask any questions to me over an E-Mail: email@example.com
Enjoy DirectAccess !!!
Maintaining that competitive edge in a fast changing business landscape is not an option now. These goals require a new approach to IT and data center management emphasizing automation and optimization. Windows Server 2008 R2 was designed and built with these goals in mind.
Windows Server 2008 R2 addresses cost savings across a number of areas, including streamlined management, less reliance on expensive third-party software, more scalable application serving and lowered WAN bandwidth costs. Customers have seen server consolidation rates up to 3-to-1 as well as up to an 80% decrease in IT man-hours spent on rote administrative tasks like file system management. Power efficiency is also improved over Windows Server 2008 and again over Windows Server 2003 R2. Early adopters of Windows Server 2008 R2 have documented significant savings in this regard, up to 18% over Windows Server 2003 R2.
These documents provide important information you should know prior to deploying and using the Windows Server 2008 operating system, including known issues that you may need to avoid or work around. The documents are continuously updated, so you should check this location for updated versions periodically. You will find four documents for Windows Server 2008 R2:
This software is an optional supplement to the Windows Server 2008 R2 operating system. In Windows Server 2008 R2, the Streaming Media Services role (which includes the latest version of Windows Media Services) is not included in Server Manager.
To obtain Windows Media Services for Windows Server 2008 R2, you must run the Streaming Media Services role installer file on the platform.
If you are interested in the Streaming Media then download the latest version of Windows Media Service for Windows Server 2008 R2.
The Windows 7 Application Compatibility List for IT Professionals is a Microsoft Office Excel-based spreadsheet listing software applications which have met Windows 7 Logo Program testing requirements for compatibility with 32-bit and 64-bit Windows 7, and have thereby earned the right to display the Windows 7 Logo Program logo with the application. These products are identified with the compatibility status "Compatible – Windows 7 Logo." Additionally, this list includes applications with the following compatibility statuses: "Compatible," "Free Update Required," "Paid Update Required," "Future Compatibility," and "Not Compatible." These statuses are based upon the software publishers' statements of compatibility. These products have not met the Windows 7 Logo Program testing requirements. For an explanation of the various compatibility statuses, please see the Release Notes for the Windows 7 Application Compatibility List. For the latest collection of compatible applications and hardware devices, please visit the Windows 7 Compatibility Center. You can also leave feedback on compatibility and suggest new products to get added in future reports.
Windows Internet Explorer 8 is Microsoft's latest web browser. Unlike previous versions, Internet Explorer 8 renders content in the most standards-compliant way possible. This means that web pages will be displayed in Internet Explorer 8's standards mode by default. Through product feedback channels, our users have indicated that, during the beta period, some websites may not have been compatible with Internet Explorer 8 in its default, standards-based mode. As a result, these domains have been added to a list of sites that, for the short-term, are most likely to be displayed better in Compatibility View. All Internet Explorer 8 users are given the choice to use this list, and the subset that chooses to do so will see each listed domain automatically displayed in Compatibility View, without additional user interaction or notice. The sites on this list have high traffic volume (in their regions), and having a compatible website ensures a significant number of Internet Explorer 8 users will have a great experience. This list will be periodically updated and automatically downloaded to Internet Explorer 8 users who have opted-in to use Compatibility View updates from Microsoft. For more information on Compatibility View list updates, please see - http://support.microsoft.com/kb/960321.
AppLocker is a new feature of Windows7 that allows administrators to define policies that can allow or deny a user's ability to run or install executable, MSI, or script files. Microsoft Application Virtualization (App-V) separates the application from the operating system preventing application conflicts and enabling the ability to run multiple versions of an application of the same desktop. Virtual applications can be delivered in many ways – streaming by assigning applications to user, delivering to machines via Configuration Manager or by using file streaming from removable media. Using App-V and Applocker together ensures that no matter how the application is delivered or what format is takes, physical or virtual, it will respect the policies defined by IT. Watch these demonstrations to learn how to configure App-V; create, update, and publish virtual applications; and create and manage policies for virtual applications.
The Microsoft Touch Pack for Windows 7 is a collection of games and applications that are made available to computers with multi-touch enabled displays running Windows 7.
The Touch Pack includes: Microsoft Blackboard, an intricate game of physics in which you solve a puzzle by creating a fanciful machine on a blackboard. Microsoft Garden Pond, a tranquil game that takes place in serene Japanese water gardens. Microsoft Rebound, a game in which you use your fingertips to control Tesla spheres with an electrical field between them to catapult a metal game ball into your opponent's goal. Microsoft Surface Globe, a program that you can use to explore the earth as a flat 2-D map or as an immersive 3-D experience. Microsoft Surface Collage, a program that you can use to explore and interact with your photos and arrange them as a desktop background. Microsoft Surface Lagoon, a screen saver and interactive water simulation, complete with a meditative rock arrangement and playful, shy fish.
The PoC Jumpstart provides resources to deploy a desktop PoC with Windows 7, Office 2010, Internet Explorer 8, and Application Virtualization with Microsoft Desktop Optimization Pack technology.
This self-contained, self-service kit will help you complete a Proof-of -Concept (PoC) at your organization, allowing you to quickly evaluate the new Microsoft desktop technologies, including Windows 7, Office 2010 Pro Plus, Internet Explorer 8, and Application Virtualization with Microsoft Desktop Optimization Pack technology App-V. It will also familiarize you with some of the important deployment tools provided by Microsoft to assist with your broader deployment efforts. This PoC is not meant to be comprehensive training mechanism but rather an introductory set of modules to familiarize you with tools and technologies. • Microsoft Windows Server 2008 Enterprise Edition – A platform that helps IT Professionals increase the flexibility and reliability of their server infrastructure. • Microsoft Assessment and Planning Toolkit (MAP) – A tool to assess your hardware readiness for Windows 7 and Office 2010. • Microsoft Application Compatibility Toolkit (ACT) – A tool to assess your software readiness for Windows 7 and Office 2010. • Microsoft Office Migration and Planning Manager (OMPM) – A tool to assess and upgrade Office versions and files. • Microsoft Deployment Toolkit – A tool to create, configure, and deploy custom images, applications, and components. • Windows 7 Enterprise 90-day Trial image – This evaluation edition forms the base image for deployment on client computers. • Microsoft Office Professional Plus 2010 – This system is the best productivity experience across the PC, Phone, and Web. • Office 2010 with Application Virtualization – This system is deployed virtually to streamline and centralize operations. • Microsoft SQL Server 2005 Express Edition – This database system is used to store application compatibility and Microsoft Office assessment data for the ACT and OMPM tools. • Microsoft SQL Server 2008 Express Edition – This database system is used to store image and task sequence data for MDT Deployment Workbench. • Microsoft SQL Server 2008 Evaluation Edition – This database system is used to store hardware assessment data for the MAP tool. The PoC Jumpstart is intended to show you that an upgrade to new Microsoft Optimize Desktop technologies can be seamless, feasible, easy and cost-effective. The PoC Jumpstart will also shed light on the deployment process (tools and technologies) and give your organization confidence for undertaking a broader deployment motion. After completion of the PoC, you should have a test environment setup that will allow you to evaluate the various features of the Microsoft Optimized Desktop and help you make informed decisions to meet your business needs.


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Anyone who has hung out in a yoga ashram or health spa will tell you that the morning beverage of choice is hot lemon water with cayenne pepper and honey or maple syrup. After all my years of living, studying and working in ashrams and spas you would think I would have adopted this healthy lifestyle habit. But I have a confession. Although I've often had hot lemon water, I never was brave enough to put a pinch of cayenne pepper in my morning brew. Until now, that is.
Last week I was hit with the sore throat/cough/body ache virus that passed through town. So I decided to give the lemon/cayenne concoction a try. And boy, am I glad I did! First of all, it actually tastes good. But more importantly, the zing of cayenne was instantly soothing to my sore throat.
If you'd like to try this time-honored healing drink, here's what you need:
- Juice of ½ an organic lemon (in the photo you can see my favorite lemon squeezer)
- Pinch of Cayenne
- Sweetener (I use Valencia Orange Stevia, but you could use honey or maple syrup – the amount is up to you)
- Hot water (not boiling, however, because boiling water can denature the enzymes in the lemon)
And remember Happiness in a Glass? Another yummy beverage that helps me regain my strength and sacred power!
What is your secret healing ingredient when your body has lost its mojo? Share it with me in the comments below. Thank you

subset: commoncrawl


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A message transfer system between multiple processors in a network. Each processor includes an interprocessor communications (IPC) hardware unit having an unique address count. An address count generator in a designated IPC hardware unit generates a sequence of binary count numbers such that when the generated count number matches the address of the IPC hardware unit, then that particular hardware unit and its associated processor are granted a time period of bus access for sending messages on the IPC network bus to other processors. Messages on the IPC network bus can be received by an IPC hardware unit at any time irrespective of the generated count number. Any sending processor that has bus access can concurrently provide multiple messages where each of the multiple messages is directed to each particular processor for reception. Thus one sender, with bus access, can communicate with multiple receivers during its transmission onto the IPC network bus connecting the processors.
1. An interprocessor message transfer system communicating on a digital bus means in a multiple processor network, said system comprising:
(a) communication hardware unit means associated with and connected to each associated processor and having a unique address count value for identifying each said communication hardware unit means of each said associated processor, said hardware unit means including:
(a1) access count signal generation means for generating a sequence of address count values which cycle through each unique address count value of each said associated processor's communication hardware unit means;
(a2) strobe means to freeze said generated address count value when it matches the said unique address count value of said associated processors communications hardware unit;
(a3) means to enable said digital bus means access to the associated processor whose hardware unit unique address count value matches said generated address count value, thus to enable said associated processor as a sending processor;
(a4) means to transmit message data on said digital bus means from said sending processor to one or more receiving processors;
(b) said digital bus means enabling parallel bit digital data transfer, during the period when said generated address count value is frozen, via interconnection to each of said communication hardware unit means;
(c) network resource means including (i) main memory means (ii) I/O means and (iii) maintenance subsystem means, wherein said main memory means includes: a mailbox portion for holding messages associated with each said unique address count value; and wherein said I/O means provides data transfers to/from said processors without interrupting data transfers on said digital bus means; and wherein said maintenance means provides said unique address count value to each of said associated interprocessor communication hardware unit means.
2. The message transfer system of claim 1 which includes:
(a) means for enabling any processor to send a message to any other processor in the network without interrupting normal processor operations in communicating with said main memory means or said I/O means;
(b) means for accumulating messages in each said communication hardware unit means until such time as the said associated processor can receive and process said messages;
(c) means, in said communication hardware unit means, for providing an interrupt to its associated processor software to indicate reception of a message.
3. The message transfer system of claim 1 wherein said access count signal generation means includes:
(a) means for generating said sequence of address count values only when at least one of said interprocessor communications hardware unit means has the unique identifying address count of "00".
4. The message transfer system of claim 1 wherein each of said communication hardware unit means includes:
(a) control logic means for sending and receiving messages and for generating an acknowledge signal when a message has been received, said logic means including:
(a1) receive register means for holding messages received for the associated processor;
(a2) send register means for holding messages to be sent to another processor on said digital bus means.
5. A multiple processor network interconnected by a digital bus for equalizing digital bus access for message data transfers between a selected sending processor and receiving processors, said network comprising:
(a) an interprocessor communications (IPC) hardware unit connected to each processor, each said IPC hardware unit including:
(a1) address register means for holding a unique address value identifying the IPC hardware unit and its connected processor;
(a2) address count signal generations means, synchronized by a common clock means, to generate a sequence of address count values onto said digital bus means, said sequence of generated address count values occurring in rotation so as to match each one of said unique address values which identify each interprocessor communications hardware unit;
(a3) strobe means to freeze said generated address count value when it matches said unique address value in said address register means, to select as a sending processor, that processor whose IPC hardware unit's unique address provided the match;
(a4) bus access enabling means, for said sending processor, to enable message transfer onto said digital bus means;
(a5) means to receive message data by a receiving processor without interrupting the receiving processor's communications activities;
(b) said digital bus means interconnecting each said processor via its IPC hardware unit;
(c) said common clock means for synchronizing each said address count signal generation means in each of said interprocessor communication hardware units.
6. In a message transfer system for a multiple processor network where each processor connects via a first digital bus means to various network resources such as main memory, an I/O subsystem and a maintenance subsystem, an interprocessor communications (IPC) network comprising:
(a) a plurality of processors connected to each other via a second digital bus means wherein each processor is assigned a unique address value which identifies said each processor and wherein each said processor includes:
(a1) an interprocessor communications hardware unit for sending and receiving messages under the control of its associated processor software, said hardware unit including:
(a1a) control logic means providing an interface between said interprocessor communications hardware unit and said second digital bus means, and including:
(1--1) means to store said unique address value to identify the location of each said processor;
(1--2) means for generating access count values which increment in step sequence to duplicate each unique address value of each of said processor's interprocessor communications hardware unit in said multiple processor network, and including:
(i). means to compare each generated access count value with said unique address value of each said processor's interprocessor communications hardware unit;
(ii). means to continuously repeat said step sequence of access count values;
(iii). connection means to a common clock generation means:
(1-3) means to set a freeze period to freeze said access count value when the value of the said access count value matches the said unique address value of a processor's interprocessor communications hardware unit;
(1-4) means for enabling communication, during said freeze period, so that digital signals can be transferred from said processor, whose unique address value matches the generated access count value, to other processor interprocessor communications hardware units, said digital signals including:
(i). message data;
(ii). access count values;
(iii). strobe for freezing said access count values;
(iv). message acknowledgement;
(a2) said second digital bus means forming said network for connecting each said interprocessor communications hardware unit to each of the said interprocessor communications hardware units of each other processor in the said network;
(a3) common clock generation means connected to synchronize each said means for generating access count signals in each of said interprocessor communication hardware units.;
(b) microcode instruction means, in each processor, for setting said unique address value into each interprocessor communications unit;
(c) said main memory including dedicated message areas for holding messages destined for specific processors;
(d) said maintenance subsystem for monitoring the proper operation of said network.
7. The interprocessor communications network of claim 6 wherein each said processor is granted an access period to said second digital bus means during the frozen time period that the said access count signal is equal to the unique address value of one of said processors, and wherein said maintenance subsystem or a selected processor includes:
(i) means to set the said unique address value of each of said processors in a sequential set of number values to insure that each processor will get said access period to said second digital bus means on a rotational basis when said access count signal matches said unique address value.
8. The interprocessor communications network of claim 7 wherein the enabling of access to said second digital bus for any processor is controlled by the said interprocessor communications hardware unit servicing that processor.
9. The interprocessor communications network of claim 6 wherein said means to store includes:
(a) address register means, holding said unique address value for identifying each particular said interprocessor communications (IPC) hardware unit;
(b) and wherein said means to transmit data includes:
(i). send logic means for sending message data in a multiple message format onto said second digital bus means;
(ii). receive logic means for receiving that portion of said message data on said second digital bus means which is designated for the particular said unique address value of the interprocessor communications hardware unit and its associated processor.
10. The interprocessor communications network of claim 9 wherein said multiple message format includes:
(a) a source address signal;
(b) a destination address signal, said signal including destination addresses for one or for multiple numbers of processors;
(c) a message information signal block which includes equal subsection portions of message data for each one of said processors in said network.
This is a continuation of application Ser. No. 478,813, filed on Feb. 9, 1990, now abandoned.
This disclosure involves a simplified and minimal cost means for enabling communications between processors in a multiple processor network permitting any processor to initiate and receive communication with any other processor in this system.
With the developing complexity of networks and systems for computer communications, there are many applications of multiple processor computer systems in which it is, of course, necessary for each processor to send and receive messages to/from other processors in the system. This type of operation may be designated as "an inter-processor communication net", and such types of communication nets require many different types of communications which may involve:
(1) system initialization status and commands;
(2) system event information such as task completion, notification, and hardware or software interrupt signal information;
(3) signals for assignment of system tasks, jobs, and I/O operations between processing elements;
(4) operator signal inputs and maintenance interface signal conditions involving such operations and halting and/or starting the system into operation.
It is quite commonly known that large multi-processor systems will use a "mailbox" mechanism for purposes of passing messages through specific locations in main memory which routinely stores the instruction microcodes for each processor. However, this type of operation still requires a signalling method wherein one processor may notify another processor that a message or a response is available in that processor's "mailbox". The simple, efficient, "interprocessor communication net" described herein will manage to provide this type of attention mechanism such that a minimum amount of information needs to be transferred.
The presently described system presents a simple, low-cost communication signalling network useful in a multi-processor system network having from one to four main processing units. This arrangement could be called an "interprocessor communication net" or IPC.
Each processor in the network is provided with a hardware IPC unit which connects to the IPC hardware units of each of the other processors.
The IPC unit permits equal access opportunity for each processor to reach into the IPC signal network even though regular processing can continue during the time that signal messages are being transmitted. The IPC unit also permits multiple signal messages to be received and held until serviced by the software of the receiving processor.
Each processor is provided with its own unique IPC address which will have equal access and power on the network.
Any message received by a given processor is handled by the IPC unit hardware which takes care of the network protocols and holds the network information after which it can provide a hardware interrupt to the processor's software to indicate the reception of an IPC message.
A simple access mechanism is used to allow each processor access to the network without affecting any other messages being transmitted. Additionally, a simple fixed message format is used for all messages on the IPC net to permit messages to be sent by any processor to any other processor.
FIG. 1 is a system intercommunication diagram showing the interconnection of four possible processors;
FIG. 2 is a block diagram showing the major elements and interfaces of the IPC hardware units in each processor;
FIG. 3 is a drawing showing the signals on the IPC net;
FIG. 4 is a more detailed diagram of the IPC net devices unit of FIGS. 2 and 3;
FIG. 5 is a more detailed block diagram of the IPC control logic of FIG. 2;
FIG. 5A is a drawing in block form showing the IPC sequence logic of FIG. 5 in more detail;
FIG. 5B is a schematic drawing of the IPC SEND logic block of FIG. 5A shown in more detail;
FIG. 5C is a schematic drawing of the IPC RECEIVE logic block of FIG. 5A shown in more detail;
FIG. 6 shows the protocol format of the IPC messages used in the network;
FIG. 7 is a timing diagram showing the net bus access mechanism;
FIG. 8 is a correlation diagram showing the IPC message protocol operations.
Referring to FIG. 1, there is seen an overall network block diagram of the interprocessor communication net.
A multiple number of processors such as 1P, 2P, 3P and 4P are shown to each have their own individual IPC hardware unit respectively shown as 10, 20, 30 and 40. Each of the IPC hardware units are connected by the IPC network bus 22. The system resources, as main memory 15, I/O subsystem 25, and maintenance subsystem 45, are connected by the resource bus 32 to each of the processors.
Additionally, each of the processors are interconnected to each other by means of a bus 32 which also connects the processors to a main memory 15, and input/output subsystem 25, and the maintenance subsystem 35.
In order to adequately provide for the interprocessor signaling functions, the IPC network provides the following system functions:
(i) allows equal access opportunity for each system processor (1P, 2P, 3P, 4P) to the IPC signal network;
(ii) provides separate, independent IPC logic to allow regular processing to continue while signal messages are being transmitted.
(iii) uses a minimum of normal processing resources to allow regular system processing to proceed;
(iv) provides "soft" addressability of the IPC hardware units, thus allowing the hardware units of all processors to be identical;
(v) allows multiple signal messages to have been received and held until serviced by the receiving processor's software.
The IPC net of FIG. 1 allows up to four processors to communicate with each other. Each processor has a small extra hardware unit added to provide the IPC function, these are shown as units 10, 20, 30 and 40. This hardware is identical for all the processors and the IPC function is controlled by the operating software in each of the processors.
Each processor has its own unique IPC address. This address is a "soft" value and is set up at system initialization time by the maintenance subsystem 35. These addresses will have values of 00, 01, 10, and 11, binary. Each address value has equal access and power on the network. The only address restriction is that any system must have a processor present which has an address of "00". Of course, if more than 4 processors are in the network, then the maintenance subsystem would provide an appropriately longer sequence of address values to identify each processor's IPC hardware unit.
When the operating software in a processor requires a message to be sent to another processor, it will execute an IPC command containing the message to its associated IPC hardware unit (such as 10, 20, 30, 40). This hardware unit will then process and transmit the message over the network. The sending processor is immediately free to continue its normal system processor operations.
When a message is received by a given processor, its IPC hardware unit takes care of the network protocols and holds the message information. It also provides a "hardware interrupt" to the processor software indicating the reception of an IPC message. The processor software can service the interrupt and read the message at its convenience.
If additional messages are received after a previous message has been received (but not yet read by software), the IPC hardware unit will combine it with the previous message, but with no loss of any message information. When the processor software of a given processing unit reads an IPC message, a message buffer in the IPC hardware unit is "cleared".
Since all processors (and all the IPC hardware units) share the same simple IPC network resources, a simple "access mechanism", described in connection with FIG. 5, is used to allow each processor access to the net without affecting other messages being transmitted. Once access to the network has been granted, a simple handshake protocol, described in connection with FIG. 8, is used by the IPC hardware unit to transmit the message.
A simple, fixed message format, described in FIG. 6, is used for all messages on the IPC net. This allows messages to be sent by any processor to any other processor and including itself. This also provides the ability to do an "OR" function or to combine several messages together to be read at one time by the processor software.
In the overall system diagram of FIG. 1, there are shown the system resources such as the main memory 15, the input/output subsystem 25, and the maintenance subsystem 35. This diagram also shows the separate IPC net with its hardware units. This separate IPC facility allows normal processor operations to continue over bus 32 while message traffic takes place on the IPC network bus 22. The extra hardware involved is minimal and inexpensive to the system.
FIG. 2 is a block diagram of the IPC hardware units (10, 20, 30, 40) in each processor and shows the major subunits and interfaces involved. Thus, in FIG. 2, the IPC hardware unit 10 would have a IPC control logic unit 12 and an IPC net devices unit 14. Each of these blocks and subunits are identical for each of the processors involved.
FIG. 3 illustrates the bus connections and signals on the IPC net bus 22. The IPC Net Devices unit 14 connects to the IPC net bus 22 by means of a series of connections, the major connection of which is the IPC data bus 14d of 16 bits. Additional connections between the net bus 22 and the net devices unit 14 are seen as the IPC strobe signal line 14s, the IPC acknowledge signal 14a, both of which are of one-bit size, while the IPC access counter signals are shown on line 14c as composed of 2 bits. The total group of 20-bit lines shown in FIG. 3 may be designated as interconnecting bus 14B which forms the IPC net bus 22. All four of the processors tie into these signals which involve certain usages and protocol which will be discussed hereinafter.
In FIG. 3 it is seen that all the IPC net signals are bi-directional and the designation "-B" indicates an active low signal.
FIG. 4. shows the IPC net drivers and receivers indicating the actual circuit devices of net device unit 14 used to interface to the IPC net bus 22. Each of the devices involved are standard, low-cost devices. The IPC data bus 14d is handled by the use of two 8-bit, bi-directional transceiver chips 141. The control signals 14s, 14a, 14c are outputs from the NAND open collectors 142, 144,146. Each of these signals is split off via inverters 143, 145, 147, and fed back to the control logic 12, FIGS. 2 and 5.
These control signals of FIG. 4 are driven with simple, common-collector NAND gates 142, 144, and 146 respectively, with pull-up resistors on each line. Note that all the signals on the IPC net (FIG. 3) are bi-directional, and that each of these are split into uni-directional signals (FIG. 4) for use in the control logic 12, FIG. 2.
The IPC control logic block 12 of FIG. 2 is shown in expanded form in the diagram of FIG. 5 which indicates the IPC control logic block unit in more detail.
Each IPC unit (such as 10, 20, 30, 40) has a three-bit binary counter called an "access counter" 121 (FIG. 5) which is used for the net access mechanism described in connection with FIG. 7. This access counter 121 can source the IPC net signal lines 22, designated ICTn-B, 14c (FIG. 4) and ICTnOUT of FIG. 5.
Each IPC hardware unit also has a two-bit "address register" 122, FIG. 5, which can be initially loaded by either the maintenance subsystem 35 or by the processor software. This register holds the address value for the particular IPC device hardware unit.
Messages received on the IPC net bus 22 which are addressed to this particular IPC device hardware unit are held in the Receive Register 123 of FIG. 5 which is a 16-bit register. This register can be used to combine numerous numbers of received messages. The register 123 (Receive Register) is read out by the processor software by command.
Each IPC hardware unit (10, 20, 30, 40) has a 16-bit "Send Register" 124 which is loaded by a processor software command. This register holds the message which is to be sent over the IPC net bus 22.
The IPC sequence logic unit 125 is used to control the IPC net protocol which is described in connection with FIG. 8.
The IPC sequence logic unit 125 is shown in more detail in the drawings of FIG's 5A, 5B, and 5C. FIG. 5A shows a drawing of the IPC sequence logic block 125 as divided into a Send Logic unit 125s and a Receive Logic unit 125r. FIG. 5B shows a schematic drawing of the IPC Send Logic block 125s which will be later defined through a set of send logic equations.
Likewise, the receive logic block 125r is shown in schematic form in FIG. 5C and subsequently defined according to a set of logic equations.
In FIG. 5, the input lines to the IPC sequence logic are shown as: the two-bit line for the access counter signal designated ICTnIN; the incoming strobe signal designated ISTBIN; and the acknowledge signal of one bit designated IACKIN. Additionally the sequence logic 125 has a one-bit output signal line for the strobe output designated ISTBOUT and the acknowledge line designated IACKOUT.
IPC PROCESSOR INTERFACE: At the left side of FIG. 5, there is seen a block entitled processor interface 126. This involves the processor software which controls the IPC hardware unit (10, 20, 30, 40) with four commands. These four commands include:
(a) IPC CLEAR COMMAND: This command can be used to put the IPC hardware unit into an initialize state.
(b) LOAD IPC ADDRESS: This command is used to set the IPC address value.
(c) IPC SEND COMMAND: This command initiates the transmission of an IPC message to a processor. The message is loaded into the SEND register, 124 of FIG. 5.
(d) IPC READ COMMAND: This command allows the software to read messages received on the net. When this command is executed and the message has been read, the Receive Register 123 is automatically cleared.
In addition to the four software IPC commands, the IPC hardware unit (10, 20, 30, 40) provides two "status indicators" back to the processor software as follows:
(i) IPC SEND STATUS: This bit can be read by the software. If it is "ON", there is a pending message to be transmitted.
(ii) IPC RECEIVE INTERRUPT: This is a hardware processor interrupt indicating that an IPC signal message has been received and is waiting to be read by software.
IPC MESSAGE FORMAT: FIG. 6 shows the format of IPC messages. This is the format of messages used on the IPC net bus 22, in the Receive Logic 125r and in the Send Logic 125s, FIG. 5A, and over the processor bus 22 to the IPC hardware unit (10, 20, 30, 40).
In FIG. 6, the most significant two bits (15, 14) contain the "source address" which is the address of the sending IPC device unit. If several messages have been combined, then, in the Receive Register (123, FIG. 5), these bits contain the address of the most recently received message.
The next two bits (13, 12) contain the address of the receiving IPC devices (destination address). These two bits are used by the IPC logic to receive or to ignore messages on the IPC data lines 14d. Flexibly, the destination address could be expanded to a universal address which would concurrently transmit a message to each processor in the network so that one sending processor could transmit to multiple processors.
The lower twelve bits (11-0) are used for the actual message signalling information (message information) sent between the processors. This particular field of message information is subdivided into four 3-bit fields. One subfield is assigned for messages destined for each of the four possible processors. Thus, the message information can contain at least one message for each of the four processors.
Each processor can send three bits of signal information to each other processor. The actual definition of these bits is "soft" in nature, but might be used to signal attention, or to specify a message in the message "mailbox", or to designate a response to a previously received message.
Messages can be combined in the Receive Register 123, FIG. 5, of each IPC hardware unit (10, 20, 30, 40). This "combining" is the logical "OR" of previously received messages held in the Receive Register with the incoming message.
Each message that is received will cause an interrupt signal to the processor software, which will then read the message(s) at its earliest opportunity. After the message(s) are read, the Receive Register 123 is automatically cleared.
In regard to the IPC message format shown in FIG. 6, each processor message field is seen to be three-bits long. Thus, each processor can receive three bits of information from each of the other processors, including itself.
These three bits from/to each processor may be described as follows:
(1) PROCESSOR ATTENTION: If this bit is "ON", the sending processor has put a message for the receiving processor in a predetermined "mailbox" in main memory.
(2) I/O INITIATE: When this bit is "ON", the sending processor is signalling the receiving processor to commence the I/O operation that is queued in the I/O Queue in main memory.
(3) I/O FINISHED: When this bit is "ON", the sending processor is signalling the receiving processor that a previously initiated I/O operation has been completed.
IPC BUS ACCESS MECHANISM: The bus access mechanism allows each one of the four processor-IPC hardware units equal opportunity for access into the IPC net of bus 22. Since the mechanism used is very simple, it is also very low in cost.
Each IPC hardware device unit (10, 20, 30, 40) has an IPC access counter 121 (FIG. 5). This counter is a three-bit binary counter which is capable of sourcing the ICTn-B signals (on line 14c of FIG. 4) on the IPC net. Only one processor IPC device unit in the system can actually be the source for the access counter signals at a given time. As a unique IPC address value, the processor and IPC unit with the address value of "00" will be the device to "source" these IPC net signals.
The ICTn-B signals are the upper two bits of the three-bit IPC access counter 121. These are shown on FIG. 5 as ICTnOUT. These signals will be free-running binary count values changing at half the system clock rate. They will run through the values: 00, 01, 10, 11, 00, 01, 10, 11, ... etc.
The value on the ICTn-B lines 14c at any instant provides a "window" for each processor IPC device unit to control the IPC net. For example, when ICTn-B is equal to 00, then the IPC device unit 0 can control the net if it has a message to send; if ICTn-B is equal to 10, then the IPC device unit 2 can control the net if it has a message to send. This is the unit 20 of FIG. 1.
The window value (FIG. 7) on the ICTn-B lines (FIGS. 4 and 5) remains for two system clock-periods before moving to the next window value. If an IPC hardware unit requires the use of the IPC net, it will activate the strobe line ISTn-B, 14s, during its window time. This strobe signal will freeze the access counter 121 at the current value until the strobe signal is deactivated. During this "frozen window" time, (FIG. 7), the IPC device unit (with address 01) will transmit its message via the message protocol. The bus access mechanism is basically shown in FIG. 7.
FIG. 7 is a timing diagram showing the sequence of events involving the bus net "access mechanism". It shows the clock signal, which may be an 8-MHz system clock, wherein all the IPC logic, as well as the processor logic, is made synchronous.
The second line in FIG. 7 shows the ICTO-B signal which is the least significant bit of the two-bit IPC counter signals. These bits count in binary at one-half the system clock rate until the count is frozen (held) by the activation of the IPC strobe signal 14s. This counter provides the access window for each of the four processors into the IPC net of bus 22. Each processor is allowed onto the bus when the counter value equals the value of its unique IPC unit address value. In the example shown in FIG. 7, the processor's IPC unit value is "01" at the "frozen counter".
The third line of FIG. 7 designated ICT1-B is the most significant bit value of the two-bit IPC counter signal.
The fourth line designated "window value" depicts the equivalent arabic number of the binary values of the IPC counter signals discussed above.
The fifth line of FIG. 7 shows the IPC strobe signal ISTB-B, (14s). This signal is the "OR" of all the strobes from each of the four processors. When it is activated by a processor, which it can only do when the counter equals its IPC address unit value, it freezes the current counter value and also signals all processors to receive a IPC message, (as is also indicated in FIG. 8).
ACCESS OPERATION: As seen in FIG. 7, the IPC counter 121 runs continuously until it is frozen. If a given processor needs access to the IPC network, it waits until the counter value equals its own unique IPC address (previously set by software).
When the counter value is "01", the counter signals the processor IPC logic 125, FIG. 5, to activate its IPC sequence strobe signal. This strobe signal goes to all the processors over the IPC network. It freezes and holds the counter at its current value and also notifies all processors to receive a message.
While the access counter 121 is frozen at a given processor's address unit value, that particular processor has access and control of the IPC net and no other processor may drive onto the net.
When the current processor with net access has completed the transmission of its message, it then drops its IPC strobe signals which, in turn, "frees-up" the counter to continue counting through the processor addresses. At this point, the IPC net is free and available to any other processor to use.
The IPC message protocol and operation is shown in FIG. 8. The first line of FIG. 8 shows the window value (as discussed in FIG. 7) with the designation of the signal as the IPC counter signal, ICTn-B.
The second line of FIG. 8 shows the IPC strobe signal, ISTB-B, which is the "OR" of all the individual strobe signals from each processor. Only one processor can drive this at a time. Only the processor whose "address is on the counter" can do the driving. This signal notifies all processors that a message is on the IPC network.
Line 3 indicates the Send Register in the driving processor logic. It contains the IPC message information previously loaded by software. This register drives onto the IPC network 22 via data signals on bus 14d.
Line 4 of FIG. 8 is designated IACK-B and is the IPC acknowledge signal which is the "OR" of all of the individual acknowledge signals from each processor. Again, only one processor can drive this acknowledge line at a time, and only the processor for whom the current message is intended, can do the driving acknowledgement. This processor is specified in bits 13 and 12 (destination) of the IPC message format of FIG. 6. This signal acknowledgement is activated when the receiving processor has received the current message on the bus. The sending processor will deactivate its strobe signal in response to this signal.
The fifth line of FIG. 8 indicates the Receive Register in the receiving processor logic. The incoming IPC message is strobed into this register. This register uses an "OR-ing" mechanism to store the incoming message. That is, the incoming message is "OR-ed" with any previous message still stored in the register. When this Receive Register is loaded, the processor's software is notified to come at its earliest convenience to read the message. When the register is read by software, it is then cleared to zero (empty).
The sixth line of FIG. 8 shows the IPC data bus (14d) which includes the IPC 16 bit network data signals. These signals connect to the transceiver circuits 141, FIG. 4, on all the processors. This is a bi-directional data bus for all IPC messages between all processors. Again, only one processor can drive at a given time, and this will be the sending processor. All of the processors can receive on this bus and the messages on this bus are of the fixed format as shown in FIG. 6.
The seventh line of FIG. 8 is the Send Status line which is an indicator from the IPC logic 12 to the processor software of the sending processor. This indicates whether the Send Register 124, FIG. 5 is full (that is, a message is pending) or is empty (that is, the message has already been sent). The processor software will wait until the previous message has been sent before loading another message for transmission.
The eighth line of FIG. 8 is designated Receive Interrupt. This is a hardware interrupt to the processor software of the receiving processor. It notifies the software of the reception of an IPC message into the Receive Register 123, FIG. 5. It may be noted that sometimes it may take the software some time before it can service this interrupt. Meanwhile, several incoming messages may have been received. When the software finally does read this register, it will actually receive all (several) messages at once.
IPC TRANSMISSION PROTOCOL: When a processor's software needs to send another processor an IPC signal message, it will execute the SEND MESSAGE command to its own IPC hardware unit (10, 20, 30, 40) together with the message to be sent. This message will follow the message format as discussed in FIG. 6. This format will include the proper address values.
Once the software has executed this command, it can continue its normal operations and the IPC hardware unit (10, 20, 30, or 40) will take care of the transmission of the message.
The IPC hardware unit will now contain a message in its Send Register 124, and will take the following steps in order to send it (FIG. 8):
(i) wait for access to the bus 22, that is, wait for its own address window value on the ICTn-B lines;
(ii) activate the IPC strobe signal, ISTB-B;
(iii) wait for the receiving IPC device unit to return the IPC acknowledge signal IACK-B. When the third step (iii) has been done, the message has been sent and received. The IPC hardware unit will indicate to the processor's software regarding the message completion by using the IPC Send Status bit.
The IPC Send Logic 125s (FIG. 5A) and Receive Logic 125r operate independently. The Receive Logic monitors the IPC net at all times by waiting to receive an incoming message. The following conditions will indicate that an incoming message is available and addressed to this particular IPC hardware unit:
(a) The IPC strobe signal, ISTB-B 14s, is active "ON" (14s) (FIG. 8).
(b) The Destination Address field (bits 13, 12), FIG. 6, of the IPC-IN bus are equal to this particular device's Address Register (122, FIG. 5) value.
If the above two conditions are true, then the message on the net is intended for this particular IPC hardware unit and it will be strobed into its Receive Register 123, FIG. 5. The receiving device will then activate the IPC acknowledge signal, IACK-B, 14a, FIG. 4, thus notifying the sending device that the message has been received. The receiving device unit will then notify its processor software with a IPC receive interrupt condition.
Additionally, received messages will be combined into the Receive Register 124 until the software reads it by executing the IPC READ COMMAND at which time the register is cleared.
The previous discussion regarding FIG. 8 showed the IPC net handshake protocol. It may be noted that a receiving device does not necessarily need to respond with an acknowledge immediately, since the sending unit will simply wait until it receives this signal.
IPC SEQUENCE LOGIC: It was previously indicated in FIG. 2 that the IPC control logic block 12 included the IPC sequence logic 125, FIG. 5. This logic is identical for all IPC hardware units in all of the processors involved. This logic controls the IPC net protocol and the access mechanisms. It also provides the status and interrupt indicators to the processor software.
The IPC sequence logic 125, FIG. 5A, can be divided into two independent parts: these are (i) Send logic 125s and (ii) Receive logic 125r. These two parts of this block in FIG. 5A provide the functions that their names imply.
The following Table I for the Send Logic and Table II for the Receive Logic involve certain logic equations which use the following logical symbols where:
* represents the logical AND;
+ represents the logical OR function;
/ represents the logical NOT function;
The "name FF" represents the names of flip-flops.
TABLE 1______________________________________IPC SEND LOGIC______________________________________ISNEN = (IADR = ICTnIN) This is the IPC SEND ENABLE gate which indicates that the Access Count value window is equal to the sender's IPC Address Register.ISNFF set = (IPC SEND COMMAND) reset = STBOUTFF + (IPC CLEAR COMMAND) This is the IPC SEND STATUS FLIP-FLOP which is set by the execution of the software command and reset when the message has been successfully transmitted. Software may also directly reset it by command.ISTBOUT = ISNFF * ISNEN This is the output signal to drive the IPC Strobe signal, ISTB-B.STBOUTFF set = ISNFF * IACKIN reset = IACKIN/ This flip-flop captures the incoming IPC Ack- nowledge signal from the receiving IPC device.______________________________________
TABLE II______________________________________IPC RECEIVE LOGIC______________________________________IRVEN = (IADR = IPC-IN: 13, 12) This is the IPC RECEIVE ENABLE gate which is true when the incoming IPC data bus bits 13 and 12 are equal to the IPC Address reg- ister.IRXSTBFF set = ISTBIN * IRVEN * DIRVRFF/ * CIRVRFF/ reset = ISTBIN/ This flip-flop captures the incoming IPC Strobe signal from the sending IPC device. It only captures the Strobe if the receive enable is true. If the processor software is in the pro- cess of reading a previous message from the Receive Register, this flip-flop will wait to be set after the register has been read and cleared.IRV-FF set = IRXSTBFF * DIRVRFF/ * CIRVRFF/ * ACKOUTFF/ reset = DIRVRFF This is the IPC RECEIVE INTERRUPT indica- tor flip-flop. It is set when an incoming strobe has been captured and the processor is not reading any previous messages. It is reset when the proces- sor reads the current message.ACKOUTFF set = IRXSTBFF * DIRVRFF/ * CIRVRFF/ reset = IRXSTFBB/ This flip-flop drives out the IPC Acknowledge signal to the sending IPC device. It is set when a Strobe has been captured and is reset when the Strobe has been deactivated.DIRVRFF set = (THE IPC READ COMMAND) reset = (BDACK (processor interface signal) This flip-flop controls the transferring of the Receive Register to the processor when the read command is executed.CIRVRFF set = DIRVRFF * BDACK reset = CIRVRFF This flip-flop will clear the Receive Register after the processor software has read it.LIRVR = IRXSTBFF * DIRVRFF/ * CIRVRFF/ * ACKOUTFF/ This gated term will cause the Receive Register to be loaded with the message on the incoming IPC-IN bus.______________________________________
Described herein has been a simple, low-cost communication network for multiple processor systems for up to four processors. With the addition of a simple, low-cost interprocessor communication hardware unit attached to each processor and connected by an interprocessor communication net bus 22, it is possible to pass messages to and from each and any of the processors without significantly disturbing normal operations of any of the processors with the network resources such as main memory, the I/O subsystem and the maintenance subsystem.
The IPC hardware unit uses standard industry drivers and open collector gates to drive the bus permitting minimal cost units to be involved. Further, the bus interconnection between the processors is by means of standard, off-the-shelf ribbon-type cable.
While the disclosure of the preferred embodiment described herein involved four processors, the concept is not limited to four processors only. Thus, by simply widening the IPC data bus 22 and the width of the address fields, there is simple provision for expanding the number of processors that can be involved in the network.
Thus, while the preferred embodiment of the invention has been described in a detailed structure, it is also possible for other implementations to be developed which fall within the scope of the appended claims herein.
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House Bunny star Anna Faris plays in the ocean after reportedly marrying fiance Chris Pratt this weekend. Sources say the pair married in a small ceremony on Saturday after announcing their engagement earlier this year.
Last month Anna hinted the couple would "slip off and elope" to avoid the pressure of a big wedding. Chris reportedly told RadarOnline, "I'm a very happy guy. We're in Hawaii having a wonderful time."
Their love looks real, but is he kidding with those American flag trunks?[Photos: Splash News Online]
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In my opinion, Deputy Peter is doing a fine job. If this arrangement saves money and the deputies in Williams are also policing our city, why go back to our own Police Department? This is working. If other big cities are doing away with their own police departments, Auburn can do it too. If the city would decide to have our own department, I would hope it would be opened up to other applicants. I can't see re-hiring Poltorak if he's unable to work. A new police department should start over completely, new people, new perspectives, new ideas. No agendas, no favors, no more "you scratch my back, I'll scratch yours." As far as the above statement about local police having more time and getting to know the citizens, I would have to say that I have seen Deputy Peter around a lot more than Poltorak, ever. I'm sure he's gotten to know the citizens and business owners and has become familiar with our city, just like any new person hired would also have to.
The only good thing about the dash cam video (yes I watched it) is that you can see the car was surrounded by emergency personnel. I'm sure after reading the article in the Toledo Blade that they did everything they could to comfort and help the girls in the car. Still, so very sad and tragic. I still haven't read anything to say why the woman was driving the wrong way.
Not in complete agreement there. I would rather spend time with my pets than most people I meet and see on a daily basis.
It all depends on the type of patrons he wants to draw into his bar. If he wants to keep it family, a place where you can take your kids for a dinner or burger, or whatever, then that's one thing. I can't imagine a topless bar in little Crump, a farming community. With one of the other pictures of the guys belly up to the bar, it shows the patrons it might draw in!! It just seems disgusting to me. And to beetlebomb, how would you feel if the " bare breasts and smiling faces" greeting drooling men belonged to your daughter, wife, sister, or some other female relative??
Just a little FYI cityworker, I have never had a ticket in over 40 years of driving. I never said that Sly just sat around Western "where the kids hang out" either. So glad that you did your research and called all over the state to prove Sheriff Miller wrong. Well done. Most of this issue is tugging at peoples heart strings because Sly has been here forever. That is no reason not to merge with Williams for better coverage by the Sheriff Dept. Who wouldn't want that?
Personally, I feel sorry for the deputy to have to finish out his time in the city. People are so angry over this, as I have witnessed at the meetings. Yes, cityworker, I did go. I wanted to see the show. And in closing, aren't we all "behind a computer screen" while we are voicing our opinion here? Even you??
I say renew the contract with Bay County Sheriff! Yes ThreeG's, we may not have to lock our doors, but I can guarantee it isn't because of Sly. He hasn't been patrolling our neighborhood. We don't see him around here. We actually have seen the sheriff deputy more than we have seen Sly in the 25 plus years we have lived here!! It is a comfort to see that old patrol car with the deputy in it drive through our neighborhood. We've never had our home vandalized, but again, not because of Sly. I think when his day is over, he's gone! He doesn't know what goes on around town when he's not on duty. He doesn't come around here after hours. And so what if he has to respond to a call if he's not on duty?!?!? Isn't that part of the job?!? ThreeG's, you must live by Western somewhere where Sly usually patrols looking for kids. That would explain his presence in your neighborhood and not in ours. I agree with yamon7. We too will request the State Police or Bay County Sheriff if we have a need for police. We have had to call the police 3 times in our over 25 years in Auburn. Jim Klann responded twice and was very professional. Sly came the 3rd time and was not helpful at all. Too bad this can't be voted on again now that the Sheriff Deputy has been on duty. I bet the outcome would change. The commissioners that voted yes have this agenda to keep Sly around town no matter what. How sad. Bring in a chief from out of town like was suggested earlier and let him clean house!!
I'd like to know who witnessed the Deputy patrolling outside of Auburn. Who has time to follow the Deputy around and make note of the stops he makes, dates, times, where he patrols, and what he does while on the clock? Has anyone followed Sly recently and seen what he does while on the clock?


text: No recent wiki edits to this page. Konga was a chimpanzee who, due to the mad science of one Professor Charles Decker, was turned into a 30 foot tall gorilla. Mind controlled by Decker Konga was killed at the end of issue #1. In issue 2 however we find that the death from the first issue had not taken and for 22 more issues, along with an annual, and a few "special issues," Konga, the little chimp that grew, faced a slew of aliens, dictators, mad scientists, giant robots, great white hunters and monsters until he lumbered off into comic book limbo. The comic that did better than the film on which it was basedBut then as the film was originally to be called "I was a teenage gorilla" until they went with Konga instead, it would have to be. Part of a trilogy of monster books by Charlton in the early 60's based on B-Movies where the comics then took over the story where the films left off after issue # 1 and then continued apart from the movie version, Konga was a surprise hit for minor league Charlton Comics, as was their second try Gorgo, the third try, Reptilicus, not so much, lasting on two issues, after which it was changed to a slightly different monster not based on the movie when for another 6 issues.


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The COEs bring local expertise and skills to advance our global business strategy. In conjunction with EMC business units, the COEs are responsible for the development of many products across EMC's broad software and hardware offerings, and for providing global services support to EMC customers worldwide. Additionally, the COEs provide back office processing activities for internal operations.
The COEs have been designed to provide EMC business units with world-class talent, infrastructure, and management to deliver to the needs of EMC's customers. EMC business units are, in essence, internal customers of the COEs. Each COE is managed locally, and a cross-functional leadership team consisting of EMC's senior executives oversees strategy and investment decisions. Nearly 100 percent of senior management at the COEs is hired from the local community.
One unique advantage of our COE model is that employees from different business units have more opportunities for collaborative innovation. Each year, the COEs contribute a high percentage of submissions to EMC's annual worldwide Innovation Roadmap, and they play a part in hosting the global event.
Our COEs are highly collaborative and work closely with University Relations, the Academic Alliance, Corporate Training, and the Innovation Network on local recruiting strategies. Although many technology companies are seeking to hire top talent in our COE locations, we have kept attrition rates below the market average by focusing efforts on employee retention, including benefits, work environment, career development, and compensation. In addition, sustainability teams at our COEs met three times in 2013 to share best practices and improve their programs.
Expansion is based on business unit demand for talent. Current COEs will continue to grow as necessary, and we will continue to explore new locations that could best serve the needs of the business. To meet the growing needs of customers in the Western Hemisphere, we opened a new COE in Utah in 2013. Near term, this center is focused on the service needs of customers in North and South America, allowing us to provide better business hour alignment and support in Spanish, Portuguese, and English. In addition, as part of a $100 million USD investment in Brazil, EMC has opened the Brazil Research and Development Center in the heart of the Rio Technology Park on the campus of the Universidad Federal de Rio de Janeiro.
Managing Change
The world of IT is evolving rapidly, requiring EMC to be adaptive and flexible as companies, technologies, and markets change. Though industry consolidation, acquisitions, and restructuring have become common in the 21st century, we work hard to make transitions as smooth as possible for employees in order to retain top talent and preserve relationships.
Retaining top talent is one of the primary goals following any merger or acquisition. Early in the process, we create an assimilation plan to balance integration into EMC, while maintaining important aspects of the acquired company's culture.
In the course of conducting normal business operations, EMC is occasionally required to reduce headcount in certain areas of the business, reallocate investments, de-emphasize less productive initiatives, and focus new investments in areas of opportunity. Any of these actions can result in valued employees leaving our business involuntarily. EMC takes these actions only after thoughtful consideration and with an empathetic understanding of the impact our actions can have on the lives and careers of our team members. For example, we began offering an early retirement program in 2013 to help mitigate some of these impacts. We also work to exhaust all options before making the difficult decision to reduce the size of our workforce.
When our changing business needs require reducing employment in a particular location or organization, we work with impacted employees to attempt to redeploy them to other growth areas of the business whenever possible prior to taking the taking the difficult action of severing employment. When we do have to make reductions, we offer global job search assistance provided by a third-party organization and paid for by EMC, in addition to providing separation pay and benefits. In either case, our mission is to ensure each individual is treated with dignity, compassion, fairness, and respect.


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agents enquiry
This site is for use by Gold Cover Agents only.
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For over 25 years Gold Cover has helped
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affinity groups.
Contact Tel: 01892
here to see a list of destinations for which cover is
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Registered Office: 146 New
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- Willamette
- Athletics
- News Archive
- 2006
- September
- Willamette Plays 14th-Ranked UC-Santa Cruz to 0-0 Tie in Two Overtimes, as Both Teams Remain Undefeated
Women's Soccer | Wednesday, September 13, 2006
Willamette Plays 14th-Ranked UC-Santa Cruz to 0-0 Tie in Two Overtimes, as Both Teams Remain Undefeated
SALEM, OR -- Willamette University and the University of California-Santa Cruz played to a 0-0 tie in two overtimes on Wednesday, Sept. 13 at Sparks Field. Shutouts were earned by Kari Woody (Sr., GK, Boise, ID/Timberline HS) of Willamette, with three saves, and by Katie Loomis (Fr., GK) of UC-Santa Cruz, who made four saves.
Both teams remained undefeated, as the Bearcats moved to 3-0-1 and the Banana Slugs went to 4-0-2. UC-Santa Cruz entered the game ranked 14th in the nation in this week's NSCAA/Adidas Poll for NCAA Division III.
The game featured quality play from both teams in the match-up of Top 10 teams in the NSCAA/Adidas West Region Poll. UC-Santa Cruz was ranked #2 in the Region, while Willamette was tied for #4.
The Banana Slugs recorded 15 total shots, while the Bearcats earned 14 total shots. Even so, quality scoring chances were at a minimum, as both teams played well on defense. Willamette managed four shots on goal and UC-Santa Cruz took three shots on goal.
Several of the best scoring opportunities were earned in the final 10 minutes of regulation. At 82:11, Willamette's Susan Butler (Sr., MF, Boise, ID/Boise HS) headed the ball near the goal, but her shot was blocked. With 5:19 left, Karli Cowman of Santa Cruz took a hard shot at Woody, but the WU goalie recorded the save and held on to the ball, as another UCSC player approached for a rebound.
With just 43 seconds on the second-half clock, Annick Lamb of UCSC received a pass inside the penalty area, with only Woody to beat. She fired the ball from about seven yards out, but her shot smacked into the crossbar and was eventually cleared.
In the first overtime, Willamette achieved one shot . UC-Santa Cruz registered two shots during the second overtime. The only shot on goal of the extra sessions was by Lamb, whose shot with 5:05 left in the second overtime was easily saved by Woody.
The Bearcats were credited with six corner kicks. UC-Santa Cruz earned five corners. Willamette was called for 14 fouls and the Banana Slugs were whistled for 11 fouls.
WU concluded its season-opening, four-game homestand. The Bearcats open Northwest Conference play this weekend, at Whitman College in Walla Walla, Wash., on Saturday, Sept. 16 and at Whitworth College in Spokane, Wash., on Sunday, Sept. 17. Both games are scheduled to get underway at 12 p.m. (PDT). Whitworth is ranked 22nd nationally in NCAA Division III and is currently ranked #3 in the West Region.


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Bob's Red Mill, Baking Powder, Gluten Free, 16 oz (453 g)
Haven't had a chance to try this
Posted by mirindalikethedrink on Feb 27, 2014
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SAVE THE DATE, November 20th at 6:30 PM is our Third PACK MEETING of the year at the Fellowship Hall building of Oak Grove United Methodist Church (OGUMC).
*(As a request, PLEASE BRING A CANNED FOOD ITEM FOR THIS EVENT as your entry to this event.)
Special Notes
SEE BELOW - for a new video on Pack 577's trip to Patriot's Point, Charleston, SC. A GREAT TIME was had by all!! "THANK YOU!" Bill Denman for not only coordinating this trip but the wildly popular Trailblazer Camp Out as well!
THANK YOU for all that attended and served during Oak Grove United Methodist Church's 53rd Annual Barbecue. I believe it was a great success. Thanks goes out to our Scout Liaison, Bill Berg, for spearheading the event for our Troop and Pack!!
New Scout Sign-up Day Results
We had a great showing of new and eager young Cub Scouts that wanted to join our Pack on the evening of the 28th of August. Currently we have roughly (61) new Cub Scouts to fill our Pack out with excitement for new adventures. THANKS go out to everyone that both joined and supported the evening making our Pack 577 one of the top Packs in the Atlanta Council!!! Currently, we are (172) boys strong!!
If you would like to still experience what PACK 577 has to offer, it's not to late!
Look below to get your son started with Cub Scouting!
Download the registration info below and email us at email@example.com if you're interested in joining our Pack.
Our Story and Overview...
Pack 577 started in 1961 and has a rich history of teaching youth from the first to fifth grade. We are part of the Hightower District of the Atlanta Area Council Boy Scouts of America. Our Pack is sponsored by the Oak Grove United Methodist Mens Fellowship of Oak Grove United Methodist Church.
Our pack is one of the largest in Atlanta. Each year, more than 150 boys participate in our activities. We have our monthly pack meetings usually on the 3rd Thursday of each month from 6:30 to 7:45 in the Fellowship Hall of Oak Grove United Methodist Church. Our dens meet a different times of the month based on the schedule set with each den leader and the boy's parents.
Our main goal is to make sure our Cub Scouts have fun, while learning valuble skills that will serve them throughout their lives! We do this by teaching our boys outdoor skills, sportsmanship, how to work with others, citizenship and more.
Our pack is supported by more than 40 parent volunteers, the parents of our Scouts. They serve in many ways, as Pack or Den leaders, camping coordinators, coordinating our Pinewood Derby, etc.
The video below will give you and your son a great feel for our annual activities. The calendar will give you dates for our upcoming events.
Each year, our Pack raises funds to support our program by selling popcorn. This income supplements annual dues of approximately $75.00 dollars.
Key contacts in our pack are:
Den Leaders for 2014 include:
(FYI - We ALL are volunteers in Scouting. We are one of the largest Packs in both the Atlanta Area and the State. That can only be achieved by GREAT LEADERS and families that make Scouting fun and supporting one another while still maintaining very busy schedules at home.
The following is a list of our NEW TIGER DEN LEADERS! (46) Boys:
Tiger Den #1 Jason Daffner (12) boys
Tiger Den #2 Bruce King (11) boys
Tiger Den #3 Ben Bryant (10) boys
Tiger Den #4 Mike Cottrell & Scott Cobbs (13) boys
Advancing Dens of (126) Boys:
Wolf Den #1 Shane Griffin, Assistant - Russell Fair (13) boys
Wolf Den #2 Eva Van De Water, Assistants - Jeffrey Russell & Carol "Taylor" Taylor (13) boys
Bear Den #2 Anupam Narula, Assistants - Brad Hayes & Michael "Mick" West (15) boys
Bear Den #3 Dan Bridges, Assistants - Bill Denman & Paige Payne (15) boys
Bear Den #7 Chadwick "Chad" Payne, Assistant - Michael "Mike" Starr (13) boys
Webelos 1 Den #1 Tom Rowland, Assistants - Shane Griffin & Bryan Bassett (10) boys
Webelos 1 Den #2 Brantt Hudson, Assistant - Bryan Martin (12) boys
Webelos 1 Den #3 Lukasz Arendt, Assistants - Russell Fair & Michael Smith (10) boys
Webelos 2 Den #2 Greg Brass, Assistant - Robert Martin (10) boys
Webelos 2 Den #3 Bill Denman, Assistant - Michael Schneider (15) boys
Registration and 2014-15 Calender
2014 New Scout Registration Packet - Read this for all the info you need to sign up you son with Pack 577
Pack 577 2014-15 Calendar
Take a minute also check us out on Facebook at Pack 577.
Pack 577 is part of the Hightower Trail District (www.hightowertrailbsa.com). For more information about scouting in general, please visit the national Boy Scouts of America website.
Patriot Point visit in Charleston, SC - October 11-13th, 2014
A BIG "Thank You!" goes out to parent, William Higgins, for capturing these moments and putting it together in a video for all to see.
Click here to go to ScoutTrack.
Visit Boy Scout Troop 77.


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Office of Academic Assessment
Choosing Assessment Strategies
The links below will provide you with a variety of methods for assessing student learning. While you will see some ideas repeated across the links, each will provide a slightly different frramework for thinking about what you want to assess and how you might do so.
For wide-ranging lists of resources, the following:
Internet Resources for Higher Education Outcomes Assessment
National Institute for Learning Outcomes Assessment (NILOA)
The links below are organized into four sections--Books from the Assessment Library; Lists of Methods; Tests, Etc.; and Advantages and Disadvantages of Selected Methods.
Books from the Assessment Library
Links to additional resources for rubrics:
•For links to a variety of rubrics, click here.
•For a web page with more assorted rubrics, click here.
•For selected service learning rubrics, click here.
•For rubric rating descriptors, click here.
Lists of Methods
Assessment Instruments and Methods Available To Assess Student Learning In the Major
Divides assessment strategies into direct and indirect measures and provides a description of each. From the University of Wisconsin-Madison.
Assessment Strategies and Methods
See Chapter 4 of this manual from the University of Massachusetts Office of Academic Planning and Assessment, Program-Based Review and Assessment; Tools and Techniques for Program Improvement.
Explains how and why to create strategies for authentic assessment ("A form of assessment in which students are asked to perform real-world tasks that demonstrate meaningful application of essential knowledge and skills"-- Jon Mueller)
Knowledge surveys offer a way to measure student knowledge at the beginning and the end of a course, as well as to provide them with an overview of the learning expected in the course.
Measuring Quality; Choosing Among Surveys and Other Assessments of College Quality
From page 2 of this 44-page document from the American Council on Education and the Association for Institutional Research: "The purpose of this guide is to articulate a set of questions and issues that campus leaders can review when deciding whether to participate in a given survey or use a specific assessment instrument. The guide also describes some of the major national surveys and assessments."
This page provides a variety of selected resources on portfolios and e-portfolios, with links to articles, web pages, books, and more.
Selecting and Implementing Assessment Methods
From the Learning Outcomes Assessment Planning Guide from California Polytechnic Institute. Provides a list of methods with brief descriptions of each.
Tests, Etc.
Resources Related to Tests, Surveys, Portfolios, and Curriculum Mapping
A variety of resources from the National Institution for Learning Outcomes Assessment.
An Inventory of Instruments, Tools and Resources
A searchable database from the Association for Institutional Research.
First Year Assessment Instrument Database
A searchable database from the National Resource Center for the First Year Experience and Students in Transition.
Nuggets and scalets are groups of questions from the National Survey of Student Engagement which can be used to gather information on specific behaviors--e.g., writing, higher order thinking skills, collaborative learning, etc. Information can be gained from administration of NSSE at UNI; NSSE questions can also be used in program assessment surveys, with permission from NSSE. For more information, contact the UNI Office of Academic Assessment. The link for this entry will provide an overview on these resources. For more information on scalets, click here.
In 2013 the National Survey of Student Engagement was revised to increase emphasis on teaching and learrning. For access to NSSE data for UNI, contact the Office of Academic Assessment.
Advantages and Disadvantages of Selected Methods
Evaluating Assessment Strategies
See information beginnon page 14 of this resource from APA Online for advantages, disadvantages, and recommendations for a variety of assessment techniques, as well as other useful information on assessment.
For additional information, go to Internet Resources for Higher Education Outcomes Assessment and look for "Grades as outcomes assessmen"t
Assessment Methods: A Close-Up Look
This document by Barbara D. Wright, Assessment Director at Eastern Connecticut State University, suggests advantages and disadvantages for a variety of assessment strategies.


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Do-Over: State Republicans Plan Second St. Charles Caucus
Categories: Follow That Story, Politics
|David Cole, Chairman of the Missouri GOP, will run the new caucus.
There will be a few key changes made to the procedure, however.
David Cole, chairman of the Missouri Republican Party, will serve as temporary chair this go round, and he's promising "a fair, honest and transparent manner" at the proceedings. That will be in stark contrast to the last one, which broke down in a screaming match with some vocal supporters of Ron Paul, and then ended in two arrests and nothing much accomplished other than embarrassment for all involved.
It was the appointment of a caucus chairman without putting it to a vote that set off last Saturday's brouhaha, so hopefully everybody is comfortable with Cole running the show. If not, I'm sure we'll hear about it soon enough -- recording devices are permitted at this new caucus.
Sponsor Content


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Kessler takes advice from Heisman winnerOctober 18th, 2013, 9:30 am by By RICH HAMMOND
The words came from a tailback, a legendary one, so the quarterback listened.
``When Marcus Allen came in, he couldn't have said it better,'' USC quarterback Cody Kessler said. ``He said, `This is your team. You're the quarterback and these guys are going to play for you and you have to play for them.' I feel like I really have done that and that everyone has bought in.''
Allen, who won the Heisman Trophy at USC in 1981, spoke to the team last week and had a few extra words for Kessler, but the sophomore quarterback appears increasingly comfortable in his new role.
Kessler is coming off his most prolific game of the season, a 297-yard, two-touchdown, no-interception victory over Arizona, and on Saturday he will face a Notre Dame defense that is stout at the line of scrimmage but has some questions in the secondary.
Inconsistent in USC's first two games, when he had to split time with Max Wittek, Kessler has been far from perfect in his last six games but, in total, has made more positive plays than negative.Read the rest of this entry »