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A dual clock tracking decoder for use in a local station of a token ring local area network extracts the mostly repetitive bit-cell transitions corresponding to the imbedded clock of a received phase encoded message from which a short term and a long term moving average estimate is made of the clock transitions relative to a local stable clock. The short term moving average adjusts rapidly to short term jitter and is used to sample the received phase encoded message twice each bit-cell and generate an intermediate phase encoded message that is resynohronized with a clock derived from the long term moving average of the estimated imbedded clock transition and having a rate that is twice the bit-cell rate of the received phase encoded message. This provides a mechanism for sampling the states of the incoming message with a clock that is adaptive to fast short term jitter while restoring an imbedded clock that is only responsive to slow longer term jitter. The latter clock is used to resynohronize the intermediate phase encoded message.
1. A dual clock tracking decoder circuit for use in a communications system for regenerating a received binary phase encoded message, hereinafter referred to as the input message, with a prescribed bit rate by extracting an embedded clock in the input message, the embedded clock having a rate that is twice the prescribed bit rate, and regenerating the input message by resampling the input message once during each half-bit cell, the dual clock tracking decoder circuit comprising:
(a) a first clock decoder circuit with an input for accepting the input message, the first clock decoder circuit for recovering from the input message, and outputting at an output, a first clock signal with a rate that is twice the prescribed bit rate, the first clock decoder circuit configured to be tolerant to incoming phase jitter;
(b) a second clock decoder circuit with an input for accepting the input message, the second clock decoder circuit for recovering from the input message, and outputting at an output, a second clock signal with a rate that is twice the prescribed bit rate, the second clock decoder circuit configured to reduce accumulated jitter;
(c) a first sampling circuit with an input for accepting the input message, a sampling control input connected to the output of the first decoder circuit output for generating at art output a first resampled message that is a representation of the input message and is synchronous with the first clock signal; and
(d) a second sampling circuit with an input connected to the output of the first sampling circuit for accepting the first resampled message, a sampling control input connected to the output of the second clock decoder output for producing at an output a second resampled message as a representation of the input message that is synchronous with the second clock signal.
2. The dual clock tracking decoder circuit of claim 1 wherein the first clock decoder circuit and the second clock decoder circuit comprise:
(a) a state transition detector circuit with an input for accepting the input message and producing at an output a signal representative of the input message state transitions location in each half-bit cell of the input message,
(b) a filter having an input connected to the state transition detector circuit output for producing, at an output, a signal representative of a moving average of the state transition locations in each half-bit cell of the input message, and
(c) a clock generator circuit with a control input connected to the filter output for to controlling the location of an output clock state transitions corresponding to the filter output signal,
the filter of the first clock decoder circuit having a wider bandwidth than the filter of the second clock decoder circuit.
3. The dual clock tracking decoder circuit of claim 2 wherein a single state transition detector circuit is commonly shared by the first clock decoder circuit and the second clock decoder circuit.
4. The dual clock tracking decoder circuit of claim 3 wherein the input to the filter of the second dock decoder circuit is the output of the filter of the first clock decoder circuit for sharing the filter of the first clock decoder circuit resources and for effectively reducing the bandwidth of the filter of the second clock decoder circuit.
5. The dual clock tracking decoder circuit of claim 1 wherein the first sampling circuit and the second sampling circuit each comprise a D-type flip-flop.
6. The dual clock tracking decoder circuit of claim 1 wherein the first clock decoder circuit, the second clock decoder circuit, the first sampling circuit, and the second sampling circuit are digital circuits.
7. The dual clock tracking decoder circuit of claim 1, wherein the communications system comprises a Token-Ring local area network.
8. A dual clock tracking decoder circuit for use in a communications system for regenerating a received binary phase encoded message with a prescribed bit rate, the received binary phase encoded message hereinafter referred to as the input message, the dual clock tracking decoder circuit operating synchronously with a local stable clock having a clock rate that is twice the prescribed bit rate, the dual clock tracking decoder circuit operating by extracting an embedded clack in the input message, the embedded clock having a rate that is twice the input message bit rate, and generating a recovered clock, comprising:
(a) a first clock decoder circuit and a second clock decoder circuit for recovering a clock signal from the input message, both the first clock decoder circuit and the second clock decoder circuit comprising,
(i) an input for accepting the input message,
(ii) a transition detector circuit connected to the input for detecting and outputting a sequence of state transitions in the input message, each state transition corresponding to an embedded clock pulse edge,
(iii) an encoder circuit connected to the transition detector circuit for generating a location signal representative of each state transition location relative to pulses of the local stable clock,
(iv) a filter connected to the encoder circuit output for generating at an output a moving average of the location signal, and
(v) a clock waveform generator connected to the filter output for generating a recovered binary clock signal at an output with the rate of the local stable clock, each recovered binary clock signal pulse location corresponding to the momentary value of the moving average of the location signal relative to the pulses of the local stable clock, the filter of the first clock decoder circuit having a faster response time than the filter of the second clock decoder circuit;
(b) a first sampling circuit with a data input for accepting the input message, and a sampling input connected to the output of the first clock decoder circuit for producing an output signal at an output by sampling the input message synchronously with the recovered binary clock signal of the first clock decoder circuit; and
(c) a second sampling circuit with a data input connected to the output of the first sampling circuit and a sampling input connected to the second clock decoder circuit for producing a signal representative of the input message with state transitions that are synchronous with the recovered binary clock signal of the second clock decoder circuit.
9. The dual clock tracking decoder circuit of claim 8 wherein the local stable clock operates at a rate of 32 MHz.
10. The dual clock tracking decoder circuit of claim 9 wherein the filter of the first clock decoder circuit has an approximately 1 MHz bandwidth and the filter of the second clock decoder circuit has an approximately 330 KHz bandwidth.
11. The dual tracking decoder circuit of claim 10 wherein the filter of the first clock decoder circuit and the filter of the second clock decoder circuit are digital single-pole low-pass filters.
12. The dual clock tracking decoder circuit of claim 8 wherein the first sampling circuit and the second sampling circuit each comprise a D-type flip-flop.
13. The dual clock tracking decoder circuit of claim 8 wherein the first clock decoder circuit, the second clock decoder circuit, the first sampling circuit, and the second sampling circuit are digital integrated circuits.
14. The dual clock tracking decoder circuit of claim 8 wherein communications system comprises a Token-Ring local area network.
15. A method for use in a communication system with a prescribed bit-cell rate for regenerating a binary phase encoded received message at a local station having an imbedded clock with a rate that is twice the prescribed bit-cell rate, the local station having a local stable clock with a rate equal to twice a token ring local area network bit-cell rate, the method comprising:
(a) accepting the binary phase encoded received message;
(b) generating a short term average clock from the imbedded clock with the rate of the local stable clock;
(c) generating a long term average clock from the imbedded clock with the rate of the local stable clock;
(d) sampling the binary phase encoded received message using the short term average clock to produce a binary output signal synchronous with the short term average clock and representative of the binary phase encoded received message; and
(e) resynchronizing by sampling the binary output signal using the long-term average clock.
16. The method of claim 15 wherein the communication system comprises a Token-Ring local area network station.
17. A method for regenerating a received binary phase encoded message in a communications system at a local station having a stable local clock with a rate equal to twice a bit-cell rate of a token ring local area network, the received message having an imbedded clock with a rate equal to twice the bit-cell rate of the token ring local area network, ale method comprising:
(a) receiving the binary phase encoded message;
(b)extracting pulse transition locations from the imbedded clock;
(c) forming a short term moving average of the pulse transition locations;
(d) generating a first clock with a rate equal to the stable local clock rate and with clock pulse edges corresponding to the short term moving average of the pulse transition locations;
(e) sampling the binary phase encoded message using the first clock and generating a first binary message corresponding to the sampled message;
(f) forming a long term moving average of the pulse transition locations;
(g) generating a second clock with a rate equal to the stable local clock rate and with clock pulse edges corresponding to the long term moving average pulse transition locations;
(h) resynchronizing the first binary message by sampling the first binary message using the second clock and generating a regenerated binary phase encoded message corresponding to the first binary message.
18. The method of claim 17 wherein the communication system comprises a Token-Ring local area network station.
19. A dual clock tracking decoder circuit for use in a communications system for decoding and regenerating phase encoded data having an embedded clock, the dual clock tracking decoder circuit comprising:
(a) a wideband clock decoder circuit for recovering and outputting a first clock signal from an input message, the wideband clock decoder circuit including a first filter;
(b) a narrowband clock decoder circuit for recovering and outputting a second clock signal from the input message, the narrowband clock decoder circuit including a second filter, the second filter having a narrower bandwidth than the first filter;
(c) a first sampling circuit coupled to the wideband clock decoder circuit for receiving the first clock signal, the first sampling circuit for receiving the input message and outputting a first resampled message based upon the input message, the first resampled message being synchronous with the first clock signal; and
(d) a second sampling circuit coupled to the first sampling circuit and the narrowband clock decoder circuit for producing a second resampled message corresponding to the first resampled message that is synchronous with the second clock signal.
20. A method for regenerating a received binary phase encoded message by a dual clock tracking decoder circuit in a communications system, the dual clock tracking decoder circuit including a wideband clock decoder circuit and a narrowbad clock decoder circuit, the received binary phase encoded messages having an embedded clock, the method comprising the steps of:
(a) recovering a first clock signal from an input message using a first filter of the wideband clock decoder circuit;
(b) recovering a second clock signal from the input message using a second filter of the narrowband clock decoder circuit, the second filter having a narrower bandwidth than the first filter;
(c) generating a first resampled message based upon the input message, the first resampled message being synchronous with the first clock signal; and
(d) outputting a second resampled message corresponding to the first resampled message that is synchronous with the second clock signal.
This invention relates to the field of recovering clock and regenerating data information from a phase encoded binary signal, such as in a token ring local area network station. The decoder and clock recovering circuit is suitable for metal oxide semiconductor (MOS) and complementary metal oxide semiconductor (CMOS) implementation.
Phase encoding techniques are employed for single transmission channel systems in which the clock for synchronous data detection at the receiver is combined with the data stream to produce a single transmitted signal. At the receiving station, the synchronous clock is extracted from the single transmitted signal and the clock is then used to synchronously decode the data.
FIG. 1 shows several examples of phase encoded signals corresponding to the un-encoded data in line (a), including: Manchester code, line (b), in which each bit-cell interval, Tp, is occupied by a doublet that switches from high-to-low or low-to-high at the bit-cell interval center (Tp/2), where the value of the doublet in the last half interval, Tp/2 to Tp, assumes the value of the corresponding data bit; Differential Manchester code, line (c), wherein each bit-cell interval, Tp, is occupied by a doublet and the value of the corresponding bit is indicated by the transition, or lack of transition, at each bit-cell boundary, with a boundary transition corresponding to an un-encoded zero (low logic level), and a lack of level transition corresponding to a one (high logic level); frequency modulation (FM) code, line (d), in which the unencoded bit is represented as doublet within a bit-cell if the corresponding bit is a one, and by a constant high or low level over the bit interval if the corresponding bit is a zero, the doublet initial value and the instant value chosen so that a transition occurs at every bit boundary; and Miller (or modified FM) code line (e), in which a constant low or high level over a bit interval corresponds tp a zero, and a doublet corresponds to a one, with the constant level state and the initial doublet level state determined by the final state of the previous encoded bit.
Both Manchester codes produce encoded signals with transitions at each bit interval centers and data dependent transitions at the bit boundaries. The FM and Miller codes produce data dependent transitions at each bit interval center. However, the FM code produces a transition at each bit boundary while the Miller code produces a bit boundary transition only between successive unencoded zeros.
Clearly, decoding of these codes requires observing (sampTing) the encoded waveforms during a proper time interval, in each bit interval, in order to determine the state of the encoded bit. For the Manchester code, recognizing the direction of the mid-bit-interval transition or the state of the doublet during the last half of the bit interval decodes the information. For the Differential Manchester code, data is decoded by detecting if a transition occurs at the bit boundary or by exclusive-ORing corresponding half bit-cell states of successive bit-cells. The FM and Miller codes are decoded by detecting if a center bit-cell transition occurs. Hence, the first step in decoding a phase-encoded signal is the extraction of the clock from the received signal because, given the clock signal, an appropriate control signal for observing the encoded waveform at periodic bit intervals, Tp, can be constructed by introducing a delay relative to the extracted clock transitions.
The prior art methods of decoding phase encoded binary signals is represented in FIG. 2. The phase encoded binary data signal is applied to input 11 which is connected to the input of the clock decoder 12 and data decoder 13. Clock decoder 12 operates with a local clock that is closely matched to the transmitter clock embedded in the phase encoded signal, accepts the input signal and operates on the state transitions of the input signal to produce at its output a signal, RXC, which is representative of the original transmitter clock embedded in the encoded data. The reconstructed clock signal, RXC, is used by data decoder 13 to extract the data from the phase encoded input signal. Data decoder 13 introduces any necessary relative delays between the input encoded signal and the reconstructed clock, RXC, and support logic to decode the data, RXD, at the output.
Prior art clock decoders may be categorized into three main types of decoders:
1) one-shot,
2) phase locked loop (PLL), and
3) tracking Manchester decoder (TMD).
A description of and references to the first two types may be found in Bazes, M., "CMOS Digital Clock and Data Recovery Circuit," U.S. Pat. No. 5,103,466, Apr. 7, 1992, which discloses, as the subject of the patent, a clock decoder of the third (TMD) type.
The one-shot clock decoder requires a signal transition to occur consistently within each bit interval such as generated by the Manchester, Differential Manchester, and FM binary phase codes. In the latter case, the FM code produces a state transition at each bit-cell boundary (FIG. 1(d)) while in the case of either Manchester codes (FIG. 1(b), (c)) a center bit-cell transition is produced in each bit interval. The Miller code (FIG. 1 (e)) does not produce consistent transitions within each bit-cell and hence is not suitable for one-shot detection.
One-shot clock detection is based on detecting the consistent set of transitions and masking out the inconsistent (data dependent) set of transitions. If the phase encoded binary signal is applied to an edge detector, that detects each state transition and outputs a pulse for each detected transition, a stream of periodic pulses results corresponding to the consistent set of transitions and a non-periodic (or almost periodic) set corresponding to the data dependent set. A mask can be applied to gate-out the non-periodic pulse set, which occur at known positions relative to the periodic set. The periodic set of pulses may be applied to a suitable waveform generator, such as a one-shot, to form a reconstructed clock signal, RXC, with appropriate duty cycle.
The clock, RXC, may then be applied to a data detector that is used to synchronously decode the input binary phase encoded signal in which the clock has a fixed relationship to the region within each bit-cell that contains the encoded data information, i.e., in the case of the Manchester code, in the state of the last half of the bit-cell; and for the FM clock, in the presence, or lack, of a center bit-cell transition.
If the binary phase encoded signal does not have a set of consistently periodic transitions, a more complicated clock extraction method is required that uses a set of quasi-periodic pulses to generate a periodic set of pulses representative of the transmitted clock. Commonly, a phase-locked-loop (PLL) is used for this purpose.
FIG. 3 shows a one-shot clock decoder that includes an edge detector 32 operating on the binary input signal and generating a pulse for each signal state transition, AND-gate 34 for gating out bit-cell boundary transitions and passing center bit-cell transitions to one shots 36 and 38, and inverter 49 for clock waveform generation which is output at terminal 44 as RXC and fed back to AND-gate 34 through inverter 43. D-type flip-flop 40 constitutes a simple data decoder, or sampling circuit, that samples the encoded data 42 at the rising edge of RXC to produce the decoded data signal RXD 46.
FIG. 4 shows a PLL type of clock decoder that is similar to the one-shot clock decoder of FIG. 3 except that a one-shot has been replaced by PLL 58 which synthesizes a periodic clock, RXC, from the set of state transitions selected by AND-gate 54 that functions as a periodic time window. OR-gate 61 is required in order to ensure proper initialization (start-up) by temporarily disabling AND-gate and allowing all transitions to pass through. Again, the data decoder is a simple D-type flip-flop sampling circuit (60) that samples encoded 62 at the appropriate time by using RXC as the clock input and produces the decoded data, RXD, at the Q output. The PLL clock decoder has the advantage of being able to track slow changes in the received clock rate.
Both the one-shot and the PLL clock decoders incorporate analog type circuitry which is difficult to manufacture in MOS or CMOS because of the large variability in these manufacturing technologies. Also, use of a one-shot decoder is undesirable when the incoming signal jitter needs to be filtered. Consequently, Bazes in U.S. Pat. No. 5,103,466 has disclosed a clock and data decoder that is suitable for manufacturing as MOS circuits.
FIG. 5 shows a simplified block diagram of the digitally implemented tracking Manchester clock and data decoder of Bazes. Clock decoder 200 includes waveform digitizer 84, that accepts the phase encoded waveform on line 588 and samples the state of the encoded waveform a number of times, N, (typically N=16 or 32, samples per bit-cell interval) and produces a binary output signal representative of the two states. The sampling control is provided by synchronous delay line (SDL) 82 that accepts the stable local clock (which has a rate close to the phase encoded clock rate) and produces a time varying output on the N output taps. (SDL 82 is described by Bazes in U.S. Pat. No. 4,994,695 entitled "Synchronous Delay Line with Quadrature Phases.") The advance through the taps of the clock transition is used to sample, in parallel, each bit-cell interval N-times per bit-cell interval, producing a high resolution digital representation of the incoming phase encoded waveform.
The output from waveform digitizer 84 is an N sample representation of a bit interval of the phase encoded input data that is supplied to bit center detector 300. (Waveform digitizer 84 is described by Bazes in U.S. Pat. No. 4,975,702 for "CMOS Waveform Digitizer.") Bit center detector 300 tracks the bit center transitions. Digital filter 100 is a low-pass single-pole filter that accepts the bit center detector output, a binary number representing the bit center location, and computes a bit center location average value which is used to control, by line 81, the phase of the synthesized clock signal, RXC, produced by digital waveform synthesizer 86. Digital waveform synthesizer 86 also supplies the masking control signal, over line 85, to bit center detector 300. (Digital waveform synthesizer 86 is described by Bazes in U.S. Pat. No. 4,980,585 entitled "Method and Apparatus for Synthesizing Digital Waveform.")
Data decoder 400 includes a delay for properly matching the sampling of the encoded data on line 588 by the reconstructed clock, RXC, supplied on line 87. A D-type flip-flop sampling circuit is used for sampling by RXC.
In this manner, the tracking Manchester decoder of Bazes, provides the benefits of dynamically tracking the clock embedded in the phase encoded signal using an all digital implementation suitable for MOS manufacturing technology.
An important application for the present invention is in token-ring local area network (LAN) stations. FIG. 6 is a simplified block diagram of a token-ring LAN that consists of a star connected system of stations 101, each station connected by a lobe cable 114 to a concentrator 110 or 111 by means of a trunk coupling unit (TCU) 112,. Concentrators are serially interconnected by the main ring communication path 120 and the back-up ring path 121. Each TCU 112 provides means for inserting a station into the communication path or for connecting back to itself in the by-passed mode. A maximum of 250stations per token-ring can be accommodated.
Information on the token-ring is transferred sequentially, bit-by-bit, from one inserted station to the next so that, for example, station no. 1 would transmit to station no. 3 and station no. 3 would transmit to station no. 1. Each station regenerates and repeats each bit. A station transfers information into the ring where the information circulates from one station to the next. The destination station copies the information as it passes through. The source station that originated the information message strips the information from the ring.
The signaling method employed in the Token-Ring LAN is Differential Manchester, as previously described. One station, the Active Monitor, provides a fixed frequency, crystal controlled, reference clock for clocking messages originating within any Token-Ring station. The other stations on the Token-Ring derive the output timing from the received data message by recovering the originating station's embedded clock decoding the message and regenerating the message before passing the message onto the next station. The elastic buffer, situated at the Active Monitor, compensates for jitter and dynamic latency variations in the Token-Ring. If the elastic buffer elasticity is exceeded by underflow, or overflow, an error condition exists that requires re-initialization. For this reason, it is important that the decoding and regeneration process introduce a minimum amount of jitter because the repeated decoding and regeneration accumulates phase jitter as the message travels around the Token-Ring LAN.
A dual tracking Differential Manchester decoder (TDMD) improves jitter tolerance while keeping the accumulated jitter to a minimum by using two decoder circuits: one for recovering the data, and a second for recovering the clock, each recovery circuit respectively optimized for recovery of the data and the clock.
The TDMD provides a decoding and clock recovery circuit that is tolerant to incoming phase jitter while minimizing the accumulation of phase jitter when regenerating the data in a Token-Ring LAN station and also provides an improved clock recovery and decoding circuit by using digital circuits that are implementable using metal-oxide-silicon (MOS) and complementary MOS (CMOS) technology.
The present invention is illustrated by way of example and not limited to the figures of the accompanying drawings, in which like labels indicate similar elements.
FIG. 1 is a set of examples of phase encoded binary signals having embedded clocks.
FIG. 2 is a simple block diagram of a clock and data decoder suitable for decoding the phase encoded binary signals.
FIG. 3 is a block diagram of a prior art one-shot decoder.
FIG. 4 is a block diagram of a prior art phase-locked-loop (PLL) decoder.
FIG. 5 is a simplified block diagram of a Bazes type TMD phase encoded clock and data decoder.
FIG. 6 is a block diagram of a typical Token Ring network.
FIG. 7 is a detailed block diagram of a Bazes type tracking Manchester decoder (TMD).
FIG. 8 is a block diagram of a single-pole digital filter.
FIG. 9(a) is a block diagram of a digital-to-time domain converter (DTC) waveform generator.
FIG. 9(b) is a detail of a DTC switch.
FIG. 10 shows a detailed TDMD block diagram.
FIG. 11 shows a simplified TDMD clock and data recovery unit.
FIG. 12 is an idealized low-pass single-pole digital filter.
FIG. 13 shows the magnitude-squared frequency response of the digital filter.
FIG. 14(a) shows a block diagram for a programmable low-pass single-pole filter.
FIG. 14(b) is a tabulation of control signals and bandwidth of the filter of FIG. 14(a).
FIG. 15 is a block diagram of a dual TDMD system for clock and data regeneration.
FIG. 16 shows the idealized waveforms associated with the dual TDMD.
FIG. 17 is a block diagram of a dual TDMD system using shared resources.
FIG. 18 shows a set of idealized waveforms associated with reconstructing a Differential Manchester encoded signal for retransmission.
FIG. 19 shows a dual TDMD system adapted to decoding Differential Manchester encoded signals.
FIG. 20 shows a set of waveforms associated with reconstructing a Differential Manchester encoded signal.
A. Overview
In a token-ring station, the recovered clock is used for both decoding the input data stream and for transmitting the data to the next station. The recovered clock is used to determine the proper phase location at which to sample the data stream for recovery of the encoded data.
The clock recovery circuit must respond quickly to the incoming serial data stream in order to use it for decoding the data. The requirement for fast response implies that any filter used to recover the clock must have relatively large bandwidth. However, the need for minimizing jitter in the signal transferred to the next station requires that the recovered clock be as free as possible of noise and jitter which implies the use of a narrow band filter in the recovery of the clock.
The prior art solutions to the clock and data recovery problem have accommodated the conflicting filter requirements by using a sub-optimal filter with a compromise bandwidth between the two optimal choices. For example, PLL type clock decoder of FIG. 4 uses a single filter in the PLL, that has sufficient bandwidth to ensure timely data recovery response (RXD) while compromising the purity of the recovered clock (RXC). Neither the requirement for fast data recovery, nor the requirement for a stable recovered clock, are fully satisfied.
The tracking Manchester decoder (TMD) of Bazes (U.S. Pat. No. 5,163,466) is an all digital approach for clock recovery that uses a 32 tap synchronous delay line (SDL) to provide a timing reference. The incoming data is sampled at every tap (1/32 of the clock period) into a 32-bit (or 16-bit) pattern, corresponding to a sample each 1.953 ns (or 3.906 ns). The pattern is processed and filtered digitally to extract the phase of the input-data with respect to the imbedded clock. This phase information is used to recover the imbedded clock and to sample the encoded message stream for data recovery.
FIG. 7 is a detailed block diagram of the tracking Manchester decoder (TMD) 80 as taught by Bazes in U.S. Pat. No. 5,103,466 for clock and data information recovery. TMD 80 comprises a synchronous delay line (SDL) 82 coupled to and controlling waveform digitizer 84 that accepts encoded input data on input line 104 and outputs a binary valued representation of the input encoded data sampled N times per clock period with sequential samples appearing simultaneously on N distinct lines 122 that are connected to the input of transition detector 88. The state of lines 122 corresponds to the logic state of a one clock interval of the input encoded waveform at the sampled points. Transition detector 88 comprises a plurality of N two-input exclusive-OR (XOR) gates (N=16, typically). The nth XOR-gate inputs are connected to the (n-1)th and nth lines of lines 122, except for the zeroth XOR-gate that has one input connected to the zeroth line and the other connected to a flip-flop that stores the state of line N one clock period earlier. In this manner transition detector activates an output line (1-out-of-N) corresponding to the XOR-gate that senses a 0,1 or 1,0 input that indicates a state transition. Such a transition may occur at a bit-cell center or bit-cell boundary.
The N output lines 124 of transition detector 88 are applied to AND stage 90 that is used to mask out selected groups of bits by means of the N control lines 126 provided by waveform synthesizer 86 to N AND-gates, one gate per input line 124. The inconsistent and data dependent bit-cell boundary transitions are masked out, leaving only the consistent set of bit-cell center transitions that occur within ±1/4 bit-cell of the bit-cell center.
The output of N lines from AND stage 90 is split into two groups of N/2 adjacent lines, one corresponding to the lower and the other to the upper half-set of lines. Each group of N/2 lines is applied to a corresponding lower encoder 94 or upper encoder 92 that detects an active line and produces a binary number corresponding to the active line position index (0-(N/2-1)). Upper encoder 92 also adds the value N/2 to the encoded line position index when a 1 is detected on one of the upper N/2 lines to indicate the true position relative to the lower N/2 lines. The output of each encoder, lines 132 and 134, are added in adder 96 for producing an average (mod N) value for the transition whenever two transitions occur within a half clock period interval due to jitter. The adder output is latched into L-type register 98. If no transitions are detected by either encoder 92 or 94, a NT (no transition) signal is generated (high) and applied to NAND-gate 114. If both inputs to NAND-gate 114 are high, indicating no transitions detected, the output connected to the L input is deasserted causing the register not to accept the output of adder 96. Thus, the previous value is retained at output lines 138. The output of register 98 is a sequence of numbers, each indicating an estimated position of the bit-cell center transition during each clock period.
The output of register 98 is applied to digital filter 100, a low-pass single-pole filter, for producing a smoothed (or moving average) estimate of the bit-cell center transition on output line 140.
FIG. 8, a block diagram of filter 100, shows an input line 138 from register 98 into subtractor unit 170 input A and the filter output on line 140 connected to input B for forming the difference y(n)-x(n) at output 171, where y(n) is the nth value of the filter output on line 140 and x(n) is the nth input value supplied by register 98. Binary scaling (2-s), where s is the number of right bit shifts applied by TAU control line 188, is applied to the value at line 171 by programmable shifter 180 for controlling the bandwidth of filter 100. The binary scaled output on line 181 is combined with the filter output at subtractor unit 182 to produce a value, (1-2-s)y(n)+ 2-s x(n), equal to the difference between the output of shifter 180 and the filter output on line 140. The output of subtractor 182 is stored in D-type register 184 for one clock delay and then fed-back to subtractor units 170 and 182 and to the filter output line 140. Rounding logic unit 186 is for reducing the number of bits (2log2 N) out of the filter to log2 N bits. The output from filter 100 can be represented as a difference equation relating the current output, y(n), to past input and output x(n-1) and y(n-1), or
y(n)=(1-2-s)y(n-1)+2-s x(n-1) (1)
which has a corresponding z-transform equation
Y(z)=2-s z-1 X(z)/(1-(1-2-s)z-1). (2)
Therefore, the z-transform transfer function is
H(z)=Y(z)/X(z)=2-s z-1 /(1-(1-2-s)z31 1)(3)
which is characteristic of a single-pole low-pass filter with a pole located at z=(1-2-s).
Referring back to FIG. 7, digital filter output line 140 delivers the moving average (filtered) value of the bit-cell center (a log2 N bit number) to shifter unit 118 of waveform synthesizer 86.
Waveform synthesizer 86 comprises pattern generator 116, shifter 118 and digital to time converter (DTC) 120. Pattern generator produces a binary pattern with N/2 centered 1's and N/4 0's on either side. The pattern is supplied to shifter 118 where the pattern is circularly shifted in accordance with the output of digital filter 100. If the output line 140 indicates that the detected clock is at bit-cell center, no shift is introduced. Otherwise, the pattern is rotated left so that the pattern is centered about the indicated clock position provided on the digital filter output line 140. The rotated pattern is applied to AND stage 90 where it masks-off all positions in the pattern delivered by transition detector 88 that correspond to 0's in the shifter 118 output pattern. In this way, bit-cell boundary transitions are removed and bit-cell center transitions are preserved.
The output pattern of shifter 118 is also provided as an input to DTC 120 together with the output of SDL 82. DTC 120 is shown in FIG. 9(a) and (b) and is described in detail by Bazes, U.S. Pat. No. 4,980,585. DTC 120 receives tap waveforms TAP 0:N-1! from SDL 82 and waveform BIT 0:N-1! from shifter 118. Also, N transition gates 854 0:N-1! for selectively connecting any one of the BIT 0:N-1! waveforms to a commonly connected output line 861 are controlled by waveforms TAP 0:N-1!. When a transmission gate 854 k! is turned on, it transfers the bit pattern on TAP k! to output line 861, otherwise TAP k! is isolated from output line 861. Also, transmission gate 854 k! is turned on only if TAP k! is high and TAP k+1! is low. Only one transmission gate 854 is turned on at a time. Because of the repeated scanning pattern produced by SDL 82 at TAP 0:N-1!, the bit pattern out of shifter 118 is generated as a synthesized clock waveform that changes from one clock period to the next in accordance with the shifted pattern produced by shifter 118. The DTC 120 output is buffered by buffer 142 to produce the regenerated output clock RXC.
FIG. 9(b) shows the detail structure of transition gate 854 k!. TAP k! and output signal (TAP k+1!), on line 8629k+1! from the next adjacent transition gate, control switch 852 k! as explained above.
In order to cancel out any relative delay (skew) of the DTC generated RXC signal on output line 110, a delay 112 is provided in data decoder 400 so that RXC samples the encoded data during each bit-cell at the 3/4 bit-cell point, as required for a Manchester phase encoded signal.
The dual TMD circuit, to be described, substantially improves the performance of the Bazes TMD by using two digital filters, each producing a clock. A wideband digital filter produces a highly adaptable (wideband) clock that responds to dynamic jitter for decoding the data and thus improving receive jitter margins. A narrowband digital filter operates on the same data stream and extracts a stable minimum jitter clock that may be used for regenerating the received signal for transmission to the next station in a Token-Ring LAN.
Because the wideband and narrowband clocks are derived from a common received data stream, the phase difference between the two clocks is bounded, differing only by the phase differences introduced by the two filter characteristics, and by any differential noise inherent in the filter process. Because of this fixed phase difference relationship, both bandwidths may be chosen to independently optimize their respective purposes while allowing synchronization between data and clock without the use of an elastic buffer. A maximum delay between the two clocks is held to within a half of a clock period.
The improvement in performance can be achieved at minimal cost because using an all digital implementation allows the use of common resources for both clock recovery circuits. It has been found that the increase in die size for implementing the dual TMD over the Bazes TMD was less than 25% for the clock recovery circuits.
B. Tracking Differential Manchester Decoder (TDMD).
In order to accommodate the TR LAN, the TMD of Bazes, which was designed for decoding Manchester encoded data in an Ethernet LAN, must be modified for regenerating Differential Manchester coded data. More specifically, Manchester decoding only requires one sample per bit-cell. Accordingly, Bazes generates a recovered clock at the same frequency as the data bit-rate (10 MHz and 10 Mbits/sec). Clock regeneration is done by detecting mid-bit-cell transitions and decoding is done by sampling with the regenerated clock, as previously described.
In the case of a Token-Ring (TR) LAN that uses Differential Manchester encoding, the encoded data must be sampled twice in each bit-cell in order to decode and distinguish two non-data symbols (J and K) from the two data symbols (0 and 1). Symbols J and K have no mid-bit-cell transition and are distinguished by J having the same state as the last half of the previous bit-cell, while K assumes the opposite state of the last half or the previous bit-cell. Symbols J and K are used in the message-start delimiter pattern (J, K, O, J, K, O, O, O) and in the message-end delimiter pattern (J, K, I, J, K, I, I, E), where E is a frame-bit, or token-error-detection bit for indicating an error detected by any of the stations on a TR LAN.
In the case of the TDMD for use in a TR LAN, the 32-bit sampled pattern out of waveform digitizer 84 is a 32-sample waveform with 1 bit per sample. The waveform represents one half of a bit cell interval. Thus, for a 16 Mbit/second message bit rate, the stable local clock running at a 32 MHz rate produces a 32 one-bit waveform representing a half-bit cell interval with a 0.977 ns interval between samples. The 32-sample half-bit cell waveforms are sequentially presented to upper and lower encoders 92 and 94, respectively, for extracting both center bit-cell transitions and bit-cell boundary transitions.
Because the regenerated clock-rate is twice the data (bit-cell) rate, both center bit-cell transitions and bit-cell boundary transitions are used for clock recovery. The center bit-cell transitions are present except when J or K is transmitted and the bit-cell boundary transitions are data dependent and occur randomly half of the time. The "missing" bit-cell centers or boundary transitions introduce "noise" into the double data clock rate which, in addition to the jitter introduced by the TR, needs to filtered. Accordingly, the masking function of AND-gate 90 of FIG. 7 is not required.
FIG. 10 shows a tracking Differential Manchester Decoder (TDMD) 80', derived from Bazes TMD of FIG. 7, in which bit center detector 300 of FIG. 7 has been replaced by bit transition detector 300' that does not have AND-gate 90 between transition detector 88 and upper and lower encoders 92 and 94. In this manner, all detected transitions are passed on to upper and lower encoders 92 and 94 where the active lines corresponding to bit-cell center and boundary transitions are encoded as a binary number representing the location of the transition in each bit-cell half.
The 32 (N) output lines 124 from transition detector 88 are split into two sets of 16 lines each 128 and 130 respectively representing the upper 16 lines and the lower 16 lines. Lower encoder 94 detects an active line and, if present, encodes the active line location as a binary number (0-15). If an active line is not detected, the no-transition (NT) output is asserted. Similarly, upper encoder 92 detects and encodes an active line position (0-15) within the upper 16 lines 128 and adds N/2=16 to indicate the true position with respect to the 16 lower lines 130. If no active line is detected, the NT output is asserted high. The output lines 132 and 134 are applied to adder 96 for producing the sum (modulo-N) of the two binary values represented on lines 132 and 134. This sum corresponds to an average value for the case when two transitions are detected in the same bit-cell half window spanned by the 32 lines of transition detector 88. When a single transition is detected within a half-bit cell window the single binary value is passed through adder 96 on lines 136 and on to L-type register 98 the binary value on lines 136 is latched by the L-input from NAND-gate 114 being asserted high. Thus latching occurs at each clock cycle except when both NT outputs of upper encoder 92 and lower encoder 94 are high indicating that no transition was detected by either encoder. If no transition is detected by both encoders 92 and 94, the previously latched value is retained, thereby causing that value to be repeated. Output lines 138 of register 98 are applied as an input to digital filter 100 for producing a smoothed (moving average) estimate of the bit-cell transitions on filter output lines 140.
The output of digital filter 100 is applied to shifter circuit 118 for shifting the clock waveform generated by pattern generation 116 so that each clock pulse onset coincides with the filter output value.
The "static" pattern of N-bits at the output of shifter 118 is supplied to DTC 120 which, as previously described, generates a dynamic clock pattern under control of the output taps of SDL 82 to output buffer 142.
A single TDMD clock recovery unit, using the modified Bazes TMD described above and shown in FIG. 10, would be marginally effective in satisfying the Token-Ring LAN jitter specification IEEE Draft Standard 802, 5Q-D3, 18 Mar 93! because the speed of tracking for the Bazes type device is slower than a PLL type decoder and clock recovery unit (FIG. 4).
C. Dual TDMD Structure
FIG. 11 shows a simplified TDMD clock and data recovery circuit for the Token-Ring LAN wherein the input data is Differential Manchester encoded with an embedded clock. Clock decoder 200 output, RXC, is used to sample (latch) the input encoded data into D-type flip-flop 201 during the rising edge of RXC. Ideally, latch occurs at the mid-point of each bit-cell half period.
The sampled bit stream, RXD, out of the Q output of D-type flip-flop 201, is decoded by using a Differential Manchester decoder circuit. Two samples are used to characterize each bit-cell.
The recovered clock's reaction to phase variations is controlled by the bandwidth of low-pass digital filter 100, as shown in FIG. 10. The purpose of digital filter 100 is to smooth-out the variations in bit-cell center location and boundary transition location estimates from the received Differential Manchester encoded signal, the estimates being represented by the log2 (N) bit words supplied by L-type register 98. The bandwidth of digital filter 100 is controlled by the TAU control line 188 which controls the bandwidth, α, corresponding to the z-plane pole location of the single-pole digital filter 100.
FIG. 12 is an abstracted form of filter 100 as taught by Bazes. The indicia used correspond to elements with the same indicia as in FIG. 10 of U.S. Pat. No. 5,103,466. The bandwidth of the filter is controlled by TAU control 188 which controls programmable shifter 180 that is used to scale the output of adder 170. The value of the scaling is given by (1-α)=2-s, where s=0, 1, 2, . . . . The corresponding z-transform transfer characteristic H(z) is given by
H(z)=Y(z)/X(z)=(1-α)z-1 /(1-αz-1) (1)
where z=ejωT, and T is the sampling interval or bit-cell interval. The magnitude-squared frequency transfer characteristic is given by
|H(ejωT)|2 =(1-α)2 /(1-2αcosωT+α2) (2)
which is plotted in FIG. 13 for α=0, 1/2, 3/4 and 7/8 corresponding to s=0, 1, 2, and 3.
It should be noted that scaling element 180 does not have to be a binary scaling element. The use of a shifter to produce a binary scale factor is a convenience that simplifies the scaling process by avoiding the use of a more general scaling element such as a multiplier. General filter stability considerations require that 0<(1-α)<1. The actual value chosen within these limits determines the effective bandwidth, α, of the filter. Thus, for better control of the filter bandwidth, a more elaborate scaling means is required such as one that uses a combination of different binary scalings ranging from the single binary scaler to a full-multiplying scaler having one binary scaler for each bit of the data word that is to be scaled.
An example of a programmable filter, suitable for use in a Token-Ring network, is described in U.S. Pat. No. 5,546,431. The filter uses a selected subset of binary scaling elements as shown in FIG. 14(a) and has selectable bandwidths as tabulated in FIG. 14(b).
FIG. 14(a) is similar to FIG. 8 except that programmable shifter 180 has been replaced by scaling unit 650, TAU control line 188 by control lines CTLA, CTLB, and CTLC, and feedback line 140 is returned to shifter unit 650 rather than to subtractor unit 182. The input line 138 has 4 bits that represent the transition location number out of L-type register 98 of FIG. 10.
Scaling unit 650 introduces scaling by right-shifting in shift registers 651-653 by 4, 6 or 7, and 5, 6, or 7 bits respectively. Adder 654 adds the shifted outputs of shifter registers 651 and 652 while combining logic 655 combines the output of shift register 653 and the output of D-type register 184 as either a sum or difference. Adder 654 output and combining logic 655 outputs are combined by subtractor 182 and stored in D-type register 184 as the next filter output value after being passed through bit truncating and rounding logic circuit 186.
Control line CTLA selects either a 6 or 7 right bit shift, S2, for shift register 652. Control lines CTLB select either a 5, 6, or 7 bit right shift, S3, for shift register 653. Control line CTLC selects either the sum or difference mode for combining logic 655. Shift register 651 produces a fixed right bit shift, S1, equal to 4.
In this manner scaling unit 650 modifies the transfer function of equation (1) to be
H(z)=βz-1 /(1-(1-β)z-1) (3)
β=2-s 1 +2-s 2 ±2-s 3 (4)
The bandwidth, BW, of the filter in Hertz is given by ##EQU1## where T is the filter clock period. If a clock rate of 32 MHz is assumed, the relationship between p, the selection of control lines CTLA, CTLB, and CTLC, the filter bandwidth and filter bandwidth increment (ABW) is summarized in FIG. 14(b).
For a fixed design, a suitable assortment of fixed binary scaling elements and sum-or-difference units may be selected to achieve the desired bandwidth for filter 100.
FIG. 15 is a block diagram of a dual TDMD system for accepting Differential Manchester encoded input data and producing two output signals: the regenerated clock (RXC), and the decoded data stream (RXD).
The encoded input data is supplied to each of two modified clock decoder 200 circuits of the type described above with one labeled wide bandwidth (WB) and the other narrow bandwidth (NB). The WB clock decoder 1500 is used to regenerate a clock signal, WCLK, from the encoded input data stream which appears at output line 302 and is applied to the CLK input of D-type flip-flop (DFF) 301. The encoded data is applied to the D-input of flip-flop 301 after passing through delay unit 303. Delay unit 303 provides the delay necessary to ensure that the WCLK samples the center of each bit-cell for properly decoding the data. The output at the Q terminal of DFF 301 is the decoded data stream. Thus, WB clock decoder 1500 is used to recover the encoded data. The bandwidth of filter 100 is adjusted for optimal data recovery.
NB clock decoder 1501 is used to regenerate the clock signal imbedded in the input data stream using a clock decoder 200 that has a narrower bandwidth filter 100 than that used in the WB clock decoder. The narrower bandwidth reduces more noise and jitter than the wider band filter of the NB clock decoder.
The output of the NB clock decoder, RXC, is applied to sampling circuit DFF 304 through inverter 305 for sampling data RXD1 produced by DFF 301. The Q output of DFF 304 is a decoded data stream that is synchronous with the recovered clock, RXC.
The waveforms associated with the dual TDMD of FIG. 15 are shown in FIG. 16, lines (a)-(e), in which Tc represents the clock cycle. The Differential Manchester encoded input data is shown on line (a). Line (b) shows WCLK, the detected clock out of the WB clock decoder which is used to sample the data on line (a) on the rising transition resulting in RXD1 (line (c)) out of the Q output of DFF 301. The output clock RXC of the NB clock decoder 1501 is shown on line (d). Because RXC# (logical complement of RXC) is used to sample RXD1, RXD is shown as being clocked by the falling transitions of RXC (rising transitions of RXC#) on line (e). In this manner, the center of each half-bit cell coincides with a rising transition of RXC.
FIG. 17 shows an implementation for a dual TDMD 350' in which waveform digitizer 84, bit transition detector 300' and digital filter 100 are shared by the wide band TDMD and the narrow band TDMD. Clearly, the output from transition detector 300' is needed by both TDMDs. The output of digital filter 100 is supplied to waveform synthesizer 86 which generates the wide band clock for decoder 400. Decoder 400 samples the incoming encoded data and produces RXD1 at the decoder output.
The output of digital filter 100 is shown as being supplied to digital filter 100' that provides the additional filtering required for the narrow band waveform synthesizer 86'. The narrow band clock, RXC, out of synthesizer 86' samples RXD1 in decoder 400' to produce RXD as an output.
FIG. 17 also shows an alternative embodiment in which the output of bit transition detector 300' is supplied to both digital filter 100 and 100'. The latter connection is shown as a dotted line from bit transition detector 300' to digital filter 100'. In this configuration the output of digital filter 100 would be accepted by waveform synthesizer 86 and not by digital filter 100'. In this embodiment, digital filter 100' would have the same transfer function as the filter in narrow band clock decoder 1501 of FIG. 15.
D. Token-Ring Operation
Because each ring station is unable to fully compensate for phase distortion introduced mainly by the lobe cables (114 of FIG. 6), phase jitter accumulates as the signal travels around the ring. These accumulated phase errors accumulate at a certain average rate with respect to time. The average rate of accumulation is called the phase slope and is expressed in nanoseconds of jitter per nanosecond of time. The Token-Ring LAN specification limits the maximum phase slope acceptable.
It is known that there is correlation between the filter used in the clock recovery circuit (such filter 100 in clock decoder 200 of the TMD) and the observed residual phase jitter in the recovered clock. A filter bandwidth of less than 400 KHz generally ensures that the accumulated phase jitter is kept within the accumulated phase slope specification limit. The IEEE Draft Standard 802.5Q D3, 19 Mar. 93, Appendix C, indicates that a first order filter of 360 KHz bandwidth has a theoretical dynamic trading error between the recovered and the encoded clock is 7.1 ns. The actual phase jitter, due to delays of 4-5 clock periods in a Bazes type TMD during which phase slopes can contribute additional jitter, is found to equal or exceed 10 ns.
By using a dual TDMD 350 decoder such as shown in FIG. 15, in which a wideband filter is used in the WB TDMD clock decoder to decode the incoming encoded data, the dynamic tracking error is reduced. Worst case analysis indicates that the phase slope is approximately 5 ns, providing adequate margin to reliably sample the encoded data.
Because the WB and NB clock decodes use the same input (the received data stream), the phase difference between the two decoder outputs is limited. This eliminates the need for synchronizing the WB and NB output clocks and also eliminates the need for an additional elastic buffer. An additional delay of only 1/2 clock period is introduced as shown by comparing RXD1 at line (c) of FIG. 16 with RXD at line (e).
FIG. 18 shows the waveforms associated with a dual TDMD for recovering an encoded message for retransmission for an idealized (noiseless, jitterless) case. Line (a) shows the input waveform with a bit-cell period of 62.5 ns corresponding to a standard bit-rate of 16 Mbits/s. The WB clock, DRXC, with a 32 MHz rate is generated by wide band clock decoder (WB TDMD) 500, of FIG. 19 from the encoded input data. The sampled waveform, ISIG, out of DFF 501 is shown at line (c) of FIG. 18. Similarly, narrow band clock, RCLK, also a 32 MHz clock generated by narrow band clock decoder (NB TDMD) 510 of FIG. 19 and shown at line (d) of FIG. 18, is used to sample ISIG and results in output signal RCVR at the Q output of DFF 502. Signal RCVR represents the recovered waveform of the encoded signal that is synchronous with NB-clock RCLK.
FIG. 20 shows a set of waveforms generated by a dual TDMD when tracking error (phase slope) is present. A constant phase slope corresponds to a constant rate difference between a reference clock at the station of origin and the clock rate observed (estimated) at a downstream station.
The vertical dotted line labeled 0, represents the ideal point in time for sampling the state of the first-half of the bit-cell.
If a single TMD clock decoder (prior art) were to be used for recovery of the DATA-- IN waveform (line (a)), then the sampling point, corresponding to the rising transition of RCLK could be as early as indicated by dotted line 1 because the compromise narrower band filter cannot respond to fast dynamic jitter changes without further degrading the recovered clock jitter error.
By using a dual TDMD system with a wider filter for the WB TDMD, the WB recovered clock can respond faster to phase errors and contain the variation in sampling point to a narrower region as indicated by dotted line 2. Resampling ISIG with the NB clock, RCLK, results in a recovered and resynchronized encoded data signal, RCVR, that has a minimized resampled jitter error as indicated by dotted line 3.
The time window within which resynchronization of ISIG with RCLK must occur is between dotted line 2 and the rising transition of DRXC. If the phase difference between RCLK and DRXC enables correct sampling by RCLK, the margin available for tracking error is increased because the dynamic tracking error is the reduced tracking error of the quick response wide band filtered clock, DXRC.
It should be noted that the principles described above concerning the use of dual TDMD units for decoding and regenerating phase encoded data may be practiced with other clock recovery methods including the prior art methods previously described. For example, a wide bandwidth phase-locked-loop (PLL) decoder could be used as the wideband TMD clock decoder 1500 and a narrow bandwidth PLL as the second narrow bandwidth clock decoder 1501 of FIG. 15.
Also, the dual TDMD system described may also be used to decode data and the associated embedded clock for other forms of binary phase encoded data and in communication systems other than the Token-Ring LAN. For example, a Manchester encoded message, such as in the Ethernet LAN, may be operated-on by the system of FIG. 15 by extracting the center bit-cell transitions using a Bazes type TMD for both the narrow and wide bandwidth clock decoders. The wide bandwidth decoder sampling the Manchester encoded data at the 3/4 bit-cell position to determine the message state while the narrow bandwidth clock decoder resynchronizes the decoded signal (RXD1) for retransmission. The method and apparatus described is generally applicable to communications systems using phase encoded binary signals having an embedded clock.
These variations, and others, in the use of the principles taught by this inventor will become apparent to those practicing the art.
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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Biomedical Engineering
This group is open to everyone, but will be of greatest interest to MSOE biomedical engineering students, faculty and program alumni. It is a place to announce and discuss program related topics and ask questions. Current MSOE BE students are particularly encouraged to join and participate.
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Sure, yeah...the shooting was horrible tonight and ball handling downright sloppy..but the season JUST started..if this is going on 20 games out, then YES we have a problem, but right now, its too early to diagnose b/c EVERYBODY is playing horrible right now..Pop even sat all his starters in the 2nd half to see what he's got, and they LOST..and we know how many rings he's won!....teams will pick it up..including ours!
..and I bet when they pick it up, you guys will be right back on the bandwagon singing their praises...if youre IN be in, if youre not get out!
Im so sick of all these fair-weather fans who throw in the towel after just a couple of bad losses...it happens..its part of the process to getting better and stronger. Thats why you play a lot of games.
We dont suck! Its early in the season and we are 2-2...CHILL! The guys are still learning to play with each other and besides we just have to score more offensively with our backcourt and clean up the turnovers..with our backcourt...OUR BIG ARE AWESOME AND ARE PLAYING GREAT! We cant "SUCK" only four games into the season! Get off the bandwagon.
We dont suck! Its early in the season and we are 2-2...CHILL! The guys are still learning to play with each other and besides we just have to score more offensively with our backcourt and clean up the turnovers..with our backcourt...OUR BIG ARE AWESOME AND ARE PLAYING GREAT! We cant "SUCK" only four games into the season! Get off the bandwagon.
Haha@ Donovan...Its a good night to be a Bees and Brees fan!!! NOLA all day! Cant remember the last time both teams won on the SAME night!
I agree with you, Blue...TP needs to get this kid's name and face out there! EG baby!
@Khalil...I feel your frustration, but its one the first game bro..lets calm down...WE WON! Geaux Hornets! Let's keep surprising em all!
@ Larris
Where did you hear that rumor? I HIGHLY doubt Chris Paul would want to play another quarter now for the team that tried to trade him...how does ANY player want to do that? Can you imagine the attitude Paul, Odom, Gasol, Scola, Martin, and the other guys will bring to workouts tomorrow?? LOL should be interesting!
The deal has been put on "hold".
Its a WIN/WIN situation for the Hornets...and its a WIN/WIN for Chris Paul, who could still not sign an ext with the Lakers and be free to go wherever he wants, and the Hornets suffer no loss or penalty by trading him, but GAIN a whole lot. Great job by Demps MANAGING this team.
Thats right, and he isnt getting younger, but what a slap in the face it would be if the Hornets got to the finals..I dont see the Hornets being able to get so many bodies for the roster if we kept Chris Paul..they HAD to move him..they are still weaning off of that joke-of-a-GM Jeff Bower's mistakes. Its going to happen and the Hornets WILL contend. Mark my words.
It IS about taking advantage of your chance, and I feel like now is our chance..its not about one player...I dont care how good a player is, check the ego at the door..even Jordan understood that in order for the system to work, all players had to gel together and play well together. That is why they were so successful. I still believe the Hornets will be fine. I really feel like Howard should leave also. Most times having a bunch of players who play well together can win even more so than having one superstar and not have enough to get "over the hump" against other teams. We did get a LOT bigger. This season should be fun to watch.
I dont know if they are better..Gasol and Odom were a lot more valuable than people recognize...Paul will have to work a whole lot harder on that team...and still..his knee is an issue..he is not the same player..I guarantee you..it wont be a cake walk.
Yeah, X..we all gotta move on..I think the Hornets will be just fine..CP3 is just one player...
Odom is 31-32...not sure about contracts tho
@ Michael Mason
I like that scenario bro..having Gasol with the new squad would be real nice...
Exactly! @speedy
These are not BUM players...these guys were stars on their respective teams and they play well..so who knows what we are building here?!
That was exactly my thinking, 9thwardsaint
The 3 is Ariza's natural spot anyway. I think the Hornets will be okay. People forget CP was injured a lot of the season anyway and his knee is still an issue. He is not the same player he once was. So we are actually the winners in all this. Give the new administration a chance to fix all the problems the previous ones set up for us.


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Winning streak vaults Duke into top 25
The latest accomplishment for Duke football came shortly before noon on Sunday.
A few hours later, Blue Devils coach David Cutcliffe stood before his team, which had just become the No. 25-ranked college football team in the land.
No Duke coach in 19 years had had the privilege of addressing his team under this circumstance.
But Saturday's 48-30 win over then No. 24 Miami, Duke's second win over a ranked team this season, was enough to impress the voters, who put Duke in the top 25 for the first time since the 1994 season.
"I addressed it in there with them," Cutcliffe said shortly after the regular Sunday team meeting and prior to a Sunday night practice. "It had been a long drought. We were one of those schools where, when the article wasn't even talking about us, they would comment about how many weeks or years since we had been in top 25 poll.
"I told (the players) that's a week-to-week proposition and you know what that means."
For the first time since the Blue Devils faced Wisconsin in the Hall of Fame Bowl on Jan. 2, 1995, they will take the field at Wake Forest on Saturday (noon, ESPN2) as a ranked team.
Duke (8-2, 4-2 in the ACC) has won six games in a row for the first time since reeling off seven straight wins to start the 1994 season.
Following the win over Miami, Cutcliffe vowed that this improvement "was no accident" and that the Blue Devils "weren't going anywhere."
Duke had gone 313 weeks without appearing in the AP poll. With Duke's entry into the poll, Temple, Southern Methodist and Indiana have gone the longest among teams playing in BCS automatic qualifier conferences without being ranked.
Cutcliffe wanted his players to enjoy the win over Miami and the accomplishment of being ranked.
"Yes they are having fun," Cutcliffe said. "If you can't enjoy playing well on Sunday, then something is wrong with you."
The rest of the week, though, will find the Blue Devils focused on beating Wake Forest. Duke had lost 12 consecutive games to the Demon Deacons before toppling them xx-xx at BB&T Field last season.
In an ACC scheduling quirk, Duke will play at Winston-Salem for a second consecutive season. Even though Wake Forest (4-6, 2-5) is struggling this season and will play without injured star receiver Michael Campanaro (broken collarbone), Cutcliffe doesn't expect an easy time.
"It's Duke-Wake," Cutcliffe said. "It's that feeling that you know you are in for a grind. Each year we have played this game it has been a war. We know we are in for an intense football game."
Because eight wins is more than any Duke has had in one season since 1994, dealing with prosperity is a new experience for the Blue Devils.
"I'm not concerned with complacency at all," Cutcliffe said. "This team will not do that. The thing is getting up tight. Everyone will do that."
So Duke will follow its same routine in practice of focusing on perfect execution.
While still basking the glow of the win over Miami on Saturday night, Duke left guard Dave Harding said this team knows how to win.
"I think this team is not a fluke," Harding said. "We come to play and play hard every day. I think this is a winning team."


text:
Coverage and insight from Austin.
Monthly Archive for August, 2008
UT player charged with DWI
Texas defensive tackle Lamarr Houston was arrested early Sunday morning and charged with driving while intoxicated, a Class B misdemeanor charge. He was booked at 5:02 a.m. Bond was set for $3,000, and as of late Sunday morning, Houston was still being held in Travis County Jail. Houston had three tackles in the 52-10 victory […] [Read More]
Seats have been claimed
The lucky folks with the seatbacks on the highest row possible have finally arrived. They sat down at 5:54 p.m. according to my watch, which is about five minutes faster than most people's. I know all you guys were yearning to know. [Read More]
No. 10 officially retired
In a short but sweet ceremony, Vince Young's No. 10 is now off limits. After a highlight video — Young and coach Mack Brown stood on the sidelines watching together — Young accepted a large framed jersey and then addressed the crowd. He thanked family and coaches, but also gave a hearty thanks to the […] [Read More]
5 Things To Watch
I'm back for some serious blogging now … is that even possible? I'm going to try. Here's my list of five things to watch in the game today. Clearly, these aren't the only things to watch, but you get the idea. 1. Will Muschamp — Not a surprise pick. Obviously, this guy's sideline demeanor is […] [Read More]
Live from Royal-Memorial
Good afternoon — I arrived at the game a little earlier than usual today. Not to avoid traffic, but simply to cure my own curiousity. From my view in the press box (which is about eight stories up on the west side of the stadium) I can count exactly two fixed seatbacks on the very […] [Read More]
Whittaker questionable for Saturday
Freshman running back Fozzy Whittaker is questionable for Saturday's opener with a left knee injury, according to UT athletic trainer Kenny Boyd. Whittaker dinged his knee almost two weeks ago in a scrimmage, and coach Mack Brown said on Monday he had missed some action during practice recovering from that. The 5-foot-10 Whittaker is 190 […] [Read More]
Putting The G in Beijing
And, for that matter, the G in gold, too. We're talking about Texas women's basketball coach Gail Goestenkors who is back in Austin now after helping the U.S. women's national team take home the gold medal in the Beijing Olympics. This was Goestenkors' second stint with Team USA — she was on the sidelines when […] [Read More]
A virtual handshake
Hello everyone — I think I jumped the gun earlier, and just started blogging away without a real introduction. Anyway, I'm your intrepid reporter for all things Longhorn. Consider me your eyes and ears on the 40 Acres. We want this blog to be fun. I think it already is. For instance, while running this […] [Read More]
The Big Day
Yes, it's only Thursday, but today's Longhorn practice should go a long way in determining who is starting in the secondary on Saturday against Florida Atlantic. The reason? Well, it's simple, and it's not. First, UT only practices in shorts today, so they can accomplish quite a bit in the passing game. But the real […] [Read More]


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Corning's Gaffer District is downtown Corning's shopping and destination, residential neighborhood, and the cultural and entertainment center of the region. In this historic district you will find busy streets, bustling stores, happening restaurants and bars, upper story living, a movie theatre, world-class museums and art galleries.
Many festivals and other special events, including a weekly farmers' market take place in the Gaffer District including:
Corning's Gaffer District is home to two of the most famous museums in Finger Lakes Wine Country. The Corning Museum of Glass and the Rockwell Museum of Western Art are both must-sees during your stay in Wine Country. Purchase a combination pass to both museums for a discounted rate. Kids and teens 19 & under are always free. Enjoy a free shuttle between the two museums and to Historic Market Street in the heart of the Gaffer District.
The Gaffer District also offers experience trails. Discover the Chocolate Trail, the Antiques & Collectable Trail, the Edible Excursions Trail, the Kids Adventure Trail. There is truly something for everyone in Corning's Gaffer District. Discover more.
The Gaffer District offers many options for dining. Whether you're looking for a classic pizzeria or upscale dining, you'll find it here. Discover culinary tastes at one of the district's restaurants, coffee shops, brewery and wine bar. Discover more.
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1 Park near Spencers Island, Nova Scotia
Parrsboro, Nova Scotia 18.83 miles E
Canning, Nova Scotia 20.23 miles SE
Kentville, Nova Scotia 21.06 miles SE
Berwick, Nova Scotia 21.42 miles S
New Minas, Nova Scotia 23.12 miles SE
Spencers Island, Nova Scotia (map) | (902) 392-2487
Sites: 24 | Latest Rate: $32.00 | 7 Reviews
|Clean Restrooms:
|Clean Showers:
Sep 2013 - $32.00
We would give this an 11, but the WI-FI is the worst, basically there is Wi-Fi, but you are lucky if you get a signal. The owners are FANTASTIC... we stay here every September and always will, as this is one of the best locations on this planet. It's just AWESOME ! - mapletod
Aug 2013 - $27.00
Awesome waterfront sites. The owners are extremely accommodating and friendly. The roads are bumpy getting there but it is definitely worth the trip. Highly recommend if you like waterfront and want to watch massive tides roll in and out. - Mountain
Jul 2013 - $32.00
If the thought of camping directly on the ocean, this campground is for you. All sites are literally feet from the Atlantic ocean. The picture on their website accurately depicts the campground. The washrooms are shared with an on-site restaurant and nearby in Advocate Harbour is a small grocery store and gas station (including diesel). This campground makes an excellent base for exploring Cape Chignecto Provincial Park, as there is no RV camping at the latter. It is also possible to do day trips to the UNESCO World Heritage site at Joggins. - driftdiver1


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I loved the overall look of this item, but after putting it up, it will not stand straight. It keeps leaning. Very disappointing.Published 3 months ago by Bonnie Waters
got this a while ago but it didn't make it thru the northeast winter, with all the ice and snow, it fell and cracked. Read morePublished 9 months ago by FJV
This bird bath is perfect for your yard. It is exactly as pictured and the birds that visit your yard will love it. Read morePublished 15 months ago by cowboysandy
It's exactly what it said it was a great feature to any garden the wiggles is amazing the birds love the moving waterPublished 16 months ago by Julie Disher
The birdbath was very light. I do like the fact that it came with a wiggler. However it blows over very easily in the wind. Read morePublished 19 months ago by NICU Nurse 21
While it is nice I was expecting it to be a heavier material than it is. The batteries that came with it though lasted longer than the average 2 months is said it would.Published 20 months ago by Peggy Stansell
I have an issue with the weight of this product. Even when filled with water, the wind blows it over. Read morePublished on July 20, 2013 by Irving E. Bressler
Very happy with bird bath. So far only a few birds have come but lots come to my feeders so I think shortly the birds will find and love it. Read morePublished on June 21, 2013 by Mary Mcgill
i looked at all kinds of bird baths, and decided on this one, even though i wanted a more "expensive" one. Read morePublished on June 18, 2013 by laura galvan


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The 115,000 students attending Pennsylvania's 14 state-owned universities can rest easy that a potential strike by faculty will not interrupt classes or final exams -- at least this fall.
Steve Hicks, president of the Association of Pennsylvania State College and University Faculties, said Tuesday the union has decided to put off consideration of a possible strike until the spring semester. He made the remark in an open letter to students.
The decision comes two weeks before the scheduled start of final exams at the 14 schools, including California, Clarion, Edinboro, Indiana and Slippery Rock universities in Western Pennsylvania. The State System of Higher Education and roughly 5,000 faculty represented by APSCUF are locked in a two-year labor dispute that is the longest in the system's three-decade history.
"Faculty know you are worried that your professors will go on strike. We know you are concerned about the impact a strike would have on your classes, your finals, and your tuition dollars," Mr. Hicks wrote. "After thoughtful deliberation and consideration about how a strike at this time would affect our students, we have decided to postpone consideration of a strike for the rest of this semester."


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STARmeterTop 5000
Down 80 this week
Ron Perlman (I)
Actor | Producer | Soundtrack
Ron Perlman is a classically-trained actor who has appeared in countless stage plays, feature films and television productions. Ronald N. Perlman was born April 13, 1950 in Washington Heights, Manhattan, New York. His mother, Dorothy, is retired from the City Clerk's Office. His father, Bertram "Bert" Perlman, now deceased, was a repairman and a ... See full bio »
More at IMDbPro » Contact Info: View agent, manager, publicist and company
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text: 20 Chrync, syncing Chrome bookmarks to your Windows Phone Windows Phone Apps By George Ponder, Tuesday, Jul 3, 2012 at 9:38 pm EDT Chrync is a nifty Windows Phone app that lets you sync your Chrome Browser bookmarks to your Windows Phone. The app doesn't require any special extensions for your PC browser and speaks to Chrome through Google servers over a secure link. More → 11 0 0 0


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Skip to Content - Skip to Navigation
Home > Academics > Colleges > Education and Educational Technology > Counseling > About Counseling > Goals and End-of-Year Reviews
Department of Counseling
1. Maintain 6 cohorts (3 school and 3 community) for Pittsburgh.
We have the complete 3rd MED, and have completed 6 cohorts. The 1st school cohort graduated and the 4th school cohort was admitted, and 9th MA cohort.
2. Review sequence of courses for Pittsburgh Programs.
We reviewed and made changes (adjust not overloading program).
3. Revise "tri-semester schedule" for CACREP.
We completed tri-semester.
4. Utilize additional complement...to create electives for licensure and current students, which would increase credit hour production.
We added one course per semester and created 3 year permit schedule that included electives.
5. Work with Graduate School to ensure high quality applicant pools.
2 times the number of applicants-school has increased in quality MED and MA has decreased in quality.
Special Recognition and Thanks to: Tri-semester: Drs. Branthoover, L'Amoreaux, Guth, Witchel, Dandeneau. Extra Admissions Work: Drs. Witchel, Dandeneau and Paul Sandusky. General Admissions: Everyone
1. Complete COUN 737 (Advance Counseling Theory) & COUN 674 (Addictions and Addictions Counseling) curriculum proposals.
Completed by Drs. Witchel and Branthoover
2. Submit curriculum proposals (CACREP) in early fall.
13 curriculum proposals were submitted in fall course descriptions and titles, and prerequisites made it through process with minor provisions.
3. Tri-semester schedule committee needs to meet and revise the schedule to address CACREP requirements.
Completed by Drs. Branthoover, Guth, Witchel, Dandeneau and L'Amoreaux.
4. Doctoral Program - distribute needs assessment to alumni, agencies, current students, regarding justification for launching. Write Notification of Intent in the Fall.
Needs assessment completed by Drs. Witchel, Dandeneau, and Marshak. Still need to get information from Dean.
5. Full curriculum review - complete packet of syllabi of record.
Completed full curriculum review and complete packet of syllabi of record.
Special Recognition and Thanks to: General Curriculum: Drs. Witchel and Branthoover. CACREP Curriculum: Dr. L'Amoreaux. Doctoral Program: Drs. Marshak, Witchel, and Dandeneau. Full Curricula Review: Everyone.
6. Advising workshop (recommend) for all department faculty.
Postponed advising workshop to Fall 2007.
We have:
1.Completed: Distribute brochures to area districts and agencies
2.Completed: Determine the feasability of WPIC videoconference series.
3.Completed: Other possible topics workshops: AIDS ***Needs assessment
4.Completed: Possible co-sponsorship of Allegheny School Counselors Association meeting
5.Completed: 1/07 School Counselor Professional Development Day
Special Recognition and Thanks to: Presenters on 10/28/06, students and graduate assistants, COE Dean, Dr. Lucky-Student Affairs, Colleen-Allegheny County, Advisory Board, CCTS, Departmental Business, IUP Research Institute
1. Ongoing
2. Mail, speakers, blinds
3. Used collaborations; move more towards site-based collaborations
Special Recognition and Thanks to: Drs. Guth, Branthoover, and Witchel, Paula Sandusky, Patsy, Graduate School staff, graduate assistants
Penn Center #1,2,3
1. Acquired technology fee grant money and acquired additional funds for Digital Counselor Training Facility in Monroeville
2. Equipment has been ordered and is currently being delivered
3. Equipment is scheduled to be installed this summer
4. Equipment for last year was assessed and additional TV, VCR, and DVD carts were purchased
1. Equipment and software installed in faculty offices for session viewing
Special Recognition and Thanks to: Drs. Dandeneau, Guth, and Branthoover, Chris Barber, Lloyd Onyett, Brad Smith, George Rogers, and IRIS folks.
1. Added one more Monroeville member, more equivalent MA & MEd membership, rotation voluntary, utilized newsletter for recruitment (ongoing).
2. Use of alumni listserv (continues) and mmore use of email for communication.
3. Completed Fall and Spring meeting - board gave departmental feedback (i.e. newsletter).
4. Resolved - no ACT 48 and CEU's
5. Results of CACREP survey presented and board meeting.
Special Recognition and Thanks to: Dr. L'Amoreaux - CACREP, Drs. Branthoover and Desmond for chairing the advisory board, Dr. Dandeneau - alumni listserv and Doctoral Survey, Dr. McCarthy, CCTS, Dr. Bruno - presentation and introduction to the board.
1. Had faculty attend CCTS workshops
2. Faculty have used professional development to attend a variety of conferences and workshops.
Special Recognition and Thanks to:
Dr. McCarthy!!!
1. Was a general goal addressed by subsequent goals, we will omit this goal for 2007-2008.
2. Completed via Alumni Newsletter and Counselor Link
3. Continued Newsletter to students and alumni
4. Continued faculty involvement in local, state, international and national conferences
5. PCA couldn't fund give away, but sponsored PCA Executive Council meeting at Penn Center instead
6. Completed - Distinguished Almuni nomination for Mr. Jerry Salandro of IRIS Tech, Inc.
Special Recognition and Thanks to: Dr. Witchel - Newsletter, Dr. McCarthy Center and IUP press release and IUP Reporter representative, Dr. Branthoover and Dr. Desmond - Advisory Board, Dr. Branthoover and Dr. Guth - site supervisors.
Special Accomplishments:
2. CCTS Workshops
3. Presentations at local and national conferences
1. Completed all goals with 2 hires
2. Attempted diversity particularly with regard to gender, male candidate turned down our offer
Special Recognition and Thanks to: Search committee - Drs. Witchel, Dandeneau, Bruno, Branthoover and Guth. Human Resources: Debbie Wardo. COE-ET Deans office: Dr. Rafoth and Ms. Koslezki.
1. Completed - submitting self-study early fall semester (electronic)
2. Completed - submitting curriculum proposals
3. Completed curriculum review
4. Site visits - both sites; follow through with recommendations of board
5. Examied doctoral programs with CACREP standards in mind
Special Recognition and Thanks to: Dr. L'Amoreax, Dr. McCarthy, graduate assistants, all faculty.
1. Did not complete a grants brainstorming workshop
2. Did not complete a grant writing workshop
3. Not applicable - see #1 and #2 above
4. Obtained one small grant from ACES and submitted federal elementary school counseling grant with Central Cambria School District
5. Conducted two contracted workshops through CCTS
6. Did not consider a white paper for federal funds for crisis
Dr. Desmond - ACES grant, Dr. Dandeneau - Federal elementary school counseling grant, Dr. McCarthy - CCTS.
Contracted Workshops: Dr. Witchel, Dr. Branthoover
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Hang tight!
Recipe by mysi caswell
"This is a great meal that can accommodate even the largest of appetites. It has everything in it but hassle. I also like to add a bit of BBQ sauce for a bit of a kick."
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1 pound
ground beef
4 large
russet potatoes, cubed
1 (11 ounce) can
creamed corn
1 cup
1 cup
3 (8 ounce) cans
tomato sauce
green onions, chopped
1/4 cup
fresh chives
ground black pepper to taste
1 cup
I am making this for tonight's supper. I started it before 7, but by noon, the potatoes still weren't done. I also added sliced carrots, which were also not done after 4 hours. I wasn't worried about it, though, since I didn't plan to serve it until dinner. I didn't brown the meat first and did add some beef base for additional flavor along with the salt and pepper and a bit of Adobo seasoning and paprika. I sampled it at lunch (minus the uncooked carrots and potatoes) and it really was good. Oh, and I didn't have barley, so I substituted rice in the same quantity, and I used diced white onions instead of green onions. Next time I might use pasta. It's totally worth trying and using as a canvas for other ideas!
Okay, I am not one for giving bad reviews, but after I made this, I went back and re-read the whole recipe, and I didn't leave anything out. Just a bad combination of good ingredients. AND, when I cooked it on low for 4 hours as directed, the potatoes were not done and the barley was still crunchy. NOT a keeper.
13 Ratings
After reading reviews, I altered this recipe and rated it according to my alterations: I upped the liquid, barley and added some more seasonings and boullion. 1 lb extra lean ground beef (seasoned with salt, pepper, garlic & onion while cooking) 3 medium potatoes, peeled & cubed 2 cups barley 1 8 oz can tomato sauce 6 cups water 4 beef boullion cubes 1 vegetable boullion cube (or 2 more beef cubes) 2 cups sliced, frozen carrots 1 cup diced onion 2 tsp to 1 tbsp black pepper 4 bay leaves 1 tsp garlic powder cook on low 5-6 hours. stir to loosen barley and keep from sticking to sides/bottom. add 1 can cream corn 2 cans green beans taste test for salt level check potatoes, carrots, barley for tenderness. If still not fork tender, increase temp to high for 30-45 minutes. Should not need more than 7 hours. makes 6 quarts! My 4 kids loved this, even asking for a third round! I am on Weight Watchers and not only is this filling, but very low in points!
This is pretty good and really hearty. I did make a couple changes. First, I used 4-6 oz sirloin steaks, cut up,
instead of ground beef. I used 3 large potatoes and I added a 6 oz. can of V8 and a bay leaf. I think it could have used a couple more of the steaks but my crock pot wouldn't hold that much.
I had to tweak this recipe A LOT! Here is what I did: 1. I used ground chuck instead of ground beef 2. I used about 1 cup of frozen whole kernel corn instead of cream corn 3. I added rice instead of barley 4. I used 2 small cans of tomato sauce and 1 can of petite diced tomatoes, drained 5. I used 1 yellow onion, chopped 6. I used about 1 Tbsp. of dried chives 7. I added about 1 Tbsp. celery salt, 1 Tbsp. sea salt, and 2 Tbsp. seasoned salt. It still did not really taste spicy enough so I added some more pepper and seasoned salt to my bowl. All in all, it is a good recipe. Just needed a little tweaking. Thanks!
Along with the other reviewers my potatoes were not done after 5 hours of cooking. I added some more water and cooked it on high for an hour so the potatoes would be done. This is a good base but needs more spice and more veggies. It was a little bland for my taste.
I was trying to throw something together with what I had around. (Probably didn't quite use what the instructions say either...) The result surprised me. My mom was really excited about it, the rest of us not quite as much but it was good.
* Percent Daily Values are based on a 2,000 calorie diet.
Slow Cooker Delight
Serving Size: 1/6 of a recipe
Servings Per Recipe: 6
Amount Per Serving
** Calories: 486
** Calories from Fat: 91
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This cabinet card portrait of a young to middle aged woman was taken at a photographic studio located in Trinidad, Cuba. She poses next to generic chair and in front of a poorly painted backdrop. She holds a small hand fan. The photographers name, according to a stamp on the reverse of the image, is Tomas Gil Gzalez. The street address of his studio was Calle De Desengano 73. Interestingly, "Desengano" translated to English means disillusionment or disenchantment. Most of us, at some time in our lives, have found our way to Disillusionment Street.
The URI to TrackBack this entry is: https://cabinetcardgallery.wordpress.com/2013/04/09/woman-finds-disillusionment-in-trinidad-cuba/trackback/
2 CommentsLeave a comment
Gzalez is likely an abbreviation for the last name Gonzalez. At that time it was common to use both paternal and maternal surnames. The photographers last name is most likely Gil-Gonzalez.


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Twitter will never stop growing, and many still prefer the micro-social network to share their photos on the go. It's fast, easy to use and can be used on almost any device. Twitter ditched Twitpic's photo sharing service and shook hands with Photobucket last year. Ever since then, nobody has been using Twitpic!
However, there are a few users out there, who still like to use the Twitpic services other than Twitter's own sharing service. All of those users, specially the iPhone users, will be happy to know that a separate Twitpic app is now available. Chances are, that most tweeters use third-party apps such as Tweetbot, Echofon (Mac) etc. Thus, Twitpic might still have a chance as most of the third party Twitter apps use their service to share photos and videos. The app takes cue from the famous photography app 'Instagram' and has similar effects and editing options for the photos. Here's the full list of features:
★ Quickly and seamlessly share your photos and videos with all of your Twitter followers
★ Edit your photos with beautiful filters and easy to use enhancement tools
★ Browse your Twitter photo timeline with photos from people you follow in a beautiful interface
★ Browse photos from the most popular Twitpic users
★ Manage your Twitpic photos and videos in your own timeline
Twitpic is available for free on the App Store. Let us know, if you'll be using this app to share your photos and videos on Twitter or will you stick to the stock Twitter iOS app? Use the comments section.
Download Twitpic for iPhone and iPod Touch [iTunes Link]


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Step 1: Find a suitable log.
Step 2: Cut, square, and de-bark
Step 3: Cut out the back.
Step 4: Hollow out the basin
Step 5: Mark and drill the fixture
very, very cool.
I have built a few pairs of log speakers and found teak oil for a first coat and Danish oil to finish works well for a durable waterproof coating that can just be wire wooled and refinished if it ever does start to taint unless you are going for the pure rustic look. But superb use for a big log hope more people take inspiration from you...!


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Tarrant County College is accredited to award an associate degree by the Southern Association of Colleges and Schools Commission on Colleges.
A list of program offerings is available online along with our degree and certificate plans.
This program awards a two-year associate degree and prepares students to enter a four-year college or university.
This program offers two study areas for a two-year associate degree which prepares students to teach children from K through 12.
This program awards a two-year associate degree which will enable students to enter as juniors at a four-year college/university with a major in a science discipline.
These programs offer two-year associate degrees in many technical, industrial, health and public service fields.
These are normally one-year programs that are designed to meet specific needs of the community.
Basics / Core Curriculum and Fields of Study are also flexible options for students who are interested in transferring to a four-year college or university.
Updated April 30, 2015


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UTSA considers smoke-free policy where smokers move off-campus
UTSA stands to lose science research grant if smoking on campus continues
SAN ANTONIO - UTSA is considering a smoke-free policy that would force smokers to move off-campus.
Already this year, University of Texas-San Antonio students became prohibited from smoking indoors and adjacent to buildings and walkways, but come 2013, UTSA would go smoke-free on campus.
A task force comprised of both smokers and non-smokers are putting together a smoke-free policy. Non-smokers are quick to point out the problem.
"As I'm walking on campus, there's just people everywhere, and smoke's just in my face," said Deanna Tran, a non-smoker.
And some say the new smoking limits already in place aren't doing much to curb that issue.
"People are walking out of classrooms, or walking out of buildings, and getting smoke blown at them," said Austin Hage. "Some people have issues with it."
Smokers on campus say the problem is not the ban itself -- it's what the ban will make them do, which is come all the way off campus for a smoke.
"It was hard for us to have to walk off campus to smoke and then come back," said one student. "And when people don't smoke, they are not exactly happy."
Josh Foster, a smoker, agreed. "That would suck if they took smoking off campus," Foster said. "A lot of people would be very angry.
The reasoning behind the smoke-free policy task force is money. The campus stands to lose a science research grant if smoking continues on campus.
As a result of issues like that, already campuses from Austin to Arlington have started bans of their own this semester.
Copyright 2012 by KSAT.com All rights reserved. This material may not be published, broadcast, rewritten or redistributed.


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Found in a copy of the Vignette Edition of the Poems by John G.[reenleaf] Whittier. Published in 1893 by the Frederick A. Stokes Company and illustrated by William A. McCullough. It really would have been something if it was stashed between pp. 98-102 were the poem "The New Wife and the Old" resides.
Book Patrol: A Haven for Book Culture
Book Patrol is a place where you can share in Michael Lieberman's passion for the printed word, the history of the book as an object and as a cultural artifact.


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Sony NEX-FS700 4K Ready Camera
- Product Details
Notes: To shoot 4k-RAW an external recorder is required (SonyHXR-IFR5 Interface Unit and Sony AXS-R5 4K Recorder) or Odyssey 7Q.Rental Includes:
Camera Highlights:
The Sony NEX-FS700 4K Ready Camera includes the Sony NEX-FS700 with hardware upgrades to completely support 4K when used with an external recorder. The NEX-FS700's imaging area matches that of standard Hollywood film cameras and features the ability to record bursts of super slow motion 4K video (bursts range from 8 to 16 seconds, depending on frame rate). This camera runs cool with no grain and no fan noise and is equipped with four ND filter levels: clear, 2, 4 & 6 stops. It can output 4:2:2 video (with embedded timecode) via HDMI 1.4 or 3G/HD-SDI to an external recording unit. This camera is ideal for 2nd unit shooters or for anyone working on feature films, commercials, music videos, or recording lectures.