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Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed by an interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, all interrupts received by the interrupt handler are formed into an event message according to a uniform format regardless of the manner in which the interrupt is signaled. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Event messages are stored in an event buffer for access and handling by the host. The event buffer is managed by the interrupt handler.
1. A system comprising:
a plurality of clients that perform processing tasks, and that signal interrupts in one or more of a plurality of manners;
an interrupt handler coupled via a system bus to a host interface controller, at least one host processor, and through a memory controller to a system memory, the interrupt handler further coupled directly to the plurality of clients, wherein the interrupt handler is operable,
to receive interrupts signaled by the plurality of clients;
to arbitrate among the received interrupts to determine in what order the received interrupts are to be handled;
to form an event message for each received interrupt signaled in one or more of the plurality of manners, wherein forming an event message comprises forming different event messages for different types of clients that; and
to request the memory controller to write the event messages in an event buffer, such that the event messages are accessible via the system bus to the at least one host processor for processing as interrupts, wherein the at least one host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.
2. The system of
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16. A method in a data processing system, the method comprising:
receiving a plurality of interrupts from a plurality of clients, wherein the plurality of interrupts include level-based interrupts and pulse-based interrupts;
arbitrating among the received interrupts to determine in what order the received interrupts are to be handled by a host processor;
forming an event message for each interrupt received, wherein the event message comprises a format that is the same for level-based interrupts and pulse-based interrupts, but includes different information; and
requesting through a memory controller that the event messages be written to a designated area of a system memory that is accessible to a plurality of host processors that handle interrupts, wherein a host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.
17. The method of
18. The method of
receiving a level-based interrupt;
receiving at least one of an interrupt type signal for the level-based interrupt, and an interrupt identification signal for the level-based interrupt; and
arbitrating among the received interrupts, including pulse-based interrupts and level-based interrupts.
19. The method of
storing the received level-based interrupt signals; and
transmitting one interrupt signal of the stored interrupt signals to a component for formation of an event message.
20. The method of
21. The method of
22. A method for processing interrupts, comprising:
receiving an interrupt from a client, comprising one or more of a message signaled interrupt (MSI) and a level-based interrupt;
arbitrating among the received interrupt and other received interrupts to determine in what order the received interrupts are to be handled by a host processor;
generating an event message from the interrupt, wherein the event message is in a same uniform format for an MSI and for a level-based interrupt;
transmitting a write request to a memory controller to request a write of the event message to an area in memory designated for event message storage, wherein the memory area is commonly accessible to a plurality of hosts; and
generating an interrupt signal to a host upon acknowledgement of the write request, wherein the interrupt signal indicates to the host that there are event messages in the area in memory, wherein the host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.
23. The method of
24. The method of
25. A method for handling interrupts, comprising:
an interrupt handler receiving multiple interrupts of different types from a plurality of clients of different types;
the interrupt handler arbitrating among the multiple interrupts to determine an order in which the interrupts are to be handled by a plurality of host processors;
the interrupt handler forming an event message in a consistent format for each of the interrupts of different types;
one of the plurality of host processors receiving an interrupt signal from an interrupt controller;
the host processor reading an event buffer that stores the event messages the plurality of clients, wherein the event buffer is commonly accessible to the plurality of host processors;
the host processor handling an interrupt specified by the event message read from the event buffer, wherein the host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt; and
the host processor signaling to the interrupt controller that the interrupt has been handled.
26. The method of
27. The method of
28. The method of
29. A computer-readable medium having instructions stored thereon, which when executed in a system cause an interrupt handling method to be performed, the method comprising:
an interrupt handler receiving multiple interrupts of different types from a plurality of clients, comprising clients that signal interrupts in different manners;
the interrupt handler arbitrating among the multiple interrupts to determine an order in which the interrupts are to be handled by a plurality of host processors;
the interrupt handler generating an event message in a uniform format for each interrupt, signaled in one or more of the plurality of manners;
the interrupt handier storing event messages in an event message storage area in a memory component that is accessible to a plurality of hosts responsible for servicing the interrupts, wherein storing comprises requesting a memory controller to perform a write to the memory component, wherein a host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt; and
the interrupt handler signaling one of the plurality of hosts that event messages are in the event message storage area.
30. The computer-readable medium of
31. The computer-readable medium of
32. The computer-readable medium of
33. The computer-readable medium of
switching out a context for clients that use pulse-based signaling;
receiving an indication from the host when a pulse-based interrupt has been handled; and
switching back in the context that was switched out.
34. A system comprising:
a plurality of components that perform tasks and report events, wherein the plurality of components comprises level-based components and pulse based components, and wherein the level-based components perform permanent tasks and the pulse-based components perform volatile tasks, wherein a permanent task involves a single thread of execution, and a volatile task involves multiple threads of execution by allowing its state to be saved and restored at selected points in time; and
an event handler coupled directly to the plurality of components, and further coupled via a system bus to a host interface controller, at least one host processor, and through a memory controller to a system memory, wherein the event handler is operable,
to receive interrupts signaled by the plurality of components, including different types of interrupts for the level-based components and the pulse based components;
to arbitrate among the received interrupts to determine in what order the received interrupts are to be handled;
to form an event message for each received interrupt signaled, including event messages in a consistent format for the different types of interrupts; and
to request the memory controller to write the event messages in an event buffer, such that the event messages are accessible via the system bus to the at least one host processor for processing as interrupts, wherein the at least one host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.
35. The system of
36. The system of
37. The system of
38. An interrupt handler apparatus, comprising:
an input unit coupled to a plurality of clients, wherein the plurality of clients include pulse-based clients that generate pulse-based interrupts and level-based clients that generate level-based interrupts;
an arbiter coupled to the input unit, wherein the arbiter receives the pulse-based interrupts and the level-based interrupts and determines an order in which the interrupts are to be handled;
an event buffer manager coupled to the arbiter to receive the pulse-based interrupts and the level-based interrupts, wherein the event buffer manager generates an event message in a predefined format for each of the pulse-based interrupts and the level-based interrupts;
a memory write controller coupled to the event buffer manager and configurable to request a write operation to a system memory to write the event messages to an event buffer, wherein the event buffer is accessible via a system bus to a plurality of hosts that process the interrupts, wherein a host handles interrupts specified by event messages according to the manner in which the interrupt were signaled, including performing a register write for a level-based interrupt.
39. The system of
40. The system of
41. The system of
The invention is in the field of scheduling operations in complex data processing systems.
In typical complex data processing systems, many different processing tasks or operations are being performed by multiple sub-units of the system at any one time. Usually, all of the operations of the system are under the control of a host processor, or central processing unit (CPU) that runs a particular operating system (OS). The CPU communicates with various input/output (IO) units of the system through one or more buses, such as a peripheral component interface (PCI) bus or a PCI Express (PCIE) bus for example.
The host processor manages operations in the system, including execution of various tasks by various IO units. The IO units must necessarily communicate a lot of information with the host processor in a manner dictated by the OS. For example, when a task is executing on an IO unit and becomes stalled or interrupted, perhaps because of lack of particular data for example, the IO unit generates an interrupt to the host processor in such a way that the host processor can identify the IO unit and the cause of the interrupt, "fix" the cause of the interrupt, and signal the IO unit that the problem is fixed and that it can proceed with the task. Traditionally, interrupts are signaled by the IO unit writing a value to an interrupt status register. According to one scheme, an interrupt status register may contain multiple bits, any one of which signals an interrupt when it is a particular value, such as a logic "1" (also referred to as a logic high). The values in the interrupt status register are OR'd and if any of the values is high, an interrupt signal is sent to the host processor, which must perform a register read to determine which bit or bits are high. The host processor also must perform a register write to clear interrupts after fixing their causes. This interrupt scheme is sometimes referred to as level-based, because the level of the interrupt bit and line remains at the level set by the IO unit until the interrupt is cleared by the host processor.
IO units are often sophisticated special-purpose processors such as graphics processing units (GPUs). As greater processing speeds are demanded for complex functions, such as graphics processing or video processing, techniques for maximizing the use of system resources constantly evolve. System resources include processing units (such as GPUs), and memory. One common technique for maximizing the use of processing system resources is multi-threaded processing, which requires context switching between tasks. Resources capable of context switching encounter an event that causes the pause or stall of one task, and in response, store the current state of the stalled task (also referred to as switching out the current context) and proceed with another task (or switch in another context) while waiting for the cause of the stall to be cured, or fixed. The host processor must be informed of the stall, for example by the resource issuing an interrupt to the host, and the host is responsible for fixing the cause of the interrupt, and informing the resource that it can switch the previous context back in and continue with the operation that had been interrupted. Such interrupts are not level-based, but are typically signaled by a pulse. In addition, such interrupts do not require storage of interrupt status information in a register, or register reads and writes by the host processor.
In a context-switching environment, the traditional register-based signal-clear mechanism no longer works. This is because the interrupt status register becomes context-sensitive. Consider the following scenario: an IO unit client under a particular context generates an interrupt; a moment later the context is switched away. When an interrupt service routine (ISR) of the host comes to service the interrupt, it reads the interrupt status register which now belongs to a different context. There are race conditions in such a scenario. An interrupt delivery mechanism that is functional in context-switching systems is thus required. One mechanism for supporting context-based interrupts over a PCIE bus is called message signaled interrupt, or MSI. Another mechanism for supporting context-based interrupts over a PCIE bus is MSI-X, which is another version of MSI. MSI allows up to 32 different interrupt sources to have their unique messages without the need for the ISR to read hardware registers. MSI-X expands the number of interrupt vectors to up to 2048.
But traditional level-based interrupts should also be supported for transitional systems or system components that support only level-based interrupts and do not support MSI or MSI-X.
In order to support context-switchable environments, one cannot associate a fixed vector with a given interrupt source. One reason is that an interrupt source can be associated with different contexts. Since all interrupt events must be reserved, if an interrupt source is assigned to a fixed vector, it is possible for a vector to be overwritten by a second interrupt before the ISR processes the first interrupt associated with the first context.
Another reason the traditional register-based mechanism is impractical for complex IO units, regardless of whether context switching occurs or not, is that the number of interrupt sources keeps growing. For example, the number of different interrupt sources for a complex GPU exceeds what a single traditional 32-bit interrupt status register can accommodate. If the ISR has to read the interrupt status register, it may need to read more than one register to locate the interrupt source. Register reads from software (the OS) are slow by nature, but the ISR may have hundreds of interrupts per second to service. This creates performance concerns.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 102 is first introduced and discussed with respect to
Embodiments of a system and method for handling interrupts are described herein. In an embodiment events, or interrupts from various client components in a system (also referred to as clients) are processed by one event handler, or interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, the non-context switchable, level-based components perform permanent tasks, and the pulse based, context switchable components perform serialized volatile tasks. In an embodiment, a permanent task involves a single thread of execution, while a volatile task involves multiple threads of execution by allowing its state to be saved and restored at selected points in time.
In an embodiment, each interrupt received by the interrupt handler is formed into an event message according to a uniform format regardless of the interrupt type or source. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Embodiments include an IO unit interrupt handler that collects all interrupts generated by clients of the IO unit and forms them into event messages. The interrupt handler stores event messages from the input unit into a designated event buffer in memory that is accessible to the host processor, also referred to simply as the host. The interrupt handler also sends an interrupt signal to the host, which responds by reading the event buffer and handling all of the event messages appropriately. The host acknowledges a pulse-based interrupt by updating a read pointer of the event buffer; and acknowledges a level-based interrupt by a register write to clear the interrupt source. In an embodiment, the read pointer is updated by interrupt handler software running on the host after it has read the contents of the event buffer that lie between the current state of the read pointer and the current state of the write pointer. Embodiments further include an adapter unit that receives level-based interrupts from level-based interrupt clients and generates an appropriate event message for storage by the IO unit to the event buffer.
The host 104 may be any central processing unit, such as a processor that is intended for consumers who wish to run various applications. The host 104 also includes or communicates with hardware and software (not shown) to facilitate transactions on the bus 124. For purposes of this disclosure, the host 104 and other components, such as the memory 108 are understood to communicate via the bus 124 through any necessary hardware and software that it known in such systems, but is not shown here for clarity. For example, various system components may be coupled via one or more bus bridges in a known manner. The IO unit 102 may be any IO unit that is capable of performing a function under control of the host 104 according to the applicable operating system of the host 104. As an example for purposes of illustrating the embodiments, the IO unit 102 is a graphics processing unit (GPU). Embodiments of the invention include any relatively complex IO unit along with a host that is capable of controlling one or more such complex IO units.
The IO unit 102 includes various clients, each of which performs a designated operation or operations. For example, the clients may include various sub-units or components. For example, when the IO unit 102 is a graphics or video processor, the clients may include a 3-D engine, and a video engine. The clients include multiple context-switchable clients 112 and multiple "legacy clients" 114. Herein, the term "legacy" refers to clients that are capable of level-based interrupt signaling, such as a display engine for example. Context-switchable clients 112 typically include such sub-units as 3-D engines and video engines. The numbers of clients 112 and 114 shown herein are for illustration only and are not limiting.
The context-switchable clients 112 and the legacy clients 114 communicate with an interrupt handler 106. The context-switchable clients 112 communicate with the interrupt handler 106 via an interface 113. The legacy clients 114 communicate with respective adapters 116. As further explained below, the adapters 116 facilitate uniform handling by the interrupt handler 106 of both level-based interrupts from the legacy clients 114, and pulse-based interrupts from the context-switchable clients 112. Context-switchable clients 112 perform volatile tasks and generate pulse-based interrupts. Communication between the context-switchable clients 112 and the interrupt handler 106 includes an interruptible message stream. The legacy clients communicate with the interrupt handler 106 via the adapters 116 and an interface 113.
The IO unit 102 further includes a memory controller 118 and a local memory 120. The memory controller 118 has the capability to access the local memory 120, and also the system memory 108 via the bus 124. The host 104 has access to both the system memory 108 and the local memory 120. Accesses of the local memory 120 by the host 104 occur through a host interface controller 122, and are typically slower than accesses of the system memory 108 by the host 104 via the bus 124.
The host interface controller 122 communicates with the interrupt handler 106 via an interface 107. The host interface controller 122 communicates with other system components external to the IO unit 102 via the bus 124 and controls access in both directions between the host 104 and the IO unit 102.
As further described below, the system memory 108 includes an event buffer 110 that is designated to store event messages at the request of the interrupt handler. In various other embodiments, the event buffer may be located elsewhere, such as in the local memory 120, or any other memory location that is accessible by both the interrupt handler 102 and the host 104. The event buffer 110 is read by the host 104, and an interrupt service routine (ISR) 105 of the host 104 handles the interrupts associated with the event messages stored in the event buffer 110.
In an embodiment, the event buffer 110 is allocated in cacheable system memory 108, which allows the ISR 105 to quickly read event messages. The ISR 105 is not expected to write to the event buffer. It is preferable for the write pointer writeback location to be a location that allows the ISR 105 to read the read pointer quickly. In an embodiment in which the IO unit is a GPU, the cacheable system memory is mapped to a graphics address remapping table (GART). In various embodiments the GART may support virtual mappings, per-context mappings, or global, system mappings
The size of the event buffer should be sufficient to buffer the speed difference as a result of parallel execution between hardware and software. In worst cases, hardware may be generating interrupts in the order of thousands per second, and software may be overloaded by interrupts. The ISR 105 should try to avoid overflow of the event buffer where possible. In an embodiment, the event buffer 110 stores 4096 event messages of 128 bits each, or 64 Kbytes. The event buffer 110 in various embodiments could be smaller or larger than 64 Kbytes, and can be allocated based on empirical data.
In an embodiment, the control of the event buffer 110 is similar to the control of a ring FIFO buffer. There is a read pointer for the consumer, a write pointer for the producer, and a wrapping mechanism. One property of the event buffer 110 is that the consumer, in this case the ISR 105, can be designed to consume all outstanding interrupt data in the event buffer 110 instead of processing one interrupt and returning, which may be less efficient. By processing all outstanding interrupts, the ISR 105 also has the opportunity to prioritize those interrupts in an order desirable to software.
There may be an issue when the ISR 105 is slowed or stopped while processing interrupts, causing the event buffer 110 to overflow. As hardware cannot wait for software, the choices include stopping the generation of subsequent interrupts, or overwriting unprocessed older interrupts in the event buffer 110. In an embodiment, there is an option to stop the generation of subsequent interrupts, which is controlled by a register setting. It is suggested that losing older interrupts that signaled outdated events is a better choice over losing more recent interrupting events. Therefore there is a flag to indicate such overflow events from hardware, so that the ISR 105 can capture the more recent interrupts by calculating the difference between the read pointer, the write pointer, and taking the overflow flag into account. Embodiments support both losing older interrupts and losing newer interrupts. Under normal situations, software should be able to set up a reasonably sized ring buffer (2048 entries, for example) that is sufficient to buffer interrupts.
The interrupt handler 106 sequences through all outstanding interrupt requests from all clients 112 and 114, maintains the event buffer 110, and signals the host interface controller 122 to signal an interrupt to the host 104. There is also an option to stop the generation of subsequent interrupts, which is controlled by a register setting.
As previously shown and described, the interrupt handler 106 communicates with the memory controller 118 and the host interface controller 122, each of which communicate with other system 100 components via the bus 124. The host 104, and the system memory 108 and its event buffer 110 are also shown connected to the bus 124. As previously explained, a connection as shown in the figure may not actually be a direct connection, but is shown as such for clarity of illustration.
Various context-switchable clients 112 are shown, as well as various legacy clients 114. The context-switchable clients 112 and the legacy clients 114 communicate interrupts to the interrupt handler 106 via respective interfaces 113. The interrupts are stored in an input unit 202, which in an embodiment is a series of first-in-first-out buffers (FIFOs) as shown. The input unit 202, in an embodiment, contains a consumer FIFO for each client interface 113. The input unit 202 receives at least one signal from the clients, including an interrupt occurrence and at least one of an interrupt source identifier and an interrupt type identifier.
An arbiter 204 receives interrupt requests from the input unit 202 and arbitrates among them to determine in what order they will be handled (also referred to as serviced or processed). In an embodiment, the arbitration scheme is a round-robin scheme in which the output of the input unit 202 FIFOs is processed in the order received. In other embodiments, as further described below, other arbitration schemes could be employed, including priority assignment based on information in the interrupts.
Each context-switchable client 112 sends an interrupt request to the interrupt handler 106 along with a context identification (context ID) value. In an embodiment, the client-interrupt handler interface 113 includes a CLIENT_IH_interrupt_send signal that indicates the client is sending the interrupt handler 106 an interrupt. The interface 113 further includes a CLIENT_IH_interrupt_id, which in one embodiment is an interrupt source identification (ID) sent over four cycles. The CLIENT_IH_interrupt_id stays active until an acknowledgement is received. An interrupt source ID uniquely identifies the interrupt source.
The interface 113 further includes a CLIENT_IH_interrupt_ctxid signal. From a context-switchable client 113, the CLIENT_IH_interrupt_ctxid is a Context ID associated with an interrupt and sent over four cycles. In one embodiment, the Context ID is 28-bits. In the case of legacy clients 114, this part of the interface 113 may be used to send supplemental information.
The interface 113 further includes a CLIENT_IH_interrupt_free signal that is transmitted to the sender to indicate the interrupt-sending transaction is complete and the sender is free.
The interface 113 further includes a CLIENT_IH_block_status signal, which is a single null-protocol line used by legacy clients 114. In an embodiment, the CLIENT_IH_block_status signal is the OR of all of the legacy client's interrupt status bits. The CLIENT_IH_block_status signal is made available in the interrupt handler level_status register 232.
The event buffer controller 206 receives interrupts and stores them as ordered event messages in the event buffer 110. The event buffer controller 206 keeps track of an event buffer 110 read pointer (RPTR) 230 and an event buffer 110 write pointer (WPTR) 220 to determine if enough space is available for the current event message. Event buffer full, full drain and overflow conditions are also determined in the event buffer controller 206. If there is enough space in the event buffer 110 and memory write controller 208 is ready, the event message is sent to the memory write controller 208. The event buffer WPTR 220 is incremented when the memory write controller 208 acknowledges write clean of memory write requests. A timestamp of the interrupt request is captured in the memory write controller 208 in units of 128-system clock (128-sclk). In an embodiment, the system clock uses a crystal-based clock counter, which provides a relatively more stable clock. The timestamp is packaged with the interrupt request to form an event message. In an embodiment, the WPTR 220 is a hardware pointer and should not be written under normal operations. In an embodiment, the event buffer controller 206 contains a 32-deep FIFO. This FIFO size can be changed, for performance analysis purposes for example.
For context-switchable interrupt clients, each event message includes at least one of a context ID and an interrupt source ID. For non-context-switchable interrupt clients, each event message includes an interrupt source ID and a flag indicating the non-context switched nature of the interrupt, or a unique context ID as the flag. The event message according to an embodiment is 128 bits as illustrated in Table 1.
The ISR 105 can decide whether a context ID is present when processing an interrupt by doing a table lookup on the Interrupt Source ID field. The full list of interrupt sources (not shown) indicates which are context-specific. Non-context switched interrupt sources can make use of the Source Data field for interrupt-specific information to be delivered to the system, which reduces register reads for the ISR 105.
In an embodiment, the interrupt handler 106 is responsible for generating the interrupt source ID. One option for identifying the interrupt source is to assign a hard-code ID to each of the interrupt sources based on their input line into the interrupt handler 106. The ISR 105 uses the same set of hard-coded IDs to identify the interrupt source. Another option is to set up an array in the interrupt handler 106 internal memory for software to program each interrupt source with a desirable ID. This involves either an index/data register pair for software to assign an arbitrary interrupt source ID, or a self-incrementing counter for software to write the interrupt source IDs to the array in sequential order. This option allows the ISR 105 flexibility to group interrupt sources that go into the same process code paths. Generally, the ISR 105 should be able to process different interrupt sources with pre-coded values with little overhead, even when some interrupts are processed by the same code path. Some components have multiple sources internally, so they will pass the Source ID explicitly. If there is only one internal source for a particular component, its Source ID may be hard-wired.
The SCLK counter is used as a timestamp for each interrupt triggering event. The timestamp is used by software to trace interrupt-generation, in handling time differences, and in debugging potential interrupt problems such as interrupt loss, overrun, anomaly in servicing time intervals, and performance analysis.
Interrupt sources are listed in a table (not shown) that includes various attributes for each source. A "Source Type" attribute indicates whether the ultimate source in the driving component is a level or pulse. A "Combined I/F To IH" attribute indicates that one interrupt interface covers more than one source. Some level-based interrupt clients may choose to OR their internal interrupt sources together to a single line to the interrupt handler. If the interrupt sources are OR'ed, the ISR first identifies the interrupt client from the event buffer, and reads the interrupt status register in the interrupt client. The mask (if applicable) and acknowledgement is also made in the interrupt client rather than the interrupt handler. Most legacy clients provide access to the individual interrupt signals before they are OR'ed. These can make use of the interface adapter described later.
A "FIFO Depth" attribute specifies how many entries are needed for the data link between an interrupt client and the interrupt handler. This is to account for the latency due to the interrupt handler waiting for previous interrupt requests to go through the memory controller. If the memory controller FIFO is full, the interrupt client is back-pressured to stall.
A "Mask & Clear" attribute indicates whether interrupts are permanently lost when the source is masked, and whether an interrupt source needs a register write to clear. Masks are discussed further below. Level-based interrupts cannot be lost because their level remains high until a clear is received from the ISR 105. Pulse-based interrupts are lost when masked, because the interrupts are transient and there is no sticky status maintained.
A memory write controller 208 receives event messages from the event buffer controller 206 and communicates with the memory controller 118 to request writes to the event buffer 110 in the system memory 108. The memory write controller 208 receives an event message from the event buffer controller 206. In an embodiment, the event buffer controller 206 contains a 32-deep FIFO. This FIFO size can be changed, for performance analysis purposes for example. The event messages are sent to the memory write controller 208 on a debit/credit protocol in an embodiment. The default number of credits is 16. The minimum number of credits to send an event message is two.
The memory controller-interrupt handler interface 109 is used to perform writes of event messages to the event buffer 110. In an embodiment, the interface 109 has an aligned write request size of 8 Bytes, with an 8 Byte data field. In an embodiment, a write mask is included, which indicates when asserted that a particular 1 Byte in the write data should be written to memory. For read/write coherency the memory write controller 208 may use two-phase write-clean signals. Any memory controller interface appropriate to the normal operation of the system is applicable to embodiments as described herein.
A register unit 218 performs register writes and reads in an interrupt handler 106 register decode space. Serial register commands are received from the host interface controller 122. The interrupt handler registers in the register unit 218 are updated based on the de-serialized register command. For register reads, the register value is serialized and sent to the host interface controller 122. The register unit 218 includes the WPTR register 220 and the RPTR register 230. The register unit 218 also includes a WPTR address register 224, a base address register 228, a write overflow register 222, and an event buffer size register 226. The event buffer size register 226 in an embodiment contains the size of the event buffer 110 expressed in log 2 of the actual size in DWORDSs. The value is between 3 and 16. Event buffer size=2^RB_SIZE DWORDs. The event buffer is full when 2^RB_SIZE-1 DWORDs are consumed. A level status register 232 contains the status of each level-based client 114.
The host interface controller-interrupt handler interface 107 is used for the interrupt handler 106 to communicate an interrupt from the interrupt generator 216 to the host 104. The interface 107 is also used by the host 104 to update the RPTR 230 of the interrupt handler 106.
The interrupt handler 106 further includes an interrupt generator 216 that generates an interrupt signal to the host 104 through the host interface controller 122. In an embodiment, the interrupt generator 216 generates rising and falling edges on the an interrupt line. If the event buffer is enabled, the interrupt line is asserted if the RPTR 230 and the WPTR 220 mismatch. If the event buffer is disabled, the interrupt line is asserted based on the OR of client status lines.
A performance counter 210 receives performance signals from all other units in the interrupt controller 106. In an embodiment, two 32-bit performance counters are supported. Events to be profiled are selected from a list in a particular register.
A status unit 212 collects status signals from all the units in interrupt handler 106 and reports them in a status register.
For purposes of illustration, the adapter 116 is shown supporting three independent interrupt source lines, int_line_A, int_line_B, and int_line_C, each supported by an input block 302. Each block 302 also receives an int_type_X signal, and an int_id_X signal. The adapter 116 can support any number of lines with any number of blocks 302. Each line is received by detector (DET) unit 304 that can be configured to handle the protocol of the incoming line. A detected new interrupt event goes to a requester unit (REQ) 306 that asks an arbiter (ARB) 312 to queue a new request into a request FIFO 314. Each line also has its own hard-wired source ID, set by tying off the int_id_X inputs. If a new interrupt event arrives before the request is queued, or the request FIFO overflows, an overrun flag is set. New interrupt events are lost if there is an overrun. Overrun status can be read from a status register 310 by the host via the host interface controller. The OR of all level-type inputs (the output of an OR gate 316) is sent to an interrupt handler status register. In an embodiment the adapter 116 includes line configurations, as shown in Table 2, which determine a line type. Other specific configurations are possible.
Miscellaneous Considerations
Various considerations may apply in different embodiments. Some of these are described below.
"Re-Arm" Mechanism
Accommodation is made in the interrupt handler for legacy interrupt clients that would like to remain unchanged. As previously discussed, legacy interrupts clients use level-based interrupts. When such a client generates an interrupt, it raises its interrupt line. When the ISR has serviced the interrupt, the corresponding register "ACK" bit is cleared by software, and the level goes down. The interrupt handler communicates with the host interface controller with a level-based line. The host interface controller detects the rising and falling edges of the line and generates ASSERT/DE-ASSERT signals (or an MSI message) to the system depending on whether MSI is enabled. The interrupt handler makes a logical OR among all level-based interrupt clients. The interrupt handler also makes a comparison between the read pointer and the write pointer. The interrupt line keeps its level high if any level-based interrupt client has its level high, or when the read pointer and the write pointer mismatch. The line goes low when all level-based interrupts are cleared and the read/write pointers equal. One implication for this level-based interface is that, when MSI is enabled, a "re-arm" mechanism needs to be implemented to trigger another interrupt event for any interrupts remaining unprocessed when the ISR returns to the OS. This implication is further explained in the paragraphs below.
There are two scenarios in which interrupt generation is handled in different ways because the MSI may be enabled or disabled by the system. In both cases below, the ISR is responsible to keep the read pointer register updated when servicing interrupts, and to clear level-based interrupt status registers.
When MSI is disabled, interrupts are handled by system software in the same way as level-based interrupts; that is via the INTx mechanism to check/clear interrupts. Hardware sends ASSERT signal to set INTx when there is an outstanding interrupt, and sends DE-ASSERT signal to clear INTx when there is no outstanding interrupt. The host interface controller detects the rising and falling edges from the interrupt handler. A rising edge triggers an ASSERT signal to the system, and a falling edge triggers a DE-ASSERT signal to the system.
Generation of a new interrupt will set the IH_host-interface-controller interrupt line to high, which will trigger an ASSERT. If the line is already high, a new interrupt generated will have no effect because INTx is already set, and a new ASSERT is ignored by the system. When the ISR finishes processing and returns to the caller (e.g., the OS), if there is an outstanding interrupt, the caller will call the ISR again because INTx has not been cleared.
When all interrupts are processed, the read and write pointers will be equal (and the write pointer overflow bit is cleared), and all level-based interrupts are cleared. In that case the IH→host-interface-controller interrupt line goes low, which triggers a DE-ASSERT signal to clear INTx.
In an MSI-enabled environment, interrupts are signaled by messages (as memory write requests) rather than levels. A new message needs to be sent by hardware if the ISR did not process all outstanding interrupts in its previous run. For example, there can be a second interrupt generated during the ISR processing of the first interrupt. The ISR is unaware of the second interrupt because it has passed the point of reading the write pointer, or it has passed reading the interrupt status register. When the ISR returns to the caller, the second interrupt remains unprocessed. Hardware needs to recognize this outstanding interrupt and issue another MSI event. Otherwise, unless there are subsequent interrupts, the second interrupt is effectively lost. Even if there is third interrupt coming, the ISR has to wait longer to catch the second interrupt, which may not be a good option for performance reasons.
The host interface controller detects the rising edges from the interrupt handler. A rising edge triggers an MSI message. Falling edges are ignored. If there is a second interrupt generated while the first one has not been cleared, the IH→host-interface-controller interrupt line will remain high. There will be no rising edge for the second interrupt, so there will not be a new MSI message. To solve this issue, a "re-arm" mechanism injects a temporal low-level in the IH→host-interface-controller interrupt line in order to get another rising edge. The new rising edge will then trigger a new MSI message to the system. The pulse needs to be maintained for two or more cycles to safeguard the pulse detection in the host interface controller.
In order to "re-arm," the ISR programs a "re-arm" register every time before it returns to the caller. This gives the system an opportunity to generate a new MSI message to call the ISR again, if there is an outstanding interrupt. When the event buffer is enabled, because the ISR needs to update the read pointer each time, writing to read pointer serves as a trigger for the interrupt handler to determine if read pointer=write pointer, and if all levels from legacy clients are low. A pulse is inserted on the IH→host-interface-controller line if either of the two conditions is not met. When the event buffer is disabled, the check of read pointer=write pointer is suppressed and only levels for legacy clients are checked. For consistency, writing to the read pointer again serves as a re-arm trigger.
Lossless Mask
For pulse-based interrupts, masking new interrupts would mean their permanent loss. This is because they are temporal interrupts without a sticky status register. When the mask is turned on, an interrupt is not triggered. When the mask is turned off, the interrupts are already gone. Whether this is acceptable depends on how software will be using those interrupt masks. In some cases, all masks are on at initialization time. When an ISR client registers, the corresponding mask is turned off, and that interrupt is enabled. Of course, an ISR client can come and go dynamically, but the client would not be interested in past interrupts (before its registration time). It should be acceptable for such clients to lose older interrupts from before their lifetime. There are some exceptional interrupts which gets masked on/off from time to time without re-registering. In this case, an additional interrupt may be added after turning off the mask. Masking level-based interrupts does not cause any loss.
Aspects of the embodiments described above may be implemented as functionality programmed into any of a variety of circuitry, including but not limited to programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices, and standard cell-based devices, as well as application specific integrated circuits (ASICs) and fully custom integrated circuits. Some other possibilities for implementing aspects of the embodiments include microcontrollers with memory (such as electronically erasable programmable read only memory (EEPROM)), embedded microprocessors, firmware, software, etc. Furthermore, aspects of the embodiments may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course the underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (MOSFET) technologies such as complementary metal-oxide semiconductor (CMOS), bipolar technologies such as emitter-coupled logic (ECL), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, etc.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number, respectively. Additionally, the words "herein," "hereunder," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. When the word "or" is used in reference to a list of two or more items, that word covers all of the following interpretations of the word, any of the items in the list, all of the items in the list, and any combination of the items in the list.
The above description of illustrated embodiments of the system and method is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the system and method are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The teachings of the disclosure provided herein can be applied to other systems, not only for systems including graphics processing or video processing, as described above. The various operations described may be performed in a very wide variety of architectures and distributed differently than described. In addition, though many configurations are described herein, none are intended to be limiting or exclusive.
In other embodiments, some or all of the hardware and software capability described herein may exist in a printer, a camera, television, a digital versatile disc (DVD) player, a handheld device, a mobile telephone or some other device. The elements and acts of the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the system and method in light of the above detailed description.
In general, in the following claims, the terms used should not be construed to limit the system and method to the specific embodiments disclosed in the specification and the claims, but should be construed to include any processing systems and methods that operate under the claims. Accordingly, the system and method is not limited by the disclosure, but instead the scope of the method and system is to be determined entirely by the claims.
While certain aspects of the method and system are presented below in certain claim forms, the inventors contemplate the various aspects of the method and system in any number of claim forms. For example, while only one aspect of the system and method may be recited as embodied in computer-readable medium, other aspects may likewise be embodied in computer-readable medium. Accordingly, the inventors reserve the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the system and method.
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text:
Couple survives after car crushed by lumber that fell off truck on I-70 near Georgetown
Lumber truck shoves car against guard rail
GEORGETOWN - It's a vacation that one Minnesota couple will never forget.
Albert and Julie Watkins had spent some time hiking in the mountains near Vail. They were driving back to Denver early Friday when they noticed a lumber truck spewing smoke on I-70 east of the Continental Divide.
"We had just come out of the Eisenhower Tunnel," Albert Watkins told 7NEWS. "There was a cluster of vehicles. We saw the truck with smoke. We watched. It looked like he was slowing down and under control."
Watkins says that a few minutes later, the truck began passing everyone in the right lane.
"I told Julie, 'the trucks in trouble,' he said. "And a few seconds later I said, 'we're in trouble.'"
The truck, driven by Justin Knapp, began fishtailing and slammed into the Watkins' rental car, pushing it into the guard rail and spilling its load of lumber onto their car and all over the highway.
"The car sounded like it was in a junkyard compacter," Julie said. "We could hear the crunching."
"You could hear it popping," Albert said.
"I thought for sure they were going to pull us out of there like sardines," Julie added.
But once their car came to a stop, the Watkins climbed out through the passenger door window.
"We got out of there as fast as we could," they said.
Georgetown resident Richard Gorman heard the crash.
"Didn't hear any brakes," he said. "I did hear a roar and this sliding/grinding sound."
Gorman says he ran to his window, looked up the hill and saw a plume of dust "that just kept coming."
He said at first he worried that a truck might come tumbling over the guard rail and down the hill into his house.
"I was ready to run outside," he said.
A few minutes later he walked up the embankment to the crash scene.
"I did not want to look into the car," he told 7NEWS, fearing there might be carnage inside.
But Gorman was surprised to learn that the occupants, the Watkins, were already standing outside, shaking in disbelief, but grateful to be alive.
"I asked if they needed anything," he said. "They wanted to know where you can rent a car in Georgetown. I explained that we don't have a car rental place in Georgetown."
Gorman said the only injuries he saw were a couple of scratches on Julie Watkins' arm.
The truck driver told authorities that his truck lost oil pressure and that the engine seized up.
"There was no power for the brakes or the horn," he said.
The accident forced the closure of both eastbound lanes of I-70 for about two hours. Work crews were then able to open one lane to traffic, but it took several more hours to remove all the lumber from the highway.
"I will never, ever again pass a truck that's starting to smoke," Watkins said. "That's what I take away from this."
"Our angels were very busy today," Julie said, "because we are here."

subset: commoncrawl


text:
Pop Internationalism by Paul Krugman
Value Added
Pop Internationalism
by Paul Krugman
MIT. 221 pp. $22.50
Paul Krugman—a self-described liberal, an adviser to the 1992 Clinton presidential campaign, and someone who was once thought to have the inside track to a job as head of the White House Council of Economic Advisers—ranks in the handful of top international economists in the world. He is also the author of works that have rubbed strongly against the grain of economic orthodoxy, questioning, for example, classical theories of trade that had gone unchallenged since the English economist David Ricardo formulated them in the second decade of the 19th century.
Iconoclast though he may be, Krugman is in one sense a straight-arrow traditionalist: he believes you cannot begin to question the laws of economics until you at least know the ABC's. This is a test which, he has never been afraid to say, many within his profession, and many others around it, have consistently foiled, being caught up rather in self-promotion, power-seeking, and bald-faced intellectual dishonesty. The "pop internationalists," Krugman's designation for apostles of a variety of false nostrums about international trade, are particular offenders.
This is one of the more forceful attacks written by an academic in recent years. Krugman's List of those peddling specious doctrines includes Secretary of Labor Robert Reich (formerly a lecturer at Harvard's Kennedy School), Lester Thurow of MIT, the journalists James Fallows and Robert Kuttner, think-tank denizens like Clyde Prestowitz and Edward Luttwak, and presidential idea-man Ira Magaziner: for Krugman, phonies, con-artists, liars, and pseudo-intellectuals all. He trundles out their books, each with its ex-cathedra tone, its military metaphors, its hubristic policy prescriptions, and finds a common thread, or lack of thread:
a complete absence of anything that looks like the kind of international trade theory that academic economists teach. . . . It is not a matter of a lack of familiarity with the latest wrinkles in research. Rather, nothing of international trade theory as economists know it—from Ricardo on—is in these books.
One prominent theme of pop internationalism, according to Krugman, is "competitiveness," a term that has gained wide currency but that is close to meaningless in Ricardian economics. Thus, Jacques Delors of the European Community gives long speeches on how "competition" from lower-wage economies has caused high French unemployment—it has not—in order to avoid confronting the wasteful French welfare state. And President Clinton characterizes the United States as akin to a corporation in a competitive marketplace—it is not—in order to justify a number of his own economic policies. "The growing obsession in most advanced nations with international competitiveness should be seen," writes Krugman, "not as a well-founded concern but as a view held in the fece of overwhelming contrary evidence."
Krugman is at his best in identifying dubious scenarios of disaster, which he then reduces to their underlying illogic. He starts with Lester Thurow's claim that our trade deficit with Japan has been responsible for a 6-percent drop in real wages over the last two decades. Granting, for argument's sake, Thurow's wild assertion that a million manufacturing jobs have been lost and that the slots which replaced them pay 30 percent less, Krugman shows by simple arithmetic that even such a momentous shift would depress the wage rate not by 6 but by 0.3 percent—putting Thurow off by a factor of twenty.
Krugman similarly demolishes the widespread view (purveyed by Robert Kuttner, among others) that trade with low-wage countries like Mexico is responsible for American wage stagnation (shades of Jacques Delors in France). This may be possible in theory, Krugman allows, but practice is something else. For one thing, the average weighted wages of America's trading partners (excluding oil producers) are now up to 88 percent of U.S. wages. For another, in 1990—a typical recent year—the industrial nations spent only 1.2 percent of their Gross Domestic Product (GDP) on manufactured goods from low-wage, newly industrializing countries. Writers like Kuttner are thus attempting to explain one economic phenomenon, in this case wage stagnation, by means of a factor that leaves 98.8 percent of the economy untouched.
Secretary Reich has pushed a similar line with a somewhat different spin: the U.S., he asserts, must now compete with low-wage countries for access to a limited investment capital pool. But Krugman knocks down this argument as well, noting that in the 1980's, capital was flowing out of the third world, and since 1990 the industrialized world has invested a mere $100 billion in emerging markets out of $18 trillion in Western GDP and $60 trillion in capital stocks. A capital outflow of $100 billion could have depressed wages in the advanced countries by, at worst, 0.15 percent.
Pop internationalists who wail about nonproblems like these have, not surprisingly, developed solutions for the ills they misidentify, usually entailing one or another government program. Though in general open-minded on the subject of government intervention Krugman displays little patience with the particular policies advanced by the targets of his wrath. In particular, he issues a devastating attack on Reich's and Magaziner's call for government investment in "high-value-added" sectors of the economy. For them, "high-value-added" is a synonym for high-tech, but in fact high-tech industries like aerospace and electronics fall below the manufacturing-sector average in returns per worker, which is the true meaning of "high-value-added." The highest value-added sectors of the American economy are petroleum refining and cigarettes, hardly industries which American taxpayers need to fund.
Krugman is slightly more sympathetic to the call by Laura D'Andrea Tyson, chairman of the Council of Economic Advisers, for subsidies to create a comparative advantage in international trade—his own work, after all, has helped create the intellectual underpinnings for such an approach. But he cautions that even the most successful of such programs, including Europe's Airbus, will have only a negligible impact on economic performance. Even if the United States could design a program to increase the size of its high-tech sector by a third, and if that program were to work effectively, GDP would increase by a puny .07 percent before the costs of the program were factored in.
This is a frequent conclusion to Krugman's arguments: when one crunches the numbers for the various disaster scenarios about which the pop internationalists have warned, the actual economic effects turn out to range from minimal to minuscule to nonexistent. As for Krugman's own approach, its cornerstone is that economic productivity "is determined by a complex array of factors, most of them unreachable by any likely government policy." In other words, the beginning of economic wisdom is recognition of the market's complexity and intractability. As Krugman devastatingly shows in Pop Internationalism, this elementary and indispensable truth seems to have gone out of fashion among some of the most visible practitioners of the dismal science.


text:
August 15, 2007
The Big Bad Swim: Lapping it up
Reviewer: James Van Maanen
Rating (out of 5): ****
What constitutes a "sleeper"? I'd always thought a movie required at least a short theatrical release in major cities to qualify for this overused label. After viewing The Big Bad Swim, however, I'd have to say that any film this good--and this unheralded--is a shoo-in for sleeper status. A dramedy about a group of Connecticut adults (of all ages and professions) taking a swim class, this first full-length film from director Ishai Setton and writer Daniel Schechter simply sneaks up and knocks you--sweetly, quietly--off your feet. Granted, Setton and Schechter have not broken any new ground with their movie, yet neither a visual moment nor a line of dialogue rings false, is pushed to excess or wasted. Many longtime filmmakers, even some who've won major awards, don't get this close to perfection when they try to create a batch of interesting, real human beings.
The performances are so good, down the line, that you may find yourself wondering if the actors were improvising. I doubt it. There is such a surety here of commitment and purpose from the filmmakers, as well as an eye for visual and verbal detail, that it won't take viewers long to relax and realize that they are in very good hands. Leads Paget Brewster (Unaccompanied Minors) and Jeff Branson (the TV soap "All My Children") are probably the most recognizable, but everyone is worth an appreciative nod. Together the cast and creators imbued their flawed and very human characters with remarkable warmth and distinction, without getting sentimental or specious in the process (and there's even a foundling puppy in the picture). Certainly, we'll be hearing more from everyone involved, and soon, I hope.
That a film this good--smart, accessible, enjoyable--was passed over for theatrical release (and the accompanying "fuss" that would draw at least a minor audience) shows a stunning lack of judgment on the part of current distributors. The Big Bad Swim has appeared (and won awards in the process) at national festivals from Tribecca to Maui, Seattle to Rhode Island and internationally from Munich to Karlovy Vary, Avignon and Zurich, and managed one-week releases in Allentown, Pennsylvania and Portland, Oregon, with individual screenings in Chicago and Fort Lauderdale, where it was lapped up by critics and audiences alike. For the rest of us, thank God for DVD.
Posted by cphillips at August 15, 2007 12:22 PM
James, I can't believe you didn't comment on how incongruous the cover is with the story and tone of this film!
BOOBS!Posted by: Erin at August 21, 2007 7:09 PM
Exactly. I first rented it online and so did not even see the box art. But, yes, it is ridiculous--and typical. Something I left out of my interview with the filmmakers was that, when I mentioned to them that, on the IMDB, the "key words" for the film were "strippers" and "nudity," they said, "Gee, there IS no nudity in the movie." Ah, yes. We know what sells--whether it's actually there or not. (Since then, I have noticed that the IMDB key words for the film have been changed--or at least been added to.) I would have preferred that the box art show that great line-up of characters that this week's Dispatch offers as its lead photo. But then, I suppose, customers might imagine that the movie was the equivalent of "Spellbound" or "Word Play"--but in a water locale....Posted by: James van Maanen at August 22, 2007 1:37 PM


text:
Cavs start Simon era with 23-6 win
Southern Lee opened its new era under head coach Don Simon with a 23-6 victory at Western Harnett Friday night.
The hurry-up, spread offense was as advertised by the Cavaliers. Junior quarterback Emond Caldwell passed for 151 yards and two touchdowns.
Southern Lee's defense, though, was the dominant unit of the night. The Cavaliers forced six Eagle turnovers and held Western Harnett to five first downs. The only Eagle score was Austin Wright's 95-yard fumble return for a touchdown in the opening quarter.
Southern Lee turned big plays into 10 quick points, adding a bunch of confidence to the opening-night effort.
Cullen Boyette, from an upback position on the Cavalier kick return, took the opening kick into Eagle territory. A flag set the Cavs on the Eagle 36 and after a couple of first downs, the Cavs got on the board with Ethan Helsman kicking a 29-yard field goal.
The first Western Harnett possession ended with Dylan Brown putting a big hit and a fumble on an end around by Brandon Tymes. Lineman Justin McKinnon fell on the ball for the Cavs.
The next snap was another big play. Caldwell bought time in the backfield before lobbing a pass to Damien Brown open over the middle. Brown took it the rest of the way for a 30-yard touchdown and a 10-0 Cavalier lead with 6:28 left in the quarter.
Two stops in the Eagle backfield made for a quick stop and the Cavs moved to the Eagle 6 on their next drive. On a first-and-goal play, the Cavs fumbled a handoff and Wright scooped the ball up on the move and dashed practically the length of the field.
The Cavalier defense held the Eagles to two first downs and 32 yards in the opening half. Another turnover set up the Cavalier offense in position to strike late in the half.
Brown intercepted a deflected pass, giving the Cavs the ball on the Eagle 32. A Caldwell to Aaron Blockman pass and run gained 14 yards, then on third-and-10, the Cavs called a screen pass at the right time. Caldwell tossed to Monte McLean for an 18-yard touchdown with 1:18 left in the half. The Cavs led 16-6 at halftime.
The Eagles had their chances to get back within a possession. The second Eagle drive of the half ended on a fourth down play at the Cavalier 30, with Cavalier lineman Ben Long recovering a fumble after Eagle quarterback Austin Speck was striped as he tried throwing on the run.
Southern Lee drove to the Eagle 1-yard line early in the fourth quarter. Caldwell, and all the Cavaliers, thought he scored on a run up the middle. He had the ball taken away, the Cavs argued after he broke the goal line, but Eagle tackle Nik Dunlap rumbled 80 yards to the Cavalier 19.
The Eagles couldn't capitalize from there. On 3rd-and-8, the Cavs forced and recovered their fourth fumble of the game.
The Cavs tacked on a touchdown late in the fourth quarter. McLean carried in from a yard out. Patrick Bunnell's 23-yard rush on a 4th-and-2 play at the Eagle 31 was the key for the last Cavalier score.
Caldwell was 15-for-34 passing for 151 yards, two touchdowns and an interception. Bunnell carried 12 times for 95 yards. Blockman was Caldwell's favorite target, getting eight receptions for 77 yards. Brown had three catches for 37 yards.
On the defensive side, Dalton Parker had two sacks and two tackles for loss. Jeremiah Jones had two tackles for loss plus an interception, picking off Speck with 1:30 left in the game.
The Cavs held Speck to 7-for-18 passing for 13 yards and two interceptions. Jae'pell Ortiz led the Eagles with 10 carries for 55 yards.
Southern Lee (1-0) hits the road again this coming Friday, going to Northwood. Western Harnett (0-1) will visit county rival Harnett Central Friday night.


text: Today's Community Conversation lecture will be looking at how insects affect our food supply, in both positive and negative ways. Scott Hoffman Black of the Portland-based Xerces Society for Invertebrate Conservation will present a talk on "Insects and Human Food Security," set to start at noon in the Wollenberg Auditorium at the Rose Center for the Arts. Admission is free.


text:
What are the best, worst, and craziest gimmicky makeup products/tools you've tried?
What are the best, worst, and craziest gimmicky makeup products/tools you've tried? Share!
One that I can recall that I did like were the MAC Masterclass Brushes – they weren't perfect, but I really liked the larger Oval brush for certain applications. One of the worst was Benefit's Fine One One. Can't think of one for craziest!
Thanks to Stephanie for today's question! Do you have a question idea? Submit yours here.
Discussion and debate are highly encouraged, and we expect community members to participate respectfully. When asking a question, please check the FAQ section (above) for information about purchasing, price, dupes, and the like. If you have general feedback or need technical support, please contact us.
Comments that include advertisements, self-promotion, insults, etc. may be in violation of our comment policy and subject to deletion. Please see our comment policy for more information.


text:
CHURUBUSCO — The Lady Eagles made quick work of Fremont, closing out the game in just five innings by the 10-run mercy rule Tuesday 11-0.
After taking the first-inning to warm up with only one run, the Churubusco scored nine runs in the second and third innings in the NECC match-up.
To read the rest of this story, please order an e-subscription, found under the e-edition subscription link, or call The Post & Mail at 244-5153, ext. 207 and ask for a subscription.
[1] http://www.thepostandmail.com/sites/default/files/buscosoftball:Lacey Pulley(background) Kelary Crabill.jpg


text:
Tulipia Area Rug
# 14968
Product Description
The Tulipia Area Rug from the Antoinette Collection is a classically-designed wool area rug that speaks to all of your basic design needs. Expertly-crafted from 100% New Zealand wool, this durable accent piece features intricate floral designs against a bold backdrop for a dramatic floor covering that is sure to be the focal point of your room.
Product Details


text: Atlanta-based folk singer Shawn Mullins dropped by the Birchmere and was greeted with a super attentive audience, that didn't make a peep during his 90-minute set. "You guys are being real quiet today," said Mullins. "And I like that, it sure the hell beats the days where I played in bars where fights would break out every other minute." Mullin's music isn't for the rowdy, and the silence from the


text:
Thursday, April 10, 2014
While the snow is disappearing downcountry, the incredible spring conditions just keep rolling at Sugarbush. Yesterday's surprise squall dumped a quick inch or two and refreshed everything with a new coat.
Dr. Johnny Fever practicing some physics on Paradise yesterday.
Not that we needed more, base depths are at mid-winter levels. Even the woods are still filled.
Conditions are so good, you'll flip.
Today's 1st Tracks Snow Report.
Sochi Olympian Nolan Kaspar visited Mt. Ellen.
Last weekend's bonus Mt. Ellen days were tasty, too. We got to watch Nolan Kaspar tear it up on Inverness Sunday morning, then some Reimergasse Park laps, groomer cruisers and off-piste explorations, capped off with a great deck show by the Detonators.
Getting some coaching from one of the world's best!
Thank you to all our passholders! We already miss Mt. Ellen, too.
How about a big cheer for Sugarbush Parks? Check out the new Racer's Edge Park!
Beautiful installation.
Still wintery on the ridgelines.
The off-piste is off the hook.
Air turn.
Heaven's Gate looking very good yesterday.
Professor Egan sharing the forest for the trees.
Mid-winter depths with spring sunshine? Yes, please.
More freshies! Yesterday and today have been amazing.
We've got a quiet event weekend, but the real fun is on the mountain anyway. Saturday looks like one of the sweetest days of the whole spring, with temps near 60 and brilliant sunshine.
Even with the deep snowpack, the end of the season is less than a month away. Time to wring out the best of spring. Better be here!
John Atkinson
Chairman, Sugarbush Stoke Exchange
Staff Photographer/ Snow Reporter/ Coach
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text:
- Focus Areas
- Resource Library
- Videos
- Funding Opportunities
- Events
- Teachers
- Parents
Grants to States to Support Oral Health Workforce Activities
Opportunity Type: Grant
Funder Type: Federal
Funder: Health Resources and Services Administration
This program's purpose is to "help states develop and implement innovative programs to address the dental workforce needs of designated dental health professional shortage areas."
"Applications for this program should describe innovative approaches to addressing and measuring oral health workforce needs," and can include programs developed to expand or establish oral health services such as a school-linked dental facility.
Nine grant awards are expected, with an award ceiling of $500,000. There is a cost sharing or matching requirement.
A National Charter School Resource Center report shows how a California charter school participated in a similar grant to support its community.
CFDA Number: 93.236
Link to More Information: http://www.grants.gov/search/search.do;jsessionid=cLrVQc9dBZSTXrdDxCt6yJX43LlpNq...
Grant Details
Due Date: April 3, 2013
Award Size: Ceiling $500,000


text:
Gear Review
Love it!
Love this jersey! The inside seems to have a light fleece that I really like. When I wear a long sleeve jersey I like it a little warmer. This jersey is it! Quality logos, zipper and the colors are eye catchers.
View More Details on Castelli GPM Full-Zip Long Sleeve Jersey


text:
Defining what the research says
It was the early 70's
More than effective practice
There are other questions that the research can help us to answer. These include, what makes MI efficacious (for example, to what extent does client "change talk" contribute to outcome), what is effective in training practitioners and what does research in other fields tell us about why MI works? The first two questions were the focus of several columns in the MINT Bulletin. You will find links to these in the references11. Those contributions included one on the MI Spirit (2009), two on MI training (2006) and three on "change talk" (2004-5). More recent studies may provide a reason to revisit what the research says about these topics.
Was this first blog of "What the research says about MI" helpful to you?
What questions would you like answered and/or what would you like to read about in the months ahead?
research citations on "resistance"
Thank you for putting this information together for us Grant.
I want to find out where the research is regarding "resistance"
and MI. I understood that Bill Miller had some research findings
in this area. His research and/or the research of others
in this area will be appreciated.
Thank you in advance.
What the research says ...
What a nice compilation. Thanks, Grant, for taking the time to supply one of our first posts!
Debby Westcott aka: Probie15
Thanks Grant for this posting. I look forward to subsequent editions!


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The Annals of the American Academy of Political and Social Science (November 1961); and Daedalus (Winter 1962)
The Youth Field
The Annals of the American Academy of Political and Social Science, November 1961 ("Teen-Age Culture,"
by Jessie Bernard).
Daedalus, Winter 1962 ("Youth: Change and Challenge,"
by Stephen Graubard).
Business is booming in the study of youth. Most of the recent books and articles on youth and adolescence have addressed themselves to such practical problems as juvenile delinquency, the not-quite-delinquent "wild-ness" of teen-agers, the impact (or lack of impact) on students of academic values, and, somewhat more generally, the special tensions attendant upon adolescence as a "transitional stage." But beyond this concern with relatively practical problems, there lies a body of recent work whose preoccupations with youth are intended to tell us as much about adults as about children. I have in mind, for example, Edgar Friedenberg's fine book The Vanishing Adolescent, Paul Goodman's much discussed Growing Up Absurd, Kenneth Keniston's long article last year in The American Scholar, Eric Erikson's work on adolescence and identity, and James Coleman's carefully researched but disappointing The Adolescent Society. The latest additions to this literature are the two present symposia, which contain a total of 22 articles.
The major preoccupation of the contributions to The Annals is a quasi-ethnographic fascination with something called "the teenage culture" or "youth culture," or sometimes "the adolescent subculture." These terms summarize the belief of many that adolescents are a species of exotica, that they move in a hedonistic, irresponsible, and "expressive" milieu, distinctive enough to qualify for the sociological classification "subculture." Adolescents, in any case, seem mysterious enough that their parents require manuals on how to understand them.
The central theme of The Annals, however, is that the rebellious, anti-adult, Dionysian features of "teen-age culture" have been grossly exaggerated. One article, it is true, uses teen-age magazines to document the major preoccupations of teen-agers (sex appeal, Hollywood, TV, records, popularity, and so on) and a second discusses the spread of these motifs to Britain and the Continent. But the substance of most of the other selections suggests that the character of adolescent peer groups should not seriously obstruct young people from eventually becoming responsible adults—which is, after all, what most official worriers about youth are worrying about when they worry. For example, Kirk Dansereau sees adolescent behavior as a prototype of the adult world of the near future, in which life will be organized around leisure, not work. Again, a study of rural youth concludes that these young people are fully as traditional and conservative as their parents. Ira Reiss argues that while the sexual codes of adolescents are more liberal than traditional norms allow, for the most part they are quite in accord with the "permissiveness" that actually governs sexual behavior today. And so on. In her editorial summary of the entire issue, Jessie Bernard concludes: "The volume might well be viewed, therefore, as a picture of adult culture today as reflected in the teen-age culture which it fosters." But adults know that the distorted reflection is temporary (they'll grow out of it), and this knowledge in large measure accounts for the chuckling benignity with which many adults regard the "excesses" of adolescents. Genuine subcultures are never taken so lightly.
But if The Annals succeeds in making its rather bland point that the adolescent society is far from being beyond the pale of respectability, far from worshipping at the feet of Dionysius, this success ought not to deceive us into believing that "youth culture" is merely a myth. Though genuine subcultures of youth involve only minorities of young persons and, indeed, spill over the usual barriers of age-grading, they do flourish. In what is far and away the best and most interesting paper in The Annals' collection, David Matza introduces the idea of "subterranean tradition," which is adhered to by a small part of the population, tolerated by somewhat broader segments of it and, although officially denounced, regarded by the public "with ambivalence in the privacy of contemplation." He argues very persuasively that in the U.S. subterranean traditions of youth take three major forms—radicalism, bohemianism, and delinquency. He maintains that these rebellious traditions do not attract more young adherents than they do because each has a "conventionalized version" which serves to drain the original of its most significant content. Thus radicalism competes with the tradition of "doing good," of social reform and community service; the conventionalized version of delinquency, on the other hand, is "teenage culture"; and certain aspects of fraternity life (though Matza admits that this is the most questionable of his parallels) provide a conventionalized version of bohemianism. If you can't squelch 'em, co-opt 'em, seems to be the great American principle of civil order.
One of the many virtues of Matza's paper is that it enables us to distinguish between the routine, ephemeral, essentially transitional features of adolescence—which can be understood as an attempt by adolescents to cope with the specific temporary pressures our system of age-grading imposes on them—and genuine subterranean (i.e. subcultural) styles—which tend to leave a relatively permanent mark on those who have been extensively involved in them. Exdelinquents, ex-radicals, and ex-bohemians tend to be permanently visible; ex-swooners, ex-hot-rodders, and ex-basketball players do not. I think that an important source of much of the confusion and contradictory noises one hears about youth is the failure to distinguish between youth or adolescence as a chronological age-grade with its distinctly transitional pressures and problems, and youth or "youthfulness" as a configuration of cultural qualities or psychological predispositions, which, although concentrated among the young, are neither exclusive to it nor necessarily temporary. Everybody knows (or says) that some adults are more youthful than others. What they often do not observe is that the tendency to maintain youthfulness in later years is not just randomly distributed. Certain adult milieux are especially receptive to or tolerant of hedonistic, flamboyant, irresponsible, spontaneous, and expressive kinds of behavior; and it is toward these milieux that those youngsters who have been most deeply involved in genuine "youth" cultures tend to gravitate as they get older. Some never "grow out of it," and as adults they contribute to the maintenance of subterranean traditions from which succeeding generations of youth can draw sustenance.
In Daedalus, only Bruno Bettelheim devotes his entire article to "The Problems of Generations," but it troubles virtually all the contributors. While Talcott Parsons sees traditional American values as fundamentally unchanged, and believes that youth shares in the widespread consensus regarding. these values, most of the other authors are deeply concerned about "the search for identity," the conflict of generations, the difficulties of finding anything worth believing in, and the impact of accelerated social change which alienates youth both from the obsolete past and from the enigmatic, unanticipatable future.
A schematic summary of topics like this cannot begin to do justice to the richness and complexity of the Daedalus discussions, which contain some of the very best thinking on youth that I have encountered. Although I do not have space to praise each of the articles individually (and all ten deserve a great deal of praise), I do not think it a quibble to point out that the Daedalus symposium is not, as its title suggests, about "Youth: Change and Challenge." The symposium is about elite youth, or college youth: the kind of people about whom the myth of "generations" is created. We deceive ourselves, though, if we think that our diagnoses of cultural "generations" tell us much about the actual statistical distribution of experience in age groups. "Youth" is not James Dean rebelling with plenty of cause and choking us up with poignance, just as "age" is not snow-white Robert Frost barking his eccentric wisdom to students in search of a Sage. My father was a young man in the 1920's, but he never drank bathtub gin, nor leapt into the fountain at the Plaza, nor Charlestoned to jazz, and was certainly not beautiful and gay and damned. But my bet is that his experience, such as it was, was actually more representative than that of those who captured the myth of the 20's. Culturally speaking, however, it is as if he never lived; history as myth ignores him. Until we free ourselves from this myth of homogeneous generations, we shall continue to be innocently surprised and troubled when surveys of adolescents reveal lots of young people to be quite ordinary reflections of their parental milieux, good, pimplyfaced kids with a host of ordinary problems, who'd be at home in any Y, 4-H club, or Boy Scout troop, and will later be at home in the Methodist church, the Lions Club, and the Republican party.
This, of course, may change as one moves from high school to college and beyond—bohemianism and radicalism are very rare in high schools; they begin to emerge clearly only in college and then by no means equally in every college. But what evidence there is suggests that even most elite youth move rather smoothly through their college years into lifelong commitments to family, community, and career. They do not pay terribly much conscious attention to the search for identity, which, whatever else it is, is not cause for disapprobation by intellectuals. In spite of the clinical concerns of social psychiatrists, "growing up" in our society is perceived not as the gradual development of a firm, stable ego-identity, but as a sobering process of increasing responsibility, deferred gratifications, irreversible roles, and an instrumental approach to the world. And it is this attitude which, from the point of view of a utopian or a Dionysian, renders growing up as "absurd," and which predisposes many of us to see reluctance and lack of enthusiasm among those who opt for "maturity." Thus Bettelheim:
If manhood, if the good life in the good community, is the goal of adolescence, then the goal is clear, and with it the direction and the path. But what if existing manhood is viewed as empty, static, obsolescent? Then becoming a man is death, and manhood marks the death of adolescence, not its fulfillment.
With more emotional power than either Goodman or Keniston, Bettelheim is suggesting in this passage that although puberty provides us with a good objective criterion of the beginning of adolescence, we have no objective mark of its end; "maturity" remains essentially a matter of opinion. Several of the Daedalus writers apparently agree with Dostoevsky that "to live beyond forty is bad taste." Kasper Naegele refers to the Greek wish that youth should not be spoiled by age, and Erik Erikson remarks that the cumulative experience of childhood and adolescence "bequeaths to all methodical pursuits a quality of grandiose delusion." Under these conditions, then, growing up is indeed absurd. But Daedalus chickens out at the end. Having convinced us that "we" have given "them" a rotten world full of bleak prospects to grow up into, Daedalus turns right around and, like the forced, affirmative Hollywood ending in which the logic of dramatic necessity is blithely discarded in favor of "upbeat" requirements, recommends to the young that they carry on, engagé, heads high.
But if the world of youth, as so many of these writers suggest, really is a truer, wholer, more authentic kind of existence, on what basis do we recommend that it be left behind in favor of the mixed blessings of "maturity"? Because there's no choice? Because one "has to" grow up? Well, not really; one doesn't have to. Henry Miller hasn't. Bertie Russell never grew up. Ernest Hemingway didn't. Norman Mailer is probably a superior kid today to what he was in 1948. Kenneth Rexroth isn't grown up. Dylan Thomas died adolescent and so did Charlie Parker. They remain, as the song says, Like Young, and quite unlike those who drink Pepsi. I do not sentimentalize, I do not make heroes of these men, and I do not recommend to anybody their modes of staying young. But it is a fact that these lives are available as models, and plenty of young bohemians and radicals dedicate themselves in this manner to perpetual youth. And who will say that they contribute less to our civilization than the thousands who get up off the couch, bristling with egoidentity, to return, strengthened, to the grim combat of family, community, and career?


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Vastrapur, Rest of Ahmedabad & IN 2 MORE LOCATIONS
7 Reviews / 7 Ratings
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September 05,2012
Hitesh Bajaj, Software Engineer
August 16,2012
Must of Chicken Lovers
Must go for chicken lovers.(In chicken courses they only serve FRIED Chicken)
Cool place to be with friends.
Chicken is what they are for, very soft and fine chicken.
Classy sitting arrangements.
Service good.
If you are vegeterian, dont be sad, they have some veg menu as well.
August 15,2012
the opening of KFC was much awaited for me! for someone who loves non vegetarian food, this is the place! the chicken buckets- total international and delicious taste, a must have over here if you love non vegetarian food. the zinger burgers- so tasty and crispy. like they are tailored the way i love it. and my favourite!! the KRUSHERS! i have tasted all the krushers and i loved them all. though chocolate will remain an all time favourite for me! KFC - you know you wanna go there so just go as you wont regret !
February 27,2012
December 23,2011
Awesome for vegetarians too !!
Well been here every time i visit alphaone mall...
Awesome place to be with friends..
Cool interiors..
Price rates are also affordable..
Service is a bit slow but its ok..
veg. snacker just rs.25 and veg zinger rs. 129 (approx.)
awesome place
awesome ambiance
Tasty food..
will get addicted to kfc..
you come out of restaurant with a smile..
December 14,2011
KFC in Ahmedabad
After what seemed like a long time(!), KFC has finally opened in Ahmedabad (AlphaOne mall, Vastrapur).
It is regularly packed with a non-stop steady stream of customers eager to get their finger lickin' share of fried chicken.
The decor isn't anything fancy but given the fast turnaround of customers it's not a place to go to sit for a while and take a long time over your food. Fast food is the name of the game.
First visit we ordered a chicken 'bucket' which was good - probably the best of the options (also had popcorn chicken and chicken strips).
One let-down was the 'lack' of the usual KFC taste ('regular' flavor) but otherwise it is a place that is hard to beat, including on price which is well worth the money.
Second visit we opted for the 'zinger' meal which strangely(!) came with either fries OR a single piece of chicken - take care when you order as we expected fries but were told it was an 'either-or' deal.
Looking for some additional sides to the meal we also ordered the 'coleslaw'. It is not what you'd expect from a coleslaw by western standards - more like cabbage, onion and carrot (finely sliced) with a thin vinaigrette. Taste is ok but doesn't really compare with a traditional 'slaw.
Definitely worth a visit tho' if you're looking for that non-veg fried chicken 'fix'!
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Florence M. Dauphin
BLACKSTONE- Florence M. Dauphin 98, formerly of Early Village in Blackstone, MA, died Thursday at Philip Hulitar Center. She was the wife of the late Joseph A. Dauphin.
Born in Woonsocket, she was a daughter of the late Jules and Analda (Lefebvre) Tessier.
Florence was a clerk at the former Robert's Children's Shop for twenty eight years before retiring in 1989.
She is survived by a daughter, Lucille M. Salvas of Woonsocket, and four granddaughters, Melissa Souers of Marietta, GA, Tracey Gentile of Juneau, AK, Colette Herrick of Mansfield, MA, and Danielle Cantin of Concord, NH, and two great-granddaughters, Katelynn and Rayna. She was also the mother of the late Raymond J. Dauphin and sister of the late Sr. Marguerite Tessier, Eugenie, Jules and Ernest Tessier.
Her funeral with visitation will be held Monday at 9:00 AM from the Fournier & Fournier Funeral Home, 463 South Main St., Woonsocket, with a Mass of Christian Burial at 10:30 AM in St. Paul's Church, St. Paul's St., Blackstone. Burial will be held in St. Jean Baptiste Cemetery in Bellingham. Please visit
www.fournierandfournier.com [1] for guestbook and directions.
|Dauphin,Florence.jpg [2]
[1] http://www.fournierandfournier.com
[2] http://www.woonsocketcall.com/sites/default/files/Dauphin,Florence.jpg


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5 Successful 2012 Apps For Ideas and Inspiration
Views 732
The count of apps in App Store and Google Play if taken together would lurk around 1.5 million. While both technology biggies never grow tired of boasting about their individual growing numbers, it does takes the app competition to a very high level. To establish a new app in such a choking environment is a challenge in itself, and it certainly helps if one keeps in mind the recent crowned app winners. So, here are the 5 successful apps of 2012 for ideas and inspiration;
The Room
The mystery game ran away with the honors of the 'Best iPad Game of 2012' for plenty of reasons. Graphics, music, levels, and of course the puzzle itself has made iPad users to go in download frenzy. Though the game comes with a price tag, it has entertained a great number of downloads. The noteworthy point here is that there is no dearth of free games on both App Store and Google Play but still a game with a price tag made it to the top. So, if you have a game app idea that can leave the users asking for more, then, kindly go ahead with it.
The organizing app, EverNote features in the 'best apps of 2012' page of Google Play. It helps users keep track of their activities through memos, photos, notes and various other means. It can be downloaded for free and is also New York Times 'Top 10 Must-Have App'. It adds value to the daily lives of its users and helps them stay organized. Its success reflects that people are increasingly looking for technologies that can help them streamline. So, it can be a wise idea to approach an Android application development company with some twist in the same idea.
Goodnight Moon & Grimm's Snow White
Story book apps are flavor of the season, and are greatly looked for by tech savvy parents. Goodnight Moon for Apple devices and Grimm's Snow White for Android devices have been downloaded by parents all over the world to give their toddlers and children interactive bedtime experience. Android and iPad app developers have been exploring new target audience recently, and children along with their parents have held their attention. However, one does have to give a lot of thought to user experience and interactivity to target the little ones. So, jump in with an open mind.
For iPhone users, Letterpress is another game worth taking notice. It is being hailed as the perfect cocktail of fun and strategy. The word game seeks inspiration from Boggle and Othello, and comes with the option of playing against friends through Game Center. The game consolidates the fact that a mobile game can achieve success in strategy too. Letterpress will certainly generate curiosity in the quarters of iPhone and iPad application development.
Rayman Jungle Run is another game that was widely loved. Though these were some app success stories for inspiration, which 2012 app do you think deserve a mention?
About FATbit:
FATbit Technologies is an iPhone app development company India that helps entrepreneurs change app ideas into reality. Besides iPad apps developers, the company also has rich Android development talent too.
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(1) In order to attend the required orientation and to become properly settled before classes begin, you must arrive at Baylor on or before the program start date listed in Item #5 of your SEVIS I-20. Arriving later than this date is not allowed except for some graduate students. (Graduate students who wish to arrive later must have the permission of their department chair to do so, and that department must notify our International Student and Scholar Services staff in writing.) Be aware that attempting to enter the United States later than this date found on the I-20 will probably result in the denial of your entry. If you are not able to report to Baylor by this required date, you should defer your enrollment until the following semester.
(2) Be sure that all information on your I-20 is accurate, including the proper sequence of your first and last names. Any differences in your passport and your I-20 will result in a denial of your visa. Therefore, if you discover errors on your I-20, please report them immediately to our staff firstname.lastname@example.com.
(3) By submitting your Confirmation of Financial Resources (CFR) to Baylor, you are declaring that you have enough money to fund your entire first year of expenses. Failure to do so will cause the cancellation of your class schedule, the invalidation of your visa, and the necessity of your prompt departure from the U.S. Furthermore, you must be prepared to pay for an annual increase in the cost of attendance. Please understand that Baylor has no additional financial assistance available to you.
(4) Attention graduate students: If your family intends to live with you during your graduate program, they may join you only after the successful completion of your first semester. ISSS staff will assist you with their F-2 visa process. Be aware that bringing your family is extremely expensive, and there is no financial assistance available for their expenses. In addition to the routine costs of maintaining a family, all F-2 dependents must be enrolled in Baylor�s mandatory health insurance. Expenses for a spouse and two children can add more than $21,000 to required funding before their I-20s can be issued.
We would be very pleased to have you at Baylor; however, if you cannot meet the requirements above, you should reconsider enrolling at this institution.
We do hope you will find it possible to join us. As you make your decision, email us at firstname.lastname@example.com if you have any questions, particularly about the F-1 visa. We will gladly assist you.
Naymond H. Keathley, Ph.D.
Interim Director


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You might be picked for census survey
By Mary M. Heidbrink, Staff Writer : May 1, 2013 : Updated: May 5, 2013 1:52am
The U.S. Census Bureau is notifying households in Bexar and surrounding counties of its upcoming American Housing Survey, and is asking for cooperation from those chosen to participate.
Residents may be contacted in person or by phone and will be asked questions such as the cost of their housing, what type of cooling and heating appliances they have, and how many rooms are in their home.
Visit www.census.gov/housing/ahs for more information.