text:
A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data.
1. A computer comprising:
a central processing unit;
a bus;
memory for storing texels that are accessed using texture memory addresses; and
a graphics accelerator including:
a processor for generating pixel data, including texture coordinates for a texture to be mapped to a surface for display, for a plurality of pixels during a single clock interval;
a circuit for translating the texture coordinates into a texture memory address of texels corresponding to a pixel and computing a texture cache address of the texels based on a replacement policy for replacing texels in a texture cache;
the texture cache for storing a portion of the texels that are stored in the memory, wherein the portion of the texels are accessed using the texture cache address and are used in generating texture values;
a buffer for storing requests for texels corresponding to pixels for a period sufficient to replace texels not stored in the texture cache, wherein a request for the texels corresponding to a pixel includes the texture cache address, pixel data, and texel flags indicating whether each one of the texels corresponding to the pixel is stored in the texture cache; and
a circuit for generating texture values from texels to map the texture to pixels describing the surface for display.
2. A computer as claimed in
3. A computer as claimed in
texture cache accessing circuitry,
texture cache miss generating circuitry,
memory accessing circuitry responsive to a texture cache miss for writing missing texels to the texture cache.
4. A computer as claimed in
5. A computer as claimed in
6. A computer as claimed in
7. The computer as claimed in
8. The computer as claimed in
9. The computer as claimed in
10. A method for generating texture values comprising the steps of:
storing texels in a memory that is accessed using texture memory addresses;
generating pixel data, including texture coordinates for a texture to be mapped to a surface for display, for a plurality of pixels during a single clock interval;
translating the texture coordinates into a texture memory address of texels corresponding to a pixel and computing a texture cache address of the texels based on a replacement policy for replacing texels in a texture cache;
storing a portion of the texels that are used in generating texture values in the texture cache that is accessed using the texture cache address;
buffering requests for texels corresponding to pixels in a buffer for a period sufficient to replace texels not stored in the texture cache, wherein a request for the texels corresponding to a pixel includes the texture cache address, pixel data, and texel flags indicating whether each one of the texels corresponding to the pixel is stored in the texture cache; and
generating the texture values from texels to map the texture to pixels describing the surface for display.
11. A method as claimed in
12. A method as in
13. The method as claimed in
14. The method as claimed in
15. The method as claimed in
16. A graphics accelerator comprising:
a circuit for generating pixel data including texture coordinates for a texture to be mapped to a surface for display,
a circuit for translating the texture coordinates into a texture memory address used to access a memory storing texels of texels corresponding to a pixel and computing a texture cache address of the texels based on a replacement policy for replacing texels in a texture cache;
the texture cache for storing a portion of the texels that are stored in the memory, wherein the texels are accessed using the texture cache address and are used in generating texture values;
a buffer for storing requests for texels corresponding to pixels for a period sufficient to replace texels not stored in the texture cache, wherein a request for the texels corresponding to a pixel includes the texture cache address, pixel data, and texel flags indicating whether each one of the texels corresponding to the pixel is stored in the texture cache; and
a circuit for generating texture values from texels to map the texture to pixels describing the surface for display.
17. A graphics accelerator as claimed in
cache accessing circuitry,
cache miss generating circuitry,
memory accessing circuitry responsive to a texture cache miss for writing missing texels to the texture cache.
18. A graphics accelerator as claimed in
19. The graphics accelerator as claimed in
20. The graphics accelerator as claimed in
The application is a continuation of, and claims priority benefit of, U.S. patent application Ser. No. 09/273,827, titled "Improved Texture Caching Arrangement for a Computer Graphics Accelerator", filed Mar. 22, 1999, now U.S. Pat. No. 6,919,895 having common inventors and assignee as this application. The subject matter of the related patent application is hereby incorporated by reference.
1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for caching data representing the texture of surfaces to be displayed by a computer.
2. Description of the Related Art
In three dimensional graphics, surfaces are typically rendered by assembling a plurality of polygons into a desired shape. The polygons are conventionally triangles having vertices which are defined in world space by three dimensional distance coordinates, by color values, and by texture coordinates. The color values define the brightness of each of red/green/blue (r, g, b) colors at each vertex and thus the color at each vertex. The texture coordinates (u, v) define the coordinates of each vertex on a texture map defined by values stored in memory. Other characteristics such as transparency, fog, spectral colors, and additional textures may also define each vertex in a particular system to provide more sophisticated rendering.
It has been the practice that an application program executing on a central processor provides to a graphics accelerator the coordinates and attributes of the vertices of each triangle which is to be included in the shape being assembled for display. The surfaces represented by an assembly of polygons are, as a generality, being viewed in perspective.
Typically, the application furnishes the horizontal (x) and vertical (y) distance coordinates as screen values. If instead the application furnishes the distance coordinates as world space values, then these values should, for proper display, be transformed into screen coordinates by a perspective transformation process. Along with the distance coordinates, the application typically furnishes the color values, the texture coordinates, and other attributes of the vertices as world space values. If the x and y screen coordinates of the vertices are known, the pixels defining a triangle on the screen may be determined. Then, the world space depth values (z), the color values, and the texture coordinates may be used to determine the depth value, the color values, and the texture coordinates for each pixel.
In order to provide perspective-correct values for each of the various attributes of a pixel to be displayed, the world space values of these attributes should be transformed into screen values. The vertices of a triangle define a plane in world space so the depth of positions in the triangle vary linearly from one vertex to the other within the triangle in world space. This allows the depth value for each position in the triangle in world space to be determined by a linear interpolation process. If the depth at any position in the triangle can be known, then the depth of each pixel which defines the triangle on the screen may be determined by perspective transformation of the world space depth values.
Similarly, the color values and the texture coordinates for each pixel defining the triangle vary linearly from vertex to vertex in world space; and the same type of linear interpolation process and perspective transformation could be used to find the color values and texture coordinates for each pixel in screen space.
Once the depth value, color values, and texture coordinates for each pixel have been determined, the texture coordinates could be utilized to determine texture values from the related texture map; and these texture values could then be utilized to modify the color values of each pixel in the triangle.
Although, all of this is conceivable, the prior art has not provided hardware to accomplish these processes because of the very large number of steps required and the time necessary to accomplish those steps. Instead, most of the attributes provided by an application program are simply treated as though they are screen coordinates. This provides colors and other attributes which may be somewhat distorted but useable. However, texture patterns are so distorted by such a compromise that they are unusable.
A texture map is a matrix of values which describe a pattern to be applied to the surface of the triangle to vary the colors in accordance with the pattern. Sets of texture coordinates u and v each indicate a particular texture value (texel) in a texture map and allow that texel to be accessed. The texture coordinates of the vertices of a triangular surface area thus define the position of the triangle on the texture map so that the texels within the triangle determine the texture applied to each portion of the surface of the triangle. Each individual screen pixel describing the triangle covers some portion of the texture map as the triangle is projected onto the screen.
Screen texture coordinates obtained by the linear interpolation and perspective projection processes are not typically integral values. On the other hand, indexing into a texture map is accomplished using integral coordinates. Consequently, non-integral coordinates obtained by interpolation and perspective projection must somehow be used to obtain texture values. A simple method of obtaining texture values uses the closest integral u and v values for each pixel to index into the texture map and then selects the texture value at that intersection. A more accurate method of determining a texture value called bilinear interpolation utilizes the integer portion of the u and v coordinates at the center of each pixel to determine four additional sets of integral coordinates defining positions on a texture map surrounding the pixel center. The process selects the texels at these four positions and then uses the fractional portion of the texture coordinates at the pixel center to weight the texture values surrounding the index point. The four weighted texture values are combined into a more accurate representation for modifying the color values of that pixel to reproduce the texture pattern.
Those skilled in the art have recognized that where a pixel covers a very large number of texture values on a texture map, only a small portion of those values will be represented in the final texture value selected to modify the color of that pixel using the methods described. Consequently, a more accurate method of texture mapping has been devised which provides texture maps at a plurality of different scales. A proper scale can be chosen so that the pixels defining the individual triangles may be made to cover numbers of texels in the projection of the texture map in screen space which accurately reproduce the texture value. The process of selecting a texture value for a pixel then includes an initial step for each particular triangle being rendered in which a texture map is selected having a scale adapted to accurately represent texture values for the pixels of that triangle. This selection may include an additional process of selecting scales above and below a desired scale and interpolating between those scales to reach a final scale.
Although these methods provide progressively more accurate texture values for pixels if the triangle lies in a plane parallel to the screen surface, they are all based on the assumption that the projection of a pixel onto the texture map is square or rectangular in shape. This assumption is incorrect in the greater number of cases when three dimensional shapes are being rendered. In fact, none of these methods is capable of describing with sufficient accuracy the texture values which should be attributed to the pixels when three dimensional shapes are rendered in any significant perspective on a flat screen surface.
Because of this, additional processes are being developed which include methods for determining texture values at a greater plurality of points within a pixel all of which points are positioned with regard to both the shape of the pixel and the shape of the texture map. In such methods, texture values are determined at each of these plurality of points (or at four points surrounding each point of this plurality of points) within a projected pixel and the values blended into a single final texture value.
As may be seen, the process of determining texture values for pixels is very complex and requires very large numbers of texels for many triangles. Whatever process is used to determine accurate texture values, it is first necessary to transfer this very large number of texture values from memory to the graphics accelerator circuitry so that these texture values may be utilized in the determination of a final texture value for each pixel in the triangle.
Conventionally, the data defining the texture values for each triangle are individually transferred by the central processing unit to the graphics accelerator via the system input/output bus. This requires that the central processing unit gain access to the system bus through the bus control circuitry, send the data for a first texture value, regain control of the bus to send data regarding a second texture value, and so on. Typically, it takes a great number of bus accesses to send the texture value data for each pixel in a single triangle. As will be appreciated, this is a relatively slow process. To date, the process has been acceptable because graphics accelerators have been too slow to handle the data provided by the central processing unit. However, at least one graphics accelerator has become fast enough to handle more data than the central processing unit is capable of transferring in this manner.
To cut down on bus transit time, many graphics accelerators now utilize very large amounts of local storage on the graphics accelerator and move as many texture maps as possible to that storage. These accelerators then utilize a processor on the graphics accelerator board to access this secondary memory and thereby reduce bus transit time. However, even though these accelerators often provide eight or sixteen megabytes of data storage some part of which may be used for caching textures, this secondary memory must still be accessed in the same manner that main memory is accessed to transfer the texture values to a texture engine where the texture values are manipulated to produce a final texture value for each pixel. Even this local memory access is significantly slower than desirable.
A recent graphics accelerator has overcome this problem by providing a texture cache for texels in addition to local storage for texture maps. The cache may be accessed much more rapidly than either local memory or system memory, and its use therefore significantly accelerates the operation of the graphics pipeline. For example, if cache access requires one interval of time, then access of a texture map in local memory may require thirty-two to sixty-four times that interval; and access of a texture map in local memory may require sixty-four to one hundred twenty-eight times that interval. In one embodiment, such a cache is usually capable of storing all of the texels to be used in defining a texture value for each pixel of a particular graphics primitive and to have those texels available for computation of a texture value as each pixel is rendered. Such a texture cache is described in detail in U.S. patent application Ser. No. 09/056,656, entitled Texture Cache For A Computer Graphics Accelerator, filed Apr. 7, 1998, and assigned to the assignee of the present invention.
One problem that has been encountered in utilizing such a texture cache is that there are times when the texel data is not available in the texture cache. For example, when a new texture is first applied to a triangle, the texels are not yet available in the cache. Similarly, since a cache must have a finite size, often all of the texture data needed for any triangle cannot be stored in the cache. Consequently, if the texture data is not in the cache, then the graphics pipeline must stall until the data is retrieved from local or system memory. The result is that significant delays in the graphics rendering pipeline occur.
It is desirable to provide apparatus and a method for more rapidly providing data defining texture values for use by graphics accelerator circuitry.
This and other desired results of the present invention are realized by a method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, a cache to hold texels for use by the circuitry to generate texture value for any pixel, a stage for buffering the acquisition of texel data, and control circuitry for controlling the acquisition of texture data, storing the texture data in the cache, and furnishing the texture data for blending with pixel data. The use of the buffer stage and control circuitry allows a significant reduction in the need to stall the graphics pipeline.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
The setup circuit 27 accomplishes all of the operations necessary to produce the screen coordinates and color values of all of the pixels describing any surface to be presented on the output display. The setup circuit also provides as output the texture coordinates u, v for each texture which is to be applied to each such pixel defining a surface. The portion of the setup circuit 27 which produces these pixel values and texture coordinates is often referred to as a rasterizer.
The texture coordinates generated by the setup circuit 27 define a primary position for a pixel on a texture map. Any pixel may cover a number of particular texels on a texture map. The texture coordinates determined by the setup circuit 27 define a position on the texture map at which the center of a pixel appears on the screen. Texture coordinates are utilized to derive texture values from the texels for each pixel in the triangles in order to map the texture to the triangle.
The accelerator circuit 15 includes a texture engine 28 which utilizes the texture coordinates provided by the setup circuit 27 for each pixel to produce texture values for that pixel. The texture engine 28 also receives texels from a texture cache 20 designed in accordance with the present invention for holding texels transferred from memory. Texels in memory are accessed and provided to the texture cache 20 utilizing a direct memory access engine 29 designed in accordance with one embodiment of the present invention.
Typically, texture mapping is accomplished by a process called bilinear interpolation. By selecting the integral portion of each texture coordinate and adding one to each integral portion, four distinct sets of integral texture coordinates are generated which bracket the position of the original texture coordinates at the center of a pixel. These bracketing texture coordinates may be used to derive texture values from an appropriately scaled texture map. It will be seen that the bilinear interpolation process typically selects the four closest texels to the pixel center position defined by the original texture coordinates. The values of these texels are weighted using the non-integral portions of the original texture coordinates and blended by a texture engine to produce a final texture value for a pixel. More advanced processes evaluate a plurality of positions defined by a plurality of texture coordinates within a pixel to generate a final texture value for the pixel. This final texture value is then one of the attributes used to modify the color values of the pixel before the pixel data is placed in the frame buffer for use in displaying an image.
In order to accomplish this complex process, a very large number of texture values must be available to the graphics accelerator. In accordance with the present invention, a graphic driver responding to an application program may set up data structures (preferably in local memory 21) which describe a large portion of memory (system or local) in which particular texture maps may be stored. The kernel driver obtains page tables from the operating system and uses these to provide page table entries in each data structure giving the physical addresses of texture map data in memory (system or local). The kernel driver then provides a reference to allow the direct memory access (DMA) engine 29 to access the data structures and find the portion of memory in which the texture maps are stored in response to application commands. The kernel driver may store the page tables in local memory 21 so that the DMA engine 29 may accomplish virtual-to-physical address translations locally.
The DMA engine 29 receives commands from an application program indicating the address of a sequence of texels in memory and uses the data structure information to retrieve the addressed texels to fill the cache 20. In one embodiment of the invention, the texels are stored in cache lines which may be accessed in the cache 20 by the u and v coordinates in a pattern which provides locality in both u and v.
Although not a preferred embodiment, it would also be possible for texture data to be furnished to the cache 20 by the CPU 11 under control of the application program.
The texture values generated by the particular process utilized by the texture engine 28 are utilized along with the other attribute values to determine the color values to be placed in a pixel lighting pipeline 22 with the dimensional coordinates and r, g, b color values. The lighting pipeline 22 blends the r, g, b color values and texture values to produce color values for the textured pixel and transfers these pixel color values to a rendering engine 23 which uses the dimensional coordinates and the values stored in a frame buffer 24 to render the pixel data to the frame buffer for display.
In order to describe the improved cache, an embodiment in which four texels are used in a bilinear interpolation process to derive a texture value for a particular pixel will be described. However, the invention may be used with processes utilizing many more than four texels to define a final texture value for a pixel. In the embodiment described, four texture values (texels) must be available at the graphics accelerator 15 during the setup process in order to determine a texture value for the texture for any pixel. Generally, texture values are stored in memory as a part of an array which is an individual texture map. Consequently, it has been typically necessary to transfer at least four texels over the system bus from memory to the graphics accelerator for each pixel processed during the setup routine. With bus access times and other requirements, storage of texture map portions in different pages of memory, and similar problems, the time required for texel transfers is a significant limiting factor in the speed of graphics displays. Alternatively, texture maps are transferred to local memory and accessed there by the graphics accelerator. Although this eliminates the bus time required for access, it requires a significant amount of local memory and still requires accessing the texels in local memory, a time consuming process.
The use of a texture cache overcomes this problem by significantly reducing the amount of texel data required to be transferred from memory. In order to accomplish this, the present invention utilizes the cache 20 of texel data as a part of the graphics accelerating device 15. The cache 20 stores texels which are transferred to the device 15 for use. Since the generation of pixel texture values typically requires the utilization of four adjacent texels in a texture map to produce a single texture value for each pixel rendered on the output display, many of the texels are used a plurality of times in computing adjacent pixels defining a triangle. Consequently, texel values stored in the cache 20 may be used and reused in generating texture values for the pixels in any triangle. Moreover, the texels which are stored in the cache 20 for generating texture value for one triangle are often the same texels used in generating texture values for an adjacent triangle. Consequently, once transferred to and stored in the cache 20, the texels need not be transferred to the cache again unless the cache replacement policy causes them to be overwritten. This significantly reduces data transfer time over the system bus or a local bus from local memory and speeds the graphics rendering process.
In one embodiment, the cache 20 is directly available to the texture engine 28 and may be accessed using the u and v texture coordinates. Theoretically, it would be possible to provide a cache large enough to hold an entire texture map. However, the size of such a cache would make it costly to implement and would greatly increase the time required for transmission of texture values since an entire texture map of values would have to be transferred for each triangle using a new texture map, no matter how small a part of the texture map was to be used by the triangle.
It is more efficient to provide a cache having a size estimated to be sufficient to store, in most cases, texels defining the texture over an entire triangle. By reducing the size of the cache, the number of texels being transferred for each new triangle is much less than the number required to transfer an entire texture map. Moreover, texels transferred to the cache are reused thereby reducing the total amount of data transferred. Consequently, the time of transfer is significantly reduced. Furthermore, the cost of such a cache is much less than that required to hold entire texture maps.
One difficulty in providing a cache to hold texture values is that in contrast to the typical one dimensional processor cache utilized to store data and instructions recently utilized, a cache for texture values must be accessed in two dimensions in order to provide rapid operation. That is, a texel is accessed in a texture map by using the u and v coordinates to determine a position in the map in the same way that x and y coordinates determine a position on the screen. The integer portions of any texture coordinate pair define a position in the plane of the texture map. It is necessary to access four texels surrounding each of whatever number of positions at which values are determined in order to compute the final texture value for a pixel. Consequently, the positional relationship of the texels to one another should be maintained in the cache in order to provide rapid access to the values. The patent application referred to above describes an embodiment of such an arrangement for providing four texels at a time.
In one embodiment, a cache size is selected which is sufficient to hold the data for two of a large percentage of the typical triangles utilized for rendering a shape to a display. A particular texture cache is organized as sixty-four 128 byte lines.
In the embodiments described in the patent application and with any other cache designed to hold texels from which texture values may be generated for mapping a texture to pixels defining a surface, if texel values are not available in the texture cache when the pixel positions and diffuse color values are generated, then a miss occurs. If a miss occurs, the pipeline must be stalled, and the texels accessed in system or local memory. In prior art embodiments, the access delay which occurs from such a stall is between thirty-two and one hundred twenty-eight times that required to access the texel data in the texture cache.
The present invention reduces significantly the cumulative delay caused by stalling the pipeline when texels required for the operation are not in the cache.
The operation of the translation engine 33 is described by the flow chart of
The buffer 35 is typically a first-in first-out buffer having a number of stages chosen to reduce the need to stall the pipeline in order to access memory for missing texel data. Each stage stores pixel data relevant to the texture blending operation and includes a number of flags which indicate whether the texel data is present in the cache. If two pixels are produced per clock, one embodiment stores data for both pixels in the same buffer stage.
If all of the texel data is not present for any pixel, the translation engine 33 generates cache addresses for the texels which are missing, generates a miss request, and sends the memory and cache addresses of the missing texels to a miss processor 37. The translation engine 33 also places pixel and texel data in the input stage of the buffer 35 along with cache addresses for the texels and sets flags at the buffer stage to indicate the texel data which is present in the cache.
The operation of the miss processor 37 is described by the flow chart of
The pixel values generated by the source of pixel values 27 include pixel coordinates (x, y), texture coordinates (u, v), a texture identification, and a level of detail inter alia. These values are furnished to the translation engine 33. The translation engine provides both memory addresses and cache addresses at which the texels utilized to determine a texture value for a pixel should reside.
In an embodiment utilizing four texels per pixel to determine a texture value, the translation engine 33 provides circuitry which uses the pixel address, the level of detail, and the u v coordinates for a texture to compute four texel addresses and to generate the fractions and weights to be ascribed to each texel. The translation engine converts the u and v texture coordinates to u and v coordinates which are correct for the specific level of detail selected for the texture map through a shift operation. U.S. patent application Ser. No. 09/057,062, entitled Method and Apparatus for Scaling Texture Maps for Graphical Images, Priem et al, filed Apr. 8, 1998, and assigned to the assignee of the present invention discusses processes for determining level of detail. The translation engine provides u and v texture coordinates for the four texels. The integer portions of the u and v coordinates of the four texels are utilized to determine memory addresses of the texels. The manner in which memory addresses are determined depends on the particular organization of memory and is not pertinent to the present invention.
In one embodiment, the texture cache storage itself is organized as four individual RAMs so that four texels may be furnished simultaneously to the texture stage of the accelerator. Data in the texture cache storage is typically replaced one line at a time in accordance with a replacement policy. One such policy is discussed in detail in the above-mentioned patent application. The memory addresses computed by the translation engine are looked up in the cache. If these addresses reside in the cache, the pixel data including the non-integer part of texel addresses are placed in the buffer 35 and the texels are marked as present by setting a flag in the buffer stage for each texel found in the cache. Assuming four texel are to be accessed per pixel, then each of four flags is marked valid. If there is a miss in the cache for any texel, then the translation engine generates a miss request and sends the memory address to the miss processor 37 to access memory for the texels. In addition, the translation stage uses its replacement policy to compute a cache address for the texel data and this is placed in the buffer. The cache address is also sent to the miss processor 37 to indicate the cache position for the memory data which is being accessed.
In one embodiment, the miss processor 37 utilizes a direct memory access circuit (DMA) to obtain the texel data. It should be noted that the texels required for a particular pixel may all reside in positions in memory that are to be placed in different cache lines. This may require that as many as four individual accesses of memory take place to access the texel data. This embodiment of the miss processor queues memory accesses derived from miss requests and issues the individual requests to the DMA circuitry as the DMA circuitry becomes available. The miss processor stores the cache address provided by the translator engine with the miss request. When the data for a miss request is returned, the miss processor 37 causes the data to be written to the appropriate cache address and sets the flag in the appropriate stage of the buffer 35 to indicate the data for the texel is in the cache. As each texel value is returned from memory, it is placed in the cache; and the valid flag bit for that texel is set.
In the embodiment described, a buffer 35 of sixty-four stages is utilized. As the data for each pixel address is placed in the buffer, memory is accessed (if necessary) for that pixel. As new pixel data in the sequence of pixels is generated, it is placed in the buffer 35; and pixel data already in the buffer is moved one stage closer to the cache. If memory access for texels not in the cache requires approximately sixty-four clock intervals, then the pixel data for which the access was initiated should be at the front of the buffer 35 when the texel data arrives from memory and is placed in the cache. Thus, all four texels should be available for use by the texture stage of the graphics pipeline at the same time that the pixel data appears. It should be noted the number of stages of the buffer 35 are selected in a particular embodiment in view of the access time to be expected with the particular circuit embodiment. If most accesses tend to be in local memory, then the buffer may require fewer stages than if most accesses are of system memory.
Those skilled in the art will recognize that by including the buffer and control circuitry for accessing memory to produce texel data essentially as each pixel is ready to be blended with the texture data, the overall speed of graphics pipeline is greatly accelerated over that of prior art texture caches. Rather than continually having to stall the graphics pipeline in order to access memory for cache misses, a single delay typically occurs equivalent to a single access of memory when a particular sea change in the cache occurs.
Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.
Patent Citations
Non-Patent Citations
Referenced by
Original Image


text:
|Appointment Requests for ETSU Students and Alumni are scheduled by calling 423-439-4450.
Resume Walk-in Hours for our Undergraduate Students are on M, W, R from 9 am-3 pm during fall and spring semesters.
ETSU Students and Alumni can search for available job opportunities on College Central Network. Please register and upload your résumé. When ready, select the box to display your résumé to potential employers.
Going Global career and employment resources include more than 10,000 pages of constantly-updated content on topics including job search sources, work permit/visa regulations, resume writing guidelines and examples, employment trends, salary ranges, networking groups, cultural/interviewing advice… and much more. Visit the global forum to chat about living and working abroad!
USA City Guides contain career and employment resources for the 40 largest metropolitan areas in the USA. Included in this database are job search resources, employment outlook, professional networking groups, cost of living, major employer listings by industry sector, non-profits and volunteer opportunities. H1B employer listings are listed for all 50 states!
| Locations | Industries | Sign In
Employer Sponsors

subset: commoncrawl


text:
Food Newtork personality Ellie Kreiger has been named first Mindful by Sodexo Ambassador. First Mindful by Sodexo Ambassador
Send your favorite person a care package, add Cat Cash, or purchase a WildCat Meal Pack online with a new, improved process. Shop Now
Sodexo Earns Top Rank in RobecoSAM "Sustainability Yearbook 2015" RobecoSAM Yearbook 2015
Northwestern Dining ranked in the top 14 dining halls in America. THE 14 BEST COLLEGE DINING HALLS IN AMERICA
Northwestern Dining Ranked #12 for Universities with the Healthiest and Freshest Food Top 25 Universities with the Healthiest and Freshest Food
Northwestern University has pledged to increase it's "Real Food" by year 2020. Tribune Article
Sign up to receive the Northwestern Dining and Northwestern Catering Newsletters.
Newsletter Sign Up


text:
Attwood® Centric II SAS Seat with Seat Lock - down
Item # WX2-189347
- Google+
- Details & Specs
Folding Attwood® Centric II SAS Seats with SAS Shock Absorbing System for amazing comfort!
A smooth ride? You bet. Luxury Centric II SAS Seats from Attwood® feature special SAS technology that absorbs up to 4 G's of shock, so your back doesn't have to. To put that in perspective, the fastest drag racers in the world top out at 4 G's or so... WAY more force than you'll experience on the water. Even in the worst chop at high speeds, you'll still feel like you're sitting on your couch at home! It's THAT comfortable.
Installs easily! The bottom mount is universal to work with any pedestal you may have. Just a few minutes separate you from compact comfort and marine-grade durability! And we've got 'em in a wide range of color choices to match your boat... pick yours and drop us a line today!Details:
- Universal mount on the bottom fits any pedestal.
- SAS Shock Absorbing System suspension absorbs up to 4 G's of impact from waves and hull pounding
- Soft-but-sturdy poly foam fill spells big comfort
- Marine-grade vinyl upholstery stands up to tough sea conditions
- Deep-tuck backrest means you sit IN the seat, not ON the seat.
State Color, as available in the Shopping Cart. Order ONLINE Now!
- Reviews
Attwood Centric II SAS Seat with Seat Lock - down is rated out of 5 by 1.Rated 5 out of 5 by DENNIS from I had the stock seat on my boat prior to this and any chop would kill my back. Shooting pain, etc.. I wasn't expecting this seat to get rid of that alone so I purchased a suspension seat mount as well. I didn't even need to use the mount, this seat works great. It doesn't feel springy, just nice and comfortable, it definitely saved my backDate published: 2013-07-25
<!--BVSEO|dz:Main_Site-en_US|sdk:v220.127.116.11-n|msg:Error: Request errored out - The remote server returned an error: (403) Forbidden. -->
- Articles & Tips
You May Also Like
Guide Gear Low-Back Boat SeatNon-Member $24.99 Buyer's Club $22.49
Guide Gear High-back Fishing Boat SeatNon-Member $39.99 Buyer's Club $35.99
Wise® 8WD10 Boat Seat Base SwivelNon-Member $8.99 Buyer's Club $8.09


text:
WASHINGTON (AP) -- The Agriculture Department says a non-approved strain of genetically engineered wheat has been discovered in an Oregon field.
USDA officials said the wheat is the same strain as a genetically modified wheat that was tested by seed giant Monsanto a decade ago but never approved. Monsanto stopped testing that product in Oregon and several other states in 2005.
There is no genetically engineered wheat approved for U.S. farming, and the discovery is a potential threat to trade with other countries that have concerns about genetically modified foods. The United States exports about half of its wheat product.
The USDA said the genetically engineered wheat is safe to eat, but it is investigating how it ended up in the field. Officials would not comment on how it may have gotten there.
Click Here to access the online Public Inspection File
Viewers with disabilities can get assistance accessing this station's FCC Public Inspection File by contacting the station with the information listed below. Questions or concerns relating to the accessibility of the FCC's online public file system should be directed to the FCC at 888-225-5322, 888-835-5322 (TTY), or firstname.lastname@example.com.


text:
Hearts and Love Birds Valentines Invitation
In honor of St. Valentine's Day, today's offering is a cute hearts theme invitation with adorable love birds and strings of hearts. I always loved the combination of red and turquoise so I borrowed that colors for this design. Happy Heart's Day, everyone! And of course, you can use this as a wedding invitation as well. Sky's the limit with our unique, editable templates!
Size: 7″ x 5″ (wxh)
Fonts: Georgia (texts), Edwardian Script (names)
Change the colors, order matching insert cards and tell us your ideas on how you want to make this design your own.
We offer professional class design customization services for a fraction of the cost of other designers and stores. Consider us your personal graphic designer. We work with you to create the perfect design for the printed materials you envision for your wedding.
Satisfaction guaranteed!
Find more information HERE or contact Michelle directly.
1. Open template in Adobe Reader. If you don't have it installed, download for FREE from Adobe.com.
2. Click on the blue box to activate the editable text area.
3. Click the 'CTRL' then 'E' keys on the keyboard ('Command' then 'E' on Mac).
The "Form Field Text Properties" toolbar will pop up.
4. Change the fonts, text color, alignment with the toolbar - just like doing it in Word.
5. Print on 8.5"x11" paper.
6. Trim and send.


text:
Jacking Off & Smoking in My Car!
Over 175 Exclusive & Hot Pics
of Me Jacking off in the Car!
The Following Site Contains Gay Themed Adult Material
You are not from a country, state, province, or locale in which viewing adult material is in any way illegal.
You have the legal right to possess and view adult material in your community.
You are an adult of at least 18 years of age and do not find adult materials regarding homosexuality to be offensive.
If you use these services in violation of the above agreement, you understand that you may be in violation of local and/or federal laws.
By logging on, you will have released and discharged the providers, owners and creators of this site from any and all liability which might arise.
Only If you agree with all the above may you click the
button below and Enter Our Site!
Kindly Listed with The Following Sites:
Webmasters Add Link
Gay Men Portal
Webmasters Add Link
18 U.S.C. 2257 Record-Keeping Requirements Compliance Statement


text:
Local Campus Colleges
Finding a great college in your area has many advantages. For one thing, local colleges are sometimes better informed about regional industries and career paths. Secondly, many campus colleges offer hybrid degree programs, which can keep you connected without cramping your busy lifestyle - offering some classes online and others... at a local campus. Finally, even if you prefer the convenience of fully online coursework, it's always reassuring to know you can access in-person resources - whether you need support from a math tutor, a financial aid counselor, or a reference librarian. Enter your zip code to start the process of searching for colleges in your area, your city, or your state.
Trillium College strives to create knowledge, to open the minds of students, and to enable students to take best advantage of their educational opportunities. more >
Trillium College's Ottawa Campus strives to provide quality career training to their students to enable them to take best advantage of their educational opportunities. The staff of Trillium College's Ottawa campus is committed to our mission and values, and the application of the highest professional practices and career training standards. more >
With over 20 years in the Private Career College industry, Trillium College has grown to be one of the largest diploma schools in Ontario. Trillium College has helped thousands of people advance their careers and establish new ones. In order to get ahead and stay ahead, you need the right kind of preparation. You need career-focused education that teaches you the skills that employers demand. You need hands-on, practical experience and you need the right kind of career placement assistance, to get started. Trillium College offers a wide range of career-oriented programs related to exciting industries, such as healthcare, social sciences, business and technology. Our courses are taught by knowledgeable instructors who have many years of experience in their field. Our small classes are taught in modules, so you can focus on one topic at a time. Most of our diploma programs can be completed in less than a year, and all our diploma programs are approved as vocational programs under the Private Career Colleges Act, 2005. more >
Style your own future at The Hair Design Schools, where you'll study the fundamentals of beauty and get hands-on experience in our on-site student salon. You'll have the opportunity to learn the latest hair and styling techniques developed just for Hair Design Schools. Our schools are conveniently located in Tennessee, North Carolina, and New Jersey. more >
As an online student at South University, you have access to the many benefits of South University - including excellence in education and personalized attention - while enjoying the convenience of earning your bachelor's degree entirely online. Accreditation and Licensing See suprograms.info for program duration, tuition, fees, and other costs, median debt, federal salary data, alumni success, and other important info. more >
Massachusetts school of law ("MSLAW") is dedicated to providing a high quality, practical and affordable legal education. Our focus is on teaching students the skills they need to be immediately successful in practicing law whether one chooses to join an established law firm, a public office or start his or her own law firm, advance in business, or carve our new career paths within their current profession. MSLAW offers a flexible schedule to accommodate working professionals who continue in their career path as they obtain their law degree. more >
Wichita Technical Institute (WTI) has been offering hands-on training designed to assist students with new careers since 1954. With 5 campuses in 3 Midwestern states – in Kansas, Missouri, and Oklahoma – WTI offers top-notch instructors, the latest technology, and up-to-date curriculums. WTI helps to produce graduates who may be well-equipped to serve the market's evolving needs, and rounds out its commitment to graduates with job placement assistance and career development resources. more >
Congratulations! Your interest in TTY Career College is an important first step toward changing your life. A certification-focused program is the key to a new career with a potentially higher income, better benefits, and more satisfaction. We want to help you get certified! Consider: Start Fast, Finish Fast: You can earn a diploma or certificate preparing you for certification in 1 to 5 months. Certification Pass Pledge: We support our graduates with additional test vouchers, re-takes and private tutoring to get you certified. Tuition Assistance: Financial aid, corporate tuition reimbursement and grants are available to those who qualify. No additional Fees, No Hassles: No parking fees, no long lines, no lab fees, no cost for books, no waiting for class availability. Employment Assistance: We'll help you find your new job when you graduate.** Career-focused Curriculum: You'll receive practical instruction for work-related knowledge preparing you for industry recognized certifications. Convenience: Day and evening classes are available to fit your schedule. Programs Approved for Veterans: Take full advantage of your military benefits to earn your diploma or certificate and get certified. Accredited Institution: TTY Career College is an Accredited Member of the Accrediting Commission of Career Schools and Colleges (ACCSC). Small class sizes with Hands-on, Instructor –led training taught by Certified Faculty. You can get started toward a high-demand career in information technology, project management or Microsoft Office right now. Complete the form and see how you can qualify for financial aid (not based on grades or exams!) We invest in you! TTY Career College is an accredited member, ACCSC. ** Job placement is not guaranteed. more >
EBI was founded in 1858 as Elmira Business and Shorthand College. This school, a leader in postsecondary education, was located just blocks from EBI's current location at Langdon Plaza in Elmira, New York. EBI is now in a new building, equipped with state-of-the-art facilities and cutting-edge lab equipment. And in 2003, EBI opened its second location in the Binghamton area and is currently Binghamton's only career college. You can complete a certificate program in as little as eight months, and earn a degree in just over a year. For required program disclosure information, please go to elmiraconsumerinfo.com. more >
University of the Rockies provides high-quality, accessible learning opportunities globally for diverse groups of individuals seeking preparation for life goals, professional practice, service, and distinguished leadership. Certain degree programs may not be available in all states. Federal regulations require institutions to report certain information about students who enrolled in Title IV eligible educational programs that lead to gainful employment in a recognized occupation (GE programs). For program disclosure information, click here. more >
Since 1987, the Institute of Business & Medical Careers (IBMC) has been helping students jumpstart their careers. At IBMC, students could earn a degree, diploma, or certificate, depending on their chosen field. Programs offered at IBMC include: Business and Technology, Cosmetology, Dental, Healthcare, Legal, and Massage. In addition, IBMC provides students and graduates with employment assistance to help them explore career possibilities. more >
Looking for a career where you could enjoy the personal rewards of helping people look and feel their best? Empire Beauty Schools may help you prepare for that opportunity at one of over 100 beauty schools in 21 states. Our hands-on educational approach to learning the latest trends and fundamentals in Cosmetology is one of the reasons we are widely recognized across the country as one of the leaders in cosmetology education. (Please provide substantiation) more >
Pinnacle Career Institute has been providing people with education and training since 1953. Our programs could lead graduates to successful careers in their fields of interest. Pinnacle Career Institute offers education both accredited online career education programs, as well as campus locations in Kansas & Missouri. If you want an online technical school where you can learn without putting your life on hold, then PCI Online could be a great choice for your education. more >
Fortis College is a small private college providing in-demand career training for those seeking entry-level positions in a variety of professions. more >
Integrating theory, professional practice, and innovation, The Chicago School of Professional Psychology provides an excellent education for careers in psychology and related behavioral and health sciences. Please click here for disclosure information. more >
Florida Career College (FCC) is for individuals who seek to achieve more with their lives through education and training. No matter what stage of life you find yourself in, it is never too late to set new goals for yourself. more >
FORTIS, with 40 campuses in 15 states, offers career education and training to students pursuing careers in healthcare, business, information technology, the skilled trades, massage and cosmetology. Regardless of educational background, qualified students are prepared to succeed at FORTIS! Programs vary by campus, and students may find the one that best meets their educational and career needs in fifteen states: Alabama, Arizona, Florida, Georgia, Indiana, Louisiana, Maryland, New Jersey, Ohio, Pennsylvania, South Carolina, Tennessee, Texas, Utah and Virginia. more >


text:
Click Here to Watch the Whole Video in HD at Blake Mason
Award winning site BLAKEMASON features the hottest amateur British guys. Join today to experience it with them in HD.
Check out this fit and handsome fella - Brent is quite the guy what with his rugged good looks and toned, slender body. His personality perfectly matches his manly straight-guy image and then, as you peel off more and more clothes you can't help but fall more and more in lust with this guy! He has deep golden skin, bright blue eyes, a perfect body and a lovely fat uncut dick too... which he loves to play and tease with more than just wank ;-)...r
Now, when Brent first applied to model he said he was straight, then on arrival we managed to get him to admit to being a bit curious! But I'm still not too sure which way this guy leans or might lean... and I reckon if we got the right man in the same room as Brent then we could soon be seeing this 'straight' fella switching teams! Not that I mind either way of course - he's damn fine eye candy whatever!r
Anyway, back to his jerk off... Brent starts stood with his underwear still on but he quickly pulls his boxers off
Pixels: 320X240 | Bitrate: 350K
Pixels: 640X480 | Bitrate: 700K
Very hot looking guy with a nice body.


text:
warning!!: I am not responsible for faulty wiring or any injuries, this should be done by a professional electrician.
1 . extension cable
2. wire cutters
3. female plug
4. male plug
5. knife
6. screwdriver
Step 1: Wire cutting and striping
2. remove the paper insulation and the extra wire( i know i used black instead of red)
3. removed the individual wire insulation
Step 2: Attache male plug
2. open the plug by unscrewing the screws
3. insert the wires into the ground, positive and neutral ( the plug should have a little diagram or arrows)
4. Tighten all screws firmly
5. close the plug and close firmly the plug with the two screws
Step 3: Cut to approximative length and attach female plug
2. repeat steps 2 but don't forget to put the cap before attaching plug
3. tighten screws with wire inside
4. close the plug and tighten screw ( theres a notch on the cover and a ridge on the plug so the screw holes line up)


text:
The Technology Committee at Minnesota's North Branch Area Public Schools has been named the 2012 TIES Technology Leadership Team award winner. The committee was chosen for the prestigious award for its leadership in bringing technology to the classroom, efforts in building community around technology in the classroom within the school district and the community, and the wide variety of technologies and practices it encourages in the school district.
Read more
Vin Riera, CEO of Bloomington-based education-software firm Plato Learning will announce Thursday that the company is changing its name to "Edmentum" to reflect its growing "online-learning solutions" focused on 21st-century classrooms.
Super Duper Publications has added three educational Fun Deck mobile apps for Apple devices — Listening for Absurdities, What Does Miss Bee See, and What Doesn't Belong — to its growing number of titles available in the iTunes App Store.
Learning a new language is tedious and demands a lot of practice. Luis von Ahn doesn't want all that effort to be wasted. In fact, it might be a gold mine. Von Ahn, a computer science professor at Carnegie Mellon University, is the co-creator of Duolingo, a free language-learning site that turns students into an online workforce. His software uses their answers to simple exercises in a translation service that he expects to charge money for.
Brush of Truth, a book app for kids 8-12, was rated five stars by review site Technology in Education for engaging young readers. Created by Story Bayou, the $1.99 app will go on sale for 99 cents on Dec. 7 on iTunes for iPad, iPhone and iPod touch. Brush of Truth, recognized for its appeal to reluctant readers, also is available on Google Play for Android devices, and for Kindle Fire and Windows 7 devices.
iPads ready and headphones in place, Elizabeth Docken's fifth-grade class is in position for the hunt.
Without more funding for technology, Muhlenberg School District probably won't be able keep its computer systems up to date, administrators told school board members Wednesday.
Privacy Policy | Copyright © 2015
Professional Media Group. All Rights Reserved.
35 Nutmeg Drive, Suite 205
Trumbull, CT, 06611