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Friday, January 18, 2013
Cane Bay's basketball teams both fell to 0-2 in Region 7-AAAA play on Friday night, getting swept by Wando in Mount Pleasant.
After the Lady Cobras dropped one 40-33, the Cane Bay boys lost 62-45.
The girls dropped to 6-8 while the boys fell to 4-9. In the first region games earlier in the week, Cane Bay was swept by West Ashley.
Cane Bay was set to travel to First Baptist for a non-region game after press time on Tuesday before hosting Goose Creek on Friday in region contests and traveling to Stratford on Jan. 22.
In the girls game on Friday, freshman Shameque Robinson and junior Makayla Dudley scored eight points each to pace the Lady Cobras. Senior Brookelynn Doctor chipped in seven points while junior Adriana Barkley scored four points.
Doctor was the top rebounder with nine boards followed by Robinson with six and senior Kabreea Howell with four. Dudley had five steals and three assists.
In the boys game, Raekwon Rivers led the Cobras with 19 points while Jiquan Hammond added 17 points.
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Immediate Goals:
1. Enhance Scheduling Efforts
2. Enhance Development Efforts
3. Expand Number of NET Teams
Mid-Range Goals:
1. Open an Eastern Regional Office
2. Open a Western Regional Office
3. Increase NET's Strategic Reserves by 50%
4. Increase NET's Focus on Planned Giving
Creative Gift Ideas that Go a Long Way
There are a number of ways you can include NET Ministries in your estate plans. Some can be utilized immediately, providing financial assistance to NET today, others establish deferred gifts and will bear fruit at a later date.
Gifts of Cash or Securities
A gift of Cash or Securities can be made in any amount, either immediately, or as a deferred gift by naming NET as its recipient in your will. When donating appreciated stock or mutual funds, held for more than a year, there is the possibility of eliminating federal capital gains tax. These funds resulting from these gifts are carefully managed and invested so they will continue to grow. Each year only a small percentage of the earnings are disbursed to support the NET teams. The rest is reinvested, increasing the principle in NET's long-term reserves and guaranteeing a funding source for many generations of NET team members.
Gifts of Real Estate and other kinds of Property
NET is also able to receive gifts of property (buildings, land, art, jewelry, etc). In the case of a primary or vacation home, you can even continue to use it for the rest of your life and dedicate it to NET Ministries in your estate plan. Gifts of this kind are sold at their fair market value with the proceeds then added to the principle of NET's long-term reserves. Gifts of this type are considered on a case-by-case basis.
Proceeds from a Life Insurance Policy
Proceeds from universal or whole life insurance policies may be given by paying the premium for the policy and irrevocably assigning NET Ministries as the beneficiary and owner.By donating your insurance policy you may take an income tax deduction equal to its current cash value.
Pension/Retirement Fund Assets
All or a portion of the value of your IRA, 401(k), 403(b), Keogh, or the remainder in your pension account may be given by assigning NET Ministries as a full or partial beneficiary. Gifts from IRA's are particularly popular, for unlike your descendants, NET Ministries, as a non-profit organization, is not required to pay tax on the proceeds.
A Charitable Gift Annuity
A charitable gift annuity provides you with regular payments for the rest of your life. Upon your death, the balance of your annuity then becomes a charitable gift to the NET Ministries fund at the Catholic Community Foundation. A minimum gift a $10,000 is required to establish a Charitable gift annuity.
Charitable Remainder Trust (CRT)
Charitable remainder trusts offer a way to contribute to a designated charity while providing an immediate income tax deduction and annual income for you and an optional second beneficiary. You can establish a CRT by gifting assets (cash, stocks, bonds, property, etc.) worth at least $100,000 to NET's fund at the Catholic Community Foundation. The Foundation then sells the assets tax-free, invests the proceeds, and serves as trustee, providing you with guaranteed payments for the rest of your life (or if you prefer, a set term for up to 20 years). Payments to you are received quarterly or annually and are generally 5-6% of the trust's value. Upon the death of the beneficiaries, the remainder in the trust is added to the endowment for NET Ministries.
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A Charitable Lead Trust (CLT) is an instrument for donors who anticipate high estate and gift taxes in transferring their wealth to heirs. CLT's are irrevocable, taxable, split interest trusts. The donor funds a trust with assets such as cash or stocks that will pay an annual income stream to a charity(s) of their choice for a specified term. The assets of the trust are invested and managed by a trustee. At the end of the trust term, remaining trust assets revert to the donor, or are transferred to one or more non-charitable beneficiaries designated by the donor. Because the appreciation in value of the CLT assets is not subject to estate and gift tax, the CLT is an attractive gift vehicle for appreciating assets.


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Pot au feu with rabbit and baconMobile version Email a friend Print
By: From: Market Kitchen
On TV Tonight
- 20:00 - Rachel Khoo's Kitchen Notebook: Cosmopolitan Cook - Istanbul
- 20:30 - Rachel Khoo's Kitchen Notebook: Cosmopolitan Cook - Amalfi Coast
- 21:00 - MasterChef: The Final Three - MasterChef
- Prep time:
- 35 min
- Cook time:
- 1 hr 40 min
- Serves:
- 4
Winter vegetables, cabbage balls and spinach dumplings make this a hearty one-pot meal from Paul Merrett
Method1. For the stew: put the stock, whole carrot, garlic and the herb sprigs in a large pan and bring to a simmer.
2. Brown the rabbit legs in a little butter and add to the stock pot. Simmer for an hour and a half.
3. Meanwhile, remove the 6 outer leaves of the cabbage and blanch in boiling water for 30 seconds. Drain and refresh in a bowl of iced water. Cut out the central veins then roll the leaves briefly with a rolling pin to make them more pliable.
4. Shred the centre of the cabbage very finely, discarding the tough core. Gently fry in a knob of butter until softened. Add a few thyme leaves and season. Leave to cool. Wrap the softened cabbage in the blanched leaves to make 4 balls. Wrap these tightly in cling film and pierce a couple of times with a sharp knife.
5. When the rabbit is nearly ready, add the chopped carrots, leeks, parsnips and cabbage balls. Simmer for a further 10 minutes, or until the vegetables are tender.
6. For the dumplings: blanch the spinach in boiling water for 30 seconds, drain and refresh in a bowl of iced water. Squeeze dry and chop. Leave to one side.
7. Set a heatproof bowl over a pan of simmering water. Put the ricotta and egg yolk in the bowl and beat together as it heats up. Add the parmesan, mix well and remove from the heat. Stir in the flour and finally fold in the spinach. Season with salt and black pepper.
8. Pat flour onto the palms of your hand and roll the mixture into 10-12 small balls. Add to the stew for the last 3 minutes of cooking time.
9. To serve, spoon 1 rabbit leg, 1 cabbage ball (remove the cling film), a selection of the vegetables and 2-3 dumplings into each bowl. Garnish with a whole grilled rasher of bacon.
For the stew
- 1.7 litres chicken stock
- 3 carrots, 1 whole, 2 peeled and chopped
- 1/2 heads garlic
- sprigs thyme, plus a few picked leaves
- sprigs rosemary
- 4 rabbit legs
- butter, for frying
- 1 Savoy cabbage
- 1 leek, sliced
- 1 parsnip, peeled and chopped
- 4 rashers dry-cured streaky bacon, grilled until crisp
For the Dumplings
- 500 g spinach
- 250 g ricotta cheese
- 1 egg yolk
- 2 tbsp grated parmesan
- 125 g 00 flour, plus more for dusting


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Please take no further action on my device. Tech support in Egypt have FINALLY sorted the problem.
Thanks though...
the main issue I have apart from this bloody thing not working is complete lack of information and updates from Vodafone, either through the eForum, e-mail or by telephone. This is the most frustrating part. If I were kept in the loop over what you are doing to resolve my issues, I would be slightly happier but I get absolutely nothing for 5-7 days at a time and a reply only when I yell!
As for not being able to re-synch my Sure Signal, this is because I was sent a replacement device a few weeks ago. This is known to Vodafone and I've even supplied the serial number of the replacement device to assist with getting to the bottom of the issue. I de-registered the old device as your system would not allow me to have two devices registered at the same post code.
I have now de-registered the new device and will re-register the original device today as there is no point in continuing with the replacement as it doesn't work either.
Can I just reitterate again that this did work and flawlessly until December 13th last year when it went offline and since that time, I'vemanaged to get it working for a few days here and there by having the device re-synched or by resetting it.
Nothing has changed with either my ISP or my router settings.
Hi kilimax,
Simon was aware of the newest Serial Number, but apologies for any crossed wires.
I've have checked with James for any updates on this issue from when he raised this and we have had no new information at this time, so this has been chased for you.
As you mentioned on the last page, the fact you have the same issue on two boxes would seem to point more towards the connection than the boxes themselves, so I'm still unsure that there hasn't been a change of some kind by the ISP or a router update of some kind. Do you have an alternate connection, such as a friend's, that the Sure Signal can be tested at?
Whatever the cause, I'm confident that the source will be identified.
I'm part of the Vodafone Tech Team and here to help. As this is a public forum, we can only answer non account specific queries. Please note, we're unable to reply to private messages.
If you see a helpful post, please click the 'Thanks' button to let the author know. If a post solves your query, please click the 'This is the Answer?' button. This helps others find helpful answers in the community too.
Hey kilimax,
This thread has a number of customers seeing similar symptoms and our 3rd line technical teams have been receiving calls regarding this.
Could you head over to the thread and let me know your ISP please?
Thanks Lee. I'll head over to there right now and post some info.
Okay. I have just moved my business to Vodafone on the basis of VSS. We have one in the office which seems to work very well, and I need one at home as the signal is not brilliant. One of my employees also had one at his home - he had no signal at all and is delighted with the reception he now gets.
So so far so good until I then tried to install one at home where the network signal can be a little up and down. I registered my VSS 48 hrs ago and since then I have a steady red light but the other two are just flashing which I assume means they cannot get an internet connection. Over the weekend I have done everything to get my VSS to work with my BT Home Hub 2.0. I have followed every bit of advice on this site and the BT site (not that I can guarantee that I have done everything correctly) but I have repeated everything at least twice. I have spent an age trying to sort out something that I thought would be so simple.
I have just about given up on this unless anybody can please advise what to do, simple advice how to do it and if anything is really going to work. I have followed all the advice on portforward.com but it all seems a bit flaky to me and when I ran there port checker test it would appear that the reevant ports, 8, 50, 123, 500, 4500, etc etc are not open but I have no idea how to get them open. Given that I have a VSS working fine in my office and one at an employees home then I guess that unless this is a faulty VSS (which I doubt), the fault lies with the BT hub. But I have no idea how to fix it.
For information my VSS no, is 40120226077.
Hi pcumberlidge,
Many thanks for your post here.
When you have a solid power light and flashing system and phone light, it will usually indicate that the Sure Signal is downloading a new profile from the server.
Can I ask if this has changed at all?
The reason that I ask is that I can see that the Sure Signal connected to our server this morning and now seems to be connecting fine.
If you are still having trouble please can you let me know the results of the following;
Traceroute (instructions below)
Once I have this information I will be able to help you further if required.
VSS Traceroute command
On a PC :
Click on Start and select Run
Type CMD into the Run box and press enter/click ok
A black box will appear.
In this box type tracert 184.108.40.206 press Enter
Paste the output of this command into your reply.
I'm part of the Vodafone Tech Team and here to help. As this is a public forum, we can only answer non account specific queries. Please note, we're unable to reply to private messages.
If you see a helpful post, please click the 'Thanks' button to let the author know. If a post solves your query, please click the 'This is the Answer?' button. This helps others find helpful answers in the community too.
Hi James,
Thanks for your help. No change in the lights status which have been the same since last Friday despite several resets.
Speed test - 2.9MB/s download; 0.25MB/upload
Ping test - 65ms (on speedtest.net); 97ms (on pingtest.net) 47 ms jitter - then did it again and it was 193ms and 148ms!?
VSS Trace Route command:
'220.127.116.11' is not a recognised as an internal or external command, operable program or batch file.
Hope this helps.
Hi pcumberlidge,
Thanks for getting back to me with your speed test results.
I have taken a look at the results and can see that the issue is with your Broadband speed.
The Sure signal requires a minimum of 1MB/ps Download and 0.3 MB/ps Upload to work.
As you can see the speeds aren't fully within the parameters of the Sure signal which is why it can' connect to the server to establish a stable VPN connection.
You will need to speak with your Broadband provider to see if there is anything that they can do regarding the speed in your area.
I'm part of the Vodafone Tech Team and here to help. As this is a public forum, we can only answer non account specific queries. Please note, we're unable to reply to private messages.
If you see a helpful post, please click the 'Thanks' button to let the author know. If a post solves your query, please click the 'This is the Answer?' button. This helps others find helpful answers in the community too.
I am surprised about this as we have a VSS working fine in the office where the upload speed is generally just over 0.3MB/s but it still works fine with anything from 0.2 upwards. Below this there can be a problem and obviosuly much lower than 0.1 and it is definitely an issue (I have been keeping a close watch on speed vs call quality). Also the speed does vary at home so there are times when it is over 0.3MB/s (depending on time of day, day of week etc) so I would suspect that there is times when the speed is sufficient, but unlike the one I have in the office the one at home has NEVER appeared to have configured and established a connection. I would have thought that it would be the same as the office i.e. it would have established a connection at some point but call quality would be poor/not work below a certain level. Are you saying that unless you can get a consistent upload >0.3 it will never configure? This does not appear consistent with the one I set up in the office where the speed is often below 0.3MB/s.
Secondly most of the options reported with the BT Home Hub has been in terms of ports being opened. Given that it has never configured may this still be an issue. As such I'm not fully convinced that the broadband speed is the sole route of the problem but I will run a few speed tests over the next day or two to see how this goes and build up a picture and will let you know.
Any further thoughts on this?
Just a point to make to Vodafone, the Vodafone website says "just connect Sure Signal to a fixed-line home or office broadband with a minimum speed of 1MB". It doesn't say upload or download but I assume from your email it means download. I cannot find anywhere on the sales area of the website where it says a minimum upload of 0.3MB. I only heard this from others. There needs to be more clarity about this. Anyway as said I will run some speedtests
04-04-2012 02:30 PM - edited 04-04-2012 02:37 PM
Specs first.
Orange Broadband (5.5meg down, 0.7mb up)
Netgear DGN1000 Router
Originally ran a Suresignal 1 with the same problem but this week bought a SureSignal 2 hoping it would fix it
Serial number: 40120248428
As per the title topic, only getting red light with no other lights on box (same thing - or eqivlent, with Sure Signal 1 which we figured was broken)
The original SureSignal worked fine for a couple of years on our diabolical o2 connection which wasn't ADSL2+ and had so much packet loss i was impossible to stream anything. We upgraded to Orange LLC about a 6-7 months ago for twice as fast up and down speed and importantly a solid stable connection without packet loss.
Now Im assuming my issues are occuring because of Orange broadband and/or the Orange Netgear router.
The Suresignal is only one of two devices connected to the router. Ive troubleshooted every problem in the intro. It just refuses to connected.
Ive tried deactivating and reactivating on the account yesterday, factory reset the suresignal 2 again and left it 24 hours nothing.
unPNP is working on my router, but I forwarded ports correctly for the suresignal anyway, im sure it worked when we first transfered to Orange for a while so I have no idea whats changed. Ive even tried putting the SureSignal as the DMZ device so nothing can block it totally rulling out anything the router/firewall could do and still it wont connect.
Im totally out of ideas, there cannot be a problem our end and its unlikely there is something wrong with the suresignal box, there must be an issue with you allowing my IP to connect ot the servers or something similar. I found a thread about Orange IPs but noticed near the end you had added my IP range to the white list and this fixed it for everyone in the thread, but not for me.
Theres obviously something seriously wrong here but im hoping we can get to the bottom of it and we can start using this device aagain as we dont even get a basic phone signal at home.
Just wanted to add these details to save time too.
Png 36ms
Down: 5.5mb
Up: 0.61mb
(packet loss tests refuse to run on this site for some reason...perhaps that is a traceroute issue too? I can tell you there is no packetloss on the connection through via other tests ive run in the past and via the work I do)
Ping: 59ms
Jitter: 9ms
B* Result.
Traceroute results.
traceroute to 184.108.40.206 (220.127.116.11), 64 hops max, 52 byte packets
1 192.168.1.1 (192.168.1.1) 4.325 ms 2.786 ms 2.804 ms
2 192.168.0.1 (192.168.0.1) 3.379 ms 2.576 ms 2.149 ms
3 184.108.40.206 (220.127.116.11) 38.255 ms 41.562 ms 37.984 ms
4 184.108.40.206 (22.214.171.124) 59.133 ms 26.865 ms 19.081 ms
5 18.104.22.168 (188.8.131.52) 27.197 ms 25.724 ms 43.341 ms
6 220.127.116.11 (22.214.171.124) 27.229 ms 27.717 ms 26.560 ms
7 220.127.116.11 (22.214.171.124) 25.280 ms 27.371 ms 25.649 ms
8 188.8.131.52 (220.127.116.11) 26.569 ms 26.282 ms 26.947 ms
9 ae1-0.lontr2.london.opentransit.net (220.127.116.11) 26.381 ms 27.160 ms 27.000 ms
10 tengige0-13-1-0.lontr1.london.opentransit.net (184.108.40.206) 29.709 ms 28.181 ms
tengige0-15-0-1.lontr1.london.opentransit.net (184.108.40.206) 35.005 ms
11 level3-1.gw.opentransit.net (188.8.131.52) 26.816 ms 26.747 ms 41.798 ms
12 * ae-1-51.edge4.london1.level3.net (126.96.36.199) 36.887 ms *
13 220.127.116.11 (22.214.171.124) 39.339 ms 34.561 ms 31.656 ms
14 220.127.116.11 (220.127.116.11) 45.678 ms 46.204 ms 45.391 ms
15 * * *
NOTE: These tests are run form my Macbook Air on the wifi network - so should be slightly better with lower ping for the SureSignal hardwired drectly to the modem/router.
Hi realdannys and welcome to the eForum
I'm sorry to hear that you're still having trouble with this.
I certainly sounds as though it's theOrangeconnection that's causing this. You've been through pretty much everything in our troubleshooting guide and set it up as instructed. There isn't really much more you can do other than contact your ISP and see if there is anything that they can suggest.
Has your router assigned the Sure Signal an IP address ok?
Just for arguments sake, could you try the Sure Signal on another connection to rule out the device as the cause of the problem?
Wayne, thanks for getting back to me.
Im ruling ou the device simply because we have a SureSignal 1 as well which has exactly the same problem. The chances of both devices being defective (especially when one worked for over a year) is unlikely.
Further more it seems insane that our now vastly improved connection is not working with the device when the terrible one through o2 did.
Really though its not Orange Broadbands responsibility to change anything, its your responsibility to make sure your device universally works on internet networks. It did originally work with Orange when we first got it, if they change something on their network then the SureSignal needs a fireware upgrade to fix this.
I cannot understand how a box cannot just make a simple connection with the network when it has internet access the same way every other device I have in my house, its not the broadband providers fault its the (and judging by these forums) very tempremental, flakey and delicate SureSignal box fault.
Yes the box gets an IP address from the router - what exactly would I be contacting my Broadband provider about. This is just going to waste more time here as Im fully expecting to get the reply back that there is no reason why the network would block anything and they cannot offer support on a device they didnt make...
What can I say? I came home from work this evening to find that after 6 days of flashing lights, a steady single light and a configured VSS!! And if appears to be working fine. FIngers crossed that we have finally got there. Will let you know otherwise.
Thanks again for your help.
09-04-2012 10:21 AM - edited 09-04-2012 10:24 AM
Same problem as the rest. Solid red light only. Tried resetting device pushing reset button and reinserting power cable, no change.
Broadband speeds 12mb download 0.8mb upload.
SS has been registered since ~9am yesterday so it has been over 24hours.
All ports are open, 8, 50, 123, 500, 4500, SS has static IP assigned. Router is Netgear DGND3700 but I am connecting through an access point which is a similar device Netgear WNDR3700. I have reset both router and access point, still no change.
I even changed the cat5 cable with no result, not surprisingly. Also, the SS did previously work when I tested it a month or so ago.
Tracing route to 184.108.40.206 over a maximum of 30 hops
1 8 ms <1 ms <1 ms 192.168.1.1
2 12 ms 9 ms 9 ms 220.127.116.11
3 9 ms 10 ms 9 ms 18.104.22.168
4 12 ms 10 ms 9 ms 184.108.40.206
5 10 ms 9 ms 10 ms 22.214.171.124
6 10 ms 9 ms 10 ms 184.108.40.206
7 9 ms 12 ms 10 ms acc1-10GigE-0-2-0-7.bm.21cn-ipp.bt.net [109.159.
8 18 ms 18 ms 18 ms core2-te-0-10-0-7.ilford.ukcore.bt.net [109.159.
9 15 ms 15 ms 14 ms peer1-xe0-1-0.telehouse.ukcore.bt.net [109.159.2
10 19 ms 18 ms 21 ms LNDGW2.arcor-ip.net [188.8.131.52]
11 19 ms 19 ms 17 ms 126.96.36.199
12 * * * Request timed out.
13 * * * Request timed out.
14 * * * Request timed out.
15 * * * Request timed out.
16 * * * Request timed out.
17 * * * Request timed out.
18 * * * Request timed out.
19 * * * Request timed out.
20 * * * Request timed out.
21 * * * Request timed out.
22 * * * Request timed out.
23 * * * Request timed out.
24 * * * Request timed out.
25 * * * Request timed out.
26 * * * Request timed out.
27 * * * Request timed out.
28 * * * Request timed out.
29 * * * Request timed out.
30 * * * Request timed out.
Trace complete.
I am an advanced IT user and have spent about 10hours troubleshooting this white box - if only it had an interface and feedback of some sort! It's very frustrating working with a box with LED's and nothing more.
Would appreciate help with this please, thanks.
Get help and technical support on Vodafone's devices, products and services from our online community
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text:
A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
1. In a programmable logic device having (1) a plurality of word line conductors; (2) a plurality of P-term line conductors, each of which is programmably interconnectable to at least some of said word line conductors for producing on each P-term line conductor a signal which is a logical function of the signals on the word line conductors to which that P-term line conductor is interconnected; and (3) a clock signal utilization device for processing a signal derived from at least one first P-term line conductor in accordance with an applied clock signal, the improvement comprising:
means for providing a first signal which can be selected to be either a synchronous clock signal or a constant signal;
means associated with at least one second P-term line conductor for allowing the signal on said second P-term line conductor to be made a constant signal; and
means for logically combining said first signal and a signal derived from the signal on said second P-term line conductor to produce said applied clock signal.
2. The apparatus defined in claim 1 wherein said means for logically combining said first signal and said signal derived from the signal on said second P-term line conductor comprises an OR gate.
This application is a division of application Ser. No. 190,663, filed May 5, 1988 now U.S. Pat. No. 4,871,930.
This invention relates to programmable logic integrated circuits. In particular, the invention relates to a new architecture which provides for greater utility and flexibility of programmable logic devices ("PLDs"), and allows for programmable logic devices of much greater complexity than previously were possible.
The following references are background to this invention: Hartmann et al. U.S. Pat. No. 4,617,479; Hartmann et al. U.S. Pat. No. 4,609,986; Veenstra U.S. Pat. No. 4,677,318; Hartmann et al. U.S. Pat. No. 4,713,792; Birkner et al. U.S. Pat. No. 4,124,899; Cavlan U.S. Pat. No. 4,703,206; Spencer U.S. Pat. No. 3,566,153; J. C. Leininger, "Universal Logic Module", IBM Technical Disclosure Bulletin, Vol. 13, No. 5, Oct. 1970, pp. 1294-95; Ronald R. Munoz and Charles E. Stroud, "Automatic Partitioning of Programmable Logic Devices", VLSI Systems Design Magazine , Oct. 1987, pp. 74-78, and 86; and E. Goetting et al., "A CMOS Electrically-Reprogrammable ASIC with Multi-Level Radom Logic Capabilities", 1986 IEEE International Solid State Circuits Conference (Proceedings), pp. 244, 245, 359, and 360. All of these references are hereby incorporated by reference herein.
Several approaches have been used for the architecture of programmable logic integrated circuits. Among these are the "programmable AND, fixed OR" structure (referred to as a PAL) used in the above-mentioned Birkner et al. patent. This architecture has the advantages of higher speed and a simpler structure. However, because it has a fixed number of "product terms" (hereinafter "P-terms") per OR logic function eight P-terms is typical of most current PAL products), and because these P-terms cannot be shared by neighboring OR gates, many P-terms are typically wasted. On the other hand, thee are occasions when eight P-terms are not enough to handle the more complex logic functions. Experience has shown that in a broad range of applications, eight P-terms is on average much more than enough, and yet it is also often insufficient. For example, FIG. 2 in the above-mentioned Munoz et al. article is a graph of P-term requirements for a relatively large sample of logic functions (Munoz et al. FIG. 2 is substantially reproduced herein as FIG. 1). Similar studies done by the assignee of the present invention arrive at roughly similar conclusions: namely, a large percentage of logical functions (on the order of 50 to 70 percent) require less than four P-terms. However, a relatively significant "tail" exists where eight P-terms is not enough.
One way to achieve higher P-term utilization is to provide "variable P-term distribution". In essence, this is an attempt to guess a mixture of P-term requirements such that some OR gates have few P-terms (e.g., four), and some have a relatively large number (e.g., 12 or 16). See, for example, above-mentioned U.S. Pat. No. 4,609,986. This partially solves the problem of P-term utilization, but it significantly increases the complexity of the software support task because each function must be examined and then, depending upon its demand for P-term resources, assigned to a specific macrocell which has the minimum resources needed to fulfill the required demand (this process is called "fitting"). However, even with variable P-term distribution, many P-terms are typically still wasted.
Another way in which this P-term allocation problem can be solved is suggested in the above-mentioned paper by Leininger. With this structure, the P-term array is viewed as an array of programmable NOR or NAND gates whose inputs are programmable. Functions which require more than a single P-term are broken into multi-level NAND (or NOR) functions. Each level of (e.g., NAND) logic takes one P-term. Using this type of array, even quite complex logic functions can be done in a few levels of NAND logic. Again, however, there are some drawbacks. First, it is very likely that most logic functions will take more than a single P-term. This means that most often, several passes through the array will be required, and this causes a slowing down of evaluation of the function. Second, each P-term must feed back into the array input section. Thus, as the number of P-terms grows, so does the number of input lines. Even for arrays of modest complexity, the number of input signal lines (sometimes called "word lines") becomes excessive. For example, the part described in the above-mentioned IEEE ISSCC paper has only eight macrocells but has nearly 100 word lines, while a PAL circuit of similar complexity has only half as many word lines. Each word line adds to the length (and therefore the parasitic capacitance) of all of the P-terms. Greater P-term length leads to slower signal propagation.
Finally, there are programmable logic arrays ("PLAs") of the type described in the above-mentioned Spencer patent. Most (if not all) functions can be accomplished in one pass through the "AND" array plus one pass through the "OR" array. However, even the simplest functions require these two array delays. Thus, compared to the PAL architecture, there is a speed penalty (at least for simple functions). This type of PLA circuit is also more complex to execute in silicon because of the need for interface buffering between the AND and the OR array, and because of the inherently more complex programming circuits needed to program the two arrays.
In prior art programmable logic devices, a major obstacle to increasing the logic density has been array sizes which increase as the "square" of the increase in the number of output functions. This is true because for complete generality, it is necessary that all output functions also feed back as inputs into the array. However, in practice, it has been observed that this is massive overkill. That is, on average, only some subset of functions needs to be fed back. One solution to this problem is to break a single large array into several smaller arrays with functional communication between the smaller array blocks. In prior at devices such as the EP1200 (see U.S. Pat. No. 4,609,986) and the EP1800 (both commercially available from Altera Corporation of Santa Clara, California), this interconnect between blocks was done in a fixed manner. That is, in a device with several array blocks, there is local feedback to an array block, and there are a certain fixed number of global feedback signals between array blocks. While this approach does serve to keep the array sub-blocks to reasonable size (both from a bit density and a speed point of view), it creates routing bottlenecks between blocks. For example, in the Altera EP1800, there are four array blocks each with 12 flip-flop macrocells. Only four macrocell outputs from each array block are routed as global inputs to the other blocks. This bottleneck causes significant restrictions in allowing logic functions to "fit" within a device even though there are enough other resources (such as flip-flops, I/O pins, etc.).
In view of the foregoing, it is an object of this invention to provide an architecture for programmable logic devices which allows for the implementation of PLDs of much greater complexity.
It is another object of the invention to maximize the utilization of P-terms in PLDs.
It is a further object of the invention to make PLDs of high complexity that can operate at high speed.
It is a further object of the invention to provide for multiple logic array blocks ("LABs" ) which can operate independently or in concert, and to provide for a programmable interconnect array ("PIA") structure which allows for ease of communication between these array blocks.
It is a further object of the invention to provide a macrocell which is simpler and provides for increased functionality.
It is a further object of the invention to provide a regular, repeatable architecture which will be easy for a user to understand and easy for software tools to support.
It is a further object of the invention to provide for a modular architecture which allows for ease in constructing a family of products simply by reducing or increasing the number of LABs and the associated PIA structure.
It is a further object of the invention to allow for package bonding options such that some of the I/O pins are not bonded out, thus allowing high density PLDs to be put into relatively low pin-count packages.
The present invention solves all of the above-mentioned P-term allocation problems, and in addition provides a programmable interconnect array structure which allows the implementation of much larger programmable logic devices (PLDs) than have heretofore been possible. Among the major elements of the present invention are:
1. The logic array block ("LAB") best seen in FIG. 3.
2. The macrocell/flip-flop block best seen in FIG. 5.
3. The programmable interconnect array ("PIA") best seen in FIG. 3.
4. The input/output circuit best seen in FIG. 5.
5. The clock functions best seen in FIG. 5.
As mentioned above, the present invention increases the utilization of P-terms. Most functions (e.g., counters, demultiplexers, 2-to-1 and 4-to-1 multiplexers, and shift registers, as well as any simple AND, OR, NAND, or NOR function) can be done in one pass through the array. Many more complex functions which require three P-terms or less and which can directly utilize the EXCLUSIVE-OR (XOR) gate can also be done directly in a single pass through the array. This accounts for approximately 70% of the logic functions that are found in most logic designs. The remaining functions which require additional product terms can be done by using "expander" P-terms which (in combination with the three-P-term programmable AND, fixed OR, XOR) can produce very complex NAND-NAND, AND-OR, OR-AND, and NOR-NOR types of functions. The general advantage of this combined structure is that a majority of logic functions can be done in one pass through the array (thus achieving maximum speed), and even the most complex functions can be done in two passes.
The output of the above-mentioned AND-OR-XOR structure feeds a flip-flop logic block. In prior art circuits such as the Altera EP300 (see U.S. Pat. No. 4,617,479) this is typically a conventional D flip-flop with a mechanism for allowing the flip-flop register to be optionally bypassed to allow the combinational output to be applied directly to the output section if desired. In the device described herein, this structure has been modified such that the multiplexer and attendant control formerly required to bypass the flip-flop are no longer necessary. In place of the old structure a new flip-flop structure has been incorporated which allows operation as a D flip-flop, a level-sensitive latch, or a completely flow-through device which allows combinatorial functions to be directly propagated. A preferred structure for this new flip-flop is described in concurrently filed, commonly assigned, co-pending U.S. Pat. application Ser. No. 190,530, which is hereby incorporated by reference herein.
The device of this invention solves the routing bottleneck problem by the creation of a programmable interconnect array (PIA) which allows any logic function output and any of the I/O input signals to be input to any of the logic array blocks (LABs). With this programmable interconnect array structure in place, the LABs can be kept to sizes which are functionally convenient, modular, and have a reasonable number of programmable elements. While all logic function outputs and the I/O inputs are taken into the PIA (a total of 180 word lines in the case of the device depicted in FIG. 3), only a subset (24 in the case of the present devices) are programmably routed as inputs into each of the logic array blocks. Unless an LAB requires more than 24 such inputs (which is highly unlikely, this architecture allows for completely general routing of signals.
In most prior art programmable logic devices, certain package pins are designated as inputs and others as outputs (see, for example, the MMI 16R8, commercially available from Monolithic Memories Incorporated (now merged with and part of Advanced Micro Devices ("AMD") of Sunnyvale, California). An improvement on this has been the use of tri-state buffers in conjunction with a feedback path from the I/O pin back into the array such that when the output buffer is in its tri-state condition, the pin may be used as an input (see the above-mentioned Birkner et al. patent). This mechanism provides for flexibility of usage of pin resources. However, when the I/O buffer is tri-stated and the associated pin is used as an input, the associated output macrocell logic is lost. This is a waste of precious resources. A solution to this problem is provision for "dual-feedback" such as that found on certain pins of the Altera EP1800. Dual feedback provides a feedback path both from the I/O pin and from its associated logic macrocell. Thus when the output buffer is tri-stated, the I/O pin can be used as an input and the macrocell resource can still be used as a "buried" register. In the present device, this mechanism is further improved in that I/O pin feedback does not go directly into the array, but rather is an input to the PIA. Thus I/O input lines can go to ny or all of the LABs, while at the same time the logic macrocell function can be used (1) locally as feedback to its own LAB, and (2) globally va the PIA. Thus I/O pin functions are effectively decoupled from the logic arrays. This provides for much greater utility and flexibility than was heretofore possible.
Generally, the register functions in PLDs are clocked either synchronously (for example, see the MMI 16R8) or asynchronously (see the MMI 20RA10). In most systems, there is a need for both types of capabilities. A solution to this problem is the structure that has been used in the Altera EP600, EP900, and EP1800. In these devices a multiplexer has been provided which allows the user to select either the synchronous (global) clock signal or an "asynchronous" (local P-term) clock. This selection can be made on a macrocell-by-macrocell basis. However, this multiplexer structure adds to the complexity of the device, and the additional circuitry needed to make the selection adds delay to the clock signal. An improved approach has been taken in the present device which allows for a simple clock gating of the "global" synchronous clock with a local P-term. If the synchronous clock is desired, then the asynchronous clock P-terms are programmed such that they are always low. This allows the global clock signal to pass to the flip-flop. If asynchronous clocking is desired, the global clock signal is forced low (again by programming) and the local clock P-term is allowed through to clock the flip-flop. The clock selection (i.e., synchronous versus asynchronous) is done on a per LAB basis. This structure completely eliminates the clock multiplexer and the controls for same. This new structure is simpler and faster.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the invention.
FIG. 1 is a chart showing typical product term distribution (frequency of occurrence of logic functions requiring a given number of product terms to implement the same) for a large sample of PLD designs.
FIG. 2 is a prior art programmable logic circuit macrocell.
FIG. 3 is a block diagram of an illustrative embodiment of the present invention.
FIG. 4 is a block diagram of one section of the embodiment of FIG. 3 showing one logic array block (LAB) and one programmable interconnect array block (PIA).
FIG. 5 is a logical representation of a (macrocell) portion of an LAB in the embodiment of FIGS. 3 and 4.
FIGS. 6a (comprising parts 6a and 6aa) and 6b (comprising parts 6b and 6bb) are diagrams showing two "bond out options" for the device shown in block diagram form in FIG. 3.
FIG. 7 is a block diagram of an alternative embodiment having fewer LABs than the device shown in FIG. 3.
FIGS. 8a through 8h illustrate the way in which logic functions of varying complexity can be fit into the macrocell of the present invention.
FIG. 9 is a truth table useful in explaining the operation of a new flip-flop-type element used in the device of this invention.
FIG. 3 is an overall block diagram of an illustrative embodiment of a programmable logic device 10 constructed in accordance with the present invention. The major elements shown in this diagram are "fast inputs" 30, I/O pads 40, logic array blocks (LABs) 50, and programmable interconnect array (PIA) blocks 60.
Input signals into chip 10 come from either fast inputs 30 or I/O inputs 40. Fast inputs 30 are routed via lines 31 to all of LABs 50. These signals drive into the array portion of the LAB through buffers 57 which provide both the true and complement polarity of the signal presented to the fast input pad. These lines are called fast inputs because they go directly to the LABs, in contrast to I/O inputs 40 which go indirectly to the LABs via PIA blocks 60. This can be seen by following representative signal line 41 from the pads labeled I/O0:7 (which represent eight such I/O pads) to buffer 42. After the signal has been suitably buffered by buffer 42, it drives into the PIA along line 43. By means of programmable elements 63 which are at the intersection of PIA word lines 43 and interconnect term lines 61, a signal which originated at one of the I/O pads 40 can be routed to any LAB 50 via the interconnect term 61 through buffer 58 and then into a true/complement LAB word line buffer 57. Signals propagating to an LAB via this path take additional time to traverse the PIA. Hence these signals are "slower" than the "fast" input lines 31 which go directly to the LAB as explained above. The reasons for providing these two different paths will be explained in due course.
A typical LAB 50 will now be explained in more detail. In this architecture there can be as many LABs as is deemed desirable. For example, in various preferred embodiments implemented to date we have used either four or eight LABs.
Each LAB 50 comprises macrocells 51 and expanders 52. Inputs to the LAB are provide by fast inputs via buffers 57, PIA inputs via interconnect terms 61 through buffers 58 and 57, feedback terms from macrocell outputs via buffers 54 and 57, and expander feedback terms via buffers 55 and 56. Two types of macrocells are provided. The only difference is the inclusion of output buffers 53 (plus their associated output enable (OE) signal 110 which provides the output tri-state control) in macrocells 1 through 8. Output buffers 53 selectively apply the associated macrocell outputs to I/O signal pins 40. Macrocells 9 through 16 have no associated output buffer and are therefore sometimes referred to as "buried" macrocells. In either case, the macrocells all have buffers 54 which take the signal generated by the macrocell and feed it to its own LAB (as described above) and also drive PIA word lines 62.
In the preferred embodiment shown in FIG. 3, each LAB 50 has 16 macrocells, 32 expanders, eight fast inputs, and 24 array inputs from the interconnect terms of the PIA. Each LAB also has a number of tri-stat output drivers 53: eight drivers 53 in the case of the LABs labelled group A, B, H, and G, and five drivers 53 in the case of the LABs labelled group C, D, F, and E. While we believe these choices to be optimum for the particular embodiment shown, other choices could be made without departing from the scope and spirit of the invention. For example, in another embodiment (shown in FIG. 7), there are four LABs, each of which has seven tri-state drivers In addition, the chip shown in FIG. 7 has eight dedicated inputs and four power/ground pins.
PIA blocks 60 will now be described with reference to FIG. 3. The PIA provides a mechanism for programmably routing signals from I/O input pins 40 to any LAB and from any LAB macrocell output to any other LAB. The PIA includes word lines 43 and 62 and bit lines 61. The bit lines are also labelled "interconnect terms" in FIG. 3. In the preferred embodiment shown, there are 52 word lines 43 which come from the I/O lines, and there are 128 word lines 62 which are driven from macrocell buffers 54. Interconnect terms 61 are perpendicular to the word lines. At the intersections of the word lines and bit lines are programmable elements 63 which, when programmed in one state, provide a connection between the associated word and bit lines, and which, when programmed in the other state, provide no such connection. In the preferred embodiment, the programmable elements are EPROM transistors. However, other types of programmable elements such as EEPROM transistors, fuses, anti-fuses, or other similar elements could be used without departing from the scope and spirit of the invention. There are 24 interconnect terms 61 feeding each LAB 50 in the embodiment shown. Again, this number is an estimate as to the optimum number for the device shown in FIG. 3, but a larger or smaller number could be used if desired. The entire PIA (i.e., all of PIA blocks 60 taken together) is therefore a programmable array with 180 word lines and 192 bit lines (eight groups of 24 bit lines).
FIG. 4 is a block diagram showing a single LAB 50 and its associated PIA 60. This diagram shows, in concept, the signal routing to and from the LAB and the PIA. Lines going into the LAB are the fast inputs 570 shown as a group of 8�2=16 lines (true and complement signals), the interconnect terms 580 shown as a group of 24�2=48 lines (true and complement signals), the macrocell feedback lines 590 shown as two groups totaling 16�2=32 lines (true and complement signals), and the "expander" feedback lines 560 shown as a group of 32 lines (single polarity only). This totals to 128 word lines for each LAB in the embodiment shown. There ar 152 bit lines (P-terms) in each LAB. These will be described in detail in the discussion of FIG. 5. Shown in the diagram of FIG. 4 are the groups of signals 530 and 531 going to the output buffers labeled 53 in FIG. 3. Lines 530 provide the path for data from the macrocells to the output buffers, and lines 531 provide the path for the output enable (OE) signals from the OE P-terms. The PIA block 60 associated with this LAB is shown as having 180 word lines and 24 bit lines as previously described.
Referring now to FIG. 5, we can see more of the detail of one of the macrocells. In this case it is shown with an I/O buffer 53. If it were a buried macrocell, the only difference (at least pictorially) would be the absence of output buffer 53, the OE P-term structure (101, 103, 110), and I/O pin 40. The programmable array is shown a the intersection of word lines 102 nd bit lines 101. The label 51 refers to that part labelled "macrocell" in FIG. 3, and the label 52 refers to that part labelled "expander" in FIG. 3. Actually, in the physical layout of the chip, two expander P-terms are preferably grouped with the P-terms of each macrocell for convenience. In the description of FIG. 5, the word "macrocell" will be used to describe the entire collection of P-terms (including the two expander P-terms) and the associated logic gates 103-107, flip-flop 123, and output buffer 53, if present.
There are ten P-terms 101 in this macrocell. Each P-term receives inputs from the 128 word lines 102 (described earlier). There is a programmable element (similar to element 63 in the PIA) at the intersection of each bit line with each word line. A logical AND function of any of the word line variables can be formed by programming these elements. This is described in U.S. Pat. No. 4,617,479 and will not be repeated here. The correct logical outcome produced by each P-term is represented either as an active-low AND gate 103 or as a NOR gate 104. Those skilled in the art will recognize that other representations could be shown without departing from the scope and spirit of the invention. For example, an active-high AND gate could be used if one notes that the opposite polarity word line were used as its input and thus achieve the same logical result.
The purpose of each P-term is as follows: The P-term labelled OE is used as the output enable for the associated output buffer 53. If this were a buried macrocell, this bit line would be absent. SETN is used to control the preset of flip-flop 123. The next three terms, P0, P1, and P2, feed OR gate 105 which produces a logical sum-of-products at its output 115. This collection of P-terms, in conjunction with gate 105, forms the "programmable AND, fixed OR" function described in U.S. Pat. No. 4,124,899. The term labeled INV is used as an "invert control" for XOR gate 107. This allows for the creation of inverted sum-of-product functions at line 121. This will be recognized by those skilled in the art as expanding the number of possible functions which can be realized. In addition to acting as a static control for the inverted sum-of products option, the INV term can be used "dynamically" as a direct input to the XOR gate 107. For example, any logic function which can be reduced to (1) an EXCLUSIVE-OR of an AND function with an AND-OR function, (2 ) an EXCLUSIVE-OR of an OR function with an OR-AND function, (3) an EXCLUSIVE-OR of an OR function with an AND-OR function, or (4) an EXCLUSIVE-OR of an AND function with an OR-AND function can be implemented in detail in FIGS. 8a and 8c; the dollar sign in FIG. 8a represents the EXCLUSIVE-OR function.) ACLK is used to create an "asynchronous" clock signal for flip-flop 123 in conjunction with gate 106 and gates 109 and 108. CLEARN is used to control the "Clear" line on flip-flop 123. EXP1 and EXP2 are the "expander" P-terms. Note that each expander 52 preferably includes only a single P-term.
Our assignee has studied the most often used logic functions in relation to a variety of possible architectures. In particular, the AND-OR-XOR structure of P0, P1, P2, OR gate 105, and XOR gate 107 was analyzed assuming both less than three AND P-terms (e.g., two AND P-term) feeding OR gate 105, and more than three AND P-terms (up to eight P-terms such as is used in the prior art macrocell of FIG. 2) feeding the OR gate. The classes of functions included the following: adders, comparators, counters, decoders, demultiplexers, parity generators, and shift registers. The purpose of the study was to evaluate the architecture of the present invention relative to the prior art architecture of FIG. 2. The present new architecture is a combination of three programmable ANDs, a fixed OR, and an XOR, with single-P-term "expanders". This architecture is believed to be superior to both the prior art structure shown in FIG. 2 and to the single-P-term architectures proposed in the above-mentioned Goetting et al. reference. The study bore this out and reached several other important conclusions. It was found that having less than three P-terms feeding the OR gate is very restrictive when doing counters and shift registers. For all other functions examined, three P-terms feeding the OR gate was always as good as four P-terms feeding the OR. (This is only true assuming that in either case there is the additional BLIV P-term and XOR gate 107.) The prior art eight-P-term architecture is only superior for a very limited group of functions (for example, multiplexers with more than four inputs). The study also demonstrated that having approximately two expander P-terms per macrocell was more than sufficient to accommodate the less common functions which require many P-terms.
Expanders 52 play an important role in this new architecture. As their name implies, these P-terms allow for growth. That is, they allow for implementation of those (less common) functions which do not fit within the three-P-term limit (for example, an 8-to-1 multiplexer can be fit into 9 expanders). Expander P-terms anywhere in the LAB can be used to form elements of these more complex functions, and then the outputs of these P-terms are combined using another P-term (typically one of the P-terms feeding a fixed OR gate 105) (see, for example, FIG. 8f). Functions formed with expander P-terms can also be used to feed other expanders on single P-terms such as INV, ACLK, SETN, CLEARN, or OE. Also, there are often common P-terms which can be used by a number of logic functions. These common P-terms can be formed by he expanders and then fed to those functions (which are likely to be implemented in a programmable AND fixed OR section) for which they are required. FIG. 8e shows an example of a logic expression which requires more than three P-terms which can be factored into expressions which can be formed using the expander P-terms and recombined using another P-term (typically his will be a P-term which feeds the fixed OR gate). In FIG. 8e, the original expression has been factored such that two factors are implemented in two expanders and then combined with the remainder of the expression in one of the P-terms feeding the fixed OR gate. The original expression was:
This expression can be factored and rewritten as:
The common factors X*Y are formed on the P-term feeding the fixed OR gate, while the remaining factors (A+B+C) and (D+E) are formed on each of two expanders and fed to the P-term which contains the X*Y term. In this example, an expression which would have required six P-terms to implement can now be done in three P-terms. Suppose further that either the expression (A+B+C) or the expression (D+E) were required by some other macrocell or macrocells. These same expressions formed on the expander P-terms could be used again by those other macrocells. Thus an expression generated on the expanders can be amortized across all of the macrocells which have the expander's outputs as word line inputs. This again results in an overall saving of valuable P-term resources. Examples of various types of logic functions which can be fit into the P-term structure of the present invention are shown in FIGS. 8a through 8g. Latches require only two expanders. This structure is shown in FIG. 8h.
Continuing now with FIG. 5, XOR gate 107 receives its inputs from OR gate 105 and P-term INV. Those skilled in the art will recognize that if the logic signal on line 116 is 0, then the output of XOR gate 107 (line 121) will have the same logic value as input 115. On the other hand if line 116 is 1, then 121 Will be the logical inversion of 115. In addition to allowing for inverted sum-of-product functions, or positive or inverted product-of-sum functions, this structure, in conjunction with a D flip-flop such as 123, also allows for emulating other flip-flop types such as T, J-K and R-S. Emulation of various flip-flop types using array logic and XOR gates is the subject of U.S. Pat. No. 4,677,318. When using the expander P-terms as an AND array and the P-terms feeding the OR gate 105 as an OR array, the INV signal 116 needs to be set to a logic 1.
Flip-flop block 123 appears to be a simple D flip-flop with active low preset (P) and clear (C). However, this is done for simplicity of illustration of the macrocell. FIG. 9 is a truth table which explains the full functionality of element 123. Note that if P=C=1, then 123 is an edge-triggered flip-flop. At the rising edge of CLK (line 122 in FIG. 5), whatever data is present at the D input 121 is transferred to the Q output 124. If P is 0 and C is 1 then the Q output will be forced to 1 independent of the state of CLK or D. If C is 0 and P is 1, then the Q output will be forced to 0 independent of the state of CLK or D. To those skilled in the art, the case where P=C=0 is an illegal condition and is not defined. For flip-flop 123, however, when P=C=0, the flip-flop is redefined as shown in FIG. 9. It thus becomes a "flowthrough latch". Then, whenever line 122 is high, the Q output takes the value of whatever is on the D input. Whenever line 122 is low, the Q output holds the value that was present at the D input when line 122 went low. If line 122 is held high (for example, by programming P-term ACLK high), then signals will propagate directly from 121 to 124. This is the same "combinatorial" function as was provided by multiplexers and architectural control EPROM bits on prior art EPLD circuits. The present new design is simpler, faster, and provides greater functionality. As has been mentioned, a preferred structure for implementing flip-flop 123 is shown in concurrently filed, commonly assigned, co-pending Pat. application Ser. No. 190,530, which is hereby incorporated by reference herein.
The output signal 124 from flip-flop 123 (1) goes to the input of output driver 53, (2) feeds back (via buffer 54) to a word line driver 57 of its own LAB, and (3) drives one of the word lines of the PIA (indicated as line 62 in FIG. 3). This signal 124 can be used by any other LAB via its connection through the PIA. The signal also feeds a conventional tristate I/O buffer 53 such that if the buffer is enabled by line 110, the signal from 124 will drive off chip through I/O pin 40. I/O pin 40 can also provide an input path from off chip via line 41. This line drives buffer 42 (FIG. 3) whose output becomes one of the word lines for the PIA shown as line 43 in FIG. 3. I/O buffer 53 can be dynamically controlled by the OE P-term, in which case pin 40 may be both an input and an output depending upon the state of line 110. Alternatively, by programming the chip such that OE is always 0 buffer 53 will always be disabled, in which case I/O pin 40 can be used permanently as an input. Thus each of I/O pins 40 can be configured as input, output, or bi-directional input/output terminals. Because of the feedback of signal 124 to the LAB and the PIA, and the I/O input line 41, disabling of the output driver 53 does not result in the loss of the macrocell's functionality. This is a significant advantage over some prior art devices.
Turning now to the clock structure for the LAB, this structure includes inverter 109, AND gate 108, OR gate 106, and P-term ACLK. Three modes of operation are anticipated as follows:
COMBINATORIAL MODE: In this case, P=C=0 as previously described. Further, the ACLK P-term is programmed to always be 1, and line 122 is therefore also always 1. Whatever data is present at line 121 will pass through flip-flop 123 and appear at line 124.
ASYNCHRONOUS MODE: In this case, the line labeled ECKN (which is an extra P-term (not shown) in the LAB) is programmed to be 1. This means that line 125 is logic 0. Then line 122 is directly controlled by the state of the ACLK P-term. ACLK can be any (inputs active-low) AND function of any of the word line variables. Each flip-flop in the LAB has its own separate ("asynchronous") P-term clock.
SYNCHRONOUS MODE: P-term ACLK is programmed to be always 0. Also, ECKN is programmed to be 0 and thus ECK is 1. This allows the signal EXT.(SYNC.)CLK. on line 32 to propagate through AND gate 108 and appear on line 125. EXT.(SYNC.)CLK. line 32 comes from an input pad (one of the "fast inputs") not shown. This signal on line 125 passes through OR gate 106 and appears on line 122. In this way, an external signal can directly control the clocking of flip-flop 123. Because there is a single ECKN P-term per LAB, the selection of synchronous mode is done on a per LAB basis rather than on a per macrocell basis.
Another advantage of the chip architecture of the present invention is that chips of any given configuration can be packaged in any of a variety of ways with no loss of internal resources. For example, FIG. 6a illustrates one way in which the chip of FIG. 3 can be bonded out to 68 pins, while FIG. 6b shows how the same chip can be bonded out to 40 pins. The chip pads which are not bonded out in FIG. 6b are certain I/O pins. However, the "output" signals that could be applied to these chip pads are still usable internally, and the remaining external inputs can be applied to any LAB via PIA 60. Thus, even though some chip pads are not bonded out in FIG. 6b, the only loss in chip capability is the loss of the external chip I/O connections. (With reference to FIGS. 6a and 6b, the eight LABs on the chip are designated A through H. Thus, for example, in FIG. 6a eight I/O pads I/OA0-8 of LAB A are bonded out to lead tips 11 through 4, respectively, while in FIG. 6b only four I/O pads I/OA0, 1, 2, and 7 are bonded out to lead tips 37 through 34, respectively. In FIG. 6a LABs A, D, E, and H each have eight bonded-out I/O pads and the remaining LABs each have five bonded-out I/O pads. In FIG. 6b LABs A, D, E, and H each have four bonded-out I/O pads and the remaining I/O pads each have three bonded-out I/O pads. In both FIG. 6a and 6b the "fast" inputs are designated I0 through I7.)
Although particular numbers of such components as macrocells, expanders, fast inputs, and array inputs from the PIA are employed in the depicted embodiments described above, it will be understood that (among other possible variations within the scope of the invention that will occur to those skilled in the art) any number of such components can be used without departing from the scope and spirit of the invention.
Patent Citations
Non-Patent Citations
Referenced by
Legal Events
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On April 22nd New York's Roseland Ballroom will host The T.J. Martell Foundation's 13th Annual Family Day in honor of Train. As well as performing an intimate acoustic set, multiple Grammy Award winning band Train will be acknowledged for their charity work. And there's even more cause for a Train celebration, as their new album, California 37, will be released on April 17th, mere days before the iconic event. Train front man Pat Monahan said of the occasion, "Train is honored to be part of T.J. Martell's Family Day. The T.J. Martell Foundation has been doing incredible work in the medical community and we are inspired by their dedication. We hope to make this the best Family Day ever." Joining Train on the day will be a Cobra Starship, who will put on a special DJ set, and Nickelodeon star Ariana Grande who will also play live. And along with Train, Crush Management (who represent both Train and Cobra Starship) will also be honored. The event will raise money for leukemia, cancer and AIDS research and tickets can be purchased via TJMartellFoundation.org or by calling Foundation at (646) 841-1394. We suggest you try to get involved — it's a great opportunity to contribute to a good cause while seeing your favorite musicians perform!
[Photo: Getty Images]


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For Immediate Release: 9/29/2003
|County Recognized by NATOA with Government Programming Awards
Montgomery County was recently recognized by The National Association of Telecommunications Officers and Advisors (NATOA) for excellence in broadcast, cable, multimedia and electronic programming developed by municipal agencies.
The County's cable television show on the sniper investigation and the County's Web Site were both honored at the 18th Annual Government Programming Awards Ceremony in Denver, CO.
"Our county government cable channel and web site are useful tools for communicating with the public and we have worked hard to make them interesting and useful," said Montgomery County Executive Douglas M. Duncan. "National recognition is always welcome, and it's especially nice to be judged by others in the government programming field."
In the public safety category, Montgomery County received first place for "Solving the Sniper Shooting Case." In the category of city or county web sites, Montgomery County placed second for the Montgomery County, MD web site. The "County Cable Montgomery Web Site" received an Honorable Mention in the Government Access Station Web Site category.
NATOA received 925 entries from municipalities across the country. The entries covered 59 categories of programming including, among others, community events, documentary, public affairs and public service, interview talk show, performing arts, sports, election coverage and children's issues.
|Release ID: 03-410
Media Contact: Donna Bigler 240-777-6507
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TweakTown NewsRefine News by Category:
Software Posts - Page 67
Download of the Day: DAEMON Tools Lite 4.41.3
Our Download of the Day today is DAEMON Tools Lite 4.41.3.
With DAEMON Tools you can back up your physical CD/DVD/HD DVD/Blu-ray discs into "virtual discs" or so called "disc image" files, which run directly on your hard drive. You can also work with images created by other burning programs! DAEMON Tools supports variety of image types. Use CD/DVD image converter to have one format images in your Image Catalog!
1. Emulate virtual CD/DVD-ROM/HD DVD and Blu-ray drives
DAEMON Tools Lite [Commercial] enables you to emulate up to 4 CD/DVD virtual drives on your PC. Virtual drives will appear in your OS just like real ones. Select a virtual drive then choose a disc image you want to mount. Find the created virtual drive with mounted disc image in My Computer. Start working! Looks like working with a real drive and a real disc, doesn't it? Yes, but it is much faster!
2. Create a disc image
With DAEMON Tools Lite [Commercial] you can create ISO and MDS image files from original discs inserted in physical CD/DVD/HD DVD/Blu-ray drives. Or use images you have created earlier with other program. DAEMON Tools products work with variety of image types.
Key features
creates *.iso and *.mds images;
emulates up to 4 virtual CD/DVD drives;
performs image mounting and unmounting;
Continue reading 'Download of the Day: DAEMON Tools Lite 4.41.3' (full post)
Download of the Day: Fraps 3.4.6
Our Download of the Day today is Fraps 3.4.6.
Fraps is a universal Windows application that can be used with all games using DirectX or OpenGL technology. In its current form Fraps performs many tasks and can best be described as:
Benchmarking Software - See how many Frames Per Second (FPS) you are getting in a corner of your screen. Perform custom benchmarks and measure the frame rate between any two points. Save the statistics out to disk and use them for your own reviews and applications.
Screen Capture Software - Take a screenshot with the press of a key! There's no need to paste into a paint program every time you want to capture the screen. Your screen captures are also automatically named and timestamped.
Realtime Video Capture Software - Have you ever wanted to record video while playing your favourite game? Come join the Machinima revolution! Throw away the VCR, forget about using a DV cam, game recording has never been this easy! Fraps can capture audio and video up to 1152x864 and 100 frames per second! All movies are recorded in outstanding quality.
Fraps has support for Vista and DirectX 10 games. Since the Vista Desktop Window Manager (DWM) runs through DirectX you can now take screenshots and record video from the desktop just like any other game or 3D application in Vista.
Continue reading 'Download of the Day: Fraps 3.4.6' (full post)
Windows XP falls below 50% OS market share
At the end of July, Windows XP fell below 50% OS market share. Between June and July, Windows' market share in general dropped 0.63 percentage points (from 88.29-percent to 88.76-percent), whilst Mac OS games 0.22 percentage points and Linux gained 0.03 percentage points. Mobile operating systems have also, most obviously, gained market share. In the same period, Windows 7 gained 0.74 percentage points whilst Vista slipped 0.28.
By the end of 2010, Windows 7 nabbed 20% of the market and by the end of April 2011, it had 25%. Last month Microsoft reported they had sold over 400 million licenses in 21 months which means they're selling no less than 20 million per month. Back to school season is approaching which should see these numbers stay solid until at least 2012.
Download of the Day: SuperAntiSpyware 4.56.1000
Our Download of the Day today is SuperAntiSpyware 4.56.1000.
SUPERAntiSpyware Professional features our highly advanced Real-Time Protection to ensure protection from installation or re-installation of potential threats as you surf the Internet. Used in conjunction with our First Chance Prevention and Registry Protection, your computer is protected from thousands of threats that attempt to infect and infiltrate your system at startup or while shutting down your system.
Advanced Detection and Removal
Detect and Remove Spyware, Adware, Malware, Trojans, Dialers, Worms, KeyLoggers, HiJackers, Parasites, Rootkits, Rogue Security Products and many other types of threats.
Light on System Resources and won't slow down your computer like many other anti-spyware products. Won't conflict with your existing anti-spyware or anti-virus solution!
Real-Time Protection
Real-Time Blocking of threats! Prevent potentially harmful software from installing or re-installing!
First Chance Prevention examines over 50 critical points of your system each time your system starts up and shuts down to eliminate threats before they have a chance to infect and infiltrate your system.
Schedule either Quick, Complete or Custom Scans Daily or Weekly to ensure your computer is free from harmful software.
Continue reading 'Download of the Day: SuperAntiSpyware 4.56.1000' (full post)
iTunes 11 set to receive UI overhaul, deeper iCloud integration
Reports are out that the new version of Apple's most popular media player on Windows and Mac, iTunes 11, will feature a UI overhaul as well as deeper iCloud integration. The new UI will be cleaner than the current one and the iTunes Store will not just be a contained web browser anymore. It will instead be properly integrated into iTunes.
The source of this story, iDownloadBlog says:
It's no secret that iTunes is due for a UI upgrade, and this should come true with the release of iTunes 11. A reliable source of ours has stated that iTunes 11, the next major update to iTunes, will be revamped from the ground up.
The basic layout of the iTunes UI hasn't changed since the first version. This new update will have a completely different UI and better iCloud integration.
From what we're hearing, the UI would be much more cleaner and "slick." iCloud is also going to be more closely integrated with iTunes. Rather than the iTunes Store being essentially a web browser, the Store will actually be integrated into the entire app- much like Spotify is currently.
Continue reading 'iTunes 11 set to receive UI overhaul, deeper iCloud integration' (full post)
Download of the Day: Skype 126.96.36.199
Our Download of the Day today is Skype 126.96.36.199.
Skype is software for calling other people on their computers or phones. Download Skype and start calling for free all over the world.
The calls have excellent sound quality and are highly secure with end-to-end encryption. You don't even need to configure your firewall or router or any other networking gear.
Additionally it doesn't just work on Windows. Skype is also for Mac OS X, Linux and PDAs using Pocket PC, with a native look and feel for each platform. Talking, sending instant messages or even file transfers work between different platforms like a charm.
Skype calling - Skype has all the features of an ordinary phone so it's even easier to manage your calls.
Video calling - see who you are talking to at the same time as speaking to them.
Add Skype and SkypeOut contacts - Add contacts who use Skype and those who use ordinary phones so you can call more people.
Organising groups - group contacts under certain names and share them with your contacts so they can talk to them too.
Basic chat and emoticons - when it's not convenient to call, chat or Instant Message (IM) your contacts.
Group chat - for when it's easier to chat or Instant Message (IM) all your friends at once.
Profile settings - change how you appear to the world and let people know a bit about you.
Continue reading 'Download of the Day: Skype 18.104.22.168' (full post)
Skype releases official 5.5 Update with Facebook integration
Based on user feedback from its June beta release, Skype has now rolled out the final 5.5 build of its software which is available for download immediately.
Skype 5.5 adds deeper Facebook integration in that you can view which of your FB friends are online from it directly as well as being able to instant message them from the new 'Facebook Contacts' tab. The ability to view and update your Facebook status is also possible as well as being able to view and 'like' posts from your wall directly from Skype Home.
Continue reading 'Skype releases official 5.5 Update with Facebook integration' (full post)
NVIDIA 280.19 Beta Driver brings a ton of fixes
A new beta driver for NVIDIA cards has been made available over at GeForce.com today in the R280.19s. It promises a ton of fixes along with new and updated 3D Vision profiles as well as a couple new features.
Furthermore, while it isn't mentioned in the release notes, these drivers are recommended for testing the BattleField 3 Alpha release as they are said to address a number of in-game glitches seen in previous driver releases while helping in the performance dept.
If you happen to be running an SLI rig in conjunction with a 3D Vision kit, these drivers are also recommended to enable 3DVisionLive.com and YouTube 3D video support. On that note, the 280.19s will also give you the ability to enable Window mode in the most recent version of the 3D Vision player.
For a complete rundown on the release notes, head over to this page on GeForce.com folks.
Download of the Day: Google Chrome 14.0.835.2 Beta
Our Download of the Day today is Google Chrome 14.0.835.2 Beta.
Google Chrome is a browser that combines a minimal design with sophisticated technology to make the web faster, safer, and easier.
One box for everything
Type in the address bar and get suggestions for both search and web pages.
Thumbnails of your top sites
Access your favorite pages instantly with lightning speed from any new tab.
Incognito mode
Don't want pages you visit to show up in your web history? Choose incognito mode for private browsing.
Safe browsing
Google Chrome warns you if you're about to visit a suspected phishing, malware or otherwise unsafe website.
For information about alpha and developer builds, check out the Chrome dev channel here.
Continue reading 'Download of the Day: Google Chrome 14.0.835.2 Beta' (full post)
AMD releases Catalyst 11.7 and 11.8 Preview drivers
Just before the end of the month and in keeping with AMD's new Catalyst driver every month thing, we get word of Catalyst 11.7 as well as a bonus driver Catalyst 11.8 preview.
As you would expect, there are a long list of resolved issues.
All issues experienced with mouse cursor lag have been resolved
Log event (Event ID 62464) issues when playing video content have been resolved
Resolves system hangs seen in the AMD Catalyst 11.6 driver on specific HDMI and DP displays
Bluray playback using PowerDVD 10 under High Performance mode no longer randomly displays a blank screen.
Some Divx format files no longer display video corruption using WinDVD.
AMD SteadyVideo is now applied to Home Video clips using WinDVD 10.
Chequerboard corruption is no longer displayed intermittently when playing DirectX 10 titles in a Crossfire configuration and Eyefinity enabled.
Shogun II now renders the cinematics correctly when run in various Eyefinity configurations.
Video playback now works correctly when Hardware acceleration is enabled with VLC Player version 1.1.9.
Crossfire now functions correctly when playing Hamilton's Great Adventure.
PowerDVD now correctly handles 3D Bluray content.
Portal 2 no longer displays flickering on water surface textures with Medium and Low Shader detail settings.
And in the 11.8 preview driver you can look forward to the following...
Continue reading 'AMD releases Catalyst 11.7 and 11.8 Preview drivers' (full post)


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Tickets to La Scala and Other Theaters in Milan
Teatro alla Scala
Teatro alla ScalaThe world's most famous opera house. Founded in 1776 to replace a previous theatre destroyed by fire, La Scala was designed by the great neoclassical architect Giuseppe Piermarini and opened on August 3, 1778 with Antonio Salieri's opera "Europa Riconosciuta." In 1839 the first opera by Giuseppe Verdi (1813-1901) was performed. He soon became the composer whose name is linked more than any other with the history of La Scala. Year after year, visitors come to La Scala to experience not only the superb performances onstage, but also the exquisite atmosphere of Milan's musical jewel.
Serate Musicali
Serate MusicaliFor nearly 40 years, Serate Musicali has been winning over the Milanese public with its high quality programs and world-class artists. Each season brings in stars of the international scene, like Gil Shaham, Andras Schiff, and Antonio Pappano. In addition, Serate Musicali also plays host to new discoveries, of which some have moved on to become international stars themselves, like Hilary Hahn. Many performances take place at the 'Sala Verdi', renowned throughout Europe for the quality of its acoustics. The 2013 season includes an homage to Debussy and Wagner, Bach and Brahms cycles, space for Schumann and Mendelssohn, and three centuries worth of 'Seasons', from Vivaldi to Glass. Enjoy everything from chamber music to symphonies. A great variety with great musical quality!
Auditorium di Milano
Auditorium di MilanoOpened in 1999, the Auditorium di Milano was created by restoring the old Cinema Teatro. The structure dates back to 1939 and had lain idle for many years. The main hall of the Auditorium is now the home to one of Italyâs important symphonic ensembles - the Orchestra Sinfonica di Milano Giuseppe Verdi. Under the guidance of conductor Riccardo Chailly, the Orchestra is a highly flexible and versatile group, boasting a repertoire that ranges from Bach to the main composers of nineteenth-century symphonic music and creating new programs combining classical music with more unusual offerings.
From $34.00


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NBA Playoffs: Heat/Bulls Game 1 the most-viewed basketball game in cable history
May 16, 2011, 6:04 PM EDT
In case you haven't figured it out by now, when the Heat play, people watch. Maybe they're watching to see them win, maybe they're watching out of curiosity, or maybe they're watching in hopes that they'll get their butts kicked like they did on Sunday night.
Either way, people have been watching, and the Heat have been setting huge television ratings all year long. Combining the Heat with the Bulls, who had the greatest NBA dynasty of the modern era and have some of the most passionate sports fans in America, led to some record ratings on Sunday night:
The Chicago Bulls were even more dominant on TV than they were on the court Sunday night against the Miami Heat in the opener of NBA Eastern Conference finals playoff series.
National numbers released Monday showed the Bulls' '103-82 rout on TNT to be the most-viewed basketball game in cable history, with more than 11.109 million total viewers and a 6.2 overall household rating. The previous record was the 10.829 million viewers for the 2003 NBA All-Star Game, which was Michael Jordan's final appearance in the mid-season exhibition.
Ratings were especially good in Chicago, where the game drew a monster 24.3 average rating, just edging out the 23.3 rating the game drew in Miami.
- andrejohnsonforpresident - May 16, 2011 at 8:42 PM
Tuned in for heat vs bulls?? I watch the tnt games specifically for Charles Barkley. That guy is a trip
- purdueman - May 16, 2011 at 10:49 PM
I agree with you in that Barkley is hands down THE most entertaining NBA analyst/broadcaster, but unfortunately Sir Charles was equally AWFUL during the NCAA Tournament this year… he came off as a duck totally out of water, not knowing anything about the teams or the players.
The networks hopefully will realize this and not use Sir Charles again on NCAA Tournament broadcasts; I could have done better and I don't follow NCAA basketball much until the tournament starts (especially now with so many "one and doners".
- purdueman - May 16, 2011 at 10:52 PM
I loved Barkley's comment last night that "Jokim Noah is the only center in the league who can guard anyone, regardless of position." It's true too; did you see Noah lead a fast break dribbling almost the length of the floor last night? There isn't a current NBA center other than Noah that can do that.
The Bulls defensive "length" (the latest hot new sports term), and depth in the front court give the Heat fits and they have no answer for that. That and totally dominating the boards because of it are why I think that the Bulls will take the Heat out in six.
- hnirobert3 - May 17, 2011 at 9:03 AM
Nene has good ball handling skills as well. Moving on.
- philtration - May 17, 2011 at 9:06 PM
Noah is a lot stronger then he used to be as well.
He got pushed around by the Celtics in the 2009 playoffs and he knew it so he has worked really hard on that side of his game.
I love the Bulls front court.
- southbeachtalent - May 17, 2011 at 4:34 PM
The HEATLES!!
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Saundra Santiago (Broadway World)
"One Life To Live" actress Saundra Santiago (Carlotta Vega) will be starring as Beatriz, along with former "Guiding Light" actor Robert Bogue (ex-A.C. Mallet) who will play Mauricio, in the new production "Manipulation." Written by Victoria E. Calderon, the play surrounds a woman named Christina who finds a way to cut ties to those always bringing her down.
Though the actors are appearing in previews for their new play now, it doesn't officially open until June 16 at the Cherry Lane Theatre at 38 Commerce Street in New York City, New York. Please call 1-212-239-6200 to order your tickets today.
If you'd like to know where some other actors will be appearing check out Soap Opera Stars To Attend The 19th Annual Young Playwrights Festival.
Join us on Twitter @soapoperafan and Facebook. Come tweet and Facebook with us about "One Life To Live," all the other soap operas, "Glee," "Grey's Anatomy" and "Vampire Diaries!"


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FDIC Insured Money Market Account Sweep
This money market account is governed by Regulation D and FDIC insured. There is no minimum balance requirement to earn interest. Interest is calculated daily and paid monthly.
Your monthly statement is available either online through Business Online or our automated daily fax service.
No minimum required to open account. FDIC insured up to applicable limits. Current rate and annual percentage yield available upon request. Rates subject to change without notice. Interest is computed daily at a daily periodic rate of 1/365th (1/366th in leap year) of the annual rate of each day. Interest will be compounded monthly and paid at the end of each statement cycle. Fees may reduce earnings.


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AliveCor's Mobile Heart Monitor Evaluate Heart Health Easily, Quickly, Remotely
AliveCor Inc.'s mobile Heart Monitor is a clinical-quality, low-cost mobile electrocardiogram (ECG) heart monitor, compatible with the iPhone 4 and 4S, that enables doctors to evaluate patient heart health easily, quickly and remotely.
Clinical studies of the device indicate that a high-quality single-channel ECG can be rapidly and simply recorded using an iPhone with the AliveCor application and device, to accurately screen for cardiac arrhythmias, including atrial fibrillation. AliveCor's Heart Monitor is initially intended for use by licensed medical professionals to record, display, store, transfer and evaluate single-channel ECG rhythms.
The rhythm strips can be of any duration, and are stored on the iPhone and securely in the cloud for later analysis, sharing and printing through AliveCor's secure website. The ECG data is sent wirelessly from the Heart Monitor via AliveCor's low-power, proprietary communication protocol, and requires no pairing between the iPhone and the device.
The device incorporates electrodes into a case that snaps onto the back of an iPhone 4 or 4S. The Heart Monitor is used by launching the corresponding AliveECG app on the iPhone, holding the device in a relaxed state, and pressing fingers from each hand to each of the two appropriate electrodes on the device. The device can also be used to obtain an ECG by placing it on the chest.
AliveCor's Heart Monitor is available for pre-sale to medical professionals in the United States through the company's website at a cost of $199. AliveCor plans to begin selling the Heart Monitor in Europe in early 2013.
The monitor received U.S. Food and Drug Administration (FDA) approval and CE mark in December 2012.
For more information: www.alivecor.com


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The Siem Reap HostelSiem Reap, Cambodia
I didn't have to much time do enjoy the place, but I have to recognize that the hostel have excellents conditions. They offer services in the hostel not to much commons , the staff is very helpfull, and the atmosphere invited to met people. I was sorry for not having stayed longer to enjoy all that the hostel offered.
Me Mates VillaPhnom Penh, Cambodia
I have to say that the staff was really incredible to resolve my problems. In other place I tried to book a place in overnight bus to siem Reap (I just had 2 days and half in Cambodia) and the companies said to me that didn't exist any, already. So I booked to this hostel one niht, against what I was planned. But when I arrived their, they made everything to book for me in that night, place in the bus. They could and I was really happy. THANK YOU!
Hoa My I HotelHoi An, Vietnam
In Hoi An, there are no tradition of hostels. So the Hoa My Hostel is an Hotel, and as that, it's not the best place to meet people. But I think that is general in Hoi An. Although, the breakfast, the facilities, the cleanness are really good, and the staff helpful!
Pai Circus School & Backpacker ResortPai, Thailand
I think that Pai Circus School is one of the places with greatest potential, that I have been. The chill area, the atmosphere and the view are awesome! Good to the sunrise, to the sunset, to the all parts of the day! But... The mixed room (that was my case) wasn't so good, needs improvement, and the toilets too. And for people who stays in this room, the toilet is really far, and don't make sense.
Aoi Garden HomeChiang Mai, Thailand
I almost don't have words to describe my stay here. The rooms, the toilets, the chill area, the atmosphere, the staff, were all incredible! They are very helpful, since borrow me trekking shoes, let me take shower before my departure (and I wasn't in the hostel already), and other things that reveal the highest quality of the service. Congratulations!
Niras Bankoc Cultural HostelBangkok, Thailand
The place was really good, the rooms and toilet very clean and the staff was good too. It's close from the "night street". It was a place when I met a lot of amazing people, so it's a excellent place for who is travelling alone as me!I


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