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I know I can't believe it either- the summer has quite literally, not to sound too cliche' flown by-we blinked one day and the air outside felt thick, we dripped with sweat and my kids used their Wham-O slip n slide until they almost burned a whole through the plastic. And then today- the air, it just had that fall feeling to it. Cold, brisk and dare I say it- just a bit of gloom. I know there are still two weeks left until the unofficial end to summer but in my house, my little girl who loves to have all her ducks in a row has been amassing school supplies since August 1st.School supplies
My daughter is all about personalization and standing out from the pack- which is why she kind of went gaga for Office Max's new back-to-school collection which features a range of designs from butterflies to skulls to heart shapes, that will let your little brainiac show off her savvy style all the way into the classroom. And parents (like me) love their budget-friendliness and the fact that these products are available ALL year (so even if you're doing really last minute shopping) you'll be in luck and have plenty of product to choose from. Ultimately, their products enable students to express their personalities and interests while doing their best work.
And while other retailers carry a small stock of back-to-school supplies solely during the summer, Office Max's collections offer a large selection of creative, unique supplies for students and teachers year-round.
And what about the clothes?
Being that my daughter eats, breathes and lives Selena Gomez, the clothes shopping was a breeze for me... (in this picture she's wearing a signature dress from the Kmart Selena Gomez line) This year Kmart offers tweens and teens everything from peacoats, leggings and skinny jeans, to backpacks and yes even adorable accessories like candy-colored staplers. Not only do they still have their popular Route 66 brand, but they've recently launched their Selena Gomez "Dream Out Loud" clothing line which consists of knit leggings, graphic/distressed tees, skinny jeans, denim mini skirts, ruffle Henley tops, plaid woven tunics, layered dresses, flutter sleeve tops and sequin detailed accessories. They've also got a super-cute line of clothing from Rebecca Bonbon, a Japanese character designed by the creator of Hello Kitty, includes outerwear, headwear, accessories and bags. And Audrina Patridge,who is the newest face of BONGO, brings her rocker style to her Kmart line with; black leggings, novelty graphic tees, loop zip-down sweater vest, tie-dye tops with studded detailing, grey lace print denim. Parents will especially appreciate their layaway plan.


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This morning, Ubisoft unveiled Ghost Recon Future Warrior and announced it is scaling back development of all-new IPs to focus on more installments in existing properties. Its motivation to do the latter was laid bare, when it also announced that Assassin's Creed II has shipped 8 million units worldwide.
The M-for-Mature game was released November 17 for the PlayStation 3 and Xbox 360 in North America and shipped in Europe and elsewhere two days later. The PC version will arrive this March along with Ubisoft's controversial new online-based DRM system.
The announcement came less than a month after the company announced Assassin's Creed II had achieved worldwide sales of 6 million units. Having sold 1.6 million units globally during its first week, the game received sterling reviews. It follows a new protagonist, Ezio, who teams up with the likes of Leonardo da Vinci during the Medici-run Renaissance era in Italy.
In January, Ubisoft said it expected Assassin's Creed II to sell some 9 million units by the end of its current fiscal year in March. To help sustain interest in the game, the company is readying a new expansion, which will introduce multiplayer into the series for the first time. The expansion will arrive during Ubisoft's current fiscal year, which beings April 1, 2010, and its single-player component picks up where Assassin's Creed II left off.
Speaking today in a conference call with reporters, Ubisoft CEO Yves Guillemot said the expansion "marks the return of the legendary Ezio. But this time, he will strike directly at the heart of the Templar Order in Rome. In addition to this full new adventure, players will be able to challenge their friends in a very innovative assassination multiplayer."

subset: commoncrawl


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What's My California Delicious? Ziplining in Sonoma, California
Staff videographer Jack tells us about a recent ziplining adventure in Sonoma County, California…. This place was amazing!!! Sonoma Canopy Tours was the experience of a…Read article
5th Annual Spirit & Soul Festival and Fundraiser in Richmond, California- Sept 21st 2013
Amanda Elliott, Executive Director of the Richmond Main Street Initiative, tells us about an lively and free event in historic downtown Richmond, California on Sept. 21st, 2013 and…Read article
The Point Richmond Music Festival- September 13th, 2013
Both of the fantastic performers, Orquesta Dharma and Viento y Marea, who played in the penultimate Point Richmond Summer Concert brought a Latin Jazz vibe to…Read article
What's My California Delicious? Beach vacation to North Lake Tahoe, California
Marketing assistant Maya shares her experiences taking her mother on a trip to the shores of North Lake Tahoe, California… My mother was visiting from out…Read article
Mill Valley Film Festival 36 Sponsor Preview Party
At California Delicious, we think it is important to support local cultural events. We are so excited to announce our official sponsorship of the 36th Annual…Read article
What's My California Delicious? Riding a Hot Air Balloon in Napa Valley
Staff Photographers Joey and Patrick Risberg describe their Hot Air Ballooning Adventure in Napa, California and share some photos… At 5am we left Marin and drove up the 101 towards our…Read article
What's My California Delicious? Fly-Fishing in North Lake Tahoe, California
Guest Blogger and California resident Janice Avalone tells us about her new found passion for fly fishing…. Recently on vacation in Tahoe with a close girlfriend, I was…Read article
The Point Richmond Music Festival- August 9th, 2013
The 3rd Concert in the Point Richmond Music Series featured the talented Rusty String Express and dynamic Jenny Kerr . First things first. It's Friday…Read article
35th Annual Gilroy Garlic Festival- 26, 27 & 28th July 2013
Marketing assistant Maya tells us about her first time to Gilroy, California for the 35th Annual Garlic Festival… Welcome to Gilroy, California. Nestled in the Central…Read article
The Point Richmond Music Festival- July 12th, 2013
The 2nd installment of the Point Richmond Summer Concert Series was July 12th and featured two great music acts: Twice as Good and Willie. G… The…Read article


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LAKE CHARLES, La.
LAFAYETTE, La. (AP) Augustine Rubit scored 26 points to help South Alabama beat Louisiana-Lafayette 91-89 Thursday night in double overtime.
NEW ORLEANS (AP) Konner Tucker scored 14 points and Texas-El Paso defeated Tulane 66-57 Wednesday night in the Conference USA opener for both teams.
NEW ORLEANS (AP) Roger Mason scored 15 of his 17 points in the fourth quarter to rally the New Orleans Hornets to an 88-79 victory over the Houston Rockets on Wednesday night.
GRAMBLING, La. (AP) Anthony Nieves scored 18 points and Marquiz Baker 17 to lead Alcorn State to an 80-46 routing of Grambling State Tuesday night in Southwestern Athletic Conference action.


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Three Law Faculty Members Receive University Merit Awards
July 18, 2011
Carmen Franklin 3L was the featured student speaker at the OneJustice benefit reception and auction "Opening Doors to Justice"; approximately 350 people attended the July 13 event.
With the assistance of law students and lawyers, OneJustice works with low-income individuals in need of legal services to gain basic civil rights and to meet essential needs such as food and housing.
USF law students regularly participate in OneJustice programs that help underserved communities. The University of San Francisco School of Law is one of three schools involved in the organization's Law Student Pro Bono Project, which matches law students with nonprofits and court-based programs that need assistance. Students also provide legal support to rural communities in Justice Bus Service Learning Trips. Under attorney supervision, students conduct legal intake interviews, draft legal documents, and educate clients.
"I worked with passionate and dedicated people and I developed a first-hand understanding of the critical work that is being done with legal aid organizations in California," said Franklin, who has taken part in seven Justice Bus Service Learning Trips.
"I know that because of the Justice Bus trips and my experience with OneJustice I will be a better lawyer. No matter where I end up practicing law I am fully committed to using my legal skills to help people change their lives for the better," she said. "The Justice Bus trips have taught me that I am able to provide options to individuals that they did not know they have. I can empower them to improve their own lives by using the legal system to solve their problems."
California Supreme Court Chief Justice Tani Cantil-Sakauye was in attendance to present the Jack London Public Service Award to Peter Carson and recognize Ana de Alba and First Republic Bank. Carson is co-chair of Bingham McCutchen LLP's global pro bono practice and has supported pro bono efforts throughout his career. De Alba has worked to expand legal services in the Central Valley and to make pro bono service mandatory at Lang, Richert & Patch, where she is an attorney. First Republic Bank, an Interest on Lawyers' Trust Account (IOLTA) Leadership Bank, pays a higher interest rate than required by law on IOLTA accounts resulting in increased funding to nonprofit legal aid organizations.
"I'm proud to be with so many of you here today doing extraordinary work under remarkable circumstances," Cantil-Sakauye said. "I want you to know that from the highest level in all the courts your work is noticed and appreciated and does not go unheeded."
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Since 1947
(based on 4 reviews)
Ratings Distribution
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(2 of 2 customers found this review helpful)
Excellent product
By El
from San Diego
About Me Midrange Shopper
Comments about Personalized Rosewood Case Double:
This is a fine product as is. I cannot believe other customers who are disappointed that there were no pens included. ! It is a pencil CASE.Looks very good on my desk.
Bottom LineYes, I would recommend this to a friend
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(1 of 1 customers found this review helpful)
Not what you think. I thougth the pens
By billy jack
from marble fgalls, texas
as stated before, does not come with pens as shown. Makes one poor present as is
Bottom LineNo, I would not recommend this to a friend
The Picture is Deceptive
By RAZ
from Burlington, WI
About Me Budget Shopper
Wow--was I glad I read the one review of this product before I pressed the Order button for the four "cases" I would have purchased. Showing the pens in the case is kind of deceptive--but being a somewhat "wise" consumer, I should have read everything. I have seen these cases with pens for about the same price--that is why I thought it was a nice deal. With shipping and handling costs--it usually averages out anyway. I like reading reviews!!!!
(5 of 5 customers found this review helpful)
pens not in case even though shown
By Sam
from Eldon,Mo.
I ordered this case thinking it had the pens included.Imagine how I felt when my boss opened up this very pretty rosewood case only to find it empty.


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Award-winning photographer Jim Sugar shows how to shoot outdoors during twilight, balancing strobe output with natural light.
Award-winning photographer Jim Sugar shows how to shoot a portrait with a dramatic look and feel, using a variety of inexpensive lighting tools.
Demonstrates the use of off-camera wireless strobes to light a product shot, and provides tips that apply to product shots of all kinds.
"Now you have food photography? It doesn't get any better than that. I now do freelance graphic design for a restaurant and am asked to do their food shots. The timing is so perfect. Thank you." —Alele T.
more from our members »


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Cancer Control Research5R03CA099488-02
Roper, Kimberly D.
DESCRIPTION (provided by applicant): Recent studies have indicated a link between social support provided by support groups and outcome in cancer patients. These support groups not only affect the emotional state of the patient, but they may also change the regulation of stress hormones that influence the immune system. Indeed, some studies suggest patients who attend support groups survive longer. Much of what is known is either anecdotal or poorly documented scientifically. Few scientific studies have followed in a systematic manner the behavioral and hormonal responses of participants in these support groups. This study will investigate the acute and long-term effects of an intense weekend psychosocial workshop on stress hormone levels and several psychosocial variables including mood, quality of life, stress and coping. In the proposed study, 30 breast cancer patients will be recruited from a local breast cancer center and randomly assigned to treatment or control group. Participants will complete measures of coping, mood, stress and quality of life upon entry, immediately after the workshop, and at one and six months and one-year follow-ups. Participants will provide saliva samples for assessment of stress hormones in conjunction with psychological testing. Half of the participants will participate in a Qualife Breast Cancer Weekend Wellness workshop consisting of approximately 20 hours of experiential education to improve wellness and coping. After the six-month assessment, the remaining participants will receive the same treatment. The primary hypothesis is that the workshop will normalize regulation of stress hormones, decrease stress, and improve mood, coping, and quality of life.


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China unveils plans for Space Station
BEIJING – Authorities in charge of the manned space program unveiled plans on Monday to build a 60-ton space station, made up of three capsules, and develop a cargo spaceship to transport supplies.
The China Manned Space Engineering Office said… Continue reading
Pilot crashes plane into tax-office on purpose
Austin (Texas)
Pilot Joseph Andrew Stack (53) crashed his small Cirrus plane into the Austin Tax-Office on purpose around 10:00 am local time.
The crash was followed by an explosion and a fire, people were hanging out of the windows… Continue reading
Saab opens office in India
Saab's office in New Delhi was officially opened on January 27. The office will support Saab in its efforts to market products for defence and civil security in the Indian market.
The office in New Delhi was inaugurated by Anders… Continue reading


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Wednesday, September 4, 2013
St. Stephen native Bakari Prioleau became a distinguished graduate of the U.S. Air Force's Officer Training School at Maxwell AFB, AL on Aug. 6.
Second Lieutenant Prioleau was one of the first Air National Guardsmen to ever complete the program, earning high regards during his training.
As an 11-year veteran, Lieutenant Prioleau has completed multiple tours of duty in the Middle East to support key initiatives as well as Operation Iraqi Freedom and Operation Enduring Freedom in Iraq and Afghanistan.
Lieutenant Prioleau is a 2007 graduate of the University of South Carolina. He will report for duty as a Security Forces officer at McEntire Joint National Guard Base in Eastover, SC.
The Berkeley Independent is pleased to offer readers the enhanced ability to comment on stories. We expect our readers to engage in lively, yet civil discourse. We do not edit user submitted statements and we cannot promise that readers will not occasionally find offensive or inaccurate comments posted in the comments area. Responsibility for the statements posted lies with the person submitting the comment, not The Berkeley Independent.
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Face Atelier Revenge Lipstick Review, Photos, Swatches
The Sultry Season: Face Atelier Revenge Lipstick
Face Atelier Revenge Lipstick ($22.00 for 0.14 oz.) is a deepened red with subtle brown undertones running through it. It's extremely pigmented–I only needed one swipe to get opaque color. There is enough creaminess in the formula to apply the color evenly and easily, but it's not so creamy that it migrates or pools in places. Face Atelier's lipsticks are scent- and taste-free, too. This shade wore for quite a stretch of time at six hours, and it left behind a soft stain as it faded away.
Is this the right red for you? Would you wear it?
The Sultry Season is a series of posts featuring deep, rich shades of brown, berry, plum, and wine lipsticks and lipglosses — just right for autumn — that runs through October 2010.
See photos and swatches…
Product & Review FAQ
Where can I purchase Revenge? How much is it?
Face Atelier, $22.
Is it limited edition?
Any dupes?
It's a lighter, glossier version of Illamasqua Growl and MAC Media, and slightly darker than MAC Dark Side.
Discussion and debate are highly encouraged, and we expect community members to participate respectfully. When asking a question, please check the FAQ section (above) for information about purchasing, price, dupes, and the like. If you have general feedback or need technical support, please contact us.
Comments that include advertisements, self-promotion, insults, etc. may be in violation of our comment policy and subject to deletion. Please see our comment policy for more information.


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Oral history interview with Melvin Edwards, 1968 Aug. 10
Edwards, Melvin
b. 1937
Active in New York, N.Y.
Sound recording: 1 sound tape reel ; 7 in.
Transcript: 72 p.
Collection Summary: Interview of Melvin Edwards conducted 1968 Aug. 10, by Henri Ghent, for the Archives of American Art.
Biographical/Historical Note: Melvin Edwards (1937-) is a sculptor in New York, N.Y.
This interview is part of the Archives of American Art Oral History Program, started in 1958 to document the history of the visual arts in the United States, primarily through interviews with artists, historians, dealers, critics and others.


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Amy Burrell
Introduction to Dance Studies, Dance Production, Senior Seminar
Amy holds her undergraduate degree in Ballet and Psychology from Indiana University and received an MFA in Fine Arts from IU in 2011. Her studies focused on non-verbal communication and crossed over into costume design, performance, installations and movement. Amy Burrell is currently an adjunct lecturer in Indiana University's Contemporary Dance Program. She has been involved with the dance department since 2007 when she began designing costumes for performances. Amy is an experienced teacher in studio practices and over the years has taught dance production, intro to dance studies, ballet, modern dance, movement for actors, studio art and aerial silks.
She has worked as both a dancer and designer in Austin TX, New York City, Brazil, Germany and Cleveland OH. She is a practicing massage therapist and integrates bodywork and somatic practices into her courses.
Her performance-based practices include site specific, gallery installations, production and design for dance, interactive installations and video performance. Amy has received the Fran Snygg Art Award and a graduate fellowship from the Hope School of Fine Arts. Recent collaborations include the Indiana University Dance Theaters' Global Perspectives and Empathic Movement with Leslie Sharpe.
IU Contemporary Dance | Department of Theatre, Drama, and Contemporary Dance | Lee Norvelle Center, 275 N. Jordan Ave, Bloomington, IN 47405 | (812) 855-7020


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- Summer Life in Whitley County
COLUMBIA CITY ŌĆö Columbia City is home to a new eatery offering a taste of southern-style pit barbecue BrunoŌĆÖs BBQ. Tucked behind the Marathon full-service station located at 501 N. Line St., BrunoŌĆÖs BBQ has the look and feel of a southern roadside barbecue restaurant.
To read the rest of this story, see the Aug. 13 issue of The Post and Mail. Don't have a subscription? Call (260) 244-5153 or subscribe to our e-edition. For breaking news, sports updates and additional coverage, bookmark the homepage and find us on facebook and twitter.


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New program director for mechatronics
This summer, Dr. Chan Ham, an assistant professor of mechatronics engineering since Spring 2010, was named director of the Mechatronics Engineering program.
Dr. Ham holds master's and doctoral degrees in electrical and computer engineering from the University of Central Florida (UCF) and received his undergraduate degree in electronic engineering from Dongguk University, Korea. Before his arrival at SPSU, he was a faculty member in the UCF College of Engineering and Computer Science and simultaneously served as a scholar with the Florida Space Institute.
This summer, Dr. Ham collaborated with NASA engineer Dr. Felix Soto Toro, to deliver a keynote address during the 15th World Multi-Conference on Systemics, Cybernetics and Informatics in Orlando, Fla.
Their address was titled "Development of an Electronic Ground Support System for NASA's Payload Transfer Operations: A Case Study of a Multidisciplinary Work in the Space Shuttle Program." Dr. Ham also chaired a conference session on the "Cooperative Analysis and Design of Multidisciplinary Systems."


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" Brand: F&F / Type: Flip Flops "
I do love the range of absolute bargain shoes you can pick up from supermarkets these days! This particular pair were a spur of the moment purchase in Tesco recently where I paid £6 for these very pretty and quite fashionable beaded flip flops.
Although they are flip-flops in style they actually have a much wider top piece than a standard pair where you usually only have two, fairly thin bits of material. The triangular shaped top section sits over the top of your foot and this is where all the pretty beading is. The design works very well and I have had no issues with rubbing in this pair.
The sizes are not individual in this range and the pair I bought are a UK 5-6. I am usually a size 6 but these fit absolutely fine, the rough sizing does not seem to be an issue here. The toe bar is a sturdy plastic type of substance but it does not rub either so all in all this is a very comfortable pair of flip flips at a fantastic price.
My only gripe with this pair is that after a month or so of wearing I notice that a couple of the beads are coming away already - but these could easily be glued back into place, I guess what can you expect at this sort of price!?
In any event, these are pretty, comfortable and easy to wear and for the price I paid I still think they are a summer essential.
I like to wear flip-flops in the summer and Tesco have some really nice ones at good prices. I recently bought 4 pairs from there and got all four pairs for approximately just £20.00. This review is about the Sequin Embellished Flip-flops which were the most expensive at £6.00. They are available in black or silver. I bought the black ones.
The sequined embellished flip-flops are flat and have a nice soft sole of about 1cm. They are V shaped flip-flops but the straps are a bit wider than the others I bought. They have a round material toe post which, in the shop, was covered with a plastic cover. I assume this is for hygiene reasons and to keep the toe post clean. The straps come from the toe post as with most flip-flops but as I mentioned they are slightly wider and have a triangle shaped piece which sits on the top of the foot.
The straps are made from a sturdy cloth material and are covered with shiny black sequins and beads. They are very pretty and sparkle as the light catches them. The straps go down to nearly the heel of the flip-flop where they fix into sole. There is no lump where the straps are attached and they sit nicely rounded the sides and across the front of the foot.
The sole is plain black with white contrast stitching all around the edge. All the stitching is secure and very neat. Considering the price they are very detailed.
I have since worn the flip-flops and they have proved to be very comfortable. The toe post sits comfortably between my toes and I have experienced no rubbing or chaffing at all. They stay on my feet and the nice soft sole means I don't suffer any aching feet.
They look lovely for an evening out, the sequins and beads makes them a a little bit dressy. Having said that they are perfectly suitable for daytime and something as simple as a trip to the shops.
I am very pleased with these flip-flops from Tesco, I bought a size 5-6 (38-39 euro) and they fit perfectly. I'm usually a 6 and these are fine. I did wonder of the beads and sequins would fall off but so far they have stayed put.
I would whole heartedly recommend these, they are well made and nicely decorated. The price is excellent, as it is with all Tesco flip-flops, and although they will probably only last this year at this price I cannot complain!


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Taiwan Johnson #94
The Latest: Hogs look strong at DE — 5/4/2015
The defensive line looks to be a strength heading into the 2015 season, and it all started in the Class of 2012 when the Razorbacks brought in what could prove to be one of the best groups of defensive ends in school history.[details]


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Methods and apparatus for a memory system using a ring memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains point-to-point bus connections with each of two memory modules; the two modules maintain a third point-to-point bus connection between themselves, such that the three connections together form a ring bus. When data is sent from the controller to a module, half of the data is sent to the module in one direction along the ring and half is sent in the other direction, through the other module. Reverse bus communications from the module to the controller follow the reverse of these paths. This allows the bus to be half the width as it would otherwise be.
In an alternate embodiment, each module contains two banks of memory that are arranged in a second ring bus local to the module. This can double the density of devices mounted on a module, while reducing pin count and simplifying signal routing on the module.
1. A memory system comprising:
a first-tier controller having first and second level-one ports; and
multiple memory units, each having first and second level-one ports, connected with the first-tier controller in a first ring bus, each of the memory units and the first-tier controller capable of transmitting memory signals in a clockwise direction on the first ring bus using the corresponding first level-one port, and in a counterclockwise direction on the first ring bus using the corresponding second level-one port, and wherein each memory unit is capable of retransmitting memory signals received by that unit at one level-one port on the other level-one port.
2. The memory system of
a second-tier controller to connect the memory unit to the first ring bus and transfer memory signals between that memory unit and the first ring bus, the second-tier controller having first and second level-two ports; and
multiple memory subunits, each having first and second level-two ports, connected with the second-tier controller in a second ring bus, wherein each of the memory subunits and the second-tier controller are capable of transmitting memory signals in a clockwise direction on the second ring bus using the corresponding first level-two port, and in a counterclockwise direction on the second ring bus using the corresponding second level-two port, and wherein each memory subunit is capable of retransmitting memory signals received by that subunit at one level-two port on the other level-two port.
3. The memory system of
4. The memory system of
5. The memory system of
6. The memory system of
7. The memory system of
8. The memory system of
9. The memory system of
10. The memory system of
11. The memory system of
12. The memory system of
13. The memory system of
14. The memory system of
15. The memory system of
16. The memory system of
17. The memory system of
18. A memory module comprising:
at least one bank of memory devices;
a module controller to communicate memory signals with the bank of memory devices over a memory module bus, the module controller capable of connecting to a primary memory controller along a ring bus, the module controller comprising an interface circuit to transfer memory signals between the memory module bus and the ring bus,
wherein the module controller is capable of communication with the primary memory controller to send a set of data signals between the two, by sending one portion of the set of data signals in a clockwise direction on the first ring bus and sending the remainder of the set of data signals in a counterclockwise direction on the first ring bus.
19. The memory module of
20. A memory module comprising:
at least two banks of memory devices, each bank having first and second level-two ports;
a module controller, having first and second level-two ports, connected with the memory device banks in a module ring bus, wherein each of the memory device banks and the controller are capable of transmitting memory signals in a clockwise direction on the module ring bus using the corresponding first level-two port, and in a counterclockwise direction on the module ring bus using the corresponding second level-two port, and wherein each memory device bank is capable of retransmitting memory signals received by that bank at one level-two port on the other level-two port.
21. The memory module of
22. The memory module of
23. The memory module of
24. A method of host/memory communication comprising:
transmitting a partial set of memory signals over a clockwise bus path between a first-tier controller and a selected one of a plurality of memory units, wherein the first-tier controller and the plurality of memory units are linked by a first ring memory bus, wherein each of the memory units and the controller are capable of transmitting memory signals in a clockwise direction and in a counterclockwise direction on the bus, and wherein each memory unit is capable of retransmitting memory signals received on the bus along the bus; and
transmitting the remainder of the set of memory signals over a counterclockwise bus path between the controller and the selected memory unit.
25. The method of
26. The method of
27. The method of
28. The method of
when the second-tier controller receives memory signals from one of the memory subunits from a given bus direction on the second ring memory bus, the second-tier controller transferring those memory signals to the first ring memory bus and sending those memory signals to the first-tier controller in a corresponding direction; and
when the second-tier controller receives memory signals, from the first-tier controller and in a given bus direction on the first ring memory bus, that are destined for one of the memory subunits, the second-tier controller transferring those memory signals to the second ring memory bus and sending those memory signals to the appropriate memory subunit in a corresponding direction.
29. The method of
30. The method of
31. The method of
32. The method of
33. The method of
when the second-tier controller transfers memory signals from the narrower of the two buses to the wider of the two, that controller holding a first set of memory signals arriving on the narrower bus until a corresponding second set of memory signals arrives on that bus, and then combining the two sets of memory signals for transfer to the wider bus; and
when the second-tier controller transfers memory signals from the wider of the two buses to the narrower of the two, that controller dividing the set of memory signals into first and second subsets and placing those subsets separately on the narrower bus.
34. The method of
35. A method of connecting multiple memory units in a memory system, the method comprising:
placing a primary memory controller at a root node of a multi-tiered ring bus;
placing each memory unit at a leaf node of the multi-tiered ring bus; and
placing a ring-bus transfer controller at each intermediate node of the multi-tiered ring bus,
wherein the primary memory controller and each ring-bus transfer controller are capable of communicating a set of data signals between themselves by sending one portion of the set of data signals in a clockwise direction on the first tier of the ring bus and sending the remainder of the set of data signals in a counterclockwise direction on the first tier of the ring bus.
36. The method of
This present invention relates generally to digital memory devices and systems, and more particularly to bus architectures and bus communication methods for such devices and systems.
Microprocessors, digital signal processors, video devices, and many other types of digital data processing devices rely on an attached high-speed memory system to hold data and/or processor instructions needed by the processing device. As these processing devices become faster and more powerful, the increased demands placed on them generally translates to a need for larger and faster attached memory systems.
FIG. 1 depicts a typical memory system configuration. One or more memory devices 26A, 26B, 26C interface with a memory controller 20 through memory bus 22. A host (e.g., a central processing unit (CPU), not shown) also connects to memory controller 20 through a front-side bus FSB. The memory devices hold data in arrays of addressable memory cells. Memory controller 20 controls the exchange of data between the host and the memory storage devices.
Memory bus 22 carries memory signals on a collection of signal lines. Memory signals fall generally into one of several categories including clock and control signals, address signals, command signals, and data signals. Data signals carry the actual data that will be stored in, or retrieved from, a memory device. Address signals specify the location within a memory device where data is to be read from or written to, and may also select which of several memory devices is to be accessed. Command signals instruct a memory device as to what type of operation is to be performed, e.g., read, write, refresh, and possibly as to which of several access modes (such as a burst mode) should be used for a data transfer. Clock and control signals synchronize the other signals passing between controller 20 and the memory devices. Although memory bus 22 may use a separate signal line for each memory signal (e.g., 32 address lines to transfer a 32-bit-wide address in one clock cycle and 32 data lines to transfer a 32-bit-wide data word in one clock cycle), various schemes also exist to reuse one or more signal lines for different memory signals during different clock cycles of a memory transaction.
In the configuration shown in FIG. 1, memory bus 22 is a multi-drop memory bus. In other words, bus 22 is arranged with a backbone of signal lines. A signal line stub, or "drop", connects each of memory devices 26A, 26B, 26C to the backbone. Typically, memory bus 22 will comprise a collection of leads routed on a printed circuit board 21 known as the "main board" or "motherboard". Memory controller 20 mounts to motherboard 21 and connects to one end of the leads comprising memory bus 22. Each drop of memory bus 22 connects to an electrical terminator, or socket. A typical main board contains multiple memory sockets, e.g., the three sockets 28A, 28B, and 28C shown in FIG. 1.
Memory is added to the memory system by inserting memory modules (e.g., 24A, 24B, 24C) into one or more of the sockets. One popular type of memory module is a Dual In-line Memory Module, or DIMM. The DIMM is a rectangular low-profile circuit board that has electrical contact points arranged on both sides along one long edge. The contact points form electrical connections to the main board's memory bus when the DIMM is inserted into a DIMM memory socket.
A DIMM generally has multiple individual memory devices mounted to it. The devices all work in parallel to perform memory functions. For instance, a DIMM may have eight memory devices, each of which receives the same memory address from the controller. If the size of a data word is 32 bits, each of the memory devices is responsible for four bits of the data word that is placed on the memory bus.
The invention may be best understood by reading the disclosure with reference to the drawing, wherein:
FIG. 1 illustrates a prior art memory system;
FIG. 2 illustrates a memory system using a point-to-point memory bus architecture;
FIG. 3 illustrates a memory system using a point-to-point ring memory bus architecture;
FIG. 4 illustrates a memory system using a local ring memory bus architecture on each memory module;
FIG. 5 illustrates a multi-tier ring bus memory system using a point-to-point ring memory bus between memory modules and a local ring memory bus architecture on each memory module;
FIG. 6 demonstrates how multiple memory devices can be arranged in a hierarchical binary tree of ring buses;
FIG. 7 demonstrates how the arrangement of FIG. 6 can be truncated using continuity devices;
FIG. 8 shows an exemplary board layout for connecting up to four memory modules in a dual-ring-bus configuration;
FIG. 9 depicts a ring memory bus memory system using one group of terminology;
FIG. 10 depicts the memory system of FIG. 9 expanded to two tiers;
FIGS. 11 and 12 contain timing diagrams for operating the memory system of FIG. 10;
FIGS. 13A and 13B show a dual-tier ring bus memory module from two views;
FIG. 14 shows a side view of a dual-tier ring bus memory module that uses different bus widths for the two rings; and
FIG. 15 shows a block diagram for a data redrive/transfer circuit useful with the module of FIG. 14.
It is recognized herein that the multi-drop memory bus architecture has several characteristics that limit its expansion to greater numbers of memory devices and/or faster bus speeds. First, the stubbed bus architecture can create undesirable reflections on the signal lines at high frequency. Overall bus length can also cause timing problems that limit operational frequency, as at high frequency a significant skew will be observed between when a memory signal arrives at a closer device vs. when that signal arrives at a device further down the bus. The length of the bus and the number of device inputs also determine the capacitance that a memory device (or the controller) sees when it drives the bus—at higher frequencies, this capacitance may make it infeasible to drive signals reliably on the bus.
To combat these problems, a new memory bus architecture and memory module design have been proposed. Referring to FIG. 2, memory bus communications in this architecture pass along point-to-point connections between a memory controller 30 and buffer circuits (e.g., 38A). For instance, when memory controller 30 wishes to send memory signals to device 36C on module 34C, it sends those signals along a first segment of memory bus 32 to buffer 38A on module 34A. Buffer 38A redrives the memory signals to buffer 38B along a physically separate segment of memory bus 32, which redrives the signals in turn to buffer 38C along a third physically separate segment of memory bus 32. Buffer 38C transfers the signals to memory device 36C.
The bus architecture of FIG. 2 solves problems of the prior art. The relatively short, point-to-point bus segments greatly simplify impedance matching and bus timing issues. The capacitance seen by a bus driver can also be significantly reduced—on a given segment of bus 32, only one buffer's input needs to be driven. And each memory device only sees the buffer input on its own module, no matter how many modules exist in the memory system.
The concepts presented herein are generally applicable to the buffered module concept of FIG. 2, although, as will be seen, these concepts are useful in other configurations as well. Generally, some of the disclosed embodiments address two issues with the architecture of FIG. 2.
The first issue is bus width; from an examination of FIG. 2, it can be appreciated that buffer 38A connects to three full-width buses, one to memory controller 30, another to buffer 38B, and a third to memory device 36A. In contrast, some of the disclosed embodiments allow reductions to two full-width buses while maintaining a point-to-point bus configuration. Furthermore, with some embodiments it becomes possible to place multiple banks of memory devices on a module while maintaining this two-bus-width configuration. This advantage can significantly reduce the number of pins on the buffer and on the module card-edge connector, as well as easing routing layout on a module having multiple banks of memory.
The second issue is bus length; although in theory, the architecture of FIG. 2 can be extended to support any number of daisy-chained memory modules, signal propagation latency increases for each added module, this latency being proportional to N, where N is the number of modules. In contrast, the present disclosure includes embodiments with a latency proportional to the log of N, where N is the number of modules (or banks of memory).
By way of introduction, FIG. 3 illustrates one embodiment of the present invention. Although similar to FIG. 2, memory bus 42 differs from memory bus 32 of FIG. 2 in at least one significant aspect. After passing through the last buffer 48C, memory bus 42 loops back to a memory controller 40 to form a ring bus architecture. When buffers 48A, 48B, and 48C are enabled to intelligently pass signals bi-directionally, ring memory bus 42 can make effective use of both ring bus ports on an addressed buffer. For instance, memory controller 40 can send a data word to module 44B by sending half the word through buffer 48A, and the other half of the word through buffer 48C. When the two halves arrive at the ring bus ports of buffer 48B, buffer 48B can recombine them and transfer the data word to memory device 46B. Since only half of the data word passes in each direction, only half as many data signaling lines are needed as are needed in FIG. 2 for the same transfer rate.
The ring bus operates similarly for a read access. When a data word is read from memory device 46B, buffer 48B splits the word. Buffer 48B sends half of the data word to memory controller 40 by way of buffer 48A, and the other half of the data word to memory controller 40 by way of buffer 48C.
Several terms have been assigned particular meanings within the context of this disclosure. As used herein, a ring bus is a bus where each bus node maintains a point-to-point bus connection with a neighbor node on each side—the "first" and "last" nodes on the ring bus also maintain a bus connection between themselves. A memory unit comprises the memory accessible at one node of a ring bus; if this node lies on a lower-level ring bus of a multi-ring hierarchy, the memory unit can also be considered a memory subunit. A controller occupies a terminating position on a ring bus, i.e., ring bus signals propagate towards or away from the controller on the ring bus. The terms clockwise and counterclockwise are used in the following description to distinguish the two directions of propagation on a ring bus; these terms are not meant to assign any criticality to any given signal passing in any given direction or to infer that the bus need be configured in any sort of a physically circular fashion. A bank of memory devices is a collection of one or more devices that store data for a particular partition of host-addressable memory space.
Referring once again to FIG. 3, several possible ring memory bus implementations are possible. In one implementation, both the device addressing function and the data signaling function utilize the ring bus. Alternately, the addressing function can use buffered multi-drop or the point-to-point buffered configuration of FIG. 2, with data signaling occurring on the ring bus. Although in an optimal configuration half of the data would be sent along the bus in each direction, other divisions are also possible. While these alternate configurations are acknowledged, the following description will focus on a ring bus for both address and data signaling, where for a given memory transaction, approximately half of the data signals and approximately half of the address signals propagate in each direction along the bus.
FIG. 4 shows an alternate configuration that can improve latency and double the capacity of a module. Like FIG. 2, the modules of FIG. 4 connect to a point-to-point full-width host-to-buffer memory bus 52. But each module comprises two individually-addressable banks of memory devices (e.g., banks 56AA and 56AB on module 54A). Buffer 58A and banks 56AA and 56AB connect in a ring memory bus 52A that is local to module 54A. That is, buffer 58A functions as a controller of ring bus 52A. Half of the memory signals for a given transaction pass clockwise along bus 52A, and the other half pass counterclockwise. The non-addressed bank passes the signals along the bus. The maximum path length of FIG. 4 is five bus segments, versus six bus segments for the configuration of FIG. 2 (i.e., expanded with six modules to equal the memory capacity of FIG. 4).
FIG. 5 illustrates another configuration that combines the ring bus concepts of FIGS. 3 and 4. A first ring bus links a memory controller 60 and memory modules 64A, 64B, and 64C. A second ring bus located on each module (e.g., ring bus 62A on module 64A) connects to two banks of memory devices. Buffer 68A serves as a second-tier controller for ring bus 62A, while also allowing module 64A to appear as a single memory unit on ring bus 62. Although in the specific configuration of FIG. 5 no further latency improvement over FIG. 4 is observed, pin count reductions are possible on both tiers of ring buses.
A memory transaction on the architecture of FIG. 5 can proceed as follows. Controller 60 is directed to access a memory address that is physically located on bank 66BB. Half of the memory signals pass through 68A, 68B, and 68BA. The other half of the memory signals pass through 68C and 68B.
Two issues that arise with the ring bus (single or multi-tiered) are timing and addressing. At least one device in the bus path will account for potential timing differences between the two halves of a set of memory signals. And each non-controller node on a ring bus will receive some type of forwarding information in order to know whether to forward memory signals for a given transaction along the bus or to capture those signals because they relate to a memory unit within that node's addressable space.
The timing issue will be explored in further detail, but may be handled in several ways. First, the controller of each ring bus can be responsible for adjusting the relative timing of the two halves of a transmission. Second, the memory units of each ring bus can be responsible for adjusting the relative timing of the two halves of a transmission. These retiming responsibilities can also be handled by one unit in each multi-tier ring bus path, whether that unit be a signal source, a signal destination, or an intermediate transfer node.
Forwarding information is preferably gleaned from the address bits of a transaction (e.g., the bank selection bits). In some embodiments, this may require that the bank selection bits be duplicated and transmitted on the bus in both directions. This duplication should not, in most cases, result in an appreciable increase in bus width-thirty-two banks of memory can be addressed with only five forwarding bits.
The multi-tiered ring bus structure can be expanded past two levels. FIG. 6 depicts one expanded structure that resembles a binary tree. The host connects to a primary memory controller CRoot, which occupies a first tier in the ring bus hierarchy. Two second-tier controllers C0 and C1 connect with CRoot through a root ring bus. Each second-tier controller connects to two third-tier controllers through a second-level ring bus (e.g., second-tier controller C0 connects to third-tier controllers C00 and C11 through ring bus R0). Although other intermediate levels of controllers could be included, in FIG. 6 the fourth tier comprises the leaf nodes, e.g., the memory banks. Each third-tier controller connects to two memory banks through a third-level ring bus (e.g., third-tier controller C00 connects to memory banks M000 and M001 through ring bus R00).
The binary ring bus architecture has several desirable attributes. First, each non-controller node on a ring need examine only one forwarding bit in order to decide whether to keep a given bus transmission or forward it to the next node on the ring. This bit can be equated to a binary memory-addressing bit.
A second attribute is that the maximum number of bus segments that must be traversed by a memory signal is directly related to the bus depth, and therefore logarithmically-related to the number of memory banks addressable by the architecture. N memory banks require a maximum bus segment path P, where
A third attribute is that a simple method for determining the path differential to a leaf node (or any intermediate node) exists for the binary ring bus architecture. The clockwise and counterclockwise paths to or from a leaf node include a minimum number of bus segments equal to the tree depth (three rings in FIG. 6). To this, a clockwise path (to the node) includes an additional number of bus segments equal to the number of 1's in the forwarding address to the node. Likewise, the counterclockwise path (to the node) includes an additional number of bus segments equal to the number of 0's in the forwarding address to the node. The differential path length to a node is thus the difference between the number of 0's in the forwarding address and the number of 1's in the forwarding address. These straightforward rules can be used to register signal halves, predict when the second half of a signal will arrive at a given node, etc.
A fourth attribute is the ability to construct a partial full-tree bus with a minimum number of continuity devices. For example, FIG. 7 shows the architecture of FIG. 6, but with only two memory banks M000 and M001 actually present. A first continuity device CD1 completes the root ring bus, and a second continuity device CD01 completes ring R0.
Note that a lower-tier controller can function as a continuity device. For instance, FIG. 8 shows a high-level layout for a main board having four slots 74-77 for accommodating up to four memory modules. Second-tier controllers 84 and 94 can each function as a continuity device if their slots remain unfilled. If one of the two slots connected to a second-tier controller has no memory module, a continuity module can be placed in that slot. It is noted that it is also possible to collapse the second-tier controllers into a common integrated circuit package with primary memory controller 70, if it is feasible to connect four half-buses of memory bus pins to controller 70. An advantage of such a structure is that the clocking delays of the second-tier controllers can be avoided.
FIGS. 9 and 10 illustrate one ring-bus node-connection model useful with the present invention. FIG. 9 shows a primary memory controller 70 with two ports A and B. Primary memory controller 70 shares a ring bus with memory units 80 and 90, each of which also has an A port and a B port. To complete the ring, primary memory controller 70 port A connects to memory unit 80 port B, memory unit 80 port A connects to memory unit 90 port B, and memory unit 90 port A connects to primary memory controller 70 port B. The memory units can be virtually identical, the only difference being that each one has a unique forwarding address.
If the memory units have ring-bus subunits, FIG. 10 shows one possible ring-bus node-connection model for this configuration. In this configuration, the primary memory controller 70 can be considered a first-tier controller as it controls the first-tier ring bus. Bus ports on the first-tier ring bus are level-one ports, and bus ports on the second-tier ring buses are level-two ports. Considering memory unit 80, a second-tier controller 84 incorporates the level-one ports A and B of that memory unit to first-tier ring bus 72. Second-tier controller 84 is capable of transferring memory signals between its level-one ports A and B (in redrive mode). Redrive mode is used when second-tier controller 84 receives a memory signal (on bus segment 72A or bus segment 72C) that is not destined for memory unit 80.
Second-tier controller 84 also has two level-two ports C and D to connect to a second-level ring bus 82. Controller 84 operates in a transfer mode when a signal is to be transferred from its memory subunits to primary memory controller 70. In transfer mode, memory signals pass between level-one port A and level-two port D of second-tier controller 84, and/or between level-one port B and level-two port C.
FIGS. 11 and 12 show exemplary timing diagrams for two possible methods of implementing a read operation, illustrating how address and data signals generally move along the two-tiered ring bus architecture of FIG. 10. Although the address signals are shown as happening during a single bus time, those skilled in the art recognize that each particular type of memory device may have particular addressing sequences wherein some address signals occupy one bus time and other address signals occupy different, but time-related bus times. The notation Ax.y refers to an address x, address segment y. Likewise, the notation Dx.z refers to the data read from address x, data segment z.
FIG. 11 shows a read operation to memory subunit 86, followed by a read operation to memory subunit 88. Primary memory controller 70 initiates a read to address A1 (on subunit 86) at T1 by placing address segment A1.1 on memory bus segment 72A and its corresponding address segment A1.2 on memory bus segment 72B. Address segment A1.1 arrives at second-tier controller 84 port B; controller 84 reads the high-order forwarding bit attached to that address segment and determines that it should keep it. Thus at T2, second-tier controller 84 transfers A1.1 out its port C onto bus segment 82A on second-tier ring bus 82. Note that controller 84 may strip the high-order forwarding bit from A1.1 when transferring it to ring bus 82.
Also at T1, A1.2 arrives at second-tier controller 94 port A; second-tier controller 94 reads the high-order forwarding bit attached to that address segment and determines that it should forward it. Thus at T2, second-tier controller 94 redrives A1.2 out its port B onto bus segment 72C. A1.2 next arrives at second-tier controller 84 port A; controller 84 reads the high-order forwarding bit attached to that address segment and determines that it should keep it. Thus at T3, second-tier controller 84 transfers A1.2 out its port D onto bus segment 82B on second tier bus 82. Note that controller 84 may strip the high-order forwarding bit from A1.2 when transferring it to ring bus 82.
Also at T2, A1.1 arrives at memory subunit 86 port B; subunit 86 reads the next-to-highest-order forwarding bit and determines that it should keep it. Memory subunit 86 knows from its forwarding address that it can expect the remainder of the address (A1.2) two memory cycles later at T4. Thus, it can store A1.1 until A1.2 arrives. Alternately, if it can begin the memory cycle before A1.2 arrives (if, for instance, A1.1 contains the row address and A1.2 contains the column address), it may begin to process read operation A1.
At T3, A1.2 arrives at memory subunit 88 port A; subunit 88 reads the next-to-highest-order forwarding bit and determines that it should forward it. Thus at T4, memory subunit 88 redrives A1.2 out its port B onto bus segment 82C. A1.2 arrives at memory subunit 86 port A; subunit 86 can read the next-to-highest order forwarding bit to determine that it should keep it; alternately, A1.2 can be automatically kept-subunit 86 knows that it should receive at T4 the companion to A1.1 on its port A, based on its timing from A1.1.
Memory subunit 88 reads the data at address A1 (this is shown as taking two cycles; the actual number of cycles required is device-dependent). At T6, data D1 is ready to be sent back to primary memory controller 70. Subunit 88 drives one-half of the data D1.1 out its port B onto bus segment 82A; subunit 88 drives the other half of the data D1.2 out its port A onto bus segment 82C. Subunit 86 also signals subunit 88 to redrive D1.2.
Data segments D1.1 and D1.2 generally retrace the paths taken by address segments A1.1 and A1.2 back to primary memory controller 70. D1.1 arrives at controller 70 port A at T7; D1.2 arrives at controller 70 port B at T9. Controller 70 knows when to expect these data segments based on the forwarding address that was originally supplied with the address segments.
The read to address A2 presents a timing issue, as this address lies on a different subunit (subunit 88) than A1 lies on. In this instance, if address segments A2.1 and A2.2 were issued immediately after A1.1 and A1.2, A1.2 and A2.1 would collide on memory bus segment 82C (as would D1.2 and D2.1 on bus segment 82B). But since primary memory controller 70 can know the latency for each address segment (and corresponding data segment), it can delay issuing A2 until T4 to prevent a collision. Note that in this instance, D1.2 arrives at primary memory controller 70 at T9, and D2.1 and D2.2 arrive at T10, only one cycle later. This will not always be the case, as a read to a longer-latency path subunit can cause the data bus to be empty for one or more cycles.
Write commands operate similarly to read commands, except that data signals pass in the same direction as address signals on each bus segment. Note that a read-to-write turnaround must also ensure that the data bus is clear from the last read before write data is placed on the bus.
FIG. 12 illustrates the same two read operations under a slightly different method of operation. Here, instead of having the primary memory controller and the memory subunits retime address and data segments that arrive at different time, all retiming is accomplished in the second-tier controller that transfers the segments between ring buses 72 and 82. At T1, primary memory controller 70 initiates a read to address A1, just like it did in FIG. 11. But when A1. arrives at second-tier controller 84, second-tier controller 84 knows that if it transfers A1.1 immediately, it will arrive at memory subunit 86 two clock cycles ahead of A1.2. Thus second-tier controller 84 holds A1.1 for two clock cycles, allowing itself time to receive A1.2 at T2 and retransmit A1.2 at T3. Finally, at T4, second-tier controller 84 retransmits A1.1. Both A1.1 and A1.2 arrive during the same clock cycle at memory subunit 86.
On the return data path, second-tier controller 84 once again performs a hold, this time of D1.1 during clock cycles T7 and T8. This hold allows D1.1 and D1.2 to both arrive at controller 70 at T9. Note that in this scheme, since several data or address segments may arrive at a given port in consecutive clock cycles, second-tier controller 84 may require a multi-stage buffer to perform the hold function. Also note that the read to address A2 requires no retiming, since the path lengths are identical for the two paths.
FIGS. 13A and 13B show, respectively, top-edge and side views of a memory module 100 according to an embodiment of the invention. A bank of eight memory devices, labeled 140A to 140H, populates the upper portion of one side of module 100. A second corresponding bank (beginning with device 142A) populates the other side of module 100. The first side contains three other devices: ADD/CMD (Address/Command) Redrive/Transfer Logic 110; L (Left) Data Redrive/Transfer 120; and R (Right) Data Redrive/Transfer 130. Together, these three devices function as a module controller. The controller functions performed by these devices are partitioned into three circuits for routing and pinout convenience—a lesser or greater number of devices can be designed to perform the same function. Left and right redrive/transfer devices 120 and 130 perform the same functions at the same time, just on different groups of data lines.
Also shown in FIGS. 13A and 13B are address/command and data lines. The external address and command lines are shown as two single lines, one connecting logic 110 to ADD Port A and the other connecting logic 110 to ADD Port B (a dashed line represents a signal routed on the opposite side of the module—this is not necessary, but is one preferred method of routing). Each single-address-line depiction in FIG. 13B will typically represent multiple address and command signal lines, the number depending on device type, addressable memory size, etc. Four sets of four external data bus lines each are also shown, the sets connected respectively to L data redrive/transfer 120 ports B and A, and R data redrive/transfer 130 ports B and A. Together, these four sets form a sixteen-bit-wide data bus in the preferred ring bus implementation. This bus width is exemplary, as any other bus width can also be selected.
Externally, memory module 100 forms a node in a higher-level ring bus. Internally, devices 110, 120, and 130 together form a ring bus controller for a lower-level local ring bus including the controller and the two banks of memory devices. Address and data signals arriving at port A can be redriven out port B (and vice-versa) on the higher-level bus. These signals can also be transferred to the local ring bus. According to the layout of FIG. 13B, port A signals can be transferred to the memory devices on the facing side of module 100, and port B signals can be transferred to the memory devices on the hidden side of module 100. The memory devices on the two sides of the module also connect through the substrate (see FIG. 13A), completing the local ring bus.
Logic 110 controls bus redrive and bus transfer functions for itself and for devices 120 and 130. Logic 110 provides a clock signal CLK to devices 120 and 130 to synchronize data operations. Logic 110 provides two other signals, F/T (forward/transfer) A and F/T B to control the data paths through devices 120 and 130.
FIG. 14 illustrates an alternate memory module configuration 150. In this configuration, the left and right data redrive/transfer devices 170 and 180 also provide a MUX/DeMUX (Multiplexer/Demultiplexer) function. This function allows the external ring bus and the local ring bus to operate at different speeds and with different data widths. For instance, device 150 is shown with eight external data lines and 16 internal data lines. When the external ring bus can operate at twice the frequency of the memory devices, this configuration allows the external ring bus to transfer data at the full speed of the devices with less data lines, further reducing pin count on the bus devices and the module cards.
FIG. 15 details one possible configuration for a redrive/transfer device 170 useful with module 150. Device 170 comprises seven bidirectional two-bit buffer circuits and two 4:2 MUX/DeMUX units. One buffer circuit 172 connects between port A and port C (serving the external ring bus). When RDRV_A/B is enabled, circuit 172 redrives data signals from port A to port B. When RDRV_B/A is enabled, circuit 172 redrives data signals in the opposite direction. Buffer circuit 172 includes a latching function, controlled by LAT_B/A, that can be used to retime signals passing between ports A and B.
Two other buffer circuits 174 and 176 transfer data signals, respectively, between ports A and B and MUX/DeMUX units 178 and 180. When one of circuits 174 and 176 has its OUT signal enabled, that circuit transfers data from the MUX output to its external port. When one of the circuits has its IN signal enabled, the circuit transfers data from its external port to the deMUX input.
MUX/DeMUX units 178 and 180 are also bidirectional. Considering unit 178, A_SEL determines which of buffers 182 and 184 is currently coupled with buffer 174 through unit 178. When A_DIR is set in one state, data flows towards buffer 174; conversely, when A_DIR is set in the opposite state, data flows away from buffer 174.
Buffer circuits 182 and 184 function as a pair for data transfers IN on port D, e.g., data is received from the memory devices as four bits in parallel. For data transfers OUT on port D, first one-half of the bits are latched (e.g., the most-significant bits can be latched first into buffer 182 using D_MSB_OUT) from DeMUX 178; when the second half of the bits arrive, they can then be latched into the other buffer circuit. The latching signals LAT_DM and LAT_DL can operate in unison to latch data from the memory devices; the latching signals operate sequentially to latch data received on port A.
It is noted that the redrive/transfer circuits of FIGS. 13A/B, 14, and 15 can have other functions besides data redrive/transfer and multiplexing/demultiplexing. For instance, the circuits can incorporate multistage hold buffers that can be used to retime two halves of a ring bus transmission. The circuits can also provide clock synchronization between the A and B ports and/or between the two buses. Preferably, the circuits will provide capacitive isolation between the external and local buses. Where the memory devices require different signaling voltages than those used by the motherboard circuitry, the transfer circuits can also provide voltage translation.
The types, sizes, or numbers of memory devices selected for use with the present invention are not critical. Some possible device types include dynamic random access memory (DRAM) devices, synchronous DRAM (SDRAM) devices including double-data-rate (DDR) SDRAM devices, quad-data-rate (QDR) SDRAM devices, Rambus™ DRAM devices (with an appropriate controller), static RAM and flash memory devices. It may be possible to combine memory modules in a memory system according to the invention where two modules incorporate different types of memory devices. Where two or more memory devices are physically connected in a ring architecture, the ring buffer circuitry can be incorporated onto the memory devices themselves or placed on a separate interface circuit.
One of ordinary skill in the art will recognize that the concepts taught herein can be tailored to a particular application in many other advantageous ways. In particular, those skilled in the art will recognize that the illustrated embodiments are but one of many alternative implementations that will become apparent upon reading this disclosure. For instance, a row address may always be sent over the shortest of two paths (and the column address in the other) in order that it arrives at a memory unit in the shortest possible time. Two banks of memory on a module could also not be arranged in a lower-tier ring bus, but connected instead to the module's controller through separate point-to-point buses. Such minor modifications are encompassed within the invention, and are intended to fall within the scope of the claims. The preceding embodiments are exemplary. Although the specification may refer to "an", "one", "another", or "some" embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.
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Texas A&M plays Colorado at Boulder, Colo., on Saturday at 12:30 p.m. Join Aggies beat writer Brent Zwerneman for a live chat beginning at noon. [Read More]
Boulder 'high'? Ags vow it's more about attitude
COLLEGE STATION — There's no team in the Big 12 closer to sea level than Texas A&M, so when the Aggies prepare to play at Colorado every four years they get the inevitable question about playing 5,430 feet above gulf waters. Coach Mike Sherman, architect of A&M's vaunted Gulf Coast Offense (kidding), says the Aggies […] [Read More]
Win (on TV) and hype surrounding Johnson will grow
COLLEGE STATION — As he often does, Texas A&M offensive lineman Mike Shumard said it best in describing quarterback Jerrod Johnson's role with the team. "He's the catalyst of this offense," Shumard said. Boy, is he — and Johnson is quietly putting up some big numbers in the Big 12. Try these on for size: […] [Read More]
Tweet, tweet? Miller shrugs off Hagan's warning
COLLEGE STATION — Colorado running backs coach Darian Hagan picked a Twitter fight with Von Miller this past offseason, but Miller didn't bite. "Can't wait for the season to start!" Hagan wrote on July 22. "Von of A&M, we coming for you!" Apparently at least part of Hagan's angst came from the picture Miller, Texas […] [Read More]
Von Miller to NFL? Pass rusher to explore his options
COLLEGE STATION — Texas A&M junior Von Miller said Monday he'll explore his options concerning the NFL after this season — but right now his sole focus is on helping the Aggies win. "You've at least got to take a look at it," Miller said of checking out where he projects in the NFL draft […] [Read More]
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We're moving! Our office will be moving to 1892 S. Winton Road this summer.
About Us
Petrella Phillips LLP is a leading firm of Certified Public Accountants and business advisors with historical roots dating back to 1965.
The partners and staff have earned a reputation for professionalism, integrity, and responsiveness. We are always available for our clients. Our practical and real-life approach to business, taxation, planning, and operations has given us a unique edge in today's business environment.
We are committed to adding value with our pro-active approach to identifying opportunities that focus on business solutions. Our caring attitude, creativity, and diligence benefit you by acknowledging the simple fact that our success is dependent on your success.
We are a member of the CPA Connect Network, which gives us access to the most comprehensive suite of services and a knowledge base second to none. This allows us to offer our clients cutting edge services on a local and personal level.
Plan. Perform. Progress.


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Middle East
4:08 am
Fri June 13, 2014
Iraq's Army Is Ineffective Against Islamist Insurgents
Originally published on Fri June 13, 2014 7:30 am
There are reports of Iraqi government troops just fleeing, dropping their weapons and shedding their uniforms. The U.S. spent a lot of time and money training Iraqi forces.


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Kiplinger's 10 Great Places to Live
An annual ranking of the best parts of the country has Bryan/College Station third overall.
Kiplinger's Personal Finance's 2013 edition of "America's 10 Great Places to Live" has this area just behind Little Rock, Arkansas and Burlington, Vermont.
"Each year we take a look at America's cities and choose those that stand out in a particular category—say, for raising a family, starting out after college or enjoying retirement," said the editor of Kiplinger's, Janet Bodnar, in a press release issued by both cities. "The cities in this year's rankings have a manageable size combined with a wide range of benefits that allow residents to enjoy a convenient and comfortable lifestyle."
As expected, the mayors of the cities were pleased by the ranking.
"Bryan is an exceptional city, no matter what stage of life you're in," Bryan Mayor Jason Bienski said the press release. "We have access to the best in education and health care, we're experiencing strong business development and job growth in all areas of the city, and our historic downtown is once again earning the reputation as a true destination. We really mean it when we say Bryan offers The Good Life, Texas Style."
"I'm delighted Kiplinger's recognized us as a great place to live," College Station Mayor Nancy Berry added. "Of course, it's no secret to those who call College Station home. We're a safe city, have great parks and amenities, super schools and a wonderful arts community; plus, we're home to Texas A&M University. Add it up and you're living in one of the greatest places in the country."
Bryan/College Station is the only Texas area on the list.
More information is available at the Kiplinger's website.
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Copyright © The Furnace Cleaners Inc., 2012. All rights reserved.
Call us today at (253) 630-9433
The Furnace Cleaners Inc. 14331 SE 232nd Street Kent, WA 98042Phone: (253) 630-9433Email
We are Proud to Say we Have Been Keeping Customers Happy and Safe With Fast, Dependable and Affordable Furnace Cleaning Services for Almost 4 Decades.
Why Clean Your Furnace? Without a yearly cleaning inspection and cleaning, a furnace can wear itself out quickly, pump deadly carbon monoxide into your home, or simply stop working. We are here to make sure your system is in top working order to prevent any future, and sometimes fatal, problems from occurring.
Locally owned and operated, fully licensed, insured and bonded, you can depend on us for thorough cleaning and inspection. Our trucks, equipped with the most advanced and powerful tools, allow us to provide top-notch workmanship; there truly is a difference in the quality of work we provide.
For yearly maintenance and a thorough cleaning of your furnace and duct work, you can depend on The Furnace Cleaners Inc; we know our stuff! And we are so confident with our service that we give our customers a complete satisfaction guarantee
Keep your family safe and warm during the winter months. Schedule an appointment with us today. We offer affordable prices and senior discounts are available. You can't afford not to call us; dial (253) 630-9433 now! Feel free to browse our website for more information or contact us immediately!


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Install solar screens to cut back your own monthly electricity bills
Solar Screens include the best approach to saving cash on your power expenses. Preventing 80% or maybe more from the temperature inside your home windows coming from entering your own home they're able to provide fast convenience in your case and relief for your ac. On average, energy charges tend to be diminished through 30% following putting in solar power screens. Which has a selection of screen and also framework shade options, you'll find a mix that enhances your own home or office. In the event you opt for solar screens dallas, you will discover businesses which may work for you very well. Look for the web and you will probably buy them. Several companies in addition serve solar screens fort worth area.
Solar power Screens would be the most affordable treatment to be able to lower your energy expenses with your Houston property. Photo voltaic Screens function by simply stopping the temperature transfer that occurs via your doors and windows without having compromising your current view. Solar screen Dallas businesses offer you many solar screen possibilities ranging from 80% in order to 90% warmth obstruction. All of the solar shades dallas tend to be certain to look great, operate as time passes, and keep your own home chillier that will save a little money on the power bills. Sunshine hitting the glass will certainly generate about 230 BTU's for each sq . ft . regarding glass and this is how high temperature grow in the room might be lowered.
The solar shades dallas will probably offer you excellent defense against the sun's high temperature and also harming Ultra violet rays and also help keep your own home as well as business office cooler as well as your furnishings along with flooring protected. The best part will be the every month energy savings provided by a new one-time investment in solar power protection. Making a conclusion to safeguard your house as well as office along with solar window screens dallas will probably pay an individual back again often times over in electricity financial savings alone inside long time, not to mention an added comfort along with safety given by screens and also shades.
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June 14, 2006 | 454 Life Sciences has launched an updated version of the Genome Sequencer 20 System, which yields significant improvements in the way the system can be used and in the resulting data. Enhanced features include a single read accuracy of greater than or equal to 99 percent, which will increase the quality of consensus sequences and improve the confidence level of putative sequence deviations detected using heterozygote calling; software algorithms to enable additional applications resulting in improved assembly and contigging procedures allowing for the sequencing of hundreds of thousands of short DNA fragments.
Vendor: 454 Life Sciences
Product: Genome Sequencer 20 System
Availability: Now
For more information: www.454.com
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Total compensation and rewards
The current compensation models were introduced around 2004-2006 and it now makes sense to go back and review these principles. It is important to note that assessment of the efficiency and efficacy of our total compensation and reward models is an ongoing practice.
Expected outcomes of projects under the strategy of total compensation and rewards are:
- Approved total compensation principles to guide decision making
- Clear benchmarks for total compensation reviews
- Approved competitive market strategy for each employee group
- Alignment among existing working groups and teams ( e.g. pensions working group, benefits team)
- Report on specific strategies/ initiatives which will align with principles during the MYOB
- Guidelines for decentralized administrative practices


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|« Back to Article
Missions edge Tulsa in extra innings
Staff Report : June 25, 2014
Missions 1, Tulsa 0 (10)
TULSA, Okla. — The Missions opened a six-game road trip Wednesday night with their first extra-inning victory since April 29 in front of 4,443 at ONEOK Field.
Reymond Fuentes' pinch-hit double in the 10th drove in Yeison Asencio with the only run of the game and helped lead the club to just its third extra-inning triumph this season.
Adys Portillo worked a scoreless ninth for his first win of the year, while Frank Garces retired the side in order in the 10th to notch his sixth save.
It was the Missions' ninth shutout of the year, tying them with Mississippi for the most in Double-A. All of San Antonio's shutouts have come in the club's last 34 games.
The Missions have allowed only 25 runs in the last 12 games.
Notebook: The Padres acquired RHP Michael Dimock in a trade with the Astros and assigned him to the Missions. ... The Missions have scored just 20 runs over their last 10 games.
Next up: Missions (RHP Josh Geer, 3-7, 3.78 ERA) @Tulsa (RHP Richard Castillo, 2-6, 4.50), 7:05 p.m. today
Radio: KONO-AM 860
Staff report


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(Blytheville, AR) Just after 7:30 p.m., the skies finally opened.
A heavy band of ice cold rain fell to the ground, creating big puddles and whipping wind in northeastern Arkansas.
It's setting the stage for what residents say will be a very difficult few days, or perhaps much more.
"I put my oil in it and making sure my fluids and all is right," said Eddie Thomas.
He joined many people jockeying for space at the gas pump.
People hit up the stores, preparing for days, even weeks, inside.
Power crews are already out, since ice forming on power lines is a big concern here in Blytheville.
And that's not the only concern.
"We want everybody to stay in the house but some people just got to get out and we're prepared for it," said Deon Robinson.
Robinson of Blytheville Fire and Rescue says they've been preparing for all hands on deck this weekend.
"We got our generators and everything set up loading up fuel cans", said Robinson.
Some say it may seem a little excessive, and they hope it is.
But big ice storms have hit here before, and almost everyone who remembers them say they're nothing nice.


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I just wanted to send a quick note about the exceptional customer service that I have received and continue to receive from Nicole. We ordered a couple of awards from Glassical Designs last fall for an event and Nicole was extremely friendly and prompt in her responses and follow through. Because of her customer care and the quality of the product, we have decided to order again from your company and I was fortunate enough to work again with Nicole. I am sure we will have future orders to send your way. Please thank her for me. She deserves kudos!
Please thank her for me. She deserves kudos!,


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Leaf mulching and composting of leaves are an earth - friendly way to take care of your leaves and saves space in our landfill making room for regular garbage. These methods assist in extending the life of our landfill.
Save your time, your money and your back and help improve your lawn health by mulching leaves right on your lawn! There's no need to rake your leaves, buy bags or lug the bags to the curb when you mulch your leaves.
Leaf mulching is the process of shredding leaves with your lawn mower or leaf shredder and using them as mulch on your lawn and garden.
Leaf mulch gives nutrients back to the soil. Your lawn and gardens will require less fertilizer and other additives. Leaf mulch also helps retain moisture in soil and prevents the growth of weeds.
Click here to see a video on how it works.
*If you have too many leaves to mulch try the following:
Compost your leaves
Add thin layers of leaf mulch (1 inch) to your composter while alternating with other materials. You can also use a separate composter for only leaves. For a leaf composter, alternate 6 inches of leaf mulch with a thin layer (1 inch) of soil or finished compost and maintain by turning it regularly and keeping it moist.
Dig leaves into your garden
Dig leaves directly into your garden to add organic matter and nutrients to the soil.
Use leaves as mulch
Put leaf mulch on gardens and flower beds and around trees and shrubs.
Click here to see a video on how it works.
For more information click here.
For the month of November, leaves in paper yard waste bags will be picked at the curb on the same day as your garbage day.
There are two options for bagging leaves:
1. An earth - friendly way to take care of your leaves is to use paper yard waste bags.
Leaves will be collected separately from your garbage by City trucks and delivered to the landfill where they will be composted. The compost will be used for landscaping purposes on City property.
There is no limit to the number of paper yard waste bags set out for collection at your curb.
Paper yard waste bags are available at most hardware stores and building centres.
2. By using plastic bags for your leaves these leaves will go directly with your garbage and will be landfilled having no further use.
These bags will count towards your 10 bag limit for garbage.
For more information click here.
Go Back to Home : Residents
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Thomas W. Ewing
|This article includes a list of references, related reading or external links, but its sources remain unclear because it lacks inline citations. (March 2013)
|Tom Ewing
|Member of the U.S. House of Representatives
from Illinois's 15th district
|In office
July 2, 1991 – January 3, 2001
|Preceded by
|Edward R. Madigan
|Succeeded by
|Timothy V. Johnson
|Personal details
September 19, 1935
Atlanta, Illinois
|Political party
Thomas W. "Tom" Ewing (born September 19, 1935 in Atlanta, Illinois) is a former Republican member of the United States House of Representatives and the Illinois State House of Representatives. Ewing was a state representative from 1974 to 1991, and a U.S. Congressman representing the 15th district of Illinois from July 2, 1991 until his retirement on January 3, 2001. In January 1995 he was named a Deputy Republican House Whip. While a U.S. Congressman, Thomas Ewing was considered to be a Conservative, favoring a smaller, less intrusive government, but more on economic issues than on social ones.
Ewing has a B.S. from Millikin University, Decatur, Illinois, where we was a member of the Illinois Delta Chapter of Sigma Alpha Epsilon, and a J.D. from John Marshall Law School in Chicago. Ewing served in the United States Army Reserve from 1957 to 1963. He practiced law privately from 1963 until 1968, and Ewing was the Livingston County, Illinois district attorney from 1968 until 1973. He earned his seat in Congress after a special election was called following the resignation of Edward Madigan. In December 2000 he introduced the Commodity Futures Modernization Act of 2000.
From 2001 to 2007, Ewing served as the chairman of the Biomass Research and Development Technical Advisory Committee. This new government body was created in 2000.
External links[edit]
|United States House of Representatives
|Preceded by
Edward R. Madigan
|U.S. Representative of Illinois' 15th Congressional District
|Succeeded by
Timothy V. Johnson
- 1935 births
- Living people
- People from Livingston County, Illinois
- People from Logan County, Illinois
- Members of the United States House of Representatives from Illinois
- Members of the Illinois House of Representatives
- Illinois Republicans
- State attorneys
- American prosecutors
- United States Army soldiers
- Republican Party members of the United States House of Representatives


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The Graduate Center offers more than thirty doctoral programs in the arts, humanities, social sciences, and natural sciences, including History.
Learn about the Graduate Center's core faculty,
including Distinguished Professor David Joselit (pictured),
on the Faculty Profiles page.
Through its extensive public programming, the Graduate Center contributes to the intellectual and cultural vitality of New York City.
The Graduate Center has announced its
Doctoral Student Parental Accommodation Policies.
Support for the Graduate Center ensures continued excellence in arts and
sciences graduate education, research, and public programming.
The Master of Arts in Middle Eastern Studies offers an interdisciplinary approach to graduate study on the Middle Eastern region and its diaspora. Students enrolled in the program gain a broad understanding of the history, politics, economics, religions, and cultures of this critical region, and develop special competence in their particular area of interest. This is the first M.A. program in the country to incorporate the study of the Middle Eastern diaspora in its curriculum, encouraging new ways of thinking about the adaptation of Middle Eastern immigrant communities in the Americas and Europe. The program is geared to those interested in academic careers as well as those pursuing terminal M.A. degrees in preparation for careers outside the academy such as in public policy, journalism, social work, international relations, economic development, immigrant advocacy, education, or translation/interpretation. Students will have access to diverse faculty and wide expertise as well as to the rich resources available in New York City.
The Graduate Center
365 Fifth Avenue
New York, NY 10016-4309
Email: email@example.com
Co-DirectorGraduate CenterMiddle East & Middle-Eastern American Center365 Fifth AvenueNew York, NY 100164309
Email: email@example.com: (212) 817-7574


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Warren county manager to be compensated for travel
Warren's county manager will be compensated for travel now.
At the Warren County Board of Commissioners meeting Monday, commissioners negotiated the deal in closed session.
Afterwards, they approved a $7,500 yearly allowance for County Manger Linda Worth's travels effective Aug. 1.
Angelena Kearney-Dunlap, clerk to the board, said Worth drives all over the state attending conventions and events.
Worth said she uses her own car and gas and has not been compensated — like other local county managers have — for the entire 13 years she has been in her position.
The board also approved:
• Consent agenda items, including the declaration of August as World Breastfeeding Month in Warren County to join the county health department's awareness week and the declaration of Warren County as a Purple Heart county — the 98th county to take the oath, according to Kearney-Dunlap.
• The reappointment of Karl F. Hehl to his seat on the Alcoholic Beverage Control Commission for another three years.
• The authorization of sale of two old county maintenance vehicles and a resolution declaring intent to pay debt on new ones.
Contact the writer at email@example.com.


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Luis Benitez (2015 Computer Animation graduate) created this life-like cider still life using different computer programs.
These stills are taken from an experimental video called Retro Pop! by Jesus Rob Montilla (Digital Arts and Design, current student). In his own words, the assignment was for "an abstract piece that could represent the topic of 'color expressionism.' The concept for the video was to show commonly known objects while playing with paint and cool special effects. The cheap and weird aesthetic of the video was the goal of the project." Check it out below.
This texture study was done by Kyle Lindsey (Game Art, current student).
Christian Demars (Digital Arts and Design, current student) created this 3D model of a coffee machine. This was a final project for his 3D Arts class where they learned Cinema 4D software to complete a semi-complex model by the end of the course.
The past is not always as it seems. In this Full Sail University student film, a young man is provided a glimpse back in time, where he learns the truth about his mother's death and his father's death row conviction.
Demo reel highlights from Computer Animation and Game Art graduates with a concentration on 3D Modeling and Texture.
Carlos Rosado (2015 Digital Arts and Design graduate) created infographics for endangered animals that he formatted into an app and brochure design.
Daniela Sora (current student, Digital Arts and Design) created a 3D recreation of a record player.
Is the romanticism of journalism coming to an end? In this Full Sail University student film, a seasoned reporter faces the intersection of print and digital news, and wonders if change is really for the best.
These screen shots are from the game Cybersaurs: Annihilation as a collaboration between Game Design and Game Development students. In this third person shooter game, Rico McFury must use an arsenal of guns, arm augmentations, and special abilities to defeat a variety of cyborg dinosaurs from invading. Watch a play through of the game or download your own copy to play here.