text:
Crazy Lasagna
There is no need to make lasagna in tidy little layers and rows. It doesn't even need to be served in squares. It looks different than the traditional, but tastes as good. And it is much, much faster!
- Nathalie Dupree
For the meat sauce:
3 tablespoons peanut oil, divided use
1 onion, finely chopped
1 rib celery, finely chopped
1 small carrot, finely chopped
1 clove garlic, crushed
1 pound country sausage, crumbled
1/4 pound fresh mushrooms, chopped
1/3 cup dry red wine vinegar
1 teaspoon chopped fresh parsley
5 tablespoons chopped herbs: oregano, basil and thyme, preferably fresh
1 tablespoon rosemary, fresh or dried
Pinch nutmeg
2 (16-ounce) cans tomatoes, preferably Italian, peeled, seeded and chopped, juice reserved
1 (6-ounce) can tomato paste
Sugar to taste
Salt and freshly ground black pepper
For the white sauce:
6 tablespoons butter
5 tablespoons flour
3 cups milk (see cook's note)
White pepper
3/4 pound dried lasagna
2 cups freshly grated Parmesan cheese, divided use
4 tablespoons butter, melted
Cook's note: If time allows, flavor the milk by bringing milk to a simmer with 6 peppercorns, parsley stalk, bay leaf, small slice of celery, small slice of carrot, small onion cut in half; remove from heat and let sit 30 minutes, then strain.
To make the meat sauce, heat 2 tablespoons of the oil in a large pot and add onion, celery, carrot and garlic. Cook gently for 15 minutes, until the vegetables are soft.
In a skillet, brown the sausage in the remaining tablespoon of oil. When it is well browned, drain off excess fat, add mushrooms, and saute. Add the vinegar and cook 5 minutes, scraping the bottom of the pan to deglaze. Add the herbs, nutmeg, salt and pepper and cook until the liquid has completely evaporated. Remove from the heat, and add to the vegetables. Add tomatoes, tomato paste, and enough reserved tomato juice to thoroughly moisten. Bring to a boil, then simmer uncovered for 1 hour, adding more tomato juice if necessary and stirring from time to time. Taste. Season with sugar, salt and pepper.
To make the white sauce, melt the butter and stir in the flour. Add the milk and bring to a boil, stirring constantly until thickened. Taste and season with salt and white pepper. Remove from the heat and cover with wax paper to prevent a skin from forming.
Cook lasagna 6 to 8 at a time in a large pot of boiling salted water. As each batch is done, remove with a slotted spoon to a bowl of cold water and repeat cooking the remaining pasta. Drain and dry the pasta.
Rather than layering, put all the pasta in a buttered 9x13-inch flameproof baking dish, then add the meat sauce, white sauce, 11/2 cups of the grated cheese, and the melted butter. Swirl all together and top with the remaining grated cheese. May be made ahead to this point and refrigerated.
Preheat the oven to 350 degrees and bake until very hot, 10 minutes if freshly made, longer if made ahead and refrigerated. Freezes and reheats well.
Nathalie Dupree is the author of 13 cookbooks, most recently the James Beard award-winning "Mastering the Art of Southern Cooking." She lives in Charleston and may be reached through Nathaliedupree.com
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subset: commoncrawl


text:
A digital parallel processing system wherein a plurality of nodes communicate via messages sent over an interconnection network. Messages are maintained in strict chronological order even though sent by nodes where several sources are generating messages simultaneously. A network adapter is described for interconnecting the processor and its associated memory to a network over a bus. The adapter includes an adapter associated memory programmable into a plurality of functional areas, said functional areas including a send FIFO for storing and forwarding messages to said network from said processor; a stack list for queueing in strict message order activation commands for said send FIFO; and an adapter program area for storing adapter program instructions which control the storing of messages to said send FIFO; and control means responsive to said stack list for executing said adapter program instructions in said strict message order without processor intervention.
1. A network adapter for interconnecting a processor and its associated memory to a network over a bus for sending direct memory access (DMA) and immediate messages from said processor to said network under control of activation commands, comprising:
an adapter associated memory programmable into a plurality of functional areas, said functional areas including
a send FIFO for storing and forwarding DMA and immediate messages to said network from said processor;
a stack list for ordering the sending of DMA and immediate messages to said send FIFO; and
an adapter program area for storing adapter program instructions which control the storing of DMA messages from said processor's associated memory to said send FIFO and for storing immediate messages from said processor;
said processor being operable to store at least one of said DMA messages to its associated memory and to send an activation command to said stack list for each of said DMA messages, thereby commanding the network adapter to read in order said message from the processor's associated memory via direct memory access for sending said message to said send FIFO and network;
said processor being further operable to send at least one of said immediate messages to said adapter program store area and an activation command to said stack list for each of said immediate messages directly to the network adapter without storing said messages to its associated memory;
said activation commands for said DMA messages and said activation commands for said immediate messages being queued in strict order into said stack list; and
a controller responsive to activation commands stored in said stack list for transferring immediate messages to send FIFO and for executing said adapter program instructions for transferring DMA messages to said send FIFO, whereby DMA and immediate messages are transferred to said send FIFO in said strict message order without processor intervention.
2. The network adapter of claim 1 wherein said controller, responsive to said adapter program instructions, executes direct memory access to memory associated with said processor to control the storing and forwarding of processor messages without processor intervention.
3. The network adapter of claim 1 wherein said controller is responsive to said adapter program instructions to control the storing and forwarding of said adapter program instructions to said send FIFO.
4. The network adapter of claim 1 wherein said controller fetches and executes said adapter program instructions sequentially in the order determined by said stack list.
5. The network adapter of claim 1 wherein said stack list contains a plurality of entries, each entry being a pointer to a plurality of adapter program instructions.
6. The network adapter of claim 5 wherein said controller executes processor commands received from said bus to add pointers to said stack list.
7. The network adapter of claim 6 wherein said stack list is a FIFO which orders entries by adding the most recently received entry to the bottom of said stack list.
8. The network adapter of claim 5 wherein said controller sequentially accesses pointers in said stack list, and responsive to said sequentially accessed pointers locates and executes the corresponding adapter program, and removes said accessed pointer from said stack list.
9. The network adapter of claim 8 wherein said stack list is a FIFO.
10. A network adapter for interconnecting a processor and its associated memory to a network over a bus for sending direct memory access (DMA) messages and immediate messages from said processor to said network under control of activation commands, comprising:
an adapter memory including a send buffer, a program store, an immediate message store, and a send pointer list;
said send buffer storing and forwarding said DMA and immediate messages in order to said network from said processor;
said program store storing direct memory access (DMA) programs for controlling the network adapter to read DMA messages from the processor's associated memory via direct memory access and to
send DMA messages to said send buffer and network, and for storing and holding immediate DMA programs including immediate messages, until said messages are sent in order to said send buffer and network; and
said send pointer list queuing activation commands;
said processor being operable to store at least one of said DMA messages to its associated memory and to send one of said activation commands to said pointer list for each of said DMA messages;
said processor being further operable to send at least one of said immediate messages over said bus directly to said program of said adapter memory and to send one of said activation commands to said pointer list for each of said immediate messages;
a plurality of activation commands for said DMA messages and said immediate messages being queued in strict order into said pointer list; and
an adapter control responsive to said activation commands for transferring immediate messages to send buffer from said adapter program store and executing DMA programs for transferring DMA messages to said send buffer;
whereby said DMA and immediate messages transferred to said send buffer are in strict sequential order without processor intervention.
11. The network adapter of claim 10 wherein each of a plurality of said activation commands includes an address within said adapter memory of a corresponding DMA program.
12. The network adapter of claim 11 wherein each said plurality of activation commands further includes indicia identifying whether said DMA program is an immediate DMA program.
13. The network adapter of claim 12 wherein said adapter control is responsive to receipt of an immediate DMA program from said processor for adding a corresponding activation command to the bottom of said send pointer list.
14. Method for controlling the transfer of messages from a nodal processor and its associated memory through a network adapter to an interconnection network, said messages including direct memory access (DMA) messages and immediate messages being transferred under control of activation commands, comprising the steps of:
storing said DMA messages to said associated memory of said nodal processor;
storing said immediate messages in an adapter memory within said network adapter;
storing activation commands for said DMA and immediate messages in a send FIFO stacked list within said network adapter;
sequentially accessing said send FIFO stacked list to control the storing of said DMA and immediate messages to a send FIFO buffer; and
transferring said DMA and immediate messages from said send FIFO buffer to said interconnection network in sequential order.
15. The method of claim 14 wherein said storing steps include storing messages in said program store in other than strict sequential order, and storing pointers in said stacked list in strict sequential order.
16. The method of claim 15 wherein said transferring step includes sequentially accessing said stacked list to address and transfer said messages to said send FIFO buffer.
1. Technical Field
This invention relates to digital parallel processing systems, wherein a plurality of nodes communicate via messages sent over an interconnection network. In particular, this invention handles and keeps in chronological order the messages sent by each node when several sources are generating messages simultaneously.
2. Descriprion of the Prior Art
Known in the art is the use of network adapters for interfacing each node in a parallel system to a communication network. Such network adapters normally implement message buffers, usually a send First In First Out (FIFO) stack or buffer containing a plurality of messages to be sent to the network, and a receive (RCV) FIFO containing a plurality of messages which have been received from the network. The send FIFO stores and forwards messages to the network. The problem with this prior art scheme occurs when messages stored to the send FIFO can be generated from several sources, such as hardware controlled Direct Memory Access (DMA) operations and software controlled direct writes to the send FIFO using Programmed Input/Output (PIO) instructions to transfer data from processor registers directly into the FIFO. The problem is in regards to keeping the messages in order, as most parallel message passing systems require in-order message delivery, while maintaining DMA efficiency; that is, the purpose of DMA operations is to provide higher performance by enabling the processor and DMA channel to function simultaneously in an over-lapped manner. The two requirements of keeping message order and maintaining DMA efficiency are in direct conflict with each other. Typical solutions provide either message order or DMA efficiency, but not both. That is, efficient DMA message systems have been devised without message ordering, and message ordering systems have been implemented without supporting simultaneous overlapped DMA operations.
However, if solving the message ordering problem defeats the overlapped capability of DMA, it is not a solution at all--yet that is the typical approach. That is, the conventional way of keeping the messages in order is to defeat the overlap capability. This involves commanding one DMA operation at a time from the processor and requiring an interrupt when the DMA write to the send FIFO has completed. In response to the interrupt, processor software would then decide which message to write to the FIFO next--another DMA message or a PIO message. In this way, the software would directly control keeping the messages in order. However, because the processor must control the message ordering on a real time basis, this leads to a large loss of processing power. This additional processing slows the message handling and takes away much of the capabiltiy to do calculations in parallel with the DMA operations.
The concept of using a DMA controller to increase data transfer performance and to off-load the data transfer task from being performed under the direct control of a processor is known in the art. In one such solution, a DMA channel is implemented in hardware comprising channel registers for storing transfer parameters (address and byte count), registers for storing control parameters (status and command), a data assembler circuit for converting serial input/output (I/O) data to parallel memory data, and a channel control circuit that controls the registers and assembler. This approach requires continuous interaction between the processor and the DMA controller, such that one DMA operation at a time is commanded from the processor. When the DMA transfer is complete, the processor receives an interrupt to inform it that it can command another DMA operation. This type of interactive processing defeats much of the potential performance advantage gained by the use of the DMA controller.
Several improvements have been made on the basic DMA technique described above without really changing the most important one-at-a-time interactive approach. In one such improvement, processor and DMA access to memory are interleaved more efficiently using a processor unit containing a DMA controller having concurrent operation with the processor by dividing address and data into two parts.
In a major improvement, a DMA controller is operated to scatter or gather data into different areas of memory in a single operation. This is accomplished by using a buffer descriptor list (BDL) stored in a FIFO at the DMA controller, the BDL containing a plurality of buffer descriptor words (BDWs)--one for each part of the scatter/gather operation. The BDWs contain a memory address from where the data is to be accessed plus a byte count to define the length of the transfer. The local processor can preload the BDL with BDWs whenever the BDL has an available location, and these processor loads can be overlapped with the DMA operation. This approach works well for disk and tape units that deal with strictly DMA transfer-type operations. However, a more flexible approach is required for message transfer over an interconnection network in order to keep messages flowing at the highest possible performance over the network while providing for handling a mixture of message types, such as the DMA transfer of long messages intermixed with short messages sent directly from the processor without using the DMA function. Also, and of most importance, is the need to provide for mixing messages from different sources while at the same time maintaining the correct order of delivery of the messages. For message passing systems it is usually a requirement that messages be delivered in strict order or a system malfunction will occur.
In yet another improvement, the one-at-a-time interactive approach is avoided by using queue FIFOs which are similar to buffer descriptor lists (BDLs). In this technique, the DMA operation is partitioned into two queue FIFOS. First, a work FIFO contains a list DMAs to be done (same as BDLs). And second, a completion FIFO lists the BDWs for DMAs that have been completed. In this system, the processor can read the completion FIFO to determine which DMAs have completed. This is a twist on keeping track of which DMAs have completed. Another such twist provides a DMA priority contention scheme amongst multiple devices on the same bus.
Finally, in still another approach known in the art, both send and receive data FIFOs are implemented as part of an intelligent I/O processor for the purpose of DMA transferring data in either direction between global memory and the FIFOs.
However, none of the above solutions known in the art intermix DMA and processor and other generated messages while at the same time retaining message order and accommodating a mixture of message types essential for optimum performance in an interconnection network.
The present invention solves these problems by using a unique method and hardware apparatus at the network adapter. The solution both increases overlapped processing efficiency, while at the same time maintaining message order and relieving the software of this burden.
A network adapter is provided for interconnecting a processor and its associated memory to a network over a bus. The adapter includes an adapter associated memory programmable into a plurality of functional areas, said functional areas including a send FIFO for storing and forwarding messages to said network from said processor; a stack list for queueing in strict message order activation commands for said send FIFO; an adapter program area for storing adapter program instructions which control the storing of messages to said send FIFO; and control means responsive to said stack list for executing said adapter program instructions in said strict message order without processor intervention.
FIG. 1 is a diagram of a typical digital network showing the interconnection of a network node to the network and the components of the network node according to the preferred embodiment of this invention.
FIG. 2 is a block diagram showing the format of a send DMP pointer, a plurality of which comprise a stacked list.
FIGS. 3A, 3B, 3C and 3D, arranged as shown in FIG. 3, are a block diagram showing stacked lists and how they are used to point to indirect PIO messages according to this invention.
FIG. 4 is a block diagram showing the format of a send immediate DMP control word.
FIGS. 5A, 5B, 5C and 5D, arranged as shown in FIG. 5, are a block diagram illustrating stacked lists and send DMP processing, including the insertion of DMA and indirect PIO messages into the send FIFO according to this invention.
The invention comprises two major elements which work together to improve the performance of parallel systems using direct memory access (DMA) operations and requiring ordered message delivery. These elements are (1) stacked DMA writes to the send FIFO, and (2) indirect PIO processor message write commands to the same send FIFO.
Stacked DMA writes permit the processor to stack numerous pending DMA operations at the network adapter, and represent the first major element of the invention. The adapter executes them in order, and frees the processor to continue. This network adapter is programmable to interrupt the processor or not when it completes a specific DMA operation. A standard method for commanding the network adapter to perform a DMA operation is used in connection with the invention, which is to send a small DMA program (DMP) to the network adapter followed by a command to execute the DMP. The DMP contains information about a specific DMA operation to be performed, including the starting address of where DMA data is to be fetched from system memory, the word count of the DMA transfer, the FIFO number where the DMA data is to be placed in the network adapter, and control information such as the data transfer direction. The processor first writes one or multiple DMP's to specific addresses in adapter memory that have been reserved for DMP's. The size of the memory reserved for DMP's is variable and, in this preferred embodiment, is specified by the processor during intialization. This size depends on how many DMP's the processor must store at any given time. The storing of DMP's is done at any time prior to issuing the DMP start command, and a DMP can be reused as many times as desired without being restored from the processor. To execute a prestored DMP, the processor writes a DMP start command to the send DMA stack specifying the starting address in adapter memory of the DMP it wants to execute, and the adapter executes the DMP's in strict order. The adapter hardware contains a stacked list of pending send DMA's in adapter memory. This stack also functions as a FIFO to queue DMP starting commands. Send DMP's are activated by the command at the top of the list (queue) and processed one at a time; they are kept in order by the FIFO queued list. The stacked list can contain from 1 to L DMP start commands, where the DMP start command is basically a pointer to a prestored DMP in adapter memory.
Indirect programmed input/output (PIO) processor message write commands to the same send FIFO represent the second key element of the invention. The basic stacked lists provide the ordering capability amongst DMA operations. However, a further ordering problem arises when both DMA messages and processor PIO messages (messages written directly to the send FIFO and which bypass the stacked lists) are being intermixed to the same send FIFO. The problem occurs if the processor has stacked DMA operations to be processed in order, less than all of these have been passed to the FIFO, and then the processor writes a PIO message directly to the same FIFO intending that it be executed after all stacked DMA operations. In this instance, the PIO message is written to the FIFO out of order. If the processor wanted the PIO message stored after the last stacked DMA operation, instead of randomly, an out of order error is caused.
In accordance with this invention, this out-of-order error is avoided by using indirect PIO message write commands. These give the software the option of keeping the PIO messages in order by sending them through the same stacked list of start commands in the adapter used to start DMP's. Thus, PIO messages and DMA messages can be started by the same stacked list. This is accomplished by first storing a PIO message temporarily into adapter memory and thereafter writing a PIO start command to the stacked list that will be executed in strict chronological order. Thus, both PIO and DMA start commands are maintained in the same stacked list. The adapter inserts the PIO message into the send FIFO in order by executing an indirect PIO start command when its start command reaches the top of the stacked list. The PIO message goes indirectly from temporary adapter memory into the send FIFO under the control of the adapter.
An indirect PIO message is created by the processor storing a PIO message to temporary adapter memory by adding one control word in front of the normal PIO message. The word added contains the word count of the PIO message to be stored and the high order bit is set to indicate that this an indirect PIO. An indirect PIO comprises the first control word and the PIO message data, which is added to the send FIFO, the amount of such data being equal to the word count in the control word. The processor then stores the control word followed by data as an indirect PIO operation to temporary memory locations in the adapter memory, and not to the FIFO directly. Next the processor activates the indirect PIO operation by writing an indirect PIO start command to the stacked list. The indirect PIO start command points to the location in adapter memory where the indirect PIO is temporarily stored. The hardware in the network adapter adds this command at the bottom of the stacked list, and executes it in order along with other PIO and DMA messages in that list, when it reaches the top of the list. This keeps the PIO messages in order, instead of directly storing them to the send FIFO. The hardware executes the indirect PIO by moving the amount of data specified by the control word preceding the PIO message. The control word is destroyed after being used and is not stored to the send FIFO. Thus, PIO's and DMA's can be intermixed in any manner in the stacked list, and the hardware maintains message order without stalling or delaying the processor.
Referring to FIG. 1, a typical network node 100 implementing the invention is shown, including a processor 104, a processor I/O bus 109, and a network adapter 110. Node 100 attaches to one port of interconnection network 102 over full duplex bus 115, and includes network adapter 110. Adapter 110 includes adapter memory 118, which provides stacked list 117, DMP programs & indirect PIO messages 12, adapter FIFOs 116 including send FIFOs 111 and receive FIFOs 119, adapter registers 113 and 115, for attachment to and processor I/O bus 109 and network bus 107, respectively, and controls 114. Processor 104 interfaces directly to on-chip cache 103, system memory 106, and other I/O adapters 108 interface processor I/O bus 109.
In operation, network adapter 110 converts processor I/O bus 109 for communication to network 102. Processor 104 sends commands over I/O bus 109 to control network adapter 110, writes messages to send FIFO 111, and reads messages from receive FIFO 119. In addition, network adapter 110 is a bus master in that it can be commanded to read or write messages from and to system memory 106 using DMA operations. In accordance with this embodiment of the invention, DMA messages are read from system memory 106, over processor I/O bus 109 and stored in send FIFO 111. Herein, send FIFO 111 is located in adapter memory 118, which is part of network adapter 110.
Network adapter 110 can function as a slave or master on processor I/O bus 109.
As a slave, network adapter 110 responds to processor I/O commands (PIOs) issued directly by processor 104 software. PIO commands are capable of reading or writing adapter memory 118, adapter registers 113 and 115 and adapter FIFOs 116. Network adapter 110 differentiates which entity 113, 115 and 118 is to be read or written based on the address to which the PIO command is issued.
As a master, network adapter 110 arbitrates use of processor I/O bus 109. When acknowledged, adapter 110 owns bus 109 for a period of time and, for that period, can use bus 109 to read or write system memory 106 directly without interference with the execution of instructions in processor 104, which are usually executed from cache 103. This method of data transfer directly to/from system memory 106 is referred to as Direct Memory Access (DMA).
Network adapter 110, to be truly bi-directional with respect to network 102, attaches thereto via bi-directional bus 107, which includes at least one interface 115 for sending messages to the network, and at least one for receiving messages from the network. Messages sent by node 100 to network 102 are either transferred directly from processor 104 using PIO commands or by DMA directly from system memory 106 under control of network adapter 110. In either case, all messages to be sent to network 102 are routed over processor I/O bus 109 to network adapter 110, where they are directed through control logic 114 and stored temporarily into send FIFO 111. Control logic 115 then reads the message from send FIFO 111, and sends it to network 102 over bus 107. Network adapter 110 also supports the reverse operation, where messages arriving into network adapter 110 from network 102 are routed by control logic 114 to RCV FIFO 119. The message is temporarily stored in RCV FIFO 119 until a DMA operation is initiated at network adapter 110 to transfer the message over processor I/O bus 109 to system memory 106.
For send operations, each DMP is started by commands referred to as send DMP pointers, which point to a starting address in adapter memory 118 of the DMP program 112 to be executed. The send DMP pointer list 117 is a separate FIFO from send/receive FIFOs 116 for queueing DMP starting commands. Send DMPs 112 are processed one at a time and kept in order by pointer list 117. Pointer list 117 contains from one to L (say, 64) send DMP pointers, each pointing to a DMP 112 that has been commanded to be executed. Processor 104 software activates a send DMP 112 by writing a send DMP pointer to send DMP pointer list 117 in adapter memory 118.
Referring to FIG. 2, in connection with this embodiment, send DMP pointer 200 contains starting address fields 202, 204 of a prestored DMP program 112, and controls including word boundary address alignment field 202; a don't care field 206; spare bits 208 and 210; bit 212 for indicating, when on, an interrupt upon DMP program completion; bit 214 indicating, when on, immediate DMP enabled (program valid); and bit 216 indicating, when on, DMA enabled (program valid).
Referring to FIG. 3, a description will be given of adapter 110, including a description of stack lists 117 and controls 114 (FIG. 1) used to point to indirect PIO messages 112 (FIG. 1) in accordance with this embodiment of the invention.
Adapter memory 118 includes a plurality of DMP programs 120 in DMP programs & indirect PIO messages area 112, and send DMP pointer list 117. DMP program 120 includes four fields, including word count of DMA transfer 170, FIFO address 171, system memory address 172, and read/write and other controls 173. For purpose of this embodiment, by way of example, up to sixty four such DMP programs 120 can be written in area 112 of adapter memory 118 by PIOs from processor 104. Send DMP pointer list 117 in adapter memory 118 is a FIFO stack list, or circular buffer, of up to sixty four 32-bit send DMP pointer words 200 (FIG. 2).
Send FIFO control logic 124, part of controls 114, responsive to a send list not empty control bit 126 indicating that send list 117 is not empty, provides start DMP load address 127 and increment 128 signals to send DMP program address counter 122. Send DMP program address counter 122 provides a select DMP program signal 123 to address multiplexor 146, which provides on its output 147 an address to adapter memory 118. PIO address counter 142 provides, as is represented by line 139, a PIO address to address multiplexor 146 and a PIO write address to address compare 138. PIO write data register 144 provides processor PIO commands over data bus 140 for writing DMP programs 120 or pointers to the bottom of DMP pointer list 117, and for initializing PIO write data to stack locator register 133. Data accessed from adapter memory 118, as is represented by line 162, provides 32-bit pointer words read from pointer list 117 or DMP programs 120 to DMP program execution logic 150 and send DMP program address counter 122. Composite address 141 for reading or writing from/to send pointer list 117 is assembled by concatenating hardware 136 from high address bus 134 and low address bus 135, and fed to address multiplexor 146. Stack locator register 133 outputs are fed to hi address bus 134 and address compare 138, which provides on its output 148 a PIO to pointer list signal to the select list input of address multiplexor 146. Write counter 131 and read counter 132 registers are multiplexed at block 130 to form the low order address bits 135, and are fed to counter compare 137, which generates and provides the send list not empty signal 126 input to send FIFO control logic 124.
In operation, the apparatus of FIG. 3 implements in network adapter 110 a pointer list as a 64-word circular buffer 117. Circular buffer 117 is controlled by two six bit counters, read counter 132 and write counter 131. These counters 131, 132 are initialized to all zeroes, so that when the first send DMP pointer 200 is written to list 117 at, say, location 00h, write counter 131 is incremented to 01h. Write counter 131 is incremented after each pointer 200 is stored to list 117, so it always points to the tail, or bottom 151 of that list and defines the address 147 where the next pointer 200 is to be written to list 117. Read counter 132 remains at 00h until the DMP 120 in list 117 pointed to by field 204 (FIG. 2) has been executed, then it is moved to 01h. Thus, as read counter 132 is incremented after the DMP program 120 to which its present address 147 points (that is, indirectly points by way of field 204 in the pointer 200 in stack 117 at the location addressed in adapter memory by address 147, which in turn is derived from read counter 132) is executed successfully, it (read counter 132) always points to the top, or head 153, of send DMP pointer list 117. In this manner, read counter 132 initally defines the address of the next pointer 200 to be processed in stack list 117, and during the execution it defines the address of the pointer in stack list 117 to the DMP program 120 that is presently being executed.
Read counter 132 and write counter 131 feed comparator 137 to detect whether their contents are equal or not. Upon detecting that counters 131 and 132 are not equal, comparator 137 informs send FIFO control logic 124 that list 117 is not empty, but that a send DMP pointer 200 is pending. This causes send FIFO control logic 124 to process the next send DMP pointer 200, if no previous send message operation is active at network adapter 110.
Referring further to FIG. 3, the apparatus of the invention operates to activate send DMP programs 120. Circular buffer 117, which in this embodiment uses sixty four locations of adapter memory 118, contains a list of send DMP pointers 200 pointing (by way of DMP program starting address 204) to DMP programs 120 that have been activated for execution. Thus, processor 104 can activate up to sixty four list 117 entries and have them held pending in the FIFO order determined by the sequence of their storage to the list.
Execution of a DMP program 120 starts with processor 104 sending one or many DMP programs 120 to adapter memory 118 over processor I/O bus 109 and thence to network adapter 110, as shown in FIG. 1. Processor 104 has direct access to write all adapter memory 118, incuding send DMP pointers 200 in send pointer lister 117, and send DMP programs 120, via PIO operations. PIO writes are not DMAs, but come directly from processor 104 registers (not shown) when processor 104 executes an I/O write instruction (one of the many instructions that state-of-the-art processors are capable of executing.) A PIO operation includes address and data information. The address defines the device, register, adapter, memory location, or list that is to be written; while the data defines the information to be written at the selected address. The base address of where in adapter memory 118 the pointer list 117 is located is programmable by processor 104 via PIO writes. Stack locator, or base address register 133 points to the location in adapter memory 118 of the base of pointer list 117 and is loaded in adapter 110 hardware by processor 104 software before activating any DMP program 120 or writing any DMP pointer 200 to stack list 117. Register 133, when addressed by PIO address counter register 142, is loaded from register 144 over data lines 140. Register 133 is usually loaded during initialization of network adapter 110, and once initialized will define the specific sixty four locations in adapter memory 118 which will be used for stack list 117. Thus, the location of stack list 117 in adapter memory 118 is selectable and controlled by the processor 104 software. The path that processor 104 uses to write to register 133 is over I/O bus 109 to network adapter 110. At network adapter 110, address and data sent by a PIO write is stored in registers 142 and 144, respectively. If register 142 addresses the stack locator register 133, the value stored in register 144 is moved over data bus 140 to register 133, thereby initializaing register 133 and defining the programmable base address of stack list 117 in adapter memory 118.
After initialization, adapter 110 is ready to receive PIO writes of write DMP programs 120 into adapter memory 118 at location 112 (FIG. 1; a single such DMP program 120 is shown in FIG. 3.) Such DMP programs 120 can be written anywhere in adapter memory 118, except to the areas of adapter memory 118 that have been assigned to stack list 117, send FIFO 111, or receive FIFO 119. A PIO write command is used to store each word 170, 171, 172 and 173 of DMP program 120, one word at a time, through registers 142 and 144. To write DMP programs 120 into adapter memory 118 at location 112, register 142 supplies the address of the adapter memory 118 location to be written directly through multiplexor 146 to memory 118, while register 144 supplies data over data bus 140 directly to adapter memory 118 to write DMP programs 120. Whether bus 140 contains DMP programs 120 or send DMA pointers 200 is determined by whether or not the address in register 142 is equal or not to the address in register 133, as hereinafter described. After a DMP program 120 has been written to adapter memory 118 area 112, it can be started at anytime by writing the DMP's starting address 204 to stack list 117 in a send DMP pointer 200 using a PIO write operation.
Network adapter 110 examines the address of every PIO write operation to determine if it is for the stack list 117 or not by comparing in address compare logic 138 the address issued by the PIO write and stored into register 142 to the address in stack locator register 133. If the two address 142 and 133 compare equal, concatenating hardware 136 takes the high order base address bits 134 from stack locator register 133 and replaces the low order six address bits coming from register 133 with the six low-order bits 135 from write counter 131. This way, the hardware keeps track of the location of the tail 151 of stack list 117, and the software need only point to the base address of stack area 117, which has all six low order address bits equal to zero. This relieves the software of the task of keeping track of which stack list 117 location to write next. Likewise, a read of stack list 117 is performed in response to an address 141, 147 that is concatenated at 136 from read counter 132 and register 133 over address lines 134 and 135, respectively. Register 133 locates the base area in memory 118 where stack list 117 is located, and read counter 132 selects the exact (one of sixty four) location to be read. When writing to stack list 117, processor 104 sends an address to address counter 142 equal to the base address held in stack locator register 133 to command the write of a send DMP pointer 200 to send DMP pointer list 117.
The processing of stack list 117 starts and proceeds automatically under hardware control of send FIFO control logic 124. Whenever stack list 117 is not empty, read counter 132 is not equal to write counter 131, and send list not empty signal 126 is on. Responsive thereto, send FIFO control logic 124 first reads the address pointed to by the read counter 132 to fetch the send DMP pointer 200 from adapter memory 118 list 117. This equates to using indirect addressing to find the DMP program 120 to be executed. Send FIFO control logic 124 concatenates the address of the next send DMP pointer 120 in adapter memory 118 by forming address 136 from the base address stored in register 133 over bus 134 and the six low order bits from read counter 132 over bus 135. The composite address 141 is sent through multiplexor 146 to line 147 to address adapter memory 118, and fetch the head of stack list 117, the next send DMP pointer 200 to be executed. The send DMP pointer 200, one word formatted as shown in FIG. 2, is read from memory 118, sent over memory read bus 162, and stored in send DMP program address counter 122. Address counter 122 uses field 204, 202 (bits 18 to 0) of the send DMP pointer 200 it contains to find the beginning of the DMP program 120 in adapter memory 118. In this way, the hardware accesses and then executes the selected DMP program 120, only one at a time. Send DMP program 120 is fetched from adapter memory location 112, one word 170-173 at a time, by gating address counter 122 through multiplexor 146 to provide the address of the first word of the DMP program. Adapter memory 112 reads the addressed location, the first word 170 of DMP program 120, to memory read bus 162 for storage to DMP execution logic 150. Control logic 124 then increments address counter 122, and repeats the same operation to fetch the next three words 171-173 of DMP program 120 to execution logic 150. When all four words are fetched from DMP program 120, control logic 124 stops the fetching of DMP words and execution logic 150 executes the fetched DMP program. When the fetched DMP program completes successfully, read counter 132 is incremented by one word and the next send DMP program 120 addressed by field 204 in the next sequential entry in stack list 117 is executed, if stack list 117 is not empty. Because send DMP programs 120 are executed sequentially until send pointer list 117 is empty, processor overlap is facilitated because processor 104 merely stores a DMP program 120 (or uses a previously stored DMP program 120 over again), commands its execution by writing to the associated send pointer list 117, and then moves on to the next processor 104 task while send messages within a list are kept in order at all times.
Indirect immediate PIO message write commands are used to assure processing of PIO messages in order. Send pointer list 117 automatically causes overlapped processing and keeps DMA operations in order. However, a further ordering problem arises when both DMA messages and PIO messages are being stored and intermixed in send FIFO 111. The problem occurs if processor 104 has stacked DMA operations to be processed in order in stack list 117, and then writes a PIO message directly to send FIFO 111 before stack list 117 has completed all DMA's. The PIO message will, in that instance, be written to send FIFO 111 out of order. If processor 104 requires that a PIO message be kept in order and stored after the last stack list 117 DMA operation stored at that time, an out of order error is caused. As will be described hereafter in connection with FIGS. 4 and 5, by this invention, that error is avoided by use of the indirect immediate PIO message write command. In this manner, processor 104 software can choose to make the adding of the PIO message to send FIFO 111 a network adapter 110 controlled operation, for processing just like DMA's.
Referring to FIG. 4, send immediate DMP control word 240 includes word alignment field 242, word count field 244, don't care field 246 and valid count bit 248.
Referring to FIGS. 4 and 5, in this embodiment, network adapter 110 operates to maintain correct message order. This is accomplished as follows. Processor 104 software adds one control word 240 in front of the normal PIO message to make it into an immediate DMP program 121. The word added contains the word count 244 of the immediate message to be stored and the high order bit 248 is set to indicate that this program is valid. Field 246, bits 16 through 30, are undefined. Herein, by forcing bits 242 to zero, the word count of immediate PIO message is four bit aligned, which means a message 121 must begin and end on word boundaries. Thus, an immediate DMP program 121 contains the control word 240 of FIG. 4 followed by the PIO message, which is the data to be added directly to send FIFO 111, including the first through Nth words 281-283. The number of data words 240-283 added to send FIFO 111 is equal to the word count field 244 in control word 240. Processor 104 then stores the immediate DMP program 121 via a PIO write operation to adapter memory 112, just like it would store a normal DMP program 120, as explained in connection with FIG. 3. Next, processor 104 activates the DMP 121 by writing a send DMP pointer 200 to stack list 117 which points to the address in adapter memory 112 of the immediate DMP program 121. Send DMP pointer 200 (FIG. 2) is used to differentiate between a DMA or immediate program using control bits 30 and 31 in fields 214 and 216, respectively. Field 216 is set to indicate that the program is a normal DMP program, while field 214 is set to indicate an immediate DMP program. The settings of fields 214 and 216 are programmed to be mutually exclusive. Network adapter 110 adds this DMP pointer 200 at the bottom 151 of stacked list 117 of pending hardware operations using write counter 131, as previously described (FIG. 3). The storing of the pointer 200 to bottom 151 of stack list 117 causes the PIO message 240, 281-283 contained in the immediate DMP program 121 to be added in order to send FIFO 111. Immediate DMP program 121 is processed when its send DMP pointer 200 moves to the top 153 of stack list 117. Send FIFO control logic 124 initially fetches pointer 200 to the immediate DMP program 121 and accesses the program words 240, 281-283 in the same way as previously described with respect to fetching a normal send DMP pointer 200 and DMP program 120. Subsequent processing of the immediate DMP program will be described hereafter in connection with FIG. 5.
Referring to FIG. 5 in connection with FIG. 3, the hardware required for processing of an immediate DMP program 121 will be described. FIG. 5 is identical to FIG. 3, except for the following: immediate DMP program 121 is shown (but does not replace DMP program 120); and multiplexor 164, immediate data register 168 and immediate word counter 166 are added to the logic. Inputs to register 168 and counter 166 are from stack list 117; the output of immediate word counter 166 is fed as end signal 160 to send FIFO control logic 124, and of immediate data register 168 as ordered PIO message write signal 175 to multiplexor 164, the other input to which is the output of PIO write data register 144, and the output of which is write PIO message 161 to immediate DMP program 121 and send FIFO stacked list 117.
In operation, as previously noted, field 214 (bit 30) being set in send DMP pointer record 200 informs hardware control logic 124 that the record 200 being executed represents an immediate DMP program 121. In this case, control hardware 124 routes the first word 240 of the immediate DMP program, as it is fetched from the adapter memory 118 over bus 162, to immediate word counter 166, rather than to DMA execution logic 150. Thus, counter 166 contains the word count 244 of the message 121 being accessed from adapter memory 112. As the second 281 and each successive word 282-283 of immediate DMP program 121 are fetched from adapter memory 118, one word at a time, they are put sequentially into immediate data register 168. As each word is stored into register 168, word counter 166 is decremented by one word count (four bytes), and the address in counter 122, which is fetching the program, is incremented by one word count (four bytes.) Each word stored to register 168 is immediately routed through multiplexor 164 onto the write data bus 161 to adapter memory 118. The immediate data words 281-283 are immediately written back into adapter memory 118 one at a time, but they are written to a different area of adapter memory: send FIFO 111. (Word 240 is only stored to immediate word counter 166, not to adapter memory 118.) For simplicity, FIG. 5 does not show send FIFO 111, but FIG. 1 shows how send FIFO 111 is located in a different area of adapter memory 118. Thus, the immediate operation is basically a transfer of the PIO message 121 from one area of adapter memory, DMP programs and indirect PIO messages 112, to a different area, send FIFO 111. Data is added to send FIFO 111 in strict order using this method. The PIO message 121 is held temporarily in message area 112 until it can be transferred to its correct destination, send FIFO 111, in strict order.
The immediate operation continues one word at a time until the immediate word counter 166 decrements to zero. This signifies the end of the immediate data. After the last word 283 is successfully written to send FIFO 111, end signal 160 is sent from counter 166 to control logic 124 to terminate the operation. Then read counter 132 is incremented by one word and, as previously described, the next send DMP program 120 is accessed from stack list 117 and executed, if the stack is not empty. Send DMP types (normal 120 and immediate 121) can be intermixed in any manner, and are executed sequentially in proper order (back-to-back) while send list not empty signal 126 is true, signifying send pointer list 117 is not empty.
The method and apparatus of the invention present an improved technique of ordering messages with respect to a nodal processor and an interconnection network which maintains Direct Memory Access (DMA) efficiency, enabling DMA operations to provide maximum performance advantage by executing in a fully overlapped manner in respect to the nodal processor.
While the invention has been described with respect to preferred embodiments thereof, it will be apparent that the foregoing and further modifications and extensions may be made without departing from the spirit and scope of the invention.
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Dragon Pussy, a rocket platformer made during Nordic Game Jam 2013 on the theme "Grotesque".
X – Start the game, jump, hold to rocket.
Left- right-arrows – Walk and control rocket.
Hold 1 to restart the game.
"This is as far as we got"
Guys, you're so awesome.
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Hello, I really like this grotesque game!
i love the concept and love the graphic style!
Witch tool have you use to do it?
We need MOAR levels!!!!1!!1
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this is a very fun game! But wtf "Dragon >Pussy<" o_O


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Beadling's play-off excitement
by Ashley Houghton
Young defender reacts following win over Liverpool.
U18 defender Tom Beadling could not hide his elation as the young Black Cats secured their passage into the play-off stage of the Barclays U18 Premier League.
Beadling, who only returned the fold early in 2013 after a serious back injury, starred as goals from George Honeyman and James Stinson sent Sunderland on their way to a 2-0 victory over Liverpool.
And Beadling told safc.com that the players are delighted to have confirmed their place in the play-off mix.
"It's a great feeling to win, we knew what we had to do today so to go and win the game in the way we did was great," he said.
"The lads are buzzing because we had to dig in at times and 1-0 is a dangerous lead because if they nicked one, we had to score.
"I'm delighted to get the win and hopefully we'll push on in the next game now."
Beadling was also full of praise for Honeyman and Stinson who both struck superb finishes to edge out the Reds at the Academy of Light.
And the defender, who returned from a move to Australia to join up with the academy at the age of 13, says his focus is now on the play-off match next weekend.
"They were both great finishes and they come at good times as well; it really relieved the pressure," Beadling explained.
"It's the play-offs and anything can happen really."
Beadling featured for Kevin Ball's development squad in last week's 2-2 draw with Fulham; a performance Ball described as 'composed and assured'.
And Beadling says the experience of playing at Craven Cottage, at a higher level, was a great feeling.
"It was a great experience, I was absolutely buzzing," he said.
"It was good to come back today [to the under-18's] and get the win we're all delighted – it was just reward for our hard work."


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Professional Development Tools & Resources
QBG's School Programs
- enrich your students' experience by bringing your class to the Garden.
NYC Compost Project in Queens
- QBG is a proud host of this city-wide program that offers training, demonstrations and a Master Composter Certificate.
-- learn more about QBG on our You Tube channel
-- a citywide, public-private program with an ambitious goal: to plant and care for one million new t
rees across the City's five boroughs over the next decade.
Grow to Learn NYC
- plenty of school garden resources, including mini grants and garden-based classroom activities.
GrowNYC's Greenmarket Youth Education Program
-- school tours and "Meet Your Farmer" classroom visits.
-- programming and material support to over 500 community gardens in New York City. Workshops, which are the access point for supplies, are held every month of the year, covering gardening basics to more advanced farming and community organizing topics.
Whole Systems Integrated Sustainable Design for Education (WISE)
-- a step by step program to educate students about sustainability at their school, ending in a hands-on project. The website provides material for students to observe what resources their school has, research a sustainability project, and carry out an action on their school to improve how resources are used.
Microbe Zoo
-- discover the many worlds of hidden microbes!
Science Formative Assessments
- We love formative assessments! QBG's Professional Development staff makes sure to incorporate them in all of our lessons and this book is a terrific guide.\
For information on PD scholarships with QBG and other NYC gardens, visit the
City Gardens Club Scholarship Program
Plant Care Sheets
- Market Blooms offer a plethora of great tips organized by plant name.
Copyright 2006 Queens Botanical Garden | 43-50 Main Street, Flushing, NY 11355


text:
garden.com > Birds & Wildlife > Bird Feeders & Accessories > Bird Feeders > Item # G28274
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Sturdy & Easy to Clean
Faceted Ruby Hummingbird Feeder, by Schrodt. This handcrafted cobalt and red colored blown glass nectar bottles are sure to attract hummingbirds and they look in your garden habitat. Perches allow your hummingbirds to land, encouraging them to hang around for your viewing pleasure.
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Hanging Bird Feeder Squirrel Baffle - Green
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Parents Daily News Roundup
Wednesday, April 18th, 2012
Abducted Baby Found After Mom Slain in Texas
The mother of a woman who was shot to death as her newborn son was snatched from her arms outside a suburban pediatric center near Houston said her daughter died "trying to save her baby."
Parents of Dead Toddler Settle Tainted Wipes Lawsuit
The parents of a toddler who died after contracting a rare bacterial infection blamed on contaminated medical wipes have settled their lawsuit against the Wisconsin firms that made them.
Exposure to Air Pollution in Pregnancy May Boost Chances of Obesity in Kids
In a study published this week in the American Journal of Epidemiology, scientists at the Mailman School of Public Health at Columbia University found that exposure to air pollution during pregnancy may be associated with a greater chance of having heavier kids.
Boy Who Inspired Thousands to Join Bone Marrow Registry Dies
A 5-year-old boy whose story inspired thousands of people to become bone marrow donors died Monday after a lifelong battle with a rare immune disorder, the Boston Herald reported.
Parents Force Girl to Wear 'I like to Steal' Sign
Two parents in southwestern Illinois took the punishment of their 8-year-old daughter public by forcing her to wear a sign that read: "I like to steal from others and lie about it."
Tags: abduction, bone marrow donor, child obesity, discipline, kidnap, stealing, wipes | Categories: GoodyBlog, News


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Nobody will ever replace the one and only King of Pop, and today, on the 5th anniversary of his death, we celebrate the times when he, and others who were lucky enough to work with him, spread joy and love through music.
Nobody will ever replace the one and only King of Pop, and today, on the 5th anniversary of his death, we celebrate the times when he, and others who were lucky enough to work with him, spread joy and love through music.
Everybody knows Usher's a happily married family man (as you can learn from several of the tracks off Here I Stand). But we also know that a while back, Ush and Chili were pretty serious. Usher even bought the TLC hottie a rock, but broke it off before the two were engaged. A few months back Chili confessed to the world that Usher was "the one that got away. I love him very much and I will always love him. I don?t know how you love someone that deeply and just stop loving them."
Recently, Usher was asked about his ex's remarks in an interview with RWDmag.com. Usher had somem rather harsh words for Chili:
I mean, I think it?s a little unrealistic, I?m married [laughs], I?m not a boy. It?s been three years past, you know? But we all have unrealistic goals too. Like shoot, I will always forever love Katie Holmes and Halle Berry. I don?t feel anyway about it. It does appear maybe to be a plug for something. She got a record coming or something?
Here I Stand, Usher's new album, will be out at the end of May. But in the meantime its first single has already risen the Billboard charts to hit No. 1. "Love in This Club" is a slow, steamy jam with a guest appearance by Young Jeezy and lyrics like "They don't know what we doin'/ Let's both get undressed right here/Keep it up girl, I swear/ I'm-a give it to you non-stop/ And I don't care who's watchin'." Despite that, the track's producer, Polow da Don, insists the lyrics are not about having sex. This is confusing, to put it mildly. Anyway . . . we have 30 seconds of the video for you now. The clip features several super-famous guest stars, some slinky dance moves and a few stylish pairs of sunglasses — exactly what you want out of an Usher video. Check it out here before the video premieres next Monday, April 7.


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Temptalia Asks You – What is your stance on animal-testing and beauty products?
What is your stance on animal-testing and beauty products? Is it something that concerns you? Will you refuse to buy from a company that does? Do you make sure all your products are "cruelty-free"? Is it a non-issue for you?
Discussion and debate are highly encouraged, and we expect community members to participate respectfully. When asking a question, please check the FAQ section (above) for information about purchasing, price, dupes, and the like. If you have general feedback or need technical support, please contact us.
Comments that include advertisements, self-promotion, insults, etc. may be in violation of our comment policy and subject to deletion. Please see our comment policy for more information.


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Friday, Feb 27 4pm-9pm • Saturday, Feb 28 10am-8pm
Sunday, Mar 1 11am-4pm
Home Show Details
Sat Feb 28 10 am to 8 pm
Sun Mar 1 11 am to 4 pm
Peoria Civic Center
Adults (18+) $7.00
Seniors (60+) HALF PRICE!
Kids Under 18 FREE!
Pick up a coupon at any area CEFCU Member Center and get one free adult admission when you purchase an adult admission for $7.00
*On-site discount coupons not valid for on-line ticket purchases
Welcome to the Home Builders Association of Greater Peoria's website and directory for the 2015 Official Spring Home Show. The Official Spring Home Show will be held February 27, 28 and March 1, 2015 at the Peoria Civic Center. During the event, live updates will be available on our Facebook page. After the show, find out more about our members and the products/services they offer on the Association's web site at www.PeoriaHBA.com More>>
A Central Illinois exclusive ... walk through a display home built by Homeway Homes inside the Peoria Civic Center! This year's home is a ranch style plan, specially-designed for the show, and offers visitors the chance to walk through the home, gather information, and ask questions of the builder representatives. Show visitors have enjoyed the modular home display at the Official Spring Home Show for over a decade, and won't be disappointed this year!
Entertainment Schedule
Friday, February 27:
- 5:00 pm Chinese Acrobats
- 6:00 pm Flippenout Productions
- 7:00 pm Chinese Acrobats
Saturday, February 28:
- 11:00 am Flippenout Productions
- 12:00 pm Chinese Acrobats
- 2:00 pm Flippenout Productions
- 3:00 pm Chinese Acrobats
- 4:00 pm Flippenout Productions
- 5:00 pm Chinese Acrobats
- 6:00 pm Flippenout Productions
- 7:00 pm Chinese Acrobats
Sunday, March 1:
- 12:00 pm Chinese Acrobats
- 2:00 pm Flippenout Productions
- 3:00 pm Chinese Acrobats
CEFCU is sponsoring a special admission discount to the Show! Just stop by an area CEFCU Member Center to pick up your discount admission coupon good for one free adult admission when you purchase one adult admission (value $7.00). Coupons will be available at all Peoria-area CEFCU Member Centers beginning Feb. 15, while supplies last.
Site Map
Home | Show Map | Exhibitor List | Schedule at a Glance| Contact


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'Les Misérables' 25th anniversary tour hits ToledoWritten by Sarah Ottney | Editor in Chief | email@example.com
After years of performing the role of reformed convict hero Jean Valjean on Broadway and with touring productions of "Les Misérables," actor Andrew Varela has gone to the dark side.
For the 25th anniversary tour of the iconic musical, Varela will instead portray Javert, the police inspector who makes it his life's work to hunt down Valjean and bring him to justice.
"When I was a kid I liked Darth Vader more than Luke Skywalker," Varela told Toledo Free Press Star during a phone call from a tour stop in Providence, R.I. "So the idea of playing a bad guy always appealed to me."
However, Varela said he doesn't like to think of Javert as a bad guy; instead he enjoys the chance to humanize the character.
"One of the things I try to do is make it clear he's not trying to be a bad guy; he's just trying to do his job. He's just doing what he thinks has to be done," Varela said. "The reviews have noticed that and people always comment after the show they were struck by the humanity I brought to the role. Jean Valjean himself says 'You're just doing your job, I know.' I hope I'm bringing not only life but humanity to the character. I've found playing him has been wonderful."
Varela said one of his favorite parts of portraying Javert is singing "Stars."
"It's one of those songs you just get to belt out and has so much meaning," Varela said. "It's such an important plot point for my character. As an actor, you love the idea you get to sing this huge show-stopping number."
"Les Misérables" opened Nov. 8 at the Stranahan Theater, 4645 Heatherdowns Blvd., as part of the Broadway Series presented by the Theater League.
Performances are set for 8 p.m. Nov. 8-11, 2 p.m. and 8 p.m. Nov. 12, and 2 p.m. and 7:30 p.m. Nov. 13.
"It's been going great," Varela said of the tour, which started in Seattle in August. "We are the second-highest grossing show in the country right now, so that's pretty good. The audiences have been huge, the response has been huge and the tickets sales have been even huger."
Based on the classic novel by Victor Hugo, "Les Misérables" is set in 19th century France, a decade after the French Revolution, and focuses on the struggles of ex-convict Valjean and his experience of redemption.
Released from prison after serving 19 years for stealing a loaf of bread and subsequent escape attempts, Valjean can't find anyone willing to give him a place to live. Finally, a bishop takes him in but Valjean steals his silverware. He is caught and arrested, but released after the bishop tells police the silverware was a gift. Touched by the gesture, Valjean vows to turn his life around, changing his name and becoming successful. But when Inspector Javert later discovers Valjean's true identity, he makes it his life's work to bring him to justice.
J. Mark McVey will portray Valjean. McVey's 7-year-old daughter, Kylie McVey, is also a member of the cast, part of a new ensemble created for the anniversary production. She will also be part of the larger chorus numbers and portray Little Cosette and Young Eponine.
Varela said the 25th anniversary production maintains the elements that people loved in the original version while adding elements that allow the show to grow.
"This version is a wonderful update with new costumes and new orchestrations," Varela said. "It's really an amazing, amazing piece of theater."
The new production features a high-tech projection system that projects images on the back wall of the set.
"It makes the entire thing feel cinematic," Varela said. "For example, during the battle of the barricade, it rocks with each gunshot and each cannon blast. It makes the scenery a character."
Producer Cameron Mackintosh drew inspiration from the drawings and paintings of Hugo.
"I'm delighted that 25 years after 'Les Mis' originally opened in London the audience for this marvelous show is bigger and younger than ever before," Mackintosh said in a news release. "The new 'Les Mis' is a magnificent mix of dazzling images and epic staging, driving one of the greatest musical stories ever told."
"Les Misérables," which originally opened in London in 1985, has been seen by nearly 60 million people worldwide in 42 countries and in 21 languages, according to the release.
In 2006, it became the world's longest-running musical, surpassing the record previously held by "Cats." To date, "Les Misérables" remains the third-longest-running Broadway production of all time.
The score includes the classic songs "I Dreamed a Dream," "On My Own," "Stars," "Bring Him Home," "Do You Hear the People Sing?," "One Day More," "Empty Chairs at Empty Tables," "Master Of The House" and many more.
Varela said people will regret not taking the opportunity to see "Les Misérables" while it's in Toledo.
"It's just such a fulfilling theatrical experience. If you don't come see the show, you'll never forgive yourself. You'll have lived a life half-lived," Varela said. "If you can't watch 'Les Mis' and love it, then you have no heart, then you're probably not a human being because it's probably the most magnificent piece of theater that's ever been written."
Tickets are $23 to $80 not including fees and taxes and are available by calling the Stranahan Theater box office at (866) 381-7469, Ticketmaster at (800) 982-2787, or online at www.theaterleague.com.


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Fort Myers, FL (Sports Network) - Ryan Sweeney singled home Jonathan Diaz with the go-ahead run in the fifth inning, as the Boston Red Sox edged the Minnesota Twins, 2-1, in Grapefruit League action.
J.C. Linares led off the second with a home run for the Red Sox, while Minnesota's Justin Morneau tied things up by homering to lead off the fourth.
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Lots of rumors have been circulating about Eminem's highly anticipated eighth studio album and hopefully we can help clear things up. Some folks were talking about a July release date for the album but D12 rapper, Mr. Porter helped clear that rumor up by saying a July release is "highly doubtful". Eminem fans should not be expecting the new album until September post Memorial Day.
And…how about these songs that we're leaked from his new album?? One song named "Sick and Tired" was posted to YouTube back in February under the title "Denace – So Cold". We personally don't believe that is the Real Slim Shady but we will let you decide for yourselves. The song isn't bad, it's actually pretty good but it's not an Eminem track in our humble opinion. Also the fact that it's under someone else's name and the video disabled comments, let's us believe that something is fishy.
What do our loyal EminemLounge readers think?


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Resources for talking about school shooting available
Dec. 27, 2012 @ 08:29 PM
In the wake of the school shooting in Newtown, Conn., parents everywhere are concerned about addressing their children's concerns appropriately.
To assist with that effort, University of Minnesota Extension has made available an updated fact sheet, "A Survival Guide for Parents of Teenagers: What if the next shooting is at my school?" This guide in accessible in English or Spanish at: extension.umn.edu/family/families-with-teens/resources-parents/.
Other resources can be found at that site for addressing the needs of teens as well. Anyone needing assistance in accessing this resource should contact Joan Reid at (919) 603-1350 or email: email@example.com.


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Billy Roche
Actor | Writer | Soundtrack
Billy Roche was born on January 11, 1949 in Wexford, Ireland. He is an actor and writer, known for The Eclipse (2009), Trojan Eddie (1996) and Poor Beast in the Rain (1993). See full bio »
Born:in Wexford, Ireland
More at IMDbPro » Represent Billy Roche? Add or change photos


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Missouri Tea Party Suffers (Roy) Blunt Trauma in Primary
Categories: Politics
|Image via
|Let's be Blunt -- the Tea Party didn't stand a chance.
Before yesterday's primary, a coalition of more than two dozen Missouri Tea Party organizations called the longtime Republican congressman "a career politician and Washington insider who has sold out his constituents for special interest money" and "an abomination of everything we have been standing up for." They said that they "do not endorse or even want Roy Blunt for our next Senator."
So that means that the influential grassroots conservative movement rallied the troops, stormed the polls, tapped power of democracy and voted in their preferred candidate, Chuck Purgason, right?
Blunt annihilated Purgason, winning all but one county.
Check the map from the Missouri Secretary of State's snazzy website:
And, the more intriguing question, since they loathe Blunt so much, will they be supporting his opponent, Democrat Robin Carnahan, come November?
Daily RFT has an email out to the Franklin County Patriots -- the leaders of the anti-Blunt crusade -- asking those very questions. We'll let you know if the tea baggers are about to become turncoats.
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Room for Everyone
3,058pages on
this wiki
this wiki
|Barney & Friends Episode
|Room for Everyone
|Season 3, Episode 3
|Air date
|March 1, 1995
|Written by
|Mark Bernthal
|Directed by
|Bruce Deck
|Episode Guide
| previous
If the Shoe Fits...
| next
I Can Be a Firefighter!
Room for Everyone is the third episode from Season 3 of Barney & Friends.
By setting up make-believe rooms in the classroom, Tosha, Kathy, Carlos, and Shawn show Barney their favorite room in their house. When Carlos gets mad that he has to temporarily share a room with his brother Juan, Stella the Storyteller drops by to teach him that brothers and sisters have to stick together
Educational Theme: Rooms in a House
Stories: Paolo and Louis: The Two Brothers
|Song List
- This episode marks the first appearance of Stella the Storyteller.


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Video Game Canon Essay: Resident Evil
Elaine Dorr
When something makes a significant change in who we are as a culture it is our responsibility to save it so we know where our views came from and how certain pieces of information, literature, art, etc. have affected us. We do this in several ways, one of which is to add it to some sort of canon. This philosophy should be applied not only to written or painted works but also to electronic works as well. Video games, for example, can affect how we are culturally defined as much as books and art works and therefore should be able to be canonized. One game series in particular that has had an impact on our culture is Resident Evil. This series should be canonized because has shaped several gaming genres, brought these genres into the public's attention.
The Resident Evil series consists of shooter games, with the targets being zombies. The series includes first person shooters, third person shooters, and side scrolling games. The series is based off of a story about a pharmaceutical company, Umbrella, working in the biological warfare field. They created a virus that turns people into zombies but is capable of creating other B.O.W.'s ( bio-organic weapons). The plot line of the series started with dealing with the original outbreaks but has moved on to other bio-weapon threats involving previous main characters of the series.
The games used these characteristics in new ways to both immerse the player more fully in the game and to add a level of familiarity and with it fear. The conditions in the game were more life like in that they are plausible were the situation, in this case a zombie outbreak, to occur if the player were to stretch their mind and suspend their disbelief just a little. For instance, the player's character was relatively weak compared to other games. This point is brought up in an academic journal dealing with video games named Game Studies, "He notes the 'survival horror' genre. In games such as Resident Evil, Silent Hill or Fatal Frame, the player is not the near-invincible soldier that is so common in other games." ( Dean, Introduction), the author points out that in most other genres of games the player assumes the role of a character that could, especially in more "everyday" situations, be considered over powered. In fact the character in Resident Evil could be considered almost fragile in a sense. Another aspect of this type of game play is a limiting of resources, players are only able to collect a limited number of health and weapon related items over the course of the game. This is magnified by the fact that, especially in the earlier games, the character could hold a severely limited number of items and this had to include quest items and ink ribbons used for saving. This restriction of resources, especially the inventory system or how much the character can carry, can make the character more vulnerable and thus the game more frightening and potentially memorable as well as relatable.
Due to the Resident Evil's ( the first game in the series) popularity, success, and its "new" approach to the horror genre a new word was created to describe the specific "flavor" the game brought to horror. This meant that Resident Evil brought about the name of the genre that contained the characteristics it exemplified so well: Survival Horror. In fact, as written an article on the history of the series, the producers of the game even came up with the term, "One of the more subtle and important contributions Capcom made was the term "survival horror" itself." (Fahs,4). This series has not only helped to shape and popularize survival horror, but has even given it a name. This should, by itself, mean that the game should be remembered and kept on some sort of record so we do not lose the knowledge of the game that played a huge part in giving us the term survival horror.
The series later moved away from it's survival horror roots into other subgenres of horror. The more recent games moved towards simple shooters with zombies, with an emphasis on the cinematic more than the simple concept of "will you survive or not?". They no longer have the almost cripplingly small inventory system. The games also no longer require that quest items be held in the character's inventory as well as no longer requiring the, almost iconic, ink ribbon be carried around to save. The characters are also no longer as "fragile" as they were before, even if they are smaller they have some sort of, usually fairly intense, combat training. Finally, The game mechanics themselves tend more towards showy acrobatics and feats of strength that more than likely would be all but impossible to achieve especially with out injury. In reaction to this shift the creator of the original game, Shinji Mikami, has said during an interview with Computer and Video Games a little about what he thinks of the shift: "When I saw the trailer for 6, it looks as though it's more like a Hollywood action film than a zombie game." (Robson,1). Mr. Mikami's view point again reiterating Resident Evil's shift to a more cinematic centric and less realistic and relatable game play. This shift in game play in the series has caused Capcom to, once again, name a genre that they believed Resident Evil was entering and defining, "Capcom would agree, because according to executive producer Hiroyuki Kobayashi, RE6 is being called "dramatic horror."(Dutka, par. 3). In essence, Resident Evil has had a hand in both naming and defining two subgenres of horror.
Horror is not the only genre that has been affected by the series. While trying to make a game to follow Resident evil 3: Nemesis the team working on the project decided that the game had strayed to far from what Resident Evil should be "it proved to be a radical departure from the established Resident Evil formula and the survival horror genre in general. Rather than abandon the project entirely, the premise was changed and it eventually became the first Devil May Cry." (Devil May cry (series), series origin). The game was perceived as less based around limited resources and everyday "weak" characters, in essence survival horror, and more towards combat based on large combos and abnormal strength or acrobatics. This game, titled Devil May Cry, gave rise to the genre of " extreme combat". So, because this game and genre began as a part of Resident Evil, the genre of extreme combat, and our ideas of it, are indirectly influenced by Resident Evil.
Resident Evil has had a part in presenting to the greater public elements of game play that with out it might still be less common in the media. Not only this but it has influenced three game genres, one of which is not horror. It has also become a part of and changed the horror culture through it effects on the genres it encompasses. To reiterate, this series should be canonized because it has helped to name and define several parts of gaming and horror culture. It's contributions should be remembered and kept in some form if only so that we understand in the future where the influences came from that made our culture what it is.
Dean, Phillip D."Interactivity, Inhabitation and Pragmatist Aesthetics". Game Studies 11.2 (May 2011). Web. November 2, 2012.
"Devil May Cry (Series)". Wikia. N.d. Web. November 2, 2012.
Dutka, Ben. " Capcom labels Resident Evil 6 as 'Dramatic Horror'". PSX extreme. January 26, 2012. Web. November 2, 2012.
Fahs, Travis. "IGN Presents the History of Survival Horror". IGN. October 30, 2009. Web. November 2, 2012.
Robson, Daniel. "Shinji Mikami interview: 'To be told Japanese games suck is a bit harsh'" Computer and Video Games. July 17, 2012. Web. November 2, 2012.


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To the Editor:
I wish to express my love for our small town and its people. I want to thank the 250 patriots who attended our 9/11 Remembrance event this year and thank all those who made it possible.
Thanks to the CHS JROTC, VFW, Libby Brooks, Ali Graham, Brody Robinson, Larry Walker, Tomas and Teaque Malone, Tracey and Calab Weller, the janitorial staff at CHS, Charles Pearson, Rick Eddy, Pastor Mike Doak, Allan Furbee, Thorne's IGA, McDonald's, John and Belinda Mach, Al Kemerer for all their memorabilia, the gang at Gordon's Graphics, The Free Press Standard, Leigh Ann Rutledge, Rich Jones of JoMac, Todd and Lisa Miller of Columbus for providing a great mini concert featuring the National Anthem, American Soldier, Arlington and The Angry American Song complete with a confetti cannon that exploded over the crowd for the grand finale.
Next year I will be joining forces with Julia Strawder to help with the rebuilding of the Vets Pool and Community Center. Please support her efforts as you supported my cause in the past.
Lisa Walker
Kilgore, OH
The Free Press Standard invites you to post your thoughts on the story in the box below.
These posts do not reflect the views of the The Free Press Standard or its employees.
©2011 The Free Press Standard
Contact the webmaster at: firstname.lastname@example.com


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The panic from the administration and the foreign-policy establishment about the possibility that Congress will act to strengthen sanctions against Iran is hard to understand. Since even Secretary of Defense Chuck Hagel is running around the world saying that only sanctions and the threat of the use force on Israel's part are the only things that brought Iran back to the negotiating table, it's hard to fathom why making it even harder for Tehran to sell its oil and conduct business with those willing to brave the ire of the West will scare away them away. Yet, as we saw last week, the administration is so upset about the possibility that the Senate will follow up on House actions to tighten the sanctions that it not only sent in the heavy artillery to Capitol Hill to persuade them to back off but also tried to muscle Jewish groups into agreeing to a 60-day moratorium on advocacy for more pressure on Iran.
Those fears were echoed today in the New York Times. The paper doubled up on calls for engagement with Iran and a halt to pressure with an editorial and a curiously tone-deaf op-ed by diplomat Ryan Crocker that Michael Rubin already discussed. While it is worth taking apart the arguments against further sanctions, it is just as important, if not more so, to ponder why it is these voices are being raised now with such urgency. Though we are told that the goal is to further the cause of a diplomatic solution to the standoff over Iran's nuclear program, the urgency with which they are being put forward must raise suspicions that what is really being sought is a way to set the table for a deal that will resolve nothing but make action to halt the threat impossible.
The myth being put forward by the administration and its cheerleaders in the press is that more sanctions now would so offend the Iranians that they would halt the efforts toward diplomacy and weaken new President Hassan Rouhani in his efforts to convince the "hard-liners" in Tehran of the West's goodwill. They assume, in the Times's words, that Iran has now finally started to act in a "reasonable" manner and a continuation of the policies that brought them to the table would end all hope of diplomacy. But the absurdity of this position is so obvious that it is astonishing that anyone who has actually been paying attention to the last decade or more of diplomatic engagement with Iran could put it forward with a straight face.
First, the assumption that Rouhani's charm offensive is anything more than atmospherics is based on nothing more than the wishes of many in the West that the dispute would simply go away. The Iranian behavior in the latest round of the revived P5+1 talks that is touted by the Times as such a revolutionary change was actually no different than their posture in previous meetings. They have not weakened their resolve to go on enriching uranium nor have they stepped down from a "red line" position in which they absolutely refuse to surrender their existing stockpile of nuclear fuel. The only thing that has changed is that many in the West seem to have become so entranced with Rouhani and the possibility of renewed diplomacy that they are seeking to weaken the West's demands.
Even more to the point, if everyone takes it as a given that sanctions convinced the Iranians to give diplomacy another try—whether as part of a genuine desire for a negotiated settlement or because they want to use it, as they have in the past, to run out the clock further until they reach their nuclear goal—why would they turn and run if the West were to make it even more expensive for them to continue to defy the international community? If they are truly worried about the cost of sanctions—and the ayatollahs have been largely indifferent to the sufferings of the Iranian people up until this point—more of them can only give them a greater incentive to be forthcoming in the talks.
But the acclaim with which both the administration and outlets like the Times have greeted Iran's minimal gestures can only fuel suspicions that what is at play here is not a search for the proper strategy to make diplomacy work but a desire to avoid confrontation with Tehran at all costs.
The administration has promised time and again that it would not allow Iran to go nuclear and that "no deal is better than a bad deal." But it is impossible to avoid the conclusion that those pushing hard to weaken the West's hand in these talks by eschewing the one tactic that has the ability to make the Iranians worry are more afraid of coming to grips with the truth about this problem than they are about the Islamist regime attaining nuclear capability. The sooner the Iranians are truly put to the test and made to answer whether they are willing to give up their nuclear program the better, and only more sanctions that create a genuine embargo of their oil trade will do that.
Even more importantly, the Times argues that if appeasement disguised as engagement fails, as it as time and again, more sanctions can be imposed next year or the year after. But it should be remembered that it took this administration nearly four years to agree to the sort of tough sanctions that finally brought the Iranians back to the table–and then only at the insistence of Congress after arguments against the measures put forward by both President Obama's foreign-policy team and the Times. Now they are back at it again seeking to kick the can down the road another several months, or perhaps years.
But as we noted here last week, time is rapidly running out for the West or Israel to do something to avert the dire scenario by which Iran will attain the ability to threaten both Israel and Arab nations like Saudi Arabia and to back up their terrorist auxiliaries with a nuclear umbrella. After all these years of failed diplomacy, an argument for more delays is the moral equivalent of arguing for containment of a nuclear Iran rather than stopping it from happening.
The Senate must reject these voices of appeasement and act, as it did in 2011 and 2012, over the objections of the administration and pass more sanctions on Iran as soon as possible. A failure to do so will have incalculable consequences.


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WEBSTER COUNTY, Ky. - Nancy Kathryn Morgan, 84 of Clay, KY passed away Tuesday, July 16, 2013 at Deaconess Gateway Hospital in Newburgh, IN.
She was a lifetime member of Rock Springs Church in Wheatcroft, KY. She was preceded in death by her husband Jack Morgan in 2010
She was survived by 1 Daughter Beverly Goldman and her husband Larry of Boonville, IN, 1 Son Mark Morgan of Clay, KY 1 Granddaughter Terri Scales and her husband Scott of Newburgh, IN and 1 Great-grandson Marcus Scales.
Funeral Services will be conducted Friday, July 19, 2013 at 11:00 AM at Vanover Funeral Home in Clay, KY with Bro. Jeff McMain officiating. Burial will be in Rock Springs Cemetery in Wheatcroft, KY. Visitation will be Thursday, July 18, 2013 from 3:00 PM to 8:00 PM at Vanover Funeral Home in Clay, KY and Friday 8:00 AM til service time.
Memorial contributions may be made to Rock Springs Cemetery Mowing Fund C/O Calvin Martin P.O. Box 384, Clay, KY 42404
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Posted by Willy Franzen on February 5, 2012. Positions below updated every five minutes.
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Today's the big game! By the end of tonight there will probably be a new football hero for many fans. Unfortunately, even being the star of one of the world's biggest sporting events doesn't guarantee a carefree future. Football is a brutal sport that takes a terrible toll on the body. This is doubly bad for players. First, it causes all kinds of long-term health problems, and, second, it shortens careers significantly. This becomes a major problem for retired players who no longer have a source of income and are dealing with the physical aftermath of a career in football. Nobody wants to see their heroes down and out, which is why Gridiron Greats Assistance Fund was started. They're based in Northbrook, IL, and they "provide financial assistance and coordinate social services to dire need retired NFL players who are pioneers of the game and have greatly contributed to the NFL's status as the most popular sport in America."
I know that it's hard to empathize with someone who played a game for a living, but even today's players with their salaries that are often millions annually have a tough road ahead of them. Imagine if you made all the money that you'd make in your life in your first three years after college. It'd be pretty hard to be responsibly manage the money–especially knowing that there will likely be long-term medical problems. Fortunately, the NFL has realized the problems that life after football can present, and they've gotten much better about taking care of players after retirement; however, that still leaves many retired greats without help. Gridiron Greats Assistance Fund, which is chaired by Mike Ditka, is helping to take care of these players by "treating them with dignity, and addressing the post-football related issues in their lives." While Gridiron Greats Assistance Fund doesn't have a jobs page, you can contact them here. They've offered internships in the pat, so it many not be unreasonable to inquire about a job. It's at least worth trying if you're a big football fan. You may also want to check out our past posts on the National Football Foundation, the Pro Football Hall of Fame, USA Football, and, of course, the NFL and its teams.
Links to Help You Begin Your Research
Who do you think will win the Super Bowl?


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Despite being under the cosh for most of Saturday's League Two clash at Plymouth Argyle, Cook's decision to introduce Luis Boa Morte and Jack Lester proved decisive as both players played a part in Marc Richards' winner, his second goal in five days after scoring in Tuesday's 4-1 home win over Cheltenham.
After winning 1-0 at Home Park, Cook said: "As you go through games, levels of performance are important. We put in a level of performance that was more through commitment than anything. That was the pleasing thing because Plymouth were good value for a point.
"Make no bones about it, Plymouth were very hard done by. We accept that but that happens in football. Plymouth put us under immense pressure, that's why we went 4-4-2 when it was 0-0 to try and win the game.
"I am not a tactical genius but what we do is evaluate a game and make decisions that we think may alter the game. I was able to put Luis Boa Morte on at half time, how lucky am I as a manager?
"You would not expect any difference from Marc or Jack Lester, when they get in those positions we know they will score goals. If we put supply in the box we know they will score."


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Director's Column: Believing in Children By Jeanne W. Lepper, Director
One day this spring I had a wonderful surprise. During a visit to Bing School, Helen Bing presented us with a typed, one-page document that her mother-in-law, Anna Bing Arnold, used when she taught parent education classes in Los Angeles in the l950s. Suddenly, it all made sense. A genuine interest ... [ Read More ]


text: planning to implement openbsd 3.2 as an ethernet router in an ISP enviroment (dsl type connections) and was wondering if anyone could point me to any information or has first hand knowledge of the type of throughput one can get. here are hardware specs athlon 1 gigahertz proc 9 gig scsi drive adaptec scsi card 4 3com 3c905 nics 512 meg ram client connections would be 10 megabit each and would be coming into cisco catalyst 2900xl switches (1 switch per ethernet segement, 3 segments) with 1 segment on the openbsd box in our core network (100 megabit) wont be doing any packet filtering, just straight routing between the ethernet interfaces, but do plan on doing some qos with altqd later on. this is to be a entry level solution until we can cost justify getting a layer 3 switch (ie cisco catalyst, etc). can i expect to get throughput near 10mbit to the clients from our core network (i know i can from the switch to the client - tested with ftp, scp, http, etc) -- Chad Whitten Network/Systems Administrator Nexband Communications chadwick_(_at_)_nexband_(_dot_)_com