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A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.
1. A method of forming a dense electronic package comprising:
providing a wafer having multiple IC chips formed thereon, each chip having metallization forming I/O terminals;
adding a layer of passivation over the active surface of the wafer;
forming a plurality of second level electrical conductors on top of the passivation layer, such conductors (a) being formed of metallic material which is different from the chip metallization material, and (b) each extending between a first I/O terminal lead in contact with a chip I/O terminal and a second I/O lead terminal available for external electrical I/O connection;
cutting from the wafer a plurality of individual IC chips, each having a plurality of second level conductors and each having its second I/O terminal leads accessible for external connection;
integrating a plurality of such IC chips in a stack which has at least one access plane on which the second I/O terminal leads of the second level electrical connectors are exposed;
forming a plurality of terminal pads on the access plane, each pad (a) being in electrical contact with one of the access plane I/O terminal leads in the form of a T-shaped connection, and (b) being formed of the same metallic material as that of the electrical conductor which it contacts;
the metallic material which forms the second level electrical connectors and the terminal pads on the access plane being both (a) more chemically inert and (b) easier to process for maximum conductance at the T-shaped connections than the chip metallization material; and
then connecting the access plane terminal pads to exterior circuitry.
2. The method of claim 1 in which:
the metallic material which forms the second level conductors and their T-connection lead/pad terminals is gold.
3. The method of claim 1, which also comprises:
thickening the second level electrical conductors to substantially increase their conductance.
4. The method of claim 2, which also comprises:
forming a thin layer of an adhesive metal between each gold surface and non-gold surface, in order to provide adhesion of the non-oxidizing gold to the other surface.
5. The method of claim 4, in which:
the adhesive metal is titanium/tungsten alloy.
6. The method of claim 1, which also comprises:
removing, from the access plane of the stack, material of the IC chip edges, in such a way as to leave protruding from the access plane the metal I/O terminal leads formed by the second level electrical conductors;
selectively etching to remove any metal other than that of the second level electrical conductors; and
applying a layer of passivation to cover the access plane except where I/O terminal leads are exposed.
7. The method of claim 6, in which:
the protruding leads comprise aluminum in the original wafer and non-aluminum metal leads provided by the second level electrical conductors; and
the selective etching removes the aluminum, but not the other metal.
8. The method of claim 1 in which:
the layer of passivation added over the active surface of the wafer is silicon oxy-nitride.
9. The method of claim 8, in which:
the layer of silicon oxy-nitride is formed by plasma-enhanced chemical vapor deposition.
10. The method of claim 8 which also comprises:
adding a layer of silicon nitride passivation over the non-active surface of the wafer.
11. The method of claim 1 which also comprises:
subjecting the wafer passivation to photo-lithographic processes by which desired openings are formed through the passivation.
12. The method of claim 1 in which:
the terminal pads on the access plane which form T-shaped connections with the second level conductors are formed by means of a sputtering process.
13. The method of claim 1 in which:
the layer of passivation added over the active surface of the wafer is a polyimide material.
This application is a continuation-in-part of application Ser. No. 07/377,241, filed July 7, 1989, now abandoned.
This invention relates to the use of stacked structures (modules) comprising circuitry-carrying layers (IC chips); i.e., each layer has integrated circuitry thereon Such modules provide very densely packaged electronic circuitry. They may be used whenever space conservation in circuitry is desired, e.g., memory units, logic units.
The use of multiple layers in stacked units creates various processing problems, both during the pre stacking chip preparation, and during completion of the stacked unit, or module.
Because it is generally desirable to use IC wafers which are readily purchasable as standard (off-the-shelf) items, the existing on-chip leads require rerouting, in order to permit the eventual stacked unit to function as desired. In prior patents relating to the stacking of IC chips, it has been assumed that chip manufacturers will supply chips having leads suitable for use in stacked modules.
Among the prior relevant patents assigned to the assignee of this application are U.S. Pat. Nos. 4,525,921; 4,646,128; and 4,706,166. The first two listed patents deal with arrangements for avoiding short circuits in the stacked module, and for providing suitable electrical contact points on the access plane(s) of the stacked module, which contact points are available for connection to metallization on the access plane(s). The third listed patent deals with arrangements for bonding terminals on an access plane of a stacked module to terminals on a supporting, circuitry-providing substrate.
Rerouting the leads which are included in commercially available IC wafers has several advantages in the manufacture of stacked chip modules It also creates new problems. The present application deals with those problems, in order to make those advantages available. The assignee of this application has pioneered the use of stacked chips as focal plane modules having photodetectors on the focal plane. For example, see U.S. Pat. Nos. 4,551,629; 4,617,160; and 4,672,737. It also has pioneered the use of stacked chips as electronic modules for other fields, such as computer memory devices. There are significant differences between the two fields of use. The use as computer components may not require the extreme closeness of adjacent leads at the access plane; nor does it have the extremely restrictive power limits encountered in cryogenic photodetector enclosures.
However, a major challenge in providing stacked chips which serve as computer components is the zero tolerance of circuit failures. In a photodetector surveillance system, a certain percentage of outages (non-functioning circuits) is acceptable But in a computer component, every circuit must function properly. In the initial stack, extra chips are included to provide redundancy. This permits a limited number of imperfect chips in a completed stack to be disconnected. But the chips which remain in the operating component must have no circuit outages.
One of the electrical failure points in stacked chip modules has been the T-connections of the aluminum conductors on the chips with the metallization formed on the access plane That problem also provides motivation for the present invention.
The present invention includes both pre-stacking and post-stacking process steps which improve significantly the reliability of stacked chip electronic packages. Also, major commercial benefits are derived from the ability to utilize readily available IC wafers.
In the pre-stacking process, the chip leads are rerouted by providing a second layer of metallization formed on a passivation (insulation) layer covering the initial chip circuitry. The second layer of metallization has two purposes. The first purpose is to provide a different metal for the conductors which lead from the IC circuitry of the chip to the access plane of the chip and constitute the metal of the T-connections The T-conections on the access plane thus are formed of a much more reliable metal than aluminum The second purpose is to permit the second layer of metallization to change direction of the conductors, thereby permitting the use of readily available IC wafers.
Major benefits are obtained by using a relatively non-reactive (corrosion resistant) electrical conductor material, e.g., gold or copper, to form the lead re-routing metallization. Gold, which is usually the preferred metal, has numerous advantages over aluminum in the stacked structure, including major improvement in the quality (reliability and conductivity) of the T-connections The gold T-connections in the stacked structure constitute a marked advance over prior stacked structures.
The gold rerouting layer also permits a significant simplification of the pre-stacking process steps. In the stacked chip electronic packages, it is necessary to prevent potential short circuits by eliminating all undesired metallization, including portions of the original aluminum. The present invention avoids several steps at the wafer processing level by using a selective etching step to remove all remaining unwanted metal from the completed stack. Only the desired gold metallization remains in the final layer-containing module.
The use of a corrosion-resistant metallization material, i.e., gold, as the conducting material permits easy removal of the undesired material in the stack by a selective etching process performed on the stacked structure. A chemical is used which attacks and removes the undesired material, but does not damage the desired gold metallization.
In addition to the use of second layer metal which provides improved T-connections, the present invention deals with the problem of using the most appropriate insulation material as a film between the first and second layers of metal conductors. Significant considerations for the insulation film are reduction of its capacitive impedance, and avoidance of highly elevatged temperatures druing application of the insulation film.
FIG. 1 is based on a photograph of a vendor-supplied IC wafer having a large number of separate dice, or chips;
FIG. 2 is based on a photograph showing a close up of a six dice group, which has been modified to provide a single die suitable for use in a stacked layer package;
FIG. 3 is a diagram of a wafer, on which are identified the one out of every six dice which are modifiable in this particular wafer;
FIG. 4 shows the layout of an individual modified die after it has been cut out of the wafer;
FIGS. 5-9 are cross-sections (greatly enlarged) taken through a portion of a wafer, and showing the structural details during successive steps in the wafer modification process;
FIGS. 10A-10J are isometric views illustrating successive steps in the previously developed post-stacking steps;
FIGS. 11 and 12 are isometric views illustrating the stack before and after a new etching step which has been inserted into the post-stacking steps;
FIG. 13 shows a stack of chips mounted on a substrate;
FIG. 14 is a cross-section taken through a single (one of many) bump bonds between the stack and the substrate; and
FIG. 15 is a plan view of a T-connection, showing the relative sizes of a rerouted gold lead and a gold terminal formed on the lead.
An important aspect of the present invention is its success in providing a stacked layer electronic unit by improving both pre-stacking and post-stacking process steps. Where IC chips are intended for use in stacked layer units, there are numerous steps needed to prepare the chips for lamination. Also, integrated planning of the end-to-end process (from wafer modification to final electronic stacked unit) provides various functional and processing improvements. In other words, pre-stacking steps can favorably affect post-stacking steps, and vice versa.
FIG. 1 shows a plan view, taken from a photograph, of one manufacturer's original wafer 20, containing numerous IC chips, or dice, each of which is intended to become a separate chip, or die, 22 when the wafer has been cut along orthogonally-extending streets 24. The dice are tested at the wafer stage, and each failed die is marked with a black dot 26. The material in wafer 20 is silicon, although other IC chip materials may be used, e.g., gallium arsenide. The wafer in FIG. 1 has approximately a five inch diameter, and is approximately 0.024 inch thick. A major reason for preferring silicon ships in stacked modules is their relatively high heat dissipation efficiency. For example, silicon is 2 to 3 times more thermally conductive than gallium arsenide. A trade off for the advantages of silicon is the need for electrical insulation of the silicon because it is a semiconductor material having relatively high electrical conductivity. Gallium arsenide, also a semiconductor material, has electrical conductivity 3 or 4 orders of magnitude lower than that of silicon, and therefore is, in relative terms, an electrically insulating material.
Where the dice, or chips, are to be used as layers in a stacked structure, several steps should be performed in the wafer stage. Because the desired electronic density in the stack requires extremely thin chips, a thinning of the wafer is performed by removing material from its back surface. Performing the thinning process on individual chips would be extremely difficult, because of their minuteness. The thickness of the wafer 20 will be significantly reduced, e.g., from 24 mils to 4 mils (or less).
The wafer 20 is wax mounted face down on a rigid disc whose thickness has been measured to an accuracy of 0.001 mils and shown to be flat to within 0.05 mils. The thickness of the disc is fed into a computer and a calculation is made to give a final thickness of the wafer/disc sandwich which will keep the wafer thickness within a 0.1 mil range. The wafer is then ground to a calculated thickness. After grinding, the wafer is etched to its final thickness. The etching serves two purposes: fine-tuning of the final thickness, and removal of strain induced in the material by the grinding. After demounting and cleaning, the wafer thickness is measured to within 0.001 mil. The thickness data is then fed into a computer stacking program for later use.
Before describing the step-by-step wafer modification process, an explanation of the modification goal is in order. FIG. 2 is based on a close up photograph of a single die after modification. After forming a passivation (insulation) layer on the front (top) surface of the existing wafer, rerouting leads have been formed, preferably using gold as the material. A plurality of electrically parallel gold leads 30 are shown connecting gold terminals 32 to gold terminals 34. The terminals 32 extend through holes in the passivation layer to make electrical contact with the metal terminals, usually aluminum, formed on the original IC chip 36, which is having its leads rerouted for use in a stacked layer module.
At the other ends of the leads 30, new terminals 34 are provided, which will be in electrical (and mechanical) contact with metallization formed on the access surface of the stacked layer module. Thus far, it has been preferable to locate all of the terminals 34 along one edge of the modified chip. However, the rerouting process could be used to bring gold leads to more than one face of the stacked layer module. The rerouting is highly desirable because it permits (a) the use of standard wafers to provide chips for stacking, and (b) the use of gold leads and terminals, which have numerous advantages as electrical conductors over aluminum.
As seen in FIG. 2, and as diagrammed in FIGS. 3 and 4, the modified chip taken from the wafer of FIG. 1 uses six of the dice included in the wafer. This ratio is subject to improvement as different wafers are developed. In FIG. 3, the cross-hatched dice 36a are those which are modifiable, if each modified chip requires six original dice. In FIG. 2, the gold rerouting leads are shown crossing over two vertical streets 24a and 24b, and over one horizontal street 24c. Those original die which show black dots in FIG. 1 are not usable as IC chips chosen for lead rerouting.
FIG. 4 shows the shape of a chip 38 which has been cut from the wafer, in order to be used in a stacked chip module. The area of the stackable chip is the entire area of FIG. 4, whereas the area of the original chip, whose terminals have been connected to the gold rerouting leads, is that included in the dashed line rectangle 36a.
After thinning of the original wafer, and before the rerouting of leads, layers of passivation (insulation) are applied to both the front and back surfaces of the wafer. The front surface passivation is required because additional rerouted electrical conductors are to be formed above the existing IC circuitry. The back surface passivation is required because each layer (chip) will be next to the electrical conductors formed on the layer below.
Choosing the passivation material(s) presents certain problems. The insulating layers are chosen on the basis of: their electrical insulating properties; their mechanical properties--which include strength, porosity, etc.; their method of deposition; and their ease of delineation. There are a number of insulating thin film materials that are used in the semiconductor device industry. Primary materials are silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass, and various polyimides. Silicon nitride (SiN) and silicon oxynitride (SiON) have certain advantages, e.g., mechanical strength, humidity barrier, and etching qualities. Polyimides have certain advantages, e.g., ease of deposition, low dielectric constant, and ability to form layers of greater thickness.
A problem which polyimides tend to avoid is excessive capacitance. This is true because of (a) their relatively low dielectric constant, and (b) their greater thickness potential.
If SiN and SiON are used, a consideration in choosing between them is their respective etch rates. SiON etches eight times faster than SiN in buffered oxide etch (7:1). When buffered oxide etchant is used to remove unwanted passivation, the great difference in etch rates allows full etching of SiON on the top surface of the wafer, while SiN thickness on the bottom of the wafer is reduced only by about 12%. If the starting thickness of both insulation layers is approximately the same, removal of the SiON from selected locations on the top surface will leave the SiN on the bottom surface largely intact. If SiON is the insulation layer on the front surface (i.e., the device-carrying surface) of wafer 20, and SiN is the insulation layer on the back surface of wafer 20, synergistic benefits are obtained. The fracture safe SiON is used where that characteristic is of value; and the relatively etch-resistant SiN is used where that characteristic is of value (because adequate passivation remains on the entire back surface, while being fully removed in selected locations on the front surface).
FIGS. 5-9 show the changes in a small segment of the wafer cross-section as subsequent modification steps are taken. FIG. 5A provides a guide to the drawing symbols used to identify the different materials shown in FIGS. 5-9. FIG. 5 shows the wafer cross-section before any modification. The silicon body of the wafer is indicated by numeral 40. Streets 24e and 24f provide the cutting lines along which three dice--22a, 22b and 22c--would have been separated if the modification steps were not used. The arrows between the dashed lines show the width of the modifiable center die 22b. A device area on the upper surface of die 22b is indicated by a bracket having the numeral 42.
Aluminum (Al) metallization indicated by numeral 44 is used to provide conductors which connect the IC device area 42 to the terminals at which the chip will be connected electrically to exterior circuitry. A first layer 46 of silicon dioxide (SiO2) is shown below the aluminum metallization 44; and a second layer 48 of silicon dioxide is shown above the aluminum metallization 44. The SiO2 provides protection and insulation for the wafers supplied by the vendor. Openings 50 provided in upper layer 48 of SiO2 are available for connecting metallic conducting material which will contact the aluminum 44, and will thus provide terminal pads for connection to exterior circuitry.
As discussed above, and as shown in FIG. 6, a layer 52 of insulation (polyimide or SiON) is deposited over the entire upper (device) surface of the wafer; and a layer 54 of insulation (e.g., SiN) is deposited over the entire lower surface of the wafer. Deposition of the insulating films 52 and 54 may be performed by plasma-enhanced chemical vapor deposition (PECVD) at 380� C. in gas mixtures of silane, nitrous oxide, nitrogen, ammonia and argon. The exact mixture is dependent upon which of the films is being deposited The plasma-enhanced chemical vapor deposition (PECVD) is used instead of chemical vapor deposition (CVD) because PECVD is performed at 380� C., whereas CVD is performed above 700� C. Since the eutectic temperature of aluminum-silicon is 577� C., the CVD temperature would be destructive. Above 450� C., silicon is readily dissolved in aluminum, moving rapidly along aluminum grain boundaries, and precipitating out of solution some distance from the dissolution site.
The thickness of the insulation films 52 and 54 must be carefully chosen. The film 52 should be thick enough to avoid excessive capacitance and prevent cross-talk between the aluminum conductors below the film and the gold conductors above the film. However, excessive thickness of film 52 may cause stress on the metallic conductors.
FIG. 7 shows the wafer cross-section after performing selective etching to form certain openings in the layer 52. New streets 56 and 58 are formed in the adjacent dice 22a and 22c, respectively. And the film 52 is removed from the openings 50, into which metal will be deposited to provide conductor terminals. Prior to etching, a photolithographic process is used to permit etching only where desired. The entire surface of the passivation 52 is covered with a layer of photoresist. Then a mask is placed over the photoresist, and the uncovered portions of the photoresist are subjected to ultraviolet radiation. If the photoresist is positive, the areas in which the passivation 52 is to be removed will be those defined by the holes in the mask. Those areas are then left unprotected by removing (dissolving) the photoresist, i.e., at the new streets 56 and 58, and at the terminal openings 50.
Then the wafer is placed in a buffered oxide etch (BOE), in which the passivation 52 in the unprotected areas is removed. Silicon is not etched by the BOE. The etching time to remove passivation is carefully controlled to avoid undercutting. Witness or dummy wafers may be used for such control.
The undeveloped photoresist limits etching of the passivation to the desired locations. After the etching is completed, the photoresist is removed by a solvent. At this point, the cross-section of the wafer is as shown in FIG. 7. Except for the terminal openings 50 and the ne streets 56 and 58, the front wafer surface is covered by a layer 52 of passivation at least 1.0 micron thick. During the BOE etching, the thickness of layer 54 was reduced slightly. But its etching rate was much lower than the etching rate of the layer 52. So the passivation layer 54 remains sufficiently thick after the BOE etching.
FIG. 8 shows the wafer cross-section after deposition of a field metal layer, then plating-up of the gold leads, and finally removal of the undesired portions of the field metal layer. The initial field metal layer covers the entire surface of the wafer, and acts as an electrical conductor during the gold plating process. A very thin layer of field metal is first deposited over the entire front surface of the wafer. This field metal layer consists of a coating of titanium-tungsten (Ti-W) alloy, followed immediately by a coating of gold (Au). The Ti-W and Au materials are deposited by a sputtering process, which is continuous, i.e., deposition of the Ti-W and of the Au is accomplished during the same sputtering run. The Ti-W alloy has excellent adhesion to both the oxide and metal surfaces that it covers, and it also makes good electrical contact. Because any exposed aluminum tends to form an oxide, just prior to sputtering on the field metal, a light sputtering etch is carried out, in order to remove aluminum oxide, which would have an insulating effect.
Gold, which does not oxidize, does not adhere well to an oxide. Its inclusion in the sputtering run prevents formation of an oxide on the surface of the Ti-W alloy. Subsequently, the gold leads will be built up (thickened) by electro-plating additional gold on the initial gold coating until the gold reaches a thickness of approximately 2.5 microns. This is done after photoresist is applied to cover the field metal, except where gold leads are desired.
The dimensions and routing of the metallization which provides the gold rerouting leads have been chosen to minimize both resistance and capacitance. Gold may be preferred for it low electrical resistance, electroplating ease, and chemical inertness, especially because it does not form an oxide. This latter property means that it is expected to have low electrical contact resistance, but poor adherence to oxide-like surfaces. That shortcoming is overcome by the use of an adhesion metal beneath the gold, such as titanium, aluminum or, better, the titanium-tungsten alloy.
Metals other than gold may be used instead of gold, if the trade-off is considered desirable in a given situation. In other words, it may be preferable to use, as material for the rerouting or extending leads, a material having certain characteristics which are better than aluminum, but inferior to gold, if other characteristics of such material provide an attractive trade-off relative to gold. The primary disadvantages of gold are (a) its high cost; (b) the special efforts needed to cause it to adhere to certain materials; and (c) its undesirable property as a recombination center in silicon. The latter characteristic is due to the position of gold in the band gap in silicon, which makes gold a potential destroyer of carriers, under the influence of high processing temperatures, such as those used in diffusion and in thermal oxidation.
As stated in this application, the favorable characteristics of gold include (a) its excellent electrical conduction both in the rerouted or extended leads and at the T-connections, (b) the ease of thickening it by plating, and (c) its resistance to etching when aluminum is removed after stacking. The non-oxidizing nature of gold, and its relative chemical inertness, contribute to its favorable characteristics. Other metals, such as copper, silver, nickel, and/or their various alloys, may in some cases provide desirable trade-offs relative to gold, because they will provide, to a significant extent, its favorable qualities, while they will avoid, to some extent, one or more of its disadvantages. The resistivity figures for the metals referred to are, in the order of highest conductivity: silver 1.59, copper 1.67, gold 2.35, aluminum 2.65, and nickel 6.48.
Photolithography is used to delineate the paths of the plated gold leads. The entire field metal coating is covered with photoresist. A mask is then used having openings which define the terminals and the desired paths of the rerouted gold leads. After removing the photoresist from those lead-defining paths, an electroplating process is used to build up the gold thickness of the rerouted leads. The entire wafer is put into a gold plating bath, in which the electrical current is provided via the field metal coating.
Next, the field metal layer is removed (except for the rerouted leads) by first dissolving the remaining photoresist, and then briefly placing the wafer in successive etching materials which remove the thin field metal coating. A first etchant is used for the thin gold layer and a second etchant for the thin Ti-W layer. Each etchant is used for a very short period. The gold etchant also removes some of the plated gold of the rerouted leads, but not enough to affect the conducting efficiency of the leads. Gold is one of the most corrosion (etching) resistant metals, but it can be removed by suitable etchants. For example, the gold etch which has been successfully used in the present process contains potassium (K), iodine (I) and water, in the proportions of 113 grams of K, 65 grams of I, and 100 cc. of water. A satisfactory etch for the Ti-W layer is hydrogen peroxide (H2 O2) at 45� C. The etchants used to remove the field metal do not remove either the passivation material or the aluminum.
At this point the cross-section corresponds to FIG. 8. The thick gold leads 30 (see also FIGS. 2 and 4) have gold terminals 32 which are in electrical contact with the aluminum metallization 44. The rerouting gold leads 30 extend from the terminals 32 to the new terminals (34 in FIGS. 2 and 4) which will be in electrical contact (by means of T-connections) with metallization (gold) applied to the access surface of the stacked module into which the modified chips have been incorporated. Note that the new gold leads pass through the streets 24e and 24f in the original wafer.
FIG. 9 shows the wafer cross-section of the modified die, which is ready to be cut out of the wafer and then placed in a stacked module. The only change from FIG. 8 to FIG. 9 is the removal of the aluminum 44 from the new streets 56 and 58. This removal may be accomplished by exposing the wafer to an aluminum-only etching material containing phosphoric acid and nitric acid. This etching material attacks the aluminum, but does not attack the gold leads, the passivation layers, or the silicon.
Subsequently, after wafer testing, the modified dice (chips) are cut out of the wafer, cutting along the lines provided by the new streets (56, 58, and the orthogonal streets). A modified chip, ready for stacking, is shown in FIG. 4. In addition to the gold rerouting leads, the modified chip has four spacer pads 59 which engage the next layer after stacking. Two of the pads, located at the chip edge having lead terminals 34, are triangular. This shape later permits depth of lapping of the edge to be determined by measuring the width of the triangular pads.
The stack building steps are then performed, using the chips provided by the modified dice. The particular laminating process is not part of the present invention. One such process is described and claimed in common assignee U.S. Pat. No. 4,617,160. Generally, the chips of a stack are (a) selected in accordance with precise thickness measurement; (b) stacked in a fixture which holds them in alignment; (c) provided with a measured amount of adhesive (epoxy) between each pair of adjacent chips; and (d) heated to cure the epoxy and create a solid stack. One advantage of the present invention, which improves the stacking process, is the ability of the relatively thick plated gold terminals on each chip to act as supplemental spacers between adjacent chips, thus helping to insure glue (epoxy) lines in the stack which have consistent (and very slight) thickness. Controlling the thickness of the glue lines, in order to maintain accurate lead spacing in one of the two access plane dimensions, has been a problem in stacked chip modules.
After forming a laminated stack of chips, several process steps are required to prepare the terminals on the access plane of the stack. FIGS. 10A-10J are isometric views illustrating successive steps, which lead to the completion of the stacked chip module ready for attachment to a carrier substrate. Those post-stacking process steps are disclosed and claimed in common assignee U.S. Pat. No. 4,525,921.
FIGS. 11 and 12 illustrate a new step, inserted into the process, which is a significant part of the present invention. Referring first to the previously patented process, FIG. 10A symbolizes the multiple steps leading to the laminated stack 60 of FIG. 10B, which consists of a plurality of glued together chips 62. Each chip 62 is a complete IC chip, having a multiplicity of parallel integrated circuits, each circuit having its own lead which terminates (see FIG. 10C) at the access plane 64 of the stack (shown as the top plane). FIG. 10C represents the lapping and polishing step, which removes silicon to expose the multiplicity of leads 66 seen in FIG. 10D. Note that the leads 66 form a two-dimensional pattern. The spaced leads on the edge of a single chip are considered to extend along the X-axis. The Y-axis dimension includes the aligned leads on separate chips, whose spacing is determined by the thickness of the chips.
FIG. 10E shows a chamber 68, used in a plasma etching step, which removes silicon, epoxy, and insulation materials from the access plane of the stack, leaving the metal leads 66 protruding from the access plane 64 of the stack, as seen in FIG. 10F. The plasma etching is performed only on the access plane surface (or surfaces) of the module. A flash etch step may be needed to remove any remaining silicon oxide (SiO2) from the access plane. This is accomplished by very briefly exposing the module to hydrofluoric acid.
FIGS. 11 and 12, as stated above, disclose a significant aspect of the overall process which is part of the present invention. They represent a step performed between FIGS. 10F and 10G. A single step performed on the stacked module accomplishes what either (a) would not be feasible, or (b) would require multiple steps and much more complexity if performed prior to formation of the stack.
As a consequence of the requirement to extend the rerouted gold signal leads (30 in FIG. 2) outside the area of the active (original) die, a selective metallization removal is necessary before placing the T-connection metallization on the access plane of the module. The aluminum metal 67 removed at this stage is in the dice adjacent to the modifiable die. It lies beneath the extended gold leads (or in a plane below the gold lead plane) and it has been exposed (along with the gold leads) by the plasma etching of the silicon. Initially, it was planned to remove this aluminum at the wafer level but such removal would have required many more processing steps, and would have degraded performance. By performing the removal after all the chips have been stacked in the module (module level), the metal removal is accomplished for all the chips at one time. If this spurious, unwanted original metal is not removed, there is a possibility of shorting between the various signals of the active chips in the module.
The process that was developed is removal of the spurious aluminum metal using a selective chemical etch solution (H3 PO4 :HNO3 :H2 O). This process is performed after the silicon etch procedure (FIG. 10F) has been performed on the stacked module. The special chemical solution removes only the unwanted aluminum metal, while not affecting the gold leads of the module. In FIG. 11, there is a mixture of unwanted aluminum metal 67 with the gold signal leads 66. FIG. 12 shows the gold signal leads 66 still protruding, while the unwanted aluminum metal has been removed.
Next, in accordance with the prior process, the access plane is covered with a passivation layer 70, as shown in FIG. 10G. The preferred passivation material is polyimide. Passivation is required to insulate the metallic conductors from the silicon body of the stack. After the polyimide is applied, the metal leads need to be re-exposed. FIG. 10H shows another lapping and polishing step which uncovers the gold leads without removing the surrounding polyimide insulation.
FIG. 10J shows the re-exposed leads 66. And FIG. 10K shows metallization deposited on top of, and in electrical contact with, the leads 66. In the process of applying this metallization, metallic busline strips 72 are laid down, and also metallic chip select pads 74. Beneath the strips 72 and pads 74 are terminal pads which contact the exposed leads 66, and which have larger areas than the leads 66. These junctions are referred to as "T-connections", because the leads and pads meet at right angles, and because each pad extends across and beyond the ends of its lead 66. The metallization seen in FIG. 10K preferably is applied in a plurality of layers, as detailed below. Both Ti-W and Au are used in order to obtain maximum electrical conduction and effective adhesion at the contact areas.
In the presently preferred version of the invention, the completed stack, as shown in FIG. 10K, has its conductors (metallization) all on access plane 64. Some of the conductors are shown as bus lines, and some as rectangular terminal pads. The access plane then has its conductors connected to external circuitry in any preferred manner. For example, as disclosed in common assignee U.S. Pat. No. 4,706,166, the access plane may be placed face down on a substrate face having electrical conductors which provide routing of signals between the stack circuitry and external circuitry. Suitable insulation is formed between the substrate and the access plane of the stack; and bonding bumps serve as connections between terminals on the substrate and terminals on the access plane. Other external circuitry connecting schemes are available.
FIG. 13, which is similar to FIG. 5 of U.S. Pat. No. 4,706,166, shows a substrate 80 having mounted thereon a stack 82 containing numerous chips 84, each of which extends in a plane perpendicular to substrate 80. Both electrical conductivity and thermal conductivity are provided by soldered bumps between terminals on the stack and aligned terminals on the substrate. If necessary, extra heat conducting (but not current conducting) bumps can be used to enhance heat dissipation. In circuitry packed as densely as that in the stacked IC chips, heat transfer is a major consideration. Heat dissipation in the range of 40-100 watts can be accomplished with silicon chips which have effective heat transfer to and through the substrate 80.
A stacked chip module can have more than one access plane, if the chips extend in planes parallel to the substrate. In such an arrangement the chip conductors could lead to more than one edge of each chip; and electrical conductors could be brought down the sides of the module to contact conductors on the substrate. The present invention is applicable to such an arrangement. One problem with that concept, if semiconductor chips are used, is that more extensive electrical insulation between the stack and the substrate would also tend to create thermal insulation. Another potential problem is providing adequate electrical contact at the substrate/stack interface. In other words, the T-connection arrangement would not be readily available.
FIG. 14 is a greatly enlarged close up showing successive layers of material which provide one bump bond between the stack and the substrate. The dimensions are not intended to be proportionally accurate. The metallic layers applied to the access plane of the stack are all applied by a sputtering process. One of the gold rerouting electrical leads 66a is shown terminating at 66b, where it extends to the lower surface of an insulation layer 86 of polyimide material. The polyimide layer 86 may be approximately 3.0 microns thick. The gold conductor 66a has a thickness of about 2.5 microns. Power conductor gold leads may be 10 mils wide. Other gold leads may be 5 mils wide at their terminals, and 2 mils wide between terminals. (1 mil equals 25.4 microns). The conductor 66a is one of numerous such parallel conductors located between two silicon chips 88a and 88b.
Building up the bumps on the stack for bonding to a silicon substrate 102 involves numerous steps. Building up matching bumps on the substrate 102 also involves numerous steps. Eventually the matched, aligned bumps will be soldered together under heat and pressure.
Primary emphasis is given in this description to the metallization on the access plane of the stacked chips. There are, in effect, three metallization patterns formed on the access plane. The first is pad metallization, which provides pads used for testing purposes. The second is busline and chip-select metallization, which is formed on top of the first metallization. If testing the first pad metallization indicates any defective chip(s), a layer isolation process is performed. Using photoresist and a mask, the metal pads protruding from the failed chip(s) are etched back, and then covered with polyimide.
The first metallization applied is one consisting of 0.005 by 0.010 inch pads and 0.010 by 0.010 inch pads. The larger pads are placed on Vcc and Ground lead ends. The pads have a thin initial layer 90 of sputtered titanium-tungsten alloy to provide good adhesion and low electrical resistance to the gold lead ends 66b, and also to provide good adhesion to the surrounding polyimide. The Ti-W thickness is about 0.2 micron. A much thicker (about 1.0 micron) gold layer 92 is deposited upon the Ti-W. This pad metallization allows electrical inspection of individual chips after the stacking process.
The T-connect structure(intersection of two perpendicular planes of metal) is further illustrated in FIG. 15. Two pads 92 are shown. Each pad contacts a lead 66, which is the end of a conductor extending from the interior of the stack of chips. The lead 66 is perpendicular to its pad 92. A line 120 represents the planar engaging surfaces of two adjacent chips. The area of each pad 92 is substantially larger than the lead 66 which is joined to it; and the full conductive cross-section of each lead 66 is in electrical conducting contact with its pad 92. Their perpendicular engagement, and the sputtering of the gold pad material into contact with the gold lead material insures an effective conductive bond.
The gold T-connections replace aluminum T-connections used in prior developments. The advantages of gold T-connects are extensive. Aluminum T-connects have problems of brittleness, uneven edges due to corrosion, poor conductivity due to oxide formation, and lack of cross-sectional thickness. Gold T-connects solve all of these problems, and result in major performance improvements. In fact, gold T-connects appear to have conductivity which is 2 to 3 orders of magnitude better than aluminum T-connects.
The second metallization consists of pads and buslines. Except for the chip select pads 74 (FIG. 10K), the pads 92/94 are connected from one chip to the next by the buslines 72 (FIG. 10K). For those pads not connected by buslines, a second pad layer is applied, in order to maintain equal height throughout the stack. Since buslines must also cross stack regions of nonmetallized polyimide, a thin (0.2 micron) adhesion metal layer 94 of Ti-W alloy must precede the thicker (1.0 micron) gold layer 96.
The third, and final, metallization is the solder pad metallization. The relatively thick gold layer 96 s followed by a thin (e.g., 0.2 micron) layer 98 of a barrier metal (e.g., nickel), followed by a thicker (e.g., 2 micron) layer 100 of tin/silver (Sn:Ag, 96.5:3.5) solder. A dashed line 101 represents the engaging surfaces of solder bumps on the access plane of the stack with solder bumps on the substrate 102.
As already indicated, the preferred process in applying metallization to the access plane (or planes) of the stack is sputtering, which is particularly successful in forming highly conductive T-connects. A less attractive alternative is use of deposition by evaporation.
In controlling the metallization pattern to provide fine delineation, two possibilities are: (a) etch delineation and (b) lift-off. Etch delineation requires the use of chemical etchants; and where a plurality of metals are to be etched, a plurality of etchants must be used. This has major inherent difficulties. So the lift-off method is preferred.
The lift-off method applies photoresist prior to metal delineation. Broadly the lift-off process includes: (a) covering the surface with photoresist, (b) masking the photoresist to provide the metallization pattern, (c) developing the exposed photoresist, (d) dissolving the exposed photoresist to uncover those portions of the access plane which provide the desired metallization pattern, (e) applying metal to the entire surface, and (f) dissolving the remaining photoresist, which carries along with it the metal not included in the metallization pattern.
In order to minimize bridging between the retained and removed metal, a two-stage lift-off process is used. A first layer of photoresist is applied to the entire access plane. This entire layer is only briefly exposed to ultraviolet light. Then a second layer of somewhat different photoresist is applied the access plane. A mask is used to delineate the exposed (and developed) portions of the second layer of photoresist. After the second exposure, the photoresist is removed. By using two layers of photoresist and two exposures to develop the photoresist, a slight photoresist overhang is produced in the areas where metal is to be deposited. This creates discontinuity of the sputtered metal.
The sputtering process is first used to apply the thin layer 90 of titanium-tungsten (Ti-W) to the access plane; and it is then used to apply the much thicker layer 92 of gold (Au) on top of layer 90. Layer 92 is a gold terminal pad in the first metallization stage. The Ti-W is necessary to provide adhesion of the gold layer to the polyimide, while at the same time providing electrical conductivity which maintains the full electrical contact efficiency of the gold-to-gold T-connection (i.e., 66b to 92). Suggested thicknesses of layers 90 and 92 are 0.2 micron and 1.0 micron, respectively.
After testing the terminal pads 92, and isolating any defective chips, the second stage of metallization is applied. Like the first stage, it comprises the thin (0.2 micron) layer 94 of Ti-W, and the thicker (1.0 micron) layer 96 of Au. These layers are also applied by sputtering. Because the first stage has rectangular pads, and the second stage primarily has elongated buslines, the first and second stages require separate photoresist lift off patterns. Also the busline gold deposited will be thicker in the spaces between the first stage terminal pads.
The third stage of metallization also requires a photoresist lift off pattern; and also comprises two layers. The mask used in the first pad deposition may be used. A thin (0.2 micron) layer 98 of nickel (Ni) is sputtered on. And then the thicker (1.5 micron) layer 100 of solder (tin/silver) is sputtered on. The layer of Ni is required to prevent leaching of the gold into the solder when heat is applied to bump bond the solder bumps on the stack to the solder bumps on the substrate. As previously stated, suitable tin/silver composition of solder bumps 100 is 96.5 Sn/3.5 Ag.
The lower portion of FIG. 14 shows the material layers on the substrate. The silicon substrate 102 carries a top surface passivation layer 104 (about 1.0 micron thick), and a bottom surface passivation layer (about 1.0 micron thick). A gold conductor 108 leads into a much thicker gold terminal pad 112. Above pad 112 is a thin (about 0.2 micron thick) Ni layer 114. And above layer 114 is a tin/lead solder bump 116. A suitable composition of the tin/lead solder bumps 116 is 63 Sn/37 Pb. When the aligned solder bumps 100 and 116 are engaged with one another (see line 101) under suitable heat and pressure, the stack of chips is effectively secured to the substrate mechanically, and each pair of engaging solder bumps provides an electrical and/or thermal path. The resulting electronic module has extremely dense circuitry (e.g., a terabit of memory in a volume less than one cubic foot), combined with very effective heat dissipation. Because of the effective heat conduction of silicon, and the high bump density at the access plane/substrate interface, this module can dissipate 100 watts of heat or more, depending upon the heat sink which is used.
The solder bump bonding, therefore, is not only vital as an electrical interface, but as a heat dissipation path. In fact, in some instances, extra bump bonds may be added solely as heat conductors (without electrical conduction).
From the foregoing description, it will be apparent that the apparatus and method disclosed in this application will provide the significant functional benefits summarized in the introductory portion of the specification.
The following claims are intended not only to cover the specific embodiments and methods disclosed, but also to cover the inventive concepts explained herein with the maximum breadth and comprehensiveness permitted by the prior art.
Patent Citations
Referenced by
Legal Events
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I predominately use 3 grits of sandpaper with my orbital sander. 80, something else, and something else. I was tired of them sitting on a table only to fall off, or trying to use the packaging as some kind of clever tray when it wasn't.
I decided to make a caddy, which I could hang on my storage wall with a French cleat.
Step 1: Plywood and Then Some Holes
Draw a center line lengthwise. Use that to line up your discs and trace three holes each. You could go more, but I see no reason. Three looks like a face and who doesn't like that?
3/8" dowel rod fits the holes prefectly, therefore I drilled my holes with a 3/8" forstner bit. I went 1/2" deep, but you can do whatever you want.
Step 2: I Painted the Board
My pegs are 2 1/2" long so I can get a full pack of each grit on here. Also, I hand chamfered the edge of the dowel (with sandpaper ironically) so the paper would slide on easier.
Step 3: Glue in the Pegs
I gave it a few coats of spray lacquer for protection.
A fancy version of this photo with sandpaper storage. It's not an original idea but maybe I'll make an instructable. it's pretty far down my project list so it won't be for a while. :)
With all that dust make sure your wearing a dust mask. Not those crappy ones with the rubber bands, a good one and eye protection.
I've had plans for a while to build a sander holder to put the sander on while it's still spinning. This will be a great & simple addition to that project.
Also, I love that diablo sandpaper. It's the best there is.

subset: commoncrawl


text:
Article ID: 925419 - View products that this article applies to.
Bug #: 50000269 (SQL Hotfix)
Bug #: 469810 (SQL Server 8.0)
Bug #: 475051 (SQL Server 8.0)
Microsoft distributes Microsoft SQL Server 2000 fixes as one downloadable file. Because the fixes are cumulative, each new release contains all the hotfixes and all the security fixes that were included with the previous SQL Server 2000 fix release.
On This Page
This article describes the following about this hotfix release:
In Microsoft SQL Server 2000, you perform one of the following operations:
Error: 17883, Severity: 1, State: 0
Process 51:0 (dbc) UMS Context 0x018DA930 appears to be non-yielding on Scheduler 0.
This problem occurs because SQL Server takes a long time to free a large procedure cache. The operations that are mentioned in the "Symptoms" section trigger a process to free the procedure cache. If the procedure cache is large, this problem occurs.
Hotfix informationA supported hotfix is available from Microsoft. However, this hotfix is intended to correct only the problem that is described in this article. Apply this hotfix only to systems that are experiencing this specific problem.
If the hotfix is available for download, there is a "Hotfix download available" section at the top of this Knowledge Base article. If this section does not appear, submit a request to Microsoft Customer Service and Support to obtain the hotfix.
Note If additional issues occur or if any troubleshooting is required, you might have to create a separate service request. The usual support costs will apply to additional support questions and issues that do not qualify for this specific hotfix. For a complete list of Microsoft Customer Service and Support telephone numbers or to create a separate service request, visit the following Microsoft Web site:
http://support.microsoft.com/contactus/?ws=supportNote The "Hotfix download available" form displays the languages for which the hotfix is available. If you do not see your language, it is because a hotfix is not available for that language.
Registry informationYou do not have to change the registry.
Hotfix file informationThis hotfix contains only those files that are required to correct the issues that this article lists. This hotfix may not contain all the files that you must have to fully update a product to the latest build.
The English version of this hotfix has the file attributes (or later file attributes) that are listed in the following table. The dates and times for these files are listed in Coordinated Universal Time (UTC). When you view the file information, it is converted to local time. To find the difference between UTC and local time, use the Time Zone tab in the Date and Time item in Control Panel.
SQL Server 2000, 32-bit version
Collapse this tableExpand this table
SQL Server 2000, Itanium architecture version
Collapse this tableExpand this table
Microsoft has confirmed that this is a problem in the Microsoft products that are listed in the "Applies to" section.
This hotfix fixes only one cause of error 17883. In some cases, you may still receive error 17883 after you apply this hotfix.
For more information, click the following article number to view the article in the Microsoft Knowledge Base:
319892For more information about the naming schema for SQL Server updates, click the following article number to view the article in the Microsoft Knowledge Base:
(https://support.microsoft.com/kb/319892/ )New concurrency and scheduling diagnostics have been added to SQL Server
822499For more information about software update terminology, click the following article number to view the article in the Microsoft Knowledge Base:
(https://support.microsoft.com/kb/822499/ )New naming schema for Microsoft SQL Server software update packages
(https://support.microsoft.com/kb/824684/LN/ )Description of the standard terminology that is used to describe Microsoft software updates
Article ID: 925419 - Last Review: October 8, 2011 - Revision: 2.0
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text:
Unfortunately, The Principal Big Ten Men's Basketball Tournament Trip contest has ended.
To help you get in the game, The Principal has created The Principal Financial Playbook. It offers ten easy plays to help you create your game plan so that you can work toward achieving your financial goals.
Check out our free Principal Financial Playbook now.


text:
Honey Variety Descriptions
Trying to decide what honey to buy? Below are honey descriptions and helpful information on what these honeys taste like. Each year honey variety tastes can vary due to rain amount, nectar sources, sunlight, etc. which all affect what flowers, plants, trees, are in bloom for the bees to collect nectar and pollen from - each year we look forward to trying the various honey ourselves to see what the bees have collected for us! Honey varieties we carry include: Bamboo Honey, Buckwheat Honey, Clover Honey, Goldenrod Honey, Locust Honey, Orange Blossom Honey, Tupelo Honey, and Wildflower Honey.
Let's first discuss the difference between "regular" honey and raw honey that we sell and honey that is found in supermarkets across the U.S. Most folks are familiar with store bought honey. This honey is typically filtered at high temperatures around 160 degrees for some time and then filtered through fine filters which removes the best qualities of honey which includes the pollen, beeswax, etc. The high temps also cook the beneficial enzymes so in our view you'd be better off drinking straight sugar water. Also some large packers will add corn syrup to honey to extend the shelf life so the honey looks nice and clear for consumers to buy.
Now our "regular" honey is taken off the hives and slightly filtered and bottled. As time progresses, we then have to heat the honey to 120 degrees to reliquify it as some folks simply do not like crystallized honey. This does not pasteurize the honey as honey needs to be cooked at higher temperatures around 160 degrees for quite some time. We simply heat it just enough to make it a liquid again. This honey will also crystallize as well, but at a much slower rate since it has been slightly heated.
All of the honey we sell is 100% pure honey, nothing adding and no adulteration is done to the honey. We enjoy selling varieties of honey to folks and hope you enjoy honey as much as we do!
Honey Varieties that we Sell:
Japanese knotweed flowers are valued by some beekeepers as an important source of nectar for honeybees, at a time of year when little else is flowering. Japanese knotweed yields a monofloral honey, usually called bamboo honey by northeastern U.S. beekeepers, like a mild-flavored version of buckwheat honey. This honey is a very dark honey and also has a pleasant sweet taste to it.
Food Items are Not Returnable


text:
Cases, Armbands & Films
Incase Sports Armband Deluxe for iPod (5th Gen.)Incase's Sports Armband Deluxe is the functional and secure way to carry your 5th-generation iPod touch during a run or workout. A detachable protective case and a highly adjustable armband make working out with your iPod easy and comfortable.$44.95
- Free Shipping
- In Stock
Incase Sports Armband Pro for iPod nano (7th Gen.)The Incase Sports Armband Pro is your ideal training partner. Its touch-sensitive screen cover delivers sweatproof protection, while letting you access the iPod nano (7th Gen.) screen.$29.95
- Free Shipping
- In Stock


text:
Occidental College
Language & Culture Studio
Placement Test Information
Learn about Language Requirements & Placement Exams
Fulfillment of the Core Language Requirement
Core Language Requirements are outlined in the college catalog. Some majors or minors, such as languages, Diplomacy and World Affairs, as well as some programs to study abroad, may have additional requirements.
Exemption exams for French and Spanish: If your online placement score places you in 201 or 202 you are eligible to take the exemption exam. If you are planning on continuing this language at Oxy, you do not need to take the exemption exam now (if you cannot complete the 201 or 202 class you can take the exemption test at the Keck Language and Culture Studio at a later date).
German: Exemption Interview: If your online placement score places you in German 201 or 202 you are eligible to take the exemption interview during the first week of classes. If you are planning on continuing German at Oxy, you do not need to take the exemption interview. You must contact email@example.com to sign up for the interview.
Online Language Placement for Spanish, French, or German
Online Placement Exams for Spanish, French, and German: If you are planning on taking any of these three languages in the Fall 2014, you must take the online placement exam before you can register into the appropriate class. After completing the placement exam online you can log in to my.oxy.edu and view your result and placement under the Acadmics tab.
Instructions (For Spanish, French, or German only):
- Make sure you have a username to login onto campus email and computer systems (consult your frosh orientation packet or contact Information and Technology Services)
- Go to Moodle and select the Language Placement Test or click here: Language Placement Tests
- Read the instructions carefully, and make sure you have a full hour ahead of you. The test must be taken in one seating.
Language Placement for Chinese, Japanese, Russian, Latin and Arabic
Contact Michelle Baca (email@example.com)
Results and Registration Information
• For All test results and registration into language classes please contact the Registrar's Office: http://www.oxy.edu/Registrar.xml
(Please allow 1 business day to process your placement/exemption score and it to show up on your my.oxy.edu account )
Sunday, August 24
Language Placement Exams Fall 2014
date: Sunday, August 24
time: 1-2:30pm
location: Fowler Hall
Japanese (Fowler 201): Professor Motoko Ezaki
Chinese (Fowler 207): Professor Sarah Chen
Latin/Arabic (Fowler 202): Michelle Baca
Russian (Fowler 209): Professor Walter Richmond
Spanish Exemption (Fowler 301): Professor Robert Ellis
French Exemption (Fowler 309): Professor Arthur Saint-Aubin
- Phone: (323) 259-2843
- Location: Booth Hall 103


text:
You know what this blog needs? More miscellaneous pictures that I find on the internet:
Oh, and profanity.
This entry was posted
on Sunday, May 18th, 2008 at 10:57 am and is filed under pictures.
You can follow any responses to this entry through the RSS 2.0 feed.
You can leave a response, or trackback from your own site.
And that's why I love your blog. For the profanity.
Mail (will not be published)
maebmij's blog is proudly powered by
Entries (RSS)
and Comments (RSS).


text:
Google's Matt Cutts explains how to get your site better visibility on Google, in an interview with USA TODAY's Jefferson Graham on the Talking Tech web video show.
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Uut and Uup Add Their Atomic Mass To Periodic Table
By JAMES GLANZ
Published: February 1, 2004
A team of Russian and American scientists are reporting today that they have created two new chemical elements, called superheavies because of their enormous atomic mass. The discoveries fill a gap at the furthest edge of the periodic table and hint strongly at a weird landscape of undiscovered elements beyond.
The team, made up of scientists from Lawrence Livermore National Laboratory in California and the Joint Institute for Nuclear Research in Dubna, Russia, is disclosing its findings in a paper being published today in Physical Review C, a leading chemistry journal. The paper was reviewed by scientific peers outside the research group before publication.
''Two new elements have been produced,'' said Dr. Walt Loveland, a nuclear chemist at Oregon State University who is familiar with the research. ''It's just incredibly exciting. It seems to open up the possibility of synthesizing more elements beyond this.''
The periodic table is the oddly shaped checkerboard -- with an H for hydrogen, the lightest element, in the upper-left-hand corner -- that hangs in chemistry classrooms the world over. Each element has a different number of protons, particles with a positive electrical charge, in the dense central kernel called the nucleus.
The number of protons, beginning with one for hydrogen, fixes an element's place in the periodic table and does much to determine an element's chemical properties: ductile and metallic at room temperature for gold (No. 79), gaseous and largely inert for neon (10), liquid and toxic for mercury (80).
Elements as heavy as uranium, No. 92 on the list, are found in nature, and others have been created artificially. But much heavier elements have been difficult to make, partly because they became increasingly unstable and short-lived.
Still, for roughly half a century, nuclear scientists have been searching for an elusive ''island of stability,'' somewhere among the superheavies, in which long-lived elements with new chemical properties might exist. Dr. Loveland said that the new results indicated that scientists might be closing in on that island.
''We're sort of in the shoals of the island of stability,'' said Dr. Kenton J. Moody, a Livermore nuclear physicist who was one of the experimenters in the work.
''It's an amazing effect,'' he added. ''We're really just chipping away at the edges of it.''
The experiments took place at a cyclotron, a circular particle accelerator, in Dubna, where the scientists fired a rare isotope of calcium at americium, an element used in applications as varied as nuclear weapons research and household smoke detectors. Four times during a month of 24-hour-a-day bombardment in July and August, scientists on the experiment said, a calcium nucleus fused with an americium nucleus and created a new element.
Each calcium nucleus contains 20 protons and americium 95. Since the number of protons determines where an element goes in the periodic table, simple addition shows the new element to bear the atomic number 115, which had never been seen before. Within a fraction of a second, the four atoms of Element 115 decayed radioactively to an element with 113 protons. That element had never been seen, either. The atoms of 113 lasted for as long as 1.2 seconds before decaying radioactively to known elements.
Scientists generally do not give permanent names to elements and write them into textbooks until the discoveries have been confirmed by another laboratory. By an international convention based on the numbers, element 113 will be given the temporary name Ununtrium (abbreviated Uut for the periodic table) and element 115 will be designated Ununpentium (Uup).
Dr. Loveland said he agreed that the new elements would require independent confirmation before they could receive final acceptance. And he conceded that the Dubna find was likely to receive more than the usual amount of scrutiny: two years ago, the reported discovery of Element 118 was retracted after a scientist at Lawrence Berkeley National Laboratory was found to have fabricated evidence.
The only other truly simultaneous discovery of two elements in recent times came in 1952, when einsteinium (99) and fermium (100) were discovered in the fallout from the hydrogen bomb explosion at Eniwetok Atoll in the Pacific Ocean. The most recent successful discovery of an element -- one that has received a name -- came in 1994. That element, No. 110, is called Darmstadtium for the city in Germany where it was discovered.
But as scientists wait for confirmation on elements 115 and 113, the data presented by the Dubna and Livermore groups appear solid, said Dr. Sigurd Hofmann, a nuclear physicist at the Institute for Heavy Ion Research in Darmstadt, the laboratory where Darmstadtium was found.
''These Dubna data look quite convincing,'' Dr. Hofmann said. ''And I'm sure with some more experiments, it will finally be accepted.''
Dr. Joshua B. Patin, a 28-year-old nuclear chemist who is the lead American author on the paper, said he had found it deeply moving to add two more entries to a scientific icon that dates to the 1860's. That was when the Russian chemist Dmitri Ivanovich Mendeleyev noted clear patterns in the chemical properties of the known elements and arranged them into the periodic table, leaving gaps for other elements that he correctly predicted would someday turn up.


text:
If the game freezes, just click inside it (games can get unresponsive if you click elsewhere on the page).
We all know Draculaura is such an expert in fashion. Now we have the chance to visit her very own dressing room and you are even been invited to be her stylist. Look at all these cosmetics and beautiful clothes! Let's start the makeup and dressup for Monster High Ghoul Draculaura! Have fun!
This game is played with the mouse only.


text:
University of Wisconsin Stout | Wisconsin's Polytechnic University
Get Your Hands on Your Future
UW-Stout offers innovative, career-focused degrees based on active learning, applied theory and research.
Barb joins the Take2 action news team and Isaac reports from a ball pit in this episode. Take 2 minutes to find out what's going on at UW-Stout.


text:
School Overview
|School Membership(s)School Assoc.
|Association of Christian Schools International (ACSI)
National Christian School Association (NCSA)
|Religious Affiliation
|Grades Offered
|Grades 6 - 12
|Year Founded
Student Body
|Total Students
|400 students
|Student Body Type
|% Students of Color
State avg.: 22%
|Students by Grade
Academics and Faculty
|Total Classroom Teachers
|20 teachers
|Student : Teacher Ratio
National avg.: 13:1
|% Faculty w/Advanced Degree
|Number of AP Courses
|2 courses
|List of Courses Offered
|Link to List of Courses
|Advanced Courses
|A.P. English, Advanced Chemistry, Calculus, Literature, Physics, A.P. Government, European History, Experimental Chemistry, Functional Anatomy and Advanced Biology, Mechanical Physics,
|Classroom Dress Code
Finances and Admission
|Admission Deadline
|None / Rolling
|% on Financial Aid
|Total Sports Offered
|11 sports
|Baseball, Basketball, Cheering, Cross Country, Equestrian, Football, Golf, Softball, Swimming, Track and Field, VolleyballBaseball, Basketball,
Cheering, Cross Country,
Equestrian, Football,
Golf, Softball,
Swimming, Track and Field,
School Notes:
Salem Academy Christian Schools exists to provide an excellent education from a Christ-centered, Biblical perspective, so that our students may know and serve God. At Salem Academy we strive to achieve an excellent education on the basis of what we are told in Colossians 3:23, which says, "Whatever you do, work at it with all your heart as working for the Lord, not for men." We provide a Christ-centered, Biblical perspective in the context that all truth is God's Truth, and the foundation of that Truth is found in the person of Jesus Christ and in the Holy Scriptures (John 1:1). Growing in wisdom demonstrates intellectual, emotional and spiritual development, growing in stature represents physical growth and the development of one's reputation, and growing in favor with God and man represents spiritual and relational development. All of these areas are critical to the overall growth and development of students. It is a great privilege for the faculty and staff of Salem Academy to be able to serve students and families from the Willamette Valley. If you are not already part of the Salem Academy family, I urge you to consider how we might partner with you in providing an excellent educational experience for your student in a Preschool through High School setting, under the umbrella of a Christ-centered distinctive.
Profile last updated: 01/29/2014
Nearby Schools:
- School Location Miles Grades Students
Salem4373 Market St Ne
Salem, OR 97301
(503)391-2639(Roman Catholic)0.6 mi | Gr. 6-12 | 357 students
Salem1550 Market St Ne
Salem, OR 97301
(503)375-2620Daycare / Preschool (Church of the Nazarene)1.7 mi | Gr. PK-K | 54 students
Salem5771 Fruitland Road NE
Salem, OR 97317
(503)363-9408(Seventh-Day Adventist)2 mi | Gr. K-12 | 175 students
Salem1350 Court Street Ne
Salem, OR 97301
(503)588-0171Daycare / Preschool (Lutheran Church -- Missouri Synod)2.1 mi | Gr. PK-K | 42 students
Salem1015 Columbia St Ne
Salem, OR 97301
(503)363-8457(Roman Catholic)2.2 mi | Gr. PK-6 | 78 students


text:
- Posted August 19, 2013 by
- rolangarcia Follow
davao city, Philippines
This iReport is part of an assignment:
Travel photo of the day
Kadayawan Festival 2013
- sarahbrowngb, CNN iReport producer
Kadayawan Festival is an annual festival in the city of Davao in the Philippines. Its name derives from the friendly greeting "Madayaw", from the Dabawenyo word "dayaw", meaning good, valuable, superior or beautiful. The festival is a celebration of life, a thanksgiving for the gifts of nature, the wealth of culture, the bounties of harvest and serenity of living.
Highlights of the festival are "Hiyas sa Kadayawan," "Indak-indak sa kadalanan," and "Pamulak sa Davao."
The "Hiyas sa Kadayawan" is not your usual beauty pageant because it focuses heavily on the cultural uniqueness of the tribe and their knowledge about their tribe's cultural identity.
The "Indak-indak sa Kadalanan" is a streetdance and showdown competition of choreographed dance and narratives inspired by Mindanao's tradition, legends, myths, and other important cultural events.
While the "Pamulak sa Davao" showcases different colorful floats made of flowers, vegetables and fruits to give tribute to the abundance of harvest.
- kadayawan,
- travel,
- culture,
- itsmorefuninthephilippines,
- festival,
- philippines,
- davao,
- traditions,
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Obituaries, January 10, 2013
Jan. 10, 2013 @ 12:22 AM
Dennis Lee Hardin
WEDDINGTON, NC — Dennis Lee Hardin, age 65, died on Friday January 4, 2013. Funeral Services will be held at Spencer Baptist Church, Friday at 11 a.m. Crowe's Mortuary is in charge of the arrangements.
Mary Ellen Van Atta
Mary Ellen Van Atta, age 89, of Lake Lure, died Monday, January 7, 2013, at Willow Ridge Nursing Center.
A native of Seneca, Ohio, she was the daughter of the late John W. and Gladys Huber Koons. She was a home maker.
She is survived by her three sons, John Robert Van Atta of Grenwich, CT, R. Lewis Van Atta of Livermore, CA and Matthew E. Van Atta of Decatur, GA; and four grandchildren, Lucy Rose Van Atta, Fernanda Van Atta, Noah Van Atta and Robert Van Atta. In addition to her parents, she was preceded in death by her husband, Robert Ernest Van Atta.
Funeral services will be held at a later date.
In lieu of flowers, memorials may be made to the National Arthritis Foundation.
Crowe's Mortuary is in charge of the arrangements.
Online condolences at www.crowemortuary.com
Johnnie Mae McCorkle
Mrs. Johnnie Mae McCorkle, 108, of Asheville, NC, died Monday, January 7, 2013, at her home.
Mae was born in Rutherford County to the late John and Dovie Flack.
Mae was a retired licensed beautician and a member of Mt. Zion Baptist Church of Asheville.
She was preceeded in death by her husband, Oliver McCorkle.
Left to cherish her memories are her supportive nieces, Wilma Allen and Janice Bryant of Washington, DC; her nephew, John-John of Asheville; her devoted care takers and friends.
Funeral services will be Friday, January 11, at 12 p.m. at Mt. Zion Baptist Church in Asheville. Visitation will be one hour prior to the service.


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NARS debuts Brow Perfector—a velvety eyebrow pencil for seamless definition of the eyebrows with precision and ease. This highly-anticipated addition to the brand's brow category offering helps beauty lovers achieve even, elegant brows and every desired angle of arch.
A propel/repel pencil allows you to reshape, fill, and design brows for a full and flawless, natural matte finish, while an innovative oval shape gives complete control over brow shape, angle, and size. Natural ingredients ensure brows are nourished, soft, and smooth.
NARS Brow Perfector ($22.00 for 0.007 oz.) will be available in four shades that range from blonde to black (but no redhead). The formula is described as "velvety" with a "natural matte finish" and "natural ingredients [that] ensure brows are nourished, soft, and smooth." That last bit, I couldn't attest to and don't actually know what they're referring to as far as particulars. There's a lot of focus on the precision tip of the pencil that is oval-shaped.


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What You Should Know
|Star Rating
|2 or More Patented Ingredients
|Less Than $5 Shipping
|Trial Offer
|Rejuval Skin (2014 Editors Choice)
|Facial Toner
|IQ Derma
|Aveda Brightening Correcting Serum
|Meaningful Beauty
Aveda is a skin care and beauty line that emphasizes natural ingredients, plant extracts and floral aromas. These products are made in America, and they are commonly sold through Aveda salons and authorized dealers. As you may know, this brand offers anything from hair care, to styling products, to skin care, to makeup products, to body treatments, to grooming aids for men. Aveda even creates their own fragrances, which consumers can have designed in the store to suit their own preferences. Amongst the various skin care treatments in this line, there is Aveda Brightening Correcting Serum, which is what we will focus on in this review.
Product Details
Aveda Embrightenment Brightening Correcting Serum is claimed to be "plant-powered" in order to help fade out dark spots and skin discolorations. The user is supposed to benefit from a brighter and clearer complexion. More specifically, this Aveda treatment endeavors to exfoliate dead skin cells, diminish age spots and freckles, calm the skin, and improve overall clarity by up to 52 percent. It is directed to be smoothed onto clean skin, morning and night. The user may feel the facial skin tighten immediately after using Aveda Brightening Correcting Serum.
The primary active ingredients used in this topical formula are Ascorbyl Glucoside (this is a derivative of Vitamin C that brightens the skin), Glucosamine (sloughs away dead skin cells), Grape Extract (reduces skin discoloration), Mulberry Root (helps minimize dark spots by up to 34 percent), and Salicylic Acid (encourages skin cell turnover). Aveda Brightening Correcting Serum also contains ingredients like Sandalwood, Organic Rosemary, and Organic Rose Geranium, which all assist with calming the skin and soothing irritations. The cost of this anti-aging treatment is $50 (one fluid ounce).
The Good
- This skin care treatment contains natural plant extracts.
- Aveda Brightening Correcting Serum uses Salicylic Acid as an exfoliant.
- There are numerous reviews and testimonials posted on the main website.
The Bad
- There may not be any Aveda salons or authorized dealers near you.
- Some women may have allergies to the plant extracts used in this product.
- A full list of ingredients for Aveda Brightening Correcting Serum is not found.
- Clinical research for this face treatment is not elaborated on.
The Bottom Line
Regardless of whether you are a woman or a man, finding and choosing the best anti-aging treatment can be a hassle. This is why we create these skin care reviews on various topical formulas. Although many products aim to diminish fine lines and wrinkles, reduce age spots, improve skin firmness, and brighten the complexion, some yield better results that others. As for Aveda Brightening Correcting Serum, this product has a few good ratings from users, which is always nice to see. Naturally it would also be nice to know all of the ingredients used in this anti-aging product, as well as how long it takes to actually produce real results.


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Welcome to The Wild Hunt's semi-regular round-up of news and opinion, unleash the hounds. As you read this I'll be on my way to San Francisco, California to attend the American Academy of Religion's Annual Meeting. The AAR is the world's largest association of academics who research or teach topics related to religion, and their annual meeting has become a vital place to hear about the latest scholarship in the field of Pagan Studies (and just about every other religious and philosophical tradit … [Read more...]
Unleash the Hounds! (Off to the AAR Annual Meeting Edition)
November 18, 2011 by


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Feb. 8, 2009
DERWOOD, Md. - The University of New Mexico was well represented yesterday at the USA Cross Country Championships. Former Lobo All-American Jeremy Johnson finished 12th in the men's open race, while New Mexico freshmen Lacey Oeding and Allen Pittman were 10th and 16th, respectively, in the men's and women's junior races.
Johnson (Albuquerque, N.M.) covered the 12,000-meter Agricultural Heritage Farm Park course in 37:08 - 44 seconds shy of sixth place and a spot on the USA National Team. 2004 Olympic marathon silver medalist Meb Keflezighi won the individual title with a time of 36:06. The men's open field featured 159 runners.
Earlier in the day, Oeding proved herself to be one of the top young distance runners in the country with a top-10 finish in the field of 62. The Jasper, Ind. product covered the 6K course in 21:50 - just 13 seconds shy of a national team berth. Shippensburg State freshman Neely Spence, the 2008 NCAA Division II cross country runner-up, was the women's Junior winner with a time of 20:42.
Pittman (Los Alamos, N.M.) crossed the line of the 8K course in 25:28 - less than a minute out of the top-six. Oklahoma State standout German Fernandez won his second straight Junior title with a time of 23:20.


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It looks as if my (I mean, the media's) hype about the youngsters on tour is right on target.
I feel like the tour has taken a breath of fresh air this year: The rookies and veterans are definitely pushing each other to progress their surfing. Day two brought heats to remember, with the heat of the day going to Silvana Lima and Coco Ho—the queen of aerials and proud owner of this week's only perfect 10, versus the on-fire Hawaiian rookie. And, drum roll please, after a six-minute judge's delay, Coco Ho took the win to prove she's a force to be reckoned with. After defeating Rebecca Woods in the following round, Ho made it through to the semis where she'll face fellow islander Melanie Bartels. It looks as if Coco is mastering this whole competition thing… (more…)Thank you for visiting the Swell blog. Visit us on www.facebook.com/swell for more exclusive fan offers, giveaways and more.


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Special Operations Division Commander - Jarret Young
In 1990, Jarret Young began his law enforcement career at the Anaheim Police Department as a Police Cadet. He was hired as a Police Officer in 1993. As a Police Officer he has been assigned to Patrol, the Bike Team, the Field Training Officer Program, Community Policing Team, Gang Enforcement Unit and was a Drug Recognition Expert Instructor.
In 2005, Jarret was promoted to Sergeant. He was assigned to the Patrol Division, the Personnel Detail and was a supervisor on the Primary Response Team (PRO)Team.
In 2010, Jarret promoted to Lieutenant. He served as a Patrol Watch Commander, Internal Affairs Bureau Commander, Patrol District Commander and as a Special Tactics Detail Commander.
In 2012, Jarret promoted to Captain. He served as the Operations Division Commander and is currently the Special Operations Division Commander.
Captain Young has a Master of Arts Degree in Criminal Justice from Chapman University, a Bachelor of Science Degree in Public Administration from The University of La Verne. He is a graduate of the Supervisory Leadership Institute and the Leadership in Police Organizations Course.
Captain Jarret Young can be reached at email@example.com


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Last week, we talked a little bit about picking a raiding spec for entry-level raiding as a restoration shaman. There was some great comments and some great emails, which I am still going through and replying to. As always, if you haven't gotten a reply quite yet, don't worry -- it's on its way.
We have already covered some pre-raid gear choices, as well as gems and enchants with a little discussion on stats and stat pirority. This week, I figured we would round out or pre-raid preparations with a quick list of raiding glyphs as well as taking the opportunity to talk about some upcoming changes in the forthcoming patch 4.1 that will have a potential impact on our raid healing.
More than just pictures on the wall
The last piece of your pre-raid setup is your glyph choices. Some of our glyphs are pretty awesome; others are situational. We'll just talk about glyphs for when you're starting out raiding, as well as my personal thoughts on the choices. Here is the list of what we really have to work with.
- Glyph of Chain Heal
- Glyph of Ghost Wolf
- Glyph of Healing Stream
- Glyph of Healing Wave
- Glyph of Stoneclaw Totem
Minor Earth Shield, Glyph of Earthliving Weapon, and the last slot for Glyph of Riptide. Glyphing Earth Shield is about to become a little more important, especially after patch 4.1, but we'll get into that in a little bit here.
For Glyph of Earthliving Weapon, it should be known that this only applies to the HoT effect. It does not increase the spellpower gained from Earthliving Weapon or have any effect on Unleash Elements. That said, the glyph really pays for itself, especially when you consider that it can trigger off of Healing Rain as well as your other heals, so you can have the HoT up on large numbers of raiders in the group.
Glyph of Riptide gives Riptide an additional 6 seconds to tick, bringing its total duration up to 21 seconds. Since the spell has a cooldown of 6 seconds, you can in theory keep it up on three targets at a time once you get rolling. Now, if you find yourself having mana issues, you can swap one of them out for Glyph of Water shield, but it ultimately only results in a gain of about 170 MP5.
For major glyphs, there's a lot of choice here, but I highly recommend Glyph of Healing Stream, Glyph of Chain Heal and Glyph of Healing Wave for starting out. Chain Heal is a great spell when you can use it and get it to hit at least three people. The only problem is that if the spell hits fewer than three, this glyph can result in reduced overall healing. It is really good for 25-man raiding, but it is on the fence for 10-man raiding. If you're in situations in 10-man raiding in which you can make sure it hits at least three people, it can be a great pickup. I suggest Healing Wave because when you're first starting out raiding, chances are good that you'll have times where you are low on mana and may need to heal yourself and someone else. This makes sure you get some health back every time you cast that Healing Wave, and that can be pretty handy.
Glyphing Healing Stream Totem is almost a necessity at this point. While it won't stack with Kings or Mark of the Wild, it still raises resistance to fire, nature and frost by 195. While other classes may be able to do that as well, you can't always count on them being there or being alive. Besides, you're likely to be keeping a HST down anyways -- why not make it that much better? Keep the others in mind; we'll be coming back to them at a different time.
As far as minor glyphs go, the only one I really recommend is Renewed Life. There's nothing worse than needing to use Reincarnation only to realize you forgot to stock some Ankhs. Now some fights may do better with other glyph combinations, but as we discuss the bosses themselves, we will point those out as we come across them.
Patch-type goodness
Patch 4.1 is on the horizon, and when it does go live, there are a number of changes in store, even for restoration shaman. In the last few weeks, there have been a couple of changes announced, and I figured now would be a good time to address them while we all eagerly await Spirit Link Totem's arrival.
- Cleansing Waters now has a 6-second internal cooldown.
- Earth Shield healing done by Restoration shaman has been reduced by 20%.
- Nature's Blessing has been improved to 6/12/18% bonus direct healing on Earth Shielded targets, up from 5/10/15%.
Right now, I really like Cleansing Waters, if you hadn't already gathered that last week. The reason I like it right now is because on trash and some bosses it can be very handy for the reduced cost to Cleanse Spirit and a free heal. When you find yourself in 10-mans, without a plethora of cleansing options, it can be useful; even in 25-man raiding, you may find yourself having to cleanse something. Any reduction in mana expendeture is good, as it leaves you with more mana to cast a heal with later, and I'm never one to pass up a "free" heal.
After the patch, though, the heal will only be able to be used every 6 seconds. While Cleanse Spirit remains spammable, the heal won't be. This means that it moves a little lower on my priority list after the patch.
Earth Shield's healing being reduced was something I was surprised to see. In our heroic Maloriak kill this week, ES was less than 10% of my overall healing. In every other fight, it clocks in somewhere around 3% to 4%. This is with me keeping my ES on the add tank. While I don't think the reduction will hurt too terribly much, I do like the change to Nature's Blessing. It gives your heals a little extra kick when healing anyone that has your ES on them. This is particularly handy if you pull tank healing duty. It's an extra 3% healing at rank 3, but sometimes that extra 3% is all you need. I can tell you that when I pull tank healing on boss fights, anytime I have to use a big heal, every percent matters.
Overall, patch 4.1 is shaping up to be something I'm excited about as a restoration shaman. The further tweaking we're getting, as well as our brand new raid-wall, are really working to help us out in the long run as far as raid healing goes. What do you think of the upcoming changes? Next week, we'll begin diving into actually healing through the entry-level raid encounters in Cataclysm.
Totem Talk: Restoration will show you the basics of endgame resto shaman play as well as how to find the expansion's best reputation gear for resto shaman and tips for easier leveling. Happy healing, and may your mana be plentiful!


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The 2009 NASCAR season is officially underway and it's off to the West Coast for a few weeks...first stop, sunny California! Check out Jamie's statistics and thoughts on racing at Auto Club Speedway!
Auto Club 500
Sunday, February 22, 2009
Auto Club Speedway
5:00 pm ET on FOX
Driver: Jamie McMurray
Team: No. 26 Crown Royal Ford Fusion
Crew Chief: Donnie Wingo
Chassis: RK-626 (brand new chassis)
Click here to download the Full Preview (pdf)


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U.S. Sen. Lindsey Graham has picked up two more official primary opponents as Orangeburg lawyer Bill Connor and Columbia pastor and retired lawyer Det Bowers have both filed as Republicans.
Easley businessman Richard Cash also has filed for the seat, and there could be as many as three other GOP challengers before filing ends Sunday. State Sen. Lee Bright of Spartanburg, Charleston public relations executive Nancy Mace, Orangeburg lawyer Bill Connor, and ex-police office Dave Feliciano of Spartanburg also have said they're running.
Meanwhile, Ginny Deerin of Charleston filed as a Democrat for the S.C. Secretary of State, where Republican Mark Hammond is seeking re-election. And Karen Smith of Dorchester also filed as a Democrat for the 6th Congressional District seat held by Democratic Rep. Jim Clyburn, who is seeking re-election.
Filing closes at noon Sunday.
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Improve Your Public Speaking Skills
- Overview
- Deaden Your Nerves
- Nail the Opening
- Suck 'Em In
- Obstruct Abstractions
- Set It, Then Forget It
- Jack Up Your Act
- Screw Up on Purpose
- Beware Momentary Lapses
- Go Short
- Serve Well-Done Toasts and Roasts
- Let Them Figure It Out
- Watch the Masters
- Remember: It Ain't Brain Surgery
More Guy Wisdom Lists
Nail the Opening
When facing a roomful of businesspeople, remember the Wisk commercial, says Walker. The company's got ring around the collar. Show them how you're going to remove it.
For less formal occasions, go with Jon Miller's approach. The play-by-play man for ESPN's Sunday Night Baseball is also a veteran of the banquet circuit. "I start out real loud and try to get an immediate laugh," usually at his own expense, he says. But his best attention-grabbing trick? He opens with, "I'm going to tell you a story that's never been told before."
Sign up for our FREE Daily Dose newsletter for the best fitness, health, sex, and nutrition tips delivered to your inbox daily.


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So my Scoundrel hit level 44 and I swung by my Sage once again and popped a couple of Flashpoints, since I haven't done a lot of videos lately due to learning classes well enough to be able to make proper guides I thought I should put out some content for you guys, hopefully you'll enjoy it.
Website ? http://rurikhan.com
Facebook ? http://facebook.rurikhan.com
Twitter ? http://twitter.rurikhan.com
Google+ ? http://gplus.rurikhan.com
Digg ? http://digg.com/rurikhan
Gaming, Technology and Entertainment


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You said it Terry...Who cares about that. If I wanted to hear about sibling rivalry I'll turn on Jerry Springer.
Best Open-Mic Night St. Louis 2006 - Chippewa Chapel Traveling Guitar Circle and Medicine Show
Let's get back to the article please Robert. I don't think people really care about that.
Your monkey's fucked and he's going down!
"they've turned homelessness to their advantage"!?What?, How? By Freddy "Fraction" Boettcher,Jr. , with no regard to his/our own family, caused his own brother; Robert, who was there to help him all those years, and who subsidized his business, ...Freddy,Jr. left his own brother homeless.
Freddy Elmer Boettcher, Jr. is a criminal.He made countless false police reports, and perjured himself in legal proceedings, as well as legal documents so as raid my fathers home, steal over $30,000.00 at the selling of our property before splitting the rest with the other 5 owners, as well as my personal possessions on top of ruining my life, and destroy my reputation.


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GAO, Mali, Feb 8 (Reuters) - A suicide bomber on a motorbike blew himself up at a Malian government military checkpoint 100 km (60 miles) north of the northern city of Gao on Friday, injuring one soldier, a Mali military officer said.
It would be the first reported suicide bombing since a French-led intervention swept Islamist rebels from their desert strongholds of Gao, Timbuktu and Kidal.
"A kamikaze on a motorbike just blew himself up at the Bourem checkpoint at 6:30 am (0630 GMT). One lightly wounded soldier from Gao," the officer told Reuters by text message. (Reporting by Adama Diarra; Writing by Richard Valdmanis; Editing by Daniel Flynn)