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A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method, no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.
1. A processor for executing a plurality of instruction streams, at least one of the instruction streams being a master stream, the processor comprising:
an instruction cache for storing instructions for each of the plurality of instruction streams to be executed by the processor;
a plurality of functional resources for use by one or more of the plurality of instruction streams;
and inter-stream control bitmap, coupled to said functional resources, said inter-stream control bitmap comprising:
a plurality of control bits associated with active ones of the plurality of instruction streams, said control bits having a set of editable characteristics for said active ones of the plurality of instruction streams, said editable characteristics being set by at least the master stream.
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19. A multi-streaming processor, having an instruction cache for storing instructions for each of a plurality of instruction streams, at least one of the plurality of instruction streams being a master stream, the processor comprising:
a plurality of functional resources for use by one or more of the plurality of instruction streams; and
inter-stream control bitmap, coupled to said functional resources, said inter-stream control bitmap comprising:
control authorization bits, associated with each active stream within the plurality of instruction streams; and
priority bits, associated with each active stream within the plurality of instruction streams;
wherein said control authorization bits, and said priority bits contain editable characteristics for each of said active streams that regulate the forms of control that each of said active streams exercise over another; and
wherein the master stream has control over said control authorization bits for said active streams.
20. The multi-streaming processor, as recited in
21. The multi-streaming processor, as recited in
22. The multi-streaming processor, as recited in
interrupt detection logic, coupled to interrupt signals, for providing said interrupt signals to the multi-streaming processor;
interrupt mapping logic, for providing configurable interrupt mapping of said interrupt signals to ones of the plurality of streams; and
interrupt logic, coupled to said interrupt mapping logic, for interrupting one or more of the plurality of instruction streams according to configurable interrupt mapping provided by said interrupt mapping logic.
23. The multi-streaming processor, as recited in
24. The multi-streaming processor, as recited in
interrupt mapping bits, associated with each active stream within the plurality of instruction streams for indicating which of said active streams should be interrupted for a plurality of external interrupts.
25. The multi-streaming processor as recited in
The present application is a continuation of co-pending U.S. application Ser. No. 11/277,101, filed Mar. 21, 2006, which is a continuation of U.S. application Ser. No. 09/312,302, filed May 14, 1999 (now U.S. Pat. No. 7,020,879 that issued on Mar. 28, 2006), both of which are incorporated herein in their entirety by reference. U.S. application Ser. No. 09/312,302 (now U.S. Pat. No. 7,020,879) is a continuation-in-part (CIP) of U.S. application Ser. No. 09/216,017, filed Dec. 16, 1998 (now U.S. Pat. No. 6,477,562 that issued on Nov. 5, 2002), U.S. application Ser. No. 09/240,012, filed Jan. 27, 1999 (now U.S. Pat. No. 6,292,888 that issued on Sep. 18, 2001), and U.S. application Ser. No. 09/273,810, filed Mar. 22, 1999 (now U.S. Pat. No. 6,389,449 that issued on May 14, 2002), all three of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention is in the field of digital processors, and pertains more particularly to such devices capable of executing multiple processing streams concurrently, which are termed multi-streaming processors in the art.
2. Background
Multi-streaming processors capable of processing multiple threads are known in the art, and have been the subject of considerable research and development. The present invention takes notice of the prior work in this field, and builds upon that work, bringing new and non-obvious improvements in apparatus and methods to the art. The inventors have provided with this patent application an Information Disclosure Statement listing a number of published papers in the technical field of multi-streaming processors, which together provide additional background and context for the several aspects of the present invention disclosed herein.
For purposes of definition, this specification regards a stream in reference to a processing system as a hardware capability of the processor for supporting and processing an instruction thread. A thread is the actual software running within a stream. For example, a multi-streaming processor implemented as a CPU for operating a desktop computer may simultaneously process threads from two or more applications, such as a word processing program and an object-oriented drawing program. As another example, a multi-streaming-capable processor may operate a machine without regular human direction, such as a router in a packet switched network. In a router, for example, there may be one or more threads for processing and forwarding data packets on the network, another for quality-of-service (QoS) negotiation with other routers and servers connected to the network and another for maintaining routing tables and the like. The maximum capability of any multi-streaming processor to process multiple concurrent threads remains fixed at the number of hardware streams the processor supports. A multi-streaming processor operating a single thread runs as a single-stream processor with unused streams idle. For purposes of the present specification a stream is considered an active stream at all times the stream supports a thread, and otherwise inactive.
As described above and in the papers provided by IDS in the present case, superscalar processors are also known in the art. This term refers to processors that have multiples of one or more types of functional units, and an ability to issue concurrent instructions to multiple functional units. Most central processing units (CPUs) built today have more than a single functional unit of each type, and are thus superscalar processors by this definition. Some have many such units, including, for example, multiple floating point units, integer units, logic units, load/store units, and so forth. Multi-streaming superscalar processors are known in the art as well.
The inventors have determined that there is a neglected field in the architecture for all types of multi-streaming processors, including, but not limited to the types described above. The neglected field is that of communications between concurrent streams and types of control that one active stream may assert on another stream, whether active or not, so that the activity of multiple concurrent threads may be coordinated, and so that activities such as access to functional units may be dynamically shared to meet diverse needs in processing. A particular area of neglect is in mapping and handling of external and internal interrupts in the presence of multiple streams and also exception handling.
Accordingly, what is clearly needed in the art is apparatus and methods for more sophisticated interstream control and communication in all processor architectures that support multi-streaming or multi-threading, including but not limited to superscalar processors and processors that interleave instructions, particularly for mapping and handling of all types of interrupts and exceptions. The present invention teaches such apparatus and methods, which are disclosed below in enabling detail. Significant added flexibility, efficiency, and robustness are provided to multistream processor architectures and the ability to handle time-critical threads is enhanced at relatively low cost in the number of additional gates for implementation, as well as considerable additional benefits.
In a preferred embodiment of the present invention a multi-streaming processor system is provided, comprising a plurality of streams for executing one or more instruction threads; a set of functional resources for processing instructions from streams; and interrupt logic. Through the interrupt logic, interrupts or exceptions are detected and mapped to one or more specific streams. One interrupt or exception may be mapped to two or more streams, or two or more interrupts or exceptions may be mapped to one stream.
In some embodiments, mapping of interrupts to streams is static and determined at processor design. In other embodiments, mapping of interrupts and exceptions is programmable, and in some cases uses a storage file or table wherein the interrupt logic refers to the data store for mapping data to relate received interrupts or exceptions to streams. In other embodiments mapping is conditional and dynamic, the interrupt logic executing an algorithm being sensitive to variables to determine the mapping. In some other embodiments, it may be a combination of any of the above.
Interrupts may be external interrupts generated by sources external to the processor or, software interrupts generated by active streams. In some embodiments there is a mask for enabling/disabling recognition of mapped interrupts or exceptions.
In preferred embodiments, after mapping is determined for a detected interrupt or exception the one or more streams are interrupted by the interrupt logic. Further, after every interrupted stream acknowledges the interrupt, it is vectored to a service routine by the interrupt logic. In some embodiments, two or more streams are interrupted by one interrupt or exception, and the interrupt logic delays vectoring any stream to a service routine until all interrupted streams acknowledge the interrupt. In some embodiments two streams acknowledging the same interrupt are vectored to different service routines by the interrupt logic.
In another aspect of the invention a method for processing interrupts in a multi-stream processor is provided comprising steps of (a) detecting an interrupt or exception and passing the detected interrupt or exception to interrupt logic; and (b) mapping the interrupt or exception to one or more streams of the multi-stream processor. In step (b) in some embodiments the interrupt or exception may be mapped to two or more streams. In other embodiments, in step (a), two or more interrupts or exceptions are detected, and in step (b), the two or more interrupts or exceptions are mapped to one stream.
This mapping of interrupts to streams may be static and determined at processor design, programmable, as referring to a map in data storage, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. The interrupts may be external interrupts generated by sources external to the processor or the software interrupts generated by active streams.
In preferred embodiments, after mapping is determined for a detected interrupt or exception, the one or more streams are interrupted by the interrupt logic. After acknowledgement the interrupted stream or streams are vectored to a service routine. In some cases, two or more streams are interrupted by one interrupt or exception, and the interrupt logic delays vectoring any stream to a service routine until all interrupted streams acknowledge the interrupt. Two streams acknowledging the same interrupt may be vectored to different service routines by the interrupt logic. In further embodiments of the invention computing systems are provided having multi-stream processors having a plurality of streams for executing one or more instruction threads; and interrupt handling logic, the systems characterized in that through the interrupt logic specific interrupts or exceptions are detected and mapped to one or more specific streams. Again one interrupt or exception may be mapped to two or more streams, two or more interrupts or exceptions may be mapped to one stream. The mapping may be static, programmable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping.
In various embodiments of the present invention, described in enabling detail below, for the first time a system and method is provided for handling interrupts and exceptions for a multi-stream device in a flexible and orderly manner.
Multiple active streams operating in the same processor are often related by the nature of the threads supported. Advantages may be gained, therefore, if a thread running in one stream (an active stream) is enabled to initiate and/or control functions of one or more other active streams. Active streams may share work on the same task and may therefore need efficient methods of passing data. One active stream may temporarily require exclusive use of certain processing resources or of total throughput. Such an active stream needs a way of asserting its particular claims, while allowing other active streams to continue operating as efficiently as possible with fewer resources. These are issues in all multi-streaming processors. In this concept and the descriptions that follow, it is well to remember again that by an active stream is a stream that is running a particular thread, and also that a thread context is associated with an active stream by a register file.
Multi-streaming processors, as described in priority document Ser. No. 09/216,017, now U.S. Pat. No. 6,477,562, have physical stream resources for concurrently executing two or more instruction threads, and multiple register files as well. The present invention applies to all such processors and also to processors that may accomplish multi-streaming in other ways. In various embodiments of the present invention a set of editable characteristics is kept for active streams, and these characteristics regulate the forms of control that may be exercised by other active streams over that particular stream. These editable characteristics may take any one of several forms in different embodiments, by convenience or for special reasons. In preferred embodiments the editable characteristics are implemented in silicon on the processor chip, as this arrangement allows very quick access in operation. The invention, however, is not thus limited, and such characteristics may be stored and editable in other ways. The editable characteristics may also be mapped as stream-specific or context-specific in different situations and embodiments.
In one exemplary embodiment, a bit-map is maintained wherein individual bits or binary values of bit combinations are associated with individual streams and assigned particular meaning relative to inter-stream communication and control, indicating such things as supervisory hierarchy among streams at any particular time, access of each stream to processor resources, and state control for Master Stream, Enable and Disable modes, and Sleep modes, which are described in further detail below.
In the bit-map described above, some supervisory control bits regulate the forms of control that any other active stream may exercise over each individual active stream. Active streams may, within carefully defined limits, set and reset their own control bits, and other active streams with appropriate permission may also do so. A master thread, at any point in time, may run in a stream, which is then designated a Master Stream while running a Master Thread, and a Master Stream has complete control over slave streams, and may at any time override the control bits of the slave streams. If there is more than one Master stream running, each may have different designated slave streams. With appropriate control settings, active streams may act as supervisors of other active streams, temporarily (typically) controlling their execution and communicating with them. Further, a Master Stream has, and supervisor streams may have, control over what processing resources active slave streams may use, either directly or by modifying a stream's priorities.
In this embodiment a unique inter-stream control bit-map 115 stores individual bits, and in some cases binary values of bit combinations, associated with individual streams and assigned particular meaning relative to inter-stream communication and control, as introduced above. A shared system bus 113 connects the instruction and data caches. The diagram shown is exemplary and general, and the skilled artisan will recognize there are a number of variations which may be made. The importance for the present purpose is in the multiplicity of streams adapted to support a multiplicity of threads simultaneously.
It was described above that Inter-stream control bitmap 115 is a reference repository of control settings defining and configuring Inter-stream control. In this reference single bits in some instances, and binary values represented by two or more bits in other instances, define such things as priorities of an active stream for shared system resources, fixed resource assignment to particular streams, and control hierarchy among active streams. Specific control characteristics in one exemplary embodiment are described below.
In one aspect of control in this embodiment of the present invention, an active stream is enabled to set and edit control reference data unique to that stream. In another aspect one stream may alter the control reference data for other streams. In the latter aspect each particular stream may control which other streams may edit which control data for the particular stream.
The first column from the left in
An example of a situation wherein stream 0 might grant access to one or more streams to edit its own control data configuration would be in the case that stream 0 is running a very low priority thread, or is not running a thread at all, and is simply available for a new thread.
The second column in
The next bit column is labeled priorities, and a logical 1 in this column for a stream indicates that stream 0 grants another stream permission to set priorities for stream 0. In the instant case stream 0 does not allow any other stream to set its priorities. Priorities are typically set in embodiments of the invention to indicate access to processor resources. The next bit column is labeled interrupts, and means that another stream may interrupt stream 0. In the instant case stream 2 is granted the interrupt privilege.
It should be clear to the skilled artisan, given the teachings of this specification, that there are a variety of revisions that might be made in the matrix shown, and the meaning of specific columns. It should also be clear that the matrix illustration is exemplary, and the bits described could as well be individual bits in a two-byte register, as long as the convention is kept as to which bits relate to which streams and to which control functions and resources.
In preferred embodiments of the present invention inter-stream control is described for multi-streaming, super-scalar processors, meaning processors that have multiple streams and also multiple functional resources. Such a processor may have, for example, several integer processing units, several floating point processing units, several branch units, and so on. The inter-stream control configuration indicated by bitmap 115 (
In some cases, rather than relying on a fixed assignment and division of resources in a superscalar processor, better results may be obtained by assigning resources by priority to streams, or by a mixture of assignment for some resources and priority management for others. By fixed assignment is simply meant that for a period of time, as shown in
The second row from the top in
The lower three rows of the priority level settings for stream 0 in
At the point in time illustrated stream 0 has a seven (highest) priority for integer units, a priority level of four for floating point units, and a priority level of three for branch units. These settings are exemplary, and there may well be, in alternative embodiments, priorities maintained for other processor resources. In various embodiments of the invention temporarily fixed resource assignments may be used exclusively, in others priority may be used exclusively, and in still others, a mixture of the two. Resource priority means that in a case of contention for a resource, the active stream with the highest priority will claim the resource.
In this embodiment of the invention other control bits are used to indicate control hierarchy and state.
A Master stream is a Master stream by virtue of running a Master thread, and an active Master stream has complete access and control over other streams, which are slave streams to the Master. It is not necessary that any stream grant the Master stream permission to edit control configuration. A Master stream may have a variety of duties, one of which, in preferred embodiments, is initial setup of a multi-streaming processor. On startup and reset in a system utilizing a processor according to an embodiment of this invention, a Master stream will typically be called at some point in the boot process, and will act for example to set initial priorities for streams, to set supervisory bits, and to start specific threads in specific streams. These duties can and will vary from system to system, as, in some cases some default settings may be made by executing specialized BIOS code, and a Master thread may be called for further setup duties, and so on.
After startup a Master thread need not typically remain executing in a stream of the processor. The Master stream, having accomplished its ends, may set another thread to start in the stream it occupies, then retire, or may simply retire, leaving an inactive stream available for use by another active stream to execute such as an interrupt service routine, a utility function of another sort, and the like. A Master thread may be recalled after retiring for a number of reasons. For example, a contention for resources may require the Master for resolution, or an interrupt or exception may require the Master stream for resolution. It will also be apparent to the skilled artisan that the Master stream in some systems may be running the Operating System or a portion thereof, or a routine loaded and active with a system BIOS, and the like. In some systems according to embodiments of the invention, all inter-stream control functions may be disabled, allowing the processor to run just as a processor without the control capabilities taught herein.
In some embodiments there may be certain fixed functionality. For example, a processor according to the invention may be hard-wired to make one stream always the Master stream, and no other. By hard-wired is meant that certain functionality is preset by the hardware resources implemented in silicon devices and their connections. Specific assignments of other threads to specific streams may also be set. In such cases, specific resource priorities and/or assignments may also be set, or any other of the inter-stream functionalities taught herein. Such pre-setting will be highly desirable for highly dedicated system applications, such as, for example, network routers and the like.
It will be apparent to the skilled artisan, following the teaching herein, that there will be a number of ways that control data may be represented, stored, and accessed. The illustrations provided herein are exemplary. In a preferred embodiment, the control data map is implemented in silicon devices directly on the processor chip. This arrangement is preferred because, among other things, access to the control data is fast. In some embodiments, however, a control bitmap may be in any accessible memory device in a system, such as in an otherwise unused portion of RAM, or even on such as a flash card memory.
The concept and existence of a Master thread in a system according to an embodiment of the present invention has been discussed above. All other threads are slaves to a Master thread, so all active streams other than one Master stream are slave streams to the Master. There are, however, other levels of control other than Master and slave. Specific streams may be granted supervisory control, and be expected to exercise supervision responsibilities over other streams, as may be inferred from the teaching above. The state of supervisory bits in the embodiments of the present invention described above reflects the granularity of supervisory control.
It was described above that a Master thread may pursue such ends as initial setup and loading of threads into streams, and may return to resolve conflicts and exceptions. Just as in any other processor system, however, the overall system function is to execute one or more applications. In a general-purpose computer there may be many applications, and the uses of the computer are similarly many. One may browse the Internet, send and receive e-mails, make drawings, process photographs, compose word documents, and much more. Typically each application is dedicated to particular functions, and application threads, as applications are called, occupy one or more of the streams of the processor.
In more dedicated systems, such as, for example, a data router in a packet data network, there are relatively fewer applications, and the functions of the machine are typically ordered in some fashion other than user-initiated. In a data router, for example, the functions may be called according to characteristics of data received to be processed and forwarded.
In one aspect of the invention, software is specifically enhanced to take maximum advantage of the new and unique control functions of a multi-streaming processor according to embodiments of the invention, although this is not required in all embodiments. Also, some software executing on a processor may be enhanced according to embodiments of this invention, and other software may not. Typically, there will be at least an operating system or Master thread, or both, with specific code to cooperate with the new control and status functions built into a multi-streaming processor according to embodiments of the invention.
Given the control data resources and functions described above with reference to
Given the descriptions and exemplary architecture described above, there are a broad variety of inter-stream communications and control functions that may now be performed that were not available prior to the present invention. For example, any one active stream may manipulate its own resource allocation and priority according to its needs, which will relate closely to the nature of the thread running in the stream, and the nature of other threads available to run or actually running in other streams. Also an active stream may start, enable, disable, interrupt, branch, and join other streams with prior knowledge of possible repercussions, because each active stream may check the control data settings for other streams. The enormous advantage provided is an ability to maximize real-time efficiency rather than simply use of processor resources. That is, system goals may now be addressed. Processors have historically been designed to maximize processor resources, in an often incorrect assumption that to do so necessarily addresses system goals as well. It is easy to understand, however, that a multi-streaming processor may be fully engaged efficiently accomplishing low-priority tasks, while higher priority tasks receive inadequate attention, and therefore does not adequately address system goals.
In embodiments of the present invention, one active stream, running a thread (application) that may need or be enhanced by another thread running in parallel, may call the subservient thread and start it in an available stream. An example is a WEB browser accessing a WEB page having an MPEG video clip. The browser, running in one stream of a processor according to an embodiment of the present invention may call an MPEG player to run in an available stream. The state of the data control bits and values will guide the browser stream in selecting a stream for the MPEG player. The browser may not, for example, co-opt an active stream running a thread having a higher priority. It may, however, co-opt a stream that has set its control data bits that it may at any time be interrupted.
Operation in this embodiment can be illustrated by following a sequence of operations to accomplish a typical task, such as forking a new thread. Threads can fork other threads to run in different streams. For example an operating system may wish to fork an application program, or an application may need to fork a sub-task or thread. A thread encountering an exception may fork a process to handle it.
A preferred method in an embodiment of the invention for fork and join operations is shown in
To initialize stream 2 to run the new thread, active stream 1 loads the assigned stream's program counter with the address of the first instruction in the new thread and loads other components of the new thread's context into appropriate elements of processor resources in step 204 and sets the priority map for stream 2 in step 205. Stream 1 may also set supervisory control bits 107 for stream 2 in step 206. (Alternatively, the new thread, running in stream 2, may set the bits after step 208.) Stream 2 must have its supervisory control bits set to allow the supervisor thread to act as its supervisor and the supervisory control bits of the supervisor must be set to allow the controlled thread to interrupt it. When these initializing steps are done, the supervising thread starts the new thread in stream 2 in step 207. Alternatively, stream 2 may be put in sleep mode, waiting on an internal or external event. The new thread starts running in stream 2 in step 208. In steps 209 and 210 both streams run independently and concurrently until a join is required. In this example, it is assumed that the thread running in stream 1 finishes first.
When the supervisor thread needs to join the forked thread, it checks first to see if the forked thread is still running. If so, it executes an instruction at step 211 that puts itself to sleep, setting the sleep bit in stream control bits 118, and then waits for a join software interrupt from the forked thread. The forked thread sends a join interrupt in step 212 and the supervisor thread receives the interrupt and wakes in step 213. The supervisor completes the join operation in step 214. Finally the forked thread ends in step 215, freeing its stream for use by another thread.
As shown in
The RTD does the context switch in step 302. When the RTD is done loading the new stream's context, it can make the freshly loaded register file active and start the new stream in step 208, again, independently of the supervisor stream. Step 207 of
The embodiments described above are exemplary of many embodiments that may be implemented within the scope of the present invention. Those skilled in the art will recognize that the powerful architectural concepts taught for the first time herein may be applied to many types of processors, including but not limited to single-chip systems, microprocessors, controllers, routers, digital signal processors (DSPs), routing switches and other network devices, and processors designed for other special uses. The teachings of this invention may be practiced in conjunction with processors of any size, from simple one-chip complete systems to complex supercomputer processors. The invention may be realized in simple and highly dedicated form for small systems or in complex, sophisticated form for large systems. By defining and enabling master and supervisor streams to control the utilization of resources of slave streams, a processor can be dynamically configured to meet the requirements of particular software and software mixes, to meet strict timing requirements for example. Streams can, for example, be guaranteed a certain percentage of overall processor throughput, or a percentage utilization of particular resources or classes of resources. Thus the new architecture allows balancing the optimization of the execution of particular threads along with efficient use of processing resources.
As a further example of the use of priorities, consider a router for use in a packet-data network embodying a processor according to
Another example of the use of priorities may also be illustrated by a data router system. Consider such a system having four streams, wherein one or more threads are available to streams for processing data packets. Assume that contexts have been loaded to register files and associated with streams to start a thread in each of the four streams to process arriving data packets.
As is known in the art of data routers not all data packets need equal processing. Some packets need only be forwarded as received. Others may need to be restructured into a different format. Still others will need to be, for example encrypted/decrypted. The type of packet dictating the work flow to process the packet is typically contained in a header for the packet, and the type and scope for processing can only be known to the processor after a thread context is loaded to a register file, the register file is associated with a stream (active stream) and processing is commenced on a data packet.
In a preferred embodiment of the present invention, as was illustrated in
As described immediately above, it is necessary to commence processing of a data packet before the nature of the packet may be known. Therefore, as packets arrive and register files are loaded, each context is given an initial high priority. For example, on a scale of seven, each initial context will be assigned a priority of six.
Now, as streams become available, register files are associated with streams, according to priority of the register files and the execution priority of the streams. Associating a register file with a stream starts the context thread in the stream, constituting an active stream. The stream's execution priority is now set to the high priority (in this example, six) of the context that was loaded. As processing of the newly-loaded packet begins, it may be determined that the packet is indeed a fast packet, and the high priority is indeed appropriate, in which case the processing will continue to completion. In the present invention, at the completion of processing of a packet it is desired that the next context started in the stream be the highest-priority-level waiting context. This is done in this example by selectively lowering the execution priority until a context loads, or the execution priority is zero. The only way zero will be reached is if there is no waiting context of any priority. In this situation the stream will remain idle until any context becomes available.
In this example, if the execution priority is six at the end of processing a packet, the execution level is reset to five, then four, and so on, which assures that the next context loaded will be the waiting context with the highest priority level.
As processing commences, however, it may be determined that the packet is of a type that deserves an intermediate priority. The thread running in the stream then lowers the execution priority to perhaps four. If there are no waiting contexts higher than priority four, the active stream continues to process the data packet to completion, and follows the example described-above, wherein, upon completion the stream will set its execution priority to three, then two, and so on until a new context loads. If, however, a new packet has arrived, since new contexts are given an initial priority of six, the arrival of the new packet will force a context switch, causing the stream to cease operations on the slower packet, and to commence processing instead the new, higher-priority data packet, resetting the execution priority of the stream to six.
If the context switch ensues, the saved context still has a priority of four, and will await opportunity for re-assignment to a stream for further processing, typically under control of the RTU, as described above. There is, of course, no guarantee that any newly arrived data packet is a faster packet, but there is a certain probability that this is so. If the new packet is a faster packet, then system goals are enhanced. If not, then the active stream, now at priority level six again may again lower its own execution priority to potentially delay execution of the newly loaded packet, and seek again a faster packet to process. The new packet, for example, may be a very slow packet, requiring decryption. The active stream may then lower the execution priority to two, and again force a context switch if a new packet has arrived for processing, in which case a context will be saved with a two priority for the slow packet, which will than wait for processing opportunity by virtue of priority. If a stream is running at an execution priority of two, no new packet (six) arrives, but there is a waiting context with a four priority, the four context will pre-empt the stream with the two execution priority, and so on.
In this manner, packets may be processed with priority according to type, even though the type cannot be known until the context is loaded and processing has commenced on each newly-arriving data packet, providing a new way for system goals to be met in data routing applications, while also ensuring processor efficiency.
Many other useful functions are consistent with the invention's teachings regarding interstream control and communication. In a simple two-stream controller for a dedicated application, for example, with a fixed master/supervisor and a fixed slave stream, a single supervisory control bit for the slave stream could give the master stream a useful type of resource control, such as allowing access to a floating point unit, while allowing the slave to suspend such control during critical periods using the supervisory control bit.
The types of control that one stream may have over other streams through the mechanisms of supervisory control bits and stream control bits are not limited. A single type of control or a large number of controls may be appropriate, depending on the purpose of the system. Additional controls could regulate the sharing of global registers or global memory, memory protection, interrupt priorities, access to interrupt masks, or access to a map between interrupts or exceptions and streams, for example. In a processor with one or more low power modes, access to power control may also be regulated through additional supervisory control bits and stream control bits or such control may be reserved exclusively for a stream that is running the master thread.
The type of control that one stream may have over another stream's resources can also take many forms. In one of the simplest forms, a simple two-stream controller, for example, to be used in a dedicated application, with a fixed master/supervisor and a fixed slave stream, a single stream control bit for the slave stream could give the master stream the ability to disable the slave during instruction sequences when the master needs full use of all resources.
Priorities and scheduling of any form described in priority document Ser. No. 09/216,017, now U.S. Pat. No. 6,477,562, may be implemented in combination with the new teachings of the present invention. If such priorities are not implemented, then a stream could exert a simpler form of control by directly blocking another stream's access to one or more resources temporarily. In this case the supervisory control bits representing priorities would be replaced with bits representing resource control. Priority maps would be replaced with one or more control bits used to temporarily deny access to one or more resources or classes or resource. For example, if one stream needs exclusive use of a floating point unit, it can be made a supervisor of the other streams, and set resource control bits denying access to the floating point unit in each of the other streams while it needs exclusive access. If another partially blocked stream encountered a floating point instruction, the instruction scheduler would suspend execution of the instruction until the floating point resource control bit for that stream were reset by a supervisor stream.
The area of interrupts and exceptions has been but briefly described in the aggregate disclosure above. It will be appreciated by the skilled artisan, however, that the existence of multiple streams, with all of the many new degrees of freedom and versatility introduced thereby, creates a considerable complexity where interrupts and exceptions are concerned. The inventors have determined that there is a significantly neglected field in the architecture for all types of multi-streaming processors, including but not limited to the types described above: the flexible and orderly handling of interrupts by individual streams, as a general method for accommodating devices external to the processor, exceptions, and inter-stream communications. Accordingly, the present inventors have further provided unique and powerful apparatus and methods for extending functionality through interrupt and exception coordination and mapping. These new techniques are presented below in enabling detail.
In embodiments of the present invention related to interrupts and exceptions the inventors recognize several types:
External—the interrupt is generated by a device external to the processor, such as a printer interface, modem or other I/O device.
Internal—special instructions are executed by the processor that intentionally generate interrupts for purposes such as quickly calling a section of code or communicating between threads. Such interrupts are also known as software interrupts.
Exception—a special "exceptional" event occurs during processing, caused by execution of an instruction or a hardware error. For example, an instruction may attempt to divide a number by zero, a return stack may overflow, or an attempt to fetch from memory may generate a memory parity error.
In the realm of software interrupts, in the context of multi-stream processors, in embodiments of the present invention, a thread executing in one stream can interrupt another stream. In descriptions herein it will be said that one (active) stream interrupts another stream, which may or may not be active. This mechanism is used in embodiments of the invention to initiate processing of special events or at specific places in a code sequence. In some instances an active stream can use this inter-stream interrupt capability to gain control of the processor, preempting and stopping execution of threads in other streams. In another example, an inter-stream interrupt may be used by one stream to request some task be done by another stream to improve performance or response.
As an example of an internal, stream-to-stream interrupt, one can imagine an application program (thread) running in one stream, wherein the application has repeated and frequent need for executing another thread or task. Typically such a process in the prior art would be accomplished by calling the task, performing a context switch, processing the task, then performing another context switch to return to the original thread. In embodiments of the present invention, having dedicated registers for each stream, the main application can be mapped to one stream and the other task to another, with the first stream interrupting the second when the task is needed, avoiding considerable processor overhead.
The skilled artisan will understand that this is but one of many examples of inter-stream interrupts. The methods and hardware constructs needed to accomplish such mapping and inter-stream activity is described in more detail below.
In an extension of the mechanism of inter-stream interrupts, in embodiments of the present invention an active stream may pass off exception processing to another stream. In this process the stream encountering an exception interrupts the stream mapped for exception processing, and waits until the exception-processing stream finishes before continuing with its own processing. This unique capability is especially important for real-time systems so the overhead of changing contexts may be avoided. Structured exception handling could then also be implemented in hardware.
For an external interrupt, as described briefly above, the interrupt (405) is generated by a source external to the processor, and is detected in a multi-stream processor according to embodiments of the present invention by Interrupt Detection Logic 403. This detection can be done in any of several ways. The external devices may, for example, exert each a dedicated interrupt line having an input pin to the processor, and the detection can be on leading or trailing edge of a voltage change, for example. Other means of interrupt issuance are known to the inventors.
Once an external interrupt is detected, logic 403 communicates the receipt of the interrupt to Logic 407. It is the task of Logic 407 in this embodiment to process the interrupt according to one of several possible mechanisms, new in the art for multi-streaming processors. Specifically, Interrupt Logic 407 receives the interrupt and decides which stream or streams to interrupt depending on the type of interrupt and on one or any combination of the following mechanisms:
Once Logic 407 determines the mapping, streams are interrupted on logical paths 411. The skilled artisan will recognize there are several ways the interrupt may be issued to a stream once the determination is made. Once an interrupt is issued to a stream or streams, the streams have to acknowledge that they are ready to execute an interrupt service routine. (Vectoring to an interrupt service routine is a process well-known in the art to those with ordinary skill. This acknowledgement can occur at different times for different streams. Any delay may be due to code currently executing on the stream, or the stream may temporarily mask the interrupt. The interrupt, however, will remain pending as long as the external source exerts the interrupt. Interrupt detection logic 403 will control this behavior. If multiple streams are required to acknowledge the interrupt, the interrupt logic will wait till all of them have acknowledged before sending an external acknowledgement. This behavior can be modified as necessary, i.e. the external acknowledgement can happen after only one stream has recognized the interrupt or in any other combination.
As each stream acknowledges an interrupt, the interrupt logic sends the appropriate service vector to the stream. This vector may be the same or different for each of the streams. Depending upon the vector that the stream receives, the associated interrupt service routine will be loaded into the stream to begin executing. Hence different streams could have different responses or behavior for the same interrupt. Example—an audio device may interrupt two streams, one of which vectors to the interrupt service routine to store the audio data to a hard disk drive. The other stream may vector to an audio playback routine, and direct the audio data directly to speakers.
After each stream that is interrupted finishes its interrupt service routine it will normally return back to whatever thread it was running before the interrupt occurred. Again different streams can take different amounts of time to go back.
Internal interrupts, as briefly described above, are generally software interrupts that are used by programs to request specific functionality from the operating system or to execute sub-routines. These interrupts in embodiments of the present invention are managed to behave with the degrees of functionality described above for external interrupts. Software interrupts issued by active streams are processed by logic 407, and the interrupt logic can handle these interrupts and map them according to the three types as described above. Another variation on the mapping is the special case wherein an interrupt is only mapped to the stream executing the soft-interrupt. The rest of the steps will be as above.
Synchronized interrupts are variations on the above cases,. i.e. both internal and external interrupts. Synchronized interrupts behave differently in the vectoring stage. In the case of synchronized interrupts, the interrupt logic will not vector the streams to execute interrupt service routines until it has received acknowledgements from all the streams to which the interrupt is mapped. This behavior is to require a synchronized start of response to an interrupt. For example, consider a debugging interrupt, i.e. a breakpoint set on a thread executing on one of the streams. The debugger may want to view the state of the system at a stable point, i.e. at the point where all the streams have stopped executing whatever thread they were executing. Hence, the interrupt logic will generate the interrupt to all of the streams, but will wait till they all have generated acknowledgements before vectoring them to the debugger service routine. However, even though the logic waits for all the streams to catch up, the streams that acknowledge are stopped from further execution.
Exceptions are generated by code running in the streams and generally indicate error conditions. Exceptions are always synchronous to executing code, i.e. the stream generating the exception will always do so at the same point. There may, however, be many different responses to exceptions.
Self-response—This is the same as in a standard non multi-streaming processor. Here the stream generating the exception stops whatever it is doing and vectors to the exception handling routine and starts executing code from there. When the exception handler routine finishes, it will normally return to the point in the original code where the exception took place and the original thread will continue execution.
Blocking send to another stream—Here the stream generating the exception will stop execution of the current thread, but will not acknowledge the exception itself. The exception instead is broadcast to all other streams. Whichever stream is programmed or mapped to acknowledge the exception will do so and start execution of the exception handler routine. If no stream acknowledges the exception, then the Master thread will be sent the exception. If the master thread is already executing, it will now vector to the exception handler. If it is not running, it will be made active and allocated to a stream for execution, and then it will handle the exception. The Master thread is always capable of acknowledging any exception, if no other thread will. This way structured exception handling can be implemented in hardware. Once the exception routine returns, the original stream is notified and can then start its execution again. This method is implemented mainly for the reason that all streams may not have access to all the hardware resources needed to process a certain exception, and hence the stream that is incapable has to pass the exception to one that is capable.
Non-blocking send to another stream—This method is similar to the one above, but the original stream that generates the exception is not blocked. It generates the exception and then continues executing. Exception handling is guaranteed to complete by another stream or the master thread. This method is generally used for non-fatal exceptions like overflow. As an example consider the overflow exception—the stream generating the overflow sets a flag to indicate that it generated the exception and continues to execute. Another stream can acknowledge the exception and update a counter to count the number of times a particular value overflowed.
Any exception can be mapped to any of the above three categories. This mapping can again be done using the same techniques as for the interrupts. Exceptions can also be synchronized, in that an exception handler may not be executed until all the streams that that exception is mapped to have stopped executing and acknowledge the exception.
Implementation of the mechanisms described above, involving software and hardware interrupts and exception handling relative to multi-stream processors, may in some instances (programmable mapping) be accomplished partly through an alterable control file. Referring to
It will be apparent to the skilled artisan that there are many alterations that may be made in the embodiments described above within the spirit and scope of the present invention. For example, there are many ways the supervisory characteristics and relationships between streams may be recorded and amended, beyond the examples provided. There is similarly a broad range in granularity in control that may be exercised, and so on. Accordingly, the invention is limited only by the breadth of the claims below.
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Beyond the Performance
Jazz Connect, the popular series of pre-show jazz talks, continues this season for Ferst Center Presents jazz shows. Arrive at 7 p.m. to enjoy free discussions about the music of each jazz artist.
Led by Jay Edwards, host of Jazz Tones on WCLK 91.9 FM, you'll learn more about the artist and their particular style of jazz performance.

subset: commoncrawl


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Hold down Control (PC) or Command (Mac) key + mouseclick to select more than one option
|Avg. Dinner Entrée
|Greater than $25
|$18.01 - $25
|$12.01 - $18
|$7.01 - $12
|Less than $7
Posted by anonymous on 03/15/2010
I sometimes have to go here for work lunches and I think this is one of the worst places in midtown in terms of value and tastiness of food. It is so ridiculously expensive for no reason. Also, I just visited the restaurants website because I have to go there later today, and they require a log in to view the site! Whats that about...
Posted by John G on 01/11/2010
I just ate at Fresco and they have some nerve charging what they do for food. I paid $30 for a chicken ceasar salad! There is nothing you can do to a salad to make it worth that much money and they didnt try. It was a regular salad. The pasta and apps where freshly made and the food was good but not so much better that they can charge you 2x as much as any other high end restaurant. Hope this helps
Posted by Lily on 01/11/2010
I stepped in here with an associate and a client for a business lunch. While I found the restaurant to relate a homey, welcoming atmosphere; I received a different feeling from the people associated with this restaurant. Many of their waiters were pretentious and much too stoic for my taste. They did not make lunch very comfortable while they were standing a distance away watching us eat and chat. I thought the pasta was average; therefore, highly overpriced. Lunch came out to over $200 for three people, and we did not even order drinks.
Posted by KB in NYC on 07/29/2009
I just love Fresco because you can get terrific hearty pastas as well as delicious lighter entrees. So often, I dine with friends that want traditional Italian fare (read pasta) while I'd like something less heavy. At Fresco, we get the best of both worlds; their amazing pasta dishes (Penne Gratin is sinfully devine) and I can have their heavenly Halibut dish. A huge portion of fish with seasonal veggies in a flavorful broth. Yum. Or their lighter, brothy and flavorful Spaghetti with Fresh Clams. Okay, I hear ya, it's pricey but you get what you pay for. Finally, the Scotto's are lovely and it's nice to patronize a family-run place.
Posted by M H on 03/10/2009
Another place for me to blow my corporate expense. Food is okay, service is not bad.
Posted by Out of Towner on 12/07/2008
I ate here for the second time and was treated horribly. I guess because I was eating alone, they put me in the front of the restaurant. I had made my reservations 3 weeks prior to coming to New York. I told them that I had made my reservation weeks ago, and that I wanted to be in the dining room. They said they would not put me there. I should have just walked out. They will not ever get my money again.
Posted by LZ on 11/17/2008
Dined at Fresco first time over the weekend, on a Saturday night. Here is my observation - hope it helps! Had reservations - was taken on time. We were asked to check our coats and I guess we were taking a bit too much time because the hostess sang out "I'm ready whenever you are"..... ok, let that go.... Taken to our table, have got to admit not many tables for "2", more of a group family type place. Asked if we would like a glass of wine, but there was no listing of what wine was available or price? After ordering the wine the hostess arrives back claiming we should really move your table, a large party is coming behind you and its going to be difficult. She had a much cozier table for 2. Ok we say - we get up and follow her all to find NOT a cozy table but one that was connected to another-sort of like a corner of a booth -where we would need to sit side by side and face other diners. I told her I was much more comfortable at the other table, and this seemed to annoy her. She sternly stated "they are going to leave you know"! I then said and aren't more people coming in? She said snottily -"I would imagine"! Exactly I said, I would like my table back. "fine!" she sated. Well it was a bad spot. getting hit in the back multiple times. WAY Too many tables cramed in Very crowded, The waiter behind us dropped a dish while trying to serve between crowded tables - Food was good but WAY to expensive, Dinner for Two came to $200.00 - Waiter was the best! Nicest! Better than the Evil Hostess...Tall Woman with trendy glasses. All in all, food is good but not worth $$ - if your going to charge at least have some ambience - dated looking atmosphere - Draws in an older crowd of people... Needs a face lift and a price drop!


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What kind of tools do you use to help you get out of debt? If you're looking to go beyond your trusty spreadsheet or the envelope method, here are a few recommendations for how free software can help you get out of debt and get you closer to achieving all your personal finance goals.
Making a Plan to Get Out of Debt
Planning is something that becomes a lot easier with software. Instead of the hazy picture you have when all of your account statements are scattered around your house and you can't remember which one has the highest interest rate and which one has the lowest interest rate – not to mention which one has a payment due tomorrow – you need a software programs can put all of that information into one place. You need to make your life easier and have a clear plan in front of you.
That's where online software like ReadyForZero can really help. It's free, and it allows you to see all your accounts in one place so that you have a clear picture of how much you owe and how long it will take you to get out of debt. Free get out of debt software like ReadyForZero also helps because it gives you a chance to make your plan and then track your progress.
If you prefer to try a more simple tool at first, you can use this calculator to get a better look at your big picture in terms of your debt. Of course you need to pay off your debt, but it's helpful to know what the overall amount is and how you can break it into chunks that are more manageable.
Tracking Your Daily Expenses to Help You Get Out of Debt
I track my daily expenses, but I hate doing it manually. By syncing up my credit card and bank accounts with Mint, I can see my expenses being tracked automatically. The software also keeps track of what my trends are, how I'm doing with my financial goals, and has very rudimentary budgeting. You can also set up alerts for when you go over your preset budget or when your expenses suddenly increase, which has been very handy for fraudulent charges as well.
However, if you want to track your daily expenses manually, you can get a daily email from The Birdy to enter your expenses. You can enter your expenses by email or by text, and it also tells you what your trends are and how your spending breaks down. When you create a streak, you also get a humorous video to keep you motivated.
Borrow up to $35,000Fast Approval. Funds Direct Deposited. May Build Your Credit With On-time Payments. A fixed rate loan without any hidden fees or pre-payment penalties. Check Your Rate
Daily Reminders
For budgeting, Mint also provides handy widgets for my Android phone so that I can see how much cash I have on hand, credit card balance, and my most recent transactions at a glance. And ReadyForZero has similar alerts and notifications centered around your debt (credit cards, student loans, mortgages, etc.) – so you can get alerts when payments are due and find ways to pay off debt faster. When I'm out and about and just about to make an impulse purchase, looking at my credit card balance (and then wincing) often has me putting my credit card away.
On the flip side, I love watching my salary come in and my retirement balances go up, which is possible when using these apps. It can actually be very addicting to see your net worth increase and your debt go down!
Setting Goals
We often talk a lot about goal-setting here at ReadyForZero, and as you can imagine, there are apps for that too.
Let's say you want to make lunch every day for work so you can save money and pay off your debt. This is very doable, right? But how often are you actually making lunch? And it's so easy to go out to lunch.
Track your progress with a goal app. I like Lift, because it also brings in a social aspect where your goals have a community around them to help support and encourage each other's progress.
If you just want to track your progress with Jerry Seinfeld's "don't break the chain" method, try apps like Hab It! You can create streaks where you are checking off every day you accomplish your goal and build your habits.
No matter what apps or free software you use, we are here to help you get out of debt and reach your financial goals. Are you using specific tools not mentioned above? Let us know in the comments below!
Image Credit: Robert S. Donovan


text: ALBANY, N.Y. (AP) - Zephyr Teachout has survived another attempt by supporters of New York Gov. Andrew Cuomo to knock her off next month's Democratic Primary ballot. On Wednesday, a panel of appellate judges upheld a lower court's decision that Teachout is eligible to challenge Cuomo. Cuomo supporters alleged that the law professor didn't meet the five-year residency requirement. The challenge was brought by two men listed online as Cuomo campaign interns. They noted in court papers that Teachout listed a Vermont address on documents in 2012 and obtained a New York driver's license this spring. It was unclear Wednesday if they planned to appeal to the state Court of Appeals. Teachout says she moved to New York City in 2009 and that Cuomo wanted to keep her off the ballot to silence opposition


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Rear Fender Wiring
Putting this in the Dyna Spot just because most of them have the same rear fender (except FXDWG) and potentially the same issue.
A few months ago I installed HD permanent sissy bar mounts which required the removal and replacement of the fender strut bolts on both sides of the fender. I noticed, at that time, a wire bundle coming out of (or into depending on how you look at it) the tail light and leading to the left rear turn signal. I noticed there was a clip inside the fender to hold that wire away from anything, such as the rear tire. I made sure I put that wire securely in that clip when I got done with the install. Recently, while washing the bike, I noticed the wire hanging below the edge of the fender and had to put it back in the clip. I made sure, at that time, to make sure the clip was as snug as I could get it to make sure the wire didn't slip out again. Well, the other night it did. On my ride back from OBX bike week, I noticed my signal indicator flashing rapidly and looked back to see that my left, rear signal was out. I assumed it was the bulb. The next day, I realized that the wire had come out of the clip again and rubbed against the rear tire long enough to get eaten in half and about an inch or so of wire chewed away as well. I had a time splicing it back together an wrapping it well with tape.
Now I'm trying to think of a way to prevent that clip from losing the wire again without permanently closing the end of it. I have tape on it now but that's likely not to hold after the first rain or puddle I hit.
Any ideas or similar experiences?
Re: Rear Fender Wiring
Mine did the same thing right after I got my bike.I bought It used and the guy who owned it flush mounted the tail light and the wires were not clipped up well. Rubbed the wires in half and left me in the dark at night on back roads 10 miles from home. I ended up soldering the wires together and using heat shrink and wire ties to seal them well and hold them in place. After a scary 10 mile ride
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At the beginning of the global economic crisis several years ago, most economists and policymakers believed that Indonesia could weather the global economic storm well. In part, this was due to the low reliance on international trade.
In addition to the low proportion of exports to GDP, commodities – which tend to enjoy relative stable demand and prices – account for almost half of Indonesia's exports. This provided a reliable buffer to absorb the impact of the economic crisis.
This situation seems in question today. Indonesia's exports have fallen while at the same time imports have shown a stable trend, translating into a trade deficit of $640 million in April. This has made people nervous despite the fact that in the first four months of 2012, Indonesia still booked a trade surplus of more than $2 billion. The nerves are perfectly understandable, since for decades the country has always experienced a trade surplus, making most Indonesians allergic to the words "trade deficit."
For commodity net exporters such as Indonesia, 2012 and the years ahead will be rather uneasy. The economy and exports are influenced by global commodity demand and prices. Consequently, the gradual decrease in prices will impact the government's fiscal position, corporate profits and household incomes.
Falling demand
The Organization for Economic Cooperation and Development (OECD) forecasts that the economies of the EU, the US, India and China will grow at 1.6%, 2.4%, 7.3% and 8.2% respectively this year, much lower than the pre-crisis level. Other studies by the International Monetary Fund and the World Bank also indicate the same pattern. This relatively low growth in the world's major economies means that consumers are the root of the commodity price decline.
Unfortunately, the EU faces structural and domestic political issues in handling its crisis properly. It may take years for it to recover, potentially disturbing the recovery process in the US and possibly lowering GDP growth in India and China.
Over the past year, the price index of Indonesia's major commodities – coal, natural gas, palm oil, copper, coffee and cocoa – have decreased significantly. Only gold and tea have moved in a different direction. If the forecasts for the EU and the US economies materialize, commodity prices will not bounce back in the near future.
Meanwhile in Indonesia lower exports are not accompanied by lower imports. The growing number of Indonesia's middle-income class is one of the key factors behind the stable or increasing imports, especially for products like gadgets, computers, electronics, home appliances and vehicles. From the purchasing power perspective, this is a good development since those who purchase imported products will also purchase various domestically produced goods. However, from the international trade point of view, it is a challenge.
What Indonesia can do
Commodity prices from 1960–2011 indicate two trends. First, commodity prices tend to be more volatile. Second, the correlation among commodity prices tends to be higher. Prices move in tandem, with the oil price taking the lead. In the past, a decrease in the price of some commodities can be offset by the increase in the price of others.
In the current economic setting, producing various commodities is not a good portfolio. In short, economies that rely too much on commodities will tend to be volatile. They will move up and down in line with global commodity prices.
This is a warning sign for Indonesia to reduce its reliance on commodity exports. This is not only volatile, but also has low economic value-added. In the long run, Indonesia should transform itself into a more high-tech goods producer. With limited natural resources and its huge population, Indonesia can not achieve a high GDP per capita by digging more coal, pumping more natural gas, planting more palm oil trees and cutting more forest. There is a limit to it.
In the short term the government should make the commodity industry more fair, transparent and accountable through proper regulation and law enforcement. Reducing red tape in the mining industry and improving security in commodities-producing areas are two very crucial actions the government should take. It could improve industry efficiency and corporate income, increase government tax revenues and create employment for the general public.
In addition, promoting policy certainty is also a priority. The decrease in commodity exports is in part also attributable to the difficulties faced by commodity producers in making a business plan due to policy uncertainty. The proposed high export tax for coal, CPO and other commodities, which have finally been cancelled, was one of several examples of improper pro-cyclical policy.
The regulation that obliges mining companies such as gold, copper, aluminum, nickel and tin producers to build smelter facilities in Indonesia before 2014 is one illustration of unrealistic policies. In addition to the huge investment needed and the short time-frame, it is also unmanageable due to the lack of electricity. Making policy is cheap, especially low-quality ones; the cost of wrong policy is massive.
Nothing is new about the above ideas. They have been discussed for years or even decades. However, we hope the global trend will make us realize the importance of sound public policy, and more importantly, the consistency to implement policies accordingly. Improving exports is not an easy task and is beyond the responsibility of one or two ministries. It takes a collective effort by all stakeholders in the industry.
Wijayanto is the vice rector of Paramadina University, and is the co-Founder and managing director of Paramadina Public Policy Institute. He can be reached at firstname.lastname@example.com


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Seattle's Big Blog
Covering Seattle news, weather, arts and conversation.
Monthly Archive for July, 2008
Updated: Toronto to follow Seattle's toilet lead
Canada's CBC today reported that the city of Toronto is going ahead with plans to install self-cleaning toilets throughout the city, despite the mess they've left us here. [Read More]
A lot of you want Ichiro traded after all
Last week P-I sports columnist Jim Moore suggested the Mariners could turn things around by trading away their most famous player. The one everyone roots for. The one that gave that profanity-laden pep talk last week. The one featured on the Seattle billboard that reads, "Future Hall of Famers – raise your right bat" (or something like that). [Read More]
How the Obamas fell for Seattle's Fran's Chocolates
It was first revealed in a New York Times article in May: Barack Obama loves Seattle-based Fran's Chocolates. [Read More]
How our photog got that awesome moon pic
Visitors to the Space Needle enjoy a nearly full moon as it rises over Seattle Thursday. (Grant Haller/Seattle P-I) "I find the surprise of looking up in the sky and seeing a full moon a delight," wrote P-I photographer Grant Haller in response to an e-mail I sent him about the stunning photo of the Space Needle and the moon that graced our local cover today. [Read More]
Seattle father ran with the bulls and lived
Last Tuesday, Patrick Boatsman lived the most intense one and a half minutes of his life. [Read More]
Show More


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Picky Eaters
Saturday, November 27th, 2010
From the beginning of her bottle life, Fia took it like a champ. So much so, that even after she turned one, I was apparently feeding her too much formula. Truth is, the bottle became my crutch. If she didn't eat enough real food I'd get nervous that she would be hungry, so I'd give her one. It was quite enlightening when I recently took her to the pediatrician for her one-year appointment.
Here's how the conversation with Dr. TJ Gold began:
"How's her appetite?"
"Well, I'm still giving her about 32 ounces a day of formula. Real food is kinda hit or miss."
A stern stare. I continue.
"She gets picky at the table and I worry that she's not eating enough, so I fill her up however I can."
Dr. Gold nods knowingly, as if saying, yeah, I've seen this before.
"And do you also run around while she plays trying to put food in her mouth?" she asks.
"YES!" I exclaim, thinking she "gets" it. She understands how picky babies are. I continue: "I run around the exersaucer chucking cheese into her mouth. I run after her through the living room, shoving saltines in. Anything I can get her to eat and any way I can do it." I beam, waiting for the sign of approval.
Dr. Gold clears her throat and she says something to me that was a game changer for me.
"Terrible Two's happen because of parenting choices made during the 1's."
She continues, "And it's much harder to reverse bad behavior than to just begin with good behavior."
Look, I feel like I'm a fairly reasonable, somewhat smart and aware person. And I've read the range of babybooks—from Dr. Sears to Babywise. But in this scenario, for whatever reason, my mom instincts were off. I'm sure it stems from my primal need for sleep and my irrational fear that she'll start waking up in the night hungry if she doesn't get enough during the day. Whatever the cause, I'm so so so glad Dr. Gold stopped me cold in my tracks and reversed my behavior. It immediately made a difference, and continues to nearly a month later. Here is a recap of what I learned:
You feed your baby broccoli one day, the next day she flicks it off her tray and refuses to eat it. You try pasta, which you know she likes. And oops, there goes the flick again. She isn't interested in any of the usual staples. Desperate, you scour your fridge. Yogurt and applesauce. The sweet stuff. You pull it out, try it on her, and voilà, she eats it. Guess what? You've just been had and your baby just won a major battle. Continue like this, and soon she's the master. And you're the servant, scrambling to find food she'll eat.
"Picky eaters are formed by this exact scenario," Dr. Gold tells me. They know if they flick food off, eventually mom will come running to their rescue with something sweet.
Then she gave me a very healthy warning. "This is also how you end up with a 2-year old who can't sit still at a restaurant. And it's how you start to lose your edge as a parent. "
"But, what do I do?" I say, wringing my hands. "If she won't eat, then she'll wake up in the night, and next thing you know, I'm dealing with a newborn schedule again!!"
Not true, says Dr. Gold. Mealtime is very specific. You put her in the highchair, TV off, time to focus and you feed her. If she flicks her food, you stop feeding. Take her down. Wait 30 minutes. Try again. She's not going to starve. When she's hungry enough, she'll eat.
She also told me to switch to whole milk and cut down to 16 ounces a day max.
At the visit, Fia was in the 10th percentile for weight, 48th for height. While Dr. Gold wasn't a bit worried, I swear Fi fattened up within 3 days following her instructions. It was a remarkable shift. And now, she literally eats everything. And lots of it. When she sees me setting her food out, she toddles up to her highchair and throws her arms in the air, begging to go in it. A far cry from me running around in circles, chasing her while shoveling bits of food in her mouth.
Every baby is different, so this might not work for you, but I just thought I'd share my own experience. My new and improved routine goes like this:
7am – She wakes up. I give her a 6 oz bottle of whole milk.
8:30-9am – Breakfast. Yogurt, toast with peanut butter, banana, etc. Sippy cup with water and a splash of OJ.
11am – Lunch. Chickpeas, rice, chicken, mac and cheese….whatever I'm eating. I just cut it up in small pieces.
1-2pm – Small bottle. Snack.
5-6pm – Dinner. Again, whatever we're going to eat.
6:30pm – Bath time.
7pm – Book and 6 oz bottle. Baby sleeps through night.Add a Comment
Tags: advice, appetite, baby, baby bottle, baby food, baby formula, bottle, eat, eating, flinging food, food, formula, hungry, hungry baby, milk, picky, picky eaters, poor appetite, terrible two's | Categories: Fearless Feisty Mama, Mom Tricks and Tips


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Breeding Cane Corsos is purely a hobby for us and is not something that we rely on as a source of income so we will only breed a litter of pups on occasion.
We aim to breed excellent quality dogs from superior bloodlines that show generations of excellent health, temperament and type.
Our breeding programme is structured with the intention of improving the breed. Our goals are to produce healthy dogs with great movement and type that could do a days work if the need and circumstances arose. We aim to produce dogs that we can be proud of and we will always aim to breed to the correct standard set forth by the country of origin.
ALL of our own breeding dogs are hip AND elbow scored under the UK BVA scheme or European equivalent.
Our puppies are born in our home and are handled regularly from day one to ensure they are used to people and all household noises. At four weeks old, the puppies spend time each day outside in the puppy pen or in the field where they can run and play with each other and see the other animals that live around us including our other Corsos, our Jack Russell our horses and the cows and sheep that live in the field opposite. Our puppies are very well socialised when they leave us with adults, children and other dogs and we like all of our new owners to continue this socialisation so the puppys grow to be confident, outgoing and friendly with people and other animals.
Before leaving us we have each and every puppy vet checked, microchipped, 1st vaccination, and insured. All of our puppies are regularly wormed from 2 weeks of age. All puppies leave here with a comprehensive puppy pack and a lifetime of breeder support.
We do not promise anyone pick of the litter as we breed first and foremost for ourselves and always retain one or two pups for use within our own breeding programme.
All puppies are placed according to temperament and character of the pup itself and the owners experience.
We do like to keep in contact with all of our puppy owners and greatly appreciate the odd call/email update and pictures.
Anyone wishing to purchase a puppy from us will be fully vetted. This will involve an initial telephone chat and then if both parties are happy following this call I will invite you down to meet myself and the dogs which gives you and your family an opportunity to interact with the dogs and decide if the Cane Corso really is the right breed for you and for me to decide if you are the right owner for a Cane Corso. We will never sell a puppy until we have met the new owners and spoken to them at great length about the breed and also seen how they interact with our own adult dogs.