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The data comprises 8-bit words, plus a leading bit as a start bit at a logic one, and a trailing bit for parity, for a total of 10 bits per group. A synchronizing circuit in the receiver selects a proper phase of clock signals for shifting the data bits into a shift register. An enable flip-flop for the synchronizing circuit is set in response to the start bit at the receiver input, and is reset when the start bit appears in the last bit position of the shift register.
In a preferred embodiment, a clock signal is divided into three phases by a delay line. The synchronizing circuit has three flip-flops for selecting the phase when the enable flip-flop becomes set. These flip-flops enable gates for supplying the selected phase to the shift register. Delays are provided from the transmission line to the shift register and enable flip-flop inputs, so that the sampling is centered over each data bit.
1. A data receiver for receiving data from a data line, said data being in asynchronous bit serial form at a predetermined bit frequency in groups of N bits, the leading bit of each group being a start bit of one logic state; said data receiver comprising an N-stage shift register operative to clock data in from said data line under the control of said leading bit and synchronizing means, both said register and said synchronizing means being coupled to said data line, and with a clock connection from said synchronizing means to said shift register; means responsive to said leading bit to start said synchronizing means in order to select a phase relation to supply a train of clock pulses to said shift register at said given bit frequency via said clock connection in order to shift one of said groups from said data line into said shift register in accordance with the phase relation selected.
2. A data receiver as set forth in claim 1, further including means responsive to said one logic state indicating said leading bit in the Nth stage of said shift register to stop said synchronizing means.
3. A data receiver as set forth in claim 1, further including delay means, clock input means connected to supply clock signals at said predetermined frequency to said delay means, a given number of clock conductors from said clock input means and said delay means connected to supply clock signals on said clock conductors at different phases at said predetermined frequency.
4. A data receiver as set forth in claim 3, wherein said synchronizing means comprises phase select bistable devices with input connections from said data line and said clock conductors to trigger and selectively set said phase select bistable devices in response to said start bit in accordance with the clock signals then on said clock conductors, and gate means selectively enabled by output connections from said phase select bistable devices to connect one of said clock conductors to said clock connections.
5. A data receiver as set forth in claim 4, wherein there are three of said clock conductors for clock signals of three phases, and there are three of said phase select bistable devices.
6. A data receiver as set forth in claim 5, wherein there are four of said clock conductors for clock signals of four phases, and there are two of said phase select bistable devices which may be set in four different combinations for selection respectively from among said four phases.
7. A data receiver for receiving data from a data line, said date comprising groups of N bits in asynchronous bitserial binary form at a predetermined frequency, the leading bit of each group being a start bit which is a logic one, there being a guard interval between groups;
said data receiver comprising a shift register, synchronizing means, enable means and reset means;
said shift register comprising N bit positions, a data input coupled to said data line, a clock connection from said synchronizing means for clock pulses to shift said data received at said data input from the first to the Nth of said bit positions;
said enable means comprising a bistable device having a set input coupled to said data lead and an enable connection to said synchronizing means, operative in response to said leading bit at said input to set said enable means and in response thereto to supply an enable signal via said enable connection;
said synchronizing means comprising means operative in response to an enable signal on said enable connection to supply a train of clock pulses via said clock connection, including phase control means to synchronize said train of clock pulses to be in phase with said data for each group;
said reset means comprising means to reset said enable means and thereby terminate said train of clock pulses on said clock connection.
8. A data receiver as set forth in claim 7, wherein said reset means includes a reset connection from said Nth bit position to said enable means, operative in response to a logic one indicating said leading bit in said Nth bit position to supply a reset signal on said reset connection to reset said enable means.
9. A data receiver as set forth in claim 7, wherein said phase control means comprises phase select bistable devices with input connections from said data line on said clock conductors to trigger and selectively set said phase select bistable devices in response to said leading bit in accordance with the clock signals then on said clock conductors, and gate means selectively enabled by output connections from said phase select bistable devices to connect one of said clock conductors to said clock connection.
10. A data receiver as set forth in claim 9, further including delay means, clock input means connected to supply clock signals at said predetermined frequency to said delay means, a given number of clock conductors from said clock input means and said delay means connected to supply clock means on said clock conductors at different phases at said predetermined frequency.
11. A data receiver as set forth in claim 10, wherein there are four of said clock conductors for clock signals of four phases, and there are two of said phase select bistable devices which may be set in four different combinations for selection respectively from among said four phases.
12. A data receiver as set forth in claim 10, wherein there are three of said clock conductors for clock signals of three phases, and there are three of said phase select bistable devices, with said clock conductors connected respectively to individual ones of said phase select bistable devices, so that with 50% duty cycle of said clock signals, in response to said start bit one or two of said phase select bistable devices become set, and of the resulting six combinations for setting said phase select bistable devices, two are assigned for selection of each of said clock conductors via said gate means.
13. A data receiver as set forth in claim 12, wherein the two combinations of all of said phase select bistable devices being in the same state, which should not normally occur when said synchronization circuit is enabled, are also each assigned for selection of one of said clock conductors via said gate means.
14. A data receiver as set forth in claim 12, further including input delay means connected from said data line to said data input of said shift register for one delay time, and also to said set input of said enable means for another delay time, so that the clock pulses on said clock connection to said shift register are aligned with said bits of said data for proper shifting into said shift register.
15. A data receiver as set forth in claim 14, wherein said reset means includes a reset connection from said Nth bit position to said enable means, operative in response to a logic one indicating said leading bit in said Nth bit position to supply a reset signal on reset connection to reset said enable means, said reset connection also being connected to reset said phase select bistable devices.
16. A data receiver as set forth in claim 7, further including input delay means connected from said data line to said data input of said shift register to provide a delay time for said data, so that the clock pulses on said clock connection to said shift register are aligned with said bits of said data for proper shifting into said shift register.
17. A data receiver as set forth in claim 16, wherein said input delay means also is connected to provide a delay from said input data line to said set input of said enable means.
18. A data receiver as set forth in claim 7, wherein said synchronization circuit comprises a three-bit shift register, means to parallel load said three-bit shift register with a fixed pattern having one bit of one state and two bits of the other state, clock input means connected to supply clock signals at three times said predetermined frequency to a clock input of said three-bit shift register, means responsive to said enable signal via said enable connection to rotate said fixed pattern in said three-bit shift register using said clock signals, so that said bit of one state appears in a given position of said three-bit shift register at said predetermined frequency, said clock connection being from said given position to the first shift register.
This invention relates to a receiver for data which is transmitted in asynchronous bit-serial groups.
Data transmission systems have become commonplace, both for transmission between units in locations remote from one another and for transmission between local units in a system. Frequently the data is organized into words of a given number of bits (binary digits) each. The data may be transmitted a word at a time in parallel form, or the bits of each word may be sent serially. The parallel format requires multiple transmission leads and associated apparatus in the senders and receivers. Therefore the bit-serial format is usually considerably less expensive, but there are added engineering complexities.
The transfer of data in serial form through a single communications channel is generally accomplished by using one of two transmission techniques: synchronous or asynchronous transmission. Synchronous data transmission requires that a clock signal (sync word) be transmitted with the data in order to mark the location of the data bits for the receiver. In some systems, the clock signal is sent on a separate lead. There are also systems in which the clock signal is derived from the received data. With asynchronous transmission, a clock signal is not transmitted with the data and the words (characters) need not be contiguous. In order for the receiver to properly recover a message, start and stop elements are added to each data word. The start-stop principle of word synchronization is used in telegraphy and with teletypewriters.
One example of apparatus with data transmission is a digital switching network, such as may be used in a telephone system with pulse code modulation. In one type of arrangement known as a time-space-time network time slot interchangers at the input and output sides use buffer memories to receive data words in various time slots of each frame, and output the words in other time slots. The incoming time slot interchangers receive data words from incoming terminals and supply them to incoming superhighways, and the outgoing time slot interchangers receive data words from outgoing superhighways and output them to outgoing terminals. A space switching stage between the input and output superhighways actuates crosspoint gates in selected time slots to transmit data from an incoming superhighway to an outgoing superhighway.
The transfer of information from an incoming superhighway to an outgoing superhighway requires a finite amount of time due to transmission and switching delays in the network. The uncertainties in the time delays, known as delay variations, cause serious problems in the timing of the digital switching networks. The delay variations in the switching paths of a digital matrix are largely determined by the size of the network, its layout, and the switching device (such as integrated circuits) technology used. To overcome the effects of the delay and timing uncertainties of a network, a "guardspace" of several bits in the transmission rate must be allowed.
Because of the time delay uncertainties and a high speed transmission rate, the data is received asynchronously. Available data receivers are relatively slow.
An object of this invention is to provide a simple and effective asynchronous bit-serial data receiver capable of operation at a range of speeds; in particular a receiver which may be operated at a very high speed bit rate. The data is in groups of a predetermined number of serial bits at a given bit frequency. The leading bit of each group is a start bit at a logic one state. The receiver includes a shift register with the predetermined number of stages.
According to the invention, the data receiver includes synchronizing apparatus started in response to the start bit of a group to supply clock pulses at the given bit frequency for shifting the data into the shift register, with the phase of the clock pulses selected to sample each bit properly in spite of small variations in the edges of the data bits and clock pulses.
A feature is that the leading bit of each group is used not only as a start bit, but also as a stop bit to stop clock pulses from the synchronizing apparatus when this bit appears in the last stage of the shift register. An enable flip-flop is set by the start bit appearing at the receiver input, and is reset via a connection from the last bit position when it contains a logic one.
In some embodiments of the invention, a clock signal at the given frequency is supplied from a master clock to the synchronizing apparatus, which includes means such as a delay line to split the clock signal into phases. A set of flip-flops is arranged to select one phase when the enable flip-flop is set, and these flip-flops control gates to supply the selected phase to the shift register. In a specific preferred embodiment the clock signal is split into three phases, and three flip-flops are used for phase selection.
In order that the sampling interval may be centered over each data bit to overcome delay uncertainties in the synchronization circuit for higher speed operation, a first delay is provided between the transmission line and the data input of the shift register, and a second delay is provided between the transmission line and the enable input.
An advantage of the data receiver according to the invention is that it is capable of operating at a higher speed than available units. This receiver is also simpler in that the receiving shift register also acts as the word counter for the receiver.
Other objects and features, and the advantages thereof, appear in the following description.
FIG. 1 is a functional block diagram of the preferred embodiment of a data receiver;
FIG. 2 is a block diagram of the receiver;
FIG. 3 is a timing diagram of the receiver of FIG. 1;
FIG. 4 is a functional block diagram of another embodiment for the block diagram of FIG. 2, and FIG. 5 is a timing diagram thereof;
FIGS. 6 and 8 are functional block diagrams of other embodiments of the receiver, and FIGS. 7 and 9 are respective timing diagrams thereof.
FIG. 10 is a block diagram of a telephone switching system;
FIG. 11 is a block diagram showing the organization of one switching group of the system of FIG. 10, adding a control access circuit; and
FIG. 12 is a diagram for showing data transfer via a path through the switching network of FIG. 10.
A functional diagram of an asynchronous bit-serial receiver employing a three phase clock is shown in FIG. 1. A generalized block diagram employing a polyphase clock is shown in FIG. 2. The receiver basically comprises a shift register SR, and a synchronizing circuit SC. At the arrival of a data word, the synchronizing circuit measures and selects the appropriate clock phase of a polyphase clock for securing the data in the shift register.
With asynchronous transmission, the clock signal is not transmitted with the data and the words (characters) need not be contiguous. In order for the receiver to properly recover a message, the words are of uniform length, and start and stop elements are added to each word. Specifically in this system, each data word comprises ten bits. The leading bit is a logic one used as both a start and a stop bit, the next eight bits are the message word proper, and the last bit is a parity bit. These data words are received over the transmission line designated D in FIG. 1 and 20 in FIG. 2. With this system, the received word could be shorter than the register capacity, in which case the remaining bits would be zeros.
It should be noted that, in order to assure proper recovery of the data when the phase of the receiver clock is unknown at the arrival of the data, the data, particularly high speed data, must be sampled at three or more times the data rate, or be sampled with one phase of a clock having three or more phases. If the data, particularly high speed data, were sampled at the data rate with a clock of unknown phase multiple sampling of some data bits and no sampling of other data bits in a group might result. This problem is particularly crucial at high data rates where the variation in propagation delay through the circuits, and the inequality between rise and fall times in the hardware (such as TTL circuits) is particularly severe. For example at 30.72 megahertz, the delay variation in the sync circuit of the clock is in the order of the bit period (30 nanoseconds. Thus a clock of three or more phases is needed to recover this data. A three phase clock yields sampling margins of T/3 where T is the duration of a data bit. A two-phase clock still would provide no finite sampling margins at very high data speeds.
In the preferred example, the clock signal at a frequency Fc is shown received on lead C in FIG. 1 and lead 23 in FIG. 2. As shown in FIG. 2, a delay line or set of delay lines 24 divides the clock signal into N phases on leads C1-CN. The signal on each of these leads is then at the same frequency Fc, but at a different phase. The leads C1-CN are supplied to the synchronization circuit SC. When a data word is received via line 20, the leading edge of the start bit via path 22 is used to enable the synchronization circuit. A delay may be included in the enabling circuit input. The synchronization circuit then selects one of the clock signal phases from one of the leads C1-CN and gates it via lead 25 to the clock input of the shift register SR.
The data from line 20 via path 21, with a delay if needed, is supplied to the shift register SR and shifted in by the clock pulses from lead 25. When the start bit reaches the tenth position, the output on path 26 may be used in the synchronization circuit SR to stop the train of clock pulses on lead 25.
In the receiver of FIG. 1, a delay line 11 drives a three-phase clock from the input clock signal on lead C. The frequency Fc may by way of example be 30.72 Megahertz. Each clock cycle then has a duration of 32.55 nanoseconds, with a 50% duty cycle. The delay line 11 provides a total delay Δ3 equal to 22 nanoseconds, and is tapped at point Δ3/2 for 11 nanoseconds. One phase is the undelayed input signal from lead C to leads C1, a second is from the tap to leads C2 and a third is from the end of delay line 11 to leads C3. The waveforms are shown on FIG. 3 at the top.
The synchronization circuit comprises phase-selection flip-flops M1, M2, M3, an enable flip-flop M4, a data selector DS, and gates 12-15. The flip-flops may be JK type 74S112, the data selector DS may be type 74S151, and the shift register SR may be type 74S194, all available from Texas Instruments, Incorporated.
The clock phase leads C1, C2, C3 are connected to the J inputs of flip-flops M1, M2, M3 respectively. The K inputs of these three flip-flops are at logic zero.
As the arrival time of the data is uncertain, the synchronization circuit is needed to select the clock phase appropriate for securing the data in the shift register. At the arrival of the start bit of the data word, the states of the three clock phases C1, C2, C3 are measured by flip-flops M1, M2, M3 respectively and determine the clock phase to be selected by the data selector DS. The clock input for flip-flops M1, M2, M3 is supplied via NAND gate 14 and lead 34. A negative going transition of the signal at the CK inputs clocks in signals at the J and K inputs. Normally between data words received the synchronization circuit is reset with all of the flip-flops having a logic zero at the Q outputs and a logic one at the Q outputs. (With slower D type flip-flops the reset is not needed) Gate 14 normally has a logic one at its input port from lead Q4 from flip-flop M4, and a logic zero at its input port from the date line D, so that its output is a logic one or high. The arrival of the start bit changes the lower input port of gate 14 to a logic one, so that the output on lead 34 goes to logic zero or low. This negative going transition clocks the flip-flops M1, M2, M3 so that those having logic one signals at the J inputs become set. This effectively measures the states of the clock phases. For examaple, if the data arrives as shown at graph D in FIG. 3, flip-flop M1 is set, while flip-flops M2 and M3 remain reset. The output from flip-flop M1 at lead Q1 is shown in FIG. 3, graph Q1.
The data sampling interval is centered over each data bit by providing a delay Δ1 for the data and a delay Δ2 for the clock-enable. These delays are obtained from a delay line 10, with Δ2 from a tap and Δ1 at the end. This helps to overcome the problem of proper sampling at the 30.72 megahertz frequency, with the delay uncertainties in the synchronization circuit. (At lower frequencies no delay lines are needed).
The signal from tap Δ2 of delay line 10 via path 30 is used to set the enable flip-flop M4. To prevent noise spikes of less than 12 nanoseconds duration (other widths could be chosen) from triggering the receiver, a glitch filter has been added. It consists of the delay Δ2 and the additional gate 12. When a start bit of proper duration arrives at the tap Δ2, the upper input ports of gates 12 and 13 are at logic one. The lower input port of gate 12 is also at logic one from the data line D, so that the lower input port of gate 13 is also a logic one. This produces a negative going transition at the output of gate 13 to set flip-flop M4. Note that the J and K inputs are fixed at logic one and zero respectively. The signal on lead Q4 inhibits gate 14 to terminate the clock signal on path 34. The signal from flip-flop M4 on lead Q4 enables the data selector Ds.
In the data selector DS, the input ports A, B, C, with weights 1, 2, 4 respectively, are used to select one of the eight signal ports D0-D7. With a logic zero at port S, the signal at the selected one of the ports D0-D7 is gated to output port Y. The selected signal is one of the clock phases C1, C2 or C3. With the example shown in FIG. 3, the port D1 for clock phase C1 is selected, as shown by graph Y.
The shift register SR has the data input via path D1 from delay line 10 connected to the shift right input port R. The shift register has other ports, not shown, which should have fixed termination potentials as required for shift right operation. The clock signals from port Y of the data selector DS via path 37 are supplied to port CLOCK. The delayed input data is shown by graph D1 in FIG. 3. The data is entered and shifted on the rising edge of the clock pulses.
As the start bit, always a logic one, is shifted into the tenth bit position (overflow position) of the shift register, the signal from putput port 101, inverted via NAND gate 15 and path 35 resets the enable flip-flop M4, and also the flip-flops M1, M2, M3. With the flip-flop M4 reset, the signal on lead Q4 becomes logic one to inhibit the data selector DS via port S, to thereby stop the clock pulses to the shift register SR. As long as the output port 10' is at logic one, path 35 is held at logic zero which prevents setting flip-flop M4 or any of the other flip-flops.
After the data from the shift register SR is taken via output ports 1-9 and placed in the holding register HR, a clear signal at a logic one is supplied via path SRC to clear the shift register SR, resetting all positions to logic zero. The enable flip-flop M4 is no longer held in the clear state, and the receiver is ready to receive a new data word.
As optimization of the sampling margins for the data is the ultimate goal in the design of an asynchronous bitserial receiver, the proper assignment of the clock phases to the clock states is paramount to the operation of the receiver. The optimum assignment depends on the delays Δ1 and Δ2 and the integrated circuit components used. As stated above, the components comprise 74S112 flip-flops, a 74S151 data selector and a shift register with type 74S194 units. There are various possible combinations for the delay times and flip-flop states for clock phase assignment. The delay times chosen are Δ1 = 16 nanoseconds, Δ2 = 12 nanoseconds, Δ3 = 22 nanoseconds, each with a tolerance of plus or minus 1.2 nanoseconds. The clock assignment is shown in Table 1.
TABLE 1______________________________________Clock Assignment M1 M2 M3 Decoded Selected Clock______________________________________1 0 1 D5 C11 0 0 D1 C11 1 0 D3 C20 1 0 D2 C20 1 1 D6 C30 0 1 D4 C30 0 0 D0 C1*1 1 1 D7 C3*______________________________________
Theoretically, the three-phase clock can assume one of the six states D1-D6. The states 000 (D0), and 111 (D7) are excluded. However, due to component tolerances, there exists a remote chance that the synchronization circuit may be trapped in one of those two states. To eliminate this problem, the clock phases are assigned to these two states as indicated by * in Table 1.
In FIG. 4 there is shown a receiver circuit similar to that of FIG. 1, except that the clock is divided into four phases, with a simpler circuit. A four-phase clock is equivalent to a system of two primary clocks in quadrature, each primary clock also having a complementary output. The input clock signal on path C' may be considered a first clock signal, and via inverter 401 the complement appears at path 402. With the 30.72 megahertz frequency Fc for the input clock signal, the duration of a data bit is a little over 32 namoseconds. A delay line 42 with a delay Δ3 of 8 nanoseconds has its input from path C', and from its output provides a second clock signal at path 52. Its complement via inverter 403 appears at path 404.
The receiver comprises a 10-bit shift register 400 and a synchronization circuit. The synchronization circuit comprises two flip-flops A1, A2 to measure the states of the clocks and an enable flip-flop A3 to start and to stop the clock to the shift register. The decoded clock states determine the selected clock phase to secure the data in the shift register. A delay line 40 provides a delay Δ1 from the input data line D' to the shift register input via path 51. A delay line 41 provides a delay Δ2 between the data line D' and path 50 for triggering the flip-flop A3. The delay Δ2 is required to prevent repeated sampling of the start bit, due to delay variations in the circuit. Typical operation is illustrated by a timing diagram in FIG. 5. At the arrival of a start bit (lead bit) of a data word, the flip-flops A1, A2 measure the states of the clock C and delayed clock Cd. The J inputs are connected to the clock signal path C' and the delayed clock signal on path 52 respectively. A negative going trigger is supplied to the clock inputs from lead D' inverted via gate 44 to path 54. The enable flip-flop A3 is set by the signal on path D', delayed in delay line 41 and inverted by gate 43. The output on path QA3 becomes a logic zero to inhibit gate 44 and end the trigger pulse. The output on path QA3 is now a logic one to enable gates 411-414.
The measured clock states are decoded at gates 411-414 to select one of the four clock phases C, C, Cd and Cd. FIG. 5 shows phase Cd selected. Therefore the clock signal on path 404 is gated via gates 414 and 415 to path 57 for supplying clock pulses to the shift register 400. The data to the shift register is delayed by Δ1 nanoseconds to ensure proper sampling of each data bit.
As the lead bit, always a logic one, is shifted into the tenth bit position (overflow position) of the shift register, the enable flip-flop A3 is reset via inverter 45 and path 55. This inhibits gates 411-414 to stop the clock signals to the shift register. The start bit also serves as a stop bit after the data is secured in the shift register 400.
After the data out is taken, the system supplies a clear signal on lead SRC to clear the shift register 400 and flip-flops A1 and A2. The enable flip-flop is no longer held in its reset state, and the receiver is ready to receive a new data word.
The assignment of the clock phases to the states of the clock signals measured at the arrival of a data character is not unique. The assignment depends upon the time delays in the circuit and the delays Δ1 and Δ2. Two possible assignments are shown in Table 3.
TABLE 3______________________________________(a) Delays: Δ1 = 16ns, Δ2 = 10ns, Δ3 32 8ns (10-13ns)Measured Clock States Assigned Clock PhaseA1 A21 0 Cd1 1 C0 1 Cd0 0(b) Delays: Δ1 = 20ns, Δ2 = 10ns, Δ3 =8ns (not critical)Measured Clock States Assigned Clock Phase1 0 C1 1 Cd0 1 C0 0 Cd______________________________________ Clock Phase Assignment as a Function of Delays Δ1 and Δ2, and Measured Clock States at the Arrival of the Data Character.
The timing diagram for the receiver, assuming the clock assignment (a) of Table 3 is shown in FIG. 5. Safety margins of T/4 nanoseconds in the sampling of the data bits are achieved, where T is the duration of a data bit.
The components for this receiver may be three 74S194 units for the shift register 400, type 74S112 flip-flops, one type 74S00 chip for 2-input gates, three 74S20 chips for 4-input gates (or a selector type 74S151) and three delay lines.
The receiver shown in FIG. 6 also comprises a 10-bit shift register 600 and a synchronization circuit. The synchronization circuit basically comprises a D flip-flop 69 and a 3-bit shift register 63. The 3-bit shift register 63 makes use of two modes of operation, right shift and parallel load. In the parallel load mode, a fixed 100 is loaded as indicated in FIG. 6. In the shift mode the contents are circulated to the right with each pulse of the input clock signal on path 64, which is at a frequency three times Fc. The clock pulses to the 10-bit shift register 600 are taken from the center output QB of the 3-bit shift register 63 via path 65, which occur at the frequency Fc.
The data words, as before, comprise ten bits, with the leading bit being a start bit which is always a logic one.
The timing diagram is shown in FIG. 7.
As to the operation, the start bit sets flip-flop 69 (if the signal at the reset port R is a logic one). The output of flip-flop 69 via lead 67 enables the right shift (circulate) of the 3-bit shift register 63. Note that lead 67 is connected to record the output (QB) of the circulating shift register 63. This results in a delay of one clock period of the 3Fc clock or 1/3of the data bit duration needed to center the data. Shift register 63 is clocked by pulses from path 64 at the frequency 3 Fc. Its output in turn via lead 65 clocks the 10-bit shift register 600 receiving the information word.
With the arrival of the last information bit, the 10-bit shift register 600 overflows with start bit into the tenth position. The tenth bit resets flip-flop 69 via path 66, and in turn it inhibits the 3-bit shift register via path 67, placing it in the parallel load mode. The clock signals to the 10-bit shift register 600 are thus removed.
After reading the contents of the shift register 600, it is cleared via a signal on lead 68.
In this receiver delay lines could be inserted from the data input line 61, to the 10-bit shift register 600 shift right input, and also to the clock input of the flip-flop 69.
A receiver employing a gated, free-running oscillator is shown in FIG. 8. This receiver essentially consists of a ten-bit shift register 800 for data reception and storage and a gated square wave oscillator. The square wave oscillator consists of a single inverting gate 84 and a 32.55 ns delay loop (equal to the period of the 30.72 MHz clock). The delay loop is implemented by means of a fixed delay line 86 of 24 ns and a variable delay. The latter is realized by an RC timeconstant. At the arrival of the start bit of a data word, the oscillator is enabled generating the 30.72 MHz clock to the shift register. The capacitor 88 in the loop is variable for adjusting the loop delay. This capacitor 88 is charged through the collector resistor of the inverting gate 84 (pull-up transistor) and discharged through the saturation resistance of the inverting gate 84 (pull-down transistor). The actual clock waveform is derived by exclusive-oring the tap-output of the delay line with its undelayed input as illustrated in FIG. 9. Thus the signal on lead F1 is from the input to the delay line, and the signal on lead F2 is from the tap Δ/2. These are combined via exclusive OR gate 89 with output via lead F to the clock input of the shift register 800.
The enabling of the synchronization circuit is accomplished by setting flip-flop 82 at the leading edge of the start bit via an inverter 80. The flip-flop output to path 83 enables gate 84.
When the start bit reaches the tenth bit position of shift register 800, the signal on path 90 via NOR gate 91 resets the flip-flop 82.
After the data is read out of the shift register 800, a signal on lead SRC is used to clear it for the next data word.
While this receiver has a very simple circuit, the oscillator being free-running, it must be very stable; that is, all component values must be controlled tightly, the supply voltage must be stabilized, the circuit must be temperature compensated, and care must be taken in tuning the delay loop to the frequency of operation. Therefore the maximum frequency for dependable operation is much lower than that of the receiver of FIG. 1.
FIG. 10 illustrates a digital communication switching system, more particularly a pulse code modulation time division multiplexed telephone system, including the preferred embodiment of the invention. A digital switching matrix is a time-space-time (TST) connecting network. The first and last digits are realized by full-availability time slot interchangers (TSI). The center stage is a time-division space stage. The square array of cross points is partitioned into vertical columns of N X I cross points, N being the number of superhighways of the network. The matrix is divided into switch groups on a superhighway basis, with each switch group having its own controller. For example, switch group A comprises an input time slot interchanger comprising an input buffer memory IBM-A connnected to superhighway IHW-A and a control memory ICM-A; an output time slot interchanger comprising an output buffer memory OBM-A, and a control memory OCM-A. Switch group A also includes the vertical column of cross points AA, BA to NA inclusive with inputs from the superhighways of the several switch groups, and an output to the output buffer memory OBM-A. The switch group A has its own individual controller CTR-A. The crosspoints have an associated control memory XCM-A, and a crosspoint decoder CD-A. The decoder CD-A enables the crosspoints in selected time slots via the lines 30AA, 30BA to 30NA inclusive. Similarly switch group B comprises an input time slot interchanger with memories IBM-B and ICM-B, a vertical column of cross points AB, BB to NB inclusive, and an output time slot interchanger comprising memories OBM-B and OCM-B, along with its controller CTR-B, a crosspoint control memory XCM-B and a crosspoint decoder CD-B. The other switch groups are similarly organized up to the including switch group N. Each switch group also includes address counters (not shown) for the input and output time slot interchangers.
Each switching group has a multiplexer shown as 10A for Group A, and 10B to 10N for the other groups. It might, for example, combine the channels from ten T1 lines T1-1 to T1-10, each of these T1 lines having an incoming pair and an outgoing pair as shown. Each of the T1 lines multiplexes twenty-four channels, making a total of 240 channels served by a switch group.
The T1 lines may connect to various equipment such as remote line switches LS-A to LS-N, to trunks such as trunk group TGB, and to the central processor PRO, as well as other devices in the central office.
The may, switches are shown as having T1 lines connected to the multiplexer of the same group. The line switches are shown as single units, but each line switch may in fact, comprise a group of units with the T1 lines extending through them in a series loop, each unit serving a group of subscriber lines. Line switch LS-A is shown as connected to subscriber lines A1, A2, and so forth up to line AM. Both calling and called lines of a line switch are assigned to channels of the T1 lines for the duration of a call.
As described above with reference to FIG. 10, a digital switching matrix is organized in digital switch groups. Each switch group is assigned its own controller CTR. A digital switch group may for example consist of 32 switch groups. The work of the 32 controllers is coordinated by the processor PRO (not shown). Network timing is derived from the system clock (not shown) and data transfer clock (not shown).
The system clock is a stable clock and operates at 2.048 MHZ. It controls all path switching operations, that is, it controls the read/write operations of all time slot interchanger (TSI) memories and the crosspoint control memories XCM-A to XCM-N.
The transfer clock may operate at 30.72 MHZ or a higher frequency. It controls the bit-serial transfer of data (speech) from an incoming time slot interchanger via a crosspoint to an outgoing time slot interchanger.
The digital switching matrix may be viewed as having two modes of operations; a synchronous mode of operation, also called Network Control Mode, and an asychronous mode of operation, referred to as Call Process Mode.
In the Network Control Mode, the Call path switching operations and the bit-serial data transfer are performed. In the Call Process Mode, the call processing functions such as device selection, digit reception and outpulsing, idle path selection, loading of all path control memories and marker functions are executed. In this mode of operation, the switching group controllers have access to the path control memories via the control access circuit CAC (FIG. 11).
The operation and control of the digital switching matrix is best explained and understood by examining the organization of a single switch group, as shown in FIG. 11 for Group A.
In the Call Process Mode, the switch-group controller CTR-A has access to the control memories of the switch group via the control access circuit CAC simply by addressing the control access circuit as illustrated in FIG. 11. The control access circuit CAC consists essentially of an address register AR, a data register DR, a return-data registrater RDR and a time-window generator TWG.
The controller CTR-A may address the control access circuit CAC via its input/output bus. This bus may by way of example consist of ten address bits (two bits for control memory selection, eight bits for address selection), nine data bits, nine return-data bits, and two bits for read/write commands (10/01) and possibly one DO command. The total input/output bus thus has 30 or 31 bits.
The control access circuit CAC isolates the synchronous operation of the switching matrix and the asynchronous operation of the controller CTR may address the control access circuit CAC at any time, but the instruction is latched in the control access circuit registers until the timing window generated TWG opens the control access cycle of the time slot. An instruction must be present prior to the start of the control access cycle, otherwise the execution of the instruction is deferred to the next control access cycle (one time slot later). After the successful execution of the instruction the control access circuit CAC sets a DONE flag (DO) to the controller CTR.
The transfer of information from incoming time slot interchanger A to outgoing time slot interchanger A via cross-point AA is shown in FIG. 12. In addition to the time slot interchanger data stores IBM-A and OBM-A, there are dual rail parallel/ serial and serial/parallel converters with synchronization circuit, these dual rail converters are R1-R2, Re-R4, R5-R6 and R7-R8.
Data are shifted from the upper rail register into the lower rail register during the control memory read cycle. The start of the data transfer is coincident with the reading of the data stores. The time of the serial/parallel and parallel/ serial converters from and to the multiplexors is included in the timing scheme. The operations indicated by the same number in a circle are executed during the same cycle.
These cycles are arranged as shown in Table 4 as (1) increment address counters and shift data from upper rail registers to lower rail registers in FIG. 12, (2) read all control memories, (3) read all data memories and (4) write all data memories. There is a transfer delay of two time slots. In Table 4, the stacking of the control cycles is shown.
TABLE 4______________________________________Stacked Control CyclesCYCLE 1 CYCLE 2 CYCLE 3 CYCLE 4______________________________________Network Increment Read Read WriteControl AC ICM IBM IBMMode OCM OBM OBM XCMCall Read/WriteProcess all memoriesMode______________________________________
As shown in FIG. 12, a parallel register and a shift register is used for each serial-to-parallel and parallel-to-serial converter so that an entire time slot of 488 nanoseconds can be used to perform the serial transfer from register R4 to register R5. All transfers between parallel registers and shift registers takes place at the start of Cycle (1). All serial transfers then begin at the start of Cycle (1) and complete at the end of Cycle (4). There is fixed delay of two time slots from the time that input buffer memory IBM-A is read until the data is written into the output buffer memory OBM-A.
The progress of one data (speech) word through the matrix will now be traced. Data from the multiplexer 10A (FIG. 10) is serially transferred via leads 12A and 16A into register R1 during the 488 nanoseconds of one time slot. In the next time slot during cycle (1), data from the shift register is transferred to the parallel register R2 to prepare for writing into the input buffer memory IBM-A. The data is held in this parallel register during the entire time slot, and written into the input buffer memory IBM-A during cycle (4). This word does not proceed further through the matrix until the occurrence of the time slot assigned to this call as stored in the control memories.
Next the data is transferred through the space switch from the incoming time slot interchange to the outgoing time slot interchanger. The control memories are read during Cycle (2) using the contents from the address counter AC for the addresses. The result from control memory ICM-A is used as the address for reading memory IBM-A in Cycle (3). The data read from memory IBM-A is held in parallel register R3 to initiate the serial transfer through the crosspoint AA. At the start of Cycle (1) of the next time slot, the data is transferred into register R4, and the word read from memory XCM into a register 100 is loaded into a register 101 that drives the crosspoint decoder CD-A to close the proper crosspoint AA. The serial transfer then takes place during the entire time slot (all 4 cycles), from register R4 into register R5. At the start of the next cycle (1), the data is gated from the receive serial shift register R5 to a parallel register R6. During Cycle (4) of this time slot the parallel register is written into the output buffer memory OBM-A.
There is a fixed delay of two time slots from the time that the memory IBM-A is read until the data is written into memory OBM-A, and the address counter AC has been incremented by two. Thus if the same address counter is used for an entire switching group, the data is written into memory OBM-A at an address two locations past the address corresponding to the time slot in which the data was sent from the incoming time slot interchanger through the switch. Thus the controller CTR-A should add two to the switch time slot number before writing it into memory OCM-A in setting up a network path.
Next the data is transferred from the outgoing time slot interchanger to the multiplexer 10A. The control memory OCM-A is read during cycle (2). The word read from memory OCM-A is used as the address for reading memory OBM-A into parallel register R7 during Cycle (3). At the start of Cycle (1) in the next time slot the data is transferred from the parallel register R7 to a shift register R8 to initiate the serial transfer to the multiplexer 10A via line 18A. The serial transfer proceeds for the entire time slot and the data is transferred into a parallel register in the multiplexer at the start of the next cycle (1). The data can then be used by the multiplexer any time during the next time slot.
It may be noted that the only operpation to occur in Cycle (1) that is associated with the cylindrical time slot interchanger operation is to increment the address counter AC. No cyclical time slot interchanger operations occur during Cycle (1). Thus, this cycle is available for the controller CTR-A to gain random access to all of the time slot interchanger memories.
While a four-cycle arrangement has been described above, it should be noted that two or three cycle embodiments are also possible, and have the advantage that slower memories may be used.
Patent Citations
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Friday, February 7, 2014
The second annual Mardi Gras parade and party will be held on Fat Tuesday, March 4 in beautiful downtown Georgetown.
The event is being sponsored by the Georgetown Business Association, the Cultural Council of Georgetown County, and the S.C. Maritime Museum.
Anyone who wants to participate in the parade should join us at 6 p.m. at Georgetown's historic Town Clock on Front Street. At 6:15 the parade will begin, led by last year's Mardi Gras King, Kevin Jayroe. We'll walk the sidewalk from Screven to King Street, turn around and walk the opposite side of the street back to Screven.
Groups or individuals who would like to participate should adorn themselves with colorful and eye-popping Mardi Gras attire, such as beads, boas, feathers, masks, sequins, hats, umbrellas and balloons. Start scouring your closet, the local thrift shops and discount stores for these items and more.
Try to get 10 of your friends or your organization to form a Krewe, such as The Maryville Krewe or the St. Mary's Krewe. If you do, contact Kevin Jayroe at Bienvenue Home, 814 Front St., (843) 318-1439, and he'll see that you get recognized.
After the parade, the party starts at 7 p.m. at the Maritime Museum at 729 Front St. Admission is $20 per person, unless you are a member of a Krewe. Krewe members are admitted for $15 per person.
Your admission fee covers Cajun Chicken and Sausage Gumbo, a variety of delicious food from area restaurants, the traditional King Cake and Moon Pies, beer, wine, and non-alcoholic beverages.
Everyone at the party will cast their ballots for this year's Mardi Gras King and Queen, best Krewe, and best costume.
Participation in the parade is free, whether or not you plan to attend the party.
Tickets to the party may be purchased at the following locations: Bienvenue Home (814 Front St.), Cultural Council of Georgetown County (922 Front St), Clock Tower Books (105 Screven St.), or the S.C. Maritime Museum (729 Front St.). Tickets may also be purchased at the door.
For questions, contact Debby Summey (843) 446-4777 or email at email@example.com.
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Cheap International Calls
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SO MUCH PROTEIN!!! Sorry for the slight delay, but it took me a few tries to get this one right! Quite proud of it though. Just sayin.
ALSO FOR YOUR SAFETY: I forgot to warn against "bean poisoning" (seriously, google it) because my slow-cooker reaches high enough temperatures to prevent it, but most don't! If you're not sure about your's (or just want to be on the safe side), boil your beans briskly for 5 minutes after soaking them and before adding them to the slow-cooker.
Music by Sylvie Lewis
Provided by Mevio's Music Alley


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The LLM/MSc in Criminal Justice and Penal Change examines the range of legal, political and social responses across the world to what is widely known as 'the penal crisis'.
Blending a rigorous understanding of fundamental theory with evidence about real world problems, you will analyse recent innovations in theory, policy and practice.
Drawing on a range of disciplinary approaches, the course will enable students to develop a rational and just response to crime.
The LLM/MSc in Criminal Justice and Penal Changeis unique in both its approach and its flexibility.
Who is the Course for?
The Strathclyde LLM/MSc in Criminal Justice and Penal Change draws students from a wide range of disciplinary and nationalities.
- Practitioners working in a wide range of law, justice and welfare areas;
- Professionals developing justice policy;
- Members of the Third / Voluntary Sector;
- Recent Graduates in law, social sciences, humanities from around Scotland, UK and around the world
Students on the Strathclyde Master's (LLM or MSc) in Criminal Justice and Penal Change come from a range of backgrounds. Some are recent graduates in law, humanities and the social sciences from around the world. Many are current practitioners, policy-makers in different fields of criminal justice and they find the course an invaluable assistance in gaining a step up the career ladder.
Postgraduate entry requirements are in our prospectus.


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Public Health
Public health care professionals work to protect and improve the health of whole groups of people – the health of populations and communities versus focusing on the health of the individual. There are three core public health functions:
- Assessment and monitoring community health
- Formulating public policies in communities and populations
- Assuring that all populations have access to appropriate and cost effective care including health promotion and disease prevention.
Some public health issues:
- The emergence of new diseases and potential pandemics of influenza, SARS, swine flu, HIV-AIDS, virulent tuberculosis and other diseases
- The threat of antibiotic resistant bacteria
- Environmental health issues regarding our water, food, air and industrial health
- Nutrition, obesity
- Alcohol, drug and tobacco addiction and abuse
- Bio-terrorism
- Health issues associated with poverty
- Women's health, health of neonates, infants, and seniors
- Issues associated with immunizations
- Sexually transmitted diseases
- Health care disparities, both in the U.S. and abroad
Public Health is a multi-disciplinary field involving many different kinds of professionals, including some physicians and nurses, as well as graduates of formal public health programs. The focus can be domestic or international. There are a variety of specialty areas within the field:
- Biostatistics - use of statistical methodology for analyzing health related data
- Epidemiology - study of the distribution and determinants of disease and disability in populations
- Health Policy and Management - study of health care systems, health care reform, health law, financial management, clinic management, and policy analysis
- Health Education/Behavioral Science - practice of selecting, applying and monitoring appropriate behavioral, social and political change strategies to enhance the health of populations
- Environmental Health - study of issues associated with the adverse chemical, physical and biologic agents in the environment on human health
Depending on their specialty, public health professionals may be employed by government agencies and health departments, insurance companies, community wellness centers, public school systems, colleges and universities, hospitals, private businesses or other facilities.
Public health degrees generally fall into two categories: professional or academic. The master's degree in public health (MPH), DrPH, and MHA are examples of degrees for people who want careers as practitioners in health departments, managed care organizations, community-based organizations, hospitals, consulting firms, international agencies, state and federal agencies. Students who may want to teach at a university or conduct research may want to pursue an academic public health degree such as a MS, PhD, and ScD.
There are currently 41 accredited schools of public health and a larger number of credited programs that exist in schools such as medical or education schools. All schools of public health have curricula built around the 6 core courses of biostatistics, epidemiology, environmental health, health management and policy, public health practice and social and behavior sciences. However, they may be quite different from each other due to varying program emphases and specialties. There are also a number of degree options outside of the MPH with varying requirements and entry points for each program. In addition, there are many combined degree programs such as the MPH/MD, MPH/MSN, MPH/JD, MPH/MBA, MPH/MSW, MPH/DVM, MPH/DDS, MPH/MPP (master's of public policy).
For students interested in international public health, the Peace Corps offers a Master's International program in partnership with various universities such at University of Pittsburgh.
Association of Schools of Public Health
- list of schools
- view web resources on careers in public health request free print brochures on graduate education and career information


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Microsoft Theater Tickets are available for all events and concerts at the theater. Barry's Tickets has no service fees or hidden charges and tickets for any Microsoft Theater concert or event are 100% guaranteed to be authentic and delivered on time.
• Call us: You can order Microsoft Theater tickets over the phone at (866)708-8499 or ask about seat locations available or any questions you might have about the Microsoft Theater seating. You can have your tickets set for E-Download, Fed Ex or have them ready for pick up at our office.
• Walk In - You can walk in and purchase tickets from Barry's Tickets which is located Caddy-Corner from the Microsoft Theater inside the Luxe Hotel and is open till 9:00pm seven days a week past the start of the game.
If you already purchased tickets online or by phone our office next to the Microsoft Theater is an easy and convenient way to pick up tickets. We are happy to print your tickets out for you if you purchased tickets from us.
Microsoft Theater at Microsoft Square Address:
777 Chick Hearn Ct. Los Angeles, CA 90015.
The Microsoft Theater at Microsoft Square currently has a seating capacity of 7100 for a concert or event. Microsoft is not just taking over the naming rights of the Nokia Theater the entire theater will be getting a renovation. The Microsoft Theater will be equipped with the latest technology all to enhance the theatergoer experience at the venue. The renovation will include new seats, new sound system as well as even new carpeting and color scheme for the venue which opened its doors originally on October 18th 2007 with six concerts by the Eagles and Dixie Chicks. Since the opening in 2007 the Theater has had over 700 concerts & events bringing more than 3.5 million fans into the venue.
The seating capacity of the Microsoft Theater, oddly enough in contrast its first impression, is a modest and intimate 7,100 seats. Divided up into the pit, orchestra, loge, and mezzanine, in order from the section closest to the stage to the section furthest, the orchestra and loge Microsoft Theater seating sections offer ample wheelchair accessible seating. It must be admired that no seat inside the Microsoft Theater is any further than 220 feet from the stage- a proximity that few other venues can provide.
Barry's Ticket Office is located Across the street from the Microsoft Theater at Microsoft Square inside the Luxe Hotel.
Barry's Tickets is located in the heart of downtown Los Angeles and open from 9:00am to 9:00pm seven days a week! Our downtown office is located Across the street from the Microsoft Theater at Microsoft Square making it fast, easy and convenient for picking up or purchasing verified authentic and guaranteed tickets to all Los Angeles Concerts even at the last minute before the performance starts.
Barry's Tickets is a full-service national event ticket marketplace. We are not affiliated with any box office, venue, sponsor, team, performer or other organization.
Any trademarked terms or images that may appear on this page are used for descriptive purposes only. © 2015 Barry's Tickets All rights reserved.


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Political Capitol
Brian Lockhart covers the Connecticut General Assembly in Hartford
Monthly Archive for March, 2012
AT&T lobbyist says telcom industry not declaring open season on CT parks
John Emra, an AT&T lobbyist, emphasized in an interview Thursday that controversial legislation opening up state parks and forests to telecommunications towers remains a work in progress. Emra said although the industry wants to stop prohibiting equipment on state property, telcom companies are fine with revised language allowing the state Department of Energy and Environmental […] [Read More]
State cops bring in Amann for help against Guv's staffing bill
State troopers were recently dealt a blow in their ongoing battle with Democratic Gov. Dannel Malloy over his efforts to eliminate a minimum staffing law on the books since 1998. State statutes call for lawmakers to maintain a force of 1,248 troopers. This minimum had been rarely met under prior Republican governors (three times – […] [Read More]
Energy Committee bill would open state parks to cell towers
Proponents argued legislation passed out of the General Assembly's Energy and Technology Committee this afternoon will allow Connecticut and state companies to better compete in the telecommunications industry. "If you're going to have competition you want to ensure that's as unfettered as possible so the customer prevails in that environment," Sen. John Fonfara, D-Hartford, a […] [Read More]
Donovan dances around ed reform questions
I joined CT News Junkie's Christine Stuart in approaching state House Speaker Chris Donovan, D-Meriden this morning at the capitol for his reaction to a legislative committee's decision to gut Democratic Gov. Dannel Malloy's controversial education reform bill. The proposal – particularly changes to tenure (job security) – has been opposed by the very teachers' […] [Read More]
Malloy admin acknowledges legislative process but not defeat
After his successful first legislative session as governor, Democrat Dannel Malloy this year has found the General Assembly less inclined to fall into line and back his proposals. They're up for election in November, he is not. Take the amendments to Malloy's sweeping education reforms. It shouldn't come as a surprise Democrats on the education committee have, […] [Read More]
Tong fundraising email targets August primary, ignores May convention
Even as he courts the Democratic delegates needed to remain competative at the party's May nominating convention, U.S. Senate candidate William Tong is telling supporters he will mount a primary in August and take the decision out of the hands of those same "party insiders." In a fundraising email Marc Bradley, Tong's campaign manager, totally ignores the convention. Bradley […] [Read More]
We want to hear all your CT stories … except maybe THOSE…
I'll be off beginning March 14 and returning March 26. I thought it would be appropriate to use this last pre-vacation blog post to share an observation involving the state's new tourism campaign. As part of Democratic Gov. Dannel Malloy's $22 million effort to brand and market Connecticut and its attractions, state tourism officials have launched a […] [Read More]
Democrats! It's OK to back Guv's ed reforms. Prez Obama says so!
Celebrity education reformer Michelle Rhee will be in Hartford Wednesday for a rally supporting Gov. Dannel Malloy's divisive ed reforms. But first, during Tuesday evening's news, her organization – StudentsFirst – will air this ad encouraging/pressuring (you decide) the legislature's Democratic majority to back Malloy. It's part of a six-figure buy that will last a […] [Read More]
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Katy Long and Jake Vidourek received the grants to support their internationally focused academic and professional careers.
Long, who received a bachelor's degree from TTU in world cultures/business and German, will attend the Vienna School of Diplomacy. She recently completed an internship at Atlantische Akademie in Reinland-Pfalz, Germany.
Vidourek, who holds degrees from TTU in music and German, will go to Vienna this fall to study the construction and development of the Viennese oboe while teaching English.
"Our past awardees have been exceptional students, but Mr. Vidourek and Ms. Long have distinguished themselves in an extremely competitive selection process," said Debbie Barnard, TTU assistant professor of French.
Long's grant in international relations covers her first year of graduate study at the Diplomatic Academy of Vienna; there was one grant advertised, and she got it, She says this experience falls right into line with her career plans.
"I'd like to work for the U.S. Foreign Service and concentrate on European affairs," said Long. "I'll be able to look at issues from an EU perspective during my Fulbright appointment."
Long previously traveled to Austria and fell in love with the culture. As an intern in Germany, she helped set up academic seminars and lectures, focusing on research and logistics.
"My boss was a former politician and we covered topics with international interests, including sports, healthcare bills, and the German election," she said. "It was an eye-opening experience and a great step for completing my major."
Long will work toward her master's degree and focus on economic issues.
"I see a lot of travel in my future, and it will be great to be in such close proximity to a United Nations office," said Long.
Vidourek's grant is in musicology, a field dominated by graduate students. But Vidourek, an oboe performance and German double major, wrote a proposal so impressive that the Fulbright Commission in Vienna found alternative funding for his grant.
He says he's been comfortable with international travel since his early college days, when he received encouragement from Barnard and Heidemarie Weidner, TTU associate professor of English. He's already visited Vienna once and Berlin twice through TTU.
"I traveled to Berlin during my sophomore year and continued to take classes about foreign cities, including Berlin and Vienna," said Vidourek. "I applied for a Fulbright because Dr. Barnard had confidence in me, and I thought I should do it based on her encouragement."
Vidourek will teach 16-18 year olds English as a teaching assistant from October through June. During that time, he will pursue expertise about his chosen instrument, the oboe. The West Chester, Ohio, native learned of TTU from his high school oboe teacher, Julie Fuqua, a TTU graduate from Nashville. He credits William Woodworth, TTU professor of oboe, for recruiting him to TTU and encouraging him in all of his endeavors - both musical and German - during his years at Tech.
"I have no doubt that Ms. Long and Mr. Vidourek will continue to distinguish themselves while in Vienna, and TTU should pride itself on attracting students of their caliber," said Barnard.


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Marci's Table
Delicious helpings from a philosophizing foodie with Marci Izard
Posts filtered on Tag
Warming Roasted Root Vegetables
This is a warm and nourishing autumn side dish has natural sweetness and a grounding effect. It may help cut down on sugar cravings too! [Read More]
Wholesome, and Awesome, Spaghetti Squash
This radiant dish packs a punch of flavor that won't knock you out with weightiness and fatigue. It is wholesome, healthy, vibrant and delicious! [Read More]
Healthy Recipes for the Holidays
While entertaining, I typically feel the need to abandon the quirky and healthy recipes that I tend to prefer. The priority becomes maximum flavor and meeting everyone's expectations. I suppose this makes me a good hostess? Shameless people pleaser?
Maybe it's all my family's fault. Either way, it definitely takes some chutzpah to serve holiday dishes that stray from your basic mashed potatoes, stuffing and green bean casserole. But there are ways to make the switch without sacrificing flavor and resorting to steamed broccoli.[Read More]
How to Eat Like You're at a Yoga Retreat
When I first saw ads for a women's retreat run by Houston's Yoga One Studios, I wasn't sure if it would be neo-amish (#monklife 2013). I had visions of a weekend marked by sun salutations and silence, along with bland food, green tea, stretch pants and sobriety. Needless to say, it made me nervous. [Read More]


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A fabulous Custom Shop Telecaster prototype reproduction.
The LTD Limited Snake Head Telecaster is a reproduction of the prototype that Fender used to take around to clubs for artist to try. It is from this guitar that the Telecaster blossomed and changed the musical landscape forever. Unique features include the "snake" headstock, a Single Custom Nocaster Vintage Tele single-coil pickup in the bridge position, vintage style bridge with 3 vintage saddles, and half Tele pickguard. Includes case, strap, cable, limited edition certificate of authenticity.


text:
Register now for free, or sign in with any of these services:
As a grad of JCU, I fully support the protesters. Should gays be excluded from teaching? That thinking goes back to 1978. Get with it! Opposition to these students is nothing more than animus toward gays. End of story.


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Nutrition: EFSA consults on dietary reference values for iodine
News in brief
15 January 2014
15 January 2014
EFSA has launched a public consultation on its Scientific Opinion proposing adequate intakes of iodine. The opinion is part of EFSA's ongoing work on Dietary Reference Values (DRVs). Interested parties can submit written comments by 26 February 2014.


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Most EVSC students fulfill state immunization requirements
EVANSVILLE - About 95 percent of Evansville Vanderburgh School Corp. students meet the state's vaccination requirements, and school district officials are trying to get the remaining few in compliance.
The state last year added new required vaccines for students entering sixth grade: tetanus, diphtheria and pertussis boosters and two doses of the chickenpox vaccine.
Waivers can be obtained in special circumstances.
School districts struggled a year ago to get the word out about the new requirements. This year, the list of students not meeting the requirements is much shorter, said Diana Butler, director of health services for EVSC.
Most students who remain out of compliance are in the sixth grade. Butler said the school district has sent home letters to those families and also has been making phone calls.
Students who have not received the required vaccines are being encouraged to contact their primary care physicians or the Vanderburgh County Health Department as soon as possible.
"We have until Nov. 1 to enter all student records into the state immunization registry," Butler said.
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Starting & Managing
Starting a Business
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For Contracting Officials
- HUBZone
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Local Assistance
About SBA
What We Do
SBA Team
SBA Locations
SBA Newsroom
SBA Initiatives
- SBA Emerging Leaders Initiative
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- Greening SBA
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MOVED: Where to look, if I want to buy an already established business?
by munkhjin_mg, Window Shopper
- Created: October 22, 2013, 11:07 am
- Updated: October 29, 2013, 10:48 am
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By Cheryl PellerinAmerican Forces Press Service
WASHINGTON, Jan. 8, 2013 Stability in the size of the Defense Department's budget -- and especially in the process of funding it -- is critical to maintaining national security, DOD Comptroller Robert F. Hale said here yesterday.
During a keynote address at the Brookings Institution here, Hale discussed three steps that must be taken to accommodate lean budget times.
Two of the steps already are in place, he said: determining a defense strategy to guide spending and instituting initiatives that stretch defense dollars.
"And third, we need -- I would say desperately need -- more stability, both in terms of budget size and, maybe particularly, budget process," Hale added.
In more than three decades of working in and around the defense budget, he said, he has never seen a period featuring greater budgetary uncertainty than the next few months present.
Meanwhile, Hale said, he hopes to submit the fifth defense budget he's overseen as comptroller.
"The first two [budgets] featured increases in the top line," he said. "The third one, in February 2011, featured substantial top-line reduction, and the last one featured a significant reduction: about $260 billion over a five-year period relative to our planned $487 billion [reduction] over 10 years. And we may not be done."
The 2012 American Taxpayer Relief Act, which Congress passed Jan. 1, may force further reductions, Hale said. Although the law avoided activating a "sequestration" mechanism in a budget law passed last year, the threat of that mechanism's automatic across-the-board cuts now looms beginning March 1, he added.
"We're still working on the details, but the total sequestration for DOD appears to be roughly $45 billion if it all goes into effect -- about 9 percent of our budget," Hale explained.
"That is less than the sequestration [amount of about $62 billion] we faced before passage of the New Year's Day act. That could have been as much as 12 percent. But we also have two fewer months in which to accommodate those changes," he said.
At a time when U.S. national security challenges have never been more complex, Hale said, the lack of budgetary stability and the reliance on continuing resolutions, which fund only a portion of the fiscal year budget at a time, makes it very hard to plan and extremely hard to plan well.
"We also cannot rule out an extension of the continuing resolution throughout the rest of this year, and that would sharply reduce the operation and maintenance funds that we have available and that we need to maintain readiness," one of the department's highest priorities, the comptroller said.
And while U.S. troops are in Afghanistan, protecting funds for wartime operations means even larger cuts in base budget dollars available for readiness, he noted.
"I think the nation's security would be better served if Congress adopted and then stayed with a more stable budget plan," Hale said.
The department hasn't enjoyed much budget-process stability during his tenure as comptroller, Hale added.
"I have personally coordinated four shutdown drills," he said. "During two of them, I was sitting in my office at 8 at night, not knowing whether at midnight we would shut down the department or not. Fortunately, we didn't in either case."
Continuing resolutions -- the nation is operating under one right now, he pointed out -- "really hogtie the department and its ability to manage," Hale added.
A questioner asked Hale how industry can help the department navigate in a leaner budget environment. "We need you to sharpen your pencils as much as we are trying to do with regard to your overhead and anything else that would help us hold down costs," he replied.
The department's Better Buying Power initiative, established in 2010, was directed at improving efficiency and productivity for the $400 billion DOD spends annually on goods and services. Part of the initiative seeks to work "more closely with industry to see what you can do there. In return, we owe you some stability, and … we're not there yet," Hale said.
"My hope is that in the next two months, all of us in the leadership of the nation and the Congress can work together to provide that stability," he added. "Our national security demands no less."
Related Articles:Obama Signs $633 Billion Defense Authorization Act Panetta Thanks Congress, Seeks End to Sequestration


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Blank screen after second reboot 180.44 Ubuntu 8.10
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Blank screen after second reboot 180.44 Ubuntu 8.10
Hello, first off I need to clarify that I am quite new to Ubuntu and Linux in general, and even though I'd like to think that I am learning at a fairly quick pace, I still need help with some of the basics. Also, I'm sure that this topic has been covered a multitude of times, however I've been unable to find a solution that works for me. Onward.
After a clean install of Ubuntu 8.10, the update manager upgrades my kernel to 2.26.27-11-generic, and reboots. I decide to install the latest drivers through the nvidia-glx-180 package in synaptic (Ubuntu doesn't find 180 in the Hardware Manager or whatever), as well as all that it suggests, the 180-dev package, and the 180-module-something-or-other that is described as being helpful in detecting hardware (sorry if I'm being vague here). After running nvidia-xconfig, I restart X using ctrl-alt-bckspc, and much to my surprise it works (I've gone through quite a few attempts at this over the past week
). I check X Nvidia Settings through the System bar, and it found everything on my system: Motherboard, SLI, both GPUs, even the monitor refresh rate (60Hz). Great, right?
Then I turn off my computer, as I usually do when I'm done with it, and upon rebooting I'm left with a completely black screen. Judging by the HDD indicator and the num lock LED, Ubuntu completely loads up, however the LED on my monitor flickers as if my computer has been turned off. The only thing I can think of is that my monitor resolution/refresh rate is conflicting with the settings, however nvidia-settings definitely tells me otherwise.
I know I'm supposed to attach the xorg.conf file and an error report, but I don't really know how I can do that if I can't access the desktop, and I can't imagine anything unusual showing up in the error report. Any suggestions? My monitor's specs are a 1280x1024@60Hz. Sorry for typing so damn much.
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See what's on at Adelaide Festival Centre.
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By Kathleen T. RhemAmerican Forces Press Service
WASHINGTON, Aug. 16, 2005 Officials working to create a draft Iraqi constitution believed "until the very end" that the draft would be finished on time, the U.S. ambassador to Iraq, who has been working closely with the Iraqis, said today.
About 20 minutes before an Aug. 15 deadline to approve a draft constitution passed, Iraqi National Assembly members voted to extend the deadline by seven days.
"It was not finished because a couple of issues were not agreed to in detail," Ambassador Zalmay Khalilzad said in a news conference in Baghdad, Iraq.
Khalilzad said officials also had some administrative concerns about the document. As changes were submitted from various parties, there may have been confusion in what was to be in the final document, he explained.
"Given the pressure of time and the fact that everyone ... was tired, there was a concern that all the changes that were made were not, perhaps, reflected in the text and that language may not also be appropriately edited," he said.
The ambassador noted that he had found one instance of articles that had been eliminated reappearing in the final draft.
He said officials decided to take some extra time to finish the job right rather than to accept what they had and fine-tune it later.
Khalilzad listed the areas in which negotiators agreed and those in which there was still work needed to reach an agreement. Members of the committee drafting the constitution have agreed on basic rights of Iraqi citizens, the role of Islam in government, the structure of the government.
Negotiation still is needed on the level of federalism and on powers of the president and prime minister, he said.
Despite press reports, Kurdish independence is "not on the table" and is not a sticking point in negotiations, Khalilzad said. "Nobody has raised, in any meeting that I have been involved in, the issue of (Kurdish) independence or separation from Iraq," he said. "Kurdish leaders have said repeatedly they want to be a participant, a stakeholder, a shareholder in this new Iraq."
Khalilzad said he is encouraged by the level of compromise negotiators already have reached and optimistic that officials will agree on a draft constitution within the added week.
"Based on my detailed knowledge of the state of discussion among the Iraqi leaders and the agreements that have been arrived at already with regard to key issues and what remains, I believe that an agreement will be arrived at if the leaders continue with the attitude of compromising, putting oneself in the shoe of the other side ... looking at options, (and) not remaining stuck with positions that may have been appropriate for a different set of circumstances," he said.
The ambassador has been very involved in discussions over the new constitution, not directing events, but offering assistance to bridge differences, he said. He explained that even though this is an Iraqi-led process, it's in America's best interest for him to help resolve any issues he can.
"I'm not going to stand by if they need my help to say, 'Well, no, you sink or swim on your own, don't call me,' or, 'Take an aspirin and call me tomorrow,'" Khalilzad said. "No. I'm going to say, 'I'm available.'"
Khalilzad said he's "not going to be shy about" the fact that the United States "has a lot at stake" in Iraq. "We want Iraq to succeed," he said. "A lot of American treasure and blood has been spent there."
Related Articles:Bush Applauds 'Heroic' Iraqi Efforts in Writing ConstitutionOne-Week Extension Granted for Iraqi Constitution


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Apr 20, 2009
It is 1:15AM on Monday morning. My husband is at work. He went in to "finish something up" and ended up staying a bit.
I can't sleep when he's not here.
So I finished a project, a personal project, that acted as a thought process. I always code when I'm feeing troubled, or anxious, or uncertain. Code makes sense. It's logic. It is ones and zeros. It's my zen.
So I redid my website.
And as I sit here, wondering if I should try to sleep or wait for my husband, I open one of my old journals looking for a memoir to write. There are so many journals, so many memories, so many really bad poems.
Tonight, though, I open to a printed page taped in my journal. It's an email I printed out from Tuesday, February 29, 2000:
"Dearest Leslie,
It seems an eternity since last we spoke. My hopes lie in that you are faring well. I fear the worst for my well being if this silence lasts one moment longer. Sparing your soul the agonizing descriptions of the depths of despair from which my feelings well, I cannot divulge the extent of my madness. Fear not, I breathlessly await your return. Ten days hence, Until then…
Yours forever,
Mrs. Flinger"
I smile. It's nice to be waited on. I will wait.
I will always wait.
Testing?! Wooohoo!
Because *some developer* went to bed entirely too late. Cough.
By Mrs. Flinger on 2009 04 20
Oh it's so pretty! do mine!
By Karen Sugarpants on 2009 04 20
Your site is purdy. (And weren't you the hottie in high school!)
By Matthew on 2009 04 20
Very, very prettiful—is he home, yet?
By Liz@thisfullhouse on 2009 04 20
Love the new look!
Also, left you an award on my page: http://www.texasredbooks.com/2009/04/new-awards-and-moving-news.html
By TexasRed on 2009 04 20
So totally the purveyor of sexy code.
<3 it!
PS: you wrote yerself a sexy hot letter? Did you get some? You know… from yerself? Heheheheh.
By Sarcastic Mom on 2009 04 20
and you code too? i think you just might be perfect! coding is a foreign language to me. i don't get it at all. i need a coding for dummies book. better yet i'll just call on my coding friends if i ever decide to break out of the blogger site. i fear anything but blogger, because i'm a wimp like that!
By natalie on 2009 04 20
Beautiful, love it!
Your man has a more-than-passing resemblance to Leo DiCaprio, in the HS one and the mid-post one. :D
By Al_Pal on 2009 04 21
When you talk about coding, it makes me so HOT.
Your site looks so purdy! Nice coding.
By Jennifer on 2009 04 21
Love the new look. Talent, my friend, pure talent.
By Darla on 2009 04 21
Leslie, LOVE the new look. A lot. Very nicely done and great advertising for your abilities!
By Tina@SendChocolate on 2009 04 24
oh and your code, she is SEXAY.
By Tina@SendChocolate on 2009 04 24
I think this is the best one yet, although I still liked those tiny feet in your flip flops.
By Oma Flinger on 2009 04 25


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sexual arousal to fighting paraphernalia such as: boxing gloves, shoes, headgear, mouthpieces etc.
"that dudes into foxy boxing" "isnt that called agonophilia?" "why yes it is.....you're one word smarter"
by imintofoxyboxing April 28, 2009
1 more definition
Top Definition
Agonophilia covers a broad range of sexual arousal, from fighting paraphernalia (boxing gloves, cups, headgear) and through the actual engagement in fighting (legitimate or fantasy). For those who actually fight the arousal is multi-dimensional. The combination of fighting gear, the physical contact with the opponent, and the actual fight is indescribable. Depending of the quality of the match, the sexual energy between the competitors, and the presence of spectators, some matches go to legitimate knockout, and sexual intercourse may follow with dominance and submissive roles determined by the outcome of the fight. Some men who ordinarily consider themselves straight clealrly enjoy the combination of fighting gear and male to male contact while fighting.
Barry was an incredibly hot man and a good boxer. Our three separate fights were intense and often bloody. Because we fought in a public boxing arena intercourse was out of the question. Early in the fourth round of the last fight I broke his nose with a three punch combination and he clinched me firmly to avoid being knocked out. Agonophilia caused me to ejaculate in my trunks just as the referee stopped the fight due to his excessive bleeding. After this we frequently had private bouts that were sensual and brutal. The sexual arousal from the gear, his great body and from beating him up was awesome and the winner got to fuck the loser.
by GlovedFighter July 16, 2011


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August 2, 2015
FORT HOOD, Texas (AP) The Army psychiatrist charged in the 2009 Fort Hood mass shooting says the U.S. government is at war with Islam.
Major Nidal Hasan released a lengthy statement to Fox News on Saturday in which he says he regrets serving in the Army and "participating in the illegal and immoral aggression against Muslims."
Hasan is charged with 13 counts of premeditated murder and 32 counts of attempted premeditated murder in the November 2009 attack at the Central Texas Army post. His trial is scheduled to start August 6th.
Since Hasan has started serving as his own attorney, he has spoken more in pre-trial hearings and jury selection. He faces the death penalty if convicted.
Fox News reports that Hasan didn't directly address the shooting.
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Reviewed By Chris L (RALEIGH, NC) Reviewed for a 2011 Hyundai Genesis —6/21/2015 5:29 AM
Installed on my 2011 Hyundai Genesis 4.6 V8 sedan and have put 2000 miles on the Posi Quiet Ceramic Brake Pads and nave had no problems. Quiet, smooth braking
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EBC brake pads is worth every dollar. My car brakes work better now, than when it was brand new. I will never replace with another brand ever again as long EBC is available.Thank you for great quality brake pads!


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Jakle's Jacuzzi
Jeanne Jakle brings you TV and radio news from San Antonio and beyond.
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Six Texans evade 'Idol' cuts; now part of Top 16
All six talented Texans continue to ride high in the saddle on "American Idol," now making up more than a third of the remaining Top 16. [Read More]
S.A. dancer up for MTV prize; could be our first reality winner
Lindsey Blaufarb is a member of Beat Freaks, the all-girl dance crew that, after wowing the judges of MTV's "America's Best Dance Crew" for weeks, made it into the last face-off. [Read More]


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WWC is the only statewide organization offering skills development and support in the areas of career planning, entrepreneurship and financial management. For Mainers in both life and career transitions, it provides an empowering environment for participants to define and achieve their goals.
Our Mission:
" Helping Maine people succeed in their workplace, business, and community."
We help individuals recognize strengths, overcome barriers, find resources, develop a plan, take action towards their goals: start a business, find a career, return to school, build assets, be active in the community.
Our Vision:
The economic empowerment of Mainers and their families.
Our Values:
Shared leadership, Community, Integrity, Resiliency, Optimism, Openness, Fairness
Our Strategic Directions for the next five years include:
- Establish a Diversified Funding Base
- Build a Sustainable organizational structure
- Support Continuous Program innovation
- Market effectively to all stakeholders
Our Structure:
Founded in 1978 as a displaced homemakers program through state legislation, Women, Work, and Community is the only statewide women's economic development organization in Maine. We are organized into six regions and serve all 16 Maine counties from 9 centers and outreach sites.
We are administered by and operate under the educational tax-exempt status of the University of Maine at Augusta/University of Maine System. An Advisory Council appointed by the Governor provides guidance and support.
Funding sources include the University of Maine System, federal and state contracts and grants, grants from private foundations, individual and corporate donations, and fee for service.
Enjoy WWC – A Brief History.
Available for download:
WWC 2014 Annual Summary WWC 2013 Annual Summary WWC 2012 Annual Summary WWC 2011 Annual Report