text:
A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips. The first plurality of metal bumps can be deposited directly on the contact pads, with or without an underbump metalization layer, or on metal conductive traces over one or more dielectric layers.
1. A semiconductor chip package comprising:
a semiconductor chip having a plurality of contact pads;
a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads;
a conductive trace extending from a location inside the hole along a surface of the first dielectric layer, the conductive trace being in electrical contact with the pad;
a second dielectric layer overlying the first dielectric layer and conductive trace and containing a second hole, the second hole overlying the trace;
a first conductive bump formed in the second hole and extending above the second dielectric layer;
an encapsulant layer overlying the second dielectric layer, the first conductive bump extending through the encapsulant layer; and
a second conductive bump on top of and in electric contact with the first conductive bump.
2. The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is located directly over a side edge of the semiconductor chip.
3. The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is coplanar with a side edge of the semiconductor chip.
4. The semiconductor chip package of claim 1 wherein:
the first dielectric layer contains a first plurality of holes, each of the first plurality of holes overlying one of the contact pads;
a plurality of conductive traces extend from a location inside the first plurality of holes, respectively, each of the conductive traces being in electrical contact with one of the contact pads;
a second dielectric layer contains a second plurality of holes, each of the second plurality of holes overlying one of the traces and being lined with a conductive layer in electrical contact with the trace;
a plurality of first conductive bumps are formed in the second plurality of holes, respectively;
each of the plurality of first conductive bumps extends through the encapsulant layer; and
a plurality of second conductive bumps are formed on top of and in electric contact with the plurality of first conductive bumps, respectively.
5. The semiconductor chip package of claim 1 wherein the second conductive bump has a flat top portion that is coplanar with a surface of the encapsulant layer.
6. A semiconductor chip package comprising:
a semiconductor chip having a plurality of contact pads;
a first conductive bump in electrical contact with the contact pad;
an nonconductive encapsulant layer overlying the semiconductor chip and surrounding the conductive bump, the first conductive bump extending through the encapsulant layer; and
a second conductive bump on top of and in electric contact with the first conductive bump.
7. The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is located directly over a side edge of the semiconductor chip.
8. The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is coplanar with a side edge of the semiconductor chip.
The present claimed invention relates to the field of semiconductor packaging. More particularly, the present claimed invention relates to a low cost process for the formation of a package which is of the same size as the IC chip.
Semiconductor chips, commonly referred to as "integrated circuits" are an essential component of any electronic devices. These chips are usually mounted on a substrate which is also equipped with terminals for the electrical connectivity with the external world. The substrate could be either a single layer metal leadframe or a multi-layer printed wire board or likewise. Besides providing means for external electrical connectivity, these substrates also provide mechanical support to the chips. Encapsulation ensures protection of the chip from harsh physical and environmental factors. The interconnection between the chip and its supporting substrate is commonly referred to as "first level" assembly. Several approaches exist for the first level assembly of chip to a supporting substrate. These include so called "Wire-bonding", "Tape Automated Bonding (TAB)" and "Flip Chip" approaches. An encapsulated chip which is equipped with terminals for interconnection to the external world is often referred to as a chip package.
The approach for the first level connection between the chip and the substrate has strong ramifications on the overall package size, performance and reliability. In an electronic device circuit, several packages are interconnected using a common substrate. A large package size increases the distance between each chip and other chips or between each chips and other elements of the circuit. These larger distances result in longer delays in the transmission of electrical signals between chips. Consequently, the entire device is slowed down. Therefore, a reduction in package sizes leading to compact assembly can permit faster operation and therefore improved performance.
The approach used for the first level assembly of the chip to the substrate also influences the capacitances and inductances associated with the chip-to-substrate connections. Interconnections which result in large values of capacitances and inductances may result in large signal transmission delays, large switching noise and therefore performance degradation. Thus, lowering the capacitive and inductive parasitics associated with first level assembly is highly desirable.
The semiconductor chip, substrate and the encapsulant is usually made of materials which have very different material properties. Specifically, the semiconductor chip, which usually consists of silicon, has very different thermal expansion properties from the substrate materials, which can be a printed wiring board, metal lead frame or a ceramic substrate or the encapsulant material which usually consists of a epoxy resin. During the operation of the device, the electrical power dissipated within the chip tends to heat the chip and the substrate so that the temperature rises each time the chip is turned on. The chip and substrate material expand by different amounts each time the temperature increases. This causes electrical contacts on the chip to move relative to the electrical contacts on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. Such stresses are generated each time the device is turned on and off. Such repeated exposure to stress may lead to breakage of the electrical interconnections.
In wire-bonding, the substrate has a top surface with a plurality of electrically conductive contact pads disposed in a ring-like pattern. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip glued to the top surface of the substrate. The front surface of the chip faces upward, and fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate.
Wire-bonding ordinarily can only be employed when the chip I/O pads are distributed along the periphery of the chip and the substrate connection pads surround the chip in a ring-like configuration. Furthermore, wire-bonding requires a minimum pad size of 75 microns on a side and becomes non-feasible if the relative spacing between the chip pads decreases below 50 microns. With the ever increasing number of gates in IC chips the I/O counts are also increasing. Distribution of these increasing number of I/O pads along the periphery without increasing the Si chip size is posing a big challenge. Distribution of the I/O pads on the entire surface of the chip provides a more efficient configuration but wire-bonding cannot be employed for such cases. In addition, a wire bond is associated with a high inductance values. Thus, for circuits which involve simultaneous switching of a large number of gates, as is the case in present generation of microprocessors, high inductances of the wire bonds lead to a large switching noise. Wire bonds usually fan out from the chip to the substrate. Therefore, overall package size increases considerably relative to the chip size. Therefore, from the compactness standpoint, too, wire-bonding does not provide an optimal first level assembly process.
Assembly using wire-bonding requires numerous process steps. For example in the formation of an overmolded wire-bonded Ball Grid Array package, some of the major steps consist of separating individual chips from the semiconductor wafer by sawing the wafer using a diamond impregnated saw. The wafer is usually mounted on a sticky polymer base so that the sawed chips remain stuck to the tape. Individual sawed chips are then attached to a substrate in a face-up configuration using a polymeric adhesive or a solder type of low melting point material. Usually, polymeric adhesive epoxies which are filled with metal flakes for good thermal and electrical conductivity are used for this attachment process. The adhesive joints are cured in an oxygen-free inert environment at elevated temperatures. Usually, the substrates have multiple repetitive units so as to process multiple chips. Then, the substrates with the attached dice are wire-bonded and then encapsulated. After the encapsulation process, solder balls are connected to the bottom face of the surface. These solder balls provide the external connectivity. After this step the individual Ball Grid Array packages are separated by sawing them off from the rest of the substrate carrier.
Tape automated bonding (TAB) requires a flexible tape with metal leads mounted on a polymer film. Usually, the tape leads fan out from the chip pads to the substrate connection pads. Therefore, the package is considerably larger than the chip. The flexible tape represents a new layer for interconnection and considerably adds to the cost of the package. This also requires deposition of excess metal in the form of bumps either on the connection regions of the leads or the chip pads. This is an additional process step and require processes similar to those used for IC fabrication such as lithography, etching and likewise. This adds to the cost of the process. Also, as in wire-bonding in TAB assembly, individual chips need to be sawed off from the wafer. Then these chips are bonded to a flexible tape which contains metal traces for external connectivity. Bonding a single lead at a time slows down the assembly cycle time considerably, thereby increasing the cycle time and the cost. Therefore, usually all the leads are bonded simultaneously to the chip pads in what is referred as "Gang Bonding" process. This requires very tight control of the planarity of the tape leads and the chip pads connection sites. The long TAB leads also have high inductances and therefore lead to large switching noises in fast digital circuits. From a mechanical stress standpoint, flexible tape represents a good solution because the tape can deform and absorb the stress thereby increasing the reliability of the joints.
In a flip-chip process, usually the I/O pads are distributed on the entire surface of the chip. This enables placement of a larger no of I/O pads at a increased pitch without increasing the size of the silicon chip. The I/O pads are deposited with metal bumps of materials which can melt at bonding temperatures and fuse with the substrate pad materials. As in the case with wire-bonding and TAB, individual chips have to sawed-off from the wafer before these are bonded to the substrate. The chip is bonded face-down such that the active face of the chip with the connection pads faces the top surface of the substrate. The metal bumps on the chip pads provide a separation between the chip and the substrate. These bumps are considerably shorter in length than a wirebond or a TAB lead. Therefore, inductances associated with these joints are considerably lower. These joints, which are composed of stiff metal bumps, pose a reliability challenge. When mechanical stress builds-up due to temperature changes and a resulting expansion mismatch between the chip and the substrate, the metal joints unlike TAB tape, cannot deform and relieve the stress. This leads to breakage of the joints. In order to improve the reliability, an epoxy resin material is dispensed in the region between the chip and the substrate. This so called "underfill" material encapsulates the exposed regions of the metallic joints and acts as a stress buffer thereby significantly improving the reliability. However, this underfilling step is an additional process and adds to the assembly cost by increasing the process cycle time as well as the number of constituent layers.
Several different approaches exist in the prior art for the formation of compact packages. Two representative examples, spanning the range from large to nearly chip size, are given here. The first one is what is referred to as an overmolded ball grid array (BGA) package 100, schematically shown in FIG. 1a. In this package, the chip 101 is bonded to a printed wiring board (PWB) substrate 102 in a face-up configuration. The PWB substrate has multiple layers of metal traces which are used for connecting the peripherally distributed chip contact regions 103 on the chip 101 to the external solder balls 104 which are distributed across the bottom face of the PWB substrate. Wirebonds 105 connect the chip connection pads to top layer traces on the PWB. The top half containing the chip and the wirebonded regions are encapsulated in an epoxy resin system 106.
The second example is a compact package shown schematically in FIG. 1b. In this package integrated circuit chip 200 has an elastomeric overlayer 201. Chip contact ports 202 of the integrated circuit chip 200 are exposed and not covered with the elastomeric overlayer 201. Metal traces or leads present in a flexible tape 203 are used to re-distribute the I/O ports 202 from the periphery of the chip 200 to the central region of the elastomeric overlayer 201. One end of the leads or traces in the flexible tape 203 connects to one of the I/O ports 202 via a wire bond, whereas the other end is routed over the elastomeric overlayer 201 and is deposited with a Ni metal bump 204 for external connectivity.
The overmolded BGA package shown in FIG. 1a involves wire-bonding, and due to the fan-out of the wire bonds from the chip to the substrate, the resultant package size is large. The package shown in FIG. 1b in comparison presents a much more compact size. Both these configurations use long wires or leads for connection of chip I/O ports to the substrate. Thus, inductances are generally high. Both these packages are applicable only to those chips which have peripherally distributed I/O pads. These packages require several different material layers besides the chip. The assembly process starts with the sawing-off of the individual chips from the wafer. Then the chips are mounted on carriers for furthering processing. In the overmolded BGA package, the PWB substrate needs to be custom designed to match the chip I/O pad distribution. Similarly, in the compact package of FIG. 1b, the flexible tape needs to be custom designed for each chip design. In these approaches, each of the IC chips is separated from the wafer and bonded to individual sites on a substrate or tape. Although the substrate or tape can be enlarged so as to contain multiple such individual chip connection sites, still there is a size restriction on the substrate due to the limitation of the equipment which is needed for assembly of these substrates. Consequently, the substrates could contain only a small number of such individual chip sites and therefore, only a small number of chips can be assembled in one step.
Thus, a need exists for a method of forming a chip package which has fewer steps, uses fewer materials and can use the existing conventional equipment and infrastructure. Still another need exists for an assembly method whereby large numbers of chips from a wafer can be processed simultaneously. Also, a need exists for an assembly method which does not require mounting of the individual chips on substrates or frames for processing. Still another need exists for an assembly method wherein a large number of chips which are connected together on a wafer can be mounted in one region on a substrate and then encapsulated and processed to yield individual compact packages. Still another need exists for a package which offers low inductance. A further need exists for a package which is fabricated from the conventional materials and procedures so that the assembly costs are lower.
The present invention provides a method and structure for a chip package wherein multiple chips which are connected to each other are assembled and encapsulated together and then sawed to form individual chip packages.
Specifically, in one embodiment, the semiconductor chip package comprises a semiconductor chip having a plurality of contact pads; a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads; a metal trace extending from a location inside the hole along a surface of the first dielectric layer, the metal trace being in electrical contact with the pad; a second dielectric layer overlying the first dielectric layer and metal trace and containing a second hole, the second hole overlying the trace and being lined with a metal layer in electrical contact with the trace; a first metal bump formed in the second hole and extending above the second dielectric layer; an encapsulant layer overlying the second dielectric layer, the first metal bump extending through the encapsulant layer; and a second metal bump formed on top of and in electric contact with the first metal bump.
In addition, the invention includes a method of manufacturing semiconductor chip packages. The method includes providing a semiconductor wafer containing a plurality of chips; forming a first dielectric layer over a surface of the wafer; forming a first plurality of holes in the dielectric layer, the holes corresponding with the locations of contact pads on the surface of the wafer; depositing a first metal layer on a surface of the first dialectic layer; patterning the first metal layer to form traces, each of the traces extending from one of the first plurality of holes; depositing a second dielectric layer over the first dielectric layer and the first metal layer; forming a second plurality of holes in the second dielectric layer, each of the second plurality of holes corresponding with the location of at least one of the traces; depositing a second metal layer over the second dielectric layer, the second metal layer extending into the second plurality of holes; removing a portion of the second metal layer, leaving the second metal layer in the second plurality of holes; forming a first plurality of metal bumps in the second plurality of holes; depositing an encapsulant layer covering the first plurality of metal bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; forming a second plurality of bumps on the exposed portions of the first plurality of bumps; and separating the chips by sawing the wafer, the first and second dielectric layer and the encapsulant layer, thereby producing the semiconductor chip packages.
In another embodiment, wafer is sawed into sections each containing a plurality of chips after the first plurality of metal bumps has been formed. The method then includes depositing an encapsulant layer covering the first plurality of metal bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; forming a second plurality of bumps on the exposed portions of the first plurality of bumps; and separating the chips by sawing the segments, thereby producing the semiconductor chip packages.
In a different embodiment, the first plurality of metal bumps are directly deposited directly over the chip contact pad regions. As in the previous embodiments, the method then includes depositing an encapsulant layer covering the first plurality of metal bumps; removing a portion of the encapsulant layer so as to expose a portion of the bumps in the first plurality of bumps; forming a second plurality of bumps on the exposed portions of the first plurality of bumps; and separating the chips by sawing the segments, thereby producing the semiconductor chip packages. Alternatively, as described above, the wafer can be sawed into multi-chip sections after the deposition of the first metal bumps and before the encapsulation process.
The present invention provides a chip package which is compact, associated with low inductance, has good reliability and can be fabricated at a low cost.
These and other objects and advantages of the present invention will become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:
FIG. 1a is a side-sectional schematic view of an overmolded ball grid array package.
FIG. 1b is a side-sectional schematic of a compact BGA package.
FIG. 2 is a schematic representation of a silicon wafer 301 containing multiple integrated circuit chips 302 and scribe lines 303.
FIG. 3 is a enlarged plan view of IC chip 302 which shows the conventional peripherally distributed I/O contact pads 304.
FIG. 4 is a cross-sectional view showing the chip contact pads 304, first dielectric layer 305 and plurality of holes 306 in layer 305.
FIG. 5 is a cross-sectional view showing the chip contact pad re-distribution layers. Shown are first dielectric layer 305, metal re-distribution layer 307, and second dielectric layer 308, plurality of holes 309 in 308, and unpattemed Underball Metallization (UBM) layer 310.
FIG. 5a is a schematic side-sectional view with the first plurality of metal bumps 311-1 after deposition.
FIG. 6 is a schematic side-sectional view of wafer 301 and chip 302 with the first plurality of metal bumps 311 formed after reflow.
FIG. 7 is the plan view showing the area distributed first plurality of metal bumps 311 on 302.
FIGS. 8a to 8 f illustrate a process of fabricating a first embodiment according to the invention.
FIG. 8a shows wafer 301 deposited with metal bumps 311 after encapsulation layer 312.
FIG. 8b is a side-sectional schematic representation of chip 302 after encapsulation which shows the various embedded elements and the encapsulating layer 312.
FIG. 8c is a schematic side-sectional representation after exposing the top surface of metal bumps 311 and creating flat metal region 313.
FIG. 8d is a schematic side-sectional representation after formation of the second plurality of metal bumps 314.
FIG. 8e shows a plan view of wafer 301 after the formation of metal bumps 314 and sawing-off along the scribe lines 303 so as to obtain individual chip packages.
FIG. 8f is a view of a chip package showing the area distributed metal bumps 314.
FIG. 9a to 9 f correspond to a second embodiment according to the invention.
FIG. 9a shows wafer 301, containing plurality of first metal bumps 311, which has been sawed-off along scribe lines 316 so as to singulate sections 317 containing multiple chips.
FIG. 9b shows the sections 317 which are bonded on to a carrier frame 318.
FIG. 9c shows the encapsulated wafer sections 319 mounted on a carrier frame 318.
FIG. 9d shows wafer sections 319, after the exposure of the first plurality of metal bumps and the attachment of the second plurality of metal bumps 314-2.
FIG. 9e shows wafer section 319 after separation of the individual chip packages by sawing-off along the scribe lines 303-2.
FIG. 9f displays a chip package 315 with metal bumps 314-2.
FIGS. 10a to 10 h refers to the third preferred embodiment.
FIG. 10a shows a wafer 301 and a chip 302 with peripheral chip contact pads 304.
FIG. 10b shows the structure after deposition of UBM layer 321.
FIG. 10c shows the structure after deposition of first plurality of metal bumps 322.
FIG. 10d shows the structure after reflow of metal bumps 323.
FIG. 10e shows the structure after deposition of the encapsulation layer 324.
FIG. 10f shows the structure after the exposure of the metal bump regions by polishing, leading to flat metal regions 325.
FIG. 10g shows the structure after the formation of second plurality of metal bumps 326 over regions 325.
FIG. 10h shows the structure after separation of a chip package 327 which has metal bumps 326.
The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover equivalent, modifications, and alternatives, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore. in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
FIG. 2 is a top plan view of a wafer 301 which contains numerous integrated circuit (IC) chips 302. Adjacent chips are separated by borders 303 referred to as scribe lines. In the present embodiment, each IC chip contains the complete integrated circuit elements. At the top layer, the chip contains regions called contact pads whereby connections for the input and output signals from the chip can be made. As shown in FIG. 3, these input and output contact pad regions, referred to as chip contact pads, are usually distributed in a ring like structure along the periphery of the chip and are illustrated as 304. An integrated circuit (IC) contains a large number of devices which are derived from transistors. In order to provide more functionality from the chip, a larger number of such devices need to be incorporated. This is referred to as increasing the integration level of the integrated circuit. As the integration level of the IC chip increases so does the number of required I/O connections in accordance with relationship called Moore's law. Thus, a larger number of chip contact pads need to be accommodated along the periphery of the chip. Increasing the size of the chip in order to accommodate these large number of chip contact pads is not economically viable due to the fact that processed silicon area is very expensive. Thus, the trend has been towards decreasing the size as well as separation of the connection pads. However, closely spaced and small contact pads are difficult to connect to the external world. Therefore, approaches have been developed for redistributing these I/O pads on the entire surface of the chip by using redistribution layers. One embodiment of the present invention uses this general approach in a novel way.
Referring to FIG. 4. the redistribution step involves depositing a dielectric layer 305 on wafer 301. This could be done by means such as spin-coating, spray-coating, or extrusion-coating from a liquid solution or paste of the dielectric material. Alternatively, dielectric layer 305 could be formed by lamination using a dry film. Still another approach involves encapsulating the wafer 301 in epoxy resin using a transfer molding process. Next, clearance holes 306 are made in the dielectric layer 305 corresponding to the locations of chip contact pads 304 . This could be done by any of several established procedures. If the dielectric layer 305 is a photosensitive material such as the photosensitive polyimides, benzocyclobutenes (BCB), Novolac photoresists, photosensitive epoxy or similar materials, then the clearance holes 306 could be fabricated by well known lithographic techniques. If the dielectric layer 305 is not photosensitive, clearance holes 306 could be made by etching the film selectively over the I/O pad regions by using a mask. The etch mask is patterned so as to have clear holes over the chip contact pad regions. Examples of a non-photosensitive dielectric could be organic layers such as non-photosensitive polyimides, non-photosensitive epoxies, inorganic films such as silicon dioxide, silicon nitride, and a silicon oxynitride.
As shown in FIG. 5, next a metal layer is deposited which electrically connects to the chip contact pads 304, through the clearance holes 306 in the dielectric layer. For example this metal could be aluminum, chromium, nickel or a combination of metals or multiple metal layers. The metal layer is deposited using established techniques such as sputtering, evaporation, etc. The metal layer is patterned into fine traces 307 which electrically connect to the contact pads 304 and terminate in the central regions over the dielectric layer 305. One end of traces 307 overlaps the chip pads 304 whereas the other end traverses centrally on the dielectric layer 305 and terminates such that the terminal ends of traces 307 are distributed across the entire area on the top of the dielectric layer 305.
A second dielectric layer 308 is then deposited on top of dialectic layer 305. Layer 308 could be made of the same material as dielectric layer 305 or it could be made of a different material. Clearance holes 309 are made in the second dielectric layer 308 so as to expose terminal regions of the metal traces 307 which are distributed on the chip area. A second metal layer 310 is then deposited so that it electrically connects to the first metal traces 307 through the clearance holes 309 in the dielectric layer 308. The second metal layer 310 is referred to as the "under bump metallization" (UBM).
Next, as shown in FIG. 5a, metal in the form of bumps 311-1 are deposited over UBM layer 310 selectively. Bumps 311-1 fill-up the clearance holes 309 in the dielectric layer 308 and overlay the terminals of the metal traces 307 and form a first plurality of metal bumps. Metal bumps 311-1 make good electrical contact to the UBM layer 310. The thickness of metal bumps 311-1 is in the range of 25-200 microns. Once metal bumps 311-1 have been deposited, the portions of UBM layer 310 that are not covered by bumps 311-1 are removed by etching process. This etching is done in an etchant which etches UBM layer 310 and does not etch the metal used to form bumps 311-1 very aggressively. Preferentially, during the removal of UBM layer 310, not more than 5% (by thickness) of the metal bumps 311-1 is removed. Thus, the UBM layer 310 is left in place only underneath the metal bumps 308. The remaining portions of UBM layer 310 form a number of cup-shaped regions.
The UBM layer 310 is used to ensure good wettability and adhesion of the overlying metal bumps 311-1. Thus, the choice of the material for UMB layer 308 is dependent on the metal used for bumps 311-1.
Deposition of the metal bumps 311-1 can be done by several established techniques. These include electro and electroless plating, evaporation using a metal shadow mask, or printing of a metal paste through a stencil aperture. Alternatively, a wire bonder can be used for bonding metal studs via a process referred to as "wire bonder stud bumping", wherein the wire bonder is used to deposit a gold or solder stud bump. A detailed description of this process is contained in "Ball Bumping and Coining Operations for TAB and Flip Chip" by Lee Levine, Proc. Electronics Components and Technology Conference, 1997, pp 265-267 and references therein, which is incorporated herein by reference. Examples of bump materials are 90/10 Pb/Sn solder, 63/37 Pb/Sn eutectic, and electrolessly plated nickel. For electroplated solder bumps, UBM layer 310 could be configured from a combination of Cr and Cu layers. The Cr layer functions as an adhesion or glue layer whereas the Cu layer provides a electrolytic or electroless plating seed layer for the solder material. Alternately, these same layers can also be used for solder bump deposition by other processes.
If the bumps 311-1 are composed of a combination of different metals such as Pb/Sn solder and solder paste material wherein the solder particles are embedded in an organic binder matrix with other constituents, then wafer 301 with metal bumps 311-1 undergoes a reflow step next. This consists of heating wafer 301 to elevated temperatures in an inert environment. This reflow step causes intermixing of the constituent metals and the formation of alloys. The reflow step is also needed if the bump material consists of solder paste. For solder paste the reflow step volatilizes the organic binders and other constituents so as to give electrically conductive solder bumps. For low melting materials such as Pb/Sn solder, the reflow step may cause melting of the bumps as well. When the solder melts, the surface tension of the molten solder forms a partial spherical bump 311, as shown in FIG. 6. The base of bump 311 is determined by the width of the "cups" formed by the UBM layer 310, because the reflowed bump material such as molten solder adheres strongly to this layer. The temperature for this reflow step is determined by the composition of the bump material. For 90/10 Pb/Sn the temperature is above 300� Celsius, whereas for 63/37 Pb/Sn eutectic a much lower temperature below 250� Celsius could be employed. In some cases. reflow may not be necessary.
In the first preferred embodiment, after the deposition of metal bumps 311, forming the second layer of connection regions on wafer 301 (a process referred to as "bumping"), wafer 301 is encapsulated with a polymeric encapsulant layer 312, as shown in FIG. 8b. Various choices exist for the material of encapsulant layer 312. Encapsulant layer 312 could be formed from epoxy resin based mold compounds, pure epoxy resins, polyimides and other polymeric materials. In addition, encapsulating layer 312 could also be formed of inorganic materials such as silicon oxide, silicon nitride, etc. Encapsulation could be done by a number of established approaches such as transfer molding using epoxy resin based mold compounds, laminating with a dry film such as polyimide or other polymeric material, or coating from a liquid solution using techniques such as extrusion, curtain, meniscus, or spin coating. For inorganic encapsulants such as silicon oxide, one can employ coatings from liquid precursors of such films such that, after baking, inorganic oxides are formed, an example of which is the spin on glass class of materials.
Encapsulation of the wafer 301 via a transfer molding process using, epoxy resin based mold compounds uses a methodology similar to the conventional transfer molding process of integrated circuit chips. In this process, the wafer is bonded to a frame before it is transferred to the mold. This frame mechanically supports the wafer and also enables handling and automated transferring of the wafer to the mold press. The frame could be configured from conventional metal leadframe-like materials. The frame assembly with the wafer is placed in the cavity of a metal mold. Molding is done at elevated temperatures such as 175� Celsius at which the mold compound melts. The fluid mold compound is transferred to the mold cavity at under high pressure. The mold compound fills up the cavity and encapsulates the wafer. The mold compound is a thermoset material which cures and hardens subsequently. After the molding process, the encapsulated wafer is taken out from the mold. The mold could be designed so as to encapsulate only the front surface of the wafer, or alternatively it could be designed so as to encapsulate the entire wafer including the back surface.
In a different embodiment the wafer is encapsulated with a polymeric film using a lamination technique. The dry film is laminated to the wafer using an epoxy adhesive glue. The thickness of the lamination film is chosen such that the entire wafer with the metal bumps 311 is embedded in the laminate film. Preferably, the laminating film thickness is at least twice the thickness of the bumps 311. The lamination process is achieved by attaching the laminate film on to the wafer using an adhesive glue under application of pressure and heat. Either a single film or multiple films could be sequentially bonded. The lamination can be done either on the top active face of the wafer or on both the top and bottom faces. When both the faces are to be laminated, the top face is laminated first, preferably so as to protect it during the lamination of the bottom face. The polymeric film softens under heat and pressure and thus could be made to deform adequately and laminate satisfactorily to the bumped regions providing satisfactory encapsulation.
The wafer could also be encapsulated by applying a coating of a polymeric film from its liquid solution and then baking the coating dry. The coating could be done by using any of the various established approaches such as extrusion coating. As before, the front surface is encapsulated first before the back surface. Alternatively, the encapsulation could also be done using a spray-coating technique wherein liquid solution of the polymeric material is sprayed over the wafer and then heated at elevated temperatures to provide a dry encapsulating film. Still another approach is spin coating wherein a liquid solution of the polymeric material is dispensed on the wafer and the wafer is rotated at a high angular speed, which leads to an uniform coating of the layer. The thickness depends on both the viscosity of the polymeric solution as well as the rotational speed. The wafer is then heated at elevated temperatures so as to drive the solvent off, leaving behind the polymeric film. In general, spin coating is only applicable for thin films (<10 microns). Therefore, in order to build-up 50-100 micron thick coating, multiple coating and baking steps are normally required.
After the encapsulation step, the entire structure, including the metal bumps 311, is covered by the encapsulant layer 312, as shown in FIG. 8b. The next step consists of exposing the metal bump regions 311 by removing the portions of encapsulant layer 312 which cover bumps 311. In one embodiment, this is achieved by mechanically polishing the encapsulated wafer in a polishing wheel with a slurry such as alumina. This mechanical polishing step removes material in a planar manner. The polishing process is continued until a thickness of the encapsulant layer 312 which is slightly in excess of the thickness covering bumps 311 is removed. As shown in FIG. 8c, this results in the removal of some material from the top portions of the bumps 311, as well. This provides a flat bump region 313 for the next level of connections. At various stages of the polishing process, the polished face could be inspected for the appearance of the flat bump regions 313, which will have a different appearance from the encapsulant. Methodologies established in the area of chemical-mechanical polishing (CMP) could also be employed for a controlled process for exposure of the metal bump regions 313.
As noted above, the exposed bump regions 313 are flat, as shown as in FIG. 8c. Flat bump regions 313 are electrically connected to the chip contact pads of 304 . In order to provide external connectivity, a second plurality of metal bumps 314, shown in FIG. 8d, is deposited over these bump regions 313. Metal bumps 314 can be in the form of bumps or balls but are referred to herein as "bumps". In one embodiment, bumps 314 are formed from the selective deposition of solder from a paste over the flat bump regions 313. This is done by depositing the solder containing paste through a mechanical stencil mask which covers the entire wafer but has openings that register with the flat bump regions 313. Solder paste material is squeezed into these openings so as to deposit only over regions 311. A reflow process can then be performed. A detailed description of the process is contained in "Fine Pitch Stencil Printing of Sn/Pb and Lead Free Solders for Flip Chip Technology", J. Kloeser et al, Proc Electronic Components and Technology Conference, 1997, pp. 254-264, and "Stencil Printing Process For Low Cost Flip Chip Interconnect", by L. Li et al., Proc. Elec. Comp, and Tech. Conf., 1998, pp. 421-426, and references therein, which are incorporated herein by reference. In another embodiment, a metals could be deposited over the bump regions 311 selectively, using electroless plating techniques. This approach is suitable for depositing materials such as Ni. A description of the various methods for formation of metal bumps is contained in "Solder Bumping Methods for Flip Chip Packaging", G. A. Rinne, Proc. Electronics Components and Technology Conference, 1997, pp 241-247, which is incorporated herein by reference.
In yet another embodiment, small solder balls could be attached to the exposed to the flat bump regions 313 using established processes used in solder ball assembly in conventional ball grid array packages. In these processes, the polished wafer is coated with a flux and then solder balls are formed over the bump regions 313. The viscous flux holds the solder balls in place. The wafer is then heated in an oxygen-free environment to such temperatures at which the solder balls melt and fuse with the exposed metal connection regions This is referred to as reflow process. Due to its surface tension, the molten solder mass forms a partial spherical ball. A detailed description of solder ball based bumping is given in "Micro-ball Bump for Flip Chip Interconnections", K. Shimokawa et al, Proc. Electronics Components and Technology Conference, 1998, pp. 1472-1476, which is incorporated herein by reference.
Metal bumps 311 need to be selected from materials and compositions such that they have a higher melting temperature than the metal in the metal bumps 314. As an example, if both the metal bumps 311 and metal bumps 314 are made of solder, then 90/10 Pb/Sn solder can be chosen for the bumps 311. 90/10 Pb/Sn solder melts at above 300� Celsius. For metal bumps 314 a 63/37 Pb/Sn eutectic composition could be selected. 63/37 Pb/Sn eutectic composition melts below 275� Celsius. Therefore, during the reflow process, metal bumps 314 will melt and fuse to the flat bump regions 311, whereas bumps 311 will maintain their structural and electrical integrity.
In still other embodiments, metal bumps 314 are formed by a vacuum deposition system such as evaporation. In this method the wafer 301 with metal bumps 313 is covered with a mask. The mask has holes that register over flat metal regions 313. Metal films are deposited over regions 313. Individual layers of Pb and Sn can be deposited by metal evaporation, using RF energy or thermal heating. The respective thicknesses of the Pb and Sn layers are adjusted so as to give the desired alloy composition after a reflow process wherein the films intermix and form an alloy.
After the attachment of metal bumps 314, the encapsulated wafer 301 is sawed to yield individual chip packages. FIG. 8e illustrates a plan view of wafer 301 populated with the second layer of metal bumps which has been sawed along the scribe lines 303. After encapsulation, the surface of wafer 301 is covered with the encapsulant, and thus the scribe lines are not visible. However, since the scribe lines 303 separate adjacent IC dice, scribe lines 303 can easily be located at the midpoint between the outermost connection regions of two adjacent chips. FIG. 8f is a schematic representation of an individual package 315 with metal bumps 314 on the top face. Package 315 has the same lateral dimensions as the chip 302.
FIGS. 9a-9 e illustrate a process sequence for a second preferred embodiment of this invention. In the second preferred embodiment, after wafer 301 has been populated with bumps 311 (see FIG. 6), wafer 301 is sawed to provide sections 317, each containing multiple IC chips. FIG. 9a shows scribe lines 316 along which the wafer 301 is sawed. The number of chips in each section 317 can be large. Following an established methodology known in the IC industry, wafer 301 is mounted on a sticky tape prior to the sawing . Thus, after sawing, the separated multi chip containing sections 317 are retained on the tape. Next, sections 317 are picked-up and attached to a frame 318 using a methodology established in IC packaging. The frame 318 and the attached wafer sections 317 undergo an encapsulation step next. In this step, wafer section 317 and some regions of the frame 318 are encapsulated in a polymeric resin composition. The encapsulation step covers all sides of sections 317, yielding the encapsulated sections 319 shown in FIG. 9c. Alternatively, one could only encapsulate only the top face of section 317 containing metal bumps 311. In one embodiment, this encapsulation step can be done by using epoxy resin-based molding compounds in a transfer-molding process using established IC molding techniques. In another embodiment, this process can be done by dispensing polymeric resin paste over the top surface of segment and then baking the assembly so as to dry and cure the paste and completely encapsulate the top surface of the segment 317. Standard pneumatic controlled dispensers wherein the polymeric paste is dispensed through a nozzle orifice under pneumatic air pressure can be employed for this dispensing process. This dispensing step can be applied to encapsulate either one or both of the top and bottom surfaces of sections 317. When encapsulating both the surfaces, the top surface is encapsulated first and then the frame 318 is flipped over and the back surface of section 317 is encapsulated.
After the encapsulation step, metal bumps 311 on the encapsulated sections 319 are exposed by removing a portion of the encapsulant layer. This can be done by a method, such as mechanical polishing, as described in the first preferred embodiment, leading to exposed flat regions similar to regions 313 shown in FIG. 8c.
Next, another layer of connections is formed by attaching a plurality of metal bumps 314-2 over the flat regions by using the methodology described above in the first preferred embodiment. After the formation of metal bumps 314-2 (the second layer of I/O connection), the encapsulated sections 319 are separated from the rest of the frame using techniques established in the IC packaging area. Next, the separated sections 319 are sawed along the scribe lines 303-2 so as to give individual chip packages. FIG. 9e schematically illustrates the section 319 after it has been sawed-off along the scribe lines 303-2. As in the first embodiment, here too, the scribe lines 303-2 fall midway between the outermost rows of metal bumps of two adjacent chips. FIG. 9f shows the packaged chip 315 with the metal bumps 314-2 distributed on the top surface of the package.
In the first and second embodiments, the first plurality of metal bumps 311 is distributed in an area array on the surface of chip 302. Metal re-distribution traces 307 and UBM layer 310 connect these metal bumps 311 to the peripheral chip contact pads 304. In an alternative embodiment, a plurality of first metal bumps are deposited directly over the chip contact pads so as to retain the peripheral distribution. This embodiment is described in detail in FIGS. 10a to 10 h. The wafer 301 with chip 302 and contact pads 304 as shown in FIG. 10a, is deposited with UBM metal layer 321, as shown in FIG. 10b. The reasons for using UBM layer 321 are similar to those discussed in the earlier embodiments. Next, a plurality of first metal bumps 322 are deposited over the contact pads 304, as shown in FIG. 10c. Once again, as discussed earlier, several different approaches can be used for the deposition of the metal bumps 322. For example, in one embodiment, this is done by depositing solder paste by using a stencil mask, following the process which has been described earlier in the first and second embodiments. In another embodiment the metal bumps 322 can be deposited by electrolytic and electroless plating following a process as described earlier in the first and second embodiments. In still another embodiment, metal bumps 322 can be deposited using a wire bonder via a process as detailed earlier in the first and second embodiments.
As discussed above, bumps 322 will have different shapes depending on the process of their formation. As has been discussed in the preceding embodiments, for certain metal types such as Pb/Sn based solder, the metal bumps 322 are subjected to a reflow process after their deposition, producing the bumps 323 shown in FIG. 10d. As has been discussed earlier, the reflow step melts the bump metal and fuses it with the UBM layer 321, thus ensuring good electrical and mechanical contact. The bumps 323 also attain a partial spherical shape, as shown in FIG. 10d. Next, the portions of UBM layer 321 which are exposed and not covered by the bumps 323 are removed by etching .
Next, wafer 301 with metal bumps 323 is encapsulated, as shown in FIG. 10e. As discussed above, several different approaches exist for the encapsulation. These include transfer molding using epoxy resin based mold compounds, lamination of polymeric films using epoxy adhesive, or applying a polymeric coating from its liquid solution and then baking it dry using approaches such as nozzle dispension, spin coating, extrusion, curtain or meniscus coating. From the encapsulation step onwards, this embodiment has the same process sequences as has been described for the two earlier embodiments. As shown in FIG. 10f, the bumps 323 are exposed by removing portions of the encapsulating layer 324, using processes such as mechanical polishing. This produces the flat metal regions 325. As in the earlier embodiments, a second plurality of metal bumps 326, shown in FIG. 10g, are attached over flat metal regions 325 by the processes described above. Next, as in previous embodiments, the wafer 301 with second plurality of metal bumps 326 is scribed along the scribe line 303 so as to provide individual chip packages 327 which have a plurality of metal bumps 326 formed over the connection pads 304.
Alternatively, as described above, the wafer can be saved into multi-chip sections after the metal bumps 323 have been deposited, followed by the encapsulation step performed on the sections.
In the embodiments described above, the bumps in the first and second plurality of bumps are described as being formed of a metal or a combination of metals such as Pb/Sn. It should be understood, however, that the bumps can also be composed of non-metal materials that are electrically conductive. This includes polymers that are intrinsically electrically conductive, referred to as conductive polymers, as well as polymer paste filled with metal particles or flakes so as to become electrically conductive when dried. Thus the invention is not limited to the particular materials mentioned in the description of the preferred embodiments. Likewise, the metal traces described above can also be formed of a conductive, nonmetallic material.
In the foregoing discussion, the metal bumps have been shown as partial spherical or cylindrical geometry. But it should be understood that the bumps can have other shapes as well and that this invention will not be limited by the shapes shown in the preferred embodiments.
In the embodiments described above, the portion of the encapsulating layer over the first metal bumps is removed by using a method such as chemical-mechanical polishing. It should be understood that other methods for the removal of the encapsulating layer could also be used, such as laser ablation or wet or dry etching techniques.
The methodology described above offers several advantages. The process provides highly miniaturized chip packages which are the same size as the chip but are fully encapsulated. The assembly process uses conventional well-established proven methodology and equipment. This provides a truly low-cost volume manufacturable process because this involves simultaneous assembly of a large number of chips from a wafer. In contrast to the conventional approach which involves separation of each individual die from the wafer and then mounting it onto a carrier frame prior to encapsulation, the described methodology significantly reduces the number of processing steps, materials and thereby the cost and yield of assembly. The described methodology involves full encapsulation of the metal bumps deposited on the chip surface using materials well established in the field, such as epoxy molding compounds. This improves the reliability of the connection regions significantly. Mechanical polishing of the encapsulated wafer or wafer segments create a highly planar surface which is free from any warpage. This ensures high yields when the chips are connected to external substrates or circuitry.
Thus, the present invention provides methods whereby a large number of chips from a wafer can be assembled and encapsulated simultaneously and then sawed-off to provide chip packages which are of the same size as the chips. The present invention further provides a method which does not require the separation of each chip from a wafer and then mounting each chip on a dedicated region of a frame before encapsulation. The present invention also provides a package with low inductance. Additionally, the present invention provides a configuration whereby the bumped wafer metal connection regions are fully embedded in the encapsulant layer thereby significantly improving the reliability of the package.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby to enable others skilled in the art best to utilize the invention and various embodiments with various modifications suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
Patent Citations
Non-Patent Citations
Referenced by
Legal Events
Original Image


text:
Posted at: 07/12/2013 8:03 AM
Updated at: 07/12/2013 8:09 AM
Police have charged a teen with DWI after a crash Friday morning in Greece. It happened around 6:30 a.m. on 390 near Ridgeway Avenue in Greece.
State Police tell News10NBC the driver was out of control and hit another car, causing his vehicle to roll and catch fire. Police say four teenagers, two females and two males, were in that car. The girls were taken to Strong Memorial Hospital with head and neck injuries.
The driver's name has not been released but he is charged with DWI.
The driver of the other vehicle was not injured.

subset: commoncrawl


text:
A simple PowerPoint template – a yearly calendar for 2014. You can print it out onto a single page to use as a calendar.
It is great for kids as you can cut it up to make your own calendars.
If you liked this PowerPoint Template we would appreciate some feedback on how you will use it. Please leave your feedback in the box below.
28 October 2013 Template number 01006
Filed under Calendar Templates, Presentations , 2014
You can browse all of our PowerPoint templates or select them by category or colour or by tag.


text:
by Marsha Dubrow
"Shakespeare's Sisters: Voices of English and European Women Writers, 1500-1700", a fascinating exhibition at Washington's Folger Shakespeare Library, illuminates little-known early women writers -- from queens to prostitutes.
The writers include 15-year-old future Queen Elizabeth I; Queen Catharine Parr, Henry VIII's sixth and final wife; Shakespeare contemporary Elizabeth Cary, viscountess Falkland, whose play was similar to "Othello"; Lady Anne Clifford, whose 17th century diaries reveal her life-long struggles to gain her inheritance, somewhat like "Downton Abbey"; and kings' mistresses Hortense and Marie Mancini, the first women memoirists, whose works became international blockbusters. The free exhibit continues through May 20.
Continue reading this article>>
Marsha Dubrow writes the DC Art Travel column on examiner.com. Her arts and travel stories have run in National Geographic Traveler, Washington Post, Houston Chronicle, as well as World Footprints. She was a Correspondent for Life, People, Punch, and Reuters. Dubrow earned an M.F.A. in Writing and Literature at Bennington College, which published her book, Single Blessedness. Her essays and fiction appear in anthologies including When Last on the Mountain and Still Going Strong.


text:
Gardens For All™
Farmers' Markets are for Families
Your local farmers' market is a great place for kids to learn about food and how it's grown.
It's Here! Spring/Summer 2015 Catalog
Shop 30+ new products! 100% of proceeds support youth garden grants.
KidsGardening Celebrates 1000 Gardens
Celebrating our partnership with Gro1000 to install 1000 community gardens and green spaces.
Rein in Stormwater with a Rain Garden
Protect the environment by capturing storm water in a rain garden before it becomes polluting runoff.
Green Gardening Tips
Invite Good Guys into the Garden
Looking for help controlling pests in the garden? There is an army of tiny helpers eager to lend a hand…
Read more »


text:
GuidanceAnalysts are looking for a profit of 95c on revenue of $277.89M. The consensus range is 94c to 96c for EPS, and revenue of $275.5M to $278.7, according to First Call. The company recently reported its same store sales rose 10% in the quarter and said sales were $275.5M. Due to the positive SSS, the company raised its Q4 EPS estimate by 5c, to between 93c and 95c per share. Gymboree also sees 2007 EPS of $2.69 to $2.71 vs. First Call consensus of $2.65, sees Q1 SSS growth in the low single digits, sees Q1 EPS 73c to 75c vs. First Call consensus of 76c and sees 2008 EPS $3.00 to $3.05 vs. First Call consensus of $2.99.
CEO Matthew McCauley said in a statement that Gymboree continued to see strong customer response to its product assortments throughout the month of January.
Analyst ViewsOn March 5, S&P Equity Research analysts upgraded the Consumer Discretionary Sector to Market Weight from Underweight, reflecting the firm's belief that a a mild U.S. recession is now largely discounted into Consumer Discretionary sector valuations and profit outlook. A long period of under-performance has left the sector with what we see as an attractive P/E-to-growth profile. Wedbush, which has a Buy rating on shares, believes the company's business remains on track and maintains a $45 target price.
Source: Earnings Preview: Gymboree


text:
Pronunciation: /ˈmalθəs/
Definition of Malthus, Thomas Robert in English:
( 1766–1834), English economist and clergyman. In An Essay on the Principle of Population (1798) he argued that without the practice of 'moral restraint' the population tends to increase at a greater rate than its means of subsistence, resulting in the population checks of war, famine, and epidemic.
- 1
- Example sentences
- Pursuing a Malthusian chain of reasoning, Mill argued that the labouring class tended to deploy increased wealth not in enjoying higher per capita living standards, but in having more children.
- However, while rising food prices indicate a growing pressure of population on land, there is in fact little evidence of a progressive Malthusian crisis of productivity in European agriculture from the late sixteenth century.
- Adopting a pessimistic Malthusian perspective on the population problem, he argued that population would outstrip the productive capacities of the economy.
- 2
- Example sentences
- Concerning the anarchist's contention that George's advocacy of Ricardo's law of rent was an extension of Malthusianism, one can only repeat what George had often observed.
- In 1822, Alexander Hill Everett had published his New Ideas on Population with the avowed purpose of countering the influence of Malthusianism.
- These groups base themselves on the reactionary legacy of Malthusianism, which proclaims 'overpopulation' to be the source of man's problems.
Pronunciation: /malˈθjuːzɪən/adjective& noun
Pronunciation: /ˌmalˈθjuːzɪənɪz(ə)m/noun
Definition of Malthus, Thomas Robert in:
- US English dictionary
What do you find interesting about this word or phrase?
Comments that don't adhere to our Community Guidelines may be moderated or removed.
Get more from Oxford Dictionaries
Subscribe to remove adverts and access premium resources
= trending


text:
Main Content
Teen Tech Week 2015
Each March the library celebrates our teen patrons and technology with a special week of events in conjunction with YALSA, the YA branch of the American Library Association.
DeMotte Library is celebrating it with a Silly Selfies contest—teens in grades 6-12 are encouraged to submit a silly selfie. Winners will be announced March 16th.
Wheatfield Library is celebrating it with a Trivia Crack program on Tuesday, March 10th from 6-7pm, teens in grades 6-12—how well do you know your trivia?—refreshments will be served. Registration is required.
Wheatfield Library is also inviting teens in grades 6-12 to celebrate Teen Tech Week by entering the Wheatfield Library's Instagram photo contest! Just post a unique picture of yourself and your favorite book and post any time between March 1 and March 14, hashtag #TTW2015.
Rensselaer Library is celebrating the week by having a Photo Editing contest—teens in grades 6-12 are invited to edit a photo to make it look surreal or unbelievable. All entries will be posted in the Teen Room, winners will be announced on March 16th.
Rensselaer Library will also celebrate by inviting teens in grades 6-12 to create a Flip Book on March 9th from 4-5pm—all materials will be provided, and registration is required.
Teens are also invited to attend the Overdrive e-book class on Wednesday, March 11th at 6pm—learn how to download books to your device.


text:
A worker had been installing copper piping when he slipped from his ladder, witnesses said.
Residents, Community Board 10 and the Department of Transportation are at odds over the proposal.
A man was struck by a livery cab while crossing 125th Street at Adam Clayton Powell Boulevard.
The wife of a landlord once jailed for building violations claims her property was destroyed.
The DOT said it will begin making changes to Adam Clayton Powell Jr. Boulevard in August.
The parking garage at 121 West 125th St. is slated to also have cultural exhibition space.
The owner of Sherman's Barbecue needs investors to save the historic restaurant.
A fire in the basement of a high-rise at 230 W. 129th St. in Harlem began in the building's basement.
Three vendors were arrested last week, leaving many worried about how they will make a living.
A 28-year-old man was found with a gunshot wound to the head on Seventh Avenue and West 117th Street.
Harlem rib joint Sherman's Barbecue once served the Beatles. Now it needs $15,000 to remain open.
The new facility on West 147th Street gives the 35-year-old institute a permanent home.
The agency is considering left turn signals and concrete median extensions to slow traffic on the dangerous Adam Clayton Powell Jr. Boulevard.
NYCHA and HPD have issued a request for proposals for rehabilitating the 36 tenement buildings in the Randolph Houses.
Tirzah Brown says her new children's store "You, Me, 'N Dupri" is meant to bring "downtown uptown."
Get our daily New York City news and alerts!
Terms of Use |Privacy Policy
Thank you for signing up!
Would you like to sign up for additional newsletters?
Thank you for signing up for additional newsletters.


text:
Starting & Managing
Starting a Business
Managing a Business
Loans & Grants
Small Business Loans
Surety Bonds
SBIC Program
Other Financial Assistance
Getting Started
Contracting Support for Small Businesses
Understanding the Federal Marketplace
For Contracting Officials
- HUBZone
- Non-Manufacturer Waivers
- Report Fraud, Waste & Abuse
- Protests
- Small Business Goaling
- Federal Acquisition Regulations (FAR)
- Certificate of Competency Program
- Procurement Center Representatives
- Government Contracting Field Staff Directory
- Service Contract Inventory
- Partnership Agreements
- Goaling Program
- Interagency Task Force on Federal Contracting Opportunities for Small Businesses
Learning Center
Local Assistance
About SBA
What We Do
SBA Team
SBA Locations
SBA Newsroom
SBA Initiatives
- SBA Emerging Leaders Initiative
- Clusters Initiative
- 7(j) Management and Technical Assistance Services Program
- Small Business Teaming Pilot Program
- Small Business Jobs Act of 2010
- Startup America
- Council on Underserved Communities (CUC)
- Intermediary Lending Pilot
- Dealer Floor Plan Financing Program
- Greening SBA
- Small Business Saturday 2013
SBA Performance
Oversight & Advocacy
You are Here
How to get on GSA contractor List ? is there any Mentor help available in SCORE Houston Chapter
by abcofficesupply, Window Shopper
- Created: March 1, 2013, 7:17 pm
- Updated: March 4, 2013, 11:20 am
Can a small business get on the GSA CONTRACT .Is there any Mentor Help available From SCORE Houston Chapter . Thank you Jay ABC OFFICE SUPPLY KING RAGS & WIPING MATERIALS SUPPLY COMPANY
Please note that Community members may not include personally identifiable information, such as phone numbers, addresses, or email addresses, in posts. Please review our Community Best Practices for more information about how best to participate in our online discussions. Thank you.
‹ MOVED: Revised Form I-9 Relesed - Join the USCIS Nat Teleconference on Mon Mar 11 @ 2:00 PM Keith Gilabert, "Opportunities for small businesses" ›
JGabriel | Community Moderator | 3/4/2013 - 11:21 am
SBA has resource partners like SCORE, Women's Business Centers and Small Business Development Centers located across the country that provide free business counseling to individuals looking to start or expand a small business. Visit our local assistance guide to find your local SBA resource partners by entering your zip code.
SBA Community
- Community Home
- Discussion Boards
- Introduction
- Tell Us...
- Discuss Popular Topics
- Developer Resources
- Blogs
- Social Media


text:
Recently Received
—01. MHL Staff Jacket.
—02. Free & Easy June 2011.
—01. MHL Staff Jacket.
—01. Brown chromexcel leather.
These shoes seem to have a bit of a fall feeling about them, but that doesn't mean they can't be purchased right now. Leffot just received two new chukka boots from Alden, but my pick is the brown chromexcel version with a plantation crepe sole. I already own this version in a blucher, and they're great. Tough, easy to wear, durable – I feel like the sole gives them a nice casual, rugged appeal. I'd personally be interested in seeing this chukka in a suede version with the same sole as well.
—01. Mark Borthwick.
—02. Philip Watts.
Featuring contributions from the likes of Mark Borthwick, Jennilee Marigomen, Juan Ignacio Moralejo and Philip Watts, the first issue of this bi-annual plant-based publication is due to be released very soon, and looks well worth tracking down.
—01. Hard in the paint.
From the paper to the plates to the pigmentation, printing a publication is a pretty portly process. We've spent a significant amount of time at the printers in the last few years on press check, an interesting and enlightening experience that not too many people get to see. This time around we shot some footage and made this little behind the scenes video of the printing of Issue 04. Printed at Hemlock Printers in Vancouver, B.C., Canada.
—01. Available in apple green and blue.
"One of Nigel Cabourn's new styles for the spring is the Aircraft Jacket. Quick to become another classic, the aviation influence played a big role in this spring's collection. This is without doubt our favorite piece from his recent offering. Made in apple green cotton camebric, the light weight jacket is a great all-year round piece."
—01. Honey saddle.
—02. Leather grip tape.
Sadly the summer in Vancouver has not yet landed, not even really a good dose of spring either. I've been looking forward to riding my bike daily, but the consistent rain has put a damper to my warm weather dreams. Over the last fall/winter, I found a bike the I really like and have slowly been outfitting it with the pieces, including the matching honey saddle and grips - was there really another option?
—01. Double blues.
—02. A hat I could never wear.
Looking through the recent update of 45rpm's summer look book, there are a number of beautiful shots, nothing surprising. But this round I actually found that I liked more of the womens looks. The blues, patterns and simplicity were nice, and the garments aren't overly feminine, so I felt they were definitely worth a look.
—01. Han Kjobenhavn Sunglasses.
—02. Neighbour Rugby Crew.
—03. Yoshii Towel Polka Dot Face Towel.
—04. Drifter Day Pack.
Neighbour opened its doors a little over a month ago and has been very well received locally. For those of you not in Vancouver, the same interesting mix of items is now available online. These are a handful of my personal favourites, but if you follow the link below there's plenty more to choose from.
Subscribe to the Inventory newsletter and receive
exclusive shop news, announcements and updates.


text:
Ok, now before you jump all over me for the title or sign me up for a program, I don't mean you should start every day off with a Bloody Maria. However, when I am on vacation I love a refreshing and spicy drink in the morning. Add in that you get a whole serving of vegetables in my drink (plus more depending on how you garnish) and how can you go wrong.
Usually this vacation morning drink for me is a spicy Bloody Mary, but recently I was introduced how good tequila could turn my "standard" into a Bloody Maria, or as Pura Vida Tequila coined theirs, a Poncho Villa. I emphasized good tequila because if you get a "cheep" brand your drink will taste cheep, and in my opinion, gross!
Pura Vida graciously sent me three bottles of their fine tequila as well as a bottle of Poncho Villa mix. Pura Vida means pure life. Their tequila is triple distilled to achieve the purest and highest quality available. It is so good, some big celebrities have stepped up to back it including Billy Gibbons of ZZ Top
For the Bloody Maria, or Poncho Villa, you use the Pura Vida Reposado Tequila. This particular tequila was recently awarded the Beverage Industry News (BIN) Editor's Choice Award for 2013. Only 13 liquors in the entire industry receive this award annually!! It also took home gold in the Spirits of Mexico Festival in 2012 (this is known as the Academy Awards for Tequila) and won the Tequila.net's Best of the Best award in 2012!
You can learn more about Pura Vida by following them on Facebook, Twitter, and Pinterest.
So now that I have you salivating for this fine tequila, let me share with you the recipe!
- 1 oz Pura Vida Reposada
- 4 oz Pura Vida Bloody Mary Maria Mix
- Shake ingredients with ice.
- Strain into an ice-filled Collins glass
- Garnish with a celery stalk and lemon wheel.
I made mine slightly different. For me, with tequila must come salt so I ran the cut side of a lime around the rim of my glass and then dipped it in salt. I also like mine spicy so I forwent the traditional garnish and sliced a hot pepper. Eat the pepper at your own risk! I use it to stir up my drink and it adds the right amount of heat for me.
As always, please drink responsibly! Come back over the next few weeks for more great tequila recipes J


text:
AK_the_Twilight's's Gamespot Rank
AK_the_Twilight's Emblems
Top 100 Community Reviewers
Power and influence. Those who rank amongst this hallowed 100 greatly benefit those searching for critical information about games. These individuals' thoughtful, analytical reviews tend to be much more detailed and sophisticated than most of the so-called professional game reviews you could find elsewhere. Sure enough, the top 100 tend to be prolific writers and avid game players.
Tagger King
Tagger King Awarded to those who've exhaustively used the tagging system, enabling themselves and others to make it a whole lot easier to find certain content.
Public Access
Public Access For successfully posting a user video. You're on the air! Don't waste it!
Virtually There: E3 2008 Nintendo & Sony Conferences
Virtually There: E3 2008 Nintendo & Sony Conferences For tuning into GameSpot's E3 2008 live broadcast of both the Sony press conference and the Nintendo press conference on Tuesday, July 15.
Virtually There: E3 2008 GameSpot Show Future Outlaw
Hey Louie, the man is dry. Give him one on the house, OK? These special viewers caught all three days of GameSpot's live stage show at E3 2008. They braved the good and saw the best to be the straightest shooters around. This emblem is on the house.
Animal Crossing City Folk Live Gameplay Marathon
Tom Nook's Still a Crook! This faithful person joined us for our live gameplay marathon of Animal Crossing City Folk. We dug up fossils together, fished together, and delighted in all things Animal Crossing.
PoP-o-Matic Emblem
You're not my donkey Like a hand-drawn helper, these users reached out and helped the prince to have an audience for his big gameplay marathon debut.
Virtually There: E3 2009 Day 3
Humans have triumphed against robots, but it seems we are the greatest monsters of all. These users tuned in to Day 3 of GameSpot's E3 2009 coverage. They've seen their entire gaming future revealed before their eyes...but the long wait to play those games might drive them mad!
Readers' Choice 2009 Chooser
Participant in 2009 Readers' Choice Awards. "Sure, that game is good... FOR BABIES!" "That game sucks! It doesn't even have online capture the flag!" "Barbie Horse Adventure: Riding Camp just lost so much of the magic that made Barbie Horse Adventure great." And so on. These intrepid readers braved the chaos of the Readers' Choice process and let their opinions be heard above the cacophony of argumentative commenters. Congratulations, voters!
Game Developers Conference 2010
Virtually There: Game Developers Conference 2010. 'cause you were totally there, but not really. Emblem holders watched and discussed at least 1 of 4 GameSpot GDC shows.
Game Expert
Here to save the day! Game Experts are knowledgeable and skilled masters in at least one game and have proven this by unlocking at least 75% of the achievements available for it. If you've ever got a question, a Game Expert's usually a good person to ask.
100% Club Member
The best of the best of the best, sir! Unlocking every achievement available for a game is a task that only the most dedicated of players complete, and for that we salute you.
E3 2010 Microsoft Conference Attendee
I was there for Microsoft's E3 2010 press conference! No really, I was. I even saw it live, with the Kinects and the Halos, and I've got this sweet achievement to prove it!
E3 2010 Nintendo Conference Attendee
I was there for Nintendo's E3 2010 press conference! No really, I was. I even saw it live, with the 3DSs and the Metroids, and I've got this sweet achievement to prove it!
E3 2010 Sony Conference Attendee
I was there for Sony's E3 2010 press conference! No really, I was. I even saw it live, with the Moves and the Killzones, and I've got this sweet achievement to prove it!
E3 2010 Early Bird
Stays up late--sometimes! These GameSpot members tuned in to a live episode of Tonight on the Spot during E3 2010 to catch some of LA's nightlife.
E3 2010 Ballot Stuffer
Because voting once is never enough. These highly dedicated fans led their own successful grassroots campaign of one and voted in every single category of the Best of E3 2010 Awards.
Greatest Game Villain Bouncer
Because we can't just let anyone in. This user voted in the All Time Greatest Game Villain wild card round to help determine the final ten villains to join the battle royale.
PlayStation Move
The Now Playing Mover For watching and chatting during the live broadcast of GameSpot's Now Playing PlayStation 3 Move marathon weeks before it was released!
Mwahahaha! From the dark places at the back of your fridge creeps forth this monster! FrankenTOTS! Thought you'd grab a quick bite while gaming? Well this tater has gone bad. REAL bad. Snack away if you dare! Don't worry that red stuff all over him is probably ketchup. Probably.
E3 2011 Microsoft Conference Attendee
E3's just not the same without dudes getting chainsawed in half, amirite? I watched the Microsoft E3 2011 press conference during the week of E3, and am a better person for it.
E3 2011 Sony Conference Attendee
Demystifying rumors and speculation, one E3 at a time. I watched the Sony E3 2011 press conference during the week of E3, and am a better person for it.
E3 2011 Nintendo Conference Attendee
Another E3, another hardware announcement. I watched the Nintendo E3 2011 press conference during the week of E3, and am a better person for it.
E3 2011 LiveCam Warrior
Fear does not exist in this dojo. I watched an episode of the E3 2011 LiveCam Tour during the week of E3, because I'm the best around.
E3 2011 Stage Show Samurai
This achievement brought to you by alliteration! I watched an episode of GameSpot's Live E3 2011 Stage show during the week of E3 and secured my place amongst the samurai elite.
E3 2011 New Game Ninja
Hi, this achievement is all about ninjas, REAL NINJAS. This achievement is awesome. I followed a game announced at E3 2011 during the week of E3 and inherited REAL ULTIMATE POWER.
E3 2011 Game Gladiator - Bronze
Are you not entertained? I followed 5 games featured at E3 2011 during the week of E3, and have won the favor of the crowd.
Users with this emblem are totally in Sync with GameSpot.
Readers' Choice Chooser
Take that, not-democracy! This user took the system into their own hands by voting in at least one category in Best of 2011.
Readers' Choice Clairvoyant
It's just like in that one movie with Nicky Cage. This user voted for a game in a category in which that game also won the Readers' Choice award.
E3 2012 Microsoft Conference Attendee
This viewer saved up all their Ballmer Buxx to buy a new Windows-compatible PC so they could log onto Internet Explorer and watch the Microsoft press conference and bear witness to all the Better-With-Kinect titles coming to their Xbox Entertainment Systems in the upcoming future.
E3 2012 Sony Conference Attendee
This viewer knows that the PlayStation Move isn't dead, it's just gone to that special place in the sky where the SNES Super Scope and the Tony Hawk Ride skateboard live. So while this viewer waits for the Move to make its triumphant return to glory, they figured they'd tune in and see what sharp business slacks Kaz Hirai has added to his wardrobe this past year.
E3 2012 Ubisoft Conference Attendee
In Ubisoft's home of Paris, France, there's an expression that goes "Je ne sais quoi." This phrase literally translates to "Listen up, Tom Clancy, you'll either get in this time chamber and let us harvest your life essence for all eternity or you'll regret ever being born. Your call." Tom Clancy visited Paris once. Once.
E3 2012 EA Conference Attendee
This viewer took an hour out of their daily routine of sobbing uncontrollably over the lack of a Mirror's Edge sequel in order to watch the EA press conference and confirm that EA still isn't making a Mirror's Edge sequel. But, hey, at least there's a new Medal of Honor game. So there's that.
E3 2012 Safari Documentarian
The only thing better than being at E3 live and in person is taking direct control over a GameSpot employee lugging around a camera and a live-streaming backpack that weighs as much as a small house. This viewer helped guide our live floor cam, going from booth to booth documenting all the wonderful sights and sounds of E3 2012.
E3 2012 Literature Enthusiast - Day 1
Taking a break from watching YouTube videos of kittens playing with a ball of yarn, this viewer made the excellent decision to read the fine E3 coverage on GameSpot's official E3 site on day one of E3.
E3 2012 Literature Enthusiast - Day 3
Taking a break from watching YouTube videos of kittens playing with a ball of yarn, this viewer made the excellent decision to read the fine E3 coverage on GameSpot's official E3 site on day three of E3.
E3 2012 Literature Enthusiast - Day 2
Taking a break from watching YouTube videos of kittens playing with a ball of yarn, this viewer made the excellent decision to read the fine E3 coverage on GameSpot's official E3 site on day two of E3.
E3 2012 Literature Enthusiast - Day 4
Taking a break from watching YouTube videos of kittens playing with a ball of yarn, this viewer made the excellent decision to read the fine E3 coverage on GameSpot's official E3 site on day four of E3.
Hey look, it's a totally original dude wearing armor. With a huge gun and a helmet (a visor?). And he's riding a unicorn. This user was granted this magical emblem for not having any of their user profile images hosted on untrusted websites during The Great Purge of March 2013.
Will you be my player 2?
This emblem goes out to all those love birds who shared with us their favorite video game valentine, or simply stopped by to say Happy Valentines Day.
E3 2013 Microsoft Press Conference
Awarded to users who watched the Microsoft press conference during E3 2013.
E3 2013 Sony Press Conference
Awarded to users who watched the Sony press conference during E3 2013.


text:
Six Great Gifts for the Newly Ordained. (and five things to shy away from.)By
You can hardly go to a cathedral these days without running into an ordination. Every year in late May and through the month of June seminaries are letting out and bishops are laying on hands. That tough slog of seminary is done—six years at least, eight for some men, perhaps even more. By this point the men are eager to get out of seminary and get on with being a priest!
Truly one of the most joyous occasions in the Church because it means the sacraments will continue to be offered, that God is still with his people. No priest:, no sacraments. No sacraments: a very stunted life for the Church.
But there is no registry at Priests R' Us where the ordinands can let you know what sort of thing to get him so you might not know what to get a newly ordained priest. So I'll offer a few suggestions ranging in price from entirely free to rather spendy, and everywhere in between.
1) Prayer.
Few words are as appreciated by priests as, "I'm praying for you." Especially true right after ordination. The man has just been re-made in an irreversible way. He is now marked for service to God and His Church. He is now specially targeted by the devil for destruction because of the scandal his downfall would cause. He. Needs. Prayers. as he sets off on this new life.
No matter what else you give, prayers are a must. Tell him you are praying for him. Give him a tangible sign: a Mass card from your home parish. A spiritual bouquet from your kids, friends, family, yourself. A few words of prayer right on the spot. Whatever. But interceding on his behalf to the Almighty God to whom he is now configured in a special way is an inestimable gift.
2) A relic.
What says, "Congratulations on being ordained to the priesthood of Jesus Christ!," quite like a piece of the remains of a saint? The mortal remains of those who are already in heaven serve as a constant reminder of where we are supposed to be headed, that holiness is possible, and the the priest is supposed to lead us there and provide the spiritual nourishment for the way.
Bonus points if the relic is of a saint the ordained man already has a devotion to. It's like introducing someone to an old best friend they had only known through Facebook. Or, if it's a saint they had not had a devotion to, it's like introducing someone to an instant new best friend.
Relics are kinda hard to come by, not being the sort of thing you can (legitimately) pick up on eBay, so if you manage to get one to pass along the priest will treasure the gift and he, you, and all for whom he prays will reap great spiritual benefit in his ministry.
If you can't abscond with something like this…
Then at least something like this…
3) An icon or statue
Something with interest. Something beautiful. Something that means something. Something unique. Interesting sacred images of the Blessed Mother or of Our Lord. If the newly ordained has a devotion to a particular saint, one of those. He may already have the one you buy for him, or he may not. If he does, priests are (or at least ought to be) pretty good at re-gifting things to those who need them.
The value of a truly beautiful, meaningful statue is not that it will necessarily be an item of constant devotion, but that as it sits or hangs in that one place for so long, even as it mostly blends into the background as one of many sacred images, at least every now and then the priest's eyes will meet the eyes in the image, or fall upon the Sacred Heart, the Immaculate Heart, the gesture of Our Lady's hand pointing toward the Christ child she holds in her arms, the hand raised in blessing, or other aspect of the depiction of grace. And in that moment—because this is how God works—that will be exactly what the priest needed to see to meditate upon to bring him back to the Center and and restore his strength for the battles he is fighting.
In the East they don't have the tradition of Eucharistic Adoration, but they do consider icons to be a portal into the heavens, entering with your mind into the life of the saints and God's eternal salvific work. So if you know how to pray, this will provide a lifetime of contact with God and the Mother of God:
4) A Confession stole.
It's a small purple strip that can fold up and fit in the pocket, and it means so much. The stole hanging around the neck and in front of the chest is the vestment of the priest's office. It is the yoke he wears to carry the burden he bears. Priests generally should have more than one of these so that one can stay in the car, one in his office, one in his brief case, one in the sacristy, one in… well, you get the point. If a person asks for the sacrament of confession at any given point the priest ought to be able to pause, gather the moment into prayer, make the tangible action of putting on the stole to indicate that something is different, something is happening, something is important, and enter into the sacrament with the penitent. The stole indicates that the man who is a priest, is a priest, not just a man. It indicates that Jesus Christ is involved in the action through the ministry of His priest. It means Christ is present because His priest is present.
5) A book that would be good for homily preparation
The last vice really allowed to seminarians is books. Guys who were not into books before going to seminary develop at least a little bit of an obsession with books. When a seminarian gets in a shipment of books other seminarians gather and ogle, especially if he got them at a deep discount—or even free! Well, this guy who just got ordained was very recently a seminarian, so he's still into books. You can feed that healthy obsession with a book or three of saints meditating on the Gospels, Blessed John Henry Newman's Parochial and Plain Sermons, von Balthasar's Light of the Word: Brief Reflections on the Sunday Readings, or splurge and get him something within the Logos Bible Software world. Logos combines and connects all Scripture, writings of the Fathers, magisterial documents, the Catechism, and so much more. One friend of mine has 800 books in his Logos setup, and it is slick—you choose a Bible verse and it automatically indicates all places in the Catechism and other Church writings, including the works of the Fathers, where that verse is referenced.
Anything that will assist the priest in preparing great homilies will be a boon to his flock, and the meditations already offered by the holy men and women of the past—those meditations that have stood the test of time—help a whole lot.
6) Portable Mass kit.
What is a priest there to do? Lots of things: teach the faith, comfort the afflicted, lead us to Christ, but ultimately and primarily, offer the sacraments. The Mass, the Eucharist, is the "source and summit," as Vatican II tells us. The goodness and grace that comes from each and every single Mass is more powerful than all the evil in all the history of the world. The priest is made to offer the sacraments, especially the Mass. The ability to say Mass anywhere, even the hotel room while traveling, means a day doesn't go by that the priest cannot offer the Holy Sacrifice.
One of my favorite lines in the Divine Liturgy of St. John Chrysostom comes shortly after the consecration. The priest raises the paten and chalice with the Sacred Species and prays to the Father, "We offer to you yours of your own, on behalf of all and for all." Just so. The priest, at every single Mass, is offering to the Father, in the presence of all the angels and saints, on behalf of the entire created order and all time, the spotless Lamb of God. The lack of implements ought never to be a reason the priest cannot do this daily.
And Five Things to Shy Away From
In the off chance you are able to afford one, do NOT get him a chalice: that's the privileged customary gift of the ordained man's family.
Shy away from vestments unless you are really, really close to the ordained and you know what style of vestments he prefers. Even then, if you are so moved, coordinate this sort of thing with the man to be sure. The only major exception to this is a tasteful set of rose-colored vestments. They're only worn twice a year, but you can bet he'll never forget who got him his tasteful rose colored vestments. (With a maniple. If you don't get a maniple, don't bother.)
And unless it is a super special sort of thing with deep meaning or historical, familial, or personal value, he almost definitely does not need another crucifix or rosary, so be judicious with those gifts.
So there you have it. Not a perfect list, and if you get something he already has he'll likely re-gift it to another priest who doesn't have it so it's still a win.
Categories:Culture Liturgy Prayer Uncategorized Vocations
22 thoughts on "Six Great Gifts for the Newly Ordained. (and five things to shy away from.)"
Dear Tom,
Although your article is written with very good intentions, I don't think such an article should be written by a lay person. I think a priest is, first and foremost, a human-being too (and I think all of them would humbly agree.) It just seems more appropriate to ask the soon-to-be priest (or his family or close friends) what he would like than to assume idealistically what he needs…
Everyone needs prayers, anyone could use relics of Saints that contain their powerful intercession. Sure: a confessional stole or preaching book would be nice, but then, he's going to have repeated gifts (and probably feel even more pressured about preaching well, which the seminary should have taught him to be already pressured about!)
My point: I don't think any of us should deny the practical and human needs of a priest too! Sometimes something monetary could be extremely helpful. The best bet: ask family or friends of the priest, or even the priest himself!
Grace builds on nature. And a priest is as human as you and me too.
Thanks for reading.
In Christ,
How about a pyx?
We got an ordinand a beautiful pyx for about $50 … some engraving for $25 … a lot less than chausbles, which we saw in the same shop for $1500.00 plus …
I have a question about rosaries as a gift. I make very special completely wire wrapped 15 and 20 decade rosaries out of swarovski crystal pearls and crystals. They are beautiful, and they are almost unbreakable. I gave one to my pastor, who just loves it. Would a new priest appreciate something like that–or would they be re-gifted?
I would add that if you choose to get rose vestments for a priest, please make sure that they are actually *rose* (as in the photo) and not cotton-candy pink. I once knew a priest who hated to wear his rose vestments (thought he dutifully did, on the two prescribed occasions) because he thought that they made him look like a piece of bubble gum.
My favorite ordination gift was one that one friend (then a deacon, just recently ordained last week Friday!) gave to another friend (ordained last year)…a bug out bag. Fully stocked with emergency supplies, camping tools and more in the case of an impending zombie attack or other 'Doomsday Preppers'-type of situation.
These young men (and so many others!) are prayerful and hilarious. We have much to look forward to in our Church and nation!
Tom: Thank You! And I look forward to seeing you in Atlanta at our Ordinations next weekend! Pray for us!


text:
Art of Li Lan
A World Achieved
written by Carter Ratcliff
Hudson Hills Press | ISBN 9781555953812
Hardback – 192 pages
Member's price: $72.00
Usually ships within 2–11 business days.
Painting in oil on linen, and pastel and watercolour on handmade paper, artist Li-lan portrays birds and airplanes in flight, insects and animals, the occasional figure, and architectural imagery from places she has visited as well as those only seen in photographs. Her oeuvre began in the early 1960s and was comprised of still lifes and bright, detailed, and full figures. Over the years she has found her domain, transitioning through various subjects, while staying true to her independent spirit. Li-lan's detailed and imaginative subjects provide thought-provoking compositions. Author and art critic Carter Ratcliff summarises his prologue with these beckoning comments: 'There is no one right way to understand Li-lan's art. It is up to each of us to find interpretations that feel satisfactory. The richer my interpretation of Li-lan's art, the stronger is my sense of myself as an interpreter, as one sensibility communicating with another...It depends, rather, on my willingness to be open to the extraordinary potential of Li-lan's imagery.'


text:
Warning: file_get_contents() [function.file-get-contents]: Couldn't resolve host name in /home/cosplayl/public_html/cont/FrontControl.php on line 2167
Warning: file_get_contents(http://rss.api.ebay.com/ws/rssapi?FeedName=SearchResults&siteId=203&language=en-IN&output=RSS20&sacat=0&ftrt=1&fbd=1&sabdlo=&sabdhi=&saprclo=&saprchi=&floc=1&saslop=1&fsop=1&fsoo=1&from=R6&fss=1&sasl=&sacur=0&afepn=5335848900&customid=Choji%2BAccessories&saslc=0&fcl=3&saaff=afepn&catref=C5&frpp=100&satitle=Choji+-%28cosplay%2Coil%29%2B+&ftrv=1&fts=&salic=95&sascs=0&fspt=0&fpos=&sadis=25&frts=0) [function.file-get-contents]: failed to open stream: operation failed in /home/cosplayl/public_html/cont/FrontControl.php on line 2167
Choji Cosplay Accessories
Looking for some cool stuff with Choji's face on it? You've found the right place!
No products matching your query have been found in our store at the moment.
Please bookmark this page and come back soon to see if we have what you want.
You may also like to select one of the alternative country flags at the top of the page to show similar items available to you from other eBay stores.
Subscribe to our RSS feed for related items to get them delivered straight to your email address or RSS reader by clicking the orange RSS icon to the left of this message.
What is RSS?
View more Choji Accessories items on eBay
Or subscribe to our RSS feed for Choji Accessories items.
Or subscribe to our RSS feed for Choji Accessories items.
|High Quality Comstom Plastic Cell Phone Case For iPhone 6 [Choji Akimichi For Naruto]
See Listing for $...
|Ideal DanRobertse Case Cover For Iphone 4/4s(naruto: Shippuden Shikamaru Nara Anime Manga Rock Lee H
See Listing for $...
|High Quality Custom Plastic Cell Phone Case For Apple iphone 6 With Choji Akimichi From Naruto(Black
See Listing for $...