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P.S. Is it just me or does Jones look like the cartoon character man from BeBe's kids?
Nice picture of them, but I have just one question: When did Bobby Brown become Jones' lawyer?
If God can help him now, then that means God was the one who made him do it in the first place.
Stay Stupid but stay silent
JP=400,00 + population and avgs 30-40 murders per year before Katrina and now still only have 30 in 6 months.
NOLA=280-300,00 population avgs 200-400 murders per year.
Both parishes sit next to each other, yet there is a HUGE disparity in murders.
Why is that? Well al know why.
There is a difference b/w expectation of privacy aka defamation suits and the 4th amendment aka illegal search and seizure.
This guy could have a civil suit against best buy and his lawyer will most likely motion for a illegal search and seizure under the 4th pertaining to his criminal trial.
Let me get this one correct.
1.Nagin denies the public law to turn over emails requested by Lee.
2. Then he tells the judge that the emails were deleted.
3. Then Nagin tells the media that "He doesn't know what the big fuss is about BECAUSE HE HAS RECOVERED ALL OF THE EMAILS.
4. Yet, none of them are recovered (I don't know why he lied AGAIN).
5. So then Nagin hires LTC to recovered lost emails that Nagin said were already recovered.
6. LTC does their work and finds it odd that everyone's emails are there EXCEPT Nagins and that in order to delete Nagin's email in the manner that they were deleted, it had to be done purposely.
7. So LTC tells City Hall this finding and that they will be telling the media about their findings in a few days and if City Hall doesn't protest the media session, LTC will go through with it.
8. City Hall does nothing and LTC tells us this great info and then suddenly Nagin tries to throw LTC under the bus. Nagin doesn't take responsibility again.
9. Now, City Hall claims that the work LTC did was incompetent and that their findings are false. How can Nagin dispute findings when they have no idea about the work being done? That's like me hiring a Physicist and then telling the Physicist his work is wrong. I know a little bit about physics but not enough to even know whether his work is correct or not.
You have to be skilled or knowledgeable of a particular craft before you can criticize it.
I can't believe people still defend Nagin. The guy is more corrupt than Dollar Bill. I have NEVER seen a leader pass the blame on someone else as much as Nagin does. In fact, I can't remember a single time Nagin actually took responsibility for anything.
Nice article right up until you Mentioned the Blazers. You said the Blazers ALMOST signed someone. Well, correct me if I am wrong but if the Blazers almost signed someone, which means they didn't sign anyone, then aren't they the same as the Hornets? Why even mention them?
I agree, Shinn seems like the Clippers owner. Then again, I think the NBA should do away with the Luxury tax. Just make it so that you can't go over the cap and just raise the cap.
If Bill Gates decides he likes Basketball and buys a team, he could afford to pay anything for a great team. So basically, the more money one owner has the more likely they can put together a great team ( in theory).
Nice article right up until you Mentioned the Blazers. You said the Blazers ALMOST signed someone. Well, correct me if I am wrong but if the Blazers almost signed someone, which means they didn't sign anyone, then aren't they the same as the Hornets? Why even mention them?
I agree, Shinn seems like the Clippers owner. Then again, I think the NBA should do away with the Luxury tax. Just make it so that you can't go over the cap and just raise the cap.
If Bill Gates decides he likes Basketball and buys a team, he could afford to pay anything for a great team. So basically, the more money one owner has the more likely they can put together a great team ( in theory).
She is right about living in an uneducated and welfare city. The chocolate city residents are mostly uneducated and they do whatever the ministers tell them to do, and in most cases it is actually against the citizens best interest. However, they aren't intelligent or educated enough to grasp that fact.
"The greatest argument against democracy is a 5 minute conversation with the average voter."--Churchill.
Until NOLA starts bringing in professionals and people who want to learn, work, and raise their children properly it will always be a toilet bowl. The avg voters will always keep it that way.
Great news, I knew Thronton could create his own shot from watching his games at LSU. I never saw someone hustle so much as he did at LSU. I like that in a player, and now that him and Collison are coming around the Hornets look better than previously. Maybe good competition from Thronton and Collison will make them both better and thus make the Hornets better.
They are kind of reminding me of the twins from Slapshot. They both are rookies and they both play basically the same position and both play basically the same style.
Now, if Wright can learn to play team basketball then the Hornets just went from being not so athletic to extremely athletic. With Cp3, Wright, Collison, Thronton, and Chandler (if he gets back to his healthy self and not traded of course)
So the Gov. should just never indict and go to trial with anyone who breaks the law? What exactly do you consider a good case? If they were all easy cases, then we wouldn't even need a justice system, lawyers, jurors, judges, or anyone else.
To me this case is as easy as it gets. Dollar Bill caught "cold" with his hand in the "Pilsbury" cookie dough.
I have some advice for you. Stay stupid but stay silent.
Seriously? This hospital mess is going to far. What do the residents want? Do they want NOLA to be worst than it already is?
This reminds me of when Lafayette Gov decided to enter the internet, cable, and phone game and they were implementing Fiber Optic to the homes, which would be 1/3 the cost of Bell South and Cox and speeds 50 times faster than Cox's fastest speed.
Cox obviously hated the idea and suddenly many "private" individuals filed suit against Lafayette gov to prevent them from going through with the business. In the end Lafayette gov did go through and the new fiber optic has already started to be available in some areas and will be available to all by 2011.
Imagine paying the a 1/3 of the cost Cox ask and having speeds 50 times faster than 10 or 20 Mbps.
My point is the bums are trying anything to prevent New Orleans from being self-sufficient and being a professional city.
It disgust me.
She was really good in College. I didn't know they still had the WNBA. Next, you are going to tell me there is still an NHL
Wow, I didn't see THETRUTHISIT, or GentillyMIke post a single comment.
I guess they are brainstorming a way to make it seem like Reily is actually very competent and doing a stupendous job.
What does Obama being in Ghana have to do with New Orleans? Wasn't Bush in office for more of Nagin's term as Mayor than Obama? I don't blame Bush for Nagin and New Orleans chocolate city residents, so why blame Obama?
Obama probably dislikes Nagin as much as everyone else in NOLA who don't have ties to the ministers or city hall.
Someone must of stepped on someone else's new pair of Jordan's.
Either that, or someone beez eyein my big, long, fake, bling chain, ya heard.
Was the perp driving an old grand Am worth 2,000 but had 1,500 dollars worth of Rims and a 1,000 dollar paint job to make it look like a snicker's wrapper?
I see your point, but your theory has way too many "ifs" in it to be plausible. IF you have two people living in same house, IF one gets that raise, IF one can find a second job.
As for the welfare issue, many people think getting housing assistance is welfare, it is not.
Welfare is a different program than food stamps and housing assistance. Also, the true welfare is capped. One can only receive it for a certain number of months then not allowed to receive it. PLus, many of those criteria that people list are actually already in place for true welfare recipients. The other criteria would have a hard time getting in place because of the little paper called the Constitution.
There needs to be some serious awakening in the black communities. It only takes one parent to start the snowball action. Teach them NOT to have sex until married or out of college. Teach them that making it on your own means EVERYTHING, no matter what the job title may be. Teach them being smart is WAY COOLER than speaking English improperly.
They need to go into these neighborhoods and give out condoms like the Jehovah Witness give out God Pamphlets. All day, every day.
I believe if one parent does it then another will and so on.
TP is starting to delete ANYTHING that is not positive it seems lately or places some colors in a bad light, even if you are just stating the facts. Like living in North Korea.
We don't need the disabled and elderly to come back here, we need young professionals. PLus, why would anyone want the disabled and elderly back in NOLA when we don't have the resources they need? They are better where they are, because any place is better than NOLA.
I bet there are still people getting rental assistance from Katrina almost 5 years and counting.....tic....tic.......


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This is a rule: If you build an aircraft, you have a solemn duty to give it a cool name.For several years, Honeywell has disobeyed this rule, producing a ducted-fan unmanned aircraft named, drearily, the Micro Air Vehicle (MAV). [Insert wrong answer buzzer sound here.] Sorry, that's not a name. That's a category.Honeywell today has […]
Tag Archives | UAV
Finally … Honeywell names the MAV
Underwater sub's trash tube can also launch UAVs
Raytheon announced today that they will demonstrate launching a UAV from an underwater submarine. When I called the company to ask, "How?", they sent me this very helpful graphic. The full explanation is on the jump, but basically the UAV goes out the trash tube in a canister, floats to the surface and launches. The […]
A STUAS/Tier II RFP as a stocking-stuffer?
While we wait for the CSAR-X solicitation process to move forward, here's an update on the much-anticipated (read: extremely delayed) STUAS/Tier II competition from Michel Merluzeau's G2 Solutions blog. Industry sources are hopeful that the Department of the Navycould solidify its Small Tactical Unmanned Aircraft System/Tier IIUnmanned Aircraft System (STUAS/Tier II UAS) program by Christmas. […]
Navy unveils first official glimpse of FA-XX strategy
My colleague Rob Coppinger (see Hyperbola) attended last week's AUVSI North America show in San Diego, and kindly forwarded me these pictures. The slides show the USN's strategy on the only recently emerging F/A-XX competition, which appears to pit the Northrop Grumman X-47 against a future aircraft vaguely resembling a blend between the Lockheed Martin […]
STUAS/Tier II: What a real competition looks like
Twenty-five years ago, the US Air Force wanted to design a new aircraft called the "advanced tactical fighter". No fewer than seven companies — Boeing, General Dynamics, Grumman, Lockheed, McDonnell Douglas, Northrop and Rockwell — answered the USAF's initial call for bids with serious proposals. (Rockwell's rejected concept for what became the F-22 is pictured […]
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Diamond Lace Detail Top
Style # 233061
AVAILABILITY: Unavailable for immediate shipment.
Have an incredible night out! Our ultra fitted cutout top is textured and features a cutout neckline and full sleeves. You'll simply love the way the fit caresses your curvature.
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- Center back to hem: 17" (43 cm)
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Find a Sheltie available near you!
Sheltie Adoption
What do you need to know before you adopt a Sheltie? We asked the experts!
Northern Virginia Sheltie Rescue says:
The Shetland Sheepdog – Sheltie for short – comes from the harsh environment of the Shetland Islands, where they were bred as shepherds' helpers. They are herders, which means they prefer for everyone to be in the same place at the same time. Smart, alert, beautiful (need lots of grooming), loyal, and athletic are some adjectives that describe Shelties. Because they are "always on duty," they can be barkers. They attach closely to their humans and usually to the other dogs in the household, although some prefer to be the only dogs in the home. Some Shelties love young children; others, not so much, so careful placement is very important. Because they are smart and agile, they excel at dog activities like agility, disk dog, rally, and they love to learn tricks. They need lots of exercise and challenges for their physical and mental abilities. In rescue, we look for adopters who can understand all this about Shelties and are not drawn to them just because they're beautiful.
Minnesota Sheltie Rescue says:
Shelties are wonderful, smart, funny and comedic little dogs, but if there was one thing we would want a new Sheltie owner to know it would be how to keep them safe. This breed is a high flight risk when startled or scared. Knowing how to keep them safe so they don't become lost is key. Among the things we would recommend are:
- Use a martingale collar vs. a regular buckle collar (Shelties have larger necks than heads which means they can pull out of a regular collar very easily when frightened.)
- Always keep your Sheltie on a leash when out and about.
- Guard home entrances and exits. Consider putting up a baby gate to prevent a Sheltie from escaping, especially when guests are coming and going.
- Make sure all gates and fence lines are free of holes or gaps.
- Take lots of pictures of your Sheltie so if they do become lost you have plenty of pictures to use for fliers.
Long Island Shetland Sheepdog Rescue, Inc. says:
The Sheltie is a beautiful, intelligent, friendly, loyal, affectionate, and gentle dog breed. They are family-oriented dogs, making them very loyal to their human pack. Typically standing at 13 to 16 inches tall and weighing 15 to 23 pounds, Shelties are a small to medium dog breed with a moderate need for exercise. Unlike some herding dogs, they do not need to run around all day. They are perfectly happy living in a city apartment or a country residence - as long as you are there to give them attention.
The Shetland Sheepdog is extremely bright, sensitive and willing to please. This combination makes for a dog that is very obedient, quick to learn and utterly devoted to his family. He is not only gentle, playful, good-natured and companionable, but also excellent with children, although he can nip at heels in play while "herding," an instinctive behavior. He barks a lot. Shelties need "mental exercise" as well. These intelligent dogs cannot just sit in the backyard and do nothing. To be happy and well behaved, they require mental stimulation, too, such as obedience training, agility, herding, or challenging games you play with them, even if it's just fetching balls and finding hidden toys.
A Sheltie may be the right dog for you if you want a pet who:
· Is conveniently-sized, light on his feet, and graceful
· Has a lovely feathered coat in a variety of striking colors
· Is athletic and animated, a speedy light-footed runner and jumper
· Has a "soft" personality … sweet, gentle, sensitive
· Is peaceful with strangers and other animals
· Is bright and attentive and learns very quickly
Shelties have a beautiful striking appearance and great athleticism to match. Once you have had a Sheltie in your life, it is unlikely that you will ever want to own a different breed.


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Thursday, November 28, 2013
Christensen, Harry C.
Lt. Col. Harry C. Christensen, U.S.A.F.-Retired, 92, Bradenton, Fl., formerly of Summerville, SC, died Nov. 24, 2013. Visitation and services were held on Wed. Nov. 27, 2013 in Bradenton, Fla. For complete obituary notice or to send a message to the family please visit www.shannonfuneralhomes.com.
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By Tim HippsSpecial to American Forces Press Service
ALEXANDRIA, Va., Aug. 5, 2005 The first round of "Military Idol" competition began this week on U.S. Army installations around the world.
The program, based on Fox Television's "American Idol" series, will select the inaugural Military Idol after a final week of singing competition Oct. 17 through 23 at Fort Gordon, Ga.
To reach the finals, military vocalists must first win a competition on one of 36 installations. Depending on the number of local competitors, that process could take from one to eight weeks, competition officials said.
The Military Idol program is the brainchild of Coleen Amstein, who works in business programs for the U.S. Army Community and Family Support Center, and Victor Hurtado, artistic director for the U.S. Army Soldier Show, one of several programs offered by Army Entertainment Division.
"I had been working with the ('American Idol') folks for a while, and in the back of my mind I had wondered how we could put something together for our soldiers," Hurtado said. "I got an e-mail ... from Coleen Amstein asking what I thought about doing an Idol promotion and asking if I could help. She had no idea about my connections with 'Idol.'"
While visions of Soldier Idols were forming in Hurtado's head, Amstein and the CFSC business programs team were brainstorming events for Morale, Welfare and Recreation facilities.
"We thought: 'Wouldn't it be great if we could bring something like 'American Idol' into our clubs?' Amstein said. "But we didn't really have the talent or the connections to do something like that."
She sent an e-mail to Hurtado, who contacted officials at FremantleMedia, which holds the rights to "American Idol."
"The concept of what we could do was the easy part," Amstein said. "The reality of the execution was certainly much more difficult than what we had expected."
A licensing agreement was contracted with FremantleMedia, and the idea evolved into a program within a year.
"It was a matter of working with legal and business affairs, making sure that 'Idol' leadership and the legal arm agreed that we could go forward and do 'Military Idol,'" Hurtado said. "My role in this has been to make sure that the soldiers and the Army got the most out of this project."
During the first round of "Military Idol" installation-level competition, contestants must sing without musical accompaniment. Three judges, who may include garrison commanders, command sergeants major and local celebrities, will narrow the field of talent.
In the second round of local competition, judges and audiences will determine who advances. Spectators will submit written ballots after the performers are finished and judges have completed their critiques. The audience vote and judges' vote each will count 50 percent in determining who advances.
During the local semifinal and final rounds, judges will critique each performance but will not vote, leaving determination of the installation winners to the audiences.
When entering the venue, everyone will receive a ballot to vote once. An additional ballot can be obtained with each purchase of an appetizer or meal during the event. The number of local rounds of competition - not to exceed eight weeks - will be determined by the installation's MWR director based on the number of contestants.
Installation-level prizes for the winner at each participating location include $500 and temporary duty costs covered by USACFSC to compete in the Armywide finals. The winning vocalist's unit also will receive $500. Second-place contestants will receive $250, and third-place performers will receive $100.
Army wide finals prizes include $1,000 to the winner, who Hurtado hopes will become an ambassador for Army entertainment. "If they can represent the Army in a positive way with something that's exceptional, it just reflects on the Army as a whole," he said.
During the finals, which are scheduled for a live, 90-minute telecast on the Pentagon Channel, the runner-up will receive $500 and the third-place performer will receive $250.
Complete rules of the contest are available at the competition's Web site.
(Tim Hipps is assigned to U.S. Army Community and Family Support Center public affairs.)


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What causes a cough?
A cough has many causes, the most common of which is an upper airway infection, such as a common cold. A persistent cough can be due to whooping cough (pertussis) or a sign of a chronic lung condition, such as emphysema or asthma. Some individuals taking angiotensin-converting enzyme inhibitors (ACE inhibitors) experience a persistent dry cough, which ceases with drug discontinuation. Whooping cough is uncommon in infants due to vaccination, but it is surprisingly common in adults because the vaccination becomes less effective over time.
Very serious and life-threatening conditions that cause coughing include congestive heart failure, pulmonary edema, and lung cancer. Other possible causes include allergies, pneumonia, and bronchitis. Because there are so many different possibilities, some of which are life threatening, it is important to contact your doctor to discuss your symptoms and answer your questions.
Infectious causes of cough
Cough is a symptom of various viral and bacterial infections including:
Acute bronchitis
Common cold (viral respiratory infection)
Croup (viral illness that is common in young children)
Influenza (flu)
Tuberculosis (serious infection affecting the lungs and other organs)
Whooping cough (pertussis)
Other causes of cough
Other causes of cough include:
Acid reflux or gastroesophageal reflux disease (GERD)
Airway irritation such as from air pollution
Asthma and allergies
Chronic obstructive pulmonary disease (COPD, includes emphysema and chronic bronchitis)
Congestive heart failure (deterioration of the heart's ability to pump blood)
Foreign body (airway obstruction)
Lung cancer
- Postinfectious cough
Postnasal drip from sinusitis or upper respiratory infection such as the common cold
Pulmonary edema
Pulmonary embolism
Tumor of the larynx
Medications can cause a cough
Certain medications that can cause a cough include ACE inhibitors (including captopril), which is used to control high blood pressure.
Questions for diagnosing the cause of a cough
To aid in diagnosing the cause of your cough, your doctor or licensed health care practitioner will ask you questions related to your symptoms including:
How long have you had the cough?
Are you coughing up anything (including blood)?
Are you breathing through your mouth (instead of your nose)?
Is your cough keeping you up at night?
Do you have a fever?
What are the potential complications of a cough?
A cough can be a sign of an infectious or inflammatory process, many of which can be easily treated. It is important to contact your health care provider when you experience a cough without an obvious cause or if your cough is persistent, recurrent, or causes you concern. Once the underlying cause is diagnosed, following the treatment you and your doctor design specifically for you can help lower your risk of potential complications including:
Dehydration if cough occurs with diarrhea or vomiting
Dehydration due to reduced fluid intake
Difficulty sleeping
Fainting spells from acute cough attack
- Cough. FamilyDoctor.org. http://familydoctor.org/familydoctor/en/health-tools/search-by-symptom/cough.html.
- Cough. Medline Plus, a service of the National Library of Medicine National Institutes of Health. http://www.nlm.nih.gov/medlineplus/cough.html.
- Tierney LM Jr., Saint S, Whooley MA (Eds.) Current Essentials of Medicine (4th ed.). New York: McGraw-Hill, 2011.
What is a cough?
A cough is your body's defensive reflex that functions to keep your airways clear of irritating or obstructing substances so that you can breathe effectively. A cough can be dry or it can be productive, meaning that you are coughing up mucus (also known as phlegm or sputum). A cough is one of the most common reasons why people visit their primary care doctor.
A cough is a symptom... Read more about coughintroduction
What other symptoms might occur with a cough?
A cough often occurs in conjunction with other symptoms, which vary depending on the underlying disease, disorder or condition. Other symptoms include fever, shortness of breath, and chest pain. Some symptoms, such as sounds the lungs make while you're breathing, changes in blood pressure, and low blood oxygen lev... Read more about coughsymptoms


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As many as 20,000 convicted drug offenders around the country are running the risk of contracting HIV/AIDS, a cabinet minister said on Friday.
Briefing the press after signing a memorandum of understanding with the National AIDS Prevention Commission (KPAN) in Jakarta, Justice and Human Rights Minister Andi Matalatta said the figure was just based on those detained for drug abuse, whose numbers reach about 40,000 nationwide.
"So half of the people detained or jailed for drug abuse are vulnerable to HIV/AIDS," Andi said.
The minister did not explain why people in detention or prison were vulnerable to contracting HIV, but reports of inmates taking drugs or engaging in the illicit prison drug trade abound.
Echoing concerns expressed by health activists, Andi said that drug users were the group most vulnerable to HIV transmission and inmates involved in abusing drugs were no exception.
To prevent transmission among inmates, the ministry and KPAN agreed to use part of the budget from a global fund allocated to preventing HIV/AIDS transmission in Indonesia.
The money, worth Rp 9.43 billion ($95,00), would be used for educational activities and to handle health problems caused by the disease.
Andi said that the high transmission rates among inmates were linked to many problems, including overcapacity in detention facilities, which affects the quality of medical services there.
Andi said Indonesia only had facilities enough for 80,000 prisoners but jails were currently crammed with more than 130,000 inmates.
Meanwhile, Nafsiah Mboi, the National HIV/AIDS Commission secretary, said the economic empowerment of AIDS sufferers and their families would become an integral part of the national program to manage the issue.
The empowerment program was expected to help people living with the disease to deal with their economic situation, Nafsiah said after a meeting with the first lady, Ani Yudhoyono, on Friday.
"They need money to pay for their therapy and medical treatment," she said. "Hopefully the economic empowerment program will help them earn some money."
Nafsiah met with the first lady and Zubairi Djoerban, chairman of the organizing committee of the 9th International Congress on AIDS in Asia and the Pacific.
Nafsiah said Ani, in her capacity as the country's National AIDS ambassador, expressed her support for the empowerment plan.
Zubairi, meanwhile, said that around 3,000 participants representing 65 countries in Asia and the Pacific would attend the AIDS congress in Bali from Aug. 9. The congress aims to strengthen networks to effectively respond to the AIDS pandemic.
Before the congress begins, Ani will hold a high-level meeting with Australia's AIDS ambassador, Murray Proctor, to address the role of AIDS ambassadors in the region and how they can be mobilized to generate more action on the issue.


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A Mexican-inspired casserole dish.
2 lbs boneless skinless chicken thighs
2 tbsp butter
1 onion, sliced
1 can (10 oz.) diced tomatoes and mild green chilies
1 can (10 oz.) condensed cream of mushroom soup
1 can (10 oz.) condensed cream of chicken soup
10 6" flour tortillas, torn into bite-size pieces
2 cups shredded Monterey Jack cheese
1/4 cup shredded Cheddar cheese
Step 1: Preheat barbecue grill to medium-high.
Step 2: Grease a 13" x 9" glass baking dish.
Step 3: Place chicken thighs on preheated barbecue and grill, turning once, for 5-7 minutes per side or until juices run clear when chicken is pierced. Let cool slightly, then cut into cubes.
Step 4: Meanwhile, preheat oven to 350°F.
Step 5: In a skillet, melt butter over medium heat. Sauté onion for 5-7 minutes or until softened. Stir in tomatoes and chilies, mushroom soup and chicken soup. Remove from heat.
Step 6: Spread half the tortilla pieces in bottom of prepared baking dish. Layer with half the onion mixture, half the chicken and half the Monterey Jack. Repeat layers. Sprinkle cheddar cheese over top.
Step 7: Cover and bake in preheated oven for 20 minutes. Uncover and bake for 10 minutes or until bubbling.
Reprinted with permission from Tiffany Collins' 300 Best Casserole Recipes (2010 Robert Rose).
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Message board »Message Board home »Sign-in or register to get startedOnline now: 0 members ; 29 anonymous
Discussion: New bat reviews are in
|March 6, 2012
775 posts
|New bat reviews are in
Our study has been completed on the latest bats in the senior line. If anyone has questions please feel free to email or call me. email@example.com 561-718-7504
|March 6, 2012
Men's 65
4459 posts
|I have a lot of remarks since I was not able to find a site that actually covered softball items let alone mention the sport. If I missed it it wasn't ware clear. I did find mention of baseball, lacrosse some other items but all of it is related primarily to clothing et all.
I was only able to find one name Alan Tanner in a post on the Old Scout web blog site. There too just a inference and request to get info via email. Old Scout has been around a very long time.
I don't think that ratings are a secretive topic. If you are a drop shipper I think we need to know that. For some creditability come out of the closet and say who you are and where. As a business which I believe you are you should at least be honest about it. Chances are you might have good info but "ratings" can be found on dozens of well known sites these days.
If you have 'ratings' for bats and are a company you should also have them on there. When I had a large web site some years ago I had pages of them for ratings as well as links to other sites with them. Share the 'knowledge' reap the rewards.
Overall these are guys who like the game and play honestly and don't want to beat around the bush to find out info. ( like I had to post about spa in another thread.)
I believe there are many others on here that would like answers as well.
Thank you.
|March 6, 2012
775 posts
There is no beating around the bush with me.it's very simple, if you have questions email or call me anytime and I am happy to converse with anyone. I love the sport and have been in it for a very long time and not just as a player.I played and was on advisory staffs for over 12 years on the major level.I posted a quick rundown on the other thread so people would know who was posting. I am not going to post an "autobiography" as was claimed just a few facts so people who didn't know would understand I am not a guy with 3 bats and 27 softballs doing a bat analysis. I have specific testing protocols that I use utilizing ballplayers from all skill levels to get a cross line result. If you would like more information all you have to do is email me and I am happy to provide it. Thanks for your interest.
|March 6, 2012
Men's 65
4459 posts
|So you say.
If you are not posting to a web site you say you have, then imo you are either hiding something or its all ambiguous like the two post relating to the bats & shoes issues you have going.
I may not be the only one interested but interested enough to inquire publicly hoping you would so same.
Besides why not post your "finding" here and save all the reply mail when you can get it all done at the same time.
What I see read in these post is; contact me so I san spin a yarn, maybe give some info you can probably find elsewhere that is close to the same or even the same. Maybe too, try to sell you something in the process.
I'm betting on that. But I have been wrong before on here.
I guess it boils down to integrity or something like it.
Good luck.
|March 6, 2012
775 posts
|Taits, If you read my previous post it states HONESTLY that my website is under construction and thus it is not posted there. I have had numerous sincere phone calls and emails from guys all over the country that I have answered honestly with the results and given my educated opinion when asked. Why are you accusing and Condemning omeone who is offering real results and information for free? You do not know me and you don't even sign your name to your own posts. I am happy to speak with anyone, anytime and give honest, true evaluations.all you have to do is call or email me like everybody else? When my site is up it will be posted for all to see. Leave me your email and I will happily forward the information to you. You do not have to buy or pay for any of it. Just honest, useful information.
|March 6, 2012
Men's 65
4459 posts
It must have been you that made the post on Old Scout... and didn't bother to reply to the post that followed.
Anyway, am not accusing you of anything, just wanting answers. But can see how you might take it that way, sorry. I am glad you have had inquiries but no one has come forward about any of them so its all conjecture.
Just like answers like most people do, with no behind the scenes drama.
I hope you get your new site built, it might have some useful info.
Since you don't want it on here, lets both just move on.
|March 6, 2012
Men's 60
907 posts
|Often times, when I see a post in this venue, I click on the person that sends the post. I do this simply due to the fact that there are more and more posts being placed by anonymous individuals. Frankly, if I see a post without registered person, I discount the content in it. Just my opinion. The anonymous registrations continue to run rampant.
Ed Andrews
Sun Reebok Sr Rep
|March 6, 2012
Men's 60
548 posts
|Tri18......Do you have any information on the
"Veteran Core"? There are a few on here that would like to know if it is coming out this year.
Do you know if it will have U2 pop?
|March 6, 2012
775 posts
|Veteran core....that is one bat that I have not tested and quite honestly don't have definitive knowledge on it. I know a few things but I will not post anything if I haven't seen it done or done it myself. I would love to have a chance to do so and could tHen provide a fair evaluation for everyone. If someone knows the rep please have them contact me and I will get right on it. Thanks, Alan Tanner
|March 6, 2012
Men's 60
1370 posts
|It hasn't been tested because it is a fantasy. Like I learned in narcs.....'Never front your money!"


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text:
Jean L. Freeman, PhD
Professor Grace Bucksch Gnitzinger Distinguished Professor in Aging
Division of Geriatric Medicine, Department of Internal Medicine
Division of Epidemiology and Biostatistics, Department of Preventive Medicine and Community Health
Division of Rehabilitation Sciences, School of Allied Health
Jennie Sealy Hospital, Room 3.132
301 University Blvd.
Galveston, TX 77555-0460
Email: firstname.lastname@example.com
Research Interests:
Dr. Freeman is the Associate Director of the UTMB Institute for Translational Sciences Education Office and the Co-Director of TRSP. She holds the Grace Bucksch Gnitzinger Distinguished Professorship in Aging and is a Fellow in the Sealy Center on Aging. She is Professor in Internal Medicine, Preventive Medicine and Community Health, and SAHS Rehabilitation Sciences. Dr. Freeman received her undergraduate degree magna cum laude in mathematics from Mount Holyoke College and her master's in mathematics from Boston University. She earned her Ph.D. from Yale University in epidemiology and public health and has directed and developed studies in health services research for more than 25 years. Dr. Freeman was recruited to UTMB in 1992. Her recent work is focused on the use of population based healthcare datasets (e.g. Medicare claims, tumor registry data, health surveys) to develop and evaluate measures of health care access, use, and outcomes in diverse populations and clinical settings. She also collaborates extensively on interdisciplinary research teams that use these data to identify disparities in receipt of appropriate prevention and treatment services, as well as the mechanisms underlying these disparities.
From 1996-2008 she had funding from the Department of Defense (DAMD17-96-1-6215) and the National Cancer Institute (RO1CA72076) to examine the use and outcomes of mammography services in older women. Currently, she is PI of an NCI funded study (R01CA133069) to estimate the risks of bowel and bladder toxicities after radiation among older women diagnosed with gynecologic cancers. She has over 110 publications and book chapters and serves on numerous institutional and external committees.
Dr. Freeman is also active in the development and direction of research training programs for all levels of trainees in clinical and health services research. In addition to her leadership roles in the ITS Education Office, she serves as Research Director of the UTMB's K12 Women's Health Research Scholars Program (A Berenson PI) , Associate Director for Training in the Sealy Center on Aging, and Vice Chair for Faculty Development in the Department of Internal Medicine. She is a member of the Graduate School of Biomedical Sciences, where serves as Director of the Health Services Research Track within the Clinical Science Graduate Program. In the Population Health Sciences program, she directs courses (Methods in Health Services Research, Outcomes Research, Health Policy & Management) and supervises or has supervised over 25 students in their dissertation/thesis research. In 2005, she was recognized by the GSBS Graduate Student Organization with the Distinguished Teaching Award.


text:
We're on 7.5.4 LAN. We have about 13 remote users currently. Everything seemed to be humming along just fine until I noticed that about 5 days ago, the TEF's, although are being created just fine, are not moving from Logs --> OUTFILES folder on Sync server to the FTP OUTFILES directory...... except for one user. Her files are still moving as they should. Is there an issue I should know about??
Sage Saleslogix has posted a bug fix for this. It is being tested now.


text:
A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.
1. A method of operating an erasable and re-programmable non-volatile memory system, which comprises, in response to receiving a command from outside the memory system having a time budget for its execution:
perform any function necessary to execute the command,
assert a busy signal outside of the memory system for a time extending beyond that utilized to perform said any necessary function while remaining within the time budget, and
perform during the extended busy signal time at least a portion of one housekeeping operation within the memory system that is unnecessary to execute the received command.
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11. A method of operating an erasable and re-programmable non-volatile memory system, comprising, in response to receiving a command to transfer one or more units of data within a given time budget:
determining whether any housekeeping operation is necessary to be able to transfer the one or more units of data,
if any housekeeping operation is necessary to be able to transfer the one or more units of data, performing at least the necessary housekeeping operation,
determining whether a housekeeping operation unnecessary to the transfer of one or more units of data is pending,
if a housekeeping operation unnecessary to the data transfer is pending, determining whether any remaining time within the time budget is sufficient for performing the pending housekeeping operation unnecessary to the data transfer,
if sufficient time remains within the time budget, performing at least a portion of the pending housekeeping operation unnecessary to the data transfer during execution of the received command, and
transferring the one or more units of data within the given time budget.
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25. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a number of memory cells that are simultaneously erasable and wherein data within logical group addresses are mapped into the physical blocks, comprising in response to receiving a command to write data to one of the logical groups and the data to be written:
determining whether data within the logical group is mapped to more than one of the physical blocks,
determining whether there is a wear leveling exchange pending between two of the plurality of blocks, and
(a) if data within the logical group are mapped to more than one of the physical blocks,
consolidating the data of the more than one of the physical blocks into a single block, and
writing the received data to an update block associated with the logical group, or
(b) if data within the logical group are not mapped to more than one of the physical blocks but there is a wear leveling exchange pending,
performing a wear leveling exchange between said two of the physical blocks, and
writing the received data to an update block associated with the logical group.
26. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a number of memory cells that are simultaneously erasable and wherein incoming data within logical group addresses mapped to one of the physical blocks are programmed into an update physical block logically linked to said one block, comprising in response to receiving a write command and data to be written:
determining whether an update block is available to receive the data to be written,
(a) if an update block is not available,
consolidating data of one of a plurality of update blocks with data of a physical block to which data of the update block are logically linked, thereby making an update block available, and thereafter writing data to the available update block, or
(b) if an update block is available,
performing a wear leveling exchange of data between two of the physical blocks, and
thereafter writing data to the available update block.
27. A method of operating a system of erasable and re-programmable non-volatile memory cells organized into a plurality of physical blocks of a number of memory cells that are simultaneously erasable and wherein incoming data within logical addresses mapped to one of the physical blocks are programmed into an update physical block logically linked to said one block, wherein a limited number of the plurality of blocks are specified to be update blocks and new update blocks are created by garbage collection that consolidates data from at least two blocks into one block, which comprises in response to receiving a write command and data to be written:
determining whether a housekeeping operation unnecessary to execution of the write command is pending and which includes the necessity to copy of a plurality of units of data from one of the plurality of blocks to an update block,
if so, copying one or more of the plurality of units of data but less than one-quarter of the units from said one block into one of the update blocks during execution of the write command,
identifying said one update block as the next in order to have its data consolidated, and
after execution of the write command, perform garbage collection on said one update block, whereby the remaining of the plurality of units of data within said one block are placed together with the one or more copied units into a common block.
This application is a continuation-in-part of U.S. patent application Ser. No. 11/040,325 filed on Jan. 20, 2005.
This invention relates generally to the operation of non-volatile flash memory systems, and, more specifically, to techniques of carrying out housekeeping operations, such as wear leveling, in such memory systems. All patents, patent applications, articles and other publications referenced herein are hereby incorporated herein by these references in their entirety for all purposes.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor removable cards or embedded modules, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, is included in the memory system to interface with a host to which the system is connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during the programming and reading of data. Other memory cards and embedded modules do not include such a controller but rather the host to which they are connected includes software that provides the controller function. Memory systems in the form of cards include a connector that mates with a receptacle on the outside of the host. Memory systems embedded within hosts, on the other hand, are not intended to be removed.
Some of the commercially available memory cards that include a controller are sold under the following trademarks: CompactFlash (CF), MultiMedia(MMC), Secure Digital (SD), MiniSD, MicroSD, and TransFlash. An example of a memory system that does not include a controller is the SmartMedia card. All of these cards are available from SanDisk Corporation, assignee hereof. Each of these cards has a particular mechanical and electrical interface with host devices to which it is removably connected. Another class of small, hand-held flash memory devices includes flash drives that interface with a host through a standard Universal Serial Bus (USB) connector. SanDisk Corporation provides such devices under its Cruzer trademark. Hosts for cards include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. A flash drive works with any host having a USB receptacle, such as personal and notebook computers.
Two general memory cell array architectures have found commercial application, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,373,746, 6,456,528, 6,522,580, 6,771,536 and 6,781,877.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates, typically formed from conductively doped polysilicon material. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region, and erased by injecting hot holes into the nitride. Several specific cell structures and arrays employing dielectric storage elements and are described in U.S. patent application publication no. US 2003/0109093 of Harari et al.
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in aforementioned United States patent application publication no. US 2003/0109093. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Memory cells of a typical flash EEPROM array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit, a minimum number of cells that are simultaneously erasable. Each block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each block, and each page stores one or just a few host sectors of data.
In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.
To further efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each plane. Use of the metablock is described in U.S. Pat. No. 6,763,424. The physical address of a metablock is established by translation from a logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are erased together. The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions including the translation between logical block addresses (LBAs) received from a host, and physical block numbers (PBNs) within the memory cell array. Individual pages within the blocks are typically identified by offsets within the block address. Address translation often involves use of intermediate terms of a logical block number (LBN) and logical page.
It is common to operate large block or metablock systems with some extra blocks maintained in an erased block pool. When one or more pages of data less than the capacity of a block are being updated, it is typical to write the updated pages to an erased block from the pool and then copy data of the unchanged pages from the original block to erase pool block. Variations of this technique are described in aforementioned U.S. Pat. No. 6,763,424. Over time, as a result of host data files being re-written and updated, many blocks can end up with a relatively few number of its pages containing valid data and remaining pages containing data that is no longer current. In order to be able to efficiently use the data storage capacity of the array, logically related pages of valid data are from time-to-time gathered together from fragments among multiple blocks and consolidated together into a fewer number of blocks. This process is commonly termed "garbage collection."
Data within a single block or metablock may also be compacted when a significant amount of data in the block becomes obsolete. This involves copying the remaining valid data of the block into a blank erased block and then erasing the original block. The copy block then contains the valid data from the original block plus erased storage capacity that was previously occupied by obsolete data. The valid data is also typically arranged in logical order within the copy block, thereby making reading of the data easier.
Control data for operation of the memory system are typically stored in one or more reserved blocks or metablocks. Such control data include operating parameters such as programming and erase voltages, file directory information and block allocation information. As much of the information as necessary at a given time for the controller to operate the memory system are also stored in RAM and then written back to the flash memory when updated. Frequent updates of the control data results in frequent compaction and/or garbage collection of the reserved blocks. If there are multiple reserved blocks, garbage collection of two or more reserve blocks can be triggered at the same time. In order to avoid such a time consuming operation, voluntary garbage collection of reserved blocks is initiated before necessary and at a times when they can be accommodated by the host. Such pre-emptive data relocation techniques are described in U.S. patent application Ser. No. 10/917,725, filed Aug. 13, 2004. Garbage collection may also be performed on user data update block when it becomes nearly full, rather than waiting until it becomes totally full and thereby triggering a garbage collection operation that must be done immediately before data provided by the host can be written into the memory.
In some memory systems, the physical memory cells are also grouped into two or more zones. A zone may be any partitioned subset of the physical memory or memory system into which a specified range of logical block addresses is mapped. For example, a memory system capable of storing 64 Megabytes of data may be partitioned into four zones that store 16 Megabytes of data per zone. The range of logical block addresses is then also divided into four groups, one group being assigned to the physical blocks of each of the four zones. Logical block addresses are constrained, in a typical implementation, such that the data of each are never written outside of a single physical zone into which the logical block addresses are mapped. In a memory cell array divided into planes (sub-arrays), which each have their own addressing, programming and reading circuits, each zone preferably includes blocks from multiple planes, typically the same number of blocks from each of the planes. Zones are primarily used to simplify address management such as logical to physical translation, resulting in smaller translation tables, less RAM memory needed to hold these tables, and faster access times to address the currently active region of memory, but because of their restrictive nature can result in less than optimum wear leveling.
Individual flash EEPROM cells store an amount of charge in a charge storage element or unit that is representative of one or more bits of data. The charge level of a storage element controls the threshold voltage (commonly referenced as VT) of its memory cell, which is used as a basis of reading the storage state of the cell. A threshold voltage window is commonly divided into a number of ranges, one for each of the two or more storage states of the memory cell. These ranges are separated by guardbands that include a nominal sensing level that allows determining the storage states of the individual cells. These storage levels do shift as a result of charge disturbing programming, reading or erasing operations performed in neighboring or other related memory cells, pages or blocks. Error correcting codes (ECCs) are therefore typically calculated by the controller and stored along with the host data being programmed and used during reading to verify the data and perform some level of data correction if necessary. Also, shifting charge levels can be restored back to the centers of their state ranges from time-to-time, before disturbing operations cause them to shift completely out of their defined ranges and thus cause erroneous data to be read. This process, termed data refresh or scrub, is described in U.S. Pat. Nos. 5,532,962 and 5,909,449, and U.S. patent application Ser. No. 10/678,345, filed Oct. 3, 2003.
The responsiveness of flash memory cells typically changes over time as a function of the number of times the cells are erased and re-programmed. This is thought to be the result of small amounts of charge being trapped in a storage element dielectric layer during each erase and/or re-programming operation, which accumulates over time. This generally results in the memory cells becoming less reliable, and may require higher voltages for erasing and programming as the memory cells age. The effective threshold voltage window over which the memory states may be programmed can also decrease as a result of the charge retention. This is described, for example, in U.S. Pat. No. 5,268,870. The result is a limited effective lifetime of the memory cells; that is, memory cell blocks are subjected to only a preset number of erasing and re-programming cycles before they are mapped out of the system. The number of cycles to which a flash memory block is desirably subjected depends upon the particular structure of the memory cells, the amount of the threshold window that is used for the storage states, the extent of the threshold window usually increasing as the number of storage states of each cell is increased. Depending upon these and other factors, the number of lifetime cycles can be as low as 10,000 and as high as 100,000 or even several hundred thousand.
If it is deemed desirable to keep track of the number of cycles experienced by the memory cells of the individual blocks, a count can be kept for each block, or for each of a group of blocks, that is incremented each time the block is erased, as described in aforementioned U.S. Pat. No. 5,268,870. This count may be stored in each block, as there described, or in a separate block along with other overhead information, as described in U.S. Pat. No. 6,426,893. In addition to its use for mapping a block out of the system when it reaches a maximum lifetime cycle count, the count can be earlier used to control erase and programming parameters as the memory cell blocks age. And rather than keeping an exact count of the number of cycles, U.S. Pat. No. 6,345,001 describes a technique of updating a compressed count of the number of cycles when a random or pseudo-random event occurs.
The cycle count can also be used to even out the usage of the memory cell blocks of a system before they reach their end of life. Several different wear leveling techniques are described in U.S. Pat. No. 6,230,233, U.S. patent application publication no. US 2004/0083335, and in the following U.S. patent applications filed Oct. 28, 2002: Ser. Nos. 10/281,739 (now published as WO 2004/040578), 10/281,823 (now published as no. US 2004/0177212), 10/281,670 (now published as WO 2004/040585) and 10/281,824 (now published as WO 2004/040459). The primary advantage of wear leveling is to prevent some blocks from reaching their maximum cycle count, and thereby having to be mapped out of the system, while other blocks have barely been used. By spreading the number of cycles reasonably evenly over all the blocks of the system, the full capacity of the memory can be maintained for an extended period with good performance characteristics. Wear leveling can also be performed without maintaining memory block cycle counts, as described in U.S. application Ser. No. 10/990,189, filed Nov. 15, 2004.
In another approach to wear leveling, boundaries between physical zones of blocks are gradually migrated across the memory cell array by incrementing the logical-to-physical block address translations by one or a few blocks at a time. This is described in U.S. patent application publication no. 2004/0083335.
A principal cause of a few blocks of memory cells being subjected to a much larger number of erase and re-programming cycles than others of the memory system is the host's continual re-writing of data sectors in a relatively few logical block addresses. This occurs in many applications of the memory system where the host continually updates certain sectors of housekeeping data stored in the memory, such as file allocation tables (FATs) and the like. Specific uses of the host can also cause a few logical blocks to be re-written much more frequently than others with user data. In response to receiving a command from the host to write data to a specified logical block address, the data are written to one of a few blocks of a pool of erased blocks. That is, instead of re-writing the data in the same physical block where the original data of the same logical block address resides, the logical block address is remapped into a block of the erased block pool. The block containing the original and now invalid data is then erased either immediately or as part of a later garbage collection operation, and then placed into the erased block pool. The result, when data in only a few logical block addresses are being updated much more than other blocks, is that a relatively few physical blocks of the system are cycled with the higher rate. It is of course desirable to provide the capability within the memory system to even out the wear on the physical blocks when encountering such grossly uneven logical block access, for the reasons given above.
Housekeeping operations are carried out during the execution of a command received from the host system with which the memory system is operably connected, and within a time budget set for execution of the command. In addition to any housekeeping operation necessary for the memory system to be able to execute the command, a housekeeping operation not directly related to or required for execution of the received command may also be performed. Such unrelated housekeeping operations need not be performed each time a command is executed but rather may be limited to being carried out during only some command executions. For example, performance of an unrelated housekeeping operation that takes too much time to complete can await receipt of a command where the necessary time becomes available because a command related housekeeping operation is not necessary to execute that command. By performing housekeeping functions as part of the execution of host commands, there is no uncertainty about whether the host will permit the housekeeping operations to be completed, so long as they are completed within the known time budget set by the host.
Examples of unrelated housekeeping operations include wear leveling, scrubbing, data compaction and garbage collection, including pre-emptive garbage collection. In addition to garbage collection or any other housekeeping operation necessary to execute a command, the memory system may carry out a housekeeping operation unnecessary to execution of the command. For example, wear leveling is unnecessary to execute a write command but is conveniently carried out during the execution of such a command when there is time in the budget to do so. The time budget is established by a host time-out or the like for executing a command such as a data write, or the existence of a certain minimum required data transfer rate during writing or reading in an application to which the memory system is likely to be put. In one specific example, where there is not enough time to perform multiple housekeeping operations, wear leveling is performed during execution of those write commands where garbage collection is unnecessary.
Additional aspects, advantages and features of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings.
Memory Architectures and Their Operation
Referring initially to
A typical controller 19 includes a microprocessor 21, a read-only-memory (ROM) 23 primarily to store firmware and a buffer memory (RAM) 25 primarily for the temporary storage of user data either being written to or read from the memory chips 11 and 13. Circuits 27 interface with the memory array chip(s) and circuits 29 interface with a host though connections 31. The integrity of data is in this example determined by calculating an ECC with circuits 33 dedicated to calculating the code. As user data is being transferred from the host to the flash memory array for storage, the circuit calculates an ECC from the data and the code is stored in the memory. When that user data are later read from the memory, they are again passed through the circuit 33 which calculates the ECC by the same algorithm and compares that code with the one calculated and stored with the data. If they compare, the integrity of the data is confirmed. If they differ, depending upon the specific ECC algorithm utilized, those bits in error, up to a number supported by the algorithm, can be identified and corrected.
The connections 31 of the memory of
The memory of
The inventive techniques herein may be implemented in systems having various specific configurations, examples of which are given in
The size of the individual memory cell blocks of
The parameters 55 may include a quantity related to the number of program/erase cycles experienced by the block, this quantity being updated after each cycle or some number of cycles. When this experience quantity is used in a wear leveling algorithm, logical block addresses are regularly re-mapped to different physical block addresses in order to even out the usage (wear) of all the blocks. Another use of the experience quantity is to change voltages and other parameters of programming, reading and/or erasing as a function of the number of cycles experienced by different blocks.
The parameters 55 may also include an indication of the bit values assigned to each of the storage states of the memory cells, referred to as their "rotation". This also has a beneficial effect in wear leveling. One or more flags may also be included in the parameters 55 that indicate status or states. Indications of voltage levels to be used for programming and/or erasing the block can also be stored within the parameters 55, these voltages being updated as the number of cycles experienced by the block and other factors change. Other examples of the parameters 55 include an identification of any defective cells within the block, the logical address of the block that is mapped into this physical block and the address of any substitute block in case the primary block is defective. The particular combination of parameters 55 that are used in any memory system will vary in accordance with the design. Also, some or all of the overhead data can be stored in blocks dedicated to such a function, rather than in the block containing the user data or to which the overhead data pertains.
Different from the single data sector block of
Re-writing the data of an entire block usually involves programming the new data into an erased block of an erase block pool, the original block then being erased and placed in the erase pool. When data of less than all the pages of a block are updated, the updated data are typically stored in a page of an erased block from the erased block pool and data in the remaining unchanged pages are copied from the original block into the new block. The original block is then erased. Alternatively, new data can be written to an update block associated with the block whose data are being updated, and the update block is left open as long as possible to receive any further updates to the block. When the update block must be closed, the valid data in it and the original block are copied into a single copy block in a garbage collection operation. These large block management techniques often involve writing the updated data into a page of another block without moving data from the original block or erasing it. This results in multiple pages of data having the same logical address. The most recent page of data is identified by some convenient technique such as the time of programming that is recorded as a field in sector or page overhead data.
A further multi-sector block arrangement is illustrated in
Yet another memory cell arrangement is illustrated in
There are many different memory array architectures, configurations and specific cell structures that may be employed to implement the memories described above with respect to
Each row of charge storage transistors (memory cells) of the block contains one or more pages, data of each page being programmed and read together. An appropriate voltage is applied to the word line (WL) for programming or reading data of the memory cells along that word line. Proper voltages are also applied to their bit lines (BLs) connected with the cells of interest. The circuit of
One specific architecture of the type of memory system described above and its operation are generally illustrated by
More physical blocks of memory are included than there are logical groups in the memory system address space. In the example of
The writing of new data into the memory system represented by
At a later time, these data may be consolidated (garbage collected) from the P(m−2) and P2 blocks into a single physical block. This is accomplished by writing the remaining valid data from the block P(m−2) and the new data from the update block P2 into another block in the erased block pool, such as block P5. The blocks P(m−2) and P2 are then erased in order to serve thereafter as update or erase pool blocks. Alternatively, remaining valid data in the original block P(m−2) may be written into the block P2 along with the new data, if this is possible, and the block P(m−2) is then erased.
In order to minimize the size of the memory array necessary for a given data storage capacity, the number of extra blocks are kept to a minimum. A limited number, two in this example, of update blocks are usually allowed by the memory system controller to exist at one time. Further, the garbage collection that consolidates data from an update block with the remaining valid data from the original physical block is usually postponed as long as possible since other new data could be later written by the host to the physical block to which the update block is associated. The same update block then receives the additional data. Since garbage collection takes time and can adversely affect the performance of the memory system if another operation is delayed as a result, it is not performed every time that it could. Copying data from the two blocks into another block can take a significant amount of time, especially when the data storage capacity of the individual blocks is very large, which is the trend. Therefore, it often occurs when the host commands that data be written, that there is no free or empty update block available to receive it. An existing update block is then garbage collected, in response to the write command, in order to thereafter be able to receive the new data from the host. The limit of how long that garbage collection can be delayed has been reached.
First Wear Leveling Embodiment
Assertion of the busy signal by the memory system between times t4 and t5, as shown, allows the memory system to perform garbage collection, when necessary to execute the write command, and then write the data received. The host does not send another command or any further data to the memory system when its busy signal is active. As shown in the last line of
The length of the busy signal that the memory system may assert is limited, however, because most hosts allow a limited fixed amount of time for the memory system to execute a write command after a data unit is transferred. If the busy signal remains active for longer than that, some hosts may repeat the command with the data and others may abort the process entirely. The memory system is operated in a manner that does not exceed this time-out period of hosts with which the memory is designed to function. One common host time-out period is 250 milliseconds. In any event, the transfer of commands and data between a host and a memory system connected with it can be delayed by the memory system's assertion of the busy signal, so it is desirable to limit its use to situations where the delay is important to overall good performance of the memory system.
In addition to the host time-out period, operation of the memory system is also constrained, in many applications, by a minimum data flow rate that must be maintained. This can require that the duration of individual busy signals asserted by the memory system be less than that the maximum allowed by the host time-out.
Similarly, wear leveling operations are preferably scheduled to avoid excessively impacting other operations and overall memory system performance. As described in the patents and applications mentioned above, wear leveling includes changing the mapping of addresses of logical groups to physical memory blocks in order to even the wear (number of erase cycles). A range of logical addresses that are constantly being rewritten, for example, are redirected from one physical block, which is being cycled at a rate higher than the average, into another physical block with a lower cycle history. There are many wear leveling algorithms, some of which monitor cycle counts of the logical group rewrites or individual physical block usage and others of which do not use such counts but otherwise distribute the wear over the memory blocks.
Typically, a wear leveling operation also involves the transfer (exchange) of data from one block to another, and this is the most time consuming part of the operation. Wear leveling exchanges are initiated from time-to-time by the memory system controller to correct for a building imbalance in the usage of the memory blocks. The purpose of wear leveling is to extend the life of the memory by avoiding one or a few blocks being cycled a number of times that exceed the useful lifetime of the memory. The loss of the use of a few, and sometimes only one, memory blocks can render the memory system inoperable.
Wear leveling is commonly performed in the background. That is, the re-mapping of blocks and any data transfer(s) takes place when the host is idle. This has the advantage of not adversely affecting the performance of the memory system but has the disadvantage that the host is not prevented from sending a command while the memory system is doing wear leveling and can even disconnect power from the memory system during the wear leveling exchange. Therefore, in the examples described herein, wear leveling is performed in the foreground, from time-to-time, as part of data writes.
Referring again to
However, execution of a write command in the memory system of
A specific example of an operation according to the timing diagram of
In a next step 231, it is asked whether a wear leveling exchange is pending. That is, it is determined whether the conditions necessary to initiate wear leveling exist. As the patents and patent applications referenced above demonstrate, there are a large number of different wear leveling algorithms with different events triggering their operation. In the wear leveling embodiment described herein, wear leveling is initiated every N erase cycles of memory blocks or metablocks. The number N may be around 50, for example. Although this is the starting point, as described hereinafter, the determination becomes somewhat more complicated when wear leveling must be postponed for significant periods of time. Such postponement can occur, for example, when a large number of successive write operations each require garbage collection. There is then no memory system busy periods that can be used for wear leveling. This occurs when there are a number of writes in succession of single units of data in different logical groups, for example.
If wear leveling is pending, a next step 233 checks the count of the garbage collection counter. If the count is not zero, this indicates that a garbage collection operation was performed in the step 229 and, therefore, there is not enough time to also do wear leveling. So wear leveling is skipped. If the count is zero, however, this indicates that no garbage collection occurred, so there may therefore be enough time to do wear leveling. But first, by a step 235, it is determined whether there is a free or empty update block for use in the wear leveling. If not, wear leveling is skipped because there will not be enough time to both do the garbage collection necessary to obtain an update block and do the wear leveling. But if there is an update block available, wear leveling is performed, in a step 237, according to an algorithm described in one of the wear leveling patents and patent applications identified above, or that described below. Generally, a wear leveling operation includes opening the available update block for wear leveling, copying all the data from a source block into the opened update block, then closing the update block and updating the address translation table to re-map the logical group of the data from the source block to the update block (destination block).
Thereafter, in a step 239, the data received into the memory system controller buffer is written into a block or metablock of the flash memory. The garbage collection counter is then set back to zero, in a step 241, for use during the next data write by the process of the
An example method of initiating a wear leveling exchange will now be described. This is part of the step 231 of
As reflected in the flowchart of
Therefore, it is desirable to vary the interval between wear leveling exchanges from the nominal N block erasure interval when wear leveling has been postponed for any significant time. The number of wear leveling operations that have been missed is maintained, and they may thereafter be individually rendered pending at intervals shorter than N block erasures apart. The curves of
At an erase count 273 of
A preferred technique is illustrated in
Second Wear Leveling Embodiment
If there is an update block available ("yes" at step 235′,
As an optional optimization, a next step 304 may force the new update block with the one page or metapage of data to be identified as the least recently used (LRU) of the system update blocks. This update block is certainly not the least recently used since it was just opened. But by designating it as the LRU update block, it will be closed the next time that another update block needs to be opened. The closure process includes garbage collection to take place, most conveniently executed by copying the remaining pages from the source block into this block. This block is then closed and the necessary new update block is opened. The wear leveling exchange has then been completed during normal operation of the memory system. No special operation is necessary for completion of the wear leveling exchange, once it has been set up.
During a subsequent interval 315, when execution of the next write command takes place that requires garbage collection in order to provide an open update block, the garbage collection 317 completes the wear leveling exchange. Data units 3 and 4, in this example, are then written into the flash memory during an interval 319.
The process of
Copying one or more pages of data into the new update block sets it up for the subsequent garbage collection without having to modify the garbage collection process. The wear leveling exchange is completed rather automatically. Alternatively, no data need be copied initially into the new update block but rather the new update block can be marked with a flag that also identifies the source block of data to be copied into it. The data exchange can then be caused to take place later in response to the flag.
An alternate method of accomplishing the same data write and wear leveling operations is illustrated by the timing diagram of
The same functions take place in the example of
By the example of
Third Wear Leveling Embodiment
An operational flowchart of
By a next step 247, a first of the multiple units of data is received into the controller buffer memory, and garbage collection is commenced, in a step 249, if necessary to be able to execute the write command. The time budget determined by the step 245 can then be decreased by the amount of time taken to do the garbage collection (not shown) by decrementing a counter or the like.
In a step 251, a second unit of data is received and it is then determined whether wear leveling can also be performed during the present data write operation. By a step 253, it is determined whether there is a wear leveling exchange pending; that is, whether the conditions exist to initiate wear leveling according to the specific wear leveling algorithm that is being used. If so, in a next step 255, the existence of a free or empty update block for use in wear leveling is determined. If one exists, wear leveling is then performed (step 257), followed by receiving any further data units of the present write command (step 259) and writing the data units of the present write command into flash memory (step 261). Of course, if it is determined by the step 253 that no wear leveling exchange is pending, then the processing moves directly from there to the step 259.
Returning to the step 255, if there is no update block readily available for use during wear leveling, a next step 263 ascertains whether there is time to perform the garbage collection necessary to obtain such an update block. Since, in this example, each of the garbage collection and wear leveling exchanges are performed during a busy signal from the memory system after receipt of a unit of data from the host, this inquiry is whether there is a third unit of data. If so, it is received (step 265) and the necessary garbage collection (step 267) is performed. The wear leveling of the step 257 is thereafter performed. But if there is no time for this additional garbage collection, the process proceeds directly to the step 261.
As a variation of the process of
One specific method of operation is shown by the timing diagram of
Although two different housekeeping operations, namely garbage collection and wear leveling, are performed during successive memory system busy periods, only one such operation is carried out during each of the memory system busy periods of
In the example of
Example Wear Leveling Algorithm
A specific wear leveling algorithm that may be executed in the step 237 of
The block pointed to is selected as the source block if certain additional criteria are met. The block needs to contain host data, and will not be selected if it is a reserved block containing memory system control data (in addition to what is described with respect to
If the block pointed to is not suitable as a source block for one of these or some other reason, the pointer is then incremented to the next logical group or physical block in order and this next block is also tested against the above-criteria. If this second block fails the test, then another is pointed to and tested. A maximum number is preferably placed on the number of blocks that are considered when a suitable block is not found. The current wear leveling exchange is then aborted and the search resumes during the next wear leveling exchange.
The destination block is selected from the erased pool blocks, normally the next block placed in order to be used for the storage of data from the host. But instead of storing host data, data from the source block is copied to this destination block. The mapping table (215) is then updated so that the logical group to which these data belong is mapped to the new block. The source block is then erased and placed into the erase pool.
The timing diagram of
One other housekeeping function that can benefit from the extended busy period(s) is the refreshing (scrubbing) of the charge levels stored in the memory cells, as mentioned above. Memory cells in one or more blocks or metablocks not involved in execution of the received command are refreshed. Another is pre-emptive garbage collection, also mentioned above. Such garbage collection is also performed on data in blocks or metablocks not involved in execution of the received command. Other overhead operations similarly unnecessary to and not required for execution of the received command may also be performed during busy periods asserted by the memory system. This is particularly useful for housekeeping operations that require copying large amounts of data since such copying takes significant amounts of time. None of the wear leveling, scrubbing, pre-emptive garbage collection or other similar operations carried out during execution of a host command is an essential part of that command's execution. They are neither directly related to nor triggered by the received command. Except for the limit of the amount of time to perform such other operations, there is little limit to what can be done during execution of a host command.
Further, in addition to performing such unrelated operations during execution of write commands, they can also be performed during execution of other host commands where the memory system can operate to delay receipt of a further host command by assertion of a busy signal or otherwise. One such other command is the read command.
Although the various aspects of the present invention have been described with respect to exemplary embodiments thereof, it will be understood that the present invention is entitled to protection within the full scope of the appended claims.
Referenced by
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