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A special purpose circuit unit, responsive to a special BBD instruction, provides for more efficient execution of program branches required in poll and test type routines used by data processors. This unit can easily be added to almost any contemporary processing system to speed up performance of priority branch operations. It includes: a stack of registers loadable with branch addresses designating locations of branch target instructions, an input register for holding bits representing branch conditions accessible from immediate (programmable) storage, and a programmable priority encoder responsive to the BBD instruction to select an address from the stack in accordance with the position in the input register of a highest priority one of the bits representing an active request for instruction branching. The selected address is used to fetch an instruction representing the start of a program segment for attending to the selected branch condition. Contents of the branch address stack are alterable by program to allow for varying selections of branch routines to fulfill conditions denotable by different sets of bits loadable into the input register. The priority encoder includes a stack of selection control registers which are also loadable by programs, to allow for variability in the priority ordering accorded to the bit positions of the input register. By dynamically loading information into the branch address and priority selection stacks, subject BBD unit can be shared dynamically for resolving sequence branching relative to multiple different classes of conditions or events depending on system requirements. The unit is configurable to execute its priority and branch address selection operations together in a single clock cycle of the system. In pipelined systems, the BBD function can be conveniently accommodated in parallel with other system functions.
1. In a data processing system, priority branch on bit apparatus for efficiently executing program branch instructions in a single system cycle to select subroutines for performing selected functions associated with a set of user parameters comprising
input register means storing a set of status bits, each bit corresponding to a respective one of said parameters;
program controlled means setting each status bit to an active state when its respective parameter requires subroutine execution;
priority register means coupled to said input register means and storing a set of priority codes, each code assigned to a respective one of said parameters and its status bit;
address register means storing a set of branch addresses each pointing to a respective one of said subroutine associated with a respective one of said parameters and its status bit;
logic means, including a priority encoding unit coupled to said priority register means and to said address register means, and responsive to the execution of a predetermined one of said branch instructions for transferring priority codes corresponding to active status bits in said input register means from the priority register means to the priority encoding unite to produce output signals representative of the active status bit having the highest priority code; and
means responsive to said output signals for selecting a branch address in said address register means corresponding to the last-mentioned active status bit.
2. In a data processing system, priority branch on bit apparatus for executing program branch instructions in a single system cycle to select subroutines for performing selected functions associated with a set of user parameters comprising
input register means storing a set of status bits, each bit corresponding to a respective one of said parameters;
first program controlled means setting each said status bit to an active state when its respective parameter requires subroutine execution;
priority register means coupled to said input register means and storing a set of priority codes, each code assigned to a respective one of said parameters and its status bit;
address register means storing a set of branch addresses each pointing to a respective one of said subroutines associated with a respective one of said parameters and its status bit; and
logic means, including a priority encoding unit coupled to said priority register means and to said address register means, and responsive to the execution of a predetermined one of said branch instructions for transferring priority codes corresponding to active status bits in said input register means from the priority register means to the priority encoding unit for selecting the branch address in said address register means pointing to the subroutine associated with the active status bit having the highest assigned priority code.
3. The data processing system of claim 2 wherein a plurality of sets of subroutines are provided, each set of subroutines being provided for performing function associated with a respective set of user parameters, said system further comprising
second program controlled means preconditioning said priority register means with a set of priority codes assigned to a predetermined one of said user parameter sets,
third program controlled means preconditioning said address register means with a set of branch addresses pointing to a respective set of subroutines associated with said predetermined one user parameter set,
said first program controlled means effective while said register means are so preconditioned for setting the status bits in said input register, corresponding to parameters in said one predetermined set requiring subroutine execution, to their active states, and
said logic means responsive to a predetermined branch instruction for selecting a branch address in said address register means pointing to the subroutine associated with the active status bit in the input register with the highest priority.
4. The data processing system of claim 3 further comprising:
a plurality of sets of first registers in said priority register means,
said second program controlled means preconditioning each set of first registers with a set of priority codes assigned to a respective different one of said user parameter sets,
a plurality of sets of second registers in said address register means,
said third program controlled means preconditioning each set of second registers with a set of branch addresses pointing to a respective set of subroutines associated with a respective different one of said user parameter sets,
said logic means further including means responsive to different ones of said program branch instructions; designating respective different first and second register sets, for transferring priority codes corresponding to active status bits in said input register means form respective first register sets to the priority encoding unit for selecting branch addresses from respective second register sets in accordance with the active status bit with the highest priority, and
program controlled means conditioning the input register means for use with different sets of suer parameters, whereby the priority branch apparatus may operate continuously with different sets of parameters without reloading of the first and second register sets.
5. The data processing system of claim 2 further comprising program controlled means for preconditioning said priority register means to vary the priority codes assigned to each of the respective parameters.
6. The data processing system of claim 2, wherein more than one subroutine may be associated with each of at least certain of said parameters, further comprising program controlled means for selectively preconditioning said address register means to vary the branch addresses associated with said certain parameters.
7. The data processing system of claim 6, wherein more than one subroutine may be associated with each of at least certain of said parameters, further comprising program controlled means for selectively preconditioning said address register means to vary the branch addresses associated with said parameters.
8. In a data processing system, a method of performing priority branch on bit operations in a single system cycle to select subroutines for performing functions associated with a set of user parameters comprising:
storing a set of status bits, each bit corresponding to a respective one of said parameters;
storing a set of priority code values, each code being assigned to a respective one of said parameters and its status bit;
storing a set of branch addresses, each pointing to a respective one of said subroutines associated with a respective one of said parameters and its status bit;
setting each said status bit to an active state when its respective parameter requires subroutine execution; and
in response to a predetermined instruction of said system;
comparing the priority code values associated with the status bits which are set to their active states,
determining the highest one of said compared priority code values, and
selecting a branch address to the subroutine associated with the active status bit having said highest compared priority code value.
9. In a data processing system wherein a plurality of sets of subroutines are provided for performing functions associated with respective sets of user parameters, a method of performing priority branch on bit operations in a single system cycle of operation to select certain of said subroutines when their respective parameters require action without having to reload branch data associated with the parameters comprising:
storing a respective set of status bits for each set of parameters, each bit in a set corresponding to a respective one of said parameters in its respective set;
setting each status bit to an active state when its respective parameter requires subroutine execution;
storing a respective set of priority values for each set of parameters and its respective set of status bits, each priority value in a set being assigned to a respective one of the parameters in its respective set and to its corresponding status bit;
storing a respective set of branch addresses for each set of parameters and its respective set of status bits, each branch address in a set pointing to a subroutine associated with a receptive one of said parameters in a respective parameter set and to its corresponding status bit;
assigning each set of parameters to a different one of a plurality of differing priority branch on bit instructions of the system; and
in response to the execution of each one of said differing instructions,
selecting a set of status bits, priority values and branch addresses corresponding to the parameter set assigned to the instruction being executed,
comparing the selected priority code values which are set to their active states,
determining the highest one of said compared priority code values, and
selecting the branch address to the subroutine associated with the active status bit having said highest compared priority code value.
Background of Invention.....
Related Patent Applications...
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Prior Art.............
Summary of Invention.........
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Patent application Ser. No. 254,986 by B. D. Mandalia et al, filed at the same time as the present application, discloses a processor that provides structures and instructions dedicated for efficient processing of header and frame information parameters in all levels of todays layered protocols; e.g. parameters characteristic of Open Systems Interconnection (OSI) protocols. Certain aspects of the disclosure of the application apply presently and are incorporated herein by this and subsequent references.
The field of invention is computer architecture with emphasis to branch processing. Microprocessor technology for real time programming environments is considered an environmental basis for this architecture.
Priority branching methods have been used for interrupt mechanisms. U.S. Pat. No. 4,636,944, 4,315,314 and 4,573,118 disclose such usage, and indicate recognition of the importance of using priority branching to reduce processing time for scanning and polling interrupt requests. However, these do not address key issues of process branching for which the present invention has been devised.
Where the art provides for priority branching only on fixed parameters such as interrupt bits, the present invention provides for branching on variable branch condition or status parameters selectable by program instructions.
Where the art provides for priority branching only in a fixed priority ordering of active parameters, the present invention provides for varied priority ordering which the user can set by programming.
Where the art provides a fixed relation between branch condition parameters and associated target addresses of instructions to be branched to, the present invention provides for user-variable associations between branch condition parameters and addresses of target instructions (also referred to hereafter as branch addresses).
The present invention provides a mechanism for executing priority branch on bit detection (BBD) operations, in response to a newly defined BBD instruction. In such operations, a set of status bits representing branch condition parameters is evaluated to ascertain which currently represent active conditions requiring branch program action, and of the latter which should be given priority. The output of this mechanism is a branch address representing the starting instruction of a branch program segment associated with the selected status bit.
Features of the priority selection process and associated circuitry embodied in the present invention are their accessibility to user program variation. Registers determining relative priorities of the status bits are dynamically loadable, under user program control, with different patterns of priority selection codes, and registers presenting the status bits to be evaluated are also loadable under program control. Thus, a single BBD circuit unit may be shared dynamically by multiple sets of status functions. Furthermore, as conditions vary in relation to a given set of status bits currently presented for evaluation, or as different sets of status bits are presented for evaluation, contents of the registers determining priority ordering can be suitably varied.
Another feature hereof is that branch addresses which are selectable as the ultimate output of such BBD circuitry are stored in a stack of registers which are also accessible to dynamic change by user programs. Thus, as conditions associated with a given set of status bits change, or as a new set of status bits is presented for evaluation, a suitable associated set of branch target addresses can be loaded.
A feature of one disclosed embodiment is that the registers for holding branch addresses and priority selection information may be extended in capacity to hold plural sets of respective parameters associatable with plural sets of status bit functions. Thus, the frequency of register loading operations required to adapt to different conditions can be reduced.
Another feature of a presently disclosed embodiment of the invention is that it reduces the normally complex series of operations associated with priority branching to a simple operation executable in a single clock cycle (machine cycle) of the system in which it is used.
Another feature is that registers holding priority determining functions and address information are arranged for access in direct one-to-one correspondence with individual status bits, so that the number of registers needed is considerably less than would be required if the status bits were to be used in combination to address registers in a table lookup mode.
These and other advantages, features and benefits of the invention will be more fully understood as this description progresses.
It is also an aim of this invention to provide for priority branch on bit circuitry to be arranged in a manner to facilitate execution of the complete priority branch operation (including priority selection and address selection action elements) in a single clock cycle of the associated data processing system, whereby such operations when frequently encountered in a processing system can be performed at enhanced throughput rates.
FIG. 1 illustrates a Communications Protocol Processor for layered protocol processing (reference Ser. No. 254,986 above) in which the present invention can be used to advantage.
FIG. 2 illustrates a prior art technique for parallelism and pipelining to speed up processing.
FIG. 3 illustrates the communication environment in which the CPP is expected to operate.
FIG. 4 illustrates a header processing unit of the CPP in which the present invention is used as a component circuit.
FIG. 5 illustrates the branch on priority bit detect processing unit in the CPP which represents one embodiment of the present invention.
FIG. 6 illustrates a programmable priority address circuit for use in the branch on bit detect unit of FIG. 5.
FIG. 7 illustrates use of multi-segment stacks in the subject branch on bit detect unit.
FIG. 8 illustrates address generation for a register stack useful in the subject unit.
FIG. 9 illustrates a stack useful in the subject unit and its access decode mechanism.
FIG. 10 illustrates a mechanism for identifying and encoding the highest priority input bit using discrete logic.
As environmental background, FIG. 1 shows the overall architecture of a communications protocol processor (CPP) in which the subject invention can be used beneficially. The CPP contains both special purpose circuits geared towards increasing throughput for certain complex and frequently encountered operations, and general purpose circuits including a more or less conventional ALU (arithmetic logic circuit). The special purpose circuits include a branch on bit detect (BBD) circuit constructed in accordance with the present invention.
In respect to general purpose circuits, ALU unit 1 supports basic arithmetic operations (ADD, SUBTRACT, COMPARE), logical operations (OR, AND, XOR), and register transfer operations. Multiplier unit (MUL) 2, operating in coordination with the ALU, supports 16 by 16 multiplication with scaling and rounding functions.
Memory access unit 3, header processing unit 4, and frame processing unit 5 provide special purpose operations. Of particular interest presently is a portion of the header processing unit providing BBD (Branch On Bit Detect) operations.
Other CPP elements include a general purpose data register stack 6, and an address index register stack 7. These comprise portions of internal variably allocatable storage that can be used as input and output for processing units 1-5 using control bus 12 and data bus 13.
Control Unit 8, containing elements 8.1-8.7 shown in the lower portion of FIG. 1, controls and monitors operation execution. Instruction register 8.1 receives instructions from instruction memory (IRAM) shown elsewhere via instruction data bus 17. Instruction operation codes (opcodes) in the instruction register are gated to decoder 8.2 which generates control signals to units 1-5 through control bus 12 and provides immediate data or address information via data bus 13. System clock 8.3 provides timed control signals to the other elements. Fetch controls 8.4 at clocked intervals direct instruction fetching action relative to IRAM. Data bus 13 consists of a multiplicity of bidirectional data paths allowing for parallel transfer of data between register stacks 6 and 7 and process units 1-5. Program counter 8.5 and next branch (or interrupt) control logic 8.6 generate next instruction addresses, one of which is selected by multiplexer 8.7 for application to IRAM via IRAM address bus 16. Data address (DA) bus 15 is used to connect memory access unit 3 to Data Ram (DRAM, also shown elsewhere), for transfer of memory data via bus (GD) 13.
Parallel execution of operations designated by instructions is possible using pipelining techniques suggested at 20 and 21 in FIG. 2. While instruction `n` is being executed next instruction `n+1` is being decoded and its next instruction `n+2` is being fetched as shown at 20. In addition, if three operations are called for by one instruction, their decoding and execution may be performed in parallel as suggested at 21. Bus transfer mechanisms and pipelining techniques for such operations are well known and described in "additional references" (1), (3), and (4) above.
FIG. 3 illustrates a typical application environment for the CPP, the latter shown at 31 in this FIG. Data Ram 32 (also termed DRAM) interfaces with multiplexor and input/output interface 33 to exchange data with physical communication interface 34. Instruction Ram 35 (IRAM) stores instructions of application programs that the CPP supports and allows dynamic execution of functions required at interface 34. Host interface 36 provides a systematic handshake for flow of data and control commands to and from a host processing system. Block 37 represents layered protocol applications and signal processing functions which can be integrally accommodated in this environment.
FIG. 4 depicts components of header process unit 4 which perform unique operations on packet header parameters in each protocol layer. The subject of the present invention, branch on priority bit detect (BBD) unit 60, performs priority branch on bit detect operations relative to communication status bit parameters contained in headers within each protocol layer. This mechanism performs its operation of priority bit selection and target address retrieval in a single CPP machine cycle, thereby enhancing throughput relative to high speed communication media. However, the same mechanism and its underlying method of operation are considered universally applicable to other processing systems and applications; as should be more fully appreciated from the following description.
Other special purpose units within header process unit 4 include register reshape unit 61, for rearranging registered header data to extract parameters related to the registered data but by known transformations, and address routing unit 62 for translating header address information for message routing purposes. These units and the CPP overall structure are more fully described in the cross-referenced patent application for "Specialized Communications Processor For Layered Protocols", and the remainder of this description will focus primarily on the structure and operation of the subject BBD unit 60.
In response to a special BBD instruction discussed later, BBD unit 60 evaluates multiple status bits and selects a target branch address associated with one of the bits. The bits represent conditions which are either active or inactive and which when active require special action via branch program segments. The bits representing active conditions are evaluated in a predetermined order of priority and the target address selected is one associated with the bit having highest priority.
A circuit embodying general characteristics of the unit 60 is shown in FIG. 5. Since it performs its priority branch address selection operation in response to BBD instructions, this circuit is called the BBD Instruction Execution Circuit. Information in input latch 80 is processed for priority bit branching to a destination address using priority address mechanism 81, output of which is transferred to output register 82. Stack initialize register 83 is used to initialize branch address stack elements (shown elsewhere) in priority address mechanism 81. Decoders 84 and 85, responsive to a BBD instruction opcode on control bus 12, generate signals for gating priority branch status bits in input latch 80 to priority address mechanism 81 and also to latch the branch address extracted from the priority address mechanism to branch address register 82. Decoder 84 responsive to a register transfer operation via data bus 13 generates a signal to load stack initialize register 83. Thus, the contents of the branch address stack are alterable by programming to adjust the branch address selections to associate variably to the status bits in latch 80.
FIG. 6 is a schematic showing of principal block elements of the priority mechanism 81 of FIG. 5. Such elements include a priority select register stack 102 within a priority encoding unit 103, and a branch address register stack 104 within associated access decode mechanism 105. Both register stacks 102 and 104 are loadable with new information by programmed register loading operations conducted through bus 107.
Acting in response to BBD instructions, unit 103 selects a priority designating code value from one of the registers in stack 102 and applies it as an addressing input to stack 104, whereby a selected branch address is transferred to output register 82. The input latch bits are applied individually to different registers in stack 102, and the bits representing active branch request conditions gate out contents of respective registers in the stack. The operation of unit 103 effectively compares the magnitudes of the values gated out from stack 102, such values effectively denoting the relative priorities of respective input latch bits, and selects as access input to stack 104 the value with highest magnitude. Thus, the branch address selected from stack 104 corresponds to a currently active highest priority bit in latches 80. Since the contents of stack 102 are loadable by programming, it should be understood that the relative priorities accorded to the input latch bits are correspondingly variable.
Furthermore, since the contents of registers 104 are alterable by programming, it will be understood that associations between bits in latches 80 and branch addresses extractable by mechanism 105 are correspondingly variable.
Another feature of the circuit composed of units 103 and 105 is that it can be easily arranged to complete its entire operation of priority determination and branch address extraction in a single "machine" or clocking cycle of the processing system in which it is used. As a result, frequently encountered complex branch on bit detect operations can be rapidly performed and thereby improve system throughput. This is particularly beneficial in processing systems interfacing to high speed communication media, as described in cross-referenced application above for "Specialized Communications Processor for layered protocols".
Yet another feature of the mechanism 81, illustrated in FIG. 7, is that the stacks 102 and 104 can be enlarged to segmented stacks 110 and 111, respectively, in order to allow for preloading segments of such stacks simultaneously with priority determination information and/or branch address information associated with multiple sets of conditions or events represented by the bits presented in input latches 80 (FIG. 5). Thus, differently coded BBD instructions designating individual stack segments can be executed repeatedly to evoke actions associated with different sets of branching associations, without having to reload the stacks between repetitions.
FIG. 7 shows how the priority selection stack 110 and branch address stack 111 may be segmented to accommodate multiple sets of different respective data types. FIG. 8 shows logic 112 for accessing such stack segments, wherein the desired segment is selectable by a data type code, and the branch address selection within the selected branch stack segment is made by the output of the priority encoder. For this purpose, the data type code could be provided either as part of the instruction opcode or as part of the operand information accompanying or designated by the opcode. This may be predefined or coded within the instruction set, depending on resources of the instruction set. The width of the data type code (T) is dependent on the number of data type segments desired (N), and defined by T=log2(N).
FIG. 9 shows a mechanism to access the various stacks for initialization and direct execution of the BBD instruction. To initialize the branch address stack, decoder 118 processes signals from control bus 12 associated with register loading instructions, to load data from input bus 115 into appropriate registers 116. For read access from this stack, priority encoder 103, responsive to a BBD instruction, supplies a priority encode address to 118 directing, branch address data to data bus 13 via output path 119. In order to support multiple protocols, stack 116 may contain plural sets or segments of branch address registers for relating different branching functions to conditions in input latch 80. As previously noted, this requires definition of different BBD instructions for branch on bit detection to different stack segments/protocols.
Implementation of a programmable priority encoder 103 is illustrated in FIG. 10. A plurality of bits from input latch 80 (FIG. 6) labeled bits 1 through 16, serve as selection control inputs for the priority encoder. Each input bit has an associated priority register 120x; where register 120a is associated with input bit 1, 120b with input bit 2, etc. Each priority register 120x may be initialized responsive to one or more register loading instructions of the processor, such as Data Move instructions (Register to Register or Memory to Register),or Load Immediate instructions. Multiple registers 120x may be initialized in parallel since the processor bus width will typically be wider than the length of a single priority register.
The purpose of initializing priority registers 120x is to set into each a unique priority code to associate under user program control with the condition represented by the respective bit from the input latch 80. Since there are 16 input bits in the example, 4 bits are required to assign each of these inputs a unique binary code number. In general, N bits are required in each priority encoder to handle 2 to the Nth power input bits. Such programmably assigned N bit numbers in registers 120x are evaluated by logic to which the register outputs couple in a manner such that of the numbers associated with input latch bits currently having active or ON states, the number with the largest binary magnitude will be selected for application to the selection input of the branch address stack, and thereby the selected branch will be associated with an input bit programmably designated (by system users or others) as having highest priority.
Once the priority registers 120x, the address register stack (not shown), and the input latch 80 (supplying input bits 1-16), have been loaded, the circuit is ready to execute the priority branch BBD instruction. In doing so, the array of logic gates shown in FIG. 10 will determine which of all the input bits which are "ON" is associated with a priority number with largest relative magnitude. This number is gated to outputs P0, P1, P2, and P3 (P3 being the most significant bit) which are used to address the register stack 116 (FIG. 9) in order to select an associated branch address.
More specifically, operation of the array of gates proceeds as follows. Each active or "ON" input in the set of input bits 1-16 from latches 80 enables the four-bit output 121x of the associated priority register 120x to be transferred to the associated row of gates 122x-127x. Input bits which are inactive or "OFF" will force outputs of associated priority registers to be all zeroes or "OFF". Outputs from priority registers 120x are compared by respective rows of gates, starting with the most significant bit.
OR gate 129a examines the most significant bits of the outputs of all priority registers 120x, and sets its output P3 "ON" if at least one of its inputs is "ON". If all inputs to this OR gate are OFF P3 is set OFF. P3 feeds back to Compare circuits 122x in each row (122a, 122b, 122c...), and causes further transfer of an ON condition through such compare circuits in each row where the most significant bit output from the respective register 120x is equal to the state of P3. Thus, if P3 is ON, then in each row where the highest order output of respective register 120x is ON, respective compare circuit 122x will have its output ON, and in all other rows, the outputs of respective compare circuits 122x will be OFF. On the other hand, if P3 is OFF, then presumably all highest order outputs of 120x are OFF and all compare circuits 122x will have their outputs ON.
ON outputs from compare circuits 122x partially enable respective AND circuits 123x, having as other inputs next most significant bits out of respective registers 120x. Thus, in any rows where respective AND circuits 123x are partially enabled, outputs of such AND circuits will correspond to the states of the respective next most significant bits out of respective registers 120x. Outputs of AND circuits 123x connect to OR circuit 129b which produces output digit P2, which couples back to compare circuits 124x in each row. Outputs of 124x enable respective AND circuits 125x which have as their other inputs third most significant digit outputs of respective registers 120x.
Outputs of AND circuits 125x couple to OR circuit 129c producing third most significant result output digit P1. The latter operates through compare circuits 126x and respective AND circuits 127x to evaluate respective least significant bit outputs of registers 120x. Outputs of 127x couple to OR circuit 129d determining the least significant result output P0.
It may be appreciated that the combination of digits P0-P3 will have a value corresponding to largest magnitude value in the registers 120x, since in any position where the output digit Pj is 1 the next most significant digits in any row will be evaluated further only if the digit from 120x corresponding to the order of Pj is 1. In all other rows all lesser significant digits will have no further effect on the less significant digits Pi (i<j). Since no two registers 120x will be set with the same combination of bits, it follows that one and only one register output will determine the ultimate value of all four digits P0-P3, and that register output will be the one with the highest numerical value.
As mentioned previously, outputs P0-P3 are used to address the branch address stack with an encoded address representing the priority number associated with a highest priority active input latch bit. This results in a one to one positional correspondence between addresses in the address stack and priority levels programmed into registers 120x. Alternately, outputs of circuits in FIG. 10 may be used to develop signals positionally associated with input bits 1-16 for direct application to individual registers in the branch address stack, and such outputs when active would directly gate contents of the respective branch address registers to the stack output.
This arrangement would require addition to the row logic circuits of FIG. 10 of not-shown compare circuits 128x (positioned to the right of respective And circuits 127x) for comparing least significant bits in respective registers 120x with P0, and And circuits 129x responsive to outputs of all respective compare circuits 122x, 124x , 126x and 128x for producing respective control signals for direct application to respective register output gates in the branch stack.
Note also that the lowest priority bit, with associated number=0, results in the same branch as if no bits are set. Thus, as shown, only 15 unique branch bit conditions can be set. Simple logic can be added if needed to check for all zeros from input bits 1-16, and gate to the branch address stack an associated different register select signal function on occurrence of that condition; if 16 unique branch address selection functions are needed. A 16 bit NOR gate, providing an active output if all input bits are zero, could be used to degate the register corresponding to the lowest priority, even if P0-P3 indicate it should be selected, and further used to select output of a not-shown 17th register within the Branch Address Register Stack.
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XR650R Thread!
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Gnarly Adventurer
Joined: Jan 2003
Location: Ontario Canada
Oddometer: 203
I've just basically finished the electrical work on my 05. I used a Tusk lighting kit from Rocky Mtn Cycle. The harness alone is just $29 if you just need that. The Tusk kit is a battery operated only system which I modified to work with a Ricky Stator dual output stator and reg/rec. I went with an ac/dc system and kept the stock harness mostly in tact. I've also added a key switch, KTM fan (dc) and grip heaters (ac) and will add a gps connection as well.
I bought OEM style connectors from
which really helps making a quaility job.
If you do a Google search for XR650R wiring diagram you'll get lots of choices. I more or less copied a wiring diagram for a 1984 XL250 for my project.
Hope that helps.
Originally Posted by
Can anyone share their wiring diagram?
My XRR is currently wired for a headlight, tail light, brake light and turn signals. It has a re-wound stator and a mini-battery. Plus, the current harness is a rat's nest of PO's additions and subtractions. Everytime I have to work on something I have to diagnose why something electrical isn't working because something jiggled loose. I would eventually like to add brighter and/or additional headlights and some 12V accessories, as well as a real battery (probably a small Ballistic). I'll probably also add a Trail Tech, but that's its own deal. What are you guys running for wiring harnesses? Are there any good aftermarket harnesses? Also, if there's some issue where I can't run all of the accessories at once (stator/battery limitations), that's totally fine.
Lastly (semi-unrelated), I used to be able to turn my lights on when the bike wasn't running (on battery power) and now I can't. In between "now" and "then" I rebuilt my whole engine and transmission so my bike wasn't running for a few weeks. At first I assumed the battery had gone weak from sitting, then I started thinking I put it back together wrong. Everything works as it should when it's running, but I get nothing when it's off. I figure if I'm going to gut and re-wire the whole thing this doesn't really matter.
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This Homemade Hovercraft Is Amazing [VIDEO]
Check out this little dude just living the dream on his very own homemade hovercraft! this little kid has no idea how lucky his is to be gliding across the earth on a pillow of air.
Fox Taunts Dog By Stealing His Toy [VIDEO]
Check out this fox pulling the ultimate power move. I imagine this is how Terry Benedict felt when he watched George Clooney rob his Las Vegas safe on his security cameras.
Armadillo Crushing The Adorable Game [VIDEO]
Check out this armadillo just completely taking the cuteness mountain and climbing its way to the top like King Kong.


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Modify a Mini-B USB Cable to Power an Enclosed GoPro Hero3 (With Skeleton Back Door)by zplus
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this motel is very beautiful and is a very friendly environment. i would reccomend it to anyone. the beds are very comfortable to sleep in, the rooms made me feel right at home, and the people made me feel very comfortable there.
- Official Description (provided by the hotel):
- Dear Guest, we are located near UCR1 mile from Riverside Convention Center/Downtown/Court House, 25+ restaurants within a mile, Movie theater .5 miles. We welcome PETS in limited rooms, please ask the front desk. FREE Wi-fi, Cable TV with 80+ channels, Refrigerator and Microwave available. ... more less
- Reservation Options:
- TripAdvisor is proud to partner with Booking.com and Priceline so you can book your Budget Inn Riverside reservations with confidence. We help millions of travelers each month to find the perfect hotel for both vacation and business trips, always with the best discounts and special offers.


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Lewis Ben Williams
Position: DT
Height: 6-2 Weight: 275 lbs.
Born: May 28, 1970 in Belzoni, MS
High School: Humphreys Co.
College: Minnesota (school history)
Weighted Career AV (100-95-...): 0 (14747th overall since 1950)
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1998 Game Log: Regular Season · Playoffs · vs.


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Select Local Merchants
Dance HaddonfieldRead MoreSignature service: Group Dance Lessons Established: 2012 Staff Size: 2?10 people Average Duration of Services: 1?2 hours30 Tanner StreetHaddonfield, NJ US
Artists In Motion Dance and Fitness StudioRead MoreMichele Wolf has been called many things, including Clara, Pixie, and a meteorite. At 12 years old, she had snagged the principal role in The Nutcracker and stole the show dancing in A Planetary Interplay and A Unicorn of Fairy Forest. Today, Wolf pours her choreography and professional experience into Artists In Motion Dance and Fitness Studio. She and her staff impart the fine art to adults and kids, teaching the fundaments of ballet, jazz, and tap. Meanwhile, fitness instructors lead all kinds of heart-starting sessions, such as Zumba, kickboxing, Barre classes, which blurs the line between fitness and dance and what's an appropriate closing argument for a defense attorney. Kids? classes, meanwhile, focus solely on the arts; the curriculum includes ballet, tap, and musical theater. The studio is also home to a dance troupe and plays host to little ones? birthday parties.16 Rockhill RoadCherry Hill, NJ US
Candlelight Dance ClubRead MoreSince opening in 1975, Candlelight Dance Club has chased a single, unwavering mission: to curate an appreciation for ballroom dance while teaching its many styles. Six instructors stand ready to lead dancers through training to conquer foxtrot, swing, tango, waltz, and rumba steps. By offering both private and group lessons, Candlelight combines one-on-one attention from an instructor with group sessions that provide more camaraderie than a firefighting team moonlighting as a cheerleading squad. A bright, wood-floored studio hosts classes as well as the club's weekly dance parties, which allow participants to try out learned moves in real time before debuting them in public. Many dance enthusiasts note a handful of dance-inspired benefits as their confidence shines, stress fizzles, and cardio endurance boosts.Ellisburg Shopping CenterCherry Hill, NJ US
Tricia Sloan Dance CenterRead MoreTricia may be the primary face of the Tricia Sloan Dance Center, but anyone who gets to know the company will also get to know the other Sloans?every member of the family is involved. The previous generation, Patti and Jim, opened the school as the Leonardo Dance Studio four decades ago. Their daughter Shannon handles accounts and assists with productions, and even youngest child Tim has a job when he's not studying dance and attending high-school classes: managing the Tim's Drinks concession stand. As for Tricia, she's uniquely equipped to teach both good form and expressiveness on stage?she's also an actress who's appeared in The Stepford Wives and on Law and Order: Special Victims Unit.1 W Mantua AveWenonah, NJ US
Flaunt FitnessRead MoreLauren ?Pinki? Schiavo began her pole career as a student at Poise Dance Studio in 2005, and her spinning skills soon blossomed and earned her an instructor position. When the studio's owner sold the space, Lauren took the helm and injected some sass into the class regimen, renaming her business Flaunt Fitness as an homage to empowered women of all ages and body types. She drew from her training in jazz dance, hip-hop moves, and gymnastics to augment her pole-dance prowess and recruited a squad of professional teachers to lead her schedule's shimmies. Flaunt Fitness' classes impart pole twirls and calorie-dropping cardio workouts under one roof. The DVD Fitness classes screen popular exercise videos as instructors ensure that guests maintain good form, and private parties spice up dance lessons with champagne and making balloon animals with just your feet. Further slimming figures, the studio sustains a support network for members with monthly encouragement meetings sharing healthful recipes and nutrition products for purchase.1939 S. 17th StreetPhiladelphia, PA US
Living Arts Dance & Fitness StudiosRead MoreLiving Arts Dance Studios offers dance lessons for children and adults, along with self-defense, karate, and kick-boxing lessons. The philosophy of Living Arts Dance Studio is that dance can benefit children by introducing them to performing arts at an early age. Their mission is to help young children find positive outlets for their energy so they will do well later on in life. Studies have proven that kids who get involved in music, art and dance at young ages do well in their other scholastic studies. Living Arts Dance & Fitness Studios also takes adults who are ready to learn some new moves. They stress that dance is an excellent way to have fun and stay fit. Adult classes include praise dance, Zumba, African dance, belly dancing, boot camp and many more.81 Fairmount AvePhiladelphia, PA US


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Photo by John Kernick
YIELD: Makes 6 servings
ACTIVE TIME: 45 min
TOTAL TIME: 45 min
Heat butter in a deep 12-inch heavy skillet over medium-high heat until foam subsides, then cook scallions, stirring occasionally, until softened, about 5 minutes. Add corn and 1/2 teaspoon each of salt and pepper and cook, stirring occasionally, 5 minutes.
Stir together cream and cornstarch in a small bowl until thoroughly combined, then add to corn and simmer, stirring, until slightly thickened, about 3 minutes. Transfer 1 1/2 cups corn mixture to a blender with garlic and purée until smooth (use caution when blending hot liquids). Return to skillet and cook, stirring constantly, until just heated through.
Transfer corn to a large shallow serving bowl and sprinkle cheese and cilantro over top.


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I'm sitting here mumbling Iggy Azalea rap lyrics to myself (see the song here, but only if you are down with very sexual content, explicit language, etc. etc. DON'T SAY I DIDN'T WARN YOU) and thinking about beauty habits. Mainly, I was wondering why I had a box of baking soda in my bathroom because I damn sure wasn't using it to clean. Although, I probably should. Thinking about the baking soda made me think of other beauty habits or "tips" I used to think were great for my skin. Baking soda was definitely something some random pic on Pinterest told me to use on my face. WHICH WAS WRONG, HORRIBLY, HORRIBLY WRONG!
Baking soda is not only too rough for facial skin but throws your skin's PH balance way off. Having too alkaline of a substance like baking soda on your face breaks down the natural sebum your skin, causing it to be less protected against bacteria and infection. Too acidic of a product (lemon juice or something similar) will burn your skin. It's important to research skin tips before you try them. The first time I tried using baking soda as a facial scrub I was absolutely in love. My skin felt SO SMOOTH. And, I wonder why? Because I had rubbed off so much skin. A little bit later I found myself with irritation and new pimples. Of course, if you use baking soda and really love it, go on keep using it if you'd like. However, there are much better products, homemade or from a brand, that will do the job and not throw your skin off-balance.
So, what else do I personally dislike as a "beauty tip"? For starters, I hate any tip that assumes whatever the tip is "fixing" needs to be fixed. If you have dark circles or crow's feet, don't feel like just because you saw something on how to reverse or hide them that it means you need to follow it. There's absolutely nothing wrong with our faces or bodies. I enjoy make up and skincare because I like the self-soothing aspect of the process, the creativity in my everyday life it provides, and maintain the general health of my biggest organ…the skin if you haven't ever read a "Did You Know?" article or had a 5th grader who just studied biology talk to you.
The third beauty tip that I rarely follow is to get a trim every few weeks. No, if your hair is healthy and you don't have split ends you don't need to get your hair cut. Save your money and buy better hair care products to prevent those split ends. They're the only reason you NEED to have your hair cut. And, YOU CAN'T REPAIR SPLIT ENDS. Nothing is going to bind them back together, sure something might temporarily bind it for an hour or something, but NOTHING WILL EVER REPAIR YOUR DAMAGED ENDS! I'm sorry, I hate to break it to you, but you have to cut them and start over on your hair-growing battle.
It sucks, I know, just lay of the flat-ironing and bleaching for a bit if you can. Throw a little argan or coconut oil in them at night and FOR THE LOVE OF GOD DON'T RUB YOUR TOWEL ON THEM TO DRY LIKE YOU'RE SCRUBBING A WET DOG! Be gentle! Softly squeeze the water out. No back and forth crazy motions so you end up like you've got a rat's nest on top of your head. My mom (she's a hairstylist) used to get so mad at me when she'd see me do this in middle school. I think back and cringe at the damage it was doing!


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"You're outdoors, instead of being at a theme park or something...," said John Dotson, who visited the show with his wife looking for an entry-level RV in the range of $10,000 to $15,000, "Instead of relying on something else to entertain you,"
He said he has never owned an RV but thinks now is the right time to buy one.
Another Michigan resident at the show, Larry Nethot, said he was looking for a replacement RV. He and his wife are former backpackers and they need a new RV because she no longer likes the outdoors. "Our parents stole our retirement home, so we've got to find another place to sleep," he said.
Nethot checked out an RV that had an LCD television, DVD player, a kitchen dinette and other home furnishing in it. "I like the outdoors but my wife can no longer stand it at the camp, " he said.
The RV is a compromise for the couple.
Jeff Rank, the president of Prime Time Manufacturing in Wakarusa, Ind., attended the Novi show and was delighted with interest from prospective customers like Dotson.
"The traffic is awesome," he said. "Let's face it, the last couple of years, it's been a struggle. People seem to be in a better mood."
Rank sells the impressive high-end LaCroose RV, which is 35 feet long and features a 26-inch LCD screen inside. That people are looking to buy some of the high-end RVs is a real sign the industry is back on track, he said. "You're already seeing the comeback in wholesale shipments to dealers," he said. "It's about a 50 to 60 to 70 percent increase in shipments."
Rank's family has been in the RV business since 1969 and he says the past few years have been one of the worst periods he has seen in the industry. "It seems like every decade we have had a 10-, 12-year run that has been whatever the U.S. economy is doing, our industry is doing."


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Gear Question
Joshua Levine
Hey just checkin out some goggs and was...
Hey just checkin out some goggs and was wondering what the differences were beween the iris and the DH from POC?
KC Gaudet
The DH version has the little nubs for the tear-off sheets. Otherwise, I believe they are the same goggle.
View More Details on POC Iris Flow Goggle


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First shot :)
Don't forget to check the attachment !
Capitaine Job is a marketplace which allows students working with small companies. We're oriented on customer service excellence and high-quality deliverables.
Logo made by the awesome @Rokas Sutkaitis
More Axel Bouaziz
keyboard shortcuts: ← previous shot → next shot L or F like Z toggle zoom


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So, it looks like my texture packs will soon be available through a platform that's quite dear to my heart. I'm working on a little something to celebrate and demo what my photocopy noise texture pack can do, using the Awaken tee design pack as a starting point.
The x2 view is a 100% crop of the result. On the left with textures, on the right without.
keyboard shortcuts: ← previous shot → next shot L or F like Z toggle zoom


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Originally written on Bush League Chronicle | Last updated 2/19/13
Injured Philadelphia 76ers center Andrew Bynum spoke with the local media on Tuesday to give an update on his rehabilitation progress (or lack thereof). For the record, Bynum has yet to play in an actual game for the 76ers this season. It appears as though he has spent the regular season managing his hair style, instead. The photo above is a look at Bynum's latest style. I'm not sure what you would call that. Perhaps it's a hybrid between his old flattened afro and his carefully-braided corn rows. Or maybe his interview session fell in between his daily hair maintenance time and he had little time to improvise. The world may never know. Via Deadspin
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So what's the big deal about breeding purebreds? You put two compatible dogs alone together in a room, lower the lights, put a Barry White CD on the stereo and voila, two months later you've got yourself a litter of purebreds-and the rest is gravy, right? Not quite. Simply breeding dogs takes considerable space, time, and capital. Consistently breeding mentally and physically sound purebreds, on the other hand, is a labor of love that involves all of the above and… (more)
Publisher: For Dummies (April 27, 2011)
Format: EPUB
Page count: 336 pages
File size: 13.9 MB
Protection: DRM
Language: English


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Author has written 1 story for Harry Potter.
Hi folks. Welcome to my author page here at FanFiction.net. I'm currently writing a fic called Harry Potter and the Remnants of the Soul. I started a webpage for the story at The latest, most up-to-date version of the story can be found there.
Harry Potter and the Remnants of the Soul
By Byron Clarke (a.k.a. Cubdom, Pestilence, Torbenstools)
Summary: On Hiatus, Post-HBP, The final battle arrived more quickly than anyone expected. Voldemort's miscalculation granted Harry a victory, but one deeply tainted by loss. Piecing together his shattered soul, Harry must finish school and step into a society where he wields incredible power, wealth, and responsibility.
Plot Synopsis: After Dumbledore's funeral, the trio returns to London on the Hogwarts Express. After spending some time together, they go to their various homes for the summer.
On Harry's birthday, they are all together at the Burrow planning their trip to hunt down the remaining Horcruxes. Voldemort, however, crashes the party and a ferocious battle occurs. As the smoke clears off the battlefield, Harry's world is turned upside down by the loss of many who were close to him.
Battling depression, Harry must figure out what to do with the remainder of his life. Fortunately, Minerva McGonagall steps in as a mentor and convinces Harry to return to Hogwarts as Head Boy.
Returning to school proves therapeutic for Harry. No longer being harassed by Voldemort, Harry is free to live the life he once longed for. Along the way, Harry finds love in the arms of a Hufflepuff, which helps him to face the challenges of adulthood in wizarding England.
Politics, Quidditch, and the media are in our hero's future.
A Little More: The primary pairing in this fiction is Harry Potter/Susan Bones. It is classified as General/Romance and is generally regarded as a political!Harry fic. Despite its dark beginning, the story is not intended to be an angst-filled 'Woe-Is-Me' tale. Instead, the plot focuses on Harry's recovery from an incredibly traumatic event. He struggles at first, but new friends and acquaintances emerge to help him as he grows up.
Harry is a powerful wizard, but not a superpowered mage. I have endeavored to paint a rich portrait of Wizarding society, history, theory, government, politics, and business. I am an accountant and a political science enthusiast. As such, my story plays to my strengths. There are lots of discussions about bloodlines, hereditary power, money, government, civil rights, family roles, and wizarding history. I hope you like it!
This story does not contain slash (homosexual) relationships.
The language employed has been rated Teen or PG-13 depending on which rating system you favor. For the most part, the language is squeaky clean, but there are a few occasional phrases that may not be suitable for those under the age of 13.
My Favorites
My favorite stories in Harry Potter Fan Fic Fandom are Resonance by Greengecko and Harry Potter and the Emerald Tablet by Lady Alchymia. Greengecko is an unbelievable writer with a very good plotline. Lady Alchymia is likewise, unbelievably good. Finally, I should mention another favorite: Reign of Power by Fayr Warning. This story is very imaginative and I have borrowed concepts from it.
|Lengthy, Well Written, Compelling Harry Potter
|Books Harry Potter


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Best Buy Fashion #9571
Release Date: 1/1/1976
Product Code: 9571
The long sleeveless dress with white lace trim around the neckline was fashioned of pretty, woven, red and white floral fabric. Three rows of lace accented the hem.
All images and descriptions courtesy of Collector Books, publisher of "Barbie® Doll Fashion: Volume 3" by Sarah Sink Eames.
Production doll may vary from the photo shown above. Mattel reserves the right to modify the fashion/fabrics, sculpt, hair color/style, and accessories. Doll cannot stand alone as shown.
Collector Photos
No one has uploaded any photos.


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Boxee Box all set for Apple AirPlay video streaming22 March 2011
Boxee Box owners prepare to be excited. Boxee Box owners who also own an iPad prepare to be double excited - VP of Marketing for Boxee, Andrew Kippen, has confirmed that new software is coming to the D-Link box and that a new iPad app will be able to... >>
Boxee for iPad app hands-on7 January 2011
Boxee is working on an iPad app to enhance the current remote app experience and make the iPad more of a companion to your TV viewing; fortunately Boxee has given Pocket-lint a walk-through of the new features we can expect to see when the app goes live. ... >>
Boxee in a different box with Iomega TV4 January 2011
Boxee has announced its second hardware partner - adding storage specialist Iomega to its current partnership with D-Link. Just like the D-Link Boxee Box, Iomega TV offers up a Linux-based operating system, with the Boxee media centre software fully loaded.... >>
KinEmote: The Kinect powered Boxee remote24 December 2010
The Kinect has been hacked yet again, this time by coders keen to get it running on their Boxee software. The motion controlled accessory for the Xbox 360 has been turned into a controller for the media software, allowing its user to scroll through the... >>
Boxee Box fires in 3D firmware update14 December 2010
If you haven't got a Boxee Box at the top of your list to Father Christmas (that's Santa for our US readers) then it can mean only one of two things; 1. You are a fool, or 2. You've already got one. If you fall into group 2, then congratulations - you... >>
Boxee Box bashes out first firmware update26 November 2010
We at Pocket-lint are big fans of the Boxee Box, just take a look at our comprehensive review - we don't hand out the Hot Product stamp willy-nilly. But the box is a tad buggy, as most new devices tend to be. Luckily though, the chaps at Boxee are aware... >>
Boxee ditches Tegra for Atom - pre-order opens in US and UK13 September 2010
Boxee has moved across to an Intel Atom CE4100 processor from an Nvidia Tegra 2 chip for higher bitrates during 1080p playback. And with its launch slated for November, parent company D-Link is about to start accepting pre-orders through Amazon.com in... >>
VIDEO: Boxee unboxed by Boxee17 July 2010
The Boxee Box, which got a full unveiling at this year's CES and due sometime in the next couple of months has landed at the Boxee offices. "The first Box arrived from the @Boxee Factory. Here's a video: http://bit.ly/aalu5L" the company announced on... >>
Boxee returns to Apple TV25 February 2010
Boxee has returned to Apple TV claims boxee on its company blog after being ejected in the latest software update. Those who decide to dabble in the darker side of hacking their Apple TV can pwn your AppleTV following these "super simple instructions,"... >>
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Carrot Chutney
|4 Pound, peeled and sliced (24 Medium Sized)
|2 Medium
|2 1⁄2 Cup (40 tbs)
|1 1⁄3 Cup (21.33 tbs)
|Mixed pickling spices
|2 Tablespoon
|Flaked coconut
|1 Cup (16 tbs)
|1⁄2 Cup (8 tbs)
|Grated fresh ginger root
|1 Tablespoon
|Bottled hot pepper sauce
|1⁄2 Teaspoon
Cook carrots in boiling water to cover till very tender, 35 to 40 minutes.
Drain and mash.
(Measure about 5 cups.) Peel oranges and lemon.
Reserve peel of one orange and half of the one lemon peel.
Remove excess white membrane from reserved peels.
Cut peel into very thin strips.
Seed and thinly slice oranges and lemon.
In 6-to 8-quart kettle mix sugar, vinegar, and peels.
Place pickling spices in cheesecloth bag.
Add bag to kettle.
Bring mixture to boil; reduce heat.
Cover; boil gently 5 minutes.
Add carrots, orange and lemon slices, coconut, raisins, ginger root, and pepper sauce.
Cook, uncovered, over medium heat till thickened, about 30 minutes; stir often.
Discard spice bag.
Ladle into hot, clean half-pint jars; leave 1/2-inch headspace.
Adjust lids.
Process in boiling water bath 10 minutes.
(Start timing when water returns to boil.)


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Back to the Future: Hill Valley is a full conversion mod for Grand Theft Auto: Vice City. Back to the Future: Hill Valley will be based on the Back to the Future Trilogy, allowing the player to re-enact all the great moments from the films. While some parts of the story are stretched to make it more enjoyable, we are determined not to stray too far from the original story-line. The people behind this mod want the community to relive the movies and have as much fun in the process as possible. With the outstanding game play of the Sandbox hit, Grand Theft Auto: Vice City, in combination with one of the best movies of all time, Back to the Future, this mod is sure to bring countless hours of fun to anybody who enjoyed the movies.
|Discussion #2
|Thread Options
|1 2 3
|Aug 19 2007, 3:54pm Anchor
i put in the dot at the end and then i put the number zero but i want it to g oup when i move like what happens in the original speedometer
|Aug 19 2007, 3:55pm Anchor
reinstall. You're only suppose to add a dot. Not delete the old info.
|Aug 19 2007, 3:59pm Anchor
i didnt look after the original speedometer i put that dot, and then i added the number zero, now i wanna know how i can make the number zero at the end of the dot go up like the speedometer
|Aug 19 2007, 4:06pm Anchor
wait...........give me an example of what you want.
|Aug 19 2007, 4:13pm Anchor
I think he wants the decimal to go up as well. Like 87.1, 87.2 etc.
Is that even possible?
Edited by: ChaosSorcerer91
|Aug 19 2007, 4:21pm Anchor
not the way it's set up.
|Aug 19 2007, 7:09pm Anchor
that is what i want and how dose it need to be set up?
|Aug 19 2007, 7:20pm Anchor
there is no way to set it up without adding more coding, and no beginner can hope to do it. Needs more advanced coders to do that. And no, i'm not doing it, it was never in the movies.
|Aug 19 2007, 7:24pm Anchor
it was on the remote control
|Aug 19 2007, 7:32pm Anchor
just the remote control. Still not going to add it, mainly the accuracy of the code, like the fact that the time machine does not travel the instant it hits 88, but a little bit above it, so you can see 88 before time traveling instead of 87.
|Aug 19 2007, 7:34pm Anchor
oh ok then
|Aug 19 2007, 7:41pm Anchor
i tried to do it with the ~(some #)~ but when i drove it only said -1
|Aug 19 2007, 7:46pm Anchor
yeah, because the speed is an integer number, not decimal.
|Aug 19 2007, 7:56pm Anchor
meh oh well
Only registered members can share their thoughts. So come on! Join the community today (totally free - or sign in with your social account on the right) and join in the conversation.


text:
premium services
online directory
customer care
Markets :: Industrial Gases
Court Invalidates Proposed Change to Airgas Bylaws
5:47 PM MST | November 29, 2010 | Nancy Seewald
The Delaware Chancery Court has ruled that Air Products' proposed change to Airgas' bylaws that would have required Airgas to hold all future annual meetings in January is invalid. The decision is a setback to Air Products, which was counting on the next meeting to install more of its nominees on Airgas' board. A majority of Airgas shareholders actually approved the amendment at Airgas' annual meeting in September, but Airgas said that because the proposals received less than 67% of the votes, they cannot be implemented. Airgas also argued...
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text:
Thomas Lutsic, Principal
8 School Road, P.O. Box 37 Guilderland Ctr., NY 12085
Phone: 518/861-8591 ext. 1000
Fax: 518/861-5874
The 412 members of the Guilderland High School Class of 2015 and their families gathered today at The State University of New York at Albany's SEFCU Arena for their commencement ceremony. Congratulations to all of this year's graduates and best of luck in the future! LEARN MORE
Summer school
registration set for June 29
Summer school registration will be held at Guilderland High School on Monday, June 29 from 8 to 10 a.m. in the High School New Cafeteria (entrance by the West Gym).
If you have any questions please contact Ann Marie McManus at 861-8591, ext. 1200. LEARN MORE
Two slots still available for Summer 2015 Driver
Education program
There are two slots available for the summer session of driver's education. Two students will be accepted on a first-come basis. The application is due no later than 2:30 p.m. on Tuesday, June 30, with remittance. DOWNLOAD THE FORM (PDF)
GHS Common Core and Regents schedule now
VIEW the schedule (PDF)
*Updated 5/29
GHS Common Core and Regents transportation schedule now available VIEW THE SCHEDULE (PDF)
Guilderland high school juniors honored at year-end ceremony
On Thursday, May 28 in the high school LGI, 28 students from the Class of 2016 were honored during Guilderland High School's annual junior awards ceremony. LEARN MORE
Guilderland High School junior presented with 2015
Young Environmentalist Award
Sarah Jones, a Guilderland High School junior, received the 2015 Young Environmentalist Award at Five Rivers Environmental Education Center on May 28. LEARN MORE
Summer School 2015
Summer School will be held at Mohonasen High School in conjunction with Capital District Regional BOCES from July 6 through August 13 from 8 a.m. to 12:35 p.m. NYS Regents will be August 12 and 13 at Mohonasen High School. Guilderland resident registration will be held at Guilderland High School on Monday, June 29, 2015 from 8 to 10 a.m. in the High School New Cafeteria (entrance at the Athletic Entrance). If you have any questions please contact Ann Marie McManus at 861-8591, ext. 1200.
Class of 2015 Senior Ball set for June 12
Attention seniors and senior parents: The Guilderland High School Class of 2015 Senior Ball is just around the corner! The Senior Ball will be held from 6 to 11 p.m. on Friday, June 12 at the Hall of Springs in Saratoga. Get complete details (pdf)
All GHS spring sports teams qualify for 2015 Spring
Scholar/Athlete Team Award
Congratulations to the following spring sports teams: baseball, boy's lacrosse, girl's lacrosse, softball, boy's tennis, girl's tennis, boy's track and field, and girl's track and field!
GHS Junior wins video contest, trip to Washington, D.C.
Sean Quinn, an 11th-grader at Guilderland High School, has won the 2015 Vietnam Veterans Memorial Fund (VVMF) 2nd annual Memorial Day Video Contest. LEARN MORE
GCSD students participate in 2015 National History
Day competition
The annual event was held April 27 in Cooperstown, New York. The competition featured the work of several Guilderland Central School District students. FMS student Nicole Chiang and GHS student Sarah Jones took home a prize in their individual categories. LEARN MORE
Class of 2016 National Honor Society students announced
Three GHS students recognized in congressional art competition
The 20th Congressional
District invited Guilderland High School to submit three pieces of student
work into the 2015 20th Congressional Art Competition.
GHS students and teachers honored during annual YMCA Outstanding Student and Educator Award ceremony
Congratulations to the 17 Guilderland High School
students and two Guilderland High School educators who were honored at the
18th annual Capital District YMCA Student and Educator Awards breakfast,
held on April 28 at the Appel Inn.
GHS English students spend a day studying 'Night'
Students in Brenna Autrey and Danielle Benner's 10th-grade English classes at Guilderland High School engaged in a multimedia and cross-curricular study of Elie Weisel's Holocaust memoir "Night" during an event they called "A Day Into Night" on April 22.
GHS Juniors qualify for U.S. Math Olympiad
Guilderland High School juniors William Dong and William Wang will represent Guilderland High School by taking the Mathematical Olympiad (USAMO) exam, April 28-29. LEARN MORE
Guilderland students perform at regional music festival
Thirty Guilderland middle school and high school students were among the more than 300 talented musicians from 13 Suburban Council schools who participated in the Suburban Scholastic Council Music Festival at Shenendehowa High School on Saturday, April 18. LEARN MORE
Students shine in Shakespeare adaptations
Ninth-grade English teacher Colleen Ottalagano's honors students recently completed their study of Shakespeare's "Romeo and Juliet." Learn more
Applications now available for summer session of Driver Education
The summer session of the Driver Education program will run from July 1 through August 14, 2015. Learn more and download an application Completed applications must be submitted to the West Office no later than 2:30 p.m. on Thursday, May 28, 2015. The final acceptance list will be posted on June 3 in the Guidance Center, East Office and West Office.
AP exam schedule now available
June Regents schedule now available
Unified basketball team introduces new website
Still need to order your cap and gown?
Attention GHS seniors: Any student who missed cap and gown orders has two options to place their order. Either call the Jostens Customer Center (800) 567-8367 and place your order over the phone or go online to www.jostens.com. Simply type in "Guilderland" to bring up the proper school page, click on "caps and gowns" and from there just follow the prompts.
High School Yearbooks
Guilderland High School yearbooks are now on sale. You can place orders to Balfour through smart-pay.com or via mail. Any questions, please contact Julie Higgins.
Two GHS students heading to state competition
Congratulations to Guilderland High School juniors Sean Quinn and Sarah Jones, who recently took home first place honors at the regional competition for National History Day. Quinn won the top prize for his individual documentary on Pete Seeger and Jones won for her individual website about the New Deal for New York: FDR and TERA. Both students will go on to compete at the state level of competition on April 27 in Cooperstown, NY.
Administration of fall PSAT/NMSQT exams at GHS
The College Board recently changed the administration dates and options for schools offering the PSAT/NMSQT exams. During the first year of the redesigned PSAT/NMSQT, the test will be administered on Wednesday, Oct. 14, 2015. No Saturday administration will be available in the first year of the redesigned PSAT/NMSQT. This creates a difficult circumstance for Guilderland High School to administer the exam on a Wednesday, when classes are in session. Typically, more than 400 students participate in the exams. There has been no determination yet as to how the exams will be administered, but it is our intention to offer them to students who wish to take the exam. Please stay tuned for more information as it becomes available.
Seventh annual GHS Dodgeball Tournament raises more than $2,800 for local food pantry
Guilderland High School student artwork selected for Art in Three Dimensions Exhibit Learn more
Teams honored with Winter Scholar/Athlete Award
Congratulations to the following Guilderland High School athletic teams, who qualified for the 2014-15 Winter Scholar/Athlete Award: Boy's Basketball, Girl's Basketball, Gymnastics, Boy's Swimming, Boy's Indoor Track, Girl's Indoor Track, and Girl's XC Ski.
Model UN team attends annual conference at Yale
Earlier this winter, Guilderland High School sent 26 students to attend the Model United Nations program at Yale University in Connecticut. Approximately 40 schools from all over the world sent roughly 1,600 students to the conference, held the week of January 22. Learn more
Six Guilderland High School students named finalists in the National Merit Scholarship Competition Learn more
Guilderland High School student named National Achievement Scholarship Program finalist
Earlier this winter, officials of National Merit Scholarship Corporation (NMSC)announced the names of the finalists in the 51st annual National Achievement Scholarship Program. Among those honored was Guilderland High School senior Lotanna Ojukwu. Learn more
Student art work chosen for The College Board's Call for Artists Project
Learn more and view the winner piece of art work
Important information about student parking
Students may not park on campus without first obtaining a parking permit or gaining administrative approval the day before they wish to drive. Download a permit application (PDF). If a student wishes to drive for only one day, a temporary parking permit may be obtained through the West Office. Students must bring a signed letter from a parent or guardian requesting the permit and include a photocopy of the vehicle's current registration and insurance card. Any student parking on campus without displaying a current parking permit or temporary permit will be subject to disciplinary consequences, including, but not limited to, the possibility of the vehicle being towed at the owner's expense.
2015-16 Guilderland High School curriculum guide now available
Student information updates
Earlier this fall, a letter was distributed to all parents via the district's SchoolTool Parent & Student Portal highlighting some important details regarding student information updates in the new school year. In particular, the letter addresses changes to how report cards and Individual Student Reports (ISRs) for grade 3-8 assessments will be available to parents as well as information about verifying and updating your child's health information. View the letter
Join our TV crew!
Are you interested in working on the GHS TV crew to cover high school sports? If so, please send an e-mail to Mr. Maycock (email@example.com) as soon as possible. This is an opportunity to earn community service or independent-study hours while covering GHS home games.
District transitioning to paperless report cards in 2014-15
GHS introduces "Bring Your Own Device" program
Learn more about the program, including FAQs and resources for parents
Late arrival/early dismissal parental permission form
Please note that both senior students and their parents must complete a
late arrival/early dismissal permission form in order to be given senior
Download the form (PDF)
Morning Announcements now available on Twitter
Did you know that you can follow the the latest news, information and updates to morning announcements at Guilderland High School on Twitter! Follow @GHSannouncement. Learn more
A new way to access the GHS library catalogue
Search the library's new catalog by scanning the QR Code at right using your smart phone (QR Reader App required). To access all the features this new catalog has to offer, make sure to log in – using the last five digits of your school ID as your username and the same four digit password you use to log into the school's network. Once logged in, you can search print resources, our subscription databases and reviewed websites all in one shot! Use the tabs in the upper right of your search screen to access all the information you now have at your fingertips. Have questions? Need help? See the librarians for assistance.
Superintendent presents 2015-16 budget proposal
Repurposing Task Force holds organizational meeting
Are you interested in running for a seat on the GCSD Board of Education?
GCSD to host Spring Recycling Extravaganza on April 25
GCSD Job Fair set for April 30
District ranked third in student performance in Albany area
Annual notifications for parents and community members
Important details for district parents -- Student information updates
District transitioning to paperless report cards in 2014-15
Important immunization changes for students entering grades K-6 (PDF)