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An external defibrillator includes a detector used to detect a life threatening condition of a patient, a controller operating the defibrillator automatically and a therapy delivery circuit that delivers appropriate therapy. The defibrillator is attached to a patient and is adapted to monitor the patient and when a life threatening condition is detected, to apply therapy automatically. An averaging scheme is used to determine a current cardiac rate by taking a first average of the intervals between a preset number of successive cardiac events, establishing a differential between this average and the intervals, dropping the interval corresponding to the largest differential. In this manner, the effects of over- and undersensing are eliminated or at least reduced.
1. An external defibrillator that can be used to apply therapy to a patient, comprising:
an electrode adapted to couple externally to the body of a patient;
a sense circuit coupled to said electrode to sense a physiological signal of the patient indicative of intrinsic cardiac activity;
a cardiac arrhythmia detector coupled to said sense circuit to detect an abnormal cardiac arrhythmia based on said physiological signal, said cardiac detector including a rate detector adapted to detect an intrinsic cardiac rate, said rate detector including an averaging element for averaging the intrinsic rate over several cardiac cycles to generate an average rate parameter, said averaging element includes a rate calculator adapted to determine a first average for a Predetermined number of cardiac events, said rate calculator being further adapted to determine a second average by dropping measurements related to one of said events, said second average being related to said cardiac rate, said abnormal cardiac arrhythmia being detected by using said average rate parameter;
a microprocessor-based controller adapted to generate automatically a command in the presence of said cardiac arrhythmia; and
a therapy delivery circuit adapted to deliver electrical therapy pulses to said patient to correct said abnormal cardiac arrhythmia in response to said command.
2. The defibrillator of claim 1 wherein said cardiac arrhythmia detector includes a comparator adapted to compare said physiological signal to a threshold value to identify a cardiac event used to determine said cardiac rate.
3. The defibrillator of claim 1 wherein said rate calculator is further adapted to determine a third average by dropping measurements associated with another of said events.
4. The defibrillator of claim 1 wherein said cardiac arrhythmia detector includes a descriminator that descriminates between ventricular tachycardia, fine fibrillation and a systole, and wherein said therapy delivery circuit is adapted to deliver cardiac therapy appropriate for the condition indicated by the descriminator.
5. The defibrillator of claim 1 wherein a difference is determined between each of said measurements and said first average, the largest of said differences is determined and the event corresponding to said largest difference is dropped.
6. An external defibrillator for generating cardiac therapy for a person suffering from an abnormal cardiac condition, said external defibrillator comprising:
a first electrode adapted to be attached to said patient;
a detector circuit coupled to said first electrode and adapted to detect an abnormal cardiac condition based on a physiological signal sensed through said first electrode, said detector circuit detecting a cardiac rate based on predetermined number of cardiac events and omitting some of said events based on predetermined criteria to avoid over- and under-sensing;
a microprocessor-based controller coupled to said detector circuit and adapted to generate a command in the presence of said life threatening condition; and
a pulse generator adapted to generate therapeutic pulses selected to terminate said abnormal cardiac condition in response to said command.
7. The external defibrillator of claim 6 further comprising a second electrode attached to said patient and being coupled to said pulse generator to deliver said therapeutic pulses to the patient's heart.
8. The external defibrillator of claim 7 wherein said second electrode is coupled to said pulse generator to deliver said therapeutic pulses to the patient's heart.
9. The external defibrillator of claim 6 further comprising a sensor circuit coupled to said first electrode to sense intrinsic cardiac signals, said sensor circuit being adapted to transmit said intrinsic cardiac signals to said detector circuit.
10. The external defibrillator of claim 6 further comprising a self-test and diagnostic circuit adapted to run tests on said external defibrillator to determine if said external defibrillator is operational.
11. The external defibrillator of claim 6 wherein said detector circuit is adapted to detect intrinsic cardiac signals and said controller is adapted to generate said command in synchronism with said intrinsic cardiac signals.
12. The external defibrillator of claim 11 wherein said detector circuit is adapted to detect R-waves and said controller is adapted to generate said command at a predetermined interval after said R-waves.
13. The external defibrillator of claim 12 wherein said controller is adapted to delay said command after said R-wave.
14. The defibrillator of claim 6 wherein said detector circuit includes a comparator adapted to compare said physiological signal to a threshold value to identify a cardiac event used to determine said cardiac rate.
15. The defibrillator of claim 14 wherein averaging element includes a rate calculator adapted to determine a first average for a predetermined number of cardiac events, said rate calculator being further adapted to determine a second average by dropping measurements related to one of said events, said second average being related to said cardiac rate.
16. The defibrillator of claim 15 wherein said rate calculator is further adapted to determine a third average by dropping measurements associated with another of said events.
17. The defibrillator of claim 16 wherein said cardiac arrhythmia detector includes a descriminator that descriminates between ventricular tachycardia, fine fibrillation and asystole, and wherein said therapy delivery circuit is adapted to deliver cardiac therapy appropriate for the condition indicated by the descriminator.
18. The defibrillator of claim 6 wherein said controller is adapted to operate in one of an automatic and an advisory mode selectable by an attendant, wherein in said automatic mode, the controller generates commands and said pulse generator applies shocks responsive to said commands without any signals from the attendant and wherein in said advisory mode said controller generates commands and said pulse generator applies shocks responsive to signals from the attendant.
19. The defibrillator of claim 6 wherein said controller is adapted to operate in one of an automatic and a advisory mode selectable by an attendant, wherein in said automatic mode, the controller generates commands and said pulse generator applies shocks responsive to said commands and in accordance with a set of therapy parameters previously set and without any signals from the attendant and wherein in said advisory mode said pulse generator prepares shocks in accordance with selected therapy parameters set by the attendant and shocks prompted to and delivered by the attendant.
20. The external defibrillator of claim 6 further comprising a display, wherein said controller is adapted to provide on said display at least one of an instruction for the operation of the defibrillator and information indicative of a condition of the patient.
21. The external defibrillator of claim 6 further comprising a second electrode adapted to deliver said therapeutic pulses to the patient and a connector coupled to said first and second electrodes.
22. The external defibrillator of claim 21 further comprising a housing that holds said detector circuit and said pulse generator, and a cable coupling said connector to said housing.
23. A method of providing cardiac therapy to a patient suffering from a life threatening cardiac condition using an external defibrillator having an electrode, said method comprising the steps of:
attaching said electrode to the patient to sense a physiological signal indicative of intrinsic cardiac signals;
detecting an abnormal cardiac condition based on said physiological condition by detecting a plurality of cardiac events, measuring a characteristic of said events and averaging said characteristics; and
applying automatically therapeutic pulses in response to said abnormal cardiac condition to said patient;
wherein said step of detecting includes detecting a plurality of intrinsic QRS complexes and measuring the intervals between successive QRS complexes; averaging said intervals to determine a first average related to a cardiac rate; determining the differentials between said average and the intervals between each QRS complex, and then determining a second average by dropping the QRS interval with the largest differential, said second average being indicative of said abnormal cardiac condition.
24. The method of claim 23 further comprising determining the differentials between said second average and the remaining intervals and then determining a third average by dropping the interval with the largest differential.
25. The method of claim 23 wherein said external defibrillator includes a display, further comprising providing on said display instructions for the operation of the defibrillator.
26. The method of claim 23 wherein said therapeutic pulses are applied to the patient with said electrode.
27. The method of claim 23 wherein said external defibrillator includes another electrode and wherein said therapeutic pulses are applied to the patient through said another electrode.
28. The method of claim 23 wherein an abnormal cardiac rhythm is detected and wherein the heart rate reverts to a normal sinus rhythm without the application of therapy, comprising aborting the application of any therapy.
29. The method of claim 23 wherein after said abnormal cardiac rhythm is detected and therapy is applied causing the heart rate to revert to a normal sinus rhythm wherein, the application of further therapy is aborted.
30. The method of claim 29 further comprising monitoring the heart for another abnormal cardiac rhythm after said reversion.
31. The method of claim 23 further comprising checking whether a predetermined number of cardiac intervals are smaller than an interval corresponding to a threshold rate Rmin immediately prior to the application of a therapeutic shock.
32. The method of claim of claim 23 further comprising checking an electrical characteristic associated with said electrode prior to the application of a therapeutic shock, wherein said therapeutic shock is applied only if said characteristic meets a predetermined criteria.
33. The method of claim 32 wherein said step of checking includes measuring an electrode impedance and determining if said impedance is in the range of 15-200 ohms.
34. The method of claim 23 further comprising selectively applying therapy to the patient in a manual mode comprising:
selecting an energy level by an attendant;
charging the defibrillator to the selected energy level; and
manually initiating a command and to discharge said defibrillator.
A. Field of Invention
This invention pertains to an external defibrillator arranged and constructed to provide anti-tachyarrhythmia therapy to a patient on demand. In particular, an automatic external cardioverter/defibrillator is described which has several operational modes including a fully automatic mode in which shocks are delivered without any manual intervention, an advisory mode and a manual mode. Moreover, the invention pertains to a defibrillator with an integral tachyarrhythmia detector which detects an abnormal heart beat and determines whether this abnormal heart beat is amenable to shock therapy.
B. Description of the Prior Art
Defibrillators are devices which apply electric therapy to cardiac patients having an abnormally high heart rhythm. Two kinds of defibrillators are presently available: internal defibrillators which are implanted subcutaneously in a patient together with leads extending through the veins into the cardiac chambers, and external defibrillators which are attached (usually temporarily) to the patient. External defibrillators are used in most instances in case of an emergency, for example, when a patient has either suffered cardiac arrest or where a cardiac arrest is imminent. Typically therefore external defibrillators are manual devices which must be triggered by a physician or other trained personal. Internal or implantable defibrillators (and cardioverters) are implanted as a permanent solution for patients having specific well defined cardiac deficiencies which cannot be treated successfully by other means. They generally operate in an automatic mode.
However, there are some instances where an external defibrillator would be very advantageous which could be operated in both automatic and manual modes. For example, presently, it is well known that after a cardiac episode, such as a sudden cardiac arrest, many patients frequently suffer a second episode of similar nature. Therefore, cardiac patients are kept in a hospital under observation. While in the hospital, the patient is attached to a monitor which indicates the patient's heart rate, temperature, respiration rate and other vital signs. Many monitors are provided with an alarm function which is activated when these vital signs fall outside a nominal range. The monitor then generates an audible and visual signal at the bed side of the patient and/or at the remote location such as a nurse station. However, if a cardiac episode does occur, the attending staff has to examine the patient to determine that the patient needs electrical therapy, and then set up and use a manual defibrillator. All these steps are inherently time-consuming.
Some attempt has been made to overcome some of these problems. For example, some external defibrillators are available which can verify that a patient is suffering from ventricular fibrillation VF and prompt an attendant to activate the defibrillator for the delivery of therapy. However, the algorithms used by these defibrillators to detect VF are very limited. For example, some of defibrillators utilize an algorithm in which the electrocardiogram ECG can be verified only while the patient is unconscious, has no pulse and does not breath. Obviously, these algorithms are not satisfactory since it is important to detect when those conditions happen and apply therapy as soon as those conditions are detected.
Commonly-owned U.S. Pat. No. 5,474,574 discloses an external defibrillator. Commonly-owned U.S. Pat. No. 4,576,170 discloses an external defibrillator that can be worn by a patient.
An objective of the present invention is to provide an automatic external cardioverter/defibrillator which is capable of detecting a current cardiac rate of a patient accurately by eliminating the effects of over- and under-sensing.
A further objective is to provide a defibrillator capable of performing amplitude and/or frequency analyses to detect a shockable rhythm based on a patient's ECG and to use the results of these analyses to categorize or recognize the current condition of the patient and to apply appropriate therapy for reverting the same.
Yet another objective is to provide an external defibrillator with several modes of operation, including an automatic mode in which shocks are applied on demand in accordance with preprogrammed shock parameters and without any prompting from an attendant, an advisory mode in which an attendant is alerted to a shockable rhythm however the application of shocks must be initiated by the attendant and a manual mode in which the attendant determines how and when shocks should be applied and the preprogrammed shock parameters are ignored.
Other objectives and advantages of the invention will become apparent from the following description of the invention.
FIG. 1 shows a front view of an automatic external cardioverter/defibrillator constructed in accordance with the subject invention;
FIGS. 2 and 3 show an orthogonal view of the defibrillator of FIG. 1 with details of the printer on the side of the housing;
FIG. 4 shows the defibrillation and sensing electrodes used with the defibrillator of FIG. 1;
FIG. 5 shows a block diagram of the circuitry for the defibrillator of FIG. 1;
FIG. 6 shows a flow chart illustrating the steps required to initialize the defibrillator of FIG. 1;
FIG. 7 shows diagrammatically the placement of the electrodes of FIG. 4 on a patient;
FIG. 8 shows a view of the display while an ECG is acquired during the initialization process of step 6;
FIG. 9 shows a flow chart for the operation of the defibrillator of FIG. 1;
FIG. 9A shows details of a rate detecting circuit for the defibrillator of FIGS. 1-5;
FIG. 9B shows a flow chart for the operation of the circuit of FIG. 5A;
FIG. 10 shows the screen displayed during automatic operation when the defibrillator is ready to apply anti-tachycardia therapy;
FIG. 11 shows a flow chart illustrating the operation of the device in the advisory mode;
FIG. 12 shows a block diagram for the tachycardia detector circuit of FIG. 5;
FIG. 13 shows a flow chart illustrating the operation of the circuit of FIG. 12;
FIG. 14 shows a flowchart illustrating the operation of the therapy selector of FIG. 5.
FIG. 1 shows a defibrillator 10 having a housing 12 with a front face display 14 on which a plurality of controls and indicating elements are provided, as described in more detail below. The defibrillator no further includes electrode assembly shown in FIG. 4 and described in detail below. As seen in FIGS. 2 and 3, one side 16 of the housing 12 is provided with a cavity 18. A printer (not shown) is mounted in cavity 18. A roll of paper 20 is mounted on shaft 22 in a manner which allows the printer to print alphanumeric characters and graphics on paper 20.
The housing 12 can be positioned on a rack, or other support means so that it can be disposed adjacent to the patient.
Referring back to FIG. 1, a screen display 24 is mounted on the front face 14 so that it is clearly visible. The display is used to provide information to the clinician related to the operation of the defibrillator 10, the status of the patient, etc. Disposed around the display 24, there are other indicator and control elements, such as the menu selection control knob 26, selector knob 28, charge button 92, shock buttons 30, 31 with built-in lights 30A, 31A respectively, and indicator lights 32, 34 and 36.
The menu selection control knob 26 is used in combination with the display 24 to select various operational parameters or operations for the defibrillator 10.
The knob 28 has several positions defining modes of operation, such as: Off, Auto/advisory, Disarm and Energy Selections. In the Off position, the defibrillator is deactivated. In the auto/advisory position, the defibrillator monitors the patient and can apply shocks using a preselected therapy. In the disarm position, an internal capacitor (not shown) is discharged to ensure that the defibrillator does not apply a shock accidentally. Finally, in the energy selection position, the defibrillator may be used to apply a shock to a patient at the selected energy level.
A socket 38 is provided for mating the housing 12 to the electrode assembly of FIG. 4. Near the top of the face 14, the housing 12 is provided with an additional illuminated indicator 33.
FIG. 4 shows details of the electrode assembly 40. The assembly 40 includes a first plug 42 constructed and arranged to mate with the jack 38 (FIG. 1), a connector 44 and a cable 46 extending between the plug 42 and the connector 44.
The assembly 40 further includes a pair of defibrillator pads 48 and 50 coupled to the connector 44 by an adapter 52, and two leads 54, 56 connected respectively to sensor electrode pairs 60 and 62. To ensure the defibrillation pads 48 and 50 are approved pads and they are used within their specified or approved time limit, e.g. 24 hours, a pad identification (pad ID) may be embedded in either the pads 48 and 58, cables 54, 56, and 46, or connectors 42 and 44. The defibrillator includes a capability to verify the pad ID and time it out after specified or approved time limit of usage.
The defibrillator 10 also includes electronic circuitry disposed in housing 12 and used to operate the defibrillator and to generate the required electrical therapy. Referring to FIG. 5, the circuitry includes a microprocessor 70 which is associated with a memory 72 for storing programs and data logging information. The defibrillator further includes a sensing circuit 74, an ECG detecting circuit 76, a rate detector circuit 78, an MDF circuit 80, a therapy selector circuit 82, a defibrillator shock generator 84, an external interface 86, and a user interface 88. The microprocessor 70 receives commands from an attendant and other control signals through the various knobs, and push buttons shown in FIG. 1 via the analog interface 88. The microprocessor also activates various visual indicators and a speaker 92 through the same interface 88. The circuits shown in FIG. 5 can be implemented by software in RAM 72 however are shown as discrete circuits for the sake of clarity. Energy for the shocks is derived from a capacitor 84A associated with the generator 84.
As can be seen in FIG. 5, the electrode pairs 60, 62 and pads 48, 50 are connected through the jack 38 to a sensing circuit 74. This circuit 74 senses the intrinsic signals detected from the heart of the patient through the electrodes or pads, filters the same, converts them into digital signals at a sampling rate of, for example, 512 samples per second. Of course the filtering can be performed on the digital signals as well. The circuit 72 further includes an impedance measuring element (not shown) which measures the impedance of between the pads 48, 50. This impedance is provided to the microprocessor 70 so that the latter can determine if the pads and sensors are properly attached to the patient. The sensing circuit also detects if the sensing electrodes are connected properly.
The sampled digital signals from circuit 74 are fed to the microprocessor 70. The ECG detector circuit 76 and the rate detector circuit 78. The ECG detector 76 detects the ECG complex of the patient. The rate detector circuit 78 detects the current cardiac rate of the patient.
The microprocessor 70 analyzes the signals received from circuits 74, 76 and 78 and operates the other elements of defibrillator in accordance with these signals as discussed in more details below. In addition, the microprocessor 70 also sends information requested by an attendant to printer 80 when a pushbutton 90 (FIG. 1) is activated. In some cases, the microprocessor 70 activates the printer 80 automatically, for example, to display an ECG during defibrillation therapy.
The microprocessor can also exchange information with other devices or display a current ECG through an external interface 86.
Before turning on the defibrillator 10, the pads 48, 50 and electrodes 60, 62 are positioned on the patient. FIG. 7 shows one possible positioning for these elements.
The operation of the defibrillator 10 and its microprocessor 70 is now described in conjunction with the flow charts of FIGS. 6 and 9. Before the defibrillator 10 can be operated, it must be initialized. This stage of initialization may be performed whenever the defibrillator 10 is set up for a particular patient. In one embodiment of the invention, the defibrillator 10 can be set up for only one patient at a time. In another embodiment, the defibrillator may be set up to provide therapy selectively to one of several patients, in which case, operational parameters unique for each patient are stored in its memory 88.
The first step in the initialization stage, step 100, the defibrillator 10 is turned on. This may be performed, for example, by turning the selector knob 28 to the auto/advisory position.
Once the defibrillator 10 is activated, it goes into a self-test mode (step 102) during which various internal functions and components are tested. During this step 102, the indicator light 32 illuminates to indicate that the defibrillator is currently unable to apply shocks and various sounds are emitted from the speaker (not shown) as well.
If the self-test fails in step 102, then in step 104, an error message is shown on display 24 and the initiation process is aborted.
If the self-test passes, then in the next step 106, the ID of the patient to be treated is obtained. For example, instructions may be shown on display 24 requesting the name and/or a unique number for the patient. The requested information can be entered by manipulating the knob 26 or by using a keyboard (not shown). The patient ID may be an optional field.
Next, in step 108, the ECG signals are analyzed to determine the best channel for the ECG acquisition. More particularly, the two pairs of sensing electrodes and the pads (which are also used in this instances as a sensing electrode pair) define three separate detection channels. The detection channel is selectable by an attendant.
Referring to FIG. 8, a portion 96 of display 24 identifies three detecting channels as channels 1, 2 and 3 respectively. In step 108, each of these channels is selected by manipulating knob 26. As each channel is selected, the ECG sensed through the corresponding pair of electrodes, the electrode pair impedance of the defibrillation pads, and current heart beat sensed through the electrodes is shown on the display 24. For example, in FIG. 8, an ECG is shown as it is sensed from channel 2 (which may correspond to electrode pair 60), with an electrode impedance of 50 ohms and a heart rate of 72 beats. These measurements are derived by the microprocessor 70 from the signals sensed through the sensing electrode pairs, the sensing circuit, and the ECG detection circuit 76. The attendant setting up the defibrillator examines the ECG and other parameters for each channel and based on attendant's observations and experience, the attendant then selects the best or optimal channel by manipulating knob 26.
Next, in step 110, the parameters for a particular therapy are selected by the attendant, including a cardiac rate Rmin. The range of Rmin is about 120-240 BPM. Another parameter set during step 110 is the rate Rmdf. Generally, the rate Rmdf is higher than Rmin.
The defibrillation therapy delivered by defibrillator 10 consists of one or more shocks. More particularly, the defibrillator 10 can be set to deliver a number of sequential shocks, for example, one to nine; each having an energy level in the range of 5 to 360 joules. The interval or delay between shocks can also be set from 10 to 600 seconds in either 5 or 10 second increments. These parameters are all selected in step 110. Moreover, if multiple shocks are used, the energy level and or delay of each shock may be constant or can be separately programmed to predetermined levels.
After the operational parameters of the defibrillator 10 have been set (or programmed) in step 110, the defibrillator proceeds to learn to recognize the ECG of the patient in step 112. During this step, the microprocessor 70 monitors the signals sensed on the channel designated in step 108 for a predetermined time period (for example, 20 seconds). In step 114, a test is performed to determine if the ECG signal recognition was successful. For example, during this period the heart rate is determined from the ECG by determining the time interval between successive R-waves, and compared to the Rmin. In addition the amplitude of the ECG signal is compared to a threshold value (such as 0.7 mv). If the heart rate is found to be below the rate Rmin and the amplitude is found to exceed the threshold then the recognition step is successful. If the recognition process is not successful, then in step 116, a message is displayed to indicate failure and the process is aborted. In step 116 suggestions may also be made to the attendant which may cure the problem. For example, the attendant may be asked to reposition the electrode pairs, and/or select a different sensing channel.
If the learning process is found to be successful, then in step 118, the ECG is shown on the display 24 together with the pertinent parameters and the attendant is requested to verify these parameters. In step 120, the attendant is given the choice of accepting the ECG or to reject it. If the attendant rejects the ECG, the process is aborted. If the attendant accepts the ECG, then in step 122, the attendant is asked to select a mode of operation (i.e., automatic or advisory). In step 124, the choices made during the initialization process are displayed to the attendant. The attendant can request that the selected parameters and mode of operation be printed out during this step.
In step 126, the attendant is given the choice of accepting the parameters as they were set in steps 106-122. If the parameters are accepted, then in step 128, the initialization process is completed, the defibrillator automatically print the parameters, and the operation starts its normal operation mode.
If in step 126, the attendant does not approve the parameters but instead selects to edit them then the process goes back to step 106.
If the attendant decides to cancel the selected parameters (step 130), the process is aborted.
Once the defibrillator 10 has been properly initialized, it is ready for operation. As described above, the mode of operation of the defibrillator 10 is determined by position of the selector switch 28. If this switch is in the auto/advisory position, and it has been previously set to the automatic mode, then it operates as described in the flow chart of FIG. 9. Starting with step 150, the defibrillator first monitors the condition of the patient's heart. During this time, the display 24 is used to show the following information: the mode of operation (in this case AUTOMATIC), the current ECG, the current heart rate Rcur and the selected Rmin.
The current heart Rcur is determined using the circuit 78 as shown in FIGS. 9A and 9B. The circuit 78 includes a comparator 78A, a threshold selector circuit 78B and a rate calculator circuit 78C. The comparator 78A and the threshold selector circuit 78B cooperate to detect the intrinsic ventricular rate in an adaptive manner. That is, prior to the acquisition of any signals, the circuit 78B selects a low threshold level Tr which may in the order of 0.2 millivotes. Once a sensed signal exceeding this level is detected by comparator 78A, the signal is identified as a potential R-wave. Thereafter. for a predetermined time period for all future incoming signals, the threshold level is increased slightly until a maximum threshold level Tm is reached. In this manner, a multiple digital signal processing method is used to detect the intrinsic cardiac signals using an adaptive threshold.
Next, the signals detected by comparator 78A are fed to a rate calculator circuit 78C. This circuit also receives a signal indicative of whether the the electrodes currently being used to detect the ECG complex are connected properly. This circuit 78C measures the interval between consecutive signals and generates the corresponding a ventricular rate, using a special averaging technique. This technique from comparable 78A has been selected to eliminate the adverse effects of over-sensing and under-sensing the cardiac signals. More particularly, referring to FIG. 9B in step 400, the impedance signal is detected and analyzed. In step 402, a test is performed to determine if this signal is abnormally high, indicating that a lead (or electrode) is off. If a lead is off, then in step 404, an alarm is generated and the rate calculation process is terminated. As part of step 404, a message is shown on display 24 with instructions to the attendant for correcting the problem.
If, in step 402, it is determined that the electrode impedance is acceptable, then in step 406, N intervals between sequential events from comparator 78A are measured. In step 408, a first average AI1 is taken of the N intervals. In step 410, the absolute difference is determined between the average AI1 and each of the intervals. The interval with the largest difference is discarded.
Next, in step 412, a new average AI2 is generated using the remaining N−1 intervals. In step 414, again, the absolute difference between each of the remaining intervals and the average AI2 is determined and the interval corresponding to the largest difference is discarded. In step 416, an average is taken of the remaining N−2 intervals and this average, or more properly, its inverse, is designated as the current cardiac rate Rcur for the patient's heart. This process (steps 400-416) is repeated for each new electric event from the comparator 78A.
Back to FIG. 9, in step 152 at regular intervals, a check is performed to determine if the current rate Rcur (as determined in FIG. 9B) is indicative of a shockable cardiac rhythm is detected. The method of detecting such a shockable rhythm and of determining the corresponding therapy is discussed below, in conjunction with FIG. 14. If a shockable rhythm is detected then in step 154, the arrhythmia is categorized (i.e., as a tachycardia or fibrillation). In step 156, the display 24 is used to show, as indicated in FIG. 10 the current ECG of the patient, at 91, patient's heart rate at 93, and the therapy parameters selected, including the selected energy level, 95A, the number of shocks delivered 95B the total number of shocks programmed 95C and the total number of shocks that remain to be delivered, 95D. Next, in step 158, the defibrillator issues visual and audible warnings to the attendant indicating that the defibrillator is preparing to deliver shocks to the patient and the patient should not be touched. The visual warnings include turning light 33 on (FIG. 1) and the audible signals including voice signals are generated through the speaker (Not shown).
Next, in step 160, the defibrillation pulse generator 84 is activated to start charging its capacitor 84A. As shown in FIG. 10, the display 24 shows during this time the selected or targeted energy level which was set during the initialization mode. The display also shows at 95A the current charge level within the defibrillation pulse generator. As the capacitor within the generator is charged up, this level is increasing, and a beeping signal is emitted to indicate this gradual charging process.
In step 162, the charge level of the capacitor is tested to determine if the set energy level has been reached. If this level has not been reached, the charging process continues.
When the selected charging level is complete, the defibrillator 10 prepares to apply shocks. In step 164, the indicator 34 is lit to indicate that the defibrillator 10 is ready to apply therapy.
At any time during the process described so far, an attendant can disable the automatic or advisory mode by moving the knob 28 to the disarm or energy selection position. In FIG. 9, in step 166, a check is performed to determine if the knob 28 has been shifted to these positions.
If the defibrillator has not been disarmed, then for all shocks, except the first shock of a treatment in step 168, a delay is imposed to conform to the delay programmed between shocks as discussed above. Once the delay is complete in step 170, an attempt is made to synchronize the shock to the ECG. More particularly in step 172, the ECG is analyzed and an attempt is made to detect an R-wave. If an R-wave is detected, then in step 174, a pulse of predetermined duration and energy level is applied to the patient within a predetermined interval, for example 60 milliseconds, after the R-wave.
As step 172 is initiated, a timer (not shown) is also activated. This timer waits for a predetermined time (for example, 2.5 seconds) for synchronization to be achieved. If no synchronization is achieved in that time period, then in step 178, a shock is applied asynchronously.
The defibrillation shock of step 174, 178 is delivered to the patient by the pads 48, 50 (FIG. 4).
After the deliver of the shock in step 180, the heart rate of the patient is determined. If a non-shockable rhythm is detected (step 182), then no more shocks are applied and the heart monitoring is continued in step 150.
If the shockable rhythm continues, then the process of steps 152-180 is repeated thereby delivering the next level of predetermined therapy.
This process continues until all the predetermined number of shocks are delivered, the system returns to step 150 and continues monitoring the patient.
Preferably, after the predetermined number of shocks is delivered, the heart is monitored in step 150 but no other steps are taken even if a shockable rhythm is detected in step 152 unless the therapy sequence resets after a predetermined period of non-shockable has been detected or the defibrillator has been reset.
If the process described above is halted at any time, for example, by turning knob 28 to the disarm or manual position as set forth above in step 166, then the capacitor 84A associated with the defibrillation pulse generator 84 is discharged internally.
In the above description, it was assumed that a ventricular tachyarrhythmia has been detected in step 154. The process may be modified to suit other types of arrhythmias as well. For example, if a fine fibrillation is detected, the steps 170, 172 are omitted since no synchronization may be achieved.
In the automatic mode, when the peak to peak amplitude of ECG signal is greater than a threshold, e.g. 0.2 milli-volts, to ensure a shock is delivered to a shockable condition, the last intervals immediately before the shock is delivered need to be less than the shockable interval corresponding to the Rmin. In this particular application, two intervals immediately prior to the shock are required to be less than the shockable interval.
As previously mentioned, one of the operational modes of the defibrillator 10 is an advisory mode. This mode is now described in conjunction with FIG. 11. In this mode the defibrillator performs the same functions that are performed in the automatic mode starting from step 150 through step 166 (FIG. 9). However, after step 166, instead proceeding with the delivery of shock therapy, the lights 30A, 31A associated with pushbuttons 30 and 31 respectively are activated and indicating to an attendant that the defibrillator is ready to apply a shock. The attendant can then elect to apply a shock by depressing pushbuttons 30, 31 simultaneously. A check is performed in step 202 to determine if the pushbuttons have been depressed. If they have not been depressed, then in step 204, a check is performed to determine if the shockable rhythm is still present. If the rhythm is still present, then the lights 30A and 31A remain activated in step 200 and the system continues to wait for the activation of buttons 30, 31. If, in step 204, it is found that a shockable rhythm is no longer present, then the system is reset in step 206.
If the buttons 30, 31 are found activated in step 202, then in step 208, an attempt is made to synchronize with the R wave. In step 210, a check is performed to determine if synchronization was achieved. If synchronization is achieved then a shock is applied in step 212. In step 224, a check is performed to determine if all the prescribed shock pulses have been applied. If shocks still remain, the system returns to step 200. Otherwise, it resets itself.
If no synchronization is achieved in step 210, then in step 214, a check is performed to determine if the pushbuttons 30, 31 are still pressed. If they are not pressed, the system resets in step 216. If the pushbuttons 33, 35 are pressed, then in step 220, a check is performed to determine if a 2.5 second timer has elapsed. If it has not elapsed then the system returns to step 208 and tries to achieve synchronization again. If the timer has elapsed, as indicated in step 220, then in step 222, a shock is applied and the system continues with step 224.
The defibrillator 10 can also be used as a standard manual defibrillator by setting the knob 28 to an energy selection position. In this position, the knob 28 can be used to select the level of energy for the defibrillation shock. In the manual mode, when the pushbutton 92 is activated, the pulse generator 84 charges its capacitor 84A to the level designated by the knob 28. When the desired level is reached, the lights 30A, 31A are illuminated and the shock can be applied by depressing the pushbuttons 30, 31.
An important part of the subject invention is the detection of a shockable rhythm (step 152 in FIG. 9). Primarily, this determination is made from the patient's cardiac rate. When selected, the MDF function is performed by the MDF circuit 80 by analyzing the ECG signal. However, simply setting a rate threshold to detect tachyarrhythmias is insufficient in some cases because an abnormally high rate (above the threshold) may not be ventricular tachycardia origin but from other causes such as sinus tachycardia, SVT (supra-ventricular tachycardia), or atrial fibrillation. Shock therapy is generally not indicated for these latter arrhythymias and may even be harmful to the patient. In the present invention, the ECG is analyzed and both its magnitude and frequency characteristics are taken into account to distinguish, if possible, VT from other SVT arrhythmias including atrial fibrillation/flutter as well as sinus tachycardia.
More specifically, the present inventors have analyzed and compared the morphologies of VT and SVT rhythms in order to discriminate them. It should be noted that ventricular tachyarrhythmias are characterized by relatively low frequency components, as compared to SVT arrhythmias. Frequency alone may not be adequate for the purposes of this invention. Amplitude must also be taken into account because it fluctuates widely during an arrhythmia episode. However, an amplitude consideration alone (for example, measuring the duration during which the subject wave-shape is above a baseline) has been found to be unsatisfactory because of the inability to detect VT accurately.
Therefore, in the present invention, a procedure has been found which takes both frequency and amplitude into consideration and hence it is referred to as MDF or modulation domain function. The method and apparatus for detecting a shockable event herein has been designed to reduce the probability of delivering therapy for an SVT condition even if its characterized by a rate which is higher than the threshold value Rmin.
Referring now to FIG. 12, the MDFr circuit 80 includes a clipping circuit 300, a first summing circuit 302, a comparator 304, a differential normalizing element 306, a second summer 308, and a comparator 310.
The operation of the circuit shown in FIG. 12 will now be described in conjunction with the flow chart of FIG. 13. The circuit 78 receives from circuit 76 a stream of digital signals Ai representative of the current ECG. As each digital signal is received (step 342), it is first clipped by clipping circuit 300 so that it does not exceed a predetermined maximum value (step 302). This step insures that abnormally large values do not unbalance the evaluation performed by the circuit 80. After clipping, the signals Ai are fed to the summer 302. The summer 302 generates a running sum S0 (step 344) of all the digital signals received over the period T. Typically, T may be about 64 milliseconds.
Next, in step 306 the running sum S0 is compared to a threshold value L0 by comparator 304. If S0 is below threshold value L0 then so is set to zero (step 348) to insure that any baseline noise existing in the ECG signal does not contribute to the summation.
Next, a normalized differential parameter X is determined by element 308 as follows. First a differential parameter D is determined using the relation:
where S0 is the current sum from summer 302 and SP is the immediate previous sum, i.e., before the current digital signal Ai has been processed by the summer 302. The parameter D is then normalized in step 352 by dividing it by the digital signal Ai to obtain the parameter X (i.e., X=D/Ai). The purpose of this step is to reduce the effect of any sudden amplitude changes in the signals Ai.
The parameter X is then fed to filter 308 which is a non-linear filter that uses four preselected parameters to perform a specific filtering function (step 354) to generate a filtered parameter Y. This parameter Y is related to X as follows:
where B0<B1<B2<B3. Typical values for these constants may be 10, 50, 160, and 220 respectively.
The parameter Y is fed to the summer 310. The summer 310 in step 356 generates a running sum of all the values of Y received for the last N seconds. For instance, N may be 4 seconds. The resulting parameter Mf is fed to a comparator 312. This comparator 312 which generates a parameter MDFi as follows. In step 356 the parameter Mf is compared to the threshold Ts. If Mf is greater than Ts then the comparator 312 generates an MDFi which is true. Otherwise MDFi is false.
One of the programmable options of the defibrillator 10 is the selective enablement of the MDF circuit 80. That is, during the initialization of the defibrillator 10, the attendant has the choice of activating the circuit 80, in which care the parameter MDFi is determined as described above, or the function can be disabled, in which care the MDFi is ignored.
Referring back to FIG. 5, the parameter MDFi is fed to the therapy selector 82. This selector 82 monitors the current cardiac rate Rcur and parameter MDFi (if applicable) and determines whether therapy is required, and if so, then what kind of therapy should be applied.
Referring to FIG. 14, in step 350, a check is performed from step 150 to determine if the peak to peak amplitude of the signal is less than 0.2 milli-volts for the previous seconds. If it does, the algorithm checks to see if a shockable rhythm has been detected prior to this latter period 368. If a shockable rhythm has been detected, the algorithm classifies the rhythm as Fine VF 370 which is shockable 372. If a shockable rhythm has not been detected, the algorithm classifies the rhythm as a systole 376 which is not considered a shockable rhythm 362.
Referring to FIG. 14, in step 352, the current rate Rcur from step 350 is first checked to see if it exceeds the minimum rate Rmin. If it does not, then the rhythm is classified as non-shockable 362 and monitoring of the heart continues in step 150 without any therapy. In step 354, a check is performed to determine if the MDF mode has been activated. If it is not, it continues to step 366. If this mode has been activated in step 354, a check is performed to determine if Rcur is greater than Rmdf 356. If it is, it continues to step 366. In step 358, a check is performed to determine if the parameter MDFi is true. If it is true, it continues to step 366. If MDFi is not true, the rhythm is classified as non-shockable 362 and no therapy is performed at this time. In step 366, a P of R test is performed during which P of the last R intervals must have corresponded to a rate higher than Rmin. For example, P could be 4 and R could be 6. If the test failed, the rhythm is classified as non-shockable 362, and it returns to step 150.
If the P of R test is passed, then the current rate Rcur is designated as a shockable rhythm corresponding to ventricular tachyarrhytbmias and the process continues to step 156 in FIG. 9.
In summary, the microprocessor 70, rate detector 78, and MDF circuit 80 and the therapy selector 82 cooperate to determine if the current cardiac condition of the patient should be classified as a shockable rhythm or not based on the current rate Rcur as well as the amplitude and frequency of the ECG signals. If the rate Rcur is below the threshold Rmin, no therapy is applied. If the rate is above Rmin, a determination is made as to whether the rhythm is shockable or not, based the parameters and modes described. Since VT and ventricular fibrillation could be life-threatening, it is preferably that a conservative approach be taken when selecting these parameters.
The process and apparatus described above and in FIGS. 12 and 13 is primarily designed for use in the automatic external cardioverter/defibrillator, however it may also be used in internal defibrillator/cardioverter devices and other cardiac devices as well.
Obviously, numerous modifications may be made to this invention without departing from its scope as defined in the appended claims.
Patent Citations
Referenced by
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South Thanet MP Laura Sandys is calling for the development of a seafront masterplan.
She spoke after the council announced it is terminating its agreement to turn the Pleasurama funfair site into a mixed-use development.
Developer SFP Ventures UK had secured planning permission in 2004 for a hotel, apartments and retail units, but the scheme failed to materialise.
In a short statement, Thanet District Council said: "Members of Cabinet have tonight decided to adopt the recommendations of the Overview and Scrutiny Panel to terminate the development agreement in relation to the Pleasurama site in Ramsgate.
"A construction expert will now be appointed to advise the council on the steps to be taken next."
Ms Sandys said: "Now is the time to develop a masterplan for the whole of Ramsgate's historic seafront and I am keen that we organise a competition for leading architects from around the country to help us restore the iconic character of our much-loved seascape.
"With the Royal Victoria Pavilion's future likely to be coming up for review very shortly, there has never been a better time to develop a masterplan for the whole seafront.
"The Pleasurama site is a most extraordinary one but it has laid derelict for far too long.
"It has become a blight on our town and we absolutely cannot allow another decade to pass with negligible progress. We are quite simply squandering one of our most superb assets.
"Ramsgate truly is a national treasure and we all want to see the fabulous seafront restored. That's why it is imperative that the next move is the right one.
"A rash decision on the future of the site could be catastrophic. We have huge potential and it's time that leading architects were brought in to help us formulate a masterplan for Ramsgate seafront."
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text: health care fraud Former Wayne State medical professor sues, accuses university of defrauding US government By Sarah Cwiek • Apr 18, 2014 Wayne State University medical school / via flickr A former Wayne State University medical professor is suing the school over alleged "system-wide" fraud. In a federal lawsuit, former assistant professor Christian Kreipke alleges the university scammed the US government out of $169 million through fraudulent research proposals. Kreipke filed the lawsuit in 2012, but court documents were only unsealed recently. They lay out Kreipke's claims that Wayne State and its physician group made fraudulent claims to get more government grant money. Federal prosecutors increase focus on health care fraud By Steve Carmody • Jul 12, 2013 Steve Carmody/Michigan Radio Federal prosecutors reached a multimillion-dollar, out-of-court settlement this week with a Jackson cardiologist in a health care fraud case. It's the latest in a string of Medicare and Medicaid fraud cases in Michigan. Federal prosecutors in the Eastern District of Michigan have filed nearly 300 charges of health care fraud during the past five years. Half the time, defendants have pled guilty or were convicted. And the pace of prosecutions has picked up during the past few years.


text:
Sir Philip Sassoon, 3rd Baronet
|The Right Honourable
Sir Philip Sassoon
Bt CMG GBE
|Sir Philip Sassoon as a staff officer during World War I
|First Commissioner of Works
|In office
27 May 1937 – 7 June 1939
|Preceded by
|The Earl Stanhope
|Succeeded by
|Herwald Ramsbotham
|Personal details
|4 December 1888
|3 June 1939 (Aged 50)
|Alma mater
|Christ Church, Oxford
Sir Philip Albert Gustave David Sassoon, 3rd Baronet, PC, GBE, CMG (4 December 1888 – 3 June 1939), was a British politician, art collector and social host, entertaining many celebrity guests at his homes, Port Lympne Mansion, Kent, and Trent Park, Hertfordshire, England.
He was educated at Eton and Christ Church, Oxford, and entered Parliament in 1912.[1]
Sassoon was a member of the prominent Jewish Sassoon family and Rothschild family. His father was Sir Edward Albert Sassoon, 2nd Baronet, MP, son of Albert Abdullah David Sassoon; his mother was Aline Caroline, daughter of Gustave Samuel de Rothschild. His sister was Sybil Sassoon, who married the Marquess of Cholmondeley. He was a cousin of the war poet Siegfried Sassoon.
First World War[edit]
A second lieutenant in the East Kent Yeomanry, Sassoon served as private secretary to Field Marshal Haig during the First World War from 1915-1918.[1]
Sassoon was present at the meeting on the First of December 1914 at the Chateau Demont at Merville in France, when King George V and Edward Prince of Wales met with Poincare, President of France, and the Generals Joffre, Foch and Rawlinson. The allies showed their determination to fight Germany and its allies. Because of his "numerous social and political connections" Sassoon, at that time a Second Lieutenant in the Royal East Kent Yeomanry, was in attendance. A square bronze plaque commemorating the occasion was auctioned in 2012.
Political career[edit]
He was Member of Parliament (MP) for Hythe from 1912, succeeding his father, initially as the "Baby of the House". He was Parliamentary Private Secretary to David Lloyd George in 1920. Between 1924 and 1929 and again from 1931 until 1937 he served as Under-Secretary of State for Air, and gained much prominence in political circles. He was appointed a Privy Councillor in the 1929 Dissolution Honours. In 1937 he became First Commissioner of Works, a post which he held until his death, aged fifty, two years later.
Trent Park[edit]
He had a reputation for being one of the greatest hosts in Britain. Herbert Baker designed one house for him in 1912, Port Lympne, later the Port Lympne Wild Animal Park, in Kent, and Philip Tilden largely re-built another at Trent Park, Cockfosters, from 1923. Stylistic differences between the two houses illustrate changes in taste among members of British high society of the period. Trent Park possessed a landscape designed by Humphrey Repton but the existing house was Victorian and undistinguished. Sassoon and his designers turned it into one of the houses of the age, "a dream of another world - the white-coated footmen serving endless courses of rich but delicious food, the Duke of York coming in from golf... Winston Churchill arguing over the teacups with George Bernard Shaw, Lord Balfour dozing in an armchair, Rex Whistler absorbed in his painting... while Philip himself flitted from group to group, an alert, watchful, influential but unobtrusive stage director - all set against a background of mingled luxury, simplicity and informality, brilliantly contrived..."[2] This atmosphere, as Clive Aslet has suggested, represented a complete about-face from Sassoon's earlier extravagance at Port Lympne to what Aslet called "an appreciation of English reserve."[3] In the words of Christopher Hussey, at Trent Sassoon caught "that indefinable and elusive quality, the spirit of a country house... an essence of cool, flowery, chintzy, elegant, unobtrusive rooms that rises in the mind when we are thinking of country houses."[4]
Port Lympne Mansion[edit]
Neither the eye-popping interiors nor the extravagant gardens at Port Lympne Mansion could be described as in any way "reserved", or even "English". Mark Girouard has written of the "quiet good taste expected of a country gentleman"[5] against which Philip may have chafed in his younger years, apparently torn between the standards of Country Life and Metro-Goldwyn-Mayer. His Ballets Russes-inspired dining room at Port Lympne with its lapis walls, opalescent ceiling, gilt-winged chairs with jade-green cushions, all surmounted by a frieze of scantily-clad Africans, suggests the outsider confidence of a Rothschild and of an openly gay man.[3] Philip Tilden added a bachelor's wing with Moorish courtyard, which Lady Honor Channon, (wife of Chips), unkindly likened to a Spanish brothel,[3] to accommodate young airmen from nearby Romney Marsh flying field - among his other enthusiasms, Sir Philip was himself an aviator - and Tilden's twin swimming pools and monumentally classical garden staircase were in much the same theatrical spirit.
One frequent guest was Lawrence of Arabia.
As Secretary of State for Air, Sassoon was Honorary C.O. of 601 (County of London) Squadron. The Squadron was nicknamed 'The Millionaires' Squadron' because it was reported to have six millionaire members. In 1932 he was enthusiastic about the new Percival Gull monoplane and ordered his own model powered by a Napier Javelin 111 six cylinder engine, with the interior finished in red leather. In this luxurious Gull G-ACGR he competed in the King's Cup and the Folkestone Aero Trophy Race. As Under-secretary of State for Air, Sassoon carried out the first general inspection of British overseas air stations, flying the Blackburn Iris. Afterwards he wrote The Third Route, published by Heinemann in 1929, recounting the story of the development of the air route from England to India.
Honours and decorations[edit]
He was appointed a Companion of St Michael and St George (C.M.G.) in 1917.[1] On 7 October 1919, it was announced that Sassoon had been awarded the French Croix de Guerre "for distinguished services rendered during the course of the campaign.[6] In 1923 he was made Knight of the Grand Cross Order of the British Empire (G.B.E.).[7]
In 2012 a set of his decorations was sold at auction.[8] The decorations were a set of the Order of The British Empire, Grand Cross (G.B.E.) made by the court-jeweller Garrard, the Order of St Michael and St George, Companion's (C.M.G.) neck Badge, also by Garrard, 1914-15 Star (engraved Lieut. Sir P.A.D.G.Sassoon. R.E.Kent Yeo.); British War and Victory Medals ( engraved Major Sir P.A.D.G.Sassoon. R.E.Kent Yeo.); 1935 Jubilee Medal and 1937 Coronation Medal (both engraved A/Cdre Sir Philip Sassoon 601 Squ. A.A.F.); France, a decoration of a Knight of the Legion d'Honneur, a decoration of a Knight of the French Colonial Order of the Black Star; Belgium, Officer of the Order of the Crown; French Croix de Guerre and Belgian Croix de Guerre; mounted in the court style.
The arts[edit]
He was Chairman of the Trustees of the National Gallery from 1933 - 1935, and as Minister for Works in the 1930s he was responsible for embellishing many of London's monuments and parks. As a collector Philip Sassoon was, like many of the Rothschilds, drawn mainly to the English and French 18th century, but he also collected contemporary artists such as John Singer Sargent and William Orpen.[9]
Personal Life[edit]
Sassoon never married and was said to have live an openly homosexual life.[10]
Sassoon died on 3 June 1939, aged 50, of complications from influenza.[11][12][13]
- Peter Stansky. Sassoon: The Worlds of Philip and Sybil (2003) Yale University Press ISBN 0-300-09547-3
- Leigh Rayment's list of baronets [self-published source][better source needed]
- Leigh Rayment's Historical List of MPs [self-published source][better source needed]
- ^ a b c Who Was Who 1929-1940. London: A. & C. Black. 1941. p. 1197.
- ^ Boothby, Robert (1947). I Fight to Live. London: Gollancz.
- ^ a b c Aslet, Clive (1982). The Last Country Houses. New Haven and London: Yale University Press. ISBN 0300034741.
- ^ Hussey, Christopher (17 January 1931). Country Life: 66–7. Missing or empty
- ^ Girouard, Mark (1978). Life in the English Country House. New Haven and London: Yale University Press. ISBN 0300022735.
- ^ The London Gazette: (Supplement) no. 31586. pp. 12401–12405. 3 October 1919. Retrieved 2012-09-01.
- ^ Dictionary of National Biography, 1931-40, Oxford : Oxford University Press, 1949, p.784
- ^ Spink, February 2005 Medal Newsletter
- ^ Agnews press release for An Exhibition of paintings and drawings from the collection of Philip and Sybil Sassoon
- ^ http://www.theguardian.com/books/2015/may/16/double-lives-a-history-of-sex-and-secrecy-at-westminster
- ^ "Sir Philip Sassoon: Death in England". The Argus (28949) (Melbourne). June 5, 1939. p. 9.
- ^ http://www.telegraph.co.uk/finance/property/counties-of-britain/3348666/Counties-of-Britain-Kent-by-Clive-Aslet.html
- ^ http://www.countrylife.co.uk/culture/book-reviews/sassoon-the-worlds-of-philip-and-sybil-43530
- Robert Boothby. I Fight to Live (1947) Gollancz London
- Clive Aslet. The Last Country Houses (1982) Yale University Press New Haven and London ISBN 0-300-03474-1
- Christoper Hussey Country Life article, 17 January 1931 issue, pp. 66–7
- Mark Girouard. Life in the English Country House (1978) Yale University Press New Haven and London ISBN 0-300-02273-5
External links[edit]
- Hansard 1803–2005: contributions in Parliament by Sir Philip Sassoon
- Portraits of Sir Philip Sassoon at the National Portrait Gallery, London
See also[edit]
|Parliament of the United Kingdom
|Preceded by
Sir Edward Sassoon
|Member of Parliament for Hythe
|Succeeded by
Rupert Brabner
|Political offices
|Preceded by
William Leach
|Under-Secretary of State for Air
|Succeeded by
Frederick Montague
|Preceded by
Frederick Montague
|Under-Secretary of State for Air
|Succeeded by
Anthony Muirhead
|Preceded by
The Earl Stanhope
|First Commissioner of Works
|Succeeded by
Herwald Ramsbotham
|Baronetage of the United Kingdom
|Preceded by
Edward Sassoon
(of Kensington Gore)
- Conservative Party (UK) MPs
- Members of the Parliament of the United Kingdom for English constituencies
- UK MPs 1910–18
- UK MPs 1918–22
- UK MPs 1922–23
- UK MPs 1923–24
- UK MPs 1924–29
- UK MPs 1929–31
- UK MPs 1931–35
- UK MPs 1935–45
- English Jews
- Rothschild family
- Baronets in the Baronetage of the United Kingdom
- Sassoon family
- 1888 births
- 1939 deaths
- Companions of the Order of St Michael and St George
- Knights Grand Cross of the Order of the British Empire
- Knights of the Order of the Black Star
- British politicians of South Asian descent
- Royal East Kent Yeomanry officers
- LGBT politicians from England


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Keep up to date with the latest news and content from BMC Clinical Pathology and BioMed Central.
I Satish Rao*, Anand C Loya, KS Ratnakar and VR Srinivasan
Corresponding author: I Satish Rao firstname.lastname@example.com
BMC Clinical Pathology 2005, 5:11
© 2015
BioMed Central Ltd unless otherwise stated. Part of Springer Science+Business Media.


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We are situated in a quiet area 820m north of the historical centre of the city Trenčín. Our strategic location on the main trace – highway Bratislava – High Tatra is our advantage. Despite this fact, our guesthouse is situated in a silent place without any noise of traffic. We offer accommodation in comfortable rooms with private bathroom and toilet.Rooms are equipped with TV, satellite receiver, fan and a device for making coffee and tea. Refrigerator and DVD receiver will provide on request. Mineral water, coffee and tea in the room are free of charge. Rooms are single, double and triple. They are furnished in a practical style to suit the business travelers, tourists and families with children as well Size of rooms (excluding halls, bathroom and toilet) is from 12 to 24 square meters according on the room.
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text:
A method is disclosed for integrating a field programmable gate array (FPGA) with a microprocessor to form a single, multi-chip or stacked, hybrid processor module. The method includes the identification and parallel routing of selected I/O pins of the FPGA and microprocessor. The method further includes the identification and routing of control pins of the FPGA and microprocessor to a controller, and, the establishment of an interface between the controller, the FPGA and the microprocessor in order to develop a processor module for coordinated processing of data utilizing both the FPGA and microprocessor resources.
1. A method for integrating a field programmable gate array (FPGA) resource having a first set of defined input/output (I/O) ports with a data processor having a second set of defined I/O ports within a single module, comprising the steps of:
identifying I/O ports of the FPGA and processor operable in parallel;
identifying control ports of the FPGA and processor;
routing the control ports to a controller;
establishing a controller-to-FPGA (C:F) interface through the control pins of the FPGA;
establishing a processor-to-controller (P:C) interface through the control pins of the processor; and,
logically connecting the C:F and P:C interfaces;
wherein the step of indentifying I/O ports operable in parallel comprises the steps of:
identifying non-control, non-power, and non-ground ports of the FPGA and processor,
determining whether the identified ports are bi-directional,
determining whether bi-directional, identified ports are tri-stable, and
routing in parallel bi-directional, tri-stable identified ports.
2. The method of claim 1, wherein the step of identifying I/O ports operable in parallel includes the steps of:
determining whether non-bi-directional, identified ports are input ports;
determining whether non-bi-directional, identified, input ports receive signals during operation which force a hardwired change of state of the processor; and,
routing in parallel non-bi-directional, identified, input ports which are determined not to force a change of state of the processor.
3. The method of claim 1, wherein the step of identifying I/O ports operable in parallel includes the steps of:
determining whether non-bi-directional, identified ports are output ports;
determining whether non-bi-directional, identified, output ports are tri-statable; and
routing in parallel non-bi-directional, tri-statable, identified, output ports.
This invention relates generally to microprocessors, and more particularly to a modular, hybrid processor with a modularized controller and a field programmable gate array for combination with a selected microprocessor from a set of microprocessors.
Recent improvements in performance capabilities of data processors have included increasing the clock speed or adding additional execution units.
Alternatively, field programmable gate arrays (FPGAs) have been considered for either augmenting or replacing microprocessors in order to expand the limitations posed by the arithmetic logic units. Wholesale replacement of microprocessors with FPGAs generally requires the entire recoding of operating systems. On the other hand, redesigning microprocessors to include FPGA-like architecture presents its own set of design errors.
Therefore, a need has been perceived for a quick and safe way to enhance the arithmetic performance of microprocessors and to implement algorithms within reconfigurable hardware.
In accordance with the present invention, a hybrid, modular processor package and method for developing a hybrid, modular data processing package from microprocessor and field programmable gate array (FPGA) technology combines a microprocessor, an FPGA, and a modular controller chip in order to obtain enhanced performance over that of the microprocessor. The combination of the microprocessor, FPGA, and controller chips is effected by identifying and selectively routing the non-control pins of the respective chips in parallel to the hybrid package pins and routing respective control pins of the microprocessor and FPGA through the controller pins. The controller chip emulates the behavior of the selected microprocessor bus interface and provides a set of services to the FPGA, such as configuration and memory management. By creating a standard interface to the FPGA and different microprocessor bus interfaces, a configuration code compatible family of computing devices can be created.
FIG. 1 is a block diagram representation of a computer system including a hybrid data processor.
FIG. 1A is a block diagram representation of a computer circuit board including the computer system of FIG. 1.
FIG. 1B is a block diagram representation of a hybrid data processor including a random access memory which shows the interconnection of the respective elemental units.
FIG. 1C is a block diagram representation of a hybrid data processor produced by stacking chips according to the present invention.
FIG. 1D is a block diagram representation of a hybrid data processor produced in a multi-chip module according to the present invention.
FIG. 2 is a flow diagram illustrating the method for producing a hybrid data processor according to the present invention.
FIG. 3 is a flow diagram illustrating the sub-steps of the pin choosing, identifying, and routing steps as shown in FIG. 2.
FIG. 4 is a flow diagram illustrating a method for operating the hybrid data processor during power-on reset according to the interface logic developed as shown in FIG. 2.
FIG. 5A is a diagram illustrating parallel routing in which the microprocessor HOLD pin is paired with an FPGA pin through a logic gate.
FIG. 5B is a diagram illustrating parallel routing in which the microprocessor FLUSH pin is paired with an FPGA pin through a logic gate.
FIG. 5C is a diagram illustrating parallel routing in which the microprocessor BREQ pin is paired with an FPGA pin through a logic gate.
FIG. 5D is a diagram illustrating parallel routing in which the microprocessor PCHK# pin is paired with an FPGA pin through a logic gate.
FIG. 6 is a block diagram representation of a hybrid data processor including a clock and glue logic according to the present invention.
FIG. 7 is a block diagram representation of a hybrid data processor showing an input/output pinout according to the present invention.
FIG. 8 is a pictorial diagram of the hybrid data processor illustrating pin configurations.
With reference to FIG. 1, there is shown a block diagram of data processing system 100 which includes hybrid, modular data processor 101. Hybrid data processor 101 connects conventionally to a conventional memory unit 103 through data/control Input/Output (I/O) buses 105. Address controller 107 receives address and control instruction information from processor 101 over buses 109, and conventionally controls the addressing of data within memory device 103 by hybrid data processor 101 utilizing buses 110.
Referring to FIG. 1A, processor 101 may be implemented on computer circuit board 111 having female socket 112 corresponding to the package pins of processor 101. The socket mates for each package pin may be connected to respective circuitry including memory device 103 and address controller 107 through buses as shown in FIG. 1. In turn, circuit board 111 may be implemented within a computer system, such as a personal computer, having an operating system stored in memory device 103 for establishing an operating environment for processor 101 and any attached peripheral elements. Additionally, application software may be stored in memory device 103 which is operable on the computer system by a user through I/O devices, such as a keyboard and a display panel. The application software may include code to support user-defined configurations of hybrid processor 101.
With reference to FIG. 1B, a block diagram of hybrid processor 101 is shown to include microprocessor (MP) 113. Microprocessor 113 may be selected from a set of conventional microprocessors which may include an Intel X86 or Pentium, AMD or Cyrix XX86, Motorola 80XXX, and similar microprocessor chips, and connected directly to field programmable gate array (FPGA) 115 through address and data buses 121, 123. FPGA 115 may comprise a conventional Xilinx XC6216 FPGA chip. Controller 117 controls communication between MP113 and FPGA115 through communication and timing interfaces 125, 127, which transfer respective control and input/output (I/O) signals between the respective elements. Random access memory 119 may optionally connect directly to FPGA 115 through address and data buses 129, 131.
With reference to FIG. 1C, there is shown a block diagram representation of the preferred embodiment of hybrid data processor 101, which may be implemented as a single, stacked chip having multiple, connected levels with each level corresponding to a respective element. As shown, hybrid processor 101 comprises microprocessor (MP) 113 situated on a first level and pluggable into a second level, field programmable gate array (FPGA) 115 coupled to microprocessor 113, and controller unit 117 coupled to both, microprocessor 113 and FPGA 115. As a hybrid of a microprocessor and FPGA, processor 101 integrates FPGA and microprocessor technology to enhance algorithm execution performance. If the designed surface area for implementing data processor 101 onto a personal computer (PC) board is small, then a stacked design as shown in FIG. 1C may be preferred. However, if the designated surface area is large, then a multi-chip module (MCM) design may be used as shown in FIG. 1D. If desired, processor 101 may be implemented either with hardware, software, or both.
By stacking FPGA resources on microprocessor 113, FPGA 115 may be positioned at the center of the system as shown in FIG. 1C. With FPGA 115 positioned at the center of the system, FPGA 115 may access or utilize each of the microprocessor resources such as memory management coprocessors, bus controllers, and any other microprocessor accessible subsystem. If designed as a single chip, the multiple levels may be combined by integration of any or all of the respective components including microprocessor, FPGA, and controller elements. However, it may be more desirable to integrate the FPGA and controller elements 115, 117 onto a single modular chip, so that various microprocessors may be selected for use with the single modular chip.
Referring to FIG. 2, process 211 is shown in a flow chart representation to include a series of steps for producing hybrid processor 101. Process 211 may be implemented with a computer-aided design (CAD) program operated on a conventional personal computer, computer workstation, mainframe computer, or similar data processing system. The CAD program for implementing process 211 may be produced by utilizing conventional CAD programming packages appropriately modified according to the steps of process 211 herein described or may be written using conventional CAD programming techniques.
Process 211 initially identifies and selects FPGA 115 based upon pre-determined selection criteria, selection step 221. In the preferred embodiment, the selection criteria for FPGA 115 include rapid configurability (on the order of microseconds, preferably), fast access to the internal state of the registers in FPGA 115, and configuration space that is addressable as memory. The Xilinx XC40XX or XC62XX chips may be selected based upon these criteria. Other choices may include FPGAs produced by Atmels, ATT, Motorola, or Altera.
Microprocessor 113 and controller 117 are selected based upon pre-determined selection criteria, step 231. The selection criteria may often be determined by hardware design constraints or the desired operating system. The Intel '486 microprocessor has been selected in the prefered embodiment; however, microprocessor 113 may be selected from any of the commercially available x86 compatibles, Sparc, MIPS Power PC Alpha, or other such devices. Alternatively, microprocessor 113 may be chosen to be a digital signal processor, a memory device such as a random access memory, or other similar data processing device.
Microprocessor pin locations are identified which may be utilized in parallel with FPGA operations, step 241. Pursuant to Step 241, FPGA 115 (XC6216 chip) pins N�, W31, W�, S�, N31, E31, S31 and E� are routable in parallel. FPGA 115 also has a 32-bit data bus CD 31-CD� and a 15-bit address bus along with CA14-CA� (not shown). FPGA 115 pins OE, R/W, GCLK, G1, G2, GC1R, and Reset are Control Pins which are routable to controller 117 pursuant to step 251.
RAM 119 is a Static 256K memory (64K�32 bits), with sixteen address pins and 32 data pins directly connectable to associated pins on FPGA 115 as shown in FIG. 1B, and with CS, OE and R/W control pins routable through FPGA 115 to controller 117.
MP 113 includes control, data and address pins which may be identified during step 251 as by exemplar from Table 1, below. Those control pins identified in Table 1 with a '#' are active with a low input signal. The respective pin identities are provided by the manufacturer, for example, in the databook Microprocessors, Volume D, copyright Intel 1993, Pages 2-13 through 2-18. Pins D31-D� may be routed in parallel with W31-W�, CD 31-CD� and PKD31-PKD�, respectively. Similarly, pins D31, PKD31, W31 and CD31 may be wired together, and pins D�, PKD�, W� and CD� may be wired together.
Address lines A31-A4 may be connected in parallel A31, S31, PKA31 preferably are routed together A14, S14, CA14, PKA14 down to A4, S4, CA4, PKA4 preferably are routed together. Since many of the 486 pins are routed to the controller, additional FPGA 115 pins may be connected to 32-bit SRAM 119 pins including 32-bit data, 16-bit address, CS, OE, and R/W pins (referred to hereinafter as RD31-RD�, RA 15-RA�, RCS, ROE, RR/W).
RD31 and E31 through RD� and E� may be connected to FPGA 115 through buses 129, 131 as shown in FIG. 1B maintaining the data pins in the same most significant bit (MSB) to least significant bit (LSB) relationship as the D 31-D� pins of MP 113. By connecting RA� to N31, RA1-RA15 to N30-N16, RCS to N15, ROE to N14, and RR/W to N13, control of the internal RAM is provided to FPGA 115.
MP 113 (Intel 486 chip) has address lines A31-A2 and BE#0-BE#3 which should be made to appear linear to FPGA 115. In order for FPGA 115 to take control of processor 101, controller 117 should connect BE#O-BE#3 of MP 113 to the LSB's of FPGA 115 S�-S3. To simplify the controller design, 32-bit words are utilized as reads and writes. Thus, whenever FPGA 115 controls MP 113, controller 117 drives BE#O-BE#3 to a logic level �.
For FPGA 115, some pins should be reserved for the hardware operating system (HOS) of processor 101.
During control pin identification step 251, control pins of microprocessor 113 and FPGA 115 are identified and routed to controller 117. Control pins of FPGA 115 that preferably are routed to controller 117 include chip selects, write enables, output enables, configuration mode, clock, reset, and any other pins that have global effect on the behavior of the FPGA. Control pins of microprocessor 113 that preferably are routed to controller 117 include power, reset, and any other pins that force microprocessor 113 into a state not under program control. Since the control signals of microprocessor 113 are generally sensed by external devices connected to the respective microprocessor pins, controller 117 (and chip 101) should mimic the microprocessor behavior with respect to those pins.
During step 261, all other pins of microprocessor 113 and FPGA 115 and their associated signals are routed through controller 117. Each of these pins require evaluation in order to determine sequencing considerations and implementation of associated logic circuitry and/or software in the manner as described above.
During step 271, an FPGA-to-Controller (FC) interface is created between FPGA 115 and controller 117. For a given FPGA 115, the FC interface preferably is standardized in order to allow a design including a hardware object code and FPGA configuration file to be utilized across different platforms.
One function of controller 117 is the configuration of FPGA 115. During or prior to the implementation of a configuration, the number of pins of the selected FPGA 115 and MP 113 are determined and compared by controller 117. Either FPGA 115 has a number of pins greater than or equal to microprocessor 113, or FPGA 115 has less pins than microprocessor 113. If FPGA 115 has enough pins to cover microprocessor 113 then FPGA 115 can configure portions of itself without microprocessor 113 intervention.
In the case where the number of FPGA pins is greater than or equal to the number of pins of microprocessor 113, each of the microprocessor pins preferably is routed to FPGA 115 with the exception of the control (identified in step 251), clock and possibly the JTAG test pins, which preferably are routed to controller 117. If the number of FPGA pins is much greater than those of microprocessor 113, then other resources may be connected to FPGA 115, such as RAM or digital signal processors (DSPs).
Through the FC interface, controller 117 controls reset and reconfiguration of FPGA 115, issuance of control signals to FPGA 115, reading from FPGA 115, and clock signals. Controller 117 is configured to reset FPGA 115 at selected times, such as when there is a system reset with the microprocessor reset pin in the active state or a non-maskable interrupt. Controller 117 also is configured to maintain the status of FPGA 115 and to allow readability by microprocessor 113 through associated controller status pins. The controller status pins may be utilized to provide configure, configure error, busy (as when FPGA 115 has been configured and is currently processing data or instructions), ready-to-be-configured, and sticky signals.
Controller 117 includes a clock control section which receives signals from any clock signals delivered to the package pins of hybrid processor 101 and delivers a system clock signal to microprocessor 113 and at least one global clock buffer on FPGA 115 nearest to an FPGA I/O buffer operable in parallel with microprocessor data and address pins. The clock control section generates a variable clock signal operable from 0 to 100 MHz and routes this clock to any other FPGA global clock buffer in order to establish single-step clocking control and simplified debugging of FPGA 115.
Controller 117 may reconfigure FPGA 115 by directly decoding some memory space in the system. Through the use of mode pins of FPGA 115 which are routed to controller 117 during step 251, FPGA 115 may be powered up in a non-active (slave) mode and wait. When control logic within microprocessor 113 determines to utilize FPGA 115, microprocessor 113 writes data to the configuration address which controller 117 directs to an FPGA configuration pin and toggles any related control pins of FPGA 115 (such as CCLK on Xilinx 4000 chips.)
During step 281, an interface is created between microprocessor 113 and controller 117 (MC interface) to enable coordinated configuration and control of FPGA 115. For instance, controller 117 may decode addresses or address space that do not conflict with any other part of the system address space. In order to avoid addressing conflicts, FPGA configuration and control sections are included within controller 117 which may be designed to emulate, rather than include, four thirty-two bit storage or thirty-two bit I/O locations. The emulated memory may be defined such that register '0' stores status and control read/write control read only status information; register '1' stores configuration data during a write operation which is read back during a read operation; register '2' stores variable clock control (Read/write) information; and, register '3' is reserved by the manufacturer and is utilized differently for each FPGA 115 and microprocessor 113 combination.
Finally, step 291 includes designing any additional logic circuitry and/or software between the microprocessor/controller and FPGA/controller interfaces to facilitate communication for selected interactions.
Referring to FIG. 3, a flowchart of a preferred process for implementing identification step 241 is shown. Identification step 241 includes sub-steps wherein microprocessor pins are tested or evaluated according to whether the pins are control, power or ground pins (sub-steps 311, 312), bi-directional and tri-stated pins (sub-steps 321, 331), input pins which do not force a microprocessor action (sub-step 351, 352) or output pins which are tristatable (sub-steps 391, 331). Microprocessor control, power, or ground pins are neither routed in parallel nor to the controller (sub-steps 311, 312). Bi-directional and tri-stated pins (sub-steps 321, 331) can generally be run in parallel with FPGA operations and may therefore be routed in parallel (sub-step 341). For example, microprocessor pins for data I/O are generally bi-directional and can be run in parallel with FPGA 115 if the I/O pins can be tristated either by software control or through an external device. If the I/O pins cannot be tristated, then they must be connected to controller 117 for mixing and/or synchronizing with signals from and to FPGA 115 (sub-step 361). If a pin on the microprocessor is utilized for input only (sub-step 351) and does not cause microprocessor 113 to change condition (sub-step 352), then the input pin may be utilized directly in parallel with FPGA operations (sub-step 341). For example, a non-vectored interrupt signal causing a microprocessor to access an address and fetch an instruction is hardwired into the microprocessor and cannot be changed. Therefore, a non-vectored interrupt signal preferably is routed to controller 117 (sub-step 361) in order to provide control to FPGA 115 and to avoid potential conflict with transactions. If a microprocessor pin is utilized for output only (sub-step 391), the output pin is run to controller 117 (sub-step 361). For example, the address pins in some microprocessors are strictly used as output pins and represent system control signals which preferably are run to controller 117 (sub-step 361) in order to permit FPGA 115 to control data processor 101 and associated peripherals or connected devices. If microprocessor 113 has a coprocessor port, it will have coprocessor control signals which are outputs of the microprocessor and inputs to the coprocessor. If these microprocessor outputs are always driving, then they preferably are routed to controller 117 (sub-step 361). Controller 117 can then mix and/or synchronize these signals between microprocessor 113 and FPGA 115 and provide the FPGA direct access to the coprocessor.
Referring to FIG. 4, a power-up sequence is illustrated. To initialize the power-up sequence of chip 101, a power-on reset (POR) signal, generated from an external system and directed to chip 101, may be passed directly to controller 117 rather than to microprocessor 113, (sub-step 411), by routing the POR pin of chip 101, either through logic circuitry and/or software. Upon receipt of the POR signal, controller 117 resets FPGA 115 and monitors the FPGA pin status to determine that FPGA 115 has been initialized, (sub-step 431). Once FPGA 115 has been initialized, the POR signal is delivered to microprocessor 113 from controller 117, (sub-step 451). In the case where FPGA 115 includes a random access memory (RAM) that replaces a system RAM, controller 117 may be required to generate its own POR signal and not decode FPGA address locations until FPGA 115 has been reset.
In order to further coordinate control of processes within data processor 101, some pins utilized for receiving control input signals to microprocessor 113, such as HOLD or FLUSH, may be logically connected through controller 117 with an associated pin from FPGA 115. Exemplar circuits are shown in FIG. 5A, wherein the HOLD instruction signal directed to a HOLD pin on a processor, such as a '486 microprocessor, is defined to be an active high (or positive voltage) input signal and is input paired with a signal from an associated FPGA pin into logical OR gate 511, and in FIG. 5B, wherein a FLUSH instruction signal directed to a FLUSH pin on a processor, such as the '486 microprocessor, is defined as an active low (zero or negative voltage) input signal and is input paired with a signal from an associated FPGA pin into logical NOR gate 521. These exemplary, logically coupled circuits enable an external system or FPGA 115 to control activation of pre-determined functions on microprocessor 113. Pins, such as the HOLD or FLUSH pins, need only be coupled through controller 117 to the external system if the respective physical package pins of chip 101 are always driven by the external system; otherwise, the FPGA pin, and corresponding signal therefrom, may be routed in parallel with the external input signal.
Similarly, some microprocessor output signals may preferably be logically coupled within controller 117 if they are always being driven by microprocessor 113. An example circuit is shown in FIG. 5C, wherein the bus request (BREQ) control pin of microprocessor 113 is defined to be continuously driven, such as with a '486 microprocessor. The signal generated from microprocessor 113 and an associated signal generated from FPGA 115 are input paired into logical OR gate 531 implemented in controller 117 to provide a coordinated output signal to the associated BREQ control pin of data processor 101. A second example circuit is shown in FIG. 5D, wherein the PCHK# pin is defined to be continuously driven with an active low signal, such as from a '486 microprocessor. The signal generated from microprocessor 113 and an associated signal generated from FPGA 115 are input paired into logical NOR gate 541 implemented in controller 117 to provide a coordinated output signal to the associated PCHK# control pin of data processor 101.
For JTAG operation, TCK and TMS control pins associated with microprocessor 113, FPGA 115, and controller 117 can be routed in parallel to physical package pins (PPP) of data processor 101.
Referring to FIG. 6, hybrid processor 101 is shown with parallel connected PPP TCK and TMS pins 611, 613. PPP TDI and TDO pins 615, 617 are shown respectively connecting to MP TDI and controller TDO pin locations 619, 621. MP TDO and FPGA TDI pin locations 623, 625 are connected. FPGA TDO and controller TDI pin locations 627, 629 are also connected.
Referring to FIG. 7, hybrid processor 101 is shown in a block diagram including glue logic 711 and clock 713. Glue logic 711 and clock 713 may be included onboard a single chip with hybrid processor 101 or may be located off-chip connecting to hybrid processor 101 through associated bus lines. Glue logic 711 may include software and/or hardware connecting MP 113 with FPGA 115 and controlled by controller 117 for integrating operations of MP 113 and FPGA 115.
Referring to FIG. 8, a 32-bit Data and 32-bit Linear Address pin configuration 801 associated with the pin locations of FPGA 115 is shown. For a selected microprocessor, the pinout of FPGA 115 must be known in order to configure the FPGA-MP interface, to pass valid data to microprocessor 113 and to send data out to a valid address in memory 103. Additionally, the FPGA-MP interface should be connected to MP control pins for user requested burst mode reads or writes and microprocessor interrupt. Since many microprocessors pinouts are the same or compatible, an FPGA-MP interface developed for a given FPGA may be usable for a variety of MPs 113 with compatible pin configurations. Therefore, multiple microprocessors 113 and/or FPGAs 115 may be connected in the hybrid processor 101, such as is shown in FIG. 8.
With further reference to FIG. 8, master driver portion 881 of FPGA 115 connects to main Data bus 123 (shown in FIG. 1B) and the North-east corner 883 contains the FPGA-controller interface to controller chip 117. In the case where FPGA 115 operates as master driver 881, a slave-only or coprocessor is replaced by a slave driver.
Hereinafter, the Hardware driver (HD) is defined to mean the logic used to control interaction between the user logic functions (ULF) and the outside world. In both slave and master mode the memory of HD can remain the same. The master mode HD provides FPGA 115 with the ability to control the processor adding and control bus 109 and request data from the outside world. In master mode, FPGA 115 can reconfigure portions of itself. When FPGA 115 is operated in slave or coprocessor mode, MP 113 can deliver data to the user functions (programs) through the FPGA-MP interface or by requesting data while the FPGA 115 monitors and evaluates the data lines and address lines (south) to determine what data is intended for the user functions. Data cannot be written with this method and should be taken from an MP Port directly.
MP 113 (e.g., Intel 486) has 5 lines associated with parity DP�-DP3 and PCHK#. To simplify the design, MP 113 will not check parity on reads this means that PCHK# can be routed directly to the 486 Physical Package pin PCHK# of processor 101. Parity must still be generated on writes from FPGA 115 when FPGA 115 is in master mode.
FPGA pins N�-N12 are connected to controller 117. In each system these control pins and the logic that drives them will be different. FPGA pins N�-N3 and DP�-DP3 may be assigned so that even parity may be generated as described on page 2-87 of MICROPROCESSORS: Volume II, Intel 486 Microprocessors.
With continued reference to FIG. 8, the FPGA pinout is shown as may be utilized in a design configuration. In accordance with process 211, I/O pin N� is next to W31 and W� is next to S� and N31 is next to E31 and S32 is next to E�, each of which may connect in parallel. The XC6216 also has a 32-bit data bus connecting to data pins CD31-CD0, and a 15-bit address bus connecting to address pins CA14-CA0, and control pins CS, OE, R/W, GCLK, G1, G2, GC1R, and Reset. The attached RAM is A10 Static 256K organized as 64K by 32 bits 16 address lines A8 and 32 data lines A9. With CS, OE and R/W which will end up A7 user control.
Pins on the 486 identified during process 211 are listed in Table 1. The respective pin identities are found in the manufacturer provided in the databook Microprocessors, Volume D, copyright Intel 1993, Pages 2-13 through 2-18. For the rest of the description PKXXX will signify a physical package pin and XXX will be a pad on the IC. For example, PKUP# will mean the 486 package pin UP# which for 168 pin PGA is pin C11. Reference to UP# means the UP# pad on the 486 die.
In accordance with process 211, pins D31-D� are respectively routed in parallel with pins W31-W�, CD-31-CD� and PKD31-PKD�. For instance, pins D31, PKD31, W31 and CD31 may all be wired together as may D�, PKD�, W� and CD�. Address pins A31-A4 may respectively be tied in parallel with pins S31-S4, CA31-CA4, and PKA31-PKA4. For instance, pins A31, S31, CA31, and PKA31 may be tied together and pins A4, S4, CA4, and PKA4 may be tied together. Since many of the 486 pins must be routed to the controller, unused XC6216 user pins may be elected to be connected to a 32 bit SRAM in the same package which may include thirty-two data, sixteen address, and control CS, OE and R/W pins. The SRAM pins may be designated RD31-RD�, RA 15-RA�, RCS, ROE, RR/W, respectively. RD31 and E31 may be connected, as may be RD� and E� in order to connect the data line in the same MSB-LSB relationship as data pins D31-D� of the MP. Additionally, pin RA� may be connected to N31, RAl may be connected to N30, and so forth such that RA15 may be connected to N16, RCS may be connected to N15, ROE may be connected to N14, and RR/W may be connected to N13 in order that the XC6216 port be given control of the internal ram. Similarly, the address lines may be connected to provide a linear appearance to the XC6216 port. The 486 has address lines A31-A2 and BE#0-BE#3. In order to design the XC6216 to control the system, the controller must develop pins BE#O-BE#3 from the LSB's of the XC6216 Pads S�, S1. To simplify the controller design, the design requirement may be imposed to read and write thirty-two bit words so that the XC6216 FPGA controls the 486 MP by driving the controller pins BE#O-BE#3 to a logic level of �. Certain ports of the XC6216 FPGA must be reserved for the hardware operating system (HOS). The east portion of the XC6216 chip is connected to the main data bus and the north-east corner contains the interface to the controller chip.
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