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Systems and methods automatically modify a laser-based system for processing target specimens such as semiconductor wafers. In one embodiment, the laser-based system detects a trigger associated with a processing model. The processing model corresponds to a set of wafers. In response to the trigger, the system automatically adjusts one or more system parameters based on the processing model. The system then uses the modified system parameters to selectively irradiate structures on or within at least one wafer in the set of wafers. In one embodiment, the trigger includes variations in a thermal state related to a motion stage. In response to the variations in the thermal state, the system operates the motion stage in a series of movements until a thermal equilibrium threshold is reached. The sequence of movements may, for example, simulate movements used to process a particular wafer.
1. A method for preheating a laser-based system for processing target specimens, the method comprising:
detecting variations in a thermal state; and
in response to the variations, preheating the laser-based system before laser processing structures on or within a target specimen, wherein the preheating generates heat to reduce the detected variations in the thermal state, and wherein the preheating comprises:
selecting a preheating motion sequence; and
operating a motion stage in a sequence of moves according to the selected preheating motion sequence without irradiating any of the structures on or within the target specimen.
2. The method of
3. The method of
generating a laser beam; and
preventing the laser beam from reaching the target specimen.
4. The method of
generating a laser beam; and
defocusing the laser beam so as to prevent processing of the structures on or within the target specimen.
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
deactivating a laser; and
while the laser is deactivated, operating the motion stage in a sequence of moves corresponding to movements used to irradiate the structures on or within the target specimen.
This disclosure relates generally to manufacturing semiconductor integrated circuits. In particular, this disclosure relates to the use of laser beams to process structures on or within a semiconductor integrated circuit.
Laser-based semiconductor processing systems are generally used, for example, to drill, machine, trim, sever, scribe, mark, cleave, make, heat, alter, diffuse, anneal, and/or measure a structure or its material on or within a semiconductor substrate. To improve throughput during fabrication of integrated circuits (ICs), it is also generally desirable that laser-based processing systems accurately and quickly process selected structures on or within the semiconductor substrate. However, conventional laser-based processing systems are typically tuned and operated with a conservative set of parameters to provide good accuracy for all types of ICs intended to be processed by the system. This "one-size-fits-all" approach often results in reduced processing speeds and overall reduced throughput.
A semiconductor link processing system, for example, typically provides the same level of accuracy when severing links on any IC. During fabrication, ICs often incur defects for various reasons. For that reason, IC devices are usually designed to include redundant circuit elements, such as spare rows and columns of memory cells in semiconductor memory devices, e.g., a DRAM (dynamic random access memory), an SRAM (static random access memory), or an embedded memory. Such devices are also designed to include particular laser-severable links between electrical contacts of the redundant circuit elements. Such links can be removed, for example, to disconnect a defective memory cell and to substitute a replacement redundant cell. Links may also be removed for identification, configuration and voltage adjustment. Similar techniques are also used to sever links in order to program or configure logic products, such as gate arrays or ASICs (application-specific integrated circuits). After an IC has been fabricated, its circuit elements are tested for defects, and the locations of defects may be recorded in a database. Combined with positional information regarding the layout of the IC and the location of its circuit elements, a laser-based link processing system can be employed to remove selected links so as to make the IC useful.
Laser-severable links are typically about 0.5-1 microns (μm) thick, about 0.5-1 μm wide, and about 8 μm in length. Circuit elements in an IC, and thus links between those elements, are typically arranged in a regular geometric arrangement, such as in regular rows. In a typical row of links, the center-to-center pitch between adjacent links is about 2-3 μm. These dimensions are representative, and are declining as technological advances allow for the fabrication of workpieces with smaller features and the creation of laser processing systems with greater accuracy and smaller focused laser beam spots. Although the most prevalent link materials have been polysilicon and like compositions, memory manufacturers have more recently adopted a variety of more electrically conductive metallic link materials that may include, but are not limited to, aluminum, copper, gold nickel, titanium, tungsten, platinum, as well as other metals, metal alloys, metal nitrides such as titanium or tantalum nitride, metal silicides such as tungsten silicide, or other metal-like materials.
Conventional laser-based semiconductor link processing systems focus a single pulse of laser output having a pulse width of about 4 to 30 nanoseconds (ns) at each link. The laser beam is incident upon the IC with a footprint or spot size large enough to remove one and only one link at a time. When a laser pulse impinges a polysilicon or metal link positioned above a silicon substrate and between component layers of a passivation layer stack including an overlying passivation layer, which is typically 2000-10,000 angstroms (Å) thick, and an underlying passivation layer, the silicon substrate absorbs a relatively small proportional quantity of infrared (IR) radiation and the passivation layers (silicon dioxide or silicon nitride) are relatively transparent to IR radiation. IR and visible laser wavelengths (e.g., 0.532 μm, 1.047 μm, 1.064 μm, 1.321 μm, and 1.34 μm) have been employed for more than 20 years to remove circuit links.
Many conventional semiconductor link processing systems employ a single laser pulse focused into a small spot for link removal. Banks of links to be removed are typically arranged on the wafer in a straight row, an illustrative one of which is shown in
Impingent upon selected links in the link run 120 is a laser beam whose propagation path is along an axis. The position at which that axis intersects the workpiece continually advances along the link run 120 while pulsing the laser to selectively remove links. The laser is triggered to emit a pulse and sever a link when the wafer and optical components have a relative position such that the pulse energy impinges upon the link (e.g., trigger position 130). Some of the links are not irradiated and left as unprocessed links 140, while others are irradiated to become severed links 150.
For a wafer 240 comprising DRAM, for example, memory cells (not shown) may be located in the areas 322 between the X-axis link runs 310 and the Y-axis link runs 320. For illustrative purposes, a portion of the wafer 240 near an intersection of an X-axis link run 310 and a Y-axis link run 320 is magnified to illustrate a plurality of links 324 arranged in groups or link banks. Generally, the link banks are near the center of a die, near decoder circuitry, and not above any of the array of memory cells. The links 324 cover a relatively small area of the total wafer 240.
System parameters that may impact the time spent executing link runs, and thus throughput, include the laser pulse repetition frequency (PRF) and motion stage parameters such as stage acceleration, bandwidth, settling time, and the commanded stage trajectory. The commanded stage trajectory includes acceleration and deceleration segments, constant velocity processing of link banks, and "gap profiling" or accelerating over large gaps between links to be processed in a link run.
These and other system parameters may change between semiconductor wafers, between different types of semiconductor wafers, and/or with time. However, conventional semiconductor link processing systems typically use predetermined hardware configurations and motion profiling parameters, regardless of the differences between semiconductor wafers and/or system characteristics that change with time. Thus, processing accuracy may exceed expected or desired levels at the cost of reduced throughput for some semiconductor wafers.
The embodiments disclosed herein provide systems and methods for processing a plurality of structures, such as laser-severable links, on a semiconductor substrate. In one embodiment, a method detects a trigger associated with a processing model for a laser-based system. The processing model corresponds to a set of target specimens. The target specimens may include, for example semiconductor wafers. In response to the trigger, the method automatically adjusts one or more system parameters based on the processing model. The method also operates the laser-based system using the one or more adjusted system parameters to selectively irradiate structures on or within at least one target specimen in the set of target specimens.
In one embodiment, a system for processing target specimens includes a laser source configured to generate a laser beam. The system also includes a motion stage configured to position a target specimen with respect the laser source so as to selectively irradiate structures on or within the target specimen with the laser beam. During variations in a thermal state, the laser source is prevented from processing the structures while the motion stage performs a series of moves to adjust the thermal state to within a predetermined thermal equilibrium threshold. In one such embodiment, the laser source is deactivated while the laser source performs the series of moves. In other embodiments, the laser source is not deactivated such that energy from the laser source adds to the overall thermal state. For example, while the laser source is active, the motion stage according to one embodiment performs the series of moves to adjust the thermal state without a target specimen (workpiece) positioned on the chuck. As another example, the laser beam according to one embodiment is defocused so as to reduce or eliminate damage to the target specimen while the motion stage performs the series of moves to adjust the thermal state to within the predetermined thermal equilibrium threshold.
In one embodiment, a method for preheating a laser-based system for processing target specimens includes detecting variations in a thermal state. The method also includes simulating, in response to the variations, movement of a laser spot with respect to a plurality of structures on or within a target specimen.
In one embodiment, a laser processing system includes means for detecting variations in a thermal state, and means for simulating movement of a laser spot with respect to a plurality of structures on or within a target specimen. The simulated movement is in response to the detected variations in the thermal state.
Additional aspects and advantages will be apparent from the following detailed description of preferred embodiments, which proceeds with reference to the accompanying drawings.
With reference to the above-listed drawings, this section describes particular embodiments and their detailed construction and operation. The principles, methods, and systems disclosed below have general applicability for processing any structure on or within a semiconductor substrate using laser radiation for any purpose. While the examples and embodiments that follow are described in the context in which those structures are laser-severable links on or within an IC (e.g., memory device, logic device, optical or optoelectronic device including LEDs, and microwave or RF devices), other structures besides laser-severable links can be processed in the same or similar manner. Thus, the teachings set forth herein are equally applicable to the laser processing of other types of structures, such as electrical structures that become conductive as a result of laser radiation, other electrical structures, optical or electro-optical structures, and mechanical or electro-mechanical structures (e.g., MEMS (micro electromechanical structures) or MOEMS (micro opto-electro-mechanical structures)).
The purpose of the irradiation may be to sever, cleave, make, heat, alter, diffuse, anneal, or measure a structure or its material. For example, laser radiation can induce a state change in a structure's material, cause the migration of dopants, or alter magnetic properties—any of which could be used to connect, disconnect, tune, modify, or repair electrical circuitry or other structures.
Generally, the same level of accuracy is not required for all wafers processed on a link processing system. Further, conventional link processing systems typically do not allow users to optimize a tradeoff between the system's accuracy and throughput. In one embodiment disclosed herein, however, a user is allowed to select parameters in, for example, a link processing recipe file to optimize or improve throughput for a desired accuracy. Allowing recipe configurable system parameters allows for higher throughput with a lower, yet acceptable, accuracy when processing some wafers. When demanded or desired, the link processing system may provide a comparatively higher accuracy to other wafers using a slightly reduced throughput.
In addition, or in another embodiment, the link processing system may automatically select system parameters based on a processing model corresponding to the link processing system and a particular set of wafers. The processing model may be configured to dynamically optimize or improve throughput for a desired accuracy. Thus, for example, the link processing system may automatically update system parameters when processing wafers with different accuracy requirements or to compensate for time varying parameters. The parameters may vary, for example, due to transient conditions within the link processing system such as when the system is warming up. The parameters may also vary, for example, due to transient external conditions such as changes in ambient temperature or vibrations.
According to certain embodiments, users and/or link processing systems may select conservative processing parameters that cause the system to process wafers relatively slowly in order to satisfy a more stringent efficiency specification. The users and/or link processing systems may also select conservative processing parameters when, for example, the system may be in a less-accurate state (e.g., while the system is warming up). Thus, the users and/or link processing systems may selectively use an appropriate balance between throughput and accuracy when processing different wafers.
In addition, or in other embodiments, the users and/or link processing systems may select different processing parameters and system configuration parameters to achieve a desired accuracy (with reduced throughput) when system conditions and/or fabrication environment conditions require more conservative wafer setups. The more conservative setups may be based upon present and past conditions and/or the particular wafers to be processed. When conditions change (e.g., an equilibrium is reached), the user and/or link processing systems may then select parameters that produce improved throughput.
In one embodiment, the link processing system automatically enhances system accuracy without any mechanical changes using motion preheating. For example, during a warm up period, after a period of time with no activity, and/or when switching from a first type of wafer to a second type of wafer, the link processing system may perform a sequence of moves using a motion stage until the system reaches a predetermined thermal equilibrium threshold.
As used herein: the term "on" means not just directly on but atop, above, over, or covering, in any way, partially or fully. Also the term "substantially" is a broadening term that means about or approximately but does not imply a high degree of closeness.
Reference is now made to the figures in which like reference numerals refer to like elements. For clarity, the first digit of a reference numeral indicates the figure number in which the corresponding element is first used. In the following description, numerous specific details are provided for a thorough understanding of the embodiments disclosed herein. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of the specific details, or with other methods, components, or materials. Further, in some cases, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
I. Recipe Dependent Processing Parameters
Link processing systems generally include "recipes" that describe how wafers are to be processed. However, conventional link processing recipe files do not allow users to modify the system to maximize or improve throughput with acceptable accuracy on a variety of wafer products. For example,
The physical layout parameters 410 may specify physical dimensions of a wafer such as die size and locations of alignment targets. The laser energy parameters 412 may specify a first laser energy to use for scanning alignment targets and a second laser energy to use for processing links. The field setup parameters 414 may specify targets, target timeouts, and respective target shapes in alignment fields, focus fields, and processing fields. Alignment fields include calibration data for XY direction alignment of the laser to the workpiece. Focus fields include calibration data for Z direction alignment of the laser to the workpiece. Processing fields, which are typically much larger than alignment fields, define the field sizes for processing link runs. For example, a 300 mm wafer may be processed using four to six processing fields. However, one to three processing fields or more than six processing fields may also be used. A link run, which may be as long as the X or Y dimension of the alignment field, may span multiple alignment/focus fields. The error handling parameters 416 may specify, for example, recovery mechanisms when poor quality scans are detected and "target timeout times" that specify a maximum duration for which the system will use data gathered during an alignment scan (sometimes referred to herein as a beam-to-work (BTW) scan). The error handling parameters 416 may also include, for example, target scan positioning tolerances.
In one embodiment disclosed herein, a link processing system that includes a processor allows users to selectively specify additional parameters in order to optimize or improve throughput for a selected wafer. For example,
The motion tuning parameters 610 may specify, for example, controller tuning values for specific actuators within the link processing system's motion stage. The maximum acceleration 612, the maximum velocity 614, and the required settle time 616 may be specified for each axis (e.g., an X-axis and a Y-axis) of the motion stage. The settle algorithm 618 may include a set of instructions for causing a processor to determine whether the motion stage has settled after a particular move along a particular axis. The settlement algorithm 618 may also include a set of instructions for determining whether the stage is sufficiently settled at a constant velocity after the velocity of a particular axis has been changed. In another embodiment, the settle algorithm 618 may be embodied in hardware logic. The settle tolerances 620 may specify tolerable position and velocity errors that the motion stage satisfies after a particular move before the settle algorithm 618 determines that the move is settled.
The error handling parameters 630 may specify, for example, hardware error detection parameters, error tolerances, monitoring configurations, and interlocking parameters (e.g., error conditions under which further link processing is stopped). For example, a wafer that is able tolerate relatively large cross-axis errors may include a recipe configuration allowing larger error tolerances before errors are triggered and processing is halted.
For a better understanding of the motion profiling parameters 512, reference is now made to
When there is a large gap 850 between subsequent links in a link run, the system accelerates to span the gap 850 in less time and then decelerates near the end of the gap to reach a nominal velocity once again. The acceleration and deceleration results in a gap profile 860 in the link velocity profile 810. At the beginning of a link run, the system undergoes an initial acceleration 870 from a resting position followed by a period of settling 880. At the end of a link run, the system undergoes a deceleration 890 back down to zero velocity. Thus, the typical operations that the system performs during execution of a link run include ramping up the stage to constant velocity, settling, processing links at constant velocity, accelerating (gap profiling) over any large gaps, and ramping back down to zero velocity at the end of the run.
A gap profiling operation involves accelerating, decelerating, and settling to travel between two links in less time than would be required at constant velocity. The increased throughput provided by gap profiling is dependent upon the quantity and spacing of large gaps between links, the acceleration capabilities of the stage, the settle time, and the link run velocity. A greater time savings results on products that have many large gaps in link runs and a small link pitch.
Generally, the time spent accelerating and decelerating at the start and end of link runs is approximately 1.5% of the time spent on link runs. The time saved with gap profiling is approximately 50% of the time that would be required to traverse the link runs at constant velocity. These numbers vary widely for different types of wafers. Wafers with few or no large gaps between links may not receive any benefit from gap profiling. On the other hand, products with sparse or random link layout may receive greater benefit from gap profiling.
Thus, returning to
An artisan will recognize from the disclosure herein that the parameters shown in
II. Automatic System Adaptation
As discussed above, in one embodiment, a user may directly specify one or more parameters in the link processing recipe file 500. The link processing system may then process one or more wafers using the specified parameters. In addition, or in another embodiment, the link processing system automatically adjusts (e.g., using the processor) hardware configuration parameters, profiling parameters, process field setup, alignment target setup, motion preheating, combinations of the foregoing, and other system parameters. The automatically configured parameters may be specified in the link processing recipe file 500 or in another system setting, as discussed above.
In one embodiment, the link processing system selects a set of parameters to use based on different system states, system configurations, system properties, system parameters, processing history, product processing history, motion profiling history, and/or parameters specified in recipe files. For example, the link processing system may select a set of system parameters based on measured temperatures, thermal drift rates, environmental conditions, and/or other parameters.
In addition, or in another embodiment, the link processing system may configure itself based on user-specified recipes so as to maximize or improve throughput while satisfying desired processing parameters such as accuracy, laser stability, and laser pulse width.
In addition, or in another embodiment, the link processing system may automatically adapt system parameters such as motion profiles, process field setup, and optical spot properties. Such adaptation may involve, for example, correlating parameter settings, properties, and results. The correlated results may include, for example, measured dynamic errors, drift rates, drift magnitudes, post processing yields, and/or post processing product damage analysis. The correlated properties may include, for example, statistical metrics of system error (e.g., motion stage errors such as cross-axis, on-axis, and/or fast steering mirror (FSM) errors) and prior knowledge of wafer properties, and/or wafer property variations (e.g., layer thicknesses or measured reflectivity). The correlated parameters may include, for example, motion profiles, settle times, process field shape and size, and laser pulse properties.
In addition, or in another embodiment, the link processing system may adaptively or automatically configure some or all wafer setup parameters, including setup parameters that are typically configured manually in conventional link processing recipe files, based on correlations of parameter settings, properties, wafer product yield, and/or processing results. After performing such an adaptive setup, in one embodiment, the link processing system (or a user) may then decide to discontinue the adaptations during regular wafer processing.
In one embodiment, automatic system adaptation (whether for setup or regular processing) may use rule based decisions or parameters, modeling, prediction, characterizations of the system or system component behavior (e.g., laser and/or mechanical components), wafer properties, accuracy budgeting, artificial intelligence, fuzzy logic, neural networks, cost function minimization, or other algorithmic implementation or methodology for changing system parameters and system behavior for achieving desired process results.
In addition, or in another embodiment, the link processing system accurately records (e.g., in a log file) changes made by the system and/or a user for troubleshooting of system errors, documentation, statistical analysis, and process control. Recording such data may be useful, for example, when the link processing system has the ability to adapt and automatically make processing changes. The link processing system captures and logs data that characterizes how the system processed the wafers. The data may include, for example, the processing parameters, configurations, hardware configurations, control parameters, motion profile parameters, processing decisions, adaptations, system behavior, system movement, system preconditioning, sensor measurements, controller variables or states, error conditions, and any other data necessary to understand how the processing proceeded. The data may include raw data and/or statistical metrics derived from the data. In one embodiment, the link processing system is also configured to reproduce or replay the recorded behavior on other systems for testing and troubleshooting.
The trigger may include, for example, a detected system state, a wafer product yield, a measured processing result, a user-modification to a hardware configuration parameter, a user-modification to a motion profiling parameter, and/or a change to wafer fabrication data. The trigger may also include, for example, a change in wafer product or type.
If the link processing system does not detect a trigger, the process 900 includes operating 912 the link processing system using current (e.g., unmodified) parameter values to selectively irradiate one or more structures on or within a wafer. When the link processing system detects a trigger, the process 900 includes automatically adjusting 914 one or more system parameters based on a processing model corresponding to a selected set of wafers. The process 900 also includes operating 916 the link processing system using the one or more adjusted parameters to selectively irradiate one or more structures on or within a wafer in the selected set of wafers.
Various example embodiments are provided below for configuring and/or adapting processing parameters, system parameters, alignment parameters, hardware configuration parameters, motion profiling parameters, processing pulse parameters, and other parameters based upon variations in wafer product type, location dependent system variations, wafer variations, system state variations, system history variations, ambient environmental variations, product yield variations, link blow quality variations, and variations in the results of product processing.
III. Example Responses to a Preheating Trigger
A. Motion Preheating
In one embodiment, the preheat trigger is based on a processing history of the link processing system. For example, the link processing system may generate the preheat trigger after being idle for a predetermined period of time prior to processing a wafer. In addition, or in another embodiment, the preheat trigger may be based on a particular wafer or type of wafer selected to be processed by the link processing system. For example, the link processing system may generate the preheat trigger when switching from a first wafer product type to a second wafer product type. Processing the first wafer product type may cause the motion stage to reach a different steady state thermal equilibrium than that reached when processing the second wafer product type. Thus, a first processing model may be associated with the first wafer product type and a second processing model may be associated with the second wafer product type.
By way of example, the link processing system may generate the preheat trigger under a number of different scenarios including, without limitation: when the system has completed processing all wafers in a lot and is waiting to receive new lots of wafers; when the system has been off and is being warmed up prior to any processing; and when the system has been processing one wafer product and is being switched to a different wafer product.
In this example embodiment, undesirable thermal drift is minimized or reduced using motion stage movement to preheat the link processing system. By subjecting the motion stage to some "idle motion" (e.g., without irradiating structures on or within a wafer), a thermal equilibrium or a state much closer to the actual operating thermal equilibrium may be reached.
Thus, the process 1000 further includes selecting 1012 a preheating motion sequence that appropriately heats the actuators in the motion stage. In one embodiment, the selected preheating motion sequence includes a sequence of moves corresponding to the sequence expected to process a next wafer. This may be the actual move sequence or an abbreviated/modified version. In another embodiment, the selected preheating motion sequence includes a sequence of moves used for the last or most recently processed wafer. This may be the actual move sequence or an abbreviated/modified version. In another embodiment, the selected preheating motion sequence includes a standard or predetermined sequence of moves. A standard sequence of moves may also be determined for a specific type of wafer product or recipe.
In another embodiment, the selected preheating motion sequence is selected to induce specific changes in the thermal state of the system. For example, if the first wafer product type in our example makes little or no use of actuators corresponding to the Y-axis and heavy use of actuators corresponding to the X-axis, and the second wafer product type makes heavy use of the actuators corresponding to the Y-axis and little or no use of the actuators corresponding to the X-axis, then the selected preheating motion sequence (e.g., when switching from the first wafer product type to the second wafer product type) may be configured to heat the actuators corresponding to the Y-axis and to let the actuators corresponding to the X-axis cool.
The process 1000 further includes operating 1014 the motion stage according to the selected preheating motion sequence. The selected preheating motion sequence may be initiated immediately after detecting the preheat trigger, after a delay period to allow one or more wafers in a current lot to be processed, and/or before processing a next wafer in a current wafer lot or a next wafer lot.
In one embodiment, the process 1000 includes selectively triggering 1015 the laser to generate pulses. These pulses may be delivered through the train of optics, selectively blocked, or blocked from reaching the workpiece. In embodiments where the pulses are not blocked, they may be delivered with a defocused spot or delivered when there is no wafer on the chuck. Generating pulses during the preheating cycle thermally stabilizes the laser and any associated pulse switching hardware prior to processing. Thus, thermal drift associated with the laser beam and the beam path may be reduced.
The process 1000 further includes determining 1016 whether the idle motion has adjusted the thermal state of the link processing system to be within a predetermined thermal equilibrium threshold. The predetermined thermal equilibrium threshold represents an acceptable range of variations in the system's thermal state. Once the system's thermal state is within the predetermined thermal equilibrium threshold, the process 1000 includes operating 1018 the link processing system so as to maintain the predetermined thermal equilibrium threshold while selectively irradiating structures on or within a wafer.
Determining whether to initiate motion preheating, selecting the specific preheating sequence, selecting the duration of the preheating, and/or determining that motion preheating is complete may be based on, without limitation: a measured or predicted thermal state of the link processing system or a comparison of this thermal state with a desired thermal state; a length of time the system has been idle or an elapsed time since the system was initialized; a type of wafer product previously processed and/or expected to be processed next; a sequences of specific moves (measured and/or predicted) previously processed and/or expected to be processed next; a history, prediction, and/or statistical analysis of move commands, duty cycles, current commands, voltage commands, and/or other parameters relevant to stage motion or system thermal state; measurements of thermal drift, including measurements based on sensors (e.g., position and/or temperature), to measure mechanical system components, measurements based on direct measurements of alignment targets, reference targets, wafers, accuracy wafers, or other metrology structures using the system's processing laser, a metrology laser, or other alignment sensors such as cameras; and/or one or more parameters such as desired system accuracy, allowable thermal drift for a selected wafer product, wafer product processing margins (e.g., on-axis, cross-axis, and/or focus margin), system error budget, and/or characterizations of component drift.
Algorithms for determining whether to initiate motion preheating, selecting the specific preheating sequence, selecting the duration of the preheating, and/or determining that motion preheating is complete, based on the above factors, may be implemented, for example, as rule based cases that may minimize or reduce cost functions. The algorithms may use, for example, artificial intelligence, fuzzy logic, neural networks, learning control, and/or adaptive algorithms.
In another embodiment, the application of motion preheating is not automatic. In such an embodiment, initiating or terminating preheating and selecting preheating move sequences may be done manually. Motion preheating may also be performed based on manually configured rules or recipe parameters.
B. Processing Field Adjustment
Generally, link processing systems provide a relatively high throughput when using a single processing field (SPF) or a small number of large processing fields. However, using large processing fields tends to reduce accuracy due to increased time ("target age") between alignment target scans. Target age coupled with thermal drift may degrade accuracy.
After a link processing system has been idle for a period of time, for example, the link processing system may be in a transient thermal state that decreases accuracy. To improve accuracy, the link processing system may use a smaller processing field to process the first three or four wafers. However, the smaller processing field may reduce the system's throughput. Thus, once the link processing system reaches the predetermined thermal equilibrium threshold, it increases the size of the processing field to speed up the processing of subsequent wafers.
IV. Example Adaptations Based on Location Dependent Processing Parameters
Link processing systems typically have different performance characteristics when motion stages are in different locations with respect to a wafer. Processing parameters that may vary as a function of location include, for example, bandwidth, response time, dynamics, resonant characteristics, and response characteristics. These properties may impact system throughput and accuracy. Thus, using a single set of processing parameters when a motion stage is in different positions may reduce overall system performance.
In one embodiment, a link processing system automatically adapts to location dependent processing parameters by statistically analyzing processing metrics (e.g., stage tracking errors, throughput, settle times, bandwidth, resonant frequencies, post-processing yield, and link blow quality). The link processing system then modifies system parameters to optimize or improve processing. Such an optimization may involve maximizing throughput while maintaining accuracy. In addition, or in another embodiment, the optimization may involve minimizing a cost function that penalizes processing time and degraded accuracy.
Example parameters that may be optimized or improved as a function of location include stage tuning parameters, motion profiling parameters (e.g., jerk time, acceleration, settle time, peak velocity, and gap profiling parameters), process parameters, alignment parameters, focus field parameters (e.g., shape, size, target locations, number of targets to use, target timeout, target models, and position geometry correction (PGC) models), laser parameters (e.g., pulse energy, spot size, and pulse shape), and any other processing parameter. PGC models map link coordinates inside a focus or alignment field. In one embodiment, the model has a format: Xsys=C0+C1*Xcad+C2*Ycad+C3*Xcad*Ycad, where C0 . . . C3 are parameters determined from curve fits during alignment field scanning, Xcad and Ycad are respective computer aided design (CAD) coordinates of the links to be processed, and Xsys is the X position in the system coordinates (interferometer) used to process a link. Similar mapping may be performed for Y and Z dimensions. Of course, an artisan will recognize from the disclosure herein that higher-order models, lower-order models, or different models may be used to map link coordinates within focus or alignment fields.
System command parameters may also be optimized or improved as a function of location. Such system command parameters may include, for example, ordering of system operations, both temporally and spatially. For example, different chuck regions may have different target timeouts and/or may require different intermixing of link runs and target scans.
In an example embodiment, the link processing system measures motion stage errors (e.g., cross-axis, on-axis, FSM, and/or TLC) as a function of time after acceleration. The required or desired settle time to meet predetermined system accuracy may vary as a function of the motion stage's X and Y locations. Thus, after measuring the motion stage errors, the link processing system determines a set of minimum settle times that ensures accuracy for various motion stage locations. The link processing system then uses the set of location-dependent settle times to profile and sequence link runs and gap profiling events. Because the link processing system does not use a single settle time at every location, throughput is enhanced while maintaining accuracy.
V. Example Adaptations Based on System State
As discussed above, thermal drift may be relatively large when the link processing system is in a transient condition such as when switching from an idle state to a wafer processing state. Thermal drift may also be large, for example, when the link processing system is switching between processing a first wafer product type and a second wafer product type. Conventional link processing systems generally implement processing field shapes and sizes that ensure accuracy during transient states. However, these fields are typically smaller than is required once thermal stability has been achieved. Thus, processing speeds and overall throughput are decreased.
In one embodiment, a link processing system automatically determines processing fields and processing operations by taking into account system parameters, system operation, system operational history, system internal environment, and system external environment. The link processing system then optimizes or improves product processing to maximize or increase throughput while maintaining acceptable accuracy. In one such embodiment, the link processing system automatically selects appropriate processing parameters during warm up and steady-state processing that ensure accuracy and maximum throughput.
Example factors that the link processing system may consider in determining how to process wafers include, but are not limited to: the number of X and Y axis link runs; the number of links included in the link runs; the statistical distribution of gaps between links over which gap profiling is performed; the predicted or measured time for the X axis link runs, Y axis link runs, and/or total processing time; previously determined system target timeout times or knowledge of the time-scale over which the system loses accuracy; predicted or measured heat generation in actuators, lasers, optical components such as an acousto-optic deflector (AOD), and other system components; and measured temperature distribution in the actuators, chuck, air-bearing stage, lasers, AODs and/or other optical components, optical mounts, system air temperature, or other system components.
The link processing system may also take into account the drift of accuracy targets. For example, the link processing system may predict the drift of accuracy targets, measure the drift of accuracy targets in real-time, and/or ascertain the drift of accuracy targets from a history of similar wafers. In addition, or in another embodiment, the link processing system may determine whether or not the system has achieved thermal steady state. For example, the link processing system may make measurements related to its thermal state and/or determine whether it has reached a thermal steady state from a history of recently processed wafers.
Other factors that the link processing system may consider in determining how to process wafers include, for example: user-selected error tolerances (e.g., on-axis, cross-axis, and/or focus height error); cost functions for analyzing a tradeoff between error and throughput; historical data gathered from post-processing yield analysis; and conditions of the operating environment such as external temperature, temperature history, and/or measured/typical vibrations of the fabrication floor.
Properties of specific link processing systems (which may be static or may vary) may be measured or user-specified, and may be used to optimize processing parameters. Examples of such properties may include measured stage cross-axis error as a function of time or laser pulse width. Another example property includes energy as a function of PRF.
After determining or measuring the system state properties and information discussed above, the link processing system may determine wafer processing parameters such as: the size, shape, and number of processing fields, alignment fields, and focus fields; the location and number of targets that require scanning in the alignment and focus fields; the target timeout time; the time at which to scan or rescan alignment targets, and/or the time/position at which to scan new alignment targets; the model and algorithms used to map link coordinates into coordinates for processing; the order in which link runs are to be processed, which may include intermixing of X and Y link runs; the optimal or desired grouping or breaking of link runs within process fields to maximize or increase throughput; the combination of link runs with the same or different cross-axis link coordinates; the proper or desired setting of the hardware configuration parameters 510 and the motion profiling parameters 512 discussed above with respect to
VI. Example Adaptations Based on Wafer Properties
In some embodiments, a link processing system automatically adapts system and/or processing parameters based on known wafer properties. Such wafer properties may include fabrication options, fabrication errors, variances within fabrication tolerances, and/or other deviations between wafers or wafer lots. Wafer properties that may trigger automatic adaptation may include, for example, passivation thickness, layer thickness, and materials used. Other properties include link or alignment target stacks, structures, and layouts. The wafer properties may vary from wafer to wafer or in different locations or regions of an individual wafer.
Prior knowledge of wafer properties may be obtained from measurements made prior to link processing or from fabrication data or log files. Knowledge of wafer properties may also be gained by system measurement of the properties.
Based on the wafer properties, the link processing system adapts system and/or processing parameters to improve yield, accuracy, throughput, and/or other desirable processing properties. For example, the link processing system may automatically adjust parameters that impact the interaction of light with the wafer, the links, and/or the alignment targets. Interactions between light and links and/or alignment targets include parameters such as laser energy, pulse shape, pulse width, spot size, and/or other optical properties. The link processing system may also adjust additional BTW scan properties such as the scan model for correlation/peak finding or the algorithms used to determine the scan locations. In certain embodiments, wafer dependent properties may influence the use of certain sensors, such as cameras for vision target alignment.
An artisan will recognize that the systems and methods described herein may be applicable to link processing, trimming, drilling, routing, via drilling, scribing, marking, singulating, dicing, component trimming/tuning, and other material alternation processes, either performed with lasers, drills, other cutting tools, and/or directed energy techniques such as using a focused ion beam (FIB). Further, the systems and methods described herein may be useful for other devices besides processing tools. For example, the systems and methods described herein may be useful for metrology tools such as electron microscopes.
It will be obvious to those having skill in the art that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. The scope of the present invention should, therefore, be determined only by the following claims.
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|Material Type:
|Document, Internet resource
|Document Type:
|Internet Resource, Computer File
|All Authors / Contributors:
Carl Shapiro
|OCLC Number:
|Doi: 10.1787/037574528284.
|1 online resource (35 p.)
|Series Title:
|OECD science, technology and industry working papers, 2002/11.
|Carl Shapiro.
This paper seeks to improve understanding of the links between innovation and competition policy. It is intended to help OECD Member countries identify ways in which they can design and implement policies that best promote innovation while protecting against anti-competitive behaviour. Special attention is given to the need for firms to co-operate during the innovation process, e.g. by forming joint ventures and by engaging in co-operative standard setting activities, and the special challenges such co-operation poses for competition policy. The paper specifically addresses competition challenges that arise from inter-firm co-operation that aims to commercialise inventions, diffuse innovation more broadly throughout the economy, or extend and elaborate on existing technology. Although the economic principles articulated here apply across the entire economy, the paper focuses attention on the information and communications technology sector, where the opportunities for innovation ...
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Hot Euro twinks having raw and raunchy bareback sex!! We have found some of the hottest young studs from the UK and all around Europe just for you.
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Week 10 VIDEO: Sleep Well and Lose Weight
…weight loss. You know, that's why meditation really works because it lowers cortisol. DHEA, we call it the fountain of youth hormone, is antagonistic to cortisol. So, the higher the cortisol, the lower the DHEA. That's why some people take it as a supplement. So, here's three things I'd like you to…Read More


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Quotes: Sitcom Arch-Nemesis
Shes always a step ahead of me. Thats what makes her such a worthy opponent.
—Lucille, Arrested Development
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Ellenore, be nice to Aly. He's my nemesis.
How pleasant it must be. To have an archfoe whose primary goal is getting to bargains before you, instead of one who wants to see you dead.
—Ted Knight, Starman#13
Whadda ya mean, "don't fight Canadian Guy to death on the front lawn"? Why else would I invite Canadian Guy over?
Newman is my sworn enemy.
—Jerry Seinfeld, Seinfeld


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YIELD: Serves 8 to 10
For Frosting:
Combine all ingredients in heavy large saucepan. Whisk over medium heat until chocolate melts and mixture is smooth and just begins to bubble, about 8 minutes. Refrigerate until just thick enough to spread, stirring occasionally, about 1 1/2 hours.
Meanwhile, prepare cake:
Preheat oven to 350°F. Line 15 1/2x10 1/2x1-inch baking sheet with foil, leaving overhang. Grease foil. Sift 1/2 cup sugar, cocoa powder, cake meal and potato starch into medium bowl.
Combine egg whites and salt in large bowl. Using handheld electric mixer, beat whites until soft peaks form. Gradually add 1/2 cup sugar; beat until stiff but not dry. Using same beaters, beat yolks and 1/2 cup sugar in another large bowl until thick, about 2 minutes. Gradually beat in oil, then nondairy creamer. Add dry ingredients; beat just until blended. Fold whites into yolk mixture in 3 additions.
Spread batter in prepared pan. Bake until tester inserted into center comes out dry and cake feels firm to touch, about 20 minutes. Cool cake in pan on rack. Freeze cake just until firm, about 30 minutes.
Using foil as aid, lift cake onto work surface. Cut cake crosswise into 3 rectangles, each about 5x10 inches. Slide large spatula under 1 cake rectangle; transfer to platter. Spread 2/3 cup frosting over. Top with second layer. Spread 2/3 cup frosting over. Top with third layer. Spread very thin layer of frosting over top and sides of cake to coat thinly and anchor crumbs. Refrigerate 15 minutes to set thin coat of frosting. Spread remaining frosting decoratively over cake. Refrigerate until cold, about 4 hours. (Can be made 3 days ahead. Cover loosely with foil; keep refrigerated.)
Cover top of cake with chocolate shavings and garnish with mint, if desired. Cut crosswise into slices and serve.


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The Big Read: Matt Harvey and the power of the pitching phenom
Apr 27, 2013, 11:27 AM EDT
In today's Big Read, Joe Posnanski takes a look at Matt Harvey's impressive start to his major league career and the idea of pitching phenoms in general. In doing so, Posnanski turns back the clock to examine some other pitchers who dominated early on in their careers, including Steve Rogers, Mark Fidrych, Fernando Valenzuela, Dwight Gooden and Hideo Nomo. It's a fun ride.
So, when a young pitcher shows up like Matt Harvey with insane fastballs and exploding sliders … there's something magical about it. Something unlimited. A quarterback, even a perfect one, needs receivers, an offensive line, a running game, a shrewd offensive coordinator. A basketball player, no matter how good, cannot take on five defenders at a time. A pitcher, though, has the ball. He is only limited by the imagination.
And so every time a Hideo Nomo or Dwight Gooden or Matt Harvey shows up on the scene, the possibilities are endless. In many ways, I've marked my baseball life by the pitching phenoms who kept showing up.
Great stuff, as always. Speaking of pitching phenoms, Harvey is scheduled to face Marlins' rookie right-hander Jose Fernandez in his next start on Monday. That's one tasty matchup.
- cadillacjosh - Apr 27, 2013 at 11:55 AM
In totally unrelated news, on MLB the show, Hernandez is a 78, which is fair for his ago. But he never really gets any better. Jacob Turner on the other hand turns into like a 94, so if you can swing a trade for him, its totally worth it. But you usually have to take on Ricky Nolasco's contract.
Matt Harvey is awesome. He's been the deciding factor in a few fantasy match ups for me.
And that should be all for arbitrary news from me for Saturday. Thank you all for your time.
- jaredo10 - Apr 27, 2013 at 12:01 PM
Good for Mets Fans. They deserve his success
- forsch31 - Apr 27, 2013 at 12:56 PM
"The pitcher is the only athlete in sports that is credited with a win or a loss. You could argue — I have argued many times — that it's silly to credit a pitcher with a win or loss. We do it anyway and have for more than a hundred years. We don't do that for a quarterback or a point guard or a goaltender or a goalkeeper."
Joe, unfortunately, needs to check his facts. The NHL has always credited goaltenders with wins and losses. In fact, their leaders page includes a "wins" category for goaltenders.
- sophiethegreatdane - Apr 27, 2013 at 4:48 PM
And to add to that, QB's get "wins" hung on them all the time. It's not an official stat, but lets not act like it doesn't happen.
To me, it's silly to have a stat that measures what the entire team does, and credit a single individual in that context.
- Mark - Apr 27, 2013 at 1:18 PM
Thanks for pointing that out Harry. I imagine it was very important to bring up the Blue Jays record when discussing Matt Harvey's success in his limited exposure to the majors..
- dirtyharry1971 - Apr 28, 2013 at 3:18 AM
It was very important and actually the Jays are now 9-16 holding up the basement in the AL East!! As for the Mutts, who cares? They aint going anywhere and will never win another WS so get over yourself
- yousuxxors - Apr 27, 2013 at 3:35 PM
yea but a goalie still needs a defense in front of him to be successful. yea they can be the deciding factor. a pitcher can dominate with a pos team … look at Harvey.
- sophiethegreatdane - Apr 27, 2013 at 4:55 PM
Your argument is so thin, it hardly warrants a response, but oh we'll– I'll be your huckleberry.
You seem to be forgetting that a pitcher needs and entire defense behind him, unless he's planning to throw 27 consecutive strike outs. Not to mention an entire 8- or 9-man offense designed to, you know, put runs on the board.
Like it or not, the pitcher can't score runs from the mound. And last time I heard from Madden or McCarver, they were busy telling us you had to out score the other team to win the game.
- yousuxxors - Apr 28, 2013 at 7:19 PM
a pitchers defense behind him is 100 times less important than a goalies defense in front of him.
- bigleagues - Apr 29, 2013 at 10:04 AM
Rogers would go on to be a fine pitcher, winning 158 games and leading the league in ERA in 1982.
Steve Rogers won 158 Games in 1982?! How come no one ever talks about this?
Also, interesting he chose the pitchers he chose. Because what does everyone of them have in common?
At some point during the splash and rise sportswriters and fans alike had them earmarked for the Hall of Fame. And NONE of them ended up being serious candidates.
IMHO the word 'phenom' is somewhat misplaced here anyway. Surely Roger Clemens, Tim Lincecum, Bret Saberhagen, Kevin Appier and Dontrelle Willis were all "phenoms". And to a certain extent, so were guys like Greinke and Rijo. I guess none of them marked a point in Posnanski's life.
But what of the ever-elusive true phenom tag?! I think it's a term that needs a formal definition in the context of baseball, once and for all …
Here is a starting point:
"Any pitcher who arrives at the Major League level no later than his Age 22 season; and with a minimum of or no Minor League experience (to be quantified) preceding his promotion to the Majors; and who by the end of his first Major League season is considered among the very best pitchers in all of baseball."
- moogro - Apr 29, 2013 at 11:08 AM
I think a goalie and a pitcher are analogous. It really shows in the playoffs, where a lot of the drama comes from having balls of steel and single-handedly dominating.
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From Cherry Hill to a West Side high school a few miles away, scores of families and friends turned out Wednesday night to mourn teenagers killed in recent days, and to decry persistent violence in the city.
On the block where 14-year-old Najee Thomas was killed, residents attended an anti-violence rally.
Standing on the curb was the boy who lost his best friend, now too scared to go to the school bus stop alone. In the back of the crowd was the attorney who came because she was touched that Najee had aspired to be a lawyer like herself. Holding the bullhorn and challenging the crowd, a gray-bearded pastor called for peace and prayer.
And receiving nonstop hugs in the middle of the crowd was Pamela Thomas Ingram — Najee's grandmother — who described her grandson as a tree just starting to branch out before he was cut down too early.
"He was everything," she said. "He was a good child, and he was reaching out."
At Edmondson Westside-High School, vigil attendees held candles to remember Michael Mayfield, 17, a Junior Reserve Officers' Training Corps member who volunteered as a peer mediator and worked to change perceptions about teens causing trouble downtown.
His father, Michael Drake, spoke softly about his son's murder from behind a pair of dark sunglasses.
"I'm devastated right now," Drake said. "I don't know what to say. I don't have an answer. I keep going, 'Why? Why?'"
Three teens have been killed in the past 10 days.
The killings have galvanized city officials, who are pledging to give young people more attention and opportunities to help keep them off the streets. Today, Mayor Stephanie-Rawlings Blake and a group of local ministers plan to hold a moment of silence and prayer for the victims' families before Mayfield's viewing and memorial service. Kevin Harris, Rawlings-Blake's spokesman, said the mayor plans to attend the boy's wake afterward.
Rawlings-Blake also announced that she has scheduled a May 13 forum with teens on violence so she can learn how to improve city services and outreach.
While 10 fewer homicides have occurred in Baltimore this year, compared with the same time last year, the killings of the teens stand out. Raysharde Sinclair, 18, a Friendship Academy of Science and Technology student, was first, fatally stabbed April 14 in the lot of a gas station in the 5100 block of York Road. Mayfield, 17, a promising baseball player, was fatally shot April 16 in a minivan in the 2300 block of Lyndhurst Ave.
Thomas was found inside his Cherry Hill home at 1:15 a.m. on Tuesday. A day later, teddy bears were stuffed in the chain link fence of his front yard, serving as a makeshift memorial.
"It's a very sad situation to have someone that young lose his life," said Edward Reisinger, City Council vice-president, who attended the Safe Streets-sponsored rally for Thomas. "We can do our programs, create youth centers, but what this community did tonight with their praying and coming together … it was healing."
Police have strong leads in Thomas' murder, Baltimore Police Commissioner Anthony W. Batts said, and homicide detectives were working all three cases around the clock.
"It's upsetting when young lives are lost," Batts said. "I have a sense of anger with the same energy as if one of my officers were injured."
Thus far, only one suspect has been arrested. Jimy James Jackson, 24, has been charged with murder in Sinclair's death. Police say Jackson held Sinclair during a fight, allowing another attacker to fatally stab him. But Jackson's lawyer, Warren A. Brown, has said his client may have held Sinclair to defend himself during a fist fight, not to set him up to be stabbed.
The man police believe did the stabbing has not been found; police have not named a suspect.
Thomas lived with his mother in a two-story rowhome in the 600 block of Roundview Road, where the rally was held.
Najee's father, Ronnie Thomas, is currently serving a 19-year sentence at a high-security U.S. penitentiary in Sumterville, Fla. Better known as "Skinny Suge," Thomas was producer of the notorious "Stop Snitching" videos that gave Baltimore a national identity as a city that shunned police cooperation and prided itself in intimidating witnesses.


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"I neither want nor intend to become famous now, but in one hundred years I wish to be read." Thus presciently asserted Germany's most beloved and celebrated nineteenth-century woman writer in a personal letter dating from 1843. During her lifetime Annette von Droste-Hülshoff achieved modest recognition, first as a relatively obscure regional author, then as a significant and original literary figure. Her true poetic genius was widely recognized only posthumously. The inclusion of her novella Die Judenbuche [The Jews' Beech Tree, 1842] in Heyse and Kurz's Deutscher Novellenschatz [Treasury of German Novellas, 1876] secured the Westphalian poetess's …
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Helfer, Martha. "Annette von Droste-Hülshoff". The Literary Encyclopedia. First published 12 July 2006
[http://www.litencyc.com/php/speople.php?rec=true&UID=5444, accessed 02 July 2015.]


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MMA News
Jon Jones Pulls Out Of UFC 170 Main Event Against Glover Teixeria
There is not much information at this point as to why Jon "Bones" Jones will not be defending his title against Glover Teixeira in the main event of UFC 170 as announced yesterday by Dana White. Today Dana White announced Jon Jones would not be fighting on Feb 22nd against Teixeira.
"I told you yesterday that Jones will fight on Feb. 22," White told reporters following the UFC 167 press conference. "He won't fight in Feb. 22. He just pulled out of the fight. He's not fighting Feb. 22."
Dana White also said "He's not injured," talking about Jones, which makes more questions than answers at this point. The UFC President also stated that he believes Jones-Teixeira could go off in March. So it looks like Teixeira will still be next in line for Jon Jones UFC light-heavyweight title but we do not know when. White would not disclose why Jones would not be defending his title at UFC 170.
Dana White also indicated that UFC 170 will still go on as planned at Mandalay Bay, with a new main event to be named at a later date. So for now this is all the info we have and as soon as more comes out we will be sure to update everyone on the situation.
123 Responses to "Jon Jones Pulls Out Of UFC 170 Main Event Against Glover Teixeria"
Despite being a Jones fan, this is weird and not very champion like. I will look for the full developments before passing any full judgement, but this is just weird.
I don't know it seems that there is more to this story and when it all unfolds that is the time to choose if he had a good reason or not. Not now with very limited information.
Yeah, I imagine Dana would be more pissed if it was just Jon being a diva or something… Maybe it's like the Lil Nog fight where he didn't even have the fight signed yet? Who knows…
That sucks Glover has been waiting and he already had fighters cutting in line before. Maybe Jones landed a role in a movie or something? Or he got his ass beat by Incognito lol
hmm the jackson cult camp strikes again
That fight with Gus rocked his confidence. The boy has pussy in his blood now. He is a cocky asshole. Great fighter for sure but what a cocky asshole.
Relax it's nothing like that, he just likes to plan ahead for his next DUI.
He wants to retire at 30 & He's nearly 27 so he will probably only have another 6-7 fights. I hope he fights Cain Velasquez.
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This report presents data on the demographic and employment characteristics of the nation's doctoral sciences and engineers. The data were developed as part of the Doctorate Data Project.[1] The goal of the 1999 Survey of Doctorate Recipients (SDR) is to provide policymakers and researchers with high-quality data and analyses for making informed decisions related to the educational achievement and career patterns of the nation's doctoral sciences and engineers. Current information on the supply and utilization of doctoral personnel in science and engineering reflects the results of SDR, the 14th in a biennial series. The population of the 1999 survey includes persons under the age of 76 who hold doctorates in science or engineering from U.S. institutions.
The SDR is a longitudinal demographic survey of science and engineering doctorate holders conducted biennially for the National Science Foundation (NSF) and for other Federal agencies (current and past sponsors included NIH and DOE) since 1973. The Technical Notes in Section II contain information on survey methodology, coverage, concepts, definitions, and sampling errors. Various changes made in the 1999 data tables are also noted in the Technical Notes.
The detailed statistical tables in Section III provide information on the number and median salaries of scientists and engineers by field of degree and occupation; for demographic characteristics such as gender, race/ethnicity, and citizenship; and employment-related characteristics such as occupation, sector of employment, median annual salary, and various labor force rates.
For further information on the survey or the availability of data on Science and Engineering doctorates, please go to http://www.nsf.gov/statistics/doctoratework/ or contact:
Kelly H. Kang
Division of Science Resources Statistics
National Science Foundation, Room 965
4201 Wilson Boulevard
Arlington, VA. 22230
Telephone: (703) 292-7796
E-mail: firstname.lastname@example.com
[1] The Doctorate Data Project consists of the Survey of Doctorate Recipients, a biennial survey conducted since 1973, and the Survey of Earned Doctorates, an annual census of research doctorates awarded since 1920, which forms the Doctorate Records File.


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Free Shuttle Pick Up/return from Bus Station.*
Excellent Beach Water & Drinking Water Quality Test Results !!
'Rare midget/mosquito insect occurrence' !
Clifden's unique ecological natura campsite is Ireland's first Climate Neutral ecoCampsite, nestled amongst the sand dunes on the western fringe of Connemara, Co. Galway. Our Park offers visitors a sustainable, cluster free, natura camping
experience on eight hectares of coastal Machair habitat bio-diversity, with unparalleled panoramic Atlantic seascape views. Our coastal Park, with its sheltered, safe, 'secluded private beach' is in easy walking distance to the stunning tidal Island of Omey.
We are ideally situated on the shores of the 'Wild Atlantic Way'. Just ten minutes from Clifden town & two minutes from the small scenic village of Claddaghduff between the beautiful Atlantic ocean & the majestic Twelve Bens mountain range which forms part of the 'Connemara National Park'. Only a short distance away, it features fantastic designated trekking routes. Here you can also gain a unique understanding of Irish bogs & the ecosystems they support.
Glamping & wild camping style plots are peaceful & privately spaced apart between 'marram grass' covered sand dunes, making your camping experience unique & more enjoyable. Here you can discover the 'peace of nature amongst the dunes',
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One kilometer of coastline with excellent bathing water quality provides the perfect water trail discovery for all kinds of sea-borne activities, including safe swimming, sea angling, crabbing, scuba diving, kite surfing, boating & the famous 'drift dive' or 'drift snorkle' along the estuary of Streamstown Bay. Ecological & geological listed sites are among the best examples seen anywhere in Europe.There are also beautiful coastal beach walks within the park, with longer walks to & around the beautiful tidal island of Omey.
We guarantee that your plot never becomes wet under foot, will remain dry & clean even in extreme wet weather conditions. It is also rare for mosquito/midget insects to appear on site due to its coastal location.
Enjoy a virtual tour of the park & its surrounding coastal region. Here you can explore through 360 degrees, panoramic, & street view level imagery.(Google Chrome browser recommended).
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Add interest to outdoor spaces with varying levels.
"Different zones, ground surfaces and raised patios offer different spots for kids to play in this San Francisco backyard," says Montreal blogger Kim Vallée. "Plus, it's sophisticated and stylish enough for entertaining."
Get more ideas for kid-friendly backyard design in Kim Vallée's blog post.
See more of blogger Kim Vallée's favourite spaces in our photo gallery.
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By Kaylee Ray and Kenny Short, WSU News interns
PULLMAN, Wash. – An upcoming book co-authored by Washington State University's Mike Leach and Buddy Levy about Apache warrior Geronimo will focus on leadership.
Levy, a clinical associate professor who teaches English at WSU, said he originally pitched the idea to his agent who also represents Leach, WSU head football coach. The agent suggested talking to Leach because he knew Leach is fascinated by Geronimo.
"It started when my mom would read us books when we were kids, and for some reason I got into Geronimo," Leach said. "We'd go to the library and grab these historic books about him, and she would read them every night."
The book, still in the works, will talk about general leadership and problem solving skills that spill over into all aspects of management and people, Levy said. His strong point is the history, whereas Leach has a profound understanding of leadership, he said.
Leach has a strong interest in how the Apache warriors trained, Levy said. He has made few references to football.
"We're telling the story together," Levy said. "Leach weighs in throughout the entire process, providing commentary on leadership, community and family."
Leach said he is excited about what they will learn throughout the process. Levy is a great researcher, he said: "It's important to me to have Buddy and his experience. I'll learn a lot from him."
The goal is to reach a broad audience and show readers what can be learned from Geronimo and how he became such an icon, Levy said.
The most challenging part of writing the book will be "weaving our two voices into one," said Levy, who added that all of his previous books have been done solo. For Leach, deciding what to keep in the story and what to take out during proofreading will be the hardest part.
Levy said Leach is a fascinating person and he is excited to work with him.
"It's a tremendous story and I think we'll make a great team," Levy said.


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|12th March 2007, 04:04 AM
diyAudio Member
Join Date: Jun 2005
Location: Sacramento, CA
Test Amp - Construction Method
Ive been working on this test amp for a short time and thought Id post the project. Here are a couple reasons for posting:
1) Id like feedback from anyone who has used this assembly method (I first saw this construction method on www.ampslab.com) and may have advice or suggestions to make this perform.
2) If anyone hasnt seen this before, maybe it will spur someones creativity or will serve as inspiration for someone who hasnt built a project to start something. Feel free to let me know if this is the case too.
Im building this system for a couple reasons. First is to test the large copper wire/power point-to-point/connected by terminal strips/power transistor construction method. I like the way it looks and it seems to be reasonable for prototypes and home-built equipment. It certainly wouldnt fly for anything professional or commercial. So here is my first attempt using this technique and from the ease of implementation and flexibility so far, if it performs well, Ill be using it again.
The next items Im testing are the PCBs. They are basically Doug Selfs Blameless design. I used ExpressPCBs standard size boards (2.5 x 3.8, double-sided, through-hole plated) and put two complete amp driver circuits on each PCB. So this test system will allow me to validate the PCB design and get them dialed-in before I move on to my monoblock project (wait til I post them some day theyll be beasts!).
The power transistors are TIP35C/36C (100V, 25A, 125W, NPN/PNP compliments) set up as darlingtons with TIP31C/32C. The slab of heatsink was purchased at the local HSC surplus store for $11.
My next step is to finish the transistors wiring, add bias transistors with wiring to the PCBs, finish input and output wiring, and of course add the power supply. Ill provide more details and specs once this is done.
"Believers cling to the myth despite the evidence, reinterpret the myth to suit the evidence, or lie about the evidence to support the myth." "To err is human; to blame errors on external factors is even more so."
|12th March 2007, 12:40 PM
diyAudio Member
Join Date: Jul 2004
Location: Scottish Borders
you did really well to fit a blameless into 2.8x1.9inch and leave room for screws and non-plated land.
The TIPs are a bit slow compared to the transistors Self used.
Stick with 1943/5200 or better.
Is that 4pair in each channel? That pushes Self's low impedance version into mediocrity.
Any chance of posting a detailed close up of both sides of your PCB?
If you go to no miller cap (JLH) compensation then leave pads for his other four compensation locations he has incorporated into his 80W mosfet design.
regards Andrew T.
|12th March 2007, 07:50 PM
diyAudio Member
Join Date: Jun 2005
Location: Sacramento, CA
Ill take some closer pictures tonight and post them. It wasnt real tough to compress the design enough to fit 2.5 x 1.9. The ExpressPCB CAD program is very easy to use and the circuit isnt too complex. The PCB contains everything but the output stage and darlington pre-drivers and even has extra supply filtering.
I used the TIP35C/36C devices because I had a handful of each that I hadnt used in ages plus I wanted to see how the Blameless circuit would perform with typical output devices. By typical, I mean nothing fancy, or ultra fast, or too linear.
As for using 16 devices, four-pair per channel, I wanted to test the capability of the copper wire construction and try to dump 20 amps into 1-ohm (400W). The devices should handle it and if everything goes well, the PCB design and construction method should prove to be robust enough for future projects.
"Believers cling to the myth despite the evidence, reinterpret the myth to suit the evidence, or lie about the evidence to support the myth." "To err is human; to blame errors on external factors is even more so."
|12th March 2007, 08:38 PM
diyAudio Member
Join Date: Jul 2004
Location: Scottish Borders
regards Andrew T.
|13th March 2007, 12:28 AM
diyAudio Member
Join Date: Jun 2005
Location: Sacramento, CA
Attached is a close-up picture of the PCA I designed. The open pads to the right (of the PCB showing components) are for the bias transistor and resistors. There are also a couple extra pads in case I have to add additional feedback caps for stability, but hopefully I wont need them. I made both the top and bottom full ground planes with a full, common grounds because the entire PCA will be a single low-current ground point. Maybe a mistake; well see.
The TO-92 devices are MPS8099 and MPS8599 and the two Class A transistors are MPSU07 and MPSU57. Again, not the best devices but theyre adequate for testing.
Regarding the TIP devices delivering 20 amps, I dont see a problem. Each is rated 25A continuous and 40A peak, hFE is 25 minimum, and there are four paralleled. Anyway, this too will be proven upon testing.
"Believers cling to the myth despite the evidence, reinterpret the myth to suit the evidence, or lie about the evidence to support the myth." "To err is human; to blame errors on external factors is even more so."
|13th March 2007, 08:08 AM
diyAudio Member
Join Date: Jul 2004
Location: Scottish Borders
What is the TIP gain@ 5A?
Now look at the base current that the driver has to supply.
Ib=Ic/hFE =20/25 = 0.8A
Next look at driver dissipation into a reactive load.
Assume that the Driver Vce=+Vrail and driver Ic=0.8A the Pdriver=30V*0.8=24W. What does the datasheet say?
Could the Vrail be higher than 30V? if the load is taking 20A then the rail voltage could be much higher.
regards Andrew T.
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New Columbia Car DealerChange City
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Arizona Cardinals
Arizona Cardinals' 2014 schedule released
The 2014 NFL schedule was released Wednesday, more than four months before the first game of the year, and the Arizona Cardinals have their season mapped out against 13 different teams heading into next year.
The Cardinals' schedule includes intraconference matchups with NFC East teams and interconference matchups with teams from the AFC West.
To open the season, the Cards will host the San Diego Chargers at University of Phoenix Stadium in Glendale as part of the Week 1 Monday Night Football doubleheader.
The Cardinals will host the defending Super Bowl champion Seattle Seahawks in Week 16 and will play them in Seattle, the site of their rousing upset win last season, in Week 12.
The Cardinals will travel to the brand new Levi's Stadium in Santa Clara, California to play the San Francisco 49ers in the regular season finale in Week 17.
The Super Bowl runner-up Denver Broncos will host the Cardinals in Week 5.
The Cardinals will make their first-ever visit to "Jerry's World," AT&T Stadium in Arlington, Tex. to take on the Dallas Cowboys in Week 9.
Quarterback Carson Palmer will visit his former team, the Oakland Raiders, for the first time as a Cardinal Oct. 19 in Week 7.
Of note:
� The Cardinals have three prime time games this season -- Week 1 vs. San Diego (ESPN), Week 15 at St. Louis on a Thursday night (NFL Network) and Week 16 against Seattle in Glendale (NBC). That Sunday night game is subject to NFL flex scheduling.
� Arizona plays back-to-back road games only once during the season -- Week 12 in Seattle, followed by a trip to Atlanta in Week 13 Nov. 30.
� The Week 4 bye is the earliest since 2001, when the Cardinals had a Week 1 bye.
� The Cardinals play only three games in the Eastern time zone -- and one of those (NY Giants, Week 2) will be an early start time.
|Monday, Sept. 8
|San Diego Chargers
|University of Phoenix Stadium
|7:20 p.m.
|Sunday, Sept. 14
|at New York Giants
|MetLife Stadium
|10:00 a.m.
|Sunday, Sept. 21
|San Francisco 49ers
|University of Phoenix Stadium
|1:05 p.m.
|Bye Week
|Sunday, Oct. 5
|at Denver Broncos
|Sports Authority Field at Mile High
|1:05 p.m.
|Sunday, Oct. 12
|Washington Redskins
|University of Phoenix Stadium
|1:25 p.m.
|Sunday, Oct. 19
|at Oakland Raiders
|O.co Coliseum
|1:05 p.m.
|Sunday, Oct. 26
|Philadelphia Eagles
|University of Phoenix Stadium
|1:05 p.m.
|Sunday, Nov. 2
|at Dallas Cowboys
|AT&T Stadium
|11:00 a.m.
|Sunday, Nov. 9
|St. Louis Rams
|University of Phoenix Stadium
|2:25 p.m.
|Sunday, Nov. 16
|Detroit Lions
|University of Phoenix Stadium
|2:25 p.m.
|Sunday, Nov. 23
|at Seattle Seahawks
|CenturyLink Field
|2:05 p.m.
|Sunday, Nov. 30
|at Atlanta Falcons
|Georgia Dome
|2:05 p.m.
|Sunday, Dec. 7
|Kansas City Chiefs
|University of Phoenix Stadium
|2:05 p.m.
|Thursday, Dec. 11
|at St. Louis Rams
|Edward Jones Dome
|6:25 p.m.
|Sunday, Dec. 21
|Seattle Seahawks
|University of Phoenix Stadium
|6:30 p.m.
|Sunday, Dec. 28
|at San Francisco 49ers
|Levi's Stadium
|2:25 p.m.
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