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This summer, incoming kindergarten students in the St. Marys Area School District will be able to boost their skills and prepare for the school experience through the Kindergarten Readiness Program (KRP).
According to the Fox Township Supervisors, the township's planning commission will need to revise the township's zoning ordinance accordingly in regard to the state's adoption of the Marcellus Shale Drilling Act. This will need to be done in order for the township to receive impact fees associated with drilling.
The supervisors approved an amendment be added to the township's lease agreement with the Fox Twp. Senior Center to confirm that the township has budgeted for the payment of the electric and gas at the senior center building since 2005.
EMPORIUM – Emporium resident Casey Saline is no ordinary fan of classic music and movies - using her vivid imagination and creative skills, she transforms old cassette tapes and movie reels into unique art that has caught the interest of the Ripley's Believe It or Not! franchise.
It's no surprise that Kane native Jim Sirianni became a high school history teacher.
The late Robert "Chief" Carson, a Kane teacher, heavily influenced Sirianni. And he listened to his tutor and has had a 36-year career as a history teacher at Kane Area High School.
"I've always been interested in history," Sirianni said.
Sirianni not only teaches history. He has dug deep into the subject—especially on the local level.


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Formula fed 2 month olds..how many ounces each feeding?
I mix feed because I still do not produce enough milk at 7 weeks, but my daughter takes 3-4oz 7 to 8 times during a 24-hr period. At her 6-week check-up, her pedia said 24-30oz daily is great for her age and weight (10lbs). :)
Mommy to Lucia Beatriz - 10.20.12 :)
My LO is at 7oz every 4 hours she is 2 months old
Proud formula feeding mom!
Married since 10/06
DD: Madilyn Claire (6/28/06)
DS: Ethan Neal (10/18/12)
4.5 oz every 3hrs and 6oz before bedtime.
My 9 week old takes about 4-4.5 every 3-4 hours. At night he will sleep about 5-6 hours and then wake up every 3-4 hours after that. I am hoping that it will get longer and longer... It did with ODS, but right now he just isn't extending his inbetween times yet.
Rick (33) + Kate (30)= Eli (5) and Jack (2)

subset: commoncrawl


text:
Raising the Standards
~Informational Video about Us~
Proud To Be Me
I am a smart, special, and valuable person.
I respect myself, and I respect others.
My words and actions are kind and honest.
I only accept the best in all that I do.
I am proud to be me.
Teacher of the Year
Support Teacher of the year 2014-2015
"Our Gym"
Important Dates
April 20
May 21


text:
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Fruits Basket Cosplay
Fruits Basket is about the life of HS student Tohru Honda, who was orphaned when her mother, Kyoko Honda, died in a terrible car accident. After that, Tohru lived with her grandfather, but when his house needs remodeling, Tohru resorts to living in a tent in a forest and holds down a job to support herself. Despite suffering many hardships, Tohru remains optimistic.
This is a cuter, more esoteric anime/manga ^_^
You'll find all the Fruits Basket Cosplay you could ever want right here!
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I have a problem with border radius on IE8, till now I used pie.js but I don't recommend this js library because is buggy. If you have a small site with not many html pages, it is more than ok to use that library, but if you have a heavy application in which many different frameworks are used, then is impossible to use that. Same behavior for CurvyCorners or other mega libraries.
So if anyone can help me with a small jQuery or javascript plugin to do just border-radius on IE 8 I'll be grateful for life.


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Iron Bowl QBs at very different stages of careers
Gabe Gross, a baseball star who eventually went on to spend seven years in the major league, started the 1998 game after coach Terry Bowden had already left the team during a 3-8 season. The Tigers lost 31-17.
Ken Hobby started the 1981 game against the fourth-ranked Tide, and lost 28-17.
Wallace hasn't reached 200 yards passing in a game yet but has also thrown just two interceptions.
"He's done a really good job of managing the game for them," Alabama coach Nick Saban said. "That's a good thing to me. Don't take that the wrong way. He's done a good job of throwing the football. He is doing all the quarterback runs that they do.
"And he's athletic enough to do it and makes good decisions about it. "
Wallace now faces a defense that yields the nation's fewest points and is second in yards allowed.
"I'm seeing everything you can imagine that a defense can run," Wallace, who was coached in high school by three-time Alabama All-American linebacker Woodrow Lowe, said. "They have an NFL-type defense. They bring everything. They do a lot of things. It's going to be kind of like Georgia, maybe a little more. Other than that, it's just one of those things where you've just got to take it a play at a time."
Wallace gets more designed runs of the two quarterbacks, but McCarron has shown an ability to escape the rush. He even scrambled for 24 yards against Western Carolina in his longest run of the season.
Saban made it clear before the play was even over that's not his role — especially in blowout wins.
"He told me he was screaming for me to get out of bounds the whole time," McCarron said. "And I kept going. I came off after we scored on that long drive, came over and he met me. I knew what he was about to say, so I said, 'I just wanted to show you who was the real athlete out of us two.' He started laughing and just walked away, couldn't do anything but smile."


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YIELD: Serves 4
Heat oil in heavy large skillet over medium-high heat. Season salmon with salt and pepper. Add to skillet; sauté until just cooked through, about 3 minutes. Using slotted spoon, transfer salmon to plate. Add garlic to same skillet; sauté 30 seconds. Add mushrooms; sauté 2 minutes. Add green onions, tomato, wine and capers; cook until mushrooms are tender, about 5 minutes. Add linguine, dill, lemon juice and salmon and toss. Season with salt and pepper.


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Original recipe yields 9 servings
Amount per serving ({{servings}} total)
Based on a 2,000 calorie diet
Ready In
It was gooey, goopy, goodness at it's finest. Normally I am not wowed by desserts with no chocolate but this was fantastic. The top cake like layer glistened and carmalized into a heavenly crun...
Easy to make, pretty good flavor, but if I made again (though doubt I will due to the unhealthy ingredients)I would cut down the amount of sugar. This was WAY too sweet for my tastebuds! My hu...
With a crust that melts in your mouth, and apples hot enough to burn your mouth (totally my fault), I though this was a wonderful recipe. It was esy to prepair and smelled divine. I believe I wi...


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Get Email Updates
Contact Us
Building Blocks
From "Acceptance" to "XSLT," use this alphabetical listing to get
familiar with commonly used acronyms and terms related to ISE. You can also learn more through our responses
to Frequently Asked Questions.
Information Assurance
International Association of Chiefs of Police
Intelligence Community
Intelligence Community Directive
Intelligence Community Policy Guidance
Intelligence Community Standard
Intelligence Community Standards Registry
Consists of a collection of Intelligence Community (IC) Standards Registry (ICSR) web-based applications supporting the continuing evolution of the Enterprise Standards Baseline (ESB) and the automation of its governance process. It supports all aspects of the ESB from standards development to daily usage and compliance guidance using a web-based front-end. It provides general information for the IC Enterprise Standards Committee (ESC), Standards Technical Working Groups (TWGs), and other ICSR Communities of Interest (COIs), as well as access to all versions of the archived ICSR documents.
Identity and Access Management
Harmonized standards that are identical in both substance and presentation. See Harmonized Standards.
1) The process, generally employing unique machine-readable names, that enables recognition of users or resources as identical to those previously described to the computer system. 2) The assignment of a name by which an entity can be referenced. The entity may be high level (such as a user) or low level (such as a process or communication channel.
The set of attribute values (i.e., characteristics) by which an entity is recognizable and that, within the scope of an identity manager's responsibility, is sufficient to distinguish that entity from any other entity.
An overarching term used to refer to the processes of authentication, authorization, assignment of attributes and privileges, access management, credential issuance, and the identification of a digital identity and the binding of that digital identity to an individual.
A set of otherwise independent identity providers and relying parties that agree to adhere to common rules and requirements for identity management and the use and protection of identity information.
Access control based on the identity of the user (typically relayed as a characteristic of the process acting on behalf of that user) where access authorizations to specific objects are assigned based on user identity.
Intrusion Detection System
Information Exchange Package Document
Integrated Justice Information Systems
A national nonprofit organization that brings together industry and government in an effort to improve national security and promote effective information sharing across all levels of the justice, public safety, and homeland security communities
Information Management
Provides specific information on how to implement a standard.
A document that explains the proper use of a standard for a specific business purpose.
Accidental exposure of information to a person not authorized access.
An assessed occurrence that actually or potentially jeopardizes the confidentiality, integrity, or availability of an information system; or the information the system processes, stores, or transmits; or that constitutes a violation or imminent threat of violation of security policies, security procedures, or acceptable use policies.
Events that, at the time of occurrence, cannot be determined to be an actual violation of law, but which are of such significance as to warrant preliminary inquiry and subsequent reporting. Examples include drug use and distribution, alcohol abuse, the discovery or possession of contraband articles in security areas, and unauthorized attempts to access classified data.
InterNational Committee for Information Technology Standards
Any communication or representation of knowledge such as facts, data, or opinions in any medium or form, including textual, numerical, graphic, cartographic, narrative, or audiovisual.
Measures that protect and defend information and information systems by ensuring their availability, integrity, authentication, confidentiality, and non-repudiation. These measures include providing for restoration of information systems by incorporating protection, detection, and reaction capabilities.
Structured information describing any or all information assurance aspects of a real object (i.e., resource) (e.g., a book, a mountain, etc.) or virtual object (e.g., a digital photograph, a service, etc.). See Metadata.
A specification for a data exchange and defines a particular data exchange. It is a set of artifacts consisting of normative exchange specifications, examples, metadata, and documentation encapsulated by a catalog that describes each artifact.
An application or protocol weakness where controlled data is inappropriately revealed to an unauthorized user or service.
The discipline that analyzes information as an organizational resource. It covers the definitions, uses, value and distribution of all data and information within an organization whether processed by computer or not. It evaluates the kinds of data/information an organization requires in order to function and progress effectively.
A condition or situation requiring knowledge or intelligence derived from received, stored, or processed facts and data.
The protection of information and information systems from unauthorized access, use, disclosure, disruption, modification, or destruction in order to provide confidentiality, integrity, and availability.
A standard that provides classification and dissemination control metadata requirements for a virtual object (e.g., an electronic document).
Office responsible to the President for policy and oversight of the Government-wide security classification system and the National Industrial Security Program
Aggregate of directives, regulations, rules, and practices that prescribes how an organization manages, protects, and distributes information.
Formal document that provides an overview of the security requirements for an organization-wide information security program and describes the program management controls and common controls in place or planned for meeting those requirements.
Potential that a threat will exploit a vulnerability of an asset or group of assets and thereby cause harm to the organization.
A trusted environment in which capabilities may be developed and exploited to discover, fuse, share and collaborate on information from any mission into integrated and synthesized information
The identification and documentation of information needs, infrastructure support, IT and NSS interface requirements and dependencies focusing on net-centric, interoperability, supportability and sufficiency concerns (DODI 4630.8).
A discrete set of information resources organized for the collection, processing, maintenance, use, sharing, dissemination, or disposition of information.
Protection of information systems against (INFOSEC) unauthorized access to or modification of information, whether in storage, processing or transit, and against the denial of service to authorized users, including those measures necessary to detect, document, and counter such threats.
Any equipment or interconnected system or subsystem of equipment that is used in the automatic acquisition, storage, manipulation, management, movement, control, display, switching, interchange, transmission, or reception of data or information. The term information technology includes computers, ancillary equipment, software, firmware and similar procedures, services (including support services), and related resources.
Data, information, processes, organizational interactions, skills, and analytical expertise, as well as systems, networks, and information exchange capabilities.
Information Security
A set of interconnected structural elements that provide the framework supporting an entire structure.
Provision that conveys an action to be performed. See Provision.
The property whereby an entity has not been modified in an unauthorized manner.
Creations of the mind such as musical, literary, and artistic works; inventions; and symbols, names, images, and designs used in commerce, including copyrights, trademarks, patents, and related rights. Under intellectual property law, the holder of one of these abstract "properties" has certain exclusive rights to the creative work, commercial symbol, or invention by which it is covered.
A federation of executive branch agencies and organizations that work separately and together to conduct intelligence activities necessary for the conduct of foreign relations and the protection of the national security of the United States.
A companion document to the Authorized Classification and Control Marking Register (CAPCO Register) that provides guidance on the syntax and use of classification and control markings.
May be based on statute, regulation, Executive Order, or other policy directives and establish policy and provide definitive direction to the IC. ICDs may: (a) define activities, systems or missions; (b) delegate authorities; (c) establish roles and responsibilities; (d) assign decision rights; (e) establish governance structures; (f) include evaluation criteria; or (g) replace or modify previous policy, or provide other such guidance as the DNI deems appropriate.
Provide further guidance required for the implementation of ICDs. ICPGs are subsidiary to ICDs and may establish subordinate responsibilities, and define procedures, processes, or methodologies that enable ICDs to be implemented effectively.
Subordinate to ICDs and ICPGs, and are fully consistent with applicable ICDs and ICPGs. ICSs are policy instruments of the IC Policy System and provide specific procedures, sets of rules, conditions, guidelines, characteristics, or specifications for intelligence or intelligence-related products, processes, or activities in support of effective and uniform implementation of laws, Executive Orders, and IC policies.
Consists of citations of standards specified through a consensus process as the minimum set of standards for the acquisition of all IC systems. The objective is to obtain integrity, interoperability and supportability among IC systems. The ICSR is sometimes referred to as "the Registry" or "the Standards Registry." The ICSR contains the IC Enterprise Standards Baseline.
Intelligence Reform and Prevention of Terrorism Act
Inter-Agency Policy Committee
Interagency Threat Assessment and Coordination Group
Ability of one product, process or service to be used in place of another to fulfill the same requirements. NOTE: The functional aspect of interchangeability is called "functional interchangeability", and the dimensional aspect "dimensional interchangeability".
The linking together of interoperable systems.
Impeding or denying someone the use of system resources.
1) The functional and physical characteristics required to exist at a common boundary or connection between persons, between systems, or between persons and systems.
A standard, which defines the services available at an interface to a process.
The primary U.S. focus of standardization in the field of Information and Communications Technologies (ICT), encompassing storage, processing, transfer, display, management, organization, and retrieval of information. INCITS is the forum of choice for information technology developers, producers and users for the creation and maintenance of formal de jure IT standards. INCITS is accredited by, and operates under rules approved by, the American National Standards Institute (ANSI).
Standard that is adopted by an international standardizing/standards organization and made available to the public.
International standard where the international standards organization is ISO or IEC.
An internationally agreed-to, harmonized document, which describes one or more profiles.
An entity which provides points of access to the internet. This may be a university, corporation, or any other entity. The means of connecting to an ISP include dial-up through a modem, broadband access via cable or DSL, or corporate networks with internet connectivity.
The ability of systems, units or forces to provide data, information, materiel and services to and accept the same from other systems, units or forces and to use the data, information, materiel and services so exchanged to enable them to operate effectively together. IT and NSS interoperability includes both the technical exchange of information and the operational effectiveness of that exchanged information as required for mission accomplishment. Interoperability is more than just information exchange. It includes systems, processes, procedures, organizations, and missions over the lifecycle and must be balanced with IA.
Unauthorized act of bypassing the security mechanisms of a system.
The process of monitoring the events occurring in a computer system or network, detecting signs of security problems.
A technical security system designed to detect an attempted or actual unauthorized entry into a secure facility or information system and alert responders.
1) Intellectual Property 2) Internet Provider
A numeric address which identifies a particular resource on an IP network such as the internet. The format of an IP address is xxx.xxx.xxx.xxx, with each xxx representing a number between 1 and 254, the decimal representations of the underlying 8-bit "octets." For a resource to be accessible on the internet, it must have an IP address assigned to it, and no 2 devices can have the same publicly accessible IP address.
International Standard
Information Sharing and Access Inter-Agency Policy Committee
Information Sharing Environment
Information Security Marking
Information Security Oversight Office
1) Internet Service Provider 2) International Standardized Profile
Information Technology
The hardware, software, and telecommunications equipment that when combined provides the underlying foundation to support the organization's goal.
The net mission/business impact considering (1) the probability that a particular threat source will exploit, or trigger, a particular information system vulnerability and (2) the resulting impact if this should occur. IT-related risks arise from legal liability or mission/business loss due to, but not limited to: 1) Unauthorized (malicious, non-malicious, or accidental) disclosure, modification, or destruction of information. 2) Non-malicious errors and omissions. 3) IT disruptions due to natural or man-made disasters. 4) Failure to exercise due care and diligence in the implementation and operation of the IT.
Submit Content and Suggestions for the ISE Website


text: The music blaring from Highland Kitchen's Victorian jukebox perfectly echoes the eatery's neighborhood vibe. Which isn't surprising, given that the 100 CDs (rotated each season) are chosen by chef Mark Romano and his bartenders. Five bucks gets you 13 songs from artists like the Flamin' Groovies and Lee Moses—plus a killer night out.


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After almost 15 years in business...Tails are wagging and pets are bragging about our pet sitting service!!!
It's no secret that our pets miss us terribly when we have to leave them at home alone. I have worked tirelessly to create a reliable, loving and affordable alternative to kenneling your pets.
Our staff of pet lovers have been formally trained and periodically undergo background checks to ensure that your sitter can throughly be trusted to be responsible for your furry, feathered or farm animal family members, as well as the keys to your home; which obviously for most people has everything in the world they own in it! We take this responsibility VERY seriously. If it's important to you, it's important to us. We want you to feel comfortable when you leave your home and pet that they are in very capable and caring hands.
WELCOME to Abundant LOVE for Pets!
My sweet boy Arthur. He's my constant companion.
Pet Care 101
Pardon our construction. More to come soon.
Spring is coming! (Hopefully;)
It's a busy time of year for people in our business. We are very pleased to be able to provide loving care for your pets while you are away for the upcoming Spring break and Passover/Easter holidays. Please try to provide us with as much advance notice as possible that you will need a pet care provider during these busy weeks.


text:
Favorite Treat Today
View Single Post
January 12 2010, 03:21 PM
John Picard
Vice Admiral
Location: Waiting for Dorian Thompson to invite me to lunch
Re: Favorite Treat Today
Jadzia wrote:
John Picard wrote:
OK, what's your favorite treat you partake of today? I've recently discovered dried Ginger root rolled in raw cane sugar and it is literally like crack.
crystalized ginger. I bought some of that just before christmas. Good for unsettled stomachs, as well as being delicious.
The first time a person tries it, there's that BURN. A burn so intense that it makes one yearn for another piece, and then another, and then another. Seriously, I told my grocer this stuff is crack
Don't like my posts? Fill out a
Psssstttt - Dorian, my location.
John Picard
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Congress Uses Powers From A Phony Constitution To Get Their Way Mandeville, LA – Exclusive Transcript – "He cited Madison and Monroe and others that had said: Look, I can find nothing in the Constitution that would cause me to sign this bill so that you can buy alfalfa seeds for farmers in Texas, for example. Explain to the audience just a little of the history behind public works and roads and canals and how the framers of the Constitution….Continue
Interview with Dr. Kevin Gutzman - Judiciary System Mandeville, LA – Exclusive Transcript – "This idea that lower-level federal court judges have no duty other than to enforce whatever the Supreme Court says, of course, reflects a long-standing argument among judges in the United States about what the relationship of other judges to the Supreme Court justices is. The most famous case involving this question is the 1816 case of Martin v. Hunter's Lessee." Check out t….Continue
Mandeville, LA – Exclusive Transcript – We have Representative Andy Holt on the Dude Maker Hotline. Representative Holt, how are you? Let me ask you, in the action that you took, is it proper to say that you filed a lawsuit, or is it proper to say that you asked the governor, Bill Haslam, to file a lawsuit? Check out today's transcript for the rest…. Begin Mike Church Show Transcript Mike: We have Representative Andy Holt on the Dude Maker Hotline. Represent….Continue
Mandeville, LA – Exclusive Transcript – Kevin - "I don't want to be misunderstood. I don't favor polygamy and I don't favor plural cohabitation, let alone flaunting that by having a reality television series about one's cohabitation, as one of the people who were parties in this lawsuit was doing. On the other hand, again, you're right. This is exactly the reason why we shouldn't have the kind of untethered federal judicial intervention in state governm….Continue
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Mandeville, LA – Exclusive Transcript – "This almost sounds like there's a spy ring going on here, like this is a big covert operation. All you nullifiers out there, all you "tenthers," as you're derisively called, you devotees of the Tenth Amendment Center, 'we will obtain your secret meetings where you sacrifice the goats, buddy. We'll find you cutting the heads off those chickens and pouring the blood on the floor at your nullification seances' " Check out….Continue
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Mandeville, LA – Exclusive Transcript – "Using this, it would be easy to make the case that the Bureau of Land Manglement actually is an unconstitutional use of a congressional power to make rules and regulations over territories. The only thing they could do would be to carry out a specific rule or regulation that Congress itself had made. In other words, the BLM can't come in and write its own rules. The Department of the Interior can't write its own rules. ….Continue
Now, does that mean that a state, if it wanted to, that they couldn't exercise the power and create a state park? No. This is the problem here. A state obviously reserved that power.….Continue
Mandeville, LA – Exclusive Transcript – Here's another great little historical inconvenience, Frank. Pennsylvania was also part of a perpetual union according to the Articles of Confederation. You have been living in this union in violation of your own theory, according to the act ratified in November of 1781 called the Articles of Confederation. How does that taste in your pipe? Check out today's transcript for the rest…….Continue
Mandeville, LA – Exclusive Transcript – There's a new book out called Politics on a Human Scale: The American Tradition of Decentralism. It's published by Lexington Books. Dr. Jeff Taylor is the author. I read part of this essay to you last week and I've referred to it a couple other times last week. Dr. Taylor is on the Dude Maker Hotline, making his first visit here. Dr. Jeff Taylor, welcome to the program, sir. Check out today's transcript for the rest…….Continue
Mandeville, LA – Exclusive Transcript – The Bill of Rights was used and created to provide further safeguards for the states against the Feds, just in case the Feds got the bright idea that they wanted to try, as the vulgar phrase goes in 2013, take our guns away. The Second Amendment says: No, you can't; you're prohibited from doing it. That doesn't mean the State of Illinois couldn't do it. It just means that the Feds can't do it. Check out today's transcr….Continue
Mandeville, LA – Exclusive Transcript – To the Dude Maker Hotline, my friend and yours, Dr. Professor Kevin Gutzman, author of James Madison and the Making of America, author of Politically Incorrect Guide to the Constitution, and co-author of Who Killed the Constitution? on the Dude Maker Hotline on a Monday. Check out today's transcript for the rest…….Continue
Mandeville, LA - Noah Millman posts at the American Conservative Magazine in part: "If the secessionist cause is to be justified in the Declaration's terms, it must make one of two claims. Either there are no "political bands" of note to dissolve – the Union is a mere compact among sovereign entities, that any party may depart from at will. Or, if those bands are granted to exist, the election of Abraham Lincoln, whose party was committed to preventing the spread of sl….Continue
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AN INTERNATIONAL GROUP of maritime security experts is working to knit together the latest communications technology to identify small ships bearing nuclear weapons. The goal is to give first responders patrolling the world's harbors and coastlines instantaneous access to experts to quickly size up possible threats in port or on the high seas.
June 2012
June 2012
Today's approach to the issue of cybersecurity is totally wrong. For years, experts have been propounding similar solutions to the problem of securing the virtual realm. Yet, that realm is less safe today than it was when the first calls for improved security achieved urgent status. The changes that define cyberspace—and what cyberspace in turn has wrought on society—cry out for a new approach rather than add-on measures to the same strategies that continue to prove unsuccessful over the long term.


text:
This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address don't match, a new translation must be performed using the set of conversion tables associated with the currently requested address.
Claims available in
Description (OCR text may contain errors)
United States Patent Ahearn et al.
[4 1 Dec. 25, 1973 1 VIRTUAL MEMORY SYSTEM [75] Inventors: Thomas P. Ahearn, Poughkeepsie;
Robert S. Capowski, Verbank; Neal T. Christensen, Poughkeepsie; Patrick M. Gannon, Poughkeepsie; Arlin E. Lee, Poughkeepsie; John S. Liptay, Poughkeepsie, all of N.Y.
[73] Assignee: International Business Machines Corporation, Armonk, NY.
[22] Filed: Oct. 17, 1972 [21] Appl. No: 298,190
[52] U.S. Cl. 340/1725 [51] Int. Cl. G061 13/00, G1 1c 9/00 [58] Field of Search 340/1725 [56] References Cited UNITED STATES PATENTS 3,569,938 3/1971 Eden et a1 340/1725 3,611,316 10/1971 Woodrum 1 340/1725 3,670,310 6/1972 Bharwani et al. 340/1725 3,675,215 7/1972 Arnold 1 1 340/1725 3,685,020 8/1972 Meade 1 340/1725 3,693,165 9/1972 Reiley et al... 340/1725 3,699,533 10/1972 Hunter 340/1725 3,701,107 10/1972 Williams, 340/1725 3,701,984 10/1972 Burns 340/173 R CPU VIR ADDR Primary Examiner-Paul 1. Henon Assistant E.raminer-James D. Thomas Attorney-James E. Murray et al.
[57] ABSTRACT This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of trans lating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address dont match, a new translation must be performed using the set of conversion tables associated with the currently requested address.
4 Claims, 10 Drawing Figures 0 2 a 28 IHASH com 7 Farm LOGIC 45 PREFIX are l 1 0m mm Bit M 56 el 1m l l l l l r l l 1 i g gmjilvm ,l gg g gnvln im REALIREAL REAL REALREAL REAL REALREAL E ole-151 01045 E D Ma a-2o a-zo 3-20 a20 s20 8-208-20 ,la2o p20 RE i L 1 l l z R l l l *1; 0 1 1 G F l l l te/MU lcMPRl t 1H a c B -54 ee 1 Mr m: MATCH MATJZH BFR SM PATENTEUBEBZFW 3.781.808
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\8 RRRRL REA VIRTUAL ADDR AIR] sro sx PX BYTE PG TBL 10 Z 5 PTO+PX REAL (P VIR sm PROT REAL 8-20 m i illlillllllllllllllllll 1 R DIRECTORY REAL 1 REAL UAR ADWWZ DLAT BFR DIR VIR RL RL 4 ADDR {ADDR ADDR 58 I4 NOT IN DLAT 1R z 5s a DATA m MS 4 I 54 .3 2 r 52 24 b 8 DATA IN BFR BFR m L PATENTED UECZSIQU SHEET 2 0F 5 i I 5 mm z a M i 2 in w w o N 3 8 E El a: m E a; w n N a z w a E ii 2 3 ma E2 5 52am Em Z L 0 aw w R 1 g I Q 2:231:53 4w GE AC TIV 5T0 PATENTEDUEBZS 1315 FIG. 8
0 0 2 E C O SHEET 5 BF 5 DLAT D ARRAY DL AT 1 ARRAY O I D L A R A O I D L A R A 1 1 8 15 3 2D 21', d 1:
1 5 1 E 1 D 2 T 4 08 2A8 W ;W W x 65 K K 65 1 1 1 1 X I D LA ID LA DMPR CMPR CMPR CMPR GATE GATE LOG10AL ADR FROM CPU 1 0 O0 1 D I 0 04 O O O T0 BUS ADDRESS PR VIRTUAL MEMORY SYSTEM INTRODUCTION Background of the Invention Various techniques are known whereby several com- I puter programs, executed either by a single central processing unit or by a plurality of processing units, share one memory. A memory being shared by programs in this manner requires an extremely large storage capacity, a capacity which is often larger than its actual capacity. To accommodate this situation the concept of "virtual storage is employed. If, for example, a system employs a 24 bit addressing scheme 2 bytes or approximately sixteen million addressable bytes of virtual storage are available. This virtual storage is divided into segments each of which is divided into pages, with each page consisting of a predetermined number of bytes. The segment and page addresses assigned to virtual storage are arbitrary programming designations and are not actual locations in main storage. Therefore, virtual segments and pages can be located randomly throughout main storage and swapped in and out of main storage as they are needed.
Random location of segments and pages in main storage necessitates the translation of virtual address into actual address using a set of conversion tables that are located in main storage. In a virtual memory system a number of sets of conversion tables, are employed, each made of of a segment table and a number of page tables. Each page table in a set of conversion tables reflects the real locations of all the pages of one segment in the segment table. Therefore, ifa particular segment table is divided into l6 segments, there would be 16 page tables and one segment table in the set of conversion tables in performing a translation.
In making a translation, the proper set of conversion tables is selected and the segment table in the set of conversion tables is used to find the location of the page tables in the real memory. The proper page table is then used to find the real location of the addressed page. The byte portion of a virtual address refers to a real location in memory so that once the segment and page portions of the virtual address have been translated to give a page location the byte portion is concatenated onto the page location to give the real address in main storage.
To avoid having to translate an address each time the memory is accessed, current translations of virtual addresses to real addresses are retained in another table called the Directory Look Aside Table (DLAT) where such addresses can be obtained with a virtual address without going through the described translation process. The use of the DLAT significantly reduces the number of translations that must be made and thus has a considerable effect on the performance of the virtual memory system. It does, however, introduce the possibility of error in that the conversion tables used in deriving the real addresses stored in the DLAT may not be the same as that associated with the data currently being paged. Therefore, even though there may be a match between the virtual address of the current paged data and one of the translations stored in the DLAT, the real address associated with the stored translation is the wrong address. One solution to this problem would be to erase all the translations stored in the DLAT each time new selected translation tables are used. However, this would slow down machine operation considerably since there is a significant increase in the amount of translation that must be done using the translation tables.
Summary of the Present Invention In accordance with the present invention, the problem referred to above is overcome by storing an identifier (ID) for each translation in the DLAT. This identifier signifies the set of tables used in making the translation. In interrogating the DLAT this stored identifier is compared with an identifier generated for the currently requested virtual address. If the virtual address and identifiers of the currently requested address match those for a translation stored in the DLAT, the translation stored in the DLAT may be used. If the identifiers or virtual addresses do not match a new translation must be performed using the set of conversion tables associated with the currently requested address. The equipment used in generating the identifiers for translations stored in the DLAT can also perform other functions. For instance, it can be used to distinguish between virtual addresses having different page and segment sizes and, in addition, can be used to indicate that a real address is being employed instead of a virtual address.
Therefore, it is an object of the present invention to prevent errors from occurring in the translation of virtual addresses to real addresses.
Another object of the present invention is to prevent errors from occurring in translation due to the use of more than one conversion table.
Other objects of the invention are to prevent translation errors due to changes in size of page and segment portions of the virtual address and to permit the same memory to be accessed by both virtual and real memory addresses.
The foregoing and other objects, features and advantages of the present invention will be apparent from the following description ofa preferred embodiment of the invention as illustrated in the accompanying drawings of which:
DESCRIPTION OF THE DRAWINGS FIG. 1 shows a preferred format for a virtual address;
FIG. 2 is a diagramatic representation of virtual-toreal address translation;
FIG. 3 shows preferred formats for segment table entries and page table entries;
FIG. 4 is a block schematic diagram illustrating the relationship between the translation process and elements of a preferred embodiment of this invention;
FIG. 5 is a preferred format for entries in a Transla tion Look Aside Table which forms one part of this invention;
FIGS. 6a and 6b are block schematic diagrams of the preferred embodiment of the invention;
FIG. 7 is a more detailed block diagram of the stepping circuit in FIG. 6;
FIG. 8 is a signal flow diagram of the preferred embodiment of the invention; and
FIG. 9 is a chart of the relationship between binary and gray codes as employed in the preferred embodiment of the invention.
DETAILED DESCRIPTION Since the invention resides primarily in the novel structural combination and the method of operation of well-known computer circuits and devices, and not in the specific detailed structure thereof, the structure, control, and arrangement of these well-known circuits and devices are illustrated in the drawings by use of readily understandable block representations and schematic diagrams, which show only the specific details pertinent to the present invention. This is done in order not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art in view of the description herein. Also, various portions of these systems have been appropriately consolidated and simplified to stress those portions pertinent to the present invention.
Virtual Address Referring to FIG. I, a preferred format for a virtual address is shown. The 24 bit virtual address is divided into three fields: a segment field (SX) which occupies bits 8-15; a page field (PX) which occupies bits 16-20; and a byte field which occupies bits 21-31. With this format, the virtual storage consists of 256 segments, with each segment consisting of up to 32 pages, and each page consisting of up to 2,048 bytes. Those skilled in the art will, of course, recognize that these field defnitions are somewhat arbitrary in nature. For example, one could define the virtual address fields so that SX occupies bits 8-11, PX occupied bits 12-19, and BYTE occupied bits 20-31. With such a format, the virtual storage would consist of sixteen segments with each segment consisting of up to 256 pages, and each page consisting of up to 4,096 bytes. Bits -7 are not used in this preferred embodiment, but could optionally be used to extend the virtual address to provide a 32 bit addressing system. Such a system would have over four billion bytes of virtual memory. The segment field serves as an index to an entry in the segment table. The segment table entry contains a value which represents the base address of the page table associated with the segment designated by the segment field. The page field serves as an index to an entry in the page table. The page table entry contains a value which represents the actual or real address ofthe page. The byte field undergoes no change during translation, and is concatenated with the translated page address to form the actual or real main storage address.
Address Translation The translation process will be further clarified by reference to FIG. 2. The translation process is a twolevel table look-up procedure involving segment and page tables from main storage. The segment address portion (SX) of the virtual address is added to a Segment Table Origin (STO) address stored in a control register 2 in order to obtain a segment table entry 4 from the segment table 6. (Control register 2 will also generally contain the length [LTH] of the segment table.) This segment table entry will contain a Page Table Origin (PTO) address which is added to the page address portion (PX) of the virtual address to provide the address ofa page table entry 8 within the page table 10. Page table entry 8 will contain a real address which is cancatenated with the byte portion of the virtual address to form the real address of a byte of data. To
avoid repeating this translation process for every storage reference, a directory is provided for storing the SX portion of the virtual address along with the corresponding real address which was read from the page table with that segment. The directory will be continually updated to contain the virtual and real page addresses of recently referenced pages. Consequently, at the beginning of a translation, the virtual page address under translation will be checked against the directory to see if the real address is already available. If it is, the directory will provide the real page address which will be concatenated with the byte portion of the virtual address to form the real main storage address. If the address under translation is not found in the directory, it will undergo translation as described above and will be placed in the directory along with its real address.
FIG. 3 shows a preferred embodiment for segment table entries 4 and page table entries 8. For each virtual address space, there is a segment table, with corresponding page table. The origin and length of the active segment table is contained in the control register (FIG. 2). The segment table entry 4 contains a length (LTH) field in bits 0-3 which designates the length of the page table in increments that are equal to a sixteenth of the maximum size. Bit 31, the I bit, indicates the validity of the information contained in the segment table entry. When the I bit is on, the entry cannot be used to perform translations. The page table entry 8 contains, in bit positions 0-12, the high order 13 bits of the real storage address. (The low order real bits of the virtual address are concatenated to the higher order bits from the page table to provide the byte displacement within the page.) There is also an I (invalidity) bit associated with each page table entry. When the I bit is on, the entry cannot be used to perform translations.
Directory Look Aside Table (DLAT) To avoid having to translate an address each time the memory is accessed, current translations of virtual addresses to real addresses are retained in a table called the Directory Look Aside Table (DLAT). As shown in FIG. 4, the virtual address 12 provided by the CPU simultaneously interrogates the Directory Look Aside Table (DLAT) l4 and a directory 16 for the buffer of the memory. The DLAT 14 contains recently translated virtual addresses along with their corresponding real addresses, while buffer directory 16 contains the real addresses of data that have been mapped into the high speed buffer. The tables contained in the DLAT and in the buffer directory may be arranged and accessed in any of several known manners. For example, each could be an associative storage array, or an addressable storage array that is addressed by bits contained in the virtual address where the DLAT is addressed by bits coming from the virtual portion of the address and the directory is accessed by bits coming from the real portion of the address.
To check to see that the DLAT has been properly accessed, a portion of the virtual address is read from the virtual address portion of the DLAT and compared to the corresponding portion of the CPU-provided virtual address 12 by a comparator 18. Likewise, to ensure that the data mapped into the high speed buffer is the data requested by the virtual address 12, the real address read from the DLAT 14 is compared to the real address read from the buffer directory [6 by comparator 20.
The outputs of comparators l8 and 20 are fed to an AND circuit 22, which will generate an output signal on line 24 if the requested data is in the high speed buffer. Appropriate portions of the virtual address and the real address will be fed via lines 26 and 28 to the buffer storage address register 30 so that the data may be addressed from the buffer. If a real address which corresponds to the virtual address 12 is contained in the DLAT 14, but the data is not in the high speed buffer, the output of comparator 20, after inversion by inverter 32, combined with the output of comparator 18 will cause AND circuit 34 to generate a signal on line 36 indicating that a main storage reference is required. If the virtual address 12 does not match a virtual address contained in DLAT 14, the output of comparator 18 will cause AND-I invert circuit 38 to generate a signal on line 40 which will indicate to the system that the translation process described above with respect to FlG. 2 must be initiated. Specific implementations of the manner in which the contents of buffer storage address register 30 and the signal on line 24 may be used to initiate a buffer access cycle, as well as the manner in which the signals on lines 36 and 40 may be used to initiate appropriate system responses, are well known to those skilled in the art and need not be described herein.
As shown in FIG. 6, the Translation Look Aside Table 46 contains 64 words, each of which contains two virtual address entries along with their respective real address entries. Some of the details of the format of a DLAT entry are shown in FIG. 5. As shown, a l2 bit portion of each entry contains bits 8 15 of some virtual address, the real address bits that form the translation of the SX and PX portions of that virtual address. ln addition, each DLAT entry contains a parity bit P, six bits, and three bits, labeled ID, that are generated in accordance with the present invention and described hereinafter.
Prefixing in the DLAT The real address bits stored in the DLAT 46 are not the real address bits obtained by the described translation process, but slightly modified versions of these addresses obtained by a process called prefixing. Prefixing is a procedure used in multiprocessing to permit more than one processor to access a particular memory without effecting each other's status information. The status information is usually stored in a particular part of memory. Prefixing constitutes changing addresses by one bit to avoid the data of one processor from destroying one status information from another. The present embodiment of applicants invention relates to a multiprocessing machine in which prefixing is used so that the data in main memory is obtained by prefixed addresses. Therefore, all real addresses are prefixed by prefix logic 45 on data received from a prefix register 47 before being entered into the DLAT 14 so that absolute addresses are available from the DLAT to compare against the absolute addresses contained in the buffer directory 56. Prefixing is a well known technique and does not constitute a part of the present invention and, therefore, will not be gone into in detail here.
Data Protection Keys in DLAT Storage protect keys are retained in the DLAT to determine if accessibility of the buffer entries is allowed without first having to check the protection key against the processor storage protection array. Thus, when the proper storage protect key is resident in the DLAT. no time is lost in accessibility. Again, storage protection does not constitute part of the invention and will not be gone into detail here.
ID Bits Stored in DLAT in accordance with the present invention, three encoded identifier bits, referred to as the ID bits, are also associated with each DLAT entry. The primary pur pose of the lD bits is to identify the translation tables that apply to the particular DLAT entry, However, they also indicate the size of the page and segment portions of the virtual address. The ID bits are generated by what is called a STO stack or just as STOK. The STOK generates ID bits into the six combinations shown in FIG. 9. Of the illustrated combinations, OlO through 1 l 1 represent different combinations of segment table of origin and page and segment sizes. When one of these six IDS is generated, it is supplied by the STOK lD generator 49 to the DLAT 46 where it is inserted with each new translation read into the DLAT 46 and compared in comparators 52 with the ID of each translation read out of the DLAT 46. When the ID read out of the DLAT 46 is identical to the ID supplied by the STOK indicated generator 49, the segment table of origin, page size and segment size used in the virtual address of the DLAT translation corespond with the segment table of origin, page size and segment size used in the virtual address now interrogating the DLAT. Thus, a DLAT compare of the ID bits occurs permitting the translation stored in the DLAT to be used to interrogate the memory. If the [D supplied by the STOK indicator generator 47 is different from that read out of the DLAT 47, it means that the STO, the page size or the segment size of the virtual address interrogating the DLAT is not the same as that of the translation and in the DLAT. In this case the wrong address has been read out of the STO stack in response to the interrogation. If this happens, a DLAT compare does not occur, preventing the translation stored in the DLAT from being used to interrogate the memory. instead, reference is made back to the set of translation tables to generate a new translation of the virtual address into a real address. When this new translation is generated it will be inserted into the DLAT 47 with a new lD provided by the STOK as shall be seen hereinafter.
The input to the STOK lD generator 49 is the output of the word select decoder which seiects one word out of six possible words stored in the STOK memory array 55. Thus, the input to the STOK generator comprises six bits of data, all but one of the bits being binary 0s and the remaining bit being a binary l which changes from bit position to bit position depending upon what word is being addressed in the STOK array 55. Each word of the STOK array stores bits 8 25 of the segment table of origin address, one bit indicating page size and one bit indicating segment size stored in the STOK array from the control registers when the particular combination of segment table of origin, page size and segment size were used. Thus, the output of the STOK ID generator is really coded information as to the location of the STOK array of the word containing the last combination of segment table of origin, page size and segment size fed into the control registers.
A pointer 59 is the output of the stepping circuit that provides three data bits in gray code to the word select decoder 57 so that the word select decoder 57 can be addressed to access each of the six words of the STOK array in the sequence shown in FIG. 9. Details of this stepping circuit are shown in FIG. 8 and will be described in detail later. It is sufficient to know that the stepping circuit is free-running, but can be stopped at any point by a signal from a hold pointer latch 71 that provides a gating signal to the pointer 59 stopping the pointer at the word containing the bits for the last used virtual address.
An input to the hold pointer latch 71 is the output of a compare circuit which compares the output of the STOK array 55 with the data stored in the control registers 51 and when they compare, the compare circuit sends a signal to the hold pointer latch latching the latch to hold the pointer at the address of the compared bits. So long as there is no change in the page size, segment size or segment table of origin used in the virtual addresses interrogating the memory, the output of the latch 71 is held at an up level maintaining the output of the pointer stationary.
When there is a change in the segment table of origin, page size and segment size used in a particular virtual address, the hold pointer latch 71 is delatched by latch release pulse which is supplied to the HP latch 71 upon occurrence of a change thereby releasing the pointer 59 and allowing the output of the pointer to be stepped along by the counter 63 so that the word select decoder output addresses words of the STOK array in the preselected sequence. As each word is addressed, it is read out into the compare circuit 53 and compared with the data in the control registers. This continues until a comparison indicates the identity of the data in the registers 51 with that stored in one word line of the STOK array 55. The compare circuit then latches the hold pointer latch and thereby stops the pointer at the address of the word line, resulting in the compare identity. The address of the word where the comparison is made is then fed to the STOK ID generator 49 and three new coded ID bits are supplied to the DLAT 46.
If no compare identity occurs between the data stored in the STOK array 55 and that stored in the control registers 51 after the output of the stepping circuit steps the STOK array 55 once through all the words in the STOK array, the stepping circuit is stopped by the hold pointer latch 71. The output of the counter 63 is then degated by the removal of the gate counter signal GC to AND gate 65. Instead, the output of a register 67 storing the gray code digits for ordering the address for the word containing the earliest entry into the STOK array is gated through AND gate 69 to the pointer 59 from a counter 67, referred to as the first in first out counter of FIFO. The pointer 59, therefore, addresses the word select decoder 57 instructing it to generate the address of the oldest entry of the STOK array 55. The data in the control registers 51 is then stored in this word and read out resulting in an identity compare signal from comparator 53 that latches the hold pointer latch 61 and holds the pointer 59 at the address of the words being entered. A signal HF that holds the FIFO 67 stationary is then removed from the FIFO 67 allowing it to step once to the next gray code number in the sequence shown in FIG. 9, thereby storing the address in which the next entry is to be made. Once this is completed, the gate FIFO signal HF is removed and the STOK ID generator 49 supplies an ID indicative of the address of the entry to the DLAT 46.
When the data stored in any particular address in the STOK array 55 is changed in the manner described above, all the DLAT entries referring to that address must be removed from the DLAT 46. Thus, when the ID for that address is first supplied to the DLAT it is compared in compare circuits 52 with the IDs in each entry stored in the DLAT 46. Those entries with the same ID are then invalidated by replacing the ID digits with 000 so that they cannot possibly match any ID supplied by the STOK array and provide an erroneous DLAT match. This leaves the purpose of only one of the eight possible three digit ID combinations to be explained. This ID is used when the memory is being interrogated by real addresses instead of virtual address. When a real address is being used the memory goes into DAT or real mode providing a pulse to gate 81 that degates the addressed data from the input of the STOK ID generator 49 causing the STOK ID generator to generate the 001 combination of digits.
STOK Stepping Circuit The details of the STOK stepping circuit of FIG. 6 are shown in FIG. 7. It can be seen in that diagram that the counter 69, the pointer 59 and FIFO 67 each comprise three AND/OR invert latches. In the diagram, the FIFO and counter latches are designated as latches while the pointer circuits are referred to as triggers. In actuality, they are all identical AND/OR invert latches, the only distinction between them being the clocking pulses sent to the counter and FIFO occur at a different time in the clocking pulse provided to the trigger. As can be seen, the output of the pointer triggers supply three bits of grey code parallel to the word select decoder 57. Each of the latches in the counter and FIFO circuit receive a clock pulse, referred to as a latch clock pulse or LC, while the latches in the pointer 59 receive a clock pulse that occurs later in time and is referred to as the trigger circuit TC. Likewise, the hold pointer goes to each of the latches in the pointer and the hold FIFO pulse is supplied to each of the latches in the FIFO. There are actually three separate sets ofAND gates 65 69 in the stepping circuit as shown in this diagram, each addressing one of the trigger circuits instead of the one shown schematically in FIG. 6. The circuit, as shown, provides the gray code output in the sequence shown in FIG. 9 when released.
Details of DLAT Operation Logical DLAT Address Hits ISV II II II II II I O\(R&UN
The virtual address bits that are mapped into the DLAT are, for this preferred embodiment, bits 8, 9, I0, 11, 12, 13, 14 and 15. To translate a virtual address, the DLAT is interrogated at one of the 64 addresses and the two entries selected. Virtual bits 8 in the address provided by the CPU are compared to the high order virtual bits read out of the DLAT and the ID is matched to the currently active ID. If a match is indicated, the translated address and protection key are obtained from the real address and key fields. If no protection violation exists the real address is then compared against the buffer directory to determine if the address has been mapped into the high speed buffer. If the address is not in the buffer, main storage is referenced When a translation is not found in the DLAT, the system performs the translation (see FIG. 2) and maps it into the DLAT.
Additional details of the preferred embodiment of the invention are shown in FIG. 68. Bits 8 31 of the virtual address supplied by the CPU are supplied to a storage address bus 44 for distribution within the data processing system. Bits 8 are used to address the Directory Look Aside Table 46 which contains virtual address bits 8 15. Bits 8 15 of the virtual address provided the CPU are also furnished to comparator 52. If comparator 52 receives inputs that are equal to each other, it will generate a signal on line 54 indicating a DLAT match. At the same time that the DLAT is being accessed, the buffer directory will be accessed by bits 21 26 of the address provided by the CPU. These bits of the virtual address correspond to real main memory locations. Therefore, their use in addressing the directory 56 is compatible with the real address orientation of the buffer memory. In the preferred embodiment, the buffer directory contains 64 words, each of which contains four or eight real addresses, depending on optional buffer size. Bits 21 26, therefore, access four or eight real addresses. Bits 21 28 appended to the three bits designating one of the four or eight buffer directory columns contained in buffer storage address register 68 will be used to access one of 1,024 or 2,048 double words stored in high speed buffer 77 for transmission to the CPU. Bits 29 31 (the low order real address bits) of the virtual address supplied by the CPU need not be utilized in accessing the high speed buffer because, in the preferred embodiment, each double word in the buffer contains eight bytes of data, each byte consisting of eight data bits plus one parity bit. The CPU will utilize the three low order bits (bits 29 31) to select one ofthe eight bytes read from the high speed buffer. If neither comparator 58 nor 60 had sensed an equality (no buffer directory match data not in high speed buffer) or if comparator 52 had not sensed an equality (no DLAT match translation not already available) the situation would be handled in the manner discussed above with respect to FIG. 4.
FIG. 8 contains a flow diagram of a determination of a particular logical or virtual address in accordance with the invention described hereinabove. As can be seen, the identifier bits l 1,, I, from the STD stack are hashed with bits 8 to 20 of the logical address to generate the address bits for the DLAT arrays. The data read out of these arrays are then compared with bits 8 to 15 of the logical address and with the ID bits to select one of the outputs from the DLAT and to assure that the proper real address has been accessed.
Although, in describing the preferred embodiment of the invention, various parameters were specified either explicitly or implicity, those skilled in the art will readily recognize that this invention is not limited to the formats and sizes described above. An example of an implicitly specified parameter is the size of the main or backing store. Since the size of the virtual memory was given as being over sixteen million bytes, and 13 bits of the virtual address were shown to be translated into 10 bits of a real address, it is clear that the real address utilized in the preferred embodiment contains somewhat over two million bytes of data.
It will also be recognized that the terms virtual memory and virtual address" need not be limited to the definitions used herein. Essentially, a virtual address is an address which is changed prior to its utilization to access storage.
Those skilled in the art will further recognize the buffer accesses need not necessarily be delayed until the address comparisons have been completed. Access to the buffer could be initiated, for example, by the virtual address and, depending upon the result of the address comparisons, system usage of data read from the buffer could be inhibited (degated) later in the cycle. In such a system, the buffer would still be real-address oriented in the sense that its buffer directory would still contain real addresses.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the above and other changes in form and details may be made therein without departing from the spirit and scope of the invention.
What is claimed is:
1. In a data processing system which contains a central processing unit, a main storage unit having a storage control unit and a plurality of addressable locations each addressable by a storage address, addressing means providing virtual address, and means for translating virtual addresses to real addresses including a plurality of sets of conversion tables, an improved translation control means comprising:
a. first table means for storing a plurality of previously used virtual addresses each with a real address which constitutes a translation of that virtual address using one of said sets of conversion tables;
b. second table means for storing identifying data from the storage control means indicating the particular set of tables used in generating each translation stored in the first table means;
c. coding means for generating a coded signal to the first table for storage along with each virtual to real address translation, said coding means providing the coded signals any time identifying data is addressed in the second table means;
cl. first comparator means for comparing the identifying data being addressed in the second table with the identifying data supplied by the storage control means for the currently requested virtual address and providing an output signal indicating a match or mismatch of this data; and
e. stepping means responsive to the signals from said comparator means for addressing in sequence different identifying data signals stored in said second table means when a mismatch signal is provided by the comparator and for addressing the address of data providing a match signal from the comparator.
2. The data processing system of claim 1 including means responsive to the currently requested virtual address for reading the same virtual address from the first table means along with the translation of that address to a real address and the coded signal indicating the set of tables used in making the translation; and
a second comparison means for comparing the stored virtual address to the currently requested virtual address and for comparing the stored coded identifying data to the identifying data for the currently requested virtual address provided by the coded means. 3. The data processing system of claim 2 including means for inserting the identifying data for the currently requested virtual address into the second table means when said data has not been found therein, including:
said coded signals as a function of the address signals. a a m a
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