text:
In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.
1. A method of operation within an integrated circuit device, the method comprising:
generating a plurality of samples of an incoming signal;
storing the plurality of samples one after another in a first storage buffer;
transferring at least a first subset of the plurality of samples from the first storage buffer to a decoder circuit in response to each assertion of a first control signal;
transferring at least a second subset of the plurality samples from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, wherein the first and second strobe signals are asserted asynchronously with respect to each other; and
generating a plurality of updated tap weights within the tap weight update circuit based, at least in part, on the second subset of the plurality of samples.
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11. An integrated circuit device comprising:
a sampling circuit to generate a plurality of samples of an incoming signal;
a storage buffer to store the plurality of samples;
a decoder circuit coupled to receive at least a first subset of the plurality of samples from the storage buffer in response to each assertion of a first control signal;
a tap weight update circuit coupled to receive at least a second subset of the plurality of samples from the storage buffer in response to each assertion of a second control signal; and
a timing control circuit configured to assert the first control signal and the second control signal asynchronously with respect to each other.
12. The integrated circuit device of
13. The integrated circuit device of
14. The integrated circuit device of
15. The integrated circuit device of
16. The integrated circuit device of claim 111 wherein the timing control circuit is configured to periodically assert the first control signal at a first frequency and to periodically assert the second control signal at a second frequency.
17. The integrated circuit device of
18. The integrated circuit device of
19. The integrated circuit device of claim 111 wherein the decoder circuit is configured to decode an N-bit data word constituted by the at least a first subset of the plurality of samples into an decoded data word having fewer than N constituent bits.
20. Computer-readable media having information embodied therein that includes a description of an integrated circuit device, the information including descriptions of:
a sampling circuit to generate a plurality of samples of an incoming signal;
a storage buffer to store the plurality of samples;
a decoder circuit coupled to receive at least a first subset of the plurality of samples from the storage buffer in response to each assertion of a first control signal;
a tap weight update circuit coupled to receive at least a second subset of the plurality of samples from the storage buffer in response to each assertion of a second control signal; and
a timing control circuit configured to assert the first control signal and the second control signal asynchronously with respect to each other.
21. An integrated circuit device comprising:
means for generating a plurality of samples of an incoming signal;
means for storing the plurality of samples;
decoding means coupled to receive at least a first subset of the plurality of samples from the storage buffer in response to each assertion of a first control signal;
tap weight update means coupled to receive at least a second subset of the plurality of samples from the storage buffer in response to each assertion of a second control signal; and
means for asserting the first control signal and the second control signal asynchronously with respect to each other.
This application is a continuation-in-part of, and hereby incorporates by reference, each of the following U.S. patent applications Ser. Nos.:
The present invention relates to high speed signaling within and between integrated circuit devices.
Electrical pulses transmitted on a band-limited signaling path disperse in time as they travel from source to destination. In systems in which data is transmitted as a sequence of level-encoded electrical pulses, such time-domain dispersion results in a blending of neighboring pulses; an effect known as dispersion-type inter-symbol interference (ISI). Dispersion-type ISI becomes more pronounced at faster signaling rates, ultimately degrading the signal quality to the point at which distinctions between originally transmitted signal levels may be lost.
In a low-noise system, the drive strengths of the post- and pre-tap output drivers would theoretically be adjusted based on errors between receiver-sampled signal levels and expected signal levels (e.g., as shown by error indication, "e" at 112) until the pre-emphasis signals generated by the transmitter effect a transfer function (W) that is an exact inverse of the transfer function (P) of the signal path 102, thereby yielding a waveform at the input of receiver 103 that is identical to the primary output signal (i.e., W*P=1). This effect is illustrated in the waveforms of
Together, the transmitter power constraint and the data-dependent attenuation present a number of challenges in the prior-art signaling system 100. A fundamental problem is how to generate the error signal used to adjust the drive strengths of the transmitter output drivers considering that no known data level can be reached for all data patterns. That is, if the known reference levels +/−1 cannot be reached in high-frequency data patterns, attempting to converge to such levels tends to produce non-optimal drive-strength settings from the standpoint of link performance.
One prior-art solution for generating error signals that may be used to update the drive strengths of the transmitter output drivers is to provide a variable gain element, G (shown in dashed outline in
In view of the challenges involved in dynamically updating drive strengths of transmit-side output drivers, many system designers opt for a simpler approach, setting the drive strengths based on empirical results obtained in particular system configurations. While such static drive strength settings work well in many systems, non-optimal settings often result in systems which are subject to post-production configuration changes (e.g., adding modules, circuit boards or other components that affect signaling system characteristics), and systems that are sensitive to process variations and to changes in environmental factors such as voltage and temperature.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be "asserted" when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be "activated" when a signal is asserted on the signal line, and "deactivated" when the signal is deasserted. Additionally, the prefix symbol "/" attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., '{overscore (<signal name>)}') is also used to indicate an active low signal. The term "terminal" is used to mean a point of electrical connection. The term "exemplary" is used to express but an example, and not a preference or requirement.
Signaling systems having a multiple-output driver transmit circuit are disclosed in various embodiments. In one embodiment, the drive strengths of output drivers within the transmit circuit are adaptively adjusted concurrently with adaptive determination of a target, receive-side signal level. Thus, even as adaptive determination of the target signal level is ongoing, the target signal level is compared with received signals to generate error signals that are used, in turn, to adjust the drive strengths of the output drivers. By this operation, a target signal level is determined and used to establish drive strength values that yield a substantially flattened channel response to different-frequency transmit data patterns.
In one embodiment, the error signals that result from comparison of received signals with the target signal level are input to a circuit that generates updated drive strength values, referred to herein as tap weights, in a manner that converges to a least-mean-square (LMS) error. In an alternative embodiment, the target signal level is used to establish a trap range, with signals falling within the trap range being used to update the drive strength values. In either embodiment, after being updated, the set of drive strength values may be scaled according to the transmit circuit power constraint. By this operation, the adaptive determination of the target signal level converges to a level that corresponds to the peak (or average) power available to the signal transmitter. Thus, a target level that corresponds to a substantially flattened frequency response at the peak or average power available to the signal transmitter is, in effect, learned by the system and used as an error reference for continued adjustment of output driver drive strengths.
In one implementation, a Taylor series approximation is used to simplify the power scaling of the drive strength values, enabling the scaling operation to be carried out in a relatively small logic circuit. In alternative implementation, drive strength values for pre- and post-tap output drivers of the transmit circuit are first updated and the drive strength of the data driver adjusted up or down to maintain the overall transmit power level within a predefined range.
In other embodiments of the invention, DC offsets within individual samplers of the receive circuit are adaptively canceled; multiplexing circuitry is provided to enable one or more samplers within the receive circuit to be temporarily removed from service and replaced by another sampler; and single- and two-phase techniques are applied to generate drive strength update values.
In other embodiments, adaptive updates to tap weights, decision thresholds and other controls are selectively inhibited according to whether incoming data meets a predetermined randomness criteria. Also, data precessing may be used to mitigate the effects of repeating data patterns on adaptively generated controls. These and other embodiments and features of the invention are disclosed below.
Signaling System Overview
Referring to
In the receive circuit 209, a single symbol is captured during each cycle of the sampling clock signal 210. That is, a rising (or falling) edge of the sample clock is used to capture a sample of the incoming signal, x′n. In a multi-data rate system, multiple symbols are captured per cycle of the sampling clock signal 210 as shown in
Still referring to
The tap weight register is used to store a set of drive strength values, W N, referred to herein as tap weights. As described below, the tap weights are iteratively updated, with each new set of tap weights being designated by an incrementally higher subscript (i.e., N, N+1, N+2, etc.). Each tap weight of a given set, WN(0)-WN(4), is supplied to a respective one of the output drivers 205 0-205 4 to control the level of the output signal generated by the output driver. In one embodiment, the signal path 202 is pulled up to a predetermined voltage level (e.g., at or near supply voltage) by single-ended or double-ended termination elements, and the output drivers 205 0-205 4 generate signals on the signal path 202 by drawing a pull-down current, IPD (i.e., discharge current), in accordance with the corresponding tap weight and data value. As a specific example, in a binary signaling system, each output driver 205 0-205 4 draws a current according to the following expression:
It should be noted that the particular numbers of pre-tap and post-tap drivers (and corresponding tap weights and shift register elements) shown in
In one embodiment, each of the tap weights, WN(0)-WN(4) is a digital value having a sign component and magnitude component. The sign component of the tap weight (e.g., sign bit) is exclusive-NORed with the corresponding transmit data value to generate the sign of the signal contribution to be generated by the corresponding output driver 205. The exclusive-NOR operation effectively multiplies the signs of the tap weight and transmit data value, yielding a logic '1' (i.e., interpreted as a positive sign in one embodiment) if the signs of the tap weight and transmit data value are the same, and a logic '0' (i.e., negative sign) if the signs of the tap weight and transmit data value are different. The magnitude component of the tap weight is a multi-bit value used, for example, to control a digital-to-analog converter (DAC) within the output driver. Thus, the expression (1) may be rewritten as follows:
Output Driver Tap Weight Determination
Referring again to
In one embodiment, the receiver 209 generates updated tap weights, W N+1, based upon a comparison of incoming signals with an adaptively determined target signal level 220, referred to herein as a data level threshold, DLEV. The receiver 209 includes an adaptive module 215 (AM) and a pair of sampling circuits referred to herein as a data sampler 211 (D) and an adaptive sampler 213 (A). The data sampler samples the incoming signal, referred to herein as x′n to emphasize the channel transformation of originally transmitted signal, xn, and generates a data sample 216 (RX Data) having a logic '1' or logic '0' state according to whether the incoming signal exceeds a zero reference. In a single-ended signaling system, the zero reference may be generated by a DAC, voltage divider or other circuit and set to a point midway between steady-state high and steady-state low signaling levels. In a differential signaling system, the common mode of the incoming differential signal may constitute the zero reference so that if the signal level on the positive signal line (e.g., line 240 of
The adaptive sampler 213 also samples the incoming signal, x′n, and generates an error sample 218 having a logic '1' or logic '0' state according to whether the incoming signal exceeds the data level threshold 220 generated by the adaptive module 215. In one embodiment, the data level threshold 220 corresponds to an expected data level of logic '1' transmission, so that if the incoming signal is determined to have a positive sign (i.e., RX Data=sgn(x′n)='1'), then the error sample 218 generated by the adaptive sampler 213 represents the sign of an error between the incoming signal level and the expected signal level (i.e., the data level threshold 220, DLEV). Accordingly, the error sample 218 is referred to herein as an error sign value (sgn(en)) and is a logic '1' (i.e., positive) if x′n, <DLEV, and a logic '0' (i.e., negative) if x′n≧DLEV).
The adaptive module 215 receives the data sign and error sign values, 216 and 218, from the data sampler 211 and adaptive sampler 213, respectively, and adaptively updates the data level threshold 220 and pre-emphasis tap weights 226 in response. Referring to
In some systems, it is desirable to shape the frequency response differently from the flattened response described in reference to
In one embodiment, each new set of updated tap weights 226 is communicated to the transmitter via a back channel 225. The back channel 225 may be formed, for example, by a relatively low-speed signaling path, or by out-of-band signaling over the signaling path 202 (e.g., using an otherwise unused code space within a signal encoding protocol such as 8 b/10 b or other signal encoding). In an alternative embodiment, a separate back channel may be omitted and the signaling path 202 may be used to communicate updated tap weights 226 (or update values that enable transmit-side generate of updated tap weights 226) to the transmit-side device.
Adaptive Module
The sign multiplier 257 includes a set of exclusive-NOR gates 258 0-258 4 each having a first input coupled in common to receive the stored error sign value from the error sign register 253 and each having a second input coupled to receive a respective data sign value from the data sign register 251. By this arrangement, each of the exclusive-NOR gates 258 0-258 4 generates a respective one of update values 260, UD(0)-UD(4), in a logic '1' state if the corresponding data sign value matches the error sign value, and in a logic '0' state if the data sign value and error sign value do not match. Thus, each of the update values 260 represents a multiplication of the signs of the input signal (i.e., x′n−1-xn−4, respectively) and error signal en−1 and therefore is a logic '1' if the signs are both positive or both negative, and a logic '0' if the signs are different. In one embodiment, each of the update values 260 is filtered within a respective one of filter elements 262 (F) to decrease update dither due to noise in the update estimate. In an alternative embodiment, the filter elements 262 are omitted.
In one embodiment, a tap weight is made more positive in response to a logic '1' update (i.e., a positive update) and more negative in response to a logic '0' update value (a negative update). More specifically, a positive tap weight is incremented (e.g., by a predetermined step size) and a negative tap weight decremented in a positive update. Conversely, a positive tap weight is decremented and a negative tap weight incremented in a negative update. In one embodiment, the positive and negative updates applied to the tap weights constitute a sign-sign least-mean-square (LMS) update that may be expressed as follows:
In the embodiment of
Still referring to
In the embodiment of
In the embodiment of
Still referring to
In one embodiment, the offset count 264 (or DAC output 266) is supplied to both the adaptive sampler and the data sampler (e.g., elements 213 and 211 of
Power Scaling
Still referring to
In an alternative embodiment, circuitry within the adaptive module itself is used to carry out re-scaling based on a Taylor-series approximation that reduces computational complexity relative to the direct re-scaling approach. That is, rewriting expression (4), the following expression for residual power (i.e., amount of power by which the updated tap weights exceed or fall below the power constraint) is obtained:
The update values 260 and existing tap weights in registers 302 are also supplied to respective scaling circuits 301 0-301 4 along with the shift value 298, and the sign component 310 of the residual power value 294. Referring to the detailed view of scaling circuit 301 4, the update value, UD(4), and tap weight WN(4) are input to an increment/decrement circuit 303 which generates an updated tap weight value 304 having an incremented magnitude if the tap weight and update have the same sign (i.e., both positive or both negative) and a decremented magnitude if the tap weight and update have different signs. In the embodiment of
Reflecting on the power scaling logic of
The power scaling logic 320 includes a set of tap weight counters 3250-3254, state counter 324, operand multiplexer 327, accumulator 329, and primary update logic 341. Tap weight updates 260 for the pre- and post-tap driver tap weights are supplied to the power scaling logic 320 along with negative versions of upper and lower power bound values, 323 and 321, respectively, and the update-weight signal 282. At the start of an update event, the update-weight signal 282 is asserted to enable the tap weight counters for the pre- and post-tap weights (i.e., 325 0 and 325 2-325 4) to be incremented or decremented according to the state of the corresponding update signal 260. Assertion of the update weight signal also triggers the state counter 324 to roll over from a final state count of seven, to an initial state count of zero and enables the state counter 324 to auto increment from zero to seven. The state count 326 is supplied to the operand multiplexer 327 so that, as the state count 326 progresses from zero to six, the operand multiplexer 327 outputs, in turn, the magnitudes of the updated tap weights stored in counters 325 0, 325 2, 325 3 and 325 4, and the negative lower and upper power bounds, 321 and 323, to the accumulator 329.
The accumulator 329 includes a temporary register 333 (TREG), summing circuit 335 and multiplexer 331. The multiplexer 331 has a control input coupled to receive the state count 326 and three input ports coupled respectively to the outputs of the operand multiplexer 327, summing circuit 335 and temporary register 333. When the state count 326 is zero, the multiplexer 331 outputs the operand 330 selected by the operand multiplexer 327 (i.e., the magnitude of updated pre-tap weight, |WN+1(0)|, maintained within tap weight counter 325 0); when the state count 326 is one, two, three or four, the multiplexer 331 outputs the sum generated by the summing circuit, and when the state count 326 is five and above, the multiplexer 331 outputs the content of the temporary register. The summing circuit 335 has first and second inputs coupled respectively to the outputs of the operand multiplexer 327 and the temporary register 333. The temporary register 333 is coupled to receive the output of the multiplexer 331 and is re-loaded in response to each transition of the state count 326. By this arrangement, when the state count 326 is zero, the magnitude of the updated pre-tap weight, |WN+1(0)| is applied to the input of the temporary register 333. When the state count 326 transitions from zero to one, the temporary register 333 is loaded with the magnitude of the pre-tap weight, and the magnitude of the primary tap weight, |WN(1)| is output by the operand multiplexer 327 and summed with the magnitude of the pre-tap weight (i.e., the content of the temporary register 333) in summing circuit 335. The sum of tap weight magnitudes WN+1(0) and WN(1) is selected by the multiplexer 331 (i.e., in response to state count=1) and supplied to the input of the temporary register. Accordingly, when the state count 326 transitions from one to two, the sum of tap weight magnitudes |WN+1(0)| and |WN(1)| is loaded into the temporary register 333 and supplied to the summing circuit 335 for summation with the magnitude of the updated post-tap weight, |WN+1(2)| (i.e., the tap weight magnitude selected by the operand multiplexer 327 in response to state count=2). By this operation, as the state count 326 is incremented from zero to four, a sum of the tap weight magnitudes is accumulated in the temporary register 333, culminating in storage of the sum of the magnitudes of all the tap weights (i.e., |WN+1(0)|+|WN(1)|+|WN+1(2)|+|WN+1(3)|+|WN+1(4)|) within the temporary register 333 when the state count 326 transitions from four to five. The sum of magnitudes of all the tap weights represents the power in the updated tap weights, prior to updating the primary tap weight and is referred to herein as a proposed power value. When the state count 326 is five and above, the multiplexer 331 selects the output of the temporary register to be re-loaded into the temporary register, effectively placing the temporary register 333 in a hold state to maintain the proposed power value therein. In an alternative embodiment, the temporary register 333 is not re-loaded after the count value reaches 5, thereby maintaining the proposed power value in the temporary register 333.
Still referring to
Still referring to
Reflecting on the operation of the power scaling logic 320, it can be seen that the proposed power may, in some instances, be greater than the upper power bound or less than the lower power bound by more than one (e.g., if the power in the initial tap weights matches the upper power bound and the magnitude of more than one tap weight is increased). In one embodiment, this circumstance is tolerated, as iterative adjustment of the primary tap weight will ultimately bring the applied power within the power constraint. In an alternative embodiment, the primary tap weight may be adjusted in each tap weight update cycle according to difference between the proposed power and upper power bound (or lower bound), thereby ensuring that the power constraint will be met in each update. In either embodiment, after the primary tap weight is adjusted, the complete set of updated tap weights may be provided to the transmit circuit, for example, via the back channel 225 shown in
Differential Samplers
When the preamplifier stage 361 is balanced (i.e., control values substantially equal to complement control values), the voltages on the preamplifier output nodes 378 and 379 are substantially equal when input signals x′ and /x′ are at the common mode potential (i.e., as when x′ and /x′ cross one another in transition). Thus, in the absence of systematic DC offset, the effective threshold of the preamplifier stage 361, and therefore the sampler 360 as a whole, occurs at the common mode of x′ and /x′. By contrast, when the preamplifier is imbalanced, for example, by increasing CDLEV relative to /CDLEV, equal values of x′ and /x′ result in output node 379 being pulled lower than output node 378 due to the fact that transistor 365 is wider than transistor 364 (and therefore has a greater gain), and that the compensating (balancing) effect of differential amplifier 363 is diminished by the reduced control value /CDLEV. Thus, increasing CDLEV relative to /CDLEV increases the effective threshold of the preamplifier above the common mode. By increasing CDLEV to the point at which the threshold between '0' and '1' signal levels is set to the target data level, DLEV, a sampler having a threshold level at DLEV is achieved. By reversing the connections of the CDLEV and /CDLEV values to the current DACs of a counterpart sampler (not shown), a sampler having a threshold level at −DLEV is achieved. Such a technique is applied in a multi-level signaling embodiment described below.
Still referring to the preamplifier stage 361, it should be noted that in the case of a binary data sampler, such as element 211 of
The sampling stage 385 includes a differential amplifier 397 formed by transistors 398 and 399, a sense amplifier 387 formed by back-to-back coupled inverters 388 and 389, and a storage circuit 396 formed by a set-reset flip-flop. The differential amplifier 397 includes control inputs coupled to the output nodes 378 and 379, respectively, of the preamplifier stage 361, and output nodes 391 and 393 coupled to source terminals of the inverters 388 and 389, respectively. A biasing transistor 390, switchably controlled by the sampling clock signal 210 (or other sample control signal), is coupled between the differential amplifier 397 and a ground reference (or other low voltage reference). The sampling clock signal 210 is additionally coupled to control inputs of positively-doped MOS (PMOS) transistors 394 and 395 which are coupled between a supply voltage (e.g., VDD) and output nodes of the inverters 388 and 389. By this arrangement, when the sampling clock signal 210 is low, transistor 390 is switched off, and transistors 394 and 435 are switched on to pre-charge the output nodes of the inverters 388 and 389 to the supply voltage. The output nodes of the inverters 388 and 389 are coupled to active-low set and reset inputs, respectively, of the storage circuit 396, so that the content of the storage circuit 396 is maintained through the low half-cycle of the sampling clock signal 210. When the sampling clock signal 210 goes high, biasing transistor 390 is switched on and draws current through the two transistors 399 and 398 of the differential amplifier 397 in proportion to the voltages developed on the output nodes 378 and 379 of the preamplifier stage 361. Thus, if the voltage developed on node 379 is higher than the voltage on node 378, the current drawn by biasing transistor 390 will flow primarily through transistor 398. Conversely, if the voltage developed on node 378 is higher than the voltage on 379, the current drawn by biasing transistor 390 will flow primarily through transistor 398. Transistors 394 and 395 are switched off in response to the high-going sampling clock signal 210 so that the pre-charged outputs of the inverters 388 and 389 are discharged by currents flowing through transistors 398 and 399. By this operation, if the incoming differential signal (x′) exceeds the common mode voltage, (i.e., (x′+/x′)�2), by more than the target data level threshold (i.e., the incoming differential signal exceeds the target threshold level, DLEV), the current drawn by biasing transistor 390 will flow primarily through transistor 398. Consequently, the output node of inverter 389 will be discharged more rapidly than the output node of inverter 388, driving the output of inverter 389 low and driving the output of inverter 388 high (i.e., the PMOS transistor within inverter 388 is switched on and the NMOS transistor within inverter 388 is switched off). The low output of inverter 389 is applied to the active-low set input of the storage circuit 396, causing the storage circuit 396 to store a logic '1' sampled data value. By contrast, if the incoming signal level does not exceed the target data level threshold, the current drawn by biasing transistor 390 will flow primarily through transistor 399, thereby driving inverter 388 low (and driving inverter 389 high) to store a logic '0' sampled data value within storage circuit 396.
Still referring to
In one embodiment, the relative gains (i.e., transconductance values) of the various transistors used to implement the current DAC 381 are established by adjusting the width-length ratio (i.e., W/L) of individual control transistors 407 and/or biasing transistors 409. For example, the width-length ratio of the x2 control transistor 407, is twice the width-length ratio of the x1 control transistor 407 0, the width-length ratio of the x4 control transistor 407 2 is twice the width-length ratio of the x2 control transistor 407 1, and so forth. The biasing transistors 409 may have similar gain ratios relative to one another (e.g., x1, x2, x4, x2N−1 as shown in
When the complementary DAC control values CDLEV and /CDLEV, and COFST and /COFST are substantially the same, and in the absence of DC offset, the sampler 420 is balanced and the effective threshold occurs at the common mode of the incoming x′ and /x′ signal levels. That is, if x′ exceeds the common mode voltage, VCM=(x′+/x′)+2, the current through node 393 exceeds the current through node 391, causing a logic '1' to be captured as the sampled data value. As CDLEV is increased and /CDLEV correspondingly decreased, the effective threshold of the differential amplifier is increased such that x′ must be higher than /x′ by an amount necessary to overcome the additional current drawn by transistor 419 of the offset control circuit 410. Thus, by increasing CDLEV and decreasing /CDLEV, the effective threshold of the sampling circuit 420 may be set to the target data level threshold. That is, a logic '1' is output as the sampled data value if the difference between x′ and /x′ exceeds the target data level threshold, and a logic '0' is output otherwise. By reversing the connections of the CDLEV and /CDLEV values to the current DACs 416 and 414, a sampler having a threshold level at −DLEV is achieved. Such a technique is applied in a multi-level signaling embodiment described below.
As with the sampler 360 of
Still referring to
Updating Tap Weights in Response to Data Level Error
Assuming a linear channel response, the linear filtering effect of the equalizer is commutative and therefore may be applied to the input signal, x(n), before the signal is transmitted on the channel 431. That is, instead of receive-side equalization, transmit-side pre-emphasis may be used to establish a pre-emphasized input signal, y(n) which, after propagating through the channel 431, yields a system response x′(n) that corresponds to the system response x′(n) realized in the receive-side equalization system of
In one embodiment, the tap weight update operation is a sign-sign LMS operation in which the sign of the channel response and sign of the error signal are used to update the tap weights as follows:
In the embodiment of
Reflecting on the adaptive generation of pre-emphasis tap weights achieved by iteratively performing the two-phase tap weight updates described in reference to
In one embodiment, the operations of blocks 475-481 are repeated until, at decision block, 483, the index variable, n, is determined to have reached a final value. When the final value is reached, the tap weight adaptation operation is deemed completed. In an alternative embodiment, the operations of blocks 475-481 are repeated until tap weight updates result in negligible reduction in the error signal. In another alternative embodiment, the operations of blocks 475-481 are repeated until all or a subset of the tap weights are determined to be dithering by one or more steps.
Referring again to
Adaptive Sampler as Proxy Data Sampler
In the embodiment of
The output path multiplexers 511 and 513 each have first and second input ports coupled to receive the outputs of the data sampler 501 and adaptive sampler 503. More specifically, the first input port of output path multiplexer 511 and the second input port of output path multiplexer 513 are coupled to the output of the data sampler 501, and the second input port of output path multiplexer 511 and the first input port of output multiplexer 513 are coupled to the output of the adaptive sampler 503. By this arrangement, when the receiver 500 is in the normal mode, the data sign values 216 generated by the data sampler 501 are provided to the data sign input of the adaptive module 505, and the error sign values 218 generated by the adaptive sampler 503 are provided to the error sign input of the adaptive module 505. Conversely, in the proxy mode, the data sign values generated by the adaptive sampler 503 are provided to the data sign input of the adaptive module 505 and the error sign values generated by the data sampler 501 are provided to the error sign input of the adaptive module 505.
In many applications, once the data level threshold, DLEV, has converged to the target level, the data level threshold changes relatively slowly, for example, in response to voltage and temperature drift. Consequently, the stream of error sign values delivered to the adaptive module 505 may be temporarily interrupted without significant adverse impact on the receiver 500 or the signaling system as a whole. By contrast, if the stream of data sign values is interrupted, the communication link (e.g., over signaling path 202) is lost for the duration of the interruption. By placing the receiver 500 in proxy mode, and thereby swapping the roles of the data and adaptive samplers 501 and 503, the data sampler 501 may be temporarily removed from service without interrupting data reception. In one embodiment, for example, an offset calibration operation is performed by switching the receiver 500 to proxy mode (i.e., asserting the proxy enable signal 516); temporarily zeroing the data level threshold, DLEV; switchably coupling the differential inputs of the data sampler 501 to one another (and switchably isolating the inputs from the signal path 202 so as not to short the component signal lines of the signal path to one another); then adjusting the OFSTD value until the sample value generated by the data sampler 501 begins to dither between '1' and '0' states. The dithering sample value indicates that the null signal input to the data sampler 501 is being detected and therefore that the offset calibration is complete. After completing the offset calibration for the data sampler 501, the control setting for the data level threshold is restored, and the proxy-enable signal 516 is lowered to re-establish the normal operating mode of the receiver 500. At this point, the data sampler 501 has been removed from service for calibration purposes, then restored to service without interruption in data reception.
Still referring to
A number of changes may be made to the embodiment of
Tap Weight and Data Level Adaptation in a Multi-Level Signaling System
In the embodiment of
As in the transmit circuit of
In one embodiment, each of the component output drivers 575, 577 and 579 is implemented by the circuit illustrated in
Referring again to
Referring to
Returning to
Still referring to
As discussed in reference to
As in the embodiment of
In the embodiment of
In the embodiment of
In one embodiment, offset cancellation operations are performed for the remaining samplers (i.e., the positive and negative LSB samplers and the adaptive sampler) in generally the same manner as the MSB sampler, except that the threshold control values provided to the sampler being calibrated are temporarily zeroed to enable detection of the DC offset, if any, then restored when the offset calibration operation is complete. Also, in the case of the positive LSB sampler, a logic '1' LSB indicates a negative L+sample, and a logic '0' LSB indicates a positive L+sample; a correlation that is the complement of the MSB case (i.e., in which a logic '1' MSB corresponds to a positive MSB sample). Inverter 622 is provided to account for this complement condition, causing the offset counter 615 to be incremented in response to a logic '0' L+ sample during calibration of the positive LSB sampler.
Clock Recovery
The clock recovery circuit 645 generates a sampling clock signal 210 (SCLK) and edge clock signal 610 (ECLK) in response to transition samples 644 (Tn−1), generated by the edge sampler 641, and the data samples 642 generated by the multi-level sampler 541. In one embodiment, the sampling clock signal 210 is provided to the multi-level sampler 541 and adaptive sampler 543 to control the sampling instant therein (as shown, for example, in FIGS. 10 and 12) and thereby define each successive data reception interval. In one embodiment, transitions in the sampling clock signal 210 are phase aligned with midpoints in the incoming data eyes (i.e., midpoint of data valid intervals in the incoming data signal, x′n), for example, as shown in
The clock recovery circuit 645 adjusts the phase of the edge clock signal 610 to maintain phase alignment between the edge clock signal 610 and transition points between incoming data eyes. That is, the edge clock signal 610 is adjusted for edge alignment with data valid intervals in the incoming data signal, x′n. The edge clock signal 610 is supplied to the edge sampler 641 where it is used to time the sampling of transitions in the incoming data signal. One or more storage circuits (not specifically shown in
In the embodiment of
In one embodiment, the early/late counter 683 is initialized to zero and, as illustrated in Table 5, is incremented in response to an early indication (i.e., a logic high early/late signal 674) and decremented in response to a late indication (i.e., a logic low early/late signal 674). By this operation, the sign bit (e.g., the MSB) of the early/late count maintained within the early/late counter 683 indicates whether more early than late indications, or more late than early indications have been received from the transition logic 671 (i.e., the count value will underflow to a negative value if more late indications than early indications are detected). Accordingly, after a predetermined number of transition detect assertions (or after a predetermined time), the majority detector 685 evaluates the sign of the early/late count (i.e., signal 684) and outputs an up/down signal 688 to the interpolator 687 accordingly. The early/late count value may then be reset to zero in preparation for counting a subsequent set of early/late indications.
In one embodiment, the interpolator 687 maintains an interpolation control word that is incremented in response to a logic high up/down signal 688 and decremented in response to a logic low up/down signal 688. The most significant bits of the interpolation control word are used to select a pair of phase vectors from the set of N phase vectors 692 generated by the reference loop 689, and the least significant bits of the interpolation control word are used to interpolate between the selected pair of phase vectors. As the control word is incremented, the interpolation is incrementally shifted from a leading one of the phase vectors to a lagging one of the phase vectors, thereby incrementally delaying (i.e., retarding) the phase of the edge and sampling clock signals 610, 210. Conversely, as the control word is decremented, the interpolation is incrementally shifted toward the leading one of the selected phase vectors, thereby incrementally advancing the phase of the edge and sampling clock signals 610, 210.
In one embodiment, the reference loop 689 is formed by a delay locked loop (DLL) that receives a reference clock signal 690 and, in response, generates a plurality of phase vectors 692 that are phase distributed within a cycle time of the reference clock signal 690. Alternatively, the reference loop 689 may be a phase locked loop (PLL) that multiplies the reference clock frequency to generate a plurality of phase vectors 692 having a higher frequency than the reference clock frequency. In another alternative embodiment, the reference loop 689 may include an internal timing reference generator (e.g., a ring oscillator or other clock generating circuit) so that no reference clock signal 690 is required. Also, as discussed above, the interpolator 687 may generate any number of sampling clock and edge clock signals. For example, in a double data rate system, the interpolator 687 generates an edge clock signal and complement edge clock signal, and a sampling clock signal and complement sampling clock signal, the sampling clock signal being offset from the edge clock signal by a quarter cycle (90 degrees) of the edge clock signal. The quarter cycle offset may be achieved, for example, by a second interpolator that maintains a control word having a 90 degree digital offset from the control word used to generate the edge clock signal. Other techniques may be used to generate the edge clock-to-sampling clock offset in alternative embodiments. In a quad data rate system, the interpolator 687 (or multiple interpolators) generates four edge clock signals and four sampling clock signals, the combined set of eight clock signals being evenly offset in phase over a cycle time of the edge clock signal (i.e., 45 degree increments between successive clock edges). This approach may be extended to support virtually any data rate.
It should be noted that numerous changes may be made to the clock recovery circuit 670 of
Returning to
Returning to
In the embodiment of
Transmit equalization can cause multi-modal distributions in edge crossings. This in turn causes the conventional clock-data-recovery loop to produce less accurate estimates on the phase of the incoming data stream. In one embodiment, error signals at both data and edge samples are combined to form the update of the equalizer taps, thereby reducing loss of timing accuracy in effect by trading off between timing accuracy and voltage accuracy due to equalizer compensation. The use of data and edge error signals to update equalizer taps are illustrated, for example and without limitation, by the update expression:
The term including the error from the data samples guides the equalizer updates toward the negative gradient direction of the mean-square-error on data samples, while the term including the error from edge samples guides the equalizer updates toward the negative gradient direction of the mean-square-error on edge samples. Said differently, the term including error in data samples affects the equalizer such that it makes that error smaller, while the term including error in edge samples affects the equalizer such that it makes the error at the edges smaller. In case when there are competing effects between these two errors, the equalizer is able to achieve the balance. This tradeoff may be achieved with different relative magnitude of step sizes (weighting) for data and edge errors.
A convenient aspect of the embodiments of FIGS. 23 (and 26 described below) is that the clock recovery loop already generates the edge error signals and conveniently filters them (i.e. generates them) only on valid transitions (i.e., by detecting early-late signals as discussed above). Hence, little or no additional circuitry in the receiver is needed to generate the edge error signals.
In the embodiment of
In one embodiment, the odd and even adaptive-sampler clock signals are generated by respective interpolators within the clock recovery circuit 707, and therefore have independently selectable phase offsets. By this arrangement, clock signal CLK_AO may be selectively phase aligned with either of the odd-phase data and edge clock signals, CLK_DO and CLK_EO, so that adaptive sampler 703, may proxy for any of the component samplers within the odd-phase 4-PAM data sampler 7031, and any of the component samplers within the odd-phase 4-PAM edge sampler 7032. Similarly, clock signal CLK_AE may be selectively phase aligned with either of the even-phase data and edge clock signals, CLK_DE and CLK_EE, so that adaptive sampler 7032 may proxy for any of the component samplers within the even-phase 4-PAM data sampler 7033, and any of the component samplers within the even-phase 4-PAM edge sampler 7034. In alternative embodiments, each of the adaptive samplers may proxy for any component sampler within any of the 4-PAM samplers. By this arrangement, one of the adaptive samplers 703 may continue to generate the error samples needed to adaptively update the pre-emphasis tap weights, W N+1, and the thresholds T_AO and T_AE (and, by extension, the T+ and T− thresholds), while the other of the adaptive samplers 703 is used as a proxy sampler for a component sampler of one of the 4-PAM samplers 701. The adaptive module 705 additionally generates an offset cancellation value for each of the adaptive samplers 703 (i.e., OFST_AO and OFST_AE), for example, by nulling the input to the adaptive sampler, zeroing the threshold of the adaptive sampler, and adjusting the offset cancellation value for the adaptive sampler until the error samples generated by the adaptive sampler begin to dither.
Referring to 4-PAM sampler 701 1, threshold multiplexer 725 is provided to select either the T+ threshold or the adaptive sampler threshold, T_AO, to be summed with the offset cancellation OFSC_DO[2] and provided to the positive LSB sampler 561. Similarly, threshold multiplexer 729 is provided to select either the T− threshold or the adaptive sampler threshold, T_AO, to be summed with offset cancellation OFSC_DO[0] and provided to the negative LSB sampler 565, and threshold multiplexer 727 is provided to select either the zero threshold or the adaptive sampler threshold T_AO, to be summed with offset cancellation OFSC_DO[1] and provided to the MSB sampler 563. Output multiplexers 735, 737 and 739 are provided in the 4-PAM sampler 701 1 to select either the output of the odd-phase adaptive sampler 703 1 or the output of the component samplers 561, 563 and 565, respectively, to be provided to the data/edge sample deserializer 704. Threshold multiplexers 725, 727 and 729, and output multiplexers 735, 737 and 739 are provided within the odd-phase edge sampler 701 2 and coupled to the component samplers thereof in the same way that like-numbered multiplexers are coupled to the component samplers of the odd-phase data sampler 701 1.
Threshold multiplexer 730 is provided to enable any of the T+, 0, T− and T_AO threshold levels to be summed with offset cancellation OFSC_AO and provided to the adaptive sampler 543 (i.e., sampler 543 being the sampling circuit within the overall sampler 703 1). Output path multiplexer 731 is provided to select the output of any one of the component samplers of 4-PAM samplers 701 1 and 701 2 or the adaptive sampler 543 to be provided to the error sample deserializer 709. By this arrangement, the adaptive sampler 543 may operate as a proxy sampler for any of the component samplers of the odd-phase data and edge samplers 701 1 and 701 2, and vice-versa, thereby enabling calibration operations or other out-of-service operations to be performed on the odd-phase data and edge samplers without interrupting the recovered stream of data and edge samples. As discussed in reference to
Still referring to
As discussed in reference to
In another alternative embodiment, the +1 and +1/3 signal levels (and/or −1 and 1/3 signal levels) may be determined using the LSB edge samplers (or MSB edge sampler), then averaged to determine the T+ threshold. Referring to
As discussed above, the T+ and T− thresholds may also be adaptively determined based on transitions (i.e., edge samples) between +1 and +1/3 signal levels. Referring to
In one embodiment of the multi-sample receiver 700 of
As discussed above in reference to
In one embodiment, the at-threshold offset cancellation operation of
The operations illustrated in
In an alternative embodiment at-threshold offset cancellation is performed in each positive LSB edge sampler by detecting +1 to +1/3 signal level transitions (i.e., MSBn=MSBn+1=1 and LSBn xor LSBn+1=1 as shown in
Dual Mode, Multi-PAM Receiver
In one embodiment, the 4-PAM sampler illustrated in
When the live enable signal 742 is deasserted, a batch update mode is selected, and the sign of the originally transmitted data value, xn, is used to select either the positive LSB sampler 561 or negative LSB sampler 565 to provide the error sample 744 to the adaptive module. As discussed above, in batch mode, the sign of the transmitted data value may be known at the receive-side IC device, for example, by sending the data transmission sequence in advance of the batch update operation, or by storing the transmit data pattern in both the transmit- and receive-side devices. In either case, the error sign values generated by the positive and negative LSB samplers 561 and 565 may be applied in the same manner as in the live adaptation mode to adapt the T+ and T− thresholds to the upper and lower binary signal levels, and to update the pre-emphasis tap weights.
Alternative Indicator Functions
In the signaling system embodiments described above, error samples generated by an adaptive sampler within a multi-sample receiver are applied to update transmit pre-emphasis tap weights in repeated sign-sign LMS update operations. Because the adaptive sampler generates errors with respect to an expected data level, logical filtering of data is used to ensure that the incoming signal in fact corresponds to the expected data level. For example, in a binary signaling embodiment in which the adaptive sampler receives a target data level threshold that corresponds to a logic '1' data transmission, the error sample generated by the adaptive sampler is applied in a tap weight update if the corresponding data sample is a logic '1'. Similarly, in a multi-PAM signaling embodiment, the error sample is applied in a tap weight update operation if the corresponding data sample corresponds to the adaptive sampler threshold level (e.g., +1/3 the normalized signal level in the embodiment of
In another alternative embodiment, a trap indicator function is used to filter errors applied in tap weight update operations (i.e., update-triggering errors) according to the error magnitude and direction. Referring to the normalized 2-PAM data eye 751 illustrated in
In one embodiment, the adaptive module 753 adaptively adjusts the trap threshold to obtain a target count of update-triggering errors per unit time, referred to herein as the target error count. The target error count may be a predetermined value that is programmed within the receive-side IC device (or transmit-side IC device) during run-time configuration or during a production-time programming operation (e.g., fuse blowing operation, or storage in a nonvolatile memory), or hardwired within the receive-side IC device (or transmit-side IC device). In one embodiment, the target error count is initially set to a relatively high number so that the adaptive module 753 drives the trap threshold higher (thereby increasing the number of incoming signals that fall within the trap zone) and the trap threshold quickly converges to a stable level. After the trap threshold has converged, the target error count is lowered (e.g., one time or iteratively) so that fewer errors, having more substantial offset from the normalized +1 signal level, are counted as errors. The error samples (i.e., sgn(x′n−TTRP)) are applied within the adaptive module 753 along with data sign values generated by the data sampler 211 in tap weight update operations.
In one embodiment, illustrated in
System with Adaptive Transmit Pre-Emphasis and Selectable-Tap DFE
While the multi-tap transmitter 201 of
The equalizing receiver 761 additionally includes a selectable-tap decision-feedback equalizer 764 (DFE) that generates an equalizing signal 767 based on selected prior decisions of the data sampler and a set of tap weight values. In the embodiment of
In the embodiment of
The tap selector 769 includes a tap control circuit 771 and a select circuit 770 that cooperate to select a subset, M, of the N storage elements within the shift register to source data samples to the equalizing driver bank. The selected storage elements are referred to herein as tap data sources and the values stored therein as tap data values. The equalizing driver bank 765 generates the equalizing signal 767 in accordance with the tap data values delivered by the tap selector and a corresponding set of tap weights referred to herein as receive equalization tap weights (REW(1)-REW(M)). By identifying the shift register storage elements having sample latencies that correspond to the propagation latencies of reflections and other distortions, then selecting only the identified shift register storage elements as tap data sources, a relatively small number of tap data sources may be selected to form receive-side equalization taps (i.e., contributors to the equalizing signal 767). That is, even though a relatively large range of sample latencies are represented by the contents of the shift register 768, only those shift register storage elements containing data samples whose corresponding signal transmission produced the reflections arriving at the receiver input in the present reception interval need be selected to source tap data values. By selecting a relatively small number of tap data sources relative to the overall number of selectable tap data sources, high latency distortions may be reduced using only a relatively small number of equalizer taps and therefore without unduly increasing the parasitic capacitance of the equalizing receiver 761.
In the embodiment of
Still referring to
Distribution of Equalization Functions; Dead Range Assignment
In one embodiment, the functions of mitigating low-latency and high-latency distortions are distributed between the equalizing transmitter 201 and equalizing receiver 761, with transmit pre-emphasis being applied within the transmitter 201 to reduce low-latency distortions (e.g., dispersion-type ISI) and decision-feedback equalization being applied within the receiver 761 to reduce high-latency distortions (e.g., reflection-type ISI). The distribution of low- and high-latency equalization functions between the transmitter 201 and receiver 761 is achieved, in part, through definition of a dead range within the shift register 768. That is, storage elements within the shift register 768 that have sample latencies lower than a predetermined number of symbol times, U, are excluded from the range of selectable tap data sources, effectively establishing the sample latency of the lowest-latency selectable tap data source at U+1. In one embodiment, U is set according to the number of post-tap drivers, V, within the equalizing transmitter to prevent interference between transmit-side and receive-side equalization. That is, transmit pre-emphasis is applied within the equalizing transmitter 201 to reduce distortions resulting from symbol transmissions up to U symbol times prior to transmission of the primary output signal, and decision-feedback equalization is applied within the equalizing receiver 761 to reduce distortions resulting from symbol transmissions more than U symbol times prior to transmission of the primary output signal. For example, if four post-tap drivers are provided in the equalizing driver 201 such that U=V=4, then the lowest latency value within the selectable range, N, of stored data values is U+1=5 symbol times, and the equalizing receiver 761 is said to have a dead range of four symbol times. In the embodiment of
The ability to control tap data source latencies with the tap selector 769 of
Tap Data Source Selection and Tap Weight Determination
Still referring to
In another embodiment, run-time embedded scoping or production-time testing is used to determine tap data source selection and, optionally, an initial setting of receive equalization tap weights and/or transmit pre-emphasis weights), with transmit-side and receive-side equalization tap weights being adaptively updated thereafter. In yet other embodiments, receive-side tap data sources are selected in a tap search operation that does not require transmission of test waveforms or otherwise interrupt transmission of live data (i.e., live data transmission may continue during the tap search operation). An initial set of receive equalization tap weights may be determined during the tap search operation, then adaptively updated after the tap search operation is completed.
Tap Data Source Selection and Tap Weight Determination—Embedded Scoping
As discussed above, embedded scoping may be used to trace the system response to a test waveform and thereby enable determination of the latency, amplitude and polarity of various signal path distortions. The latency of a given distortion, once determined, may be used to select one or more tap data sources having corresponding sample latencies, and the amplitude and polarity of the distortion used to determine the tap weight (i.e., sign and magnitude of the tap weight) to be applied to the corresponding tap data value for generation of an equalizing signal contribution. Also, the latency of a given distortion may be used to determine whether to counteract the distortion through transmit pre-emphasis or receive-side equalization (or both), and the overall range of latencies for detected distortions may be used to determine an appropriate dead range for the receive-side equalizer.
Embedded scoping involves repeated transmission of a sequence of data values, generation of a corresponding sequence of receive-side data samples for each repeated transmission (i.e., by capturing the transmitted sequence at the receiver), and comparison of each data sample sequence with a known-valid copy of the transmitted sequence of data values to confirm error-free sample generation. With each receive-and-confirm iteration, the decision threshold (e.g., a voltage level or difference between voltage levels) used to used to resolve the data sample state is offset from a nominal or calibrated level by a progressively larger amount until a symbol in the sequence no longer matches the expected value. The offset in the decision threshold at which the failure occurs is referred to herein as a pass/fail offset and represents a measure of the signal level at the sampling instant at which the failure occurred. Thus, by sweeping the decision threshold through a range of thresholds until the pass/fail offsets for each symbol in the symbol sequence have been detected, a sample plot for the incoming signal may be developed. Further, by sweeping the sampling clock signal through an incremental sequence of phase offsets, and determining the pass/fail offset at each phase offset, a complete trace of the incoming signal may be generated. Also, the granularity and start stop points of the phase offsets and/or threshold steps (e.g., steps in voltage or current) may be controlled (e.g., by configuring a programmable circuit or register) to enable the waveform trace to be constrained to selected points of interest in the incoming signal (e.g., �N� from an intended sampling instant, N representing a sweep angle).
Still referring to
Embedded scoping has a number of benefits over traditional signal measurement techniques. First, because the technique is non-invasive (i.e., no probe contact), the electrical characteristics of the system under test are unaltered, thereby yielding potentially more accurate measurement results. Also, the trace is generated from the perspective of the receive circuit itself, meaning that any non-ideal characteristics of the receive circuit are accounted for in the resulting signal trace information. Finally, because all components needed for embedded scoping may be included within a finished signaling system, embedded scoping may be used to perform numerous run-time analyses, including determining the latency and amplitude of reflections and other distortions within the signaling system.
The receive device 809 includes an equalizing receiver 810 to sample the incoming data signal, a pattern register 811 to store a local version of the data samples captured in response to the incoming data signal, a multiplexer 812 to enable the pattern register 811 to be switched between load and barrel-shifting modes, a XOR gate 813 to compare the stored data sample sequence with subsequently generated data sample sequences, and application logic 815 (or other logic) to generate a clock adjust signal (CLK ADJ) and decision threshold adjust signal (THRESH ADJ) to sweep the sampling clock signal and decision thresholds used within the equalizing receiver 810 through their scoping ranges. The application logic 815 additionally builds a trace record (i.e., data indicative of the waveform produced on the signaling path 202 in response to transmission of the test data pattern) based on the output of XOR gate 813.
When the receive device 809 is in a scoping mode of operation, the multiplexer 812 is initially set to load the pattern register 811 with the output of the equalizing receiver 810. After a desired sequence of data samples (e.g., a pulse data pattern such as 00010000000000000) is shifted into the pattern register 811, the multiplexer 812 is set to enable the barrel-shifting mode of the pattern register 811. That is, the multiplexer 812 selects the output of the pattern register 811 to be fed back to the input of the pattern register 811 so that the contents of the pattern register 811 are continuously rotated through the pattern register 811 (i.e., a barrel shifting operation). By this arrangement, the sequence of data samples loaded into the pattern register 811 is repeatedly output, bit by bit, to a first input of the XOR gate 813. The data sample sequence received by the equalizing receiver 810 is input to a second input of the XOR gate 813 so that the received sample sequence is compared, bit by bit, with the sample sequence stored within the pattern register 811. By selecting the length of the repeatedly transmitted sequence of data values to match the storage size of the pattern register 811, the pattern register contents are repeatedly compared with a newly received version of the same data sample sequence (i.e., putatively the same sequence of data samples) to establish iterative receive-and-confirm operation. Any sampling error will result in a mismatch between the sampled data value and the corresponding value within the pattern register and therefore, when compared by XOR gate 813, will result in an error signal being output from the XOR gate 813 to the application logic 815. The application logic 815 may then record the threshold offset and clock phase offset at which the error occurred to a signal level for a timing offset within a waveform trace.
In one embodiment, the tap data source selection and receive equalizer tap weight values determined in the embedded-scoping operation are not further adjusted, or are adapted occasionally in offline calibration operations. In an alternative embodiment, indicated in
The transmit pre-emphasis update logic 256 includes a data sign register 251 and sign multiplier 257 (the sign multiplier itself including exclusive NOR gates 258 1-258 v) which operate generally as described above in reference to
The receive equalizer update logic 856 includes a sign multiplier 857, filter 862 and receive equalization tap weight counters 864 1-864 M. The sign multiplier 857 includes a bank of M exclusive NOR gates, 858 1-858 M, each coupled to receive the error sample stored within register 253 and a respective one of the M tap data values 870 (i.e., TD1-TDM) selected by the tap selector 769 of
As in the adaptive module of
Still referring to
Tap Search Operations
The tap selector 769 includes a select circuit 770 and tap control circuit 771. In one embodiment, the select circuit 770 includes a switch matrix formed by column lines 905 and row lines 908, the row lines being referred to herein as tap data lines. Each storage element within the shift register 768 (i.e., each tap data source) is coupled to a respective one of column lines 905, and each of the tap data lines 908 is coupled to provide a corresponding one of tap data values TD1-TDM to the tap data input of a respective one of the equalizing drivers 766 1-766 M. As discussed above, the tap data lines 908 may additionally be coupled to the adaptive module of
In one embodiment, switch element 907 is formed by a transistor 909 having source and drain terminals coupled between tap data line 908 j and column line 905 i as shown at 904. The gate terminal of transistor 909 is coupled, accordingly, to receive the jth component signal of enable signal 906 i (i.e., Ei[j]) so that when the Ei[j] is high (i.e., indicating that jth tap data output is to be sourced by the data value at the ith position within the shift register 768), transistor 909 is switched on to couple the selected tap data source to the tap data output. Other types of switching elements may be used in place of transistor 909 in alternative embodiments.
Still referring to
In the embodiment of
After initializing the various registers (i.e., TSI register, MTW register 935 and tap weight registers 915 1-915 M) and loop indices, the tap search logic 911 outputs an adjust signal (i.e., a component signal of control signal Cj) in either a count-up or count-down state to tap weight register 915 j according to the state of the corresponding receive equalization update signal, REUD[j], and asserts the command strobe signal 912 in response to the UREW signal 852. By this tap weight register 915 j is adaptively updated, while the remaining tap weight registers 915 are held constant. The tap search logic 911 monitors the control signal used to increment and decrement the tap weight in register 915 j to determine when the tap weight has converged to a stable level (e.g., tap weight begins to dither within a predetermined number of increment/decrement steps), then compares the tap weight with the value of the MTW register 935. If the tap weight is greater than the value stored within the max tap weight register, the tap weight is transferred from tap weight register 915 j to the MTW register 935 to establish an updated maximum tap weight. In one embodiment, rather than provide tap weight transfer paths from the tap weight registers 915 1-915 M to the MTW register 935, a temporary weight register within the tap search logic 911 is used to track the value generated within the selected tap weight register 915 j, thus simplifying determination of whether the content of the tap weight value in register 915 j is greater than the value in the MTW register 935 (i.e., the temporary register content and MTW register 935 content may be compared) and, if necessary, transfer of a new maximum tap weight into the MTW register 935. In an alternative embodiment, a multiplexer may be used to select a tap weight from one of registers 915 1-915 M (i.e., from tap weight register 915 j) to be provided to the tap search logic 911 for comparison with (and to overwrite, if necessary) the content of the MTW register 935. In either case, if the MTW register 935 is loaded with a new maximum tap weight value, the TSI register is loaded with the corresponding tap data source index, i. By this operation, after tap data source index i has been stepped through the range of tap data sources for a given equalizer tap j, the TSI register contains an index to the tap data source that yielded the maximum tap weight. Consequently, the content of the TSI register is loaded into the search result buffer at the conclusion of the tap search for the jth equalizer tap and thereafter used to generate select signal Sj. Also, the maximum tap weight value in the MTW register 935 may be loaded into the tap weight register 915 j to establish an initial tap weight setting for the jth equalizer tap. Thereafter, the equalizer tap index j is incremented to select the next equalizer tap, and the MTW register 935, TSI register and tap data source index, i, are reset in preparation for another tap search operation. After tap data sources have been selected for all the equalizer taps, the tap search operation is completed, and the tap search logic 911 begins updating all the tap weight registers 915 1-915 M in response to the UREW signal 852 and according to respective receive equalization update values 860.
In one embodiment, the tap search logic 911 executes the above-described tap search during system initialization, for example, in response to assertion of a reset signal, or in response to an initial assertion of the receive UREW signal 852. Also, the tap search logic 911 may output a search-complete signal to the adaptive module upon completion of the search operation, thereby enabling the adaptive module to resume adaptation of the transmit pre-emphasis tap weights and data level threshold. Alternatively, application logic within the device containing the equalizing receiver may issue control signals to the adaptive module and the tap search logic 911 to time the sequence of configuration events, including enabling and disabling adaptation of the transmit pre-emphasis tap weights and data level threshold, enabling and detecting completion of the tap search operation, and re-enabling adaptation of the transmit pre-emphasis tap weights and data level threshold when the tap search operation is complete.
During a tap search operation, the tap weight registers 931 1-931 M within register bank 930 are initially cleared, effectively disabling the equalizing drivers 766 1-766 M from generating equalizing signal contributions. In one embodiment, the contents of the TW register 937 and tap weight register 931 M are summed in summing circuit 932 to provide a summed tap weight value to equalizing driver 766 M. By this arrangement, and by leaving tap weight register 931 M at zero until the final stage of the overall tap search operation, the TW register 937 is enabled to control the tap weight provided to equalizing driver 766 M during tap search operations (In an alternative embodiment, a multiplexer or other select circuit may be used to select either the TW register 937 or the tap weight register 766 M to drive the equalizing driver 766 M) Thus, following the approach set forth in
In one embodiment, after tap data sources have been selected for all the equalizing drivers 766 1-766 M, no further tap search operations are carried out. In an alternative embodiment, tap search operations may be repeated periodically or in response to detecting selected events (e.g., change in system configuration, operating conditions, threshold error rate). Also, because tap search operations may be performed during live data transmission (i.e., transmission of training sequences or other test data patterns, while possible, is unnecessary for carrying out tap search operations), an extra receive equalizer tap may be provided to enable substantially continuous background tap searching. Referring to
Grouped Tap Data Source Selections
Referring again to
In high-speed signaling systems symbol times are relatively short (often well under a nanosecond) so that reflections tend to disperse over multiple adjacent symbol times. Consequently, in many such systems, there may be one or two dominant reflections (or other distortions) that appear in multiple adjacent symbol times, the adjacent symbol times being referred to herein as a reflection window. Considering the embodiment of
Tap Window Searching
In one embodiment, rather than selecting M individual tap data sources to provide tap data values to the equalizing driver bank, a tap window (or multiple tap windows) formed by a set of M adjacent tap data sources is selected to source tap data values to the equalizing driver bank. In such an embodiment, a single tap window index (TWI) may be generated by the tap search logic and supplied to a tap select decoder to generate a corresponding set of select signals, S1-SM.
Still referring to
Maximum Eye Opening as Criterion for Tap Window Selection
Although signal distortions at different symbol latencies are often independent of one another, distortions themselves may generate reflections. For example, a signal reflection may itself generate a signal reflection, referred to herein as a secondary reflection, that arrives at the receiver input some number of symbol times after the original, primary reflection. In the context of decision-feedback equalization, a tap data source selection and corresponding tap weight that cancels a primary reflection may also cancel the secondary reflection even though no equalizer tap is assigned a tap data source having a sample latency that corresponds to the secondary reflection. This phenomenon presents a challenge for tap window selection as an equalizer tap selected to cancel a primary reflection may incidentally cancel a secondary reflection, thus providing a distortion mitigating benefit that is not reflected by the equalizer tap weight alone. That is, the distortion-mitigating value of a given tap window selection may not be accurately represented by the corresponding maximum aggregate weight. More specifically, a first tap window selection that results in cancellation of a primary reflection of magnitude X as well as cancellation of a secondary reflection having magnitude Y, will yield an aggregate weight that corresponds to X only, not X+Y as is actually achieved. Thus, if a second tap window selection yields an aggregate weight that exceeds X, but is less than X+Y, the second tap window may be selected as the final tap window on the basis of the higher aggregate weight even though it provides less distortion mitigation than the first tap window. In alternative embodiments, discussed below, metrics other than aggregate tap weight are used to reduce the possibility for non-optimal tap window selection.
Maximum Eye Opening as Criterion for Tap Window Selection
In alternative tap window search operations, data and error samples generated by the samplers 211 and 213 of
In one embodiment, error samples are resolved to either a logic '1' or logic '0' state according to whether the data level threshold compared with the incoming signal exceeds or is less than the incoming signal, respectively. Thus, as shown in
In one embodiment, the foregoing characteristics of the error and data sample generation are used to search for the upper and lower error boundaries and thereby obtain a measure of the data eye height for a given tap window selection. More specifically, by stepping the data level threshold from a value known to be inside the error boundary toward an incrementally more positive value, a relative value of the error boundary itself may be determined by inspecting an exclusive-OR combination of data and error samples at each step and identifying the data level threshold at which the incoming signal yields a sample lower than the data level threshold (i.e., exclusive-OR result is zero).
In an alternative embodiment, illustrated in
In yet another embodiment, an eye height measurement is initiated at each phase offset, then aborted upon determining that the eye height is nonzero or greater than a predetermined value. The positive and negative phase offsets at which zero eye height (or eye heights less than the predetermined value) are detected are used as a measure of the eye width. For example in
Referring to
At block 1104 of
At block 1107 of
After the upper error boundary has been bound in the data level search at block 1109, the FSM 1060 initializes internal state variables in preparation for a search for the lower error boundary. Thus, at block 1114 of
Returning to decision block 1121, if the eye height is not positive, the FSM 1060 concludes that an edge of the data eye has been reached. If the phase control increment is positive (e.g., determined at decision block 1127), then only the rightmost portion of the data eye has been searched (i.e., the phase offset has been stepped to more latent offsets, ending at the rightmost edge of the data eye) and, at block 1129, the FSM 1060 changes the phase control increment to a negative value, sets the phase control offset to the value of the phase control increment (i.e., establishing an initial step into the leftmost portion of the data eye) then repeats the operations starting at block 1107 to generate and accumulate eye height measurements for the left most portion of the data eye. When decision block 1127 is reached with a negative phase control increment, the entire data eye has been measured so that the value within the accumulator 1063 reflects a complete measured eye area for the current tap window. Accordingly, at decision block 1143, the measured eye area is compared with the maximum eye area value within the ME register 1061 to determine whether a new maximum eye area has been found. In the embodiment of
In alternative embodiments, rather than comparing eye areas, eye height measurements may be made for each tap window selection and compared to determine which tap window selection yielded the maximum eye height. Also, eye widths may be measured for each tap window selection and compared to determine which tap window selection yields the maximum eye width. In any case, the tap window selection yielding the maximum metric may be selected to source equalizer taps within the selectable-tap decision-feedback equalizer.
Equalizing Circuits
As discussed above in reference to
In one embodiment, the equalizing output driver 1240 of
Equalizing circuit 1290 includes a differential amplifier 1294 formed by differential transistor pair 1291, biasing current source 1292 and resistive loads 1293. Differential input signals are supplied to gate terminals of transistor pair 1291 such that differentially amplified output signals are generated on output lines POUT and /POUT. In one embodiment, output lines POUT and /POUT are coupled to input terminals of a differential amplifier within a sampling circuit so that amplifier 1294 effectively forms a first stage in a two-stage amplifier (i.e., amplifier 1294 is a preamplifier).
Equalizing circuit 1290 additionally includes a level shifting circuit 1296 coupled to the differential amplifier 1294 to provide preamplifier equalization. The level shifting circuit 1296 includes a pair of sub-circuits 1298 1 and 1298 2 each coupled between a respective one of the differential amplifier outputs (POUT and /POUT) and a clocking transistor 1299. Each of the signal sub-circuits 1298 includes a respective plurality of tap data transistors (1295 1-1295 N and 1297 1-1297 N) coupled in parallel between the differential amplifier output and the clocking transistor 1299. The control terminals of the tap data transistors 1295 1-1295 N are coupled to receive the selected tap data values, EQD1-EQDN, respectively, and the control terminals of the tap data transistors 1297 1-1297 N are similarly coupled to receive complement versions of the selected tap data values, /EQD1−/EQDN. In one embodiment, each of the tap data transistors 1295 is sized (e.g., by width-length ratio) to achieve a respective tap weight EQWN-EQW1. By this arrangement, each tap data value may be coupled to the control terminal of a selected one of the tap data transistors 1295 according to the desired tap weight. The transistors 1297 are similarly weighted and therefore allow coupling of the complement tap data values according to desired tap weights. The weights of the individual tap data transistors 1295 (and 1297) may be incrementally related (i.e., EQW1=EQW2+K=EQW3+2K . . . , where K is a constant), exponentially related (i.e., EQW1=EQW2*K=EQW3*K2 . . . ) or may have any other desired relationship (including having the same weight values or including subsets of weight values that are the same).
The clocking transistor 1299 is switched on during every other half cycle of the equalizer clock signal to enable the operation of the sub-circuits 1298. The sub-circuits 1298 operate to increase or decrease the difference between the preamplified output signals (or even change the polarity of the difference) by drawing more current from one of the preamplifier output lines (POUT or /POUT) than the other in accordance with the selected tap data values. Thus, the sub-circuits 1298 act to differentially shift the level of the preamplified output signal generated by differential amplifier 1294. An additional instance of the equalizing circuit 1290 may be provided to enable preamplifier equalization during the alternate half cycle of the equalizer clock signal.
The level shifting circuit 1330 is similar to the circuit 1296 of
In one embodiment, the equalizer clock is phase advanced relative to the sampling clock signal such that transistors 1337 and 1339 are switched on in advance of clocking transistor 1341. By this arrangement, transistors 1333 and 1337 are poised to shift the level of the sampling circuit input nodes, SIN and /SIN, when the sampling clock signal goes high. Thus, when the sampling clock signal goes high, sampling circuit input nodes SIN and /SIN are differentially discharged according to the tap data values EQD1-EQDN, /EQD1-/EQDN and the respective weights of transistors 1333 and 1337. Consequently, the signal levels at the input nodes, SIN and /SIN, of sampling circuit 1328 are differentially shifted by the level shifting circuit 1330 to reduce static offsets in the incoming data signal (applied to control terminals of differential pair 1329) caused by reflections or other distortions.
Adaptation in System with Occasional Non-Random Data
In the signaling environments described above, equalization settings, decision thresholds and other time-varying signaling controls may be continuously adapted by measuring the distribution of received signal levels over a relatively long period of time. Such operation effectively averages error data over an extended time interval to estimate the channel frequency response and to estimate the error due to ISI. Because such continual adaptation, in effect, assumes that the incoming signal carries all possible frequency content and ISI patterns, any periodic, repeated data patterns that lack a portion of the possible frequency content or ISI patterns may bias or distort equalization settings. For example, in some systems, a predetermined data pattern may be repeatedly transmitted during idle periods. If the predetermined data pattern lacks a portion of the possible frequency content or ISI patterns that may otherwise appear during random data transmission (a likely circumstance in the case of repeated transmission of the same N-bit data word), a continuous-adaptation signaling system may adapt non-optimal equalizer settings that correspond to the limited frequency content or ISI patterns of the predetermined data pattern, giving rise to the possibility of bit errors when the idle period ends and transmission of full-spectrum data begins.
If the data is determined not to meet the randomness criteria at decision block 1377, then adaptive update is inhibited at 1379 or, alternatively, the incoming data is omitted from the update data set. By this operation, adaptive update of tap weights, decision thresholds, offsets and so forth may be inhibited upon detection that incoming data does not meet a predetermined randomness criteria, thereby preventing such adaptively generated values from drifting toward non-ideal settings during idle periods or other periods of repeated data transmission. The determination of whether the data meets the randomness criteria may be performed in a number of ways including, without limitation, determining that the randomness criteria is not met if the incoming data matches one or more predetermined bit patterns (e.g., a predetermined control code or a predetermined data value such as stream of zero-valued symbols or a stream of one-valued symbols), or determining whether a statistical measure of auto-correlation (or any other measure of randomness or non-randomness) within the incoming data exceeds a predetermined threshold. Accordingly, the evaluation of the incoming data at block 1375 may include decoding one or more encoded data words formed by the incoming data to determine if the encoded data words correspond to predetermined control values or predetermined data values, or generating the statistical measure of auto-correlation (or any other measure of randomness or non-randomness).
Deserializing circuits 1403 a and 1403 b, which may be implemented as described in reference to
In the embodiment of
In one embodiment, unused code vectors within the 2N code vector space are used to represent specialized values referred to herein as control values or control characters. Such control values may include, for example and without limitation, framing characters to establish data framing (e.g., indicating the boundary between successive N-bit encoded data words or groups of encoded data words), alignment characters to establish data synchronism between different signaling links (e.g., where multiple receivers 1400 are provided to capture related data), skip characters which may be inserted or removed from the data stream as necessary to provide plesiochronous rate matching, and idle characters to indicate periods of idle data transmission.
The decoder 1407 includes circuitry to determine whether a recovered encoded data word is a control value or data value and, if a control value, asserts a control flag referred to herein as a Z-flag 1412. In one embodiment, illustrated in
In alternative embodiments, rather than selectively inhibit tap weight update based on a per-data-word basis (i.e., inhibiting or not inhibiting according to the state of the Z-flag), multiple encoded data words may be evaluated to determine whether the incoming data meets a randomness criteria. For example, in one embodiment, a window counter is used to determine the control character density for a given interval (or within a given pool of encoded data words) with the incoming set of data words deemed insufficiently random if the control character density exceeds a predetermined threshold. In another embodiment, the Z-flag is monitored to determine whether a threshold number of control characters are received in succession and, if so, a data set including the control characters is deemed insufficiently random. In another embodiment, a statistical measure of the randomness of the data is generated and compared with a threshold.
Still referring to
As discussed above, various different criteria may be applied to determine whether the incoming data meets a randomness criteria. In one embodiment, for example, the update controller 1435 asserts the inhibit signal 1432 each time the Z-flag is raised (e.g., the Z-flag may be used as the inhibit signal, obviating any further inhibit control logic). In another embodiment, the update controller 1435 includes the inhibit logic circuit 1450 shown by way of example in
Still referring to
Other types of inhibit logic circuits may be used to generate the inhibit signal 1432 in alternative embodiments. For example, instead of generating a measure of control character density, the inhibit logic circuit may assert the inhibit signal in response to determining that a threshold number of control characters have been received in succession (or that control characters are received continuously for a predetermined time interval), with the successive-receipt threshold being programmable, for example, to a value of one or more. Also, rather than maintaining a count of Z-flag assertions, separate density count values (or successive-receipt count values) may be maintained for selected control characters and/or data values that are deemed to correspond to idle times or other periods of non-random transmission. Referring to
Returning to
The processor 1409 may be virtually any type of processor including, without limitation, a general purpose processor or special purpose processor (e.g., a microcontroller, digital signal processor (DSP) or the like) and may include an internal program store to store program code that is executed by the processor 1409 to selectively inhibit one or more data snapshots from being used to generate updated tap weights. Alternatively, a separate on-chip or off-chip program store (e.g., a volatile or non-volatile memory, not shown) may be provided and coupled to the processor, for example, via a dedicated or shared bus. The program code stored within the program store may include instructions and/or data that, when executed by the processor 1409, causes the processor 1409 to evaluate the Z-flag 1412 and selectively issue the inhibit signal 1414 as described in reference to
Data Precessing
Data precessing may be used, in addition to or instead of the update-inhibit techniques described in reference to
Still referring to
Section headings have been provided in this detailed description for convenience of reference only, and in no way define, limit, construe or describe the scope or extent of such sections. Also, while the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Referenced by
Legal Events
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text:
MarShon Brooks signs deal to play in Italy next season
Aug 10, 2014, 9:30 PM EDT
MarShon Brooks was a late first round pick in the 2011 draft, and while he showed potential as a scorer with a very bad Nets team in his rookie season, he's bounced around ever since, and hasn't shown the requisite amount of improvement to earn a spot on an NBA roster.
He'll get the chance to showcase what he can do while playing overseas instead.
Brooks signed a deal with Italy's Olimpia Milano for next season, the team announced on Friday (via Sportando.net).
He's largely been an asset that's been passed around over the past couple of years more than anything else. Brooks was traded from the Nets to the Celtics last summer in the deal that sent Paul Pierce and Kevin Garnett to Brooklyn, then was dealt from Boston to Golden State in January as part of a three-team deal with the Heat that sent mostly uninspiring players to each respective team.
Then once more at February's trade deadline, Brooks was traded to the Lakers along with Kent Bazemore in exchange for Steve Blake.
Brooks posted his best numbers since his rookie season while in Los Angeles, and averaged 6.4 points on a career-best 48.9 percent shooting in 12.7 minutes per contest, albeit in just 18 total appearances.
It was reported that Brooks most recently drew interest from the Indiana Pacers in the wake of the injury to Paul George, but obviously that didn't get very far if signing overseas was the eventual decision.
- ahmedovic8 - Aug 10, 2014 at 9:35 PM
I don't understand this. Brooks is a good player and deserves to be in the NBA. His career really boggles my mind.
- ecnuob51 - Aug 10, 2014 at 10:04 PM
He's really talented. Has the potential, but I just blame laziness. I saw him being a very good sixth man, a Jamal Crawford type but I think he got too satisfied with his game and didn't work hard on getting better.
- 00maltliquor - Aug 11, 2014 at 12:18 AM
You ain't lie. The kid definitely belongs in the L but he's been put on teams that don't necessarily need him, thus lowering his value. Don't really need him either in LA but I wish we could have retained his services. Poor guy has had a bad break, and I'm pretty surprised he feels like overseas is his only option right now.
Best of luck to him though. Remember when he was the hot thing his rookie year?
- aldavis4president - Aug 11, 2014 at 12:59 AM
He's a good player, but like someone said earlier, he's lazy. Saw him at warriors practice and dude never seemed break a sweat. He had a spot to win off the bench because warriors couldn't score with our 2nd unit. He reminded me alot of Reggie Williams who also was a warrior, great talent, no work ethic.
- Lujah - Aug 11, 2014 at 8:47 PM
I hope this is not based off of seeing him once.
Also, why would he break a sweat knowing he was never going to get any play time?
- klinickal - Aug 11, 2014 at 5:51 AM
I think Brook's problem is he is too selfish. While he can play he can't play with other people and he is not good enough to be a franchise player. So yes that's his problem. He has a franchise player's attitude with a role player's game.
The funny thing is if he can learn to embrace his role he will become a star.
- rajbais - Aug 11, 2014 at 8:39 AM
This guy really fell to bottom. He was a double figure scorer as a rookie and then couldn't bounce back. What a shame.
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This season's education concerts will occur on Friday, January 23, 2015 at 9:30am and 11:30am!
The highlight of this year's program will be Camille Saint-Saens' Carnival of the Animals featuring pianists Dianna Anderson and Jay Mauchley. Additionally, we will have a narration by Terri Aldrich, the Executive Director of the Minot Area Council of the Arts.
Meet the Minot Symphony Orchestra