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The Top 10 In Action Sports
01Brick By Brick: Camping Lego Style
02Booze and Bikes: 14 Tours That Let Combine Two of the Best Things in the World
03Who Needs Hollywood? These Incredible Videos Were All Filmed on the Simplest Cameras
04Sam Pilgrim vs. The World: The Champion Aiming To Reclaim His Crown In A New Era Of Biking
05Eccentric Adventures Episode 2: Britain's Most Brutal Illegal Event is All About Cheese
06A Journey Into Darkness: We Went Mountain Biking in the Abandoned Mines of Slovenia
07After the Apocalypse: Inside The World's Most Breathtaking Ghost Towns
08Debate: Let's Stop Hating On Parents Who Want To Raise Adventurous Kids
09Guns, Roses, And Eating Insects: Adventure Cycling in Vietnam
10From Intense Trails to Intensive Care: Dicing with Death In a Mountain Biking Paradise
MAMMUT Anniversary Basecamp - The Historic Ascent! NEW EDITED VRSION
A Outdoor video by quattro_media - 4,604 views
200 years ago, on August 3rd 1811, the brothers Johann Rudolf and Hieronymus Meyer from Aargau, Switzerland, climbed the first four-thousand-metre peak in Switzerland, the Jungfrau mountain. 200 years of exciting mountaineering history followed.
Celebrating its 150th anniversary itself, Swiss mountaineering specialist MAMMUT commemorates these extraordinary jubilees by organizing the Anniversary Basecamp and kicking off the Biggest Peak Project in history on August 3rd 2011, exactly 200 years after the first ascent!
The highlight of the camp is the joint ascent to Jungfrau summit (4,158 m). In order to celebrate the anniversaries in an authentic way, one of the teams tackles the climb in historic clothes and gear!


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GSSWT invites you to participate in the new monthly Leadership Lounge at the Sally Cheever Girl Scout Leadership Center!
Each month the Volunteer Resources staff will host an evening just for you -- the adult volunteer. Come join Girl Scouts as we laugh, learn, listen, get loot and make lasting friendships. It's a place for you to meet other adults and share best practices, get new ideas, learn how to implement the Girl Scout Leadership Experience, win door prizes, hear guest speakers and, most of all, build a better adult Girl Scout experience.
Girl Scout Shop will be open -- special discounts and deals will be available for these dates only.
This event occurs in the America/Mexico City time zone.
|Powered by New Global Ventures
Girl Scouting builds girls of courage, confidence and character, who make the world a better place.
On my honor, I will try:
to serve God and my country,
to help people at all times,
and to live by the Girl Scout Law
Sally Cheever Girl Scout Leadership Center
811 N. Coker Loop
San Antonio, Texas 78216
Tel: 210-349-2404
West Side Girl Scout Leadership Center
5622 Cesar Chavez Way
San Antonio, TX 78237
Tel: 210-319-5775

subset: commoncrawl


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Harvard RWJF Scholar Colleen Reid, PhD, has co-authored a study published in International Journal of Biometeorology that explores the association between diurnal temperature range (DTR) and mortality in 95 large U.S. communities. While much research has focused on Asia, Reid's study examines the U.S., and shows a statistically significant association between DTR and mortality, driven mainly by effects of DTR on cardiovascular and respiratory mortality in the elderly.
Tag Archives: mortality
Decline in HIV mortality due to antiretroviral treatment not same for all groups in rural South African community
Harvard Pop Center affiliated researchers Kathleen Kahn, PhD, and Stephen Tollman, PhD, and colleagues have published a study in Global Health Action that evaluates the HIV mortality rates on a rural South African community from 2007-2010, when antiretroviral treatment (ART) was rolled out. Factors such as gender, age, location (distance from health center), length of residence, country of origin, transportation ownership, and level of education had an impact on the risk of dying of HIV/TB over the period of the roll-out of ART.
Having Better-Educated Offspring May Add Years to Parents' Lives
Harvard RWJF HSS Alum Esther Friedman, PhD, has co-authored a study that suggests that making an investment in children's higher education may have a big payoff for parents' lifespan. The study has received media coverage, including this article in the Milwaukee Wisconsin Journal Sentinel.
Temporary migration and epidemiology trends in rural South Africa
Harvard Pop Center affiliated faculty Kathleen Kahn and Stephen Tollman have co-authored a study that finds that in the Agincourt sub-district of northeast South Africa, temporary migration (migrants relocating mainly for work purposes and remaining linked to the rural household) is more important than age and gender in explaining variations in mortality, whatever the cause. The study suggests that public health policies should account for population mobility, and that the rural health care system should be strengthened, because migrants tend to return to rural households when they need health care.
Rural South Africa seeing increase in mortality in population aged over 50 due to HIV/TB
Harvard Pop Center Director Lisa Berkman, PhD, and affiliated researchers Kathleen Kahn, PhD, and Stephen Tollman, PhD, have co-authored a study published in the International Journal of Social Epidemiology that examines the social conditions and disability related to the mortality of older people in rural South Africa.
Do differences in social policy underlie an important part of the US health disadvantage?
A paper co-authored by Ichiro Kawachi, MD, PhD, titled "Why Do Americans Have Shorter Life Expectancy and Worse Health Than Do People in Other High-Income Countries?" published in the Annual Review of Public Health examines whether crucial differences in social policy may play an important role in why US Americans lead shorter and less healthy lives than do people in other high-income countries.
Americans Living Longer and Healthier
In a bit of good news, David Cutler, the Otto Eckstein Professor of Applied Economics, and Pop Ctr faculty member, finds that Americans are living longer healthier lives. http://news.harvard.edu/gazette/story/2013/09/the-good-life-longer/
Mortality Expectation and Fertility Choice
Pop Center faculty members, David Bloom and David Canning, and PGDA fellows, Isabel Gunther and Sebastian Linnemayr, analyze the role of mortality expectations on population growth in their paper, "Fertility Choice, Mortality Expectations, and Interdependent Preferences An Empirical Analysis".
UV index and racial differences in prostate cancer
David Cutler, Pop Center faculty member, studies the role of vitamin D and the ultraviolet index on racial disparities in prostate cancer incidence and mortality. Read more…
Dying in their prime: determinants and space-time risk of adult mortality in rural South Africa
Study by Pop Center faculty members, Kathleen Kahn and Stephen Tollman, investigates the driving forces behind adult mortality in rural South Africa and their policy implications.Read more …


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Mfg.: Escali
Model: Escali B180RC
This item is shipped brand new from the supplier. Please note the image above is for reference only.
Item:Escali Round Glass Bathroom Scale Clear 400lb Capacity
Model: B180RC
Description:This item is ideal for weight watchers who seek a clear round glass scale with an automatic shut-off feature for quick weigh-ins.
There are currently no reviews for this item. Be the first to write one.


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Voting machines malfunction in 13 Westmoreland precincts
Voters in 13 precincts throughout Westmoreland County were forced to cast paper ballots Tuesday morning as up to 30 electronic voting machines briefly malfunctioned as polls were opening for the primary.
"Everyone who wanted to vote voted," Elections Bureau Director Jim Montini said.
Officials believe an external flash drive used to input data into the machines may have been corrupted, causing the computers to malfunction. The first problem was discovered shortly after 6 a.m. The polls opened at 7 a.m.
"We're still investigating the cause," Montini said.
Montini said about 325 emergency paper ballots were used in the affected precincts until the machines were put back online.
It took about 2 1⁄2 hours to complete the repairs, he said.
The precincts affected were Salina in Bell Township, Peanut in Derry Township, Fairfield Township, Hannastown and Middletown in Hempfield Township, Hunker Borough, Hecla in Mt. Pleasant Township, Pershing Heights in New Kensington, 4-2 (Christ Methodist Church on Coulter Road) in North Huntingdon Township, Lowber in Sewickley Township, Beatty in Unity Township and the 2nd Ward in Vandergrift.
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Our RegionProviding a Great Soccer Experience Since 1981!
Established 1981, JCYSL is short for the Jefferson County Youth Soccer League. We are a region of the American Youth Soccer Organization (AYSO), an all-volunteer organization that has some 600,000+ children playing soccer in both the USA and abroad.
Non-Profit 501(c)(3)
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North American Tag-O-Rama!
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City Slicker
Joined: Sep 2010
Location: Here & There
Oddometer: 6,207
I had to go to SW DC to get it 2 years ago.
Originally Posted by
Egg has been rescued from 12th & D St SW, D.C. and is back in MD.
Grab photos as soon as I get them out of the camera and uploaded.
Damn I hate big cities and their one way frigging streets.
Round and round and round we go....
After missing the exit off I 395 S, going over the Potomac, driving around the Pentagon, going across Arlington Memorial Bridge, going by the Lincoln Memorial, up Constitution Ave to 12th, figuring out how to go around the Mall and get back on 12th, I finally got to D St SW. I didn't see the tag spot until after I went by it,(D St is a one way street going away from the tag.) I made the left after the tracks and that put me back on I 395 S.
So... after crossing the Potomac again I managed to get on the GW Memorial Pkwy this time, crossed the Memorial Bridge again, went around the other side of the Lincoln Memorial, got on Independence Ave and took a right on 12th. When I got to D St, I couldn't figure out how to get into the construction area. So I kept going straight this time and ended up at a red light on Maine Ave at 9th. I then figured I needed to hang a uby. After surveying the area for cops(u turns in DC are illegal) I decided to go for it. I roll up on the red light at 12th & D, going in the other direction this time, still trying to figure out how I'm going to get in the construction area when I see the ramp in the side walk and I'm in.
And I really do hate big cities!
In line with the tracks is the Capitol dome. Bike is on the far left.
The Egg will be in my possession again very shortly.
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First of all, thanks to @polevaultweb for the dribbble invite! Hopefully I won't dissapoint you.
Anyways, here's my first shot. It's a logo for my own design company. Hopefully I can't start working it full time in the near future. And yes, I know Lobster font is overused, but I think it suits the company identity well.
More Eski Mirza
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Fundamental Accounting Principles, Volume I, 18th ed., by Larson, Wild and Chiappetta,
Practice Set: Thunder Mountain Snowmobile
Boone & Kurtz, CONTEMPORARY BUSINESS 2006, Thomson/South-Western, ISBN:
Film Art by Bordwell and Thompson, any edition. This is an excellent introduction to film, though I
recommend purchasing a used copy of a previous edition as this text can be very expensive. ISBN-13: 9780072484557
The Orchid Thief by Susan Orlean. The version noted here was released after the film Adaptation and
contains a short piece where the author interviews herself about the film. ISBN-13: 978-0449003718
Different Seasons by Stephen King. You will read the novella "Rita Hayworth and the
Shawshank Redemption." ISBN-13: 978-0451167538
View Full Document


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Innovation is alive and well in the economy class seat manufacturing sector. Take Italian seat maker Geven, for instance. The firm this year started offering a 'convertible' slim seat. Here's how it works. A row of three economy class seats can be transformed into a business class (or premium economy class) solution by retracting the […]
Tag Archives | economy class
Geven's 'convertible' economy class seat revealed
By Mary Kirby on April 12, 2010 in Uncategorised
Airbus A350 – suitable for tomorrow's extra-wide passengers
By Mary Kirby on April 13, 2009 in Uncategorised
I'd like to highlight one final video to come out of the recent Aircraft Interiors Expo in Hamburg. In the following clip, Airbus aircraft interiors marketing manager, customer affairs Christophe Cossart shows Flight's Barbara Cockburn a new cutaway 1:120 scale model of its A350 extra-wide body (XWB). The cutaway model highlights potential interior designs and […]
VIDEO: A fly through of the Air Sleeper
By Mary Kirby on March 31, 2009 in Air Transport, Cabin Interiors
I might not be in Hamburg, but you'd be amazed at all the interiors stuff a gal can get stuck into from her desk in Amish Country. Take, for instance, MmilleniumM Group's Air Sleeper – that stacked bunk for economy and other cabin classes that I've been talking about for months. I've got the first […]
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20 January 2014: In 'EastEnders', Max Branning is furious when he discovers Jake might have got Lauren pregnant, storming through the door, Max pushes him against the wall before Lauren and Carol finally catch up and hold him off.
[Previous EastEnders Episode: Jake and Lauren's secret is out!]
"Now she's pregnant you're gonna' walk away?" Max says, as Jake reels in shock, but Lauren soon sets the record straight, "I'm not pregnant!" she says, just as Bella appears on the stairs. "You need to go," Jake says, but Max tells him he needs to know the truth. Just before things get heated, a tearful Sadie walks in - she's overheard the whole thing. "You cheated on me, with her?" Sadie asks, "I'm sorry," Lauren interrupts, before her and Max leave the couple alone to talk. Will their relationship survive?
Meanwhile, Liam, Cindy and TJ are walking home, whilst Cindy comments about her perfect man when flicking through a magazine. Noticing his friend's interest in Cindy, TJ immediately tries to warn him off, "You're wasting your time with her, could do a lot better," he says. But what is TJ really hiding?
Jake and Sadie are finding it difficult to talk, "I need to explain, it's not what you think," Jake says, but Sadie doesn't want to hear his excuses, despite this, Jake explains how he met Lauren when he and Sadie was on a break. "But she just kept coming back for more," Jake insists, starting to cry, "She understands me!" Jake shouts, "I've put my life on hold for you, and why?" Sadie says, before telling her husband that he's pathetic. "You have the nerve to tell me she understands you?" Sadie says, as Jake begins to sob, but Sadie has made her decision, "I hope she was worth it," she says, as she walks out on their marriage.
Later on, Lauren and Max pay Jake a visit and find him about to drink alcohol, "You're stronger than this! Don't! Please!" Lauren begs, before Jake tells them to get out, but before they can move Jake's thrown the glass bottle at the wall where it shatters, cutting Lauren's face. Touching blood, Lauren storms out as Max grabs Jake in anger, "Pathetic!" he says, as he runs after his daughter.
Meanwhile, at the Jackson household, TJ has discovered Liam in the kitchen, "So, Whitney's up the duff?" he asks, "Apparently not, she lied," Liam says, as he ponders over dialling Cindy Juniors's number to tell her his true feelings. Meanwhile, Cindy has just received a text from an unseen number, "Need 2 CU," it reads. Heading outside into the night, Cindy comes face-to-face with TJ, not Liam, on the swings. "So, what was so important?" she asks, "They found your stupid pregnancy test, " TJ replies, "So what we gonna' do about it?" he asks, revealing he's the father of Cindy's baby.
What will Liam say?
Shehnaz Khan has been watching EastEnders for as long as she can remember. Shehnaz likes to think she has never missed a single episode of her favourite soap within the last ten years, but is unsure that this is the case. Ultimately, Shehnaz would love to live in Walford if it really existed. Follow Shehnaz on Twitter.
More articles from Shehnaz Khan:
Why Beyonce deserved to win 'Best Live Act'
Exclusive Interview: Cover Drive chat to Shehnaz
Why Rihanna deserved to win the first ever AMA Icon Award


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Search Results: 'Network Marketing'
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Career Opportunities
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Business Development Manager, Media and Entertainment
London, United Kingdom
We are looking for an outstanding BD Manager to join our Global Media and Entertainment Partnerships. You will develop, negotiate and close strategic agreements with global media and entertainment partners (TV, radio, print, film, sports) that support Spotify's strategic mission and will positively impact our growth as an organization. This role is based in our London office and will report to the Head of Global Media and Entertainment Partnerships. Read moreApply now
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We are looking for Global Compliance & Contracts coordinator that will review all global inbound contracts to ensure compliance with legal, financial, and other policies. Read moreApply now
Marketing and PR
Regional B2B Marketing Manager, UK
London, United Kingdom
The ideal candidate will be responsible for establishing and maintaining all B2B marketing efforts in the region. You will be an expert in creating compelling narratives and marketing materials, engaging with agencies through events and programs and work with the local advertising community to maintain our position as thought leaders. Read moreApply now


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The Presentation ofPREFACE These notes are prepared and shared with you to assist those who desire to know more about preparing Bible Messages. The notes were written from the process of ... http://www.watke.org/resources/Homiletics_SermonPrep.pdf Preview Maximize
Preaching Seminar Expository Preachingexpository preaching rev. dr. darryl b. starnes, sr., instructor lesson #1 - the scriptural conception u0026 the patterns of preaching introduction: preaching defined. http://beamezion.org/resources/preachers/ExpositoryPreaching.pdf Preview Maximize
How To Use Th e POSBTO GAIN MAXIMUM BENEFIT FROM The Preacheru0027s Outline u0026 Sermon Bible , hereu0027s all you do. Follow these easy steps using the sample outline below. http://www.lmworldwide.org/uploadedFiles/OBR/Preachers_Outline_and_Sermon_Bible2/How to Use (POSB) Mar2007Screen.pdf Preview Maximize
introduction to Sermon form17 1 introduction to Sermon form Pastor Bill stares at the scribbling on a piece of paper. Finally, in frustration he crumples the paper into a ball and throws it at the trash ... http://www.familychristian.com/chapters/18344.pdf Preview Maximize
Outline of ON THE PREPARATION AND DELIVERY OF SERMONSOutline of ON THE PREPARATION AND DELIVERY OF SERMONS by John A. Broadus Fourth Edition, Revised by Vernon L. Stanfield John A. Battle, Th.D. Western Reformed Seminary (www ... http://wrs.edu/Materials_for_Web_Site/Courses/Homiletics-general/Broadus Outline Syllabus.pdf Preview Maximize
Rude PreachersC. The Bible is able to make the man of God perfect by precept and example (II Timothy 3:16-17). 1. As with other issues, we shall esteem Godu0027s word right and hate all ... http://www.letgodbetrue.com/sermons/pdf/rude-preachers.pdf Preview Maximize
MY PROCESS FOR SERMON DEVELOPMENT1 MY PROCESS FOR SERMON DEVELOPMENT Rev. Chuck Price [email protected] Someone asked me recently about my process for developing sermons. Iu0027msureevery preacher uses his ... http://chuckandlari.com/Media/SermonProcess.pdf Preview Maximize
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Bible BackgroundBIBLE SUNDAY 2011 : BIBLE BACKGROUND This background to Nehemiah 8.1-12 has been written to help preachers prepare for their sermon. It also offers an introduction to the ... http://www.biblesociety.org.uk/assets/biblesunday2011/download/BS_sermon.pdf Preview Maximize
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THE EXPOSITORY SERMON CULTURAL OR BIBLICAL ?T HE E XPOSITORY S ERMON C ULTURAL OR B IBLICAL ? Robert A. Allen Associate Professor of Bible Baptist Bible College Clarks Summit, Pennsylvania I NTRODUCTION Questioning ... http://www.bbc.edu/journal/volume2_2/expository_sermon-allen.pdf Preview Maximize
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A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.
1. A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of;
a) forming a first circuit pattern on a substrate;
b) depositing a first dielectric layer;
c) defining apertures in said first dielectric layer;
d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said first dielectric layers being initially hollow, said first metallization layer consisting of a metal conductive layer sandwiched between metal adhesive layers which facilitate bonding to adjacent dielectric layer vias;
e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer;
f) filing said first dielectric layer vias with solid material so that said first dielectric layer vias become solid; and
g) removing the remainder of said photoresist layer.
2. A method as recited in claim 1 wherein said metal conductive layer copper.
3. A method as recited in claim 2, further comprising forming a second circuit pattern including second circuit layer lines on the structure resulting from step g so that at least one of said second circuit layer lines is stacked on a respective one of said first dielectric layer vias.
4. A method as recited in claim 3 further comprising a second iteration of steps b through g to form a plurality of second dielectric layer vias over said second circuit pattern so that at least one of said second dielectric layer vias is stacked on a respective one of said first dielectric layer vias to form a multiple layer interconnect.
5. A method of forming an integrated circuit structure including solid vias, said method comprising the sequential steps of:
a) forming a first circuit pattern on a substrate;
b) depositing a first dielectric layer;
c) defining apertures in said first dielectric layer;
d) depositing a first metallization layer so as to form an upper conductive layer including a plurality of first dielectric layer vias through said apertures, said vias being initially hollow, said first metallization layer including a metal conductive layer sandwiched between metal adhesive layer;
e) depositing a photoresist layer on the structure resulting from step d) and defining apertures in said photoresist layer;
f) filling said first dielectric layer vias with conductive material so that said first dielectric layer vias become solid;
g) polishing the structure resulting from step f so as to remove excess solid conductive material so that a composite conductive layer with a planar top surface and integral solid vias remains; and
h) photolithographically patterning said composite conductive layer so as to define a first upper layer of conductive traces.
6. A method as recited in claim 5 further comprising a second iteration of steps b through h to form a plurality of second dielectric layer vias over said second circuit pattern so that at least one of said second dielectric layer vias is stacked on a respective one of said first dielectric layer vias to form a multiple layer interconnect.
The present application is a continuation-in-part of a U.S. application, Ser. No. 07/360,828, filed Jun. 1, 1989, now U.S. Pat. No. 5,055,425. The present invention relates to integrated circuits and, more particularly, to a method of forming stacked solid vias, and to structures resulting from the method. A major objective of the present invention is to provide for high-density multi-chip carriers.
Much of recent technological progress embraces the increasing miniaturization afforded by advances in integrated circuit processing technology. Dramatic improvements in the circuit density available on individual integrated circuit chips have been made. Typically, integrated circuit chips are individually packaged and the packages are mounted on printed circuit boards. The sizes of the packages limit chip density on the printed circuit board, requiring larger systems and limiting overall circuit performance due to longer inter-chip connections.
More recently, multi-chip carriers have been developed which permit multiple integrated circuit chips to be mounted on a common carrier without the need for packaging the individual chips. This allows the chips to be packed more closely together.
While multi-chip carriers have been fabricated using a variety of technologies, the greatest chip density has been achieved by multi-chip carriers fabricated using integrated circuit processing technology. In other words, a multi-chip carrier can be fabricated by photolithographically defining multiple layers of circuits interconnected by metal vias through intermediate dielectric layers. Individual integrated circuit chips attach to the upper layer of the multi-chip carrier and receive and transmit electrical signals through the multi-chip carrier's circuit layers and vias.
The vias which carry electrical signals from one circuitry layer to another are typically formed as follows. Apertures are photolithographically defined in a dielectric layer deposited over a lower circuit layer. Copper vias are then formed in these apertures by sputtering or by chemical vapor deposition. Copper is the preferred via material because of its excellent conductivity and current-carrying capacity, however copper requires a distinct adhesive layer, e.g., chromium, to bond the copper to the dielectric. Aluminum bonds readily with dielectrics without an intermediate adhesive layer, and for this reason is also sometimes used.
The vias formed by conventional sputtering or chemical vapor deposition are hollow. Hollow vias cannot be stacked through successive layers because of attendant photolithographic difficulties. Specifically, a photoresist layer follows the curvature of the hollow via's surface. The resulting curvature causes deviations in the collimated light beam used to define patterns in the photoresist; these deviations prevent certain regions of the photoresist from being exposed, and conversely, expose other regions that must not be exposed, so that the desired pattern for the next circuitry layer cannot be formed.
To address these problems, vias can be offset through individual layers to provide multi-layer interconnections. The pattern of vias through the individual circuit layers resembles a set of steps, which require extra space. The spreading of the vias across the layers limits the circuit density of the carrier and thus the density with which chips can be arranged on the carrier. In addition, the less dense arrangement requires longer signal paths, characterized by higher impedance and longer signal travel time.
What is needed is a method of fabricating a multi-chip carrier that provides for greater density in the arrangement of the integrated circuit chip carrier. More specifically, what is needed it a method of fabricating stacked vias compatible with integrated circuit processing technology.
In accordance with the present invention, an integrated circuit device comprises a substrate having a circuit pattern deposited on its surface, and a dielectric layer deposited upon the circuit pattern. The dielectric layer contains a plurality of solid conductive vias which traverse the thickness of the dielectric layer, allowing vertical connections to other circuit patterns and further similar dielectric layers. In accordance with the present invention method, hollow vias are first electroplated through etched openings in a dielectric separation layer. These hollow vias are then filled with further electroplating material, yielding solid vias which when polished provide planar upper surfaces for fabricating further circuit lines, another dielectric layer and additional solid vias. The method provides for the formation of solid vias which can be stacked. Preferably, the vias formed are of copper, however, the method also provides for the formation of vias formed of other highly conductive metals such as silver, gold, aluminum and platinum.
The first step of the method is to form a circuit pattern on a substrate. This can be done using conventional photolithographic techniques. In a second step, a dielectric layer is deposited over the substrate and circuit pattern. Photoresist is applied, as a third step, over the dielectric layer, and apertures are defined photolithographically and etched through the dielectric layer, after which the photoresist is stripped
In a fourth step, the whole surface including the apertures is covered by plating a highly conductive metal to form hollow first dielectric layer vias. Preferably, electroplating is used, but the invention provides for electroless plating as well. The preferred highly conductive material is copper. However, copper does not effectively bond to the dielectric material surrounding the vias. Accordingly, metal adhesive layers can be deposited before and after the copper conductive layer to ensure proper bonding with adjacent dielectric materials. For example, chromium can be used to ensure adequate bonding between the copper and the surrounding dielectric material.
Since the electroplating process does not result in solid vias, the next steps fill vias to achieve solid vias through the dielectric layer. In a fifth step, photoresist is applied over the electroplated metal layer. Apertures are defined through the photoresist to expose the regions of the hollow vias. In a sixth step, the exposed hollow vias are filled by electroplating a second amount of copper material. The seventh, final step removes the photoresist layer and any excess metal from the top of the vias, leaving a planarized metal layer atop the dielectric layer containing the solid vias.
The planarized metal layer now is patterned by conventional photolithography to form a second electrical circuit layer directly above the structure created by the above-described procedure. This second circuit layer includes circuit layer lines laying across and electrically attached to a portion of the first dielectric layer vias. A second dielectric layer including vias stacked over the conductive traces of the second circuit layer can be fabricated in the manner of the first dielectric layer. Subsequent circuit and dielectric layers can be similarly fabricated, resulting in a multilayer structure with vertical interconnects, or vias, through several layers.
Since multilayer interconnects can be formed with stacked solid vias, rather than relying on offset hollow vias, greater circuit density can be achieved in a multi-chip carrier. Moreover, since stacked vias minimize interconnect lengths, impedance and signal travel time are minimized. Furthermore, the stacked vias provide for more effective heat transfer from the mounted integrated circuit chips. Because of the heat-transfer characteristics of stack vias, they can be used as "studs" for heat removal, even where they are not required for electrical interconnection. These and other features and advantages of the present invention are apparent from the description below with reference to the following drawings.
FIGS. 1A-1G illustrate the cross section of the product at successive steps of the process in accordance with the present invention.
FIG. 2 is a flow diagram illustrating stages in the fabrication of a structure including a solid copper via in accordance with the present invention.
FIGS. 3A-3G represent stages in the fabrication of a structure including a solid copper via in accordance with an alternative embodiment of the present invention.
FIGS. 4A and 4B are microscope pictures of the cross section of solid copper vias, 40 microns (μm) in diameter, 40 μm tall built in a polyimide/copper structure in accordance with the present invention, polished using a first planarizing method.
FIGS. 5A and 5B are microscope pictures of the cross section of solid copper vias, 40 μm in diameter, 10 μm tall built in a polyimide/copper structure in accordance with the present invention, and polished using a second planarizing method.
FIG. 6 illustrates the polishing of substrate surfaces with a very high degree of orientation accuracy, using metallographic or wafer polishing equipment, and a substrate holder designed with three degrees of angular freedom which forces the substrate surface to automatically align to the polishing platen surface, in accordance with the invention.
FIG. 7 is a microscope picture of the cross section of four levels of stacked solid copper vias, 40 μm in diameter, in a polyimide/copper structure of five metal layers, fabricated in accordance with an alternative embodiment of the present invention, polished using a third planarizing method.
In accordance with the present invention, an integrated circuit device FIG. 1G comprises a substrate 100 having a circuit pattern 102 deposited on its surface 101, and an intermediate dielectric layer 104 deposited upon the circuit pattern. The dielectric layer contains a plurality of solid conductive vias 114 which traverse the thickness of the dielectric layer, allowing vertical connection to other circuit patterns 118 and further similar dielectric layers. In accordance with the present invention, a method for forming solid copper vias which can be stacked is illustrated in FIGS. 1A-1G. Steps of the method are given in the accompanying flow diagram of FIG. 2. FIG. 1A represents a starting point for the present invention and shows copper (Cu) lines 102 formed on a silicon substrate 100 (not shown), the upper surface 101 of which has been oxidized to form a silica layer. A thin chromium (Cr) layer can be used to bond copper lines 102 to surface 101.
A relatively thick polyimide layer is deposited over copper lines 102 and cured to form an intermediate dielectric layer 104. Using conventional photolithographic techniques, apertures 106 are formed through the entire depth of the intermediate dielectric layer 104 over portions of copper lines 102, as shown in FIG. 1B, to allow access for electrical connection to copper lines 102. Next, a composite layer 108 is formed over the surface of polyimide layer 104, partially filling apertures 106 with copper, resulting in the structure of FIG. 1C. Composite layer 108 comprises a copper center sandwiched between chromium adhesion layers. A photoresist layer 110 is then deposited over the structure of FIG. 1C. Using standard photolithographic techniques, apertures 111 are formed through photoresist layer 110, exposing copper cup 112 in order to define the location for a subsequently formed solid via, as shown in FIG. 1D.
Cup 112 is then filled with copper to form solid via 114 in an electroplating step, resulting in the structure of FIG. 1E. A polishing step removes excess copper 116 and photoresist layer 110 so that the via top surface 117 is planar as indicated in FIG. 1F. Using photolithographic techniques, upper composite layer surface 117 can be patterned to form an upper layer of conductive circuit traces 118, connected by solid vias 114 to the lower layer of conductive traces 102, as shown in FIG. 1G.
The structure of FIG. 1G can become the substrate for the next iteration of the procedure. A second dielectric layer with vias therethrough can be formed using a second iteration of the process described with reference to FIGS. 1B-1G. After several iterations, the resulting structure comprises alternating circuit layers and dielectric layers, connected with solid vias. FIGS. 4 and 5 show cross sections of solid copper vias, 40 μm in diameter, built in a polyimide/copper structure by the described via fabrication method.
In accordance with the present invention, the solid copper vias or studs are first made in the shape of cups, then are filled and overfilled with copper, to be finally polished back to the required level. The corresponding steps of the process are recapitulated below. An alternative embodiment of the invention then follows. As described, the cross sections of the product corresponding to the successive steps of the present invention are illustrated in FIG. 1, while the method steps are provided in the flow diagram of FIG. 2.
Consider the nth method layer 102 of a polyimide/copper structure shown in FIG. 1A, deposited as a circuit pattern, step 212 FIG. 2. The next layer and the cup-shaped vias connecting between these two layers can be formed by first fabricating, steps 214 and 216, a cured polyimide layer 104 with via apertures 106, FIG. 1B, and then depositing, step 218, a Cr/Cu/Cr metallization 108, FIG. 1C. The two 0.05 μm thick chromium layers provide adhesion. Ordinarily, in the prior art the metal layer is patterned by masking and etching, leaving the (n+l)th metal layer and cup-shaped, hollow vias connecting downward to the nth layer.
In order to provide solid vias, allowing denser and stackable inter-layer connections, the present invention fills the copper cups before the patterning of the (n+1) th metal layer. The present invention method starts at the procedural point represented in FIG. 1C, and follows the step given below.
A. Mask the (n+l)th metallization layer 108 with photoresist 110 (i.e., spin, dry, expose, develop, and hard bake a photoresist layer) to expose the copper cups 112, FIG. 1D, step 220 FIG. 2, through an aperture 111.
B. Etch the top chromium layer of the (n+1)th metallization layer 108 left exposed in previous step.
C. Electroplate copper 114 to fill the cups, step 222, FIG. 2 (note the resulting overfill of copper 116 shown in FIG. 1E).
D. Strip the remaining photoresist 110 and polish the overfill of copper 116, FIG. 1F, step 224, FIG. 2, using an appropriate planarization process as discussed below.
E. When needed, 0.05 μm of chromium can be deposited to cover the upper copper surface 117 for adhesion to further layers.
The topmost Cr/Cu/Cr metallization surface 117 can then be patterned to complete the (n+l)th metal layer 118, FIG. 1G. Each following layer of metal, dielectrics and vias can be fabricated similarly, by repeating fabrication steps 212 through 224.
FIGS. 4 and 5 show cross sections of solid copper vias, 40 μm in diameter, built in a polyimide/copper structure by the described fabrication method.
In accordance with the invention, stacked solid copper vias and heat-conducting studs in polyimide/copper structures can also be fabricated by an alternative method to provide high-performance multi-chip modules (MCMs). The cross sections of the product corresponding to the successive steps are illustrated in FIGS. 3A-G. The first metal layer 302, 304 can be formed over substrate 306 by first depositing a Cr/Cu/Cr metallization, FIG. 3A, then patterning it by masking with photoresist, selective etching of the successive metals and stripping the photoresist. The two chromium layers are 0.05 μm thick and provide adhesion. In accordance with the invention, the Cr/Cu/Cr metallization for the first metal layer is formed such that the solid copper vias and studs are formed before the bottom metal layer (providing electrical connection during electroplating) is etched away.
Accordingly, the processing proceeds as follows:
A. Deposit a Cr/Cu/Cr metallization 310, 0.2 to 1.0 micrometer thick, FIG. 3B. Metallization 310 serves to conduct the electrical current during the subsequent electroplating step. The chromium layers are 0.05 μm thick and mainly provide copper adhesion.
B. Mask metallization layer 310 with photoresist 312 (i.e., spin, dry, expose, develop, and hard bake), exposing the metallization where the copper vias or studs are to be built. The thickness of the photoresist should equal the height of the planned copper via to be deposited in apertures 314, FIG. 3C.
C. Selectively etch away the exposed chromium at the bottom of aperture 314, and electroplate copper to fill apertures 314 in photoresist 312. Note the resulting overfill of vias 316, FIG. 3D.
D. Polish via surfaces 318 (using polishing methods described below) and strip photoresist layer 312, then mask the copper lines, vias and studs with new photoresist 320, FIG. 3E.
E. Strip the exposed regions of the thin metallization layer 310 which served to conduct the electroplating current in preceding step C, and strip photoresist 320.
F. Deposit polyimide layer 322. The polyimide deposition process involves dry baking and plasma cleaning the substrate. Next, polyimide precursor solution is spun onto the substrate, and spun dry. Then, the wafer is soft baked to obtain a B-shape polyimide layer 322. Photoresist layer 324 is masked to provide openings 316 atop vias 316, FIG. 3F, and then polyimide bulge 323 atop via 316 is etched back. Photoresist layer 324 is stripped and finally, polyimide layer 322 is cured, FIG. 3G.
Each following intermediate layer of metal circuit paths and interconnecting vias (or studs) is fabricated similarly. The stacked vias shown in FIG. 7 were fabricated according to the above via procedure.
The fine, accurate polishing of the via and dielectric surfaces is a critical procedural step for the present invention. A silicon wafer can be on the order of 100,000 μm across, yet the top layer of the vias and studs (i.e., the irregular layer which needs to be polished flat) can be only 5 μm thick. The thinness, planarity and parallelism of the collective layer of vias/studs and the small amount of material needed to be removed stain conventional methods of polished. In accordance with the invention, a method, tooling and procedure are provided to maintain the silicon substrate, with its newly formed layer of vias and studs, at a slope smaller than 1/100,000 relative to the polishing platen during each mechanical polishing operation.
The invention employs a substrate holder designed with three degrees of angular freedom, thus forcing the substrate to automatically of self-align to the rotating polishing platen surface. The self-alignment serves to evenly remove material from the upper surface of the substrate. The equipment and tooling used, as shown in FIG. 6, include the following: a rotating polisher (for example, a Polimet polisher from Buehler, which is not shown), platens 602 and discs 604 bearing the require fine polishing grits for use on the polisher, and a substrate holder 606 with three degrees of angular freedom. There are many ways to design for three degrees of angular freedom.
In one embodiment, the holder comprises a cylindrical mass and a rod. The cylindrical mass 608 can be machined from brass to a diameter somewhat larger (for example, 0.5" larger) than that of the silicon substrate 614. Cylinder 608 has an axial hole 610 (0.17" in diameter, for example), which preferably does not penetrate the entire cylinder. Rod 612 has a tapered end of proper length, such that when rod 612 is inserted into cylinder hole 610, it is stopped by the hole's rounded edge before the end of rod 612 reaches the bottom of hole 610. Other embodiments include alternative designs possessing three angular degrees of freedom such as a ball joint, a universal joint coupled to a bearing, etc.
The polishing and planarizing procedure proceeds as follows. First, the back of substrate 614 is attached against the smooth end of cylinder 608 (i.e., the end surface without the hole). As known in the art, wafers tend to bow as various metal and dielectric layers are added to the silicon substrate. To eliminate the bow during the polishing step, the wafer is laid onto the brass cylinder 608, which has had a thin layer of beeswax applied to its surface. A lint-free cloth separates the upper surface of the wafer 614 from another flat block. The flat block presses and flattens the wafer to the brass cylinder 608 in a heating and cooling step, during which the beeswax melts and attaches the wafer to the cylinder block, resulting in a high degrees of flatness.
Second, the polishing platen rotation speed control is set to zero and the substrate/cylinder assembly is placed face down on the platen, off-center, as shown in FIG. 6. The platens are used in graded sequence from the coarse to the fine polishing grit, with customary cleaning procedures employed at each platen change to avoid cross-contamination. Next, the tapered end of rod 612 is inserted into cylinder hole 610. Holding rod 612 nearly vertically, and using it to control the position of the substrate surface on the platen, the platen rotating speed control is gradually increased from zero to the desired speed. The increase in linear speed with distance form the platen center causes the substrate 614 and cylinder block 608 assembly to rotate, thus distributing the polishing action uniformly over the substrate surface.
After the desired polishing time, the platen rotating speed control is gradually decreased to zero. The assembly is then removed, rinsed, dried and examined. Based upon the examination of the wafer surface, more polishing is carried out at the same grit grade or the sample is thoroughly cleaned in an ultrasonic bath, the platen changed to the next grade, and polishing resumed until polishing is completed.
The surfaces of the solid copper vias shown in FIGS. 4A and 4B were fabricated in accordance with the first described fabrication procedure, in accordance with the first polishing method. The above described polishing requires starting with the substrate material initially planarized, but this requirement can be relaxed by the use of padded platen surfaces (which carry the polishing grit).
In accordance with the invention, an alternative mechanical polishing method, tooling and procedure are provided to inherently maintain the substrate during the polishing operation at a slope smaller than 1/100,000 relative to the polishing platen. Instead of holding, the substrate and wafer over a rotating polishing platen, the alternative method employs a substrate holder designed to "flat" the substrate, face down at the desired pressure, on a shaking polishing platen surface such that the substrate surface inherently self-aligns to the shaking platen. The tooling and procedures are described below.
The equipment and tooling for the alternative mechanical polishing includes a shaking polisher (for example from Labtone), a polisher well for each requisite polishing grade grit, a hard flat surface (flat glass, for example) fitting the bottom of each polisher well, and a substrate holder similar to that described above (made from brass, shaped approximately 0.5" larger in diameter than the substrate which it holds). The density and height of the holder determines the polishing pressure.
The alternative mechanical polishing proceeds as follows. First, the back of the substrate is waxed flat against a cylinder end surface of the substrate holder, as described above. Next, the polisher is switched off and the substrate and cylinder assembly is placed face down on the platen. Several such assemblies can be placed on the platen for simultaneous polishing. The wells and hard flat surfaces are used in graded sequence from coarse to fine polishing grit, using customary cleaning procedures at each change to avoid cross-contamination. Then, the polisher is switched on. After the desired polishing time, the polisher is switched off. The assembly is removed, rinsed, dried and examined. Based upon the examination, more polishing is carried out at the same grid grade, or the sample is thoroughly cleaned in an ultrasonic bath, the well and platen changed to the next grade, polishing resumed, and so on until polishing is completed.
The solid copper vias of FIGS. 5A and 5B were fabricated in accordance with this second polishing procedure. The above described polishing requires starting with the substrate material initially planarized, but this requirement can be relaxed by the use of padded platen surfaces (which carry the polishing grit).
In a third polishing method, tooling and procedures are provided for polishing the final copper layer above the substrate surface without the imposition of the stringent requirements on orientation inherent to the mechanical polishing methods described above. The tooling for the third embodiment includes an acid-resistant plate (for example, of polypropylene), lint-free pieces of cloth soaked with graded strengths of copper etchant (Transene CE-200, as an example), and a substrate holder (for example, a hand-held vacuum chuck).
The third inventive procedure begins by flattening the soaked cloth against the plate surface, while the substrate is held by its back on the vacuum chuck. Next, the substrate/chuck assembly is placed with the substrate face-down on the flattened cloth, and moved about, thus continuously wiping the substrate surface against the soaked cloth. The soaked cloths are used in graded sequence form stronger to weaker etchant stretch. After the desired polishing time, the assembly is removed and immediately rinsed, dried, and examined. Based upon the examination, more polishing is carried out at the same etchant strength or the soaked cloth is changed to the next etchant strength, and polishing resumed that so on until polishing is completed.
The solid copper vias shown in FIG. 7 were polished in accordance with the third polishing procedure. FIG. 7 shows a microscope picture of the cross section of four levels of stacked solid copper vias, 40 μm in diameter, in a polyimide/copper structure of five metal (interconnect) layers. The dielectric layers are, from the bottom, 10, 40, 20 and 15 μm thick, respectively.
The present invention, combining novel via and stud fabrication and polishing techniques, can be applied in the fabrication of integrated circuit chips as well as in the fabrication of multi-chip carriers. As is apparent to those skilled in the art, many modifications to the disclosed embodiment can be made while retaining the essential features of the invention.
The present invention provides for substrates other than silicon, e.g., a metal, a metal with a dielectric layer, or a flexible substrate such as a polyimide film. The lines can be copper, silver, gold, or platinum. The conducting layer can include the same range of metals as the lines, as can the vias. The dielectric layer can be of alumina, silica, etc. The present invention also provides for the use of photosensitive dielectrics. In such a case, the photo-imageable layer used to define the vias can be retained as the dielectric layer. A photosensitive dielectric would thereby eliminate the need for a separate photosensitive mask, by directly masking and developing the dielectric layer. Elector-less plating can be used to form the vias. In this case, the conductive layer below the vias is not required. Accordingly, as an alternative embodiment, it would be neither necessary to deposit this metal nor to remove the portions of it which interconnect lines.
These and other variations upon and modifications to the described embodiments are provided for by the present invention, the scope of which is limited only by the following claims.
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The Week in Review
Follow Underground Blogger Ralph Welch on Twitter.
D-Day in Vegas
There will be many words written in this, the biggest week in 2012 for the sport of Mixed Martial Arts.
The collision between the man perceived as the greatest fighter of all time, Anderson Silva, and arguably the greatest talker of all time, Chael Sonnen, has been the standout date on the calendar ever since Dana White announced the warring factions were heading to Las Vegas.
The main question on everybody's lips after last week's explosive conference call is whether Silva's uncharacteristically emotional outburst has played into Sonnen's hands.
It's debatable.
Memorably, the last time we saw an animated Anderson Silva he unleashed a furious first round assault on Demian Maia before needlessly showboating for the remaining twenty minutes, belittling his hapless opponent. It was an embarrassing episode. So much so that Dana White famously left his seat cageside and gave the belt to Ed Soares, Silva's manager, rather than present it to the champion personally.
You can bet that White won't budge an inch this Saturday. It's been a torrid few months for the UFC: an ongoing injury jinx and high-profile drug bans have robbed them of several potential lucrative pay-per-view matchups, while TV figures for their new FOX programming have reportedly been underwhelming.
The eyes of the world will be on Las Vegas this weekend. This match simply must deliver.
May the best man win.
Forrest Griffin's reality check
Also on the card this weekend is the nostalgic contest between light-heavyweight rivals Tito Ortiz and Forrest Griffin; a rubber match between two men of steel.
Ortiz has already declared this will be his final appearance in the Octagon and this week Griffin himself spoke candidly about his own future.
The Ohio native, disarmingly honest at times, admitted that his stock had fallen slightly below the new wave of talent in his division and he was a "top 25" fighter these days rather than a genuine title contender.
Some have called it (wrongly) defeatism, others have called it realism. Regardless, there comes a time in any fighter's career when a healthy dose of perspective can prevent unnecessary pain.
Forrest Griffin has earned the right to evaluate and steer his career any way he chooses. His match with Stephan Bonnar at the inaugural TUF finale took the sport away from the periphery and began the journey towards mainstream acceptance. Griffin's own journey took him to the UFC title.
Perhaps the fairytale ending for Griffin would be to take it to the well with Bonnar one last time. To end a career as it started.
Yet romantic endings are rare in the realm of fighting.
Forrest Griffin is a former policeman, reality TV star, UFC champion, published author, and recently became a father for the first time.
Fairytale or no fairytale, his is a story worth reading.
Penn/MacDonald clean up
The specter of Performance Enhancing Drugs (PEDs) continues to loom large over combat sports.
But this week BJ Penn and Rory Macdonald attempted to build confidence that the sport is clean by signing up to be drug tested by the Voluntary Anti Doping-Agency (VADA) ahead of their clash at UFC 152.
For those who might be unaware, VADA, not to be confused with the US Anti-Doping Agency (USADA), is considered the gold standard in this field. Where VADA differs from its peers is in their use of Carbon Isotope Ratio (CIR) testing which determines whether an athlete's testosterone is natural or synthetic. VADA use it as standard for all samples, whereas USADA use it at their own discretion.
It is their diligence that caught boxing champion Lamont Peterson on the eve of his eagerly-anticipated rematch with Amir Khan. And more recently Andre Berto fell foul of their investigations, jinxing any hope of a return bout with Victor Ortiz.
It was disappointing, but not entirely unexpected, to see Golden Boy Promotions chief Richard Schaefer announce that for the foreseeable future their fighters would only be subjected to the less exhaustive USADA testing.
In the murky sport of boxing, whose corridors are often ensconced in darkness, VADA offers a flickering light of hope that the cheats can be identified. But honesty comes at a price - and it's not one that boxing is prepared to pay.
Speaking of which, it was interesting to read comments this week from shamed welterweight Nate Marquardt, who was unceremoniously dumped from the UFC roster last year over his own drug violations.
Marquardt, who has since secured a Strikeforce contract after his stint in isolation, bemoaned the constant questioning from the media about his previous indiscretions.
Sadly for Nate, he is learning the hard way that in the court of public opinion sentences can last a lifetime. The best thing he can do is keep winning.
That's no problem for Penn and MacDonald. Before they even touch gloves in the Octagon, their honesty is a victory for both themselves and the sport.
Aerts seeking Glory
He was meant to be riding into the sunset, but after losing his supposed farewell match, kickboxing icon Peter Aerts turned the horse around and headed back into town, armed with a shiny new six-fight contract.
Aerts, 41, looked in impressive shape as he entered the ring in Belgium to face Tyrone Spong, but succumbed to the significantly younger limbs of his 26 year-old opponent and lost via TKO in the third.
It would have been a disappointing end for a man who has been involved in some of the sport's most seminal moments. His 1998 victory at the K-1 Grand Prix, winning three matches in under seven minutes, will live long in the memory.
Yet there may still be more to come. On Saturday night kickboxing organisation GLORY announced the purchase of their rival promotion It's Showtime and their first order of business was to secure the services of Aerts on a long-term contract.
It's a deal likely to take him into an extraordinary third decade in the sport.
And finally…
There was surely no more heart-warming moment in MMA this week than when UFC commentator Joe Rogan received a black belt from legendary trainer Eddie Bravo.
It was the pinnacle of some 16 years of graft and endeavour, fitting in time to study the art of jiu-jitsu around his increasingly hectic UFC, comedy and TV schedule. Indeed, Rogan had been a brown belt for a prolonged period of seven years, such has been the increasing pressure on his time as the UFC continues its global assault.
Rogan has been absolutely critical to the success of his employers. Allied to his encyclopaedic knowledge of the intricacies of the sport, he's a gifted orator whose infectious enthusiasm has helped attract a new breed of fans.
Having received his belt, a visibly emotional Rogan delivered a heartfelt speech to his classmates. He spoke of his pure and personal bond with jiu-jitsu and the profound effect it has had on his life, helping him to improve as a husband, a father and a human being.
More utterly compelling words - from a man who has already given us so many.
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Recent Comments »
7/2/12 7:54 PM by kevsh
Mr. Welch has no business writing about MMA. He's articulate, insightful, informed and writes coherently. Clearly he doesn't belong here!Kidding aside, I agree, great feature.
7/2/12 6:33 PM by NazeerMKhan
Man, this guy is a great writer.
7/2/12 5:19 PM by BonquishaBLOOD
7/2/12 5:06 PM by UGCTT_Fraser_Finlay
Love this feature. Keep it up UG Blog :)


text: This sweet one of a kind patch card arrived in the mail today. Steve McNair 06 Flair Showcase Lettermen #'d 1/6 It's cut from a game used jersey nameplate. They made 6 cards, one for each letter. I got the M! (don't ask how much it cost me) I love the fact that it's from an old Oilers jersey, I'm sure there will never be another Oilers nameplate issued for McNair. It sucks that he's pictured as a Raven though. A few others arrived also... Lendale White 06 Topps Turkey Red Box Topper (big card...app 8"X6") Vince 06 Turkey Red (red bordered parallel version) Calvin Lowry 06 Leaf Limited Monikers Auto #'d 19/25


text: Programs of Study Home | Programs of Study | Polysomnographic Technology Faculty SpotlightKelly CumminsProviding resources, breaking down concepts help students find relevance of content they're learningMore Placement/Transfer 94% That's right! Ninety-four percent of SCC's 2013-2014 graduates found work or continued their education. Placement Placement/Transfer 94% That's right! Ninety-four percent of SCC's 2013-2014 graduates found work or continued their education. Placement Placement/Transfer 94% That's right! Ninety-four percent of SCC's 2013-2014 graduates found work or continued their education. Placement Polysomnographic Technology WelcomeSCC's Polysomnographic Technology program prepares students for entry-level positions in Sleep Medicine. Sleep technologists work under the supervision of a licensed physician to assist in the education, evaluation, treatment, and follow-up of sleep disorders for patients of all ages. The Polysomnographic Technology program is open to students who have obtained a minimum of an associate degree from a health care-related field of study.OverviewSCC's program is part-time comprised of nine credit hours per quarter. The program is two quarters in length (or six months). The program is offered online, with clinical rotations being completed at an approved sleep disorders center. Students will complete a comprehensive program in patient assessment, equipment calibration, data acquisition, diagnostic evaluation, therapeutic modalities and follow-up care of patients. Students are encouraged to select sleep disorders centers near their home to complete their clinical education. A Certificate in Polysomnographic Technology is awarded upon completion of the program, which is accredited by CAAHEP. Graduates of the program will be eligible to take the Registered Polysomnographic Technologist exam offered by the Board of Registered Polysomnographic Technologists.The Polysomnographic Technology program is accredited by the Commission of Accreditation of Allied Health Education Programs on recommendation of the: CoAPSG, 6 Pine Knoll Dr., Beverly, MA 01915-1425 (774) 855-4100 www.coapsg.orgMissionThe mission of the Polysomnographic Technology program is to graduate competent registry-eligible Polysomnographic Technologists.Employment OutlookThere are more than 7,000 registered polysomnographic technologists worldwide. The number of jobs in this field is expected to grow rapidly through 2016, due to an increase in interest in sleep disorders and the detrimental effects they can cause. Also, there is an increase in available treatment options, diagnostic tools and areas of research. Pediatric sleep medicine also is growing and is an area in which a polysomnographer can specialize. Recent SCC graduates report an average salary of $24 per hour.Starting TermsSummer Quarter.Polysomnographic Technician-CECurriculumProgram RequirementsTake PSGT-1000,PSGT-1010,PSGT-1020,PSGT-2000,PSGT-2010, PSGT-2020,PSGT-2030;PSGT-1000 Polysomnography 1PSGT-1010 Polysomnography LabPSGT-1020 Fundamentals of PolysomnographPSGT-2000 Polysomnography 2PSGT-2010 Polysomnography 2 LabPSGT-2020 Seminar ReviewPSGT-2030 Clinical EducationGen Ed ReqTake 4.5 credits in Written Communication or SpeechENGL-1010 Composition IENGL-1015 Composition & LiteratureSPCH-1090 Fund of Human CommunicationsSPCH-1110 Public SpeakingSPCH-2810 Business & Professional CommunRequirements Program Requirements & Student ResponsibilitiesMinimum cumulative GPA of 2.5 required to graduate from program. A current American Heart Association Healthcare Provider CPR card.Submit completed Health Statement to the Health Sciences Division (upon admission to program.)A criminal background check will be required of each student in this program. Based on the outcome of the background check, a student may be prevented from taking certain courses, accessing certain laboratory experiences, or completing the program. A non-refundable fee of $45 will be assessed for this CBC. Please note: Misdemeanor or felony convictions may prevent a graduate from acquiring a state license. A two-step skin test for tuberculosis and/or a chest X-ray are required. Flu immunization may be required. All POLY courses completed with a grade of 75% (C+) or higher to progress through the program. Students are required to attend a two-day conference at Southeast Community College- Lincoln Campus. Students are responsible for travel and lodging for the two days.Program offers Web-based courses but requires supervised clinicals/practicums/labs at identified locations.Clinical EducationStudents are required to complete 240 contact hours of clinical education. Clinical and laboratory work will be completed in an approved local sleep center. Sleep center approval and contracts will be completed on an individual basis.Other Links Health Statement Letter Health Statement Physicians Lab Immunization Information Essential FunctionsCostsIt appears your Web browser is not configured to display PDF files. You can download the PDF file here.It appears your Web browser is not configured to display PDF files. You can download the PDF file here.


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I am six weeks pregnant with no symptoms, is this normal?
I have had a blood pregnancy test that came back positive. I am six weeks pregnant (starting from the first day of my last period) and have had no noticeable symptoms. I don't have my first Dr.'s appt until I'm 10 weeks. The only thing I have noticed is peeing alot (but that's b/c I have been trying to drink lots of water) and I wake up every morning with this nervous/anxious feeling. I also haven't had much of an appetite. I'm really worried that I am not really pregnant b/c I haven't had symptoms yet. I feel like I'm driving myself crazy worrying about it. Is there anyone else out there like me??
Posted: 09/01/2007 by a BabyCenter Member
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it's absolutely normal.. i went through my whole pregnancy like this. my stomach didn't even get big until my last 2 months and i've always been a slim person so people couldnt undertsand why it wasnt noticeable but everything went fine.posted 10/30/2007 by sarahcascio
Hello! I feel the same. I have none of the symptons of being pregnant at 6 weeks. I have an 11 years history of infertility and I am 40 so I am very nervous. I welcome the sickness to come.posted 09/14/2008 by a BabyCenter Member
Iam 6 weeks pregnant with third child my oldest is 18 and 16 iam 37 for now all i have are tender breast and light crampin with constipation i dont go to the doctor untill my 10th week. Im still in shock that im pregnant!!we tried for 5 years after i had my tubes untied.we tried everything then we just gave up!! and it happened!!posted 09/13/2007 by a BabyCenter Member
I had written earlier about not getting symptoms..I forgot to knock on wood @ 8 weeks along....haven't thrown up yet, but the dull sensation of nasuea is hitting me now. Its reminding me that I'm pregnant now. Good luck to all you ladies.posted 07/22/2010 by jdameron1
Yes, those cramps you feel (they feel like menstrual cramps) are from your uterus expanding to accommodate the growing baby...it is also normal to have heartburn. If, however, you are doubled over in pain or have any worries whatsoever about the cramps, just ask your doctor and no doubt she will put you at ease. By the way, I am having those cramps right at this moment too! :) Try not to worry.posted 06/18/2010 by Dina Lorraine
I googled this question-because I am having the same thing happen to me. This is my 1st pregnancy and I am 6 weeks along-I am really not having any symptoms- even though I have had 2 positive pregnancy tests. My 1st ultrasound isn't until I am 9 weeks. Thank you for all the responses I feel so much better.posted 01/22/2009 by a BabyCenter Member
Yea I am almost 7 weeks and i do not have any symptoms but i missed my period and i took four prenancy tests that all came up positive,so i am pretty sure i am pregnant. Does anyone know if i got an ultrasound now if anthing would show up? Sydneyposted 09/30/2007 by sydgrib
yes its possible to be pregnant and have no symptoms ...i have a 4 month old i had on september 2nd and i had no symptoms at all....no throwing up or nothing i didnt even start showing till i was between 6 and 7 months....so dont worry...every woman is different is what my dr said....posted 12/28/2011 by chels52091
It's normal. My friend was pregnant with a girl and she was constantly sick. Her next pregnancy she wasn't sick at all and had barely any symptoms and she had a boy. I've heard girls make you way more sick than boys. Maybe it's a boy? Congrats!posted 12/08/2012 by harpybaby44
So I talked to my Dr about my 'no symptoms' worry and she said, every pregnancy is different. not everyone has morning sickness and nausea, however it can come later in the pregnancy, like 9 or 10 weeks or so. But even then, some people DON'T get morning sickness at all. the sickness did come for me later, at 9w. I liked it better before. I was concerned about not feeling anything also, cause this is my 2nd pregnancy, and she said that is normal too. Your muscles are already stretched from the 1st pregnancy so the feeling is not the same, also you may show sooner for the same reason. Hope this helps.posted 03/31/2010 by dawn602
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