text:
A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.
1. A content addressable memory (CAM) device comprising:
a plurality of CAM cells;
a plurality of compare lines coupled to the plurality of CAM cells; and
a multiplexer having a first input to receive a first comparand value, a second input to receive a second comparand value, and an output coupled to the plurality of compare lines.
2. The CAM device of
3. The CAM device of
4. The CAM device of
5. The CAM device of
6. The CAM device of
7. The CAM device of
8. The CAM device of
9. The CAM device of
10. The CAM device of
11. A method of operation within a CAM device, the method comprising:
selecting a first comparand value from a plurality of comparand values in response to a comparand select signal; and
outputting the first comparand value onto compare lines of a first CAM array.
12. The method of
13. The method of
14. The method of
15. The method of
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19. The method of
20. A content addressable memory (CAM) device comprising:
a plurality of CAM cells;
means for selecting a first comparand value from a plurality of comparand values in response to a comparand select signal; and
means for outputting the first comparand value to the plurality of CAM cells.
This application is a continuation of U.S. patent application Ser. No. 10/734,666 filed Dec. 12, 2003 now U.S. Pat. No. 6,914,795 which is a continuation of U.S. patent application Ser. No. 10/121,344 filed Apr. 12, 2002 now U.S. Pat. No. 6,690,595, which is a continuation-in-part of U.S. patent application Ser. No. 09/954,827 filed Sep. 18, 2001 now U.S. Pat. No. 6,597,595, which is a continuation-in-part of U.S. patent application Ser. No. 09/922,423 filed Aug. 3, 2001 now U.S. Pat. No. 7,237,156.
The present invention relates generally to content addressable memory devices, and more particularly to error detection within content addressable memory devices.
Content addressable memory (CAM) devices are often used in network switching and routing applications to determine forwarding destinations for data packets. A CAM device can be instructed to compare a selected portion of an incoming packet, typically a destination field within the packet header, with data values, called CAM words, stored in an associative storage array within the CAM device. If the destination field matches a CAM word, the CAM device records a CAM index that identifies the location of the matching CAM word within the storage array, and asserts a match flag to signal the match. The CAM index is then typically used to index another storage array, either within or separate from the CAM device, to retrieve a destination address or other routing information for the packet.
Any corruption of CAM words stored within a CAM device (e.g., due to alpha particle bombardment or failure of a storage cell within the CAM device) may result in a false match/non-match determination and ultimately in non-delivery of packets or delivery of packets to an incorrect destination. While it is known to store parity information in the CAM device for error detection purposes, the parity information is generally used to detect errors only when a host device instructs the CAM device to perform a read operation (i.e., output a CAM word). That is, parity checking is not performed during a typical compare operation because the CAM word is usually not read during such an operation. Moreover, any interruption of the normal operation of the CAM device, for example to read CAM words for error detection purposes, reduces the number of timing cycles available for compare operations, effectively lowering the compare bandwidth of the CAM device.
A content addressable memory (CAM) device having a CAM storage array and circuitry to detect errors in the CAM storage array is disclosed in numerous embodiments. In at least one embodiment, the CAM device includes circuitry to identify errors in the CAM storage array concurrently with performing host-requested compare operations, thereby providing an error checking function without reducing the compare bandwidth of the CAM device. Further embodiments include circuitry to log errors and error addresses in an error address register for subsequent host inspection, and circuitry to automatically invalidate or correct an entry in the CAM storage array upon detecting an error. Also, embodiments that include an error CAM or other circuit for generating a match error signal are also disclosed. Further, embodiments that selectively load error addresses into an error CAM are disclosed. These and other features and advantages of the present invention are described in the detailed description below.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
CAM Device
The CAM array 101 includes a plurality of CAM cells arranged in rows for storing CAM words. The CAM array also includes a validity storage 102 to store validity values. Each validity value corresponds to a respective row of CAM cells and indicates whether the row contains a valid CAM word. As discussed below, each validity value may be represented by a single bit or multiple bits. The CAM array 101 is coupled to (i.e., connected directly to or through one or more intervening circuits) the address circuit 103, priority encoder 114, flag circuit 112, comparand register 115, and read/write circuit 161. The address circuit 103 is used to select a particular row of the CAM array for read or write access. The read/write circuit 161 is used to sense the output of the selected row during a read operation and to transmit a value to the selected row during a write operation. The comparand register 115 is used to store a comparand value received via the comparand bus 143, and outputs the comparand value to the CAM array 101. In alternative embodiments the comparand register 115 may be omitted and the comparand value input directly to the CAM array 101 from the comparand bus 143. During a compare operation, the comparand may be masked by a global mask value, then compared simultaneously with all the CAM words stored in the CAM array 101. Each of the rows of CAM cells is coupled to a corresponding match line 182, and any match between the comparand and a valid CAM word results in a match signal being output to the priority encoder 114 and flag circuit 112 via the corresponding match line 182. When one or more match signals are asserted on the match lines 182, the priority encoder 114 selects one of the match signals and outputs a CAM index 174 (i.e., address of the CAM word corresponding to the selected match signal). The flag circuit 112 also receives the match signals, and outputs a match flag signal to indicate that a match has occurred. If more than one match signal is asserted, the flag circuit may additionally output a multiple match flag signal to indicate that multiple matches have occurred.
As described below in greater detail, the CAM array 101 is preferably structured to permit read and compare operations to be executed concurrently (i.e., at least partly overlapping in time). Consequently, the CAM array may be read for error checking purposes even when host-requested compare operations are being performed. This provides significant advantages over the prior art error checking technique described above because error checking can effectively be performed in the background, with little or no consumption of compare bandwidth. Moreover, the prior art error checking occurs as part of a host-requested read, meaning that only those CAM array locations selected to be read by the host are error checked. Unless the host is programmed to systematically read all the locations in the CAM array, it is likely that numerous CAM array locations will not be checked. By contrast, in embodiments of the present invention, error checking is performed systematically using an address generator within address circuit 103 to generate a predetermined sequence of error check addresses, thus ensuring that all locations within the CAM array are checked.
Still referring to
All instructions to the CAM device, including instructions to load other registers are first received in the instruction decoder 105 via the instruction bus 145. The instruction decoder 105 includes circuitry to decode the incoming instructions as well as control circuitry that responds to the decoded instructions by issuing control and timing signals to other circuit blocks within the CAM device 100. In one embodiment, the instruction decoder 105 is a state machine that transitions from state to state in response to transitions of a clock signal 104 (CLK) and according to status signals received from other circuit blocks within the CAM device 100 and instructions received from the decode circuit 106. For another embodiment, the instruction decoder 105 is a lookup table or read only memory (ROM). The instruction decoder 105 may further include delay circuitry to delay output of timing and control signals to other circuit blocks within the CAM device 100 until appropriate times within a given cycle of the clock signal 104.
The error detector 107 is used to detect errors in CAM words output from the CAM array in error checking operations. The error detector 107 is coupled to receive a CAM word and corresponding validity value from the read/write circuit 161 and to receive the control signals RESET 153 and READ 151 from the instruction decoder 105. Upon detecting an error, the error detector 107 outputs an error address 131 and asserts an error flag signal 132. The error detector 107 receives the check address 155 from the address circuit 103 for error logging purposes, and may optionally output an error address as indicated by dashed line 131. In alternate embodiments, the reset signal 153 and/or read signal 151 may be supplied by an external device (e.g., a host processor) instead of the instruction decoder 105.
The check address 155 may alternatively be output from the check address generator 124 or from the address selector 125. When the check address is output by the address selector 125, any address source, including the check address generator, may be used to supply the check address to the error detector (i.e., element 107 of
Although the HPM register 121, NFA register 122 and check address generator 124 are all shown as being part of the address circuit 103, these circuit blocks may alternatively be disposed elsewhere in the CAM device. For example, in one embodiment, the HPM register is implemented by a field of bits (i.e., to contain the HPM address) within a status register of the CAM device. In such an embodiment, the status register may be selected by the address selector to provide the HPM address for a CAM array access. Contents of the status register, including the HPM address, may also be output from the CAM device in a status read operation.
Still referring to
CAM Array
During a compare operation, a respective portion of the comparand is applied to each column of CAM cells 201 via lines CL/CLB such that the complete comparand is applied to each row of the CAM cells 201 simultaneously. In one embodiment, each of the match lines 182 is precharged to a high logical level at the start of a comparison operation, but pulled down to a low logical level by the compare circuit within any attached CAM cell 201 that receives comparand signals which do not match the stored data value. In this configuration, any match line 182 not pulled low constitutes a match signal. The match lines 182 are coupled to the flag circuit 112 of
During a read or write access to the CAM array 101, an address of CAM cells to be accessed is supplied to the address decoder 127 of
Reflecting on the structure of CAM array 101, it can be seen that providing separate signal paths to the CAM cells 201 for comparand and data values enables data to be output from the CAM array 101 concurrently with a comparand being input into the CAM array 101 for comparison purposes. By this arrangement, a CAM word (or local mask word) may be read from the CAM array for error checking purposes concurrently with performance of a compare operation. As mentioned, this concurrency of comparison and error checking operations provides significant advantages over the prior art technique described above, including the ability to do systematic background error checking with little or no reduction in compare bandwidth.
Still referring to
In one embodiment, each validity value is represented by a single binary bit, called a validity bit. In a first state (i.e., when set), the validity bit indicates that the corresponding row of CAM cells contains a valid CAM word. Conversely, in a second state (i.e., when reset), the validity bit indicates that the corresponding row of CAM cells does not contain a valid CAM word. In alternative embodiments, two or more bits may be used to represent the validity value. For example, in one alternative embodiment, the validity value is formed by a pair of bits: a skip bit and an empty bit. The skip bit indicates that the corresponding row of CAM cells are to be skipped (i.e., ignored) during a compare operation, while the empty bit indicates that no CAM word is stored in the corresponding row of CAM cells. Thus, the skip bit and the empty bit are each reset to indicate that a valid CAM word is stored in the corresponding row of CAM cells. In the interest of clarity, the validity value is described as a validity bit in the remainder of the present description. However, any number of bits may be used to form the validity value in alternative embodiments.
During a compare operation, the validity bits are used to prevent match signal assertion for those rows of CAM cells which do not contain valid CAM words. For example, in the embodiment described above in which the match line is pulled low to signal a mismatch, each reset validity bit prevents assertion of a match signal by pulling the match line low for the corresponding row of CAM cells. Consequently, no match is signaled for rows having reset validity bits regardless of whether the row contents match the comparand. During a read operation, the validity bit is sensed (i.e., via lines 193 and 194) along with the CAM word and forwarded to the error detector 107 where it is used to prevent assertion of the error signal 132 and logging of an error address 131 for invalid CAM words.
Error Detector
The data and parity bits are input to a parity check circuit 201 that includes a separate parity generator 206 and compare circuit 208 for each group of data bits and its corresponding parity bit. Each parity generator 206 generates a binary output according to the state of an even/odd select signal 232 and the number of set (or reset) data bits within the corresponding group of data bits. For example if the even/odd select signal 232 selects odd parity, circuitry within the parity generator 206 will output a logic '1' if the input group of data bits contains an odd number of logic '1' data bits, and a logic '0' if the group of data bits contains an even number of logic '1' data bits. If the even/odd select signal 232 selects even parity, the output of the parity generator 206 is inverted, i.e., outputting '1' if the input group of data bits contains an even number of logic '1' data bits and a logic '0' if the group of data bits contains an odd number of logic '1' data bits. In alternative embodiments, the logic states may be inverted so that the parity generator 206 outputs a logic '0' if the number of logic '0' data bits is odd or even (in the case of odd parity selection or even parity selection, respectively). Also, the output of the parity generator 206 may be inverted so that, if odd or even parity is selected, the total number of bits in the logic '1' state, including the bit output by the parity generator, is always odd or even, respectively.
The parity generator 206 is preferably formed using conventional combinatorial circuitry, for example a combination of exclusive OR gates, to produce a parity result shortly after a CAM word is loaded into the row buffer 162. The even/odd select signal 232 may be output from a configuration register (e.g., element 109 of
Returning to
The parity error signal 231 is supplied to the set input of an S-R flip-flop and to the load input of an error address register 203. The check address 155 from the check address generator (element 124 of
Still referring to
In alternative embodiments, storage elements other than an S-R flip-flop may be used to register the error condition. For example,
Still referring to
The read signal 151 is asserted during an error address read operation to advance the contents of the error address register 289. More specifically, when the read signal 151 is asserted, the contents of the error address register 289 are shifted forward so that the entry depicted in
The error address register 289 is depicted as having X entries (0 to X−1) available for error address storage. If all X entries of the error address register are filled with valid error addresses, a full signal, EA FULL 291, may be asserted to indicate the full condition. The full signal 291 is preferably provided to the instruction decoder (element 105 of
Instruction Decoder Operation; Concurrent Instruction Execution and Parity Check
The instruction decoder continues to monitor incoming instructions in decision block 311 until the error check timer has reached the terminal count value (as determined at decision block 314). After the error check timer has reached the terminal count, the instruction decoder signals the check address generator to increment the check address (block 315) and resets the error check timer at block 316, before beginning another error check operation at block 310.
In an alternative embodiment, the error flag signal is provided to the instruction decoder, which selectively enables the check address generator to increment the check address according to whether a parity error is detected. Accordingly, if the error flag signal is determined to be set after decision block 314, the error check operation is completed without signaling the check address generator to increment the check address and further error checking is halted until remedial action is taken (e.g., self-invalidation or self-correction, discussed below, or action by the host). Alternatively, if the error detector includes a multiple-entry error address register, the instruction decoder may signal the check address generator to increment the check address despite error flag signal assertion so long as the error address register is not full. In such an embodiment, a full signal may be output by the error address register to notify the instruction decoder when the error address register is full (i.e., when all entries of the error address register have been loaded with error addresses).
In the embodiment illustrated by
As mentioned above in reference to
Configurable Multi-Block CAM Device
Sense amplifier circuitry within the read/write circuit 322 is used to sense a CAM word output from the CAM array 321 during an error check operation as described in reference to
For embodiments that concurrently perform error checking on CAM words from each of the different storage blocks, error detector 323 may include additional circuitry (not shown) to store a value indicative of which of the error detection circuits 329 has signaled a block error 330. This value, referred to as a block identifier, is preferably stored along with the check address 155 within the error address register 337. The block identifier may then be output from the error address register 337 as part of the error address to enable a host or other circuitry within the CAM device to identify the block or blocks within the CAM array 327 that produced the error indication.
Although error detector 323 may be used to simultaneously error check a respective CAM word from each of the blocks, the provision of separate error detection circuits for each storage block increases the transistor count and complexity of the error detector implementation. In embodiments of the multiple storage block CAM device that error check one CAM word at a time, the multiple error detection circuits 329 may be omitted in favor of a single error detection circuit that is selectively coupled to the output of each of the storage blocks 325. An error detector 348 having such an alternative arrangement is illustrated in
Configurable Storage Block
A configuration signal (not shown), for example from configuration register 109 of
In the embodiment of
Still referring to
The circuit of
The circuit of
Other logical constructs for generating x2 and x4 parity error signals may be used without departing from the scope of the present invention. Also, numerous additional logical constructs may be used to generate multi-segment parity error signals for a storage block having additional segments or different distributions of validity bits within the storage block.
Still referring to
CAM Device with Self-Invalidating Function
As shown, the instruction decoder 443 is coupled to the output of the S-R flip flop 457 and therefore is signaled upon detection of a parity error. If no parity error is signaled, the instruction decoder 443 issues an increment signal 444 to the check address generator 445 which responds by incrementing a counter 446 containing the parity address. If a parity error is signaled, the instruction decoder 443 does not issue the increment signal 444 to the check address generator 445 and the address counter 446 remains pointed at the CAM word which produced the parity error.
Depending on the amount of time required to perform the self-invalidation operation, it may be desirable for the instruction decoder to issue a busy signal (illustrated in
Although a self-invalidation operation has been described, the instruction decoder 443 of
Still referring to
In many CAM applications, a backup storage of the CAM array content is maintained to allow the CAM array to be restored in the event of memory loss or corruption. In such applications, self-invalidation of a CAM word may result in loss of coherency (i.e., sameness) between the CAM array and the backup storage. Accordingly, it may be desirable to provide an alternate error storage within a CAM device so that, as the CAM device performs self-invalidation operations to clear errors in the error address register, those same errors remain logged in the alternate error storage. The host may then access the alternate error storage from time to time to determine whether errors have occurred and, if so, take appropriate actions to maintain coherency between the CAM array and the backup storage, and restore any invalidated CAM words. In one embodiment, the alternate storage is substantially identical to the error address register (and loaded at the same time) except that a self-invalidate indicator is included in each entry. The self-invalidate indicator is initially reset when an error is logged, but then set if an invalidate operation takes place at the logged error address. In an alternate embodiment, no such self-invalidate indicator is maintained.
Error Correction Code—CAM Device with Self-Correcting Function
Thus far, error checking has been described primarily in terms of parity checking.
As shown in
The syndrome 508 is additionally supplied to an error correction circuit 509 along with the CAM word 503. If the syndrome is nonzero (indicating an error), and a single bit error has occurred, the error correction circuit 509 generates a corrected CAM word 510. In one embodiment, the corrected CAM word 510 is generated by identifying a column of bits in the parity check matrix that matches the bit pattern of the syndrome 508. The position of the matching column within the parity check matrix (i.e., first column, second column, etc.) corresponds to the position of the bit in error within the CAM word 503. The bit in error is then flipped (i.e., inverted) by the error correction circuit 509 to produce the corrected CAM word 510. As shown in
If the syndrome 508 does not match one of the columns of the parity check matrix corresponding to a single bit error, a multi-bit error has occurred and CAM word output from the error correction circuit 509 is not a corrected CAM word. Accordingly, a signal to indicate whether the CAM word 503 has been corrected (called a C bit 512) is output from the error correction circuit 509 along with the CAM word 510. If a single-bit error has been detected and corrected, the C bit 512 is set to indicate that the CAM word 510 has been error corrected by the error correction circuit 509. If a multi-bit error has been detected, the C bit 512 is reset to indicate that the CAM word 510 has not been error corrected. In the embodiment of
Still referring to
As with the self-invalidation operation, it may be desirable for the instruction decoder to issue a busy signal to the host processor during a self-correction operation to prevent the host processor from issuing instructions that may result in a resource conflict within the CAM array (e.g., host instructions that require read, write or compare operations to be performed on the CAM array). This signal is indicated by dashed line 447 in
Generating a Sequence of Error Check Addresses
For the purpose of the present description, the address generator is assumed to be implemented in a CAM device having K storage blocks, each containing Z segments that are Y rows deep. Thus, the block address ranges from 0 to K−1, the segment address ranges from 0 to Z−1 and the row address ranges from 0 to Y−1.
Referring now to decision block 601, if an increment signal is detected, the row address (RA) of the error check address is evaluated in decision block 603 to determine if the row address has reached the row limit (i.e., the final row address, Y−1). This may be accomplished, for example, by a comparison of the row address and row limit in a comparator. Other techniques and circuits may also be used to detect when the row limit has been reached.
If the row address has not reached the row limit, the row address is incremented by one in block 605 to complete the increment operation. If the row address has reached the row limit, the row address is reset to zero in block 607, followed by evaluation of the segment address (SA) in decision block 609 to determine if the segment address has reached the segment limit (i.e., Z−1). If the segment address has not reached the segment limit, the segment address is incremented by one in block 611 to complete the increment operation. If the segment address has reached the segment limit, the segment address is reset to zero in block 613, followed by evaluation of the block address (BA) in decision block 615 to determine if the block address has reached the block limit (i.e., K−1). If the block address has not reached the block limit, the block address is incremented by one in block 617 to complete the increment operation. If the block address has reached the block limit, the block address is reset to zero in block 619 to complete the increment operation.
The increment operation may be changed in numerous ways in alternative embodiments. For example, in the increment operation described above, the row address is effectively treated as the least significant component of the error check address, followed by the segment address and then the block address. Any order of significance may be assigned to the row, segment and block addresses in alternative embodiments. For example, the block address may be incremented from 0 to K−1 before either the segment or row addresses are incremented, or the segment address may be incremented from 0 to Z−1 before either the block or row addresses are incremented.
In another implementation of the increment operation, one or more of the components of the error check address may be incremented by values other than one. For example, assuming Y is even, the row address component may be incremented by any odd value with modulo Y arithmetic being used to calculate the result (the decision block 603 of
Embodiment without Validity Bits
Each of the CAM device embodiments described thus far have included validity bits to indicate whether corresponding CAM words are valid and to gate the error flag signal accordingly. In alternative embodiments the validity bit storage may be omitted from the CAM device and the gating circuitry (e.g., element 222 of
System Structure and Operation
The host processor 650 issues addresses, comparands, and instructions to the CAM device 655 via the address, comparand and instruction buses, respectively (i.e., ABUS 141, CBUS 143 and IBUS 145), and receives CAM indices and status information from the CAM device 655 via an address and status bus 149 (ADS). Though not shown in
Still referring to
The host processor 650 is also coupled to a backup storage 657 which is used to store a backup copy of the CAM words stored in the CAM device 655. The backup storage 657 is preferably a non-volatile storage such as a battery-backed semiconductor storage, an electrically programmable read only memory (EPROM), a flash EPROM, or a magnetic or optical medium, but any type of data storage device may be used in alternative embodiments.
Match Error Signaling
Although the NPU 703 may act as a host processor (e.g., as described in reference to
Still referring to
In one embodiment, the error CAM 715 includes an error CAM array and a queue control circuit that establishes a first-in-first-out (FIFO) protocol for storing error address values (i.e., check addresses 155) within the error CAM array. That is, the queue control circuit forms a queue of storage locations within the error CAM array, and, in one embodiment, includes a read pointer that points to the least recently stored (i.e., oldest) error address value within the queue (the head of the queue), and a write pointer that points to the most recently stored error address value within the queue (the tail of the queue). If the error signal 712 is asserted, the error CAM 715 advances the write pointer to point to a next available storage location, the new queue tail, then loads the check address 155 for the selected CAM word (i.e., the CAM word determined to have an error) into a storage location indicated by the write pointer (alternatively, the check address may be loaded prior to advancing the write pointer). If an advance signal 708 is asserted by the instruction decoder 105, the error CAM 715 clears a validity value stored in the queue head location, thereby releasing the oldest error address value from the queue, then advances the read pointer to establish a storage location containing the next least recently stored error address value as the new head of the queue. In one embodiment, the error address at the queue head is output from the error CAM 715 via a dedicated read port to provide the error address signal 131. As with embodiments discussed above, the error address signal 131 may be output from the CAM device 700 via a dedicated interface, via a multiplexed interface (e.g., to a status bus), via a status word, and via any other output node of the CAM device. As shown in
As discussed above, the error checking engine implemented by the check address generator (i.e., within address circuit 103), read/write circuit 161 and error detection circuit 711 may operate in the background as compare operations are performed within the CAM device 700. That is, concurrently with checking a selected CAM word for error, a comparand value received via the CBUS 143 (and optionally stored in the comparand register 115) may be compared with the contents of the CAM array 101 to determine whether the comparand value matches any valid CAM words stored within the CAM array 101. A plurality of match lines 182, coupled to respective rows of CAM cells within the array 101 (as described in reference to
The match index 174, in addition to being output from the CAM device 700, is input to the error CAM 715 for comparison with error address values queued therein. If the match index 174 matches any of the error address values, the match error signal 732 is asserted to indicate that the match index corresponds to a corrupted CAM word within the CAM array 101. The match error signal 732 may then be used by the recipient device (e.g., NPU, CPU, etc.) as discussed above in reference to
It should be noted that the multiple-entry error address register 289 of
The CAM device 750 differs from the CAM device 700 of
Still referring to
The read/write circuit 803 is used in conjunction with the queue control circuit 807 to store error address values in the CAM array 800. As discussed above, in one embodiment, the queue control circuit 807 includes read and write pointers that enable the error CAM array 800 to be operated as a queue. The write pointer points to a row of CAM cells that constitute a tail storage location of the queue, and the read pointer points to a row of CAM cells that constitute a head storage location of the queue. Error address values are loaded into the queue at the tail storage location, and read out of the queue at the head storage location. More specifically, when an error signal 712 is detected at a load input of the queue control circuit 807, the queue control circuit 807 increments the write pointer to point to an available row of CAM cells within the error CAM array 800, then activates a word line 825 indicated by the write pointer to select (i.e., enable) the row of CAM cells to receive an error address via the write bit lines, WBL and
In one embodiment, the read pointer is used to select the row of CAM cells coupled to the read port formed by the read bit lines, RBL and
CAM cells 801 may be any type of CAM cell including, without limitation, binary, ternary, NAND, NOR, volatile or nonvolatile. Additionally, a single read bit line may be used instead of the pair of read bit lines (RBL and
The reset signal 153 is input to the queue control circuit 807 and to the column of validity CAM cells 802. When the reset signal 153 is asserted, the read and write pointers within the queue control circuit are reset to an initial state, and the validity value within each of the validity CAM cells 802 is cleared.
When a match index 174 is received within the error CAM array 800 (i.e., via the comparand signal lines), the match index is simultaneously compared with each error address value stored within the CAM array 800. In the embodiment of
In one embodiment, the match logic circuit 831 is implemented by an OR logic circuit so that, if a match signal is asserted to a high logic state (i.e., has a logical state indicative of a match condition) on any of the match lines 827, the match logic circuit 831 will assert the match error signal 732. Other logic circuits may be used to implement the match logic circuit 831 in alternative embodiments.
A queue load operation is initiated when a full signal 855 is deasserted by the flag logic circuit 865 and a load signal 712 (i.e., error signal 712 of
The count value maintained within the write pointer 861 constitutes a queue tail address and is output to the write address decoder 862. In one embodiment, the write address decoder 862 is a log2M to M decoder which asserts one of M write enable signals 869 according to the queue tail address (M being the number of independently addressable rows of CAM cells within the error CAM array). The M write enable signals are input, respectively, to a set of M logic AND gates 873 which are used to drive the write word lines 825. Each of the logic AND gates 873 also receives the load signal 712 and an inverted version of clock signal 804 via inverter 871. Accordingly, at a falling edge of the clock signal 804, and while the load signal 712 is asserted, the asserted one of the write enable signals 869 enables a corresponding one of the logic AND gates 873 to activate the write word line that corresponds to the incremented queue tail address. In one embodiment, the load signal remains asserted long enough for the read/write circuit 803 (described above in reference to
The count value maintained within the read pointer 863 constitutes a queue head address and is output to the read address decoder 864. In one embodiment, the read address decoder 864 is also a log2M to M decoder which activates a selected one of M read word lines 823 according to the queue head address. Unlike write word lines which are activated only during load operations, the selected read word line 823 remains activated until an advance operation is performed to increment the read word line selection. By this arrangement, the error address stored within the row of CAM cells coupled to the selected read word line is output as an error address signal via the read port formed by the read bit lines, RBL and
Reflecting upon the operation of the write pointer and write address decoder, it will be appreciated that, prior to initiation of a load operation, the write pointer points to a row of CAM cells containing the most recently stored error address value. During a load operation, the write pointer is first incremented to point to an available storage location (effectively advancing the queue tail), then an error address value is loaded into the storage location. This order of operation may be reversed in alternative embodiments by first loading an error address value into an available storage location, then incrementing the write pointer to point to a next available storage location. In such an embodiment (which may be achieved, for example, by removing inverter 871 and inverting the clock signal at the input to logic AND gate 851), the write pointer 861 may be reset to the same initial value as the read pointer 863 in response to the reset signal 153.
A queue advance operation is initiated when an empty signal 857 is deasserted by the flag logic circuit 865 and the advance signal 735 is asserted. More specifically, logic AND gate 853 responds to assertion of the advance signal 735 and deassertion of the empty signal 857 by passing a rising edge of clock signal 804 to the strobe input of the read pointer 863 (i.e., as read strobe signal 854), thereby incrementing the queue head address.
Reflecting on the operation of the queue control circuit 807, it can be seen that, at any given time, the read and write pointers 861 and 863 define which rows of CAM cells within the error CAM array (e.g., element 800 of
The empty signal 857, full signal 855 and almost full signal 859 may be output to a processor (or other device) via a dedicated output interface or via a multiplexed interface. In another embodiment, the empty, full, and almost full signals are used to set corresponding bits within a status word that may be read by a processor (or other device) in a status read operation. Also, circuitry to generate the almost full signal may be omitted altogether.
By preventing the conditioned read and write strobe signals 866, 867 from transitioning to a high logic state at the same time, the logic AND gates 893, 895 prevent the queue depth count from being changed during a clock cycle in which both the write strobe signal 852 and the read strobe signal 854 are asserted. Different types of circuits within (or external to) the counter 891 may be used for this purpose in alternative embodiments. Also, the flag logic circuit 865 may be implemented differently in alternative embodiments. For example, rather than maintain a queue depth count, the flag logic 865 may compare the count outputs of the write pointer 861 and the read pointer 863 to determine full, almost full and empty conditions.
The storage element 901 is coupled to write bit lines WBL and
Still referring to
The validity CAM cell 802 of
Referring briefly to
Selective Error Logging
Reflecting on the error CAM embodiments described in reference to
In one embodiment, the error CAM 940 includes an error CAM array and a queue control circuit that operate as described in reference to
In one embodiment, the error CAM 940 performs a match error signaling function as described above in reference to
In an alternative embodiment, the index 174 is not input to the error CAM 940 and no match error signal 732 is generated. Instead, the error CAM 940 generates an error flag signal 132 as described above in reference to
The check address 155 is input to both the read/write circuit 803 and to the compare port of the error CAM array 800 (i.e., comparand lines 951). In one embodiment, each new check address 155 is compared with the contents of all storage locations within the error CAM array 800 simultaneously to determine whether the check address 155 is a unique or redundant address. The comparison operation generates a set of match signals which are output to match logic 947 via respective match lines 946 1-946 N. Each match signal indicates whether the corresponding entry (i.e., row contents) within the error CAM array 800 contains a valid error address that matches the check address 155. In one embodiment, a high signal on a match line 946 indicates a match condition (and, conversely, a low signal indicates a mismatch condition), and the match logic 947 is a logic OR gate that outputs a high array match signal 948 if any of the match signals on match lines 946 1-946 N is high.
Logic AND gate 949 includes an inverting input coupled to receive the array match signal 948, a non-inverting input to receive the error signal 712, and an output coupled to provide the load signal 950 to the load input (LD) of the queue control circuit 807. By this arrangement, if the error signal 712 is high and the array match signal 948 is low (indicating a non-match condition and therefore that the check address 155 is a unique address), AND gate 949 asserts the load signal 950 to initiate loading the check address 155 into the error CAM array 800 at an address indicated by the tail pointer. If the check address 155 is a redundant address, array match signal 948 will go high to disable AND gate 949 from asserting the load signal 950. Thus, the error CAM array 800 is selectively loaded with each newly presented error address according to whether the error address is unique or redundant.
In one embodiment, each new check address 155 is compared with the contents of the error CAM array 800 regardless of the state of the error signal 712. Alternatively, comparison operations within the error CAM array 800 may be enabled only when the error signal 712 is asserted (i.e., check addresses for which the corresponding CAM word includes an error), for example, by selectively enabling a comparand driver circuit of the error CAM array 800 or by selectively asserting, via the instruction decoder or other control circuit, a control signal that enables the compare operation within the error CAM array 800. Also, in one embodiment, the read/write circuit 803 drives each new check address 155 onto write bit lines (WBL) of the error CAM array so that, if the load signal 950 is asserted, the corresponding row of the error CAM array will be enabled to store the check address 155. In an alternative embodiment, the load signal 950 may additionally be supplied to the read/write circuit 803, the read/write circuit 803 being enabled to drive a check address 155 onto the write bit lines of the error CAM array 800 only when the load signal 950 is asserted. Further, while the error CAM array 800 is depicted in
The CAM cell 962 operates similarly to the CAM cell 960 of
The error CAM 975 is similar to the error CAM 953 of
When the comparand select signal 972 is low, an index 174 is selected by select circuit 971 to be compared with the contents of the error CAM array 800. If the index 174 matches a valid error address within the error CAM array 800, the match condition will be signaled on a corresponding one of match lines 946, and match logic 947, in response, will assert array match signal 948. Logic AND gate 973 is coupled to receive the array match signal 948 at a non-inverting input and the comparand select signal 972 at an inverting input such that, if the comparand select signal is low (indicating selection of the index 174 as a comparand source) and the array match signal 948 is high, a match error signal (ME) is asserted to indicate that the index 174 has resulted from a match between a comparand value and a corrupted CAM word.
In one embodiment, an instruction decoder or other control circuit monitors the flow of incoming compare requests and outputs a low comparand select signal 972 (i.e., to select the index 174 as the comparand source) for each compare cycle in which a host-requested compare operation is to be performed. When an idle compare cycle is detected (e.g., due to absence of a host-requested compare operation during a given compare cycle), the instruction decoder transitions the comparand select signal 972 to a high state to enable comparison of a check address 155 with the contents of the error CAM array 800. In one embodiment, the instruction decoder may suspend one or more host-requested compare operations to enable a check address to be compared with contents of the error CAM 975 if, for example, no idle compare cycle is detected for a predetermined time or if a predetermined number of compare operations have been scheduled without an intervening idle cycle.
Although the invention has been described with reference to specific exemplary embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Patent Citations
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text:
Smoking Cessation Program
What is Freshstart?
Freshstart is the American Cancer Society's free smoking cessation program. Freshstart is comprised of 4 one-hour group sessions over the course of 4 weeks.
Each session has 4 components:
1) Individual Attention
2) Strategies & Information
3) Review & Discussion
4) Assignments
How does it work?
Each session will have a trained facilitator to help run the meeting. The facilitator will track the average number of cigarettes each participant smokes prior to each session, and ensures that sessions stay focused and on time.
Who can participate?
Anyone who would like to quit smoking can participate whether they have attempted to quit before or not. Participants are encouraged to attend all four sessions whether or not they are meeting their goals.
What are the objectives for each session?
Session 1: To understand why I smoke and how my smoking affects me and those around me.
Session 2: To master the first few days off cigarettes.
Session 3: To master the obstacles to staying off cigarettes.
Session 4: To learn how to stay quit.
For additional resources or to request a series contact:
Mark Williams, email@example.com, 259-5111.
Smoke-free campus
VSU will become a Tobacco-free campus October 1, 2014 by policy of the Board of Regents of the University System of Georgia. Learn more.

subset: commoncrawl


text:
1. Into a saucepan add about 1/2 cup of water and let it boil.
2. Put soy sauce, sake, mirin, and ginger slices into boiling water; bring to boil again.
3. Gently add salmon in. With a spoon, start scooping some of the liquid from the pan over the salmon fillet.
4. When the bottom side is done, flip the salmon over and repeat the earlier step with the other side.
5. When the other side is done too, remove salmon from pan.
6. For the sauce, let the liquids in the pan reduce down until it becomes a thick syrupy consistency.
7. In a serving plate, place the salmon fillet, pour sauce over salmon and serve with rice.


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Lodging Normandy/Provence
I'm heading to France with my wife and her mother in September and am running into itinerary planning difficulty. We are arriving in Paris on 9/15 and had planned to take the train to Bayeux and find a B&B in the countryside nearby. The first lesson I learned was, Don't arrive in small town France wanting to rent a car on Sunday. Offices closed. Also you can't get a car in Bayeux and turn it in elsewhere. Plan B, take the train to Caen, get two hotel rooms near the train station and rent from Hertz who will let me turn in the car four days later in Rouen...with a hefty drop off fee. For this part of the trip I'm looking for advice on a safe, clean hotel in Caen at a reasonable price. After that I need a night in Honfleur and another in Rouen. I would appreciate any advice or recommendations anyone would care to offer. Also, If you've had this problem and managed to find someplace in the country I'd love to hear about it. The second problem is finding a B&B or apartment centrally located in Provence to have as a base for 6-7 nights. We will rent and return a car at the Avignon train station before returning to Paris on 9/27. Many thanks.


text:
Notes & Reviews:
The Roman Trilogy consisting of "Fountains of Rome," "Pines of Rome" and "Festivals of Rome" is among Respighi's best-known and best-loved work. It is complemented here by four lesser-known works: "Church Windows," "Metamorphoseon," "Belkis," "Queen of Scheba" and "Brazilian Impressions." This re-release is available at the special price of two CDs for one.
American Record Guide, September/October 2013
Church Windows and Brazilian Impressions are the earliest recordings, and they sound wonderful - as good as anything since. This and the Lopez-Cobos are the key recordings to have. Metamorphoseon is also a fine recording - and again, so is the Lopez-Cobos. There are a lot of wind solos, and I prefer the Cincinnati winds. It's a theme with 12 variations in the 12 modes. Belkis is a rarity still. The bass drum in the War Dance is very strong. The Roman trilogy under Tortelier is brilliantly recorded - very bright and startling. Respighi used organ and piano in his orchestral music, and they sound quite clear in these recordings. I am really happy with this remastering and coupling - so many pieces in outstanding performances.
BBC Music Magazine, August 2013
Sumptuous, meaty performances, featuring Tortelier's vigorous Roman trilogy. The Philharmonia's rich sonorities enjoy a spacious Chandos recording.
ReviewsThere are currently no reviews, be the first one!
Also Purchased


text:
Camping This Summer? — Don't Forget Your Washington State Discover Pass!
I love to take my horses and head to the mountains. Most places I've been, don't need a Discover Pass, I don't think. But, I buy one every year.
I love to take my horses and head to the mountains. Most places I've been, don't need a Discover Pass, I don't think. But, I buy one every year.
We're partnering with Gloria Sadlier with MetLife Auto & Home to celebrate the upcoming start of summer! Here's what some of our listeners sent in!
Summer fun is just around the corner! And KORD will be there with you every step of the way! Let's look at what happened last summer real quick! (This is my first iPad movie attempt, so keep that in mind LOL)
We go camping to enjoy the fresh air. To enjoy campfires, fishing and family. We go camping to get a little elbow room. So why spend the night all cooped up? Check out this "best of" family camping tent that has elbow room galore!
I've talked about this before, but it's been a long winter and with the weather getting nicer, I just brought it out again....so it's time to talk about yard tunes, garage tunes, camping tunes and just plain portable tunes! I'm not just on the radio, I'm a fan of radio, so this is one of my favorite things
As summer nears it's time to think about getting your boat ready, so here are the best places to get the supplies you need for your excursions.
I love having a nice tan. But damage to the skin is also a concern.
What do you think is the best self tanner out there?
As spring spring forth bicycle riding is a perfect activity. It's an amazing way to stay in shape and it allows you to clear your mind. Here are the best bike shops around the Tri-Cities to get your wheels up to speed:
A nicely cut wine bottle can turn into one of many cool things! Here's how to do it quickly and easily...but it will probably require sanding the edge.
I've recently learned of a fellow equestrian and would like to help! Please read this! The great thing about our advanced technological world now is that it has brought us the ability to network and be there for each other in ways that we never could have before
Well, if you live in an urban area, or are like me and board my horses out in an urban area...you too may be dealing with getting sprinklers and irrigation lines working again. I've been working non-stop, trying to fix broken PVC pipe and sprinklers that my horses ruined over the winter
Spring is here! And that means...the Yard Sales are in full swing! I myself need to have a Garage Sale. I personally hate having them! I'm not good at them, and usually end up giving everything away anyway!
I decided I'd google Yard Sale Tips and came up with a cool website that has some interesting things to consider


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Dear Amy: My ex-partner and I split up about seven months ago after living together. He is significantly older than I am. It was his decision. Although it broke my heart, I wanted him to be happy, so I moved out. I moved on with my life and found a really great guy that I love very much.
My ex and I stayed in contact, and I still consider him a friend. He seems to have given up on dating and has become more isolated. I still see him occasionally for dinner. He knows that I am seeing someone exclusively and that my current boyfriend and I have a great relationship.
Recently however, he seems a little more affectionate. Others who have witnessed this tell me he's still in love with me. I still love him very much and always will, but not romantically. While I've never said this to him in those words, I feel pretty confident that he knows this.
I'm starting to wonder if hanging out with him every once in awhile is doing him more harm than good.
I don't want to give him false hope or make him any more depressed; I just want to see him happy. Is there anything I can do or say that can help him?
Dear M: If you are happy and healthy in your new relationship, you should attempt to extend your friendship with your ex to include your current partner. The reason for this is twofold. This sort of transparency is probably best for your current relationship, and it also exposes your former partner to a new circle of people and a new dynamic, which could give him a social boost.
I do not think seeing this old friend occasionally would be "bad" for him; if he is depressed and isolated, this contact might be helpful. Rather than leave all of this as subtext, you should do your best to be honest with him about your concerns — leaving the door open to a continuing friendship.
Dear Amy: You were remiss in your advice to "Flummoxed." Whether a father wants a child or not doesn't matter. You should have referred the mother to the child support authorities.
Here in California, they have enormous power to force unwilling fathers to pay support to their children. Wages can be garnished and bank accounts tapped. All the mother needs to do is contact the authorities, and they take it from there.
— Dana
Dear Dana: The question was not really about this, but you are correct.


text:
State Agencies |
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ODE is interested in your thoughts about how EdConnection fulfills your information needs. Please send any comments or suggestions to firstname.lastname@example.com.
Follow ODE's Twitter feed by clicking here.
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Sign up to receive the weekly EdConnection newsletter.
Approaching deadlines or important dates mentioned in previous editions of EdConnection
The recording of the May 16 Third Grade Reading Guarantee webcast is available here.
Beach Bags give parents an easy way to keep their children's reading skills sharp with fun summer activities arranged around five themes: weather, pets, transportation, food and neighborhoods. Each themed online Beach Bag includes two free printable "little books," two related activities, a list of classic picture books for further reading and suggested websites to explore.
The Ohio Department of Education is introducing Parent Roadmaps, which provide parents with scenarios of the interventions and assessments that their children will receive each year from Kindergarten to Grade 4 as they pertain to the guarantee.
Training and tests will be available in June, rather than mid-May as previously announced, for educators who need to update their credentials as evaluators for the Ohio Teacher or Principal Evaluation Systems. The National Institute for Excellence in Teaching (NIET), which will administer the re-calibration process, will send notification of the training's opening date to evaluators who have valid email addresses in the institute's registration system.
The Ohio Education Research Center, in partnership with the Ohio Department of Education and Battelle for Kids, is hosting the half-day learning session, Extending Your Learning through Research that Works! This free conference is open to all, including Ohio educators, researchers and policymakers.
The Ohio Leadership Advisory Council recently launched a new blog, The Leading Edge: Helping School Leaders Put Research into Practice. The blog will feature posts by Project Director Jim Gay, along with guest bloggers, including members of the council's executive core, Ohio Improvement Process facilitators and educators using Ohio Leadership Advisory Council resources in their schools and classrooms.


text:
Classic Accessories® Dryguard Waterproof Boat Cover
Item # WX2-185120
- Google+
- Details & Specs
Classic Accessories® DryguardTM Waterproof Boat Cover. No way water slips through this locked - tight Cover!
Your boat can take a beating on the road with falling rain, kicked up mud, rocks pebbles and more doing a number on the exterior.
This Cover takes protection seriously with strong 300-denier Dryguard fabric that's bolstered with waterproof lamination. Taped seams block water from ever having a chance at penetration. For reduced wind pressure, there are 2 rear air vents with built-in stiffeners... helps eliminate interior moisture too!Details:
Model A: Fits 14-16' V-hull fishing boats with beam width to 75".Model B: Fits 14-16' V-hull runabouts (outboards and I/O), Tri-hull Runabouts (outboards and I/O) and aluminum bass boats, beam width to 90."Model C: Fits 16-18 1/2' fish and ski boats and pro-style bass boats with beam width to 98".Model D: Fits 17-19' V-hull runabouts (outboards and I/O) with beam width to 102".Model E: Fits 20-22' V-hull runabouts (outboards and I/O) with beam width to 106".Model F: Fits 22-24' V-hull runabouts (outboards and I/O) with beam width to 116".
- Strong marine canvas is durable and tear-resistant
- Integrated buckle and strap system for easy fit and trailering - adjustable straps snap into quick-release buckles on the covers
- Dual rear air vents reduce inside moisture and ballooning of cover at high speeds
- Reinforcement panels on bow, windshield and stern for additional protection
- Full cut to allow extra room for accessories such as bow rails, running lights and more
- Elastic cord in bottom hem gives tight, custom fit
- PVC-free fabric is produced in an efficient, earth-conscious Bluesign®-certified factory that reduces water used in dyeing process up to 30%
- Mesh storage bag and trailering straps included
State Size, as available in the Shopping Cart. Order ONLINE Today!
- Reviews
Classic Accessories Dryguard Waterproof Boat Cover is rated out of 5 by 1.Rated 5 out of 5 by JoanC from Great cover This boat cover is easy and quick to put on and take off. We trailer our boat and its nice at the end to cover it tie it down, the start all over the next day. Love it and it is water proffDate published: 2015-05-15

 I have a 19.5' Tahoe Q5i runabout. All your covers seem to be either 17-19 or 20-22. I'm afraid the longer one would be too long. Do you have any advice?

Asked by: callmeishmael

 We would like to work with you one on this issue. Please contact us at 1-800-888-5222 M-F 7am-7pm CST, or email us at firstname.lastname@example.com, and we will respond as soon as possible.
Answered by: Customer Service

Date published: 2015-04-22

 i have a 21 foot ranger fish and ski. What model cover do i need.

Asked by: gregg

 Please refer to the size listing the the Details & Specs area. It does seem that model E would be the cover that would fit your boat.
Answered by: Customer Service

Date published: 2015-03-11

 we have a 19 ft.aluminacraft v-hull fishing boat,would one of these tarps work for us,(outboard)?

Asked by: sher

 Model D should work on your boat as long as the beam width is no bigger than 102".
Answered by: Customer Service

Date published: 2015-03-03

2015-07-05T11:25CST

bvseo_cps, prod_bvqa, vn_cps_3.1.5

cp_1, bvpage1

co_hasquestionsanswers, tq_3

loc_en_US, sid_185120, PRD, sort_recentAnswersFirst

clientName_sportmansguide

- Articles & Tips
Don't Forget
Classic Accessories Adjustable Boat Cover Support PoleNon-Member $14.99 Buyer's Club $13.49
Silica Gel DehumidifierNon-Member $21.99 Buyer's Club $19.79
You May Also Like
Guide Gear Trailerable V-Hull boat coversNon-Member $59.99 Buyer's Club $53.99
Guide Gear Boat Cover, GrayNon-Member $89.99 Buyer's Club $80.99
Sportsman 300 Trailerable Boat CoverNon-Member $44.99 Buyer's Club $40.49


text:
The Columbus Board of Education has narrowed the list of finalists to fill the seat vacated by former president Carol Perkins , who abruptly stepped down last month.
28 people have applied to fill the remaining term of Columbus School Board member Carol Perkins.
Last night was Columbus City Schools board member Carol Perkins last regular meeting before leaving the board at the end of the month.
Columbus City School Board member Carole Perkins has announced she will retire at the end of the month, nearly 7 years after she first joined the board as a mid term appointment.
Columbus School Board president Carol Perkins says she will step down from the position at the end of the month.


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A game for 2 people using a pack of cards Turn over 2 cards and try
to make an odd number or a multiple of 3.
In this game, you can add, subtract, multiply or divide the numbers
on the dice. Which will you do so that you get to the end of the
number line first?
This challenge is a game for two players. Choose two numbers from the grid and multiply or divide, then mark your answer on the number line. Can you get four in a row before your partner?
Can you use the numbers on the dice to reach your end of the number line before your partner beats you?
A shunting puzzle for 1 person. Swop the positions of the counters at the top and bottom of the board.
Reasoning based on this Japanese activity.
Got It game for an adult and child. How can you play so that you know you will always win?
Four Go game for an adult and child. Will you be the first to have four numbers in a row on the number line?
A game for 2 or more players with a pack of cards. Practise your
skills of addition, subtraction, multiplication and division to hit
the target score.
A game for 2 people. Use your skills of addition, subtraction, multiplication and division to blast the asteroids.
A number card game for 2-6 players.
Use your addition and subtraction skills, combined with some strategic thinking, to beat your partner at this game.
In this matching game, you have to decide how long different events take.
In this game for two players, the idea is to take it in turns to choose 1, 3, 5 or 7. The winner is the first to make the total 37.
A game somewhat similar to 'noughts and crosses' on a much larger
Try this matching game which will help you recognise different ways of saying the same time interval.
You'll need two dice to play this game against a partner. Will Incey Wincey make it to the top of the drain pipe or the bottom of the drain pipe first?
In this game for two players, the aim is to make a row of four coins which total one dollar.
A game for two players. You'll need some counters and somewhere to draw a board.
A game for 2 or more players. Practise your addition and subtraction with the aid of a game board and some dried peas!
This is an adding game for two players.
A game for 2 players. Using 2 dice, some counters and a games board, can you form a line of counters from one side of the board to the other?
Shut the Box game for an adult and child. Can you turn over the cards which match the numbers on the dice?
A fun puzzle with tantrix tiles.
Have a go at this game which involves throwing two dice and adding
their totals. Where should you place your counters to be more
likely to win?
An old game but lots of arithmetic!
A game played with a standard pack of cards.
A game for 2 players. Practises subtraction or other maths
operations knowledge.
A game for 2 people. Take turns placing a counter on the star. You win when you have completed a line of 3 in your colour.
Nim-7 game for an adult and child. Who will be the one to take the last counter?
Strike it Out game for an adult and child. Can you stop your partner from being able to go?
Incey Wincey Spider game for an adult and child. Will Incey get to the top of the drainpipe?
A game that tests your understanding of remainders.
The game uses a 3x3 square board. 2 players take turns to play,
either placing a red on an empty square, or changing a red to
orange, or orange to green. The player who forms 3 of 1 colour in a
line. . . .
A game for 2 players. Take turns to place a counter so that it occupies one of the lowest possible positions in the grid. The first player to complete a line of 4 wins.
A game for 1 person to develop stategy and shape and space awareness. 12 counters are placed on a board. Counters are removed one at a time. The aim is to be left with only 1 counter.
Here is a version of the game 'Happy Families' for you to make and
Play this well-known game against the computer where each player is
equally likely to choose scissors, paper or rock. Why not try the
variations too?
Solve this Sudoku puzzle whose clues are in the form of sums of the
numbers which should appear in diagonal opposite cells.
A game for 2 players. Draw a daisy with at least 5 petals. Shade 1 or 2 petals next to each other. The winner shades the last petal.
A complicated game played on a 9 x 9 checkered grid.
Design your own scoring system and play Trumps with these Olympic Sport cards.
This is a game for 2 players. Each player has 4 counters each, and
wins by blocking their opponent's counters. A good follow-on from
two stones.
Can you make the birds from the egg tangram?
First Connect Three game for an adult and child. Use the dice numbers and either addition or subtraction to get three numbers in a straight line.
Hover your mouse over the counters to see which ones will be
removed. Click to remover them. The winner is the last one to
remove a counter. How you can make sure you win?
A game for two players. You'll need some counters.
A game for 2 people that everybody knows. You can play with a
friend or online. If you play correctly you never lose!
An odd version of tic tac toe


text:
presented by Pat Newman, firstname.lastname@example.com
Workshop Number: CC-F-285
Location: E-225
Instead of typing at people, show them what you're talking about instead. Jing is free software that adds visuals to your communications. You can snap a picture of your screen or record video of onscreen action, and then share it instantly over the web, IM, or email. See how I have been using Jing to comment on student homework, explain concepts, and provide custom individualized video tutorials to answer student questions. Here is a sample: How to change the color of a chart in Word 2007


text:
Oklahoma Senior
40: 4.59
PROS: Has good speed and athleticism. Can make plays in pursuit and moves well in space. Shows closing burst to make stops in pursuit. Has good hips and is able to turn and run with receivers in the slot. Shows nice awareness in zone coverage.
CONS: Undersized linebacker that doesn't always do a great job breaking down at the point of attack and will whiff on some stops in the open field.
OVERVIEW: He was mainly a coverage linebacker that is a bit of a tweener at linebacker and safety. A very productive two-year starter that combined for 159 tackles, 16.5 for loss, 6 sacks, 3 picks, 14 pass breakups, 8 forced fumbles, and 2 recoveries in those years.
NFL FORECAST: Right now he's a tweener that I think could make a move to safety on the next level. If he's going to stay at linebacker he's going to need to bulk up. I would compare him with Cato June, and in a Dungy-style defense that likes to have fast, rangy linebackers and drop them back into coverage a lot, he can work. He'll never be a great run defender even if he does get bigger, but he can be a competent WILL linebacker like June was in Indianapolis. As a safety, he'll work best in a scheme that likes to bring him up to play in the box at strong safety, but he should be able to match up in coverage with backs, tight ends, and the occasional NFL wide receiver. He's a bit of a work in progress there, but within two years he could be good enough to be a capable starter. I don't see him as a great safety, but could be a competent starter for a few years in the right scheme. Probably most likely however is that he stays at linebacker, bulks up a little and specializes as a nickel guy. But due to the ever increasing need for versatile starters that can play all three downs, linebackers that just play in coverage aren't as common today as they were 5-10 years ago, so I'm not sure how prevalent that niche is. He shoudl at the very least be a capable NFL backup that if he can play well on special teams early in his career, can develop down the road into a decent, albeit limited starter at linebacker.
ATL FORECAST: You like Clayton in Atlanta mainly because he could immediately come in and be the team's best cover guy at linebacker. He'll need at least a full-year to bulk up before you can expect him to make significant contributions on defense. Eventually he probably fills a similar role as Coy Wire does that can function in situational football like in goalline situations where you pull a defensive back off the field to beef up the right, but still want a guy that can cover in case the offense passes the ball. He's probably not a starter, at least not long-term, but because he can play in coverage, he would be a decent WILL linebacker in our scheme.
VALUE: Because of his limited potential as a starter, Clayton probably shouldn't be taken higher than the fourth round as a linebacker. For a team interested in moving him to safety, probably take him a round later just because of the extra time it takes for him transition.
1-poor, 2-weak, 3-above average, 4-very good, 5-elite
Keenan Clayton, OLB, Oklahoma
Scouting reports of outside and inside linebackers in the 2010 draft.
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Keenan Clayton, OLB, Oklahoma
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Mixed Signal
I/O companions optimized for high-speed automotive infotainmentFebruary 17, 2015 10:38 am | by Microchip Technology Inc. | Microchip Technology Inc. | Product Releases | Comments
Microchip Technology Inc. announced the world's first H.264 video I/O companion integrated circuits (ICs) optimized for the proven and robust Media Oriented Systems Transport (MOST) high-speed automotive infotainment and Advanced Driver Assistance Systems (ADAS) ...LISTED UNDER: Mixed Signal
Sensor Signal Conditioning IC'sJuly 24, 2013 1:44 pm | Servoflo Corporation | Products
Analog & mixed signal IC's. Sensor signal conditioning IC's for analog-analog or analog-digital conversion. For capacitive and resistive bridge sensors.LISTED UNDER: Mixed Signal | Signal Conditioning


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working hdmi sound or completely disable it
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Posts: 5
working hdmi sound or completely disable it
This has been an incredibly annoying night. My old hd tv died and was replaced with a new Samsung A550. I am running mythtv and everything was working beautifully before i changed tv's. I was running hdmi with sound coming from the line out port.
Unfortunately, the new TV is too smart for its own good. Apparently the linux nvidia driver (180.29) is sending a false audio signal. This makes the TV use that instead of the line out cable. (i swear if they make things much smarter NOTHING will work)
I talked to samsung and told me they know the problem but its Nvidia's fault. I tried finding contact information on nvidia's site and they send me to Asus's site. talking to Asus is pointless since this is clearly a software/driver issue.
there appears to be a driver hotfix out for this issue... for windows.
My question is, how do i make the hdmi audio out work in linux (tried about everything already mentioned in this forum)? Or if its easier, how do i keep it from detecting the hdmi out chip so it wont send the ghost signal. I'm not looking for hi-def here. I'm also not above mutilating a hdmi cable assuming the sound channels are carried on separate wires and are not multiplexed into the video signal.
I just want to get back to where i was before this nightmare.
my machine is set up as follows:
Mythbuntu (ubuntu) 8.10
M3n78 PRO with nvidia 8300 chipset.
AMD x2 64bit 6000+
Pinnicle 800i tuner
PVR-150 tuner.
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1821 25C MS66 Prooflike NGC. B-4, R.3....
2012 August 2-5 US Coins Signature Auction- Philadelphia #1173
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|Auction Ended On:
|Aug 3, 2012
|Item Activity:
6 Internet/mail/phone bidders
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Sheraton Philadelphia Downtown Hotel
201 North 17th Street
Philadelphia, PA 19103
|Printable auction results for all items in the 2012 August 2-5 US Coins Signature Auction- Philadelphia.
1821 Prooflike Quarter, MS66, B-41821 25C MS66 Prooflike NGC. B-4, R.3. Mint records indicate 216,851 quarters were produced in 1821, but Steve Tompkins notes in Early United States Quarters 1796-1838 that "due to the use of 1820 dated dies, the total amount of 1821 dated coins is less than the stated mintage would suggest." This example is remarkably preserved for a coin nearly two centuries old, sharply struck with no marks worthy of note. Reflective fields are edged with taupe patina that highlights silver centers on both sides. Circulated early Capped Bust quarters are not plentiful, and Mint State examples are rare. NGC has certified just three pieces as MS66 (not distinguished by variety or Prooflike status), and only one finer (6/12).(Registry values: P2) (NGC ID# 23RM, PCGS# 5331)
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We are pleased to offer a remarkable 2013 Lamborghini Gallardo LP550-2 Spyder with low mileage, an accident free Carfax and only one previous owner... More
- Pearl Yellow with Black leather interior- Believed to be 11,000 miles- Navigation, reverse camera- $10,000 upgraded special build wheels- Recent clutch service- Silver... More
- New ceramic clutch kit- Brembo brakes with slotted rotors- Performance exhaust systemTo be sold at the Harrisburg 2015 auction, Harrisburg, PA, -August 1,... More
- 3,124 actual kilometers- Won Amelia Island ?Lamborghini Best in Class Vintage? March 14, 2015 Festivals of Speed- As a 1990 carry over,... More
- Only 328 LM002s produced between 1986-1992- One of only 48 produced for U.S. market in 1990- Two owner car- Believed to be 16,886... More
2011 Lamborghini Gallardo SUPERLEGGERA TWIN TURBO For Sale…. Loaded car from the Factory with Ceramic Brakes, Full interior Carbon Pkg, Navigation, Reverse Camera, E-Gear Transmission,... More
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In 1969, Lamborghini improved their 2+2 with numerous changes including a slightly more powerful 350bhp V12 engine. With many upgrades to the mechanics, aesthetics,... More
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About us?
Situated on a hill right nearby the sea, this hotel is surrounded by banana and palm trees. It offers a private beach area, free Wi-Fi and airconditioned accommodation with panoramic sea views.
The rooms at boutique hotel Dolphin come with a private bathroom with hairdryer. They all feature a balcony with excellent sea views. Some suites offer a spa bath (whirlpool) and turkisch bath.
Daily breakfast is served in buffet style. You can enjoy your meals such as seafood and traditional Aegean cuisine served in the restaurant accompanied by panoramic sea views, the hotel also has a bar.
You can relax at the traditionally decorated lounge at Dolphin boutique hotel, the front desk is available 24/7. Roomservice can also be provided.
Only 8 km. from Selimiye Bay, pet friendly Dolphin hotel is a 1-hour drive to Marmaris city centre. Dalaman airport is a 2,5-hour drive away.


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Brunner and Lucena finish fourth at Beach World Champs
USA has seven teams finish in the Top 25, four in the Top 5
SCVC 17s Strikes Gold on Final Day of BJNC
The 2015 Boys' Junior National Championships concluded on July 5 after naming the 13 Club, 17 Open, and 17 Club Division Champions
Vansant Sparks U.S. Women to Sweep of Belgium
Team USA improves to 3-0 in FIVB World Grand Prix
USAV Releases Men's Pan Am Games Roster
AJ Nally to serve as team captain; Charlie Sullivan as head coach
Tickets and Events
2015 FIVB World Grand Prix Finals
Purchase tickets for the World Grand Prix Final Round July 22-26 in Omaha, Neb.
Where you can watch USAV this summer
June 1-14: MNT at World League, WNT at USAV Cup. TO COME: beach grand slams on TV, indoor men's and women's national teams and junior events in the U.S.


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Privacy and Cookies
Panasonic Avionics has set the initial pricing scheme for its eXConnect connectivity service, which will give passengers access to broadband Internet and live television.
The in-flight entertainment (IFE) giant is setting prices at $21.95 for 24 hours of use of the Ku-band-based connectivity service or an hourly rate of $11.95.
As fleet roll-out improves, however, Panasonic expects to "get prices down from there", Panasonic vice-president, global communications services David Bruner revealed in an interview with Space News.
The firm will also offer pricing for 30 minutes of use of eXConnect in regional markets, as well as a reduced pricing model for simple texting.
Monthly subscriptions for heavy users of the service will also be made available.
GSM mobile phone access is expected to play a significant role in the eXConnect model. "We expect it will be around 50% of the revenue and only a small percent of the total system cost, judging from our experience so far," says Bruner.
"What the airlines are thinking about is allowing mobile phone access for, say, the first couple of hours of a flight, and then shutting off that service. The broadband and messaging access can continue. This is done automatically so you almost make system operation independent of the crew."
Panasonic recently revealed it has secured an initial customer base of five airlines for eXConnect - two from Europe, two from Asia and one from Africa. Installation on the first major customer will occur late in the calendar year of 2009 following a trial on a 737 Boeing Business Jet (BBJ).
Sources say Lufthansa intends to offer eXConnect on its overseas aircraft, which are already equipped with now-commercially-defunct Connexion by Boeing's system. Neither Panasonic nor Lufthansa has confirmed the relationship.
However, when asked by Space News if Panasonic will use any of the hardware that was developed for Connexion, Bruner says: "For one customer we are using Connexion antennas. They are not as good as the antennas we are developing [with partner EMS Technologies] but we're going to take advantage of the existing development."
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text: Alley Reflects New Delhi's Class War September 30, 2005 India's past and future clash in a New Delhi alley. Two blocks of tall apartments full of middle-class residents loom over a rat-infested slum filled with men, women and children who have migrated to the capital from the countryside in search of work. Listen Loading… Playlist Download Embed Embed Close embed modal <iframe src="http://www.npr.org/player/embed/4931617/4931618" width="100%" height="290" frameborder="0" scrolling="no">


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In an effort to promote good habits, Colorado educators Thursday recognized 11 state school districts and two schools that have taken steps to make healthy food and exercise as important to students as learning the ABCs.
Five years ago, students in the Durango School District began examining their strengths and weaknesses when it came to nutrition and health issues. Since then, educators and parents have made health a priority.
"The district and community joined forces, and a lot of hard work resulted in a very positive thing for us," said Keith Owen, superintendent of Durango schools, one of the recognized districts.
The Department of Education awards grants to help districts along the way. Thursday's second annual Commissioner's Choice Awards for innovation in health and wellness was part of an all-day Denver conference, "Healthy Kids Learn Better," that covered topics on nutrition, school health services, physical activity and comprehensive district health policies.
"We need to focus on the whole child," said Colorado Commissioner of Education Dwight Jones.
Jones was joined by Lt. Gov. Barbara O'Brien. The event was hosted by the Colorado Legacy Foundation, a nonprofit that surveyed schools and offers a health and wellness best-practices guide to Colorado's 176 school districts.
"Eighty-seven school districts have signed up as of yesterday; that's 83 percent of students enrolled," said Helayne Jones, executive director of the Colorado Legacy Foundation.
Many of the schools and districts recognized Thursday are doing a variety of things to get kids healthier. Some serve organic foods, while others encourage physical activity inside and outside the classroom. Some grow their own vegetables, while others create meals made from scratch.
Schools and school districts honored for this year's Commissioner's Choice Awards were:
High Point Academy in Aurora, Gunnison High School, Adams County District 14, Boulder Valley, Denver Public Schools, Douglas District RE-1, Durango District 9-R, East Grand School District 2,Garfield District RE-2, Las Animas District RE-1J, Montrose, Pueblo District 60 and Poudre District R-1.
"Healthy kids have their needs met and they perform and learn better," Owen said.
Annette Espinoza: 303-954-1655 or firstname.lastname@example.com


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Product Information
Walking In the Air from The Snowman - Digital Sheet Music
from The Snowman
At a Glance
Walking In the Air digital sheet music. Contains printable sheet music plus an interactive, downloadable digital sheet music file.
* This arrangement contains complete lyrics
* This product is available worldwide
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The Arrangement Details Tab gives you detailed information about this particular arrangement of Walking In the Air - not necessarily the song.
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The Song Details Tab gives you detailed information about this song, Walking In the Air.
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Queen's Crescent Market
|Kentish Town, Camden, Greater London
|51°32′56″N 0°09′12″W / 51.5488°N 0.1534°WCoordinates: 51°32′56″N 0°09′12″W / 51.5488°N 0.1534°W
|Queen's Crescent
|Camden London Borough Council
|Camden London Borough Council
|Goods sold
|General goods
|Days normally open
|Thursday, Saturday
|Number of tenants
Queen's Crescent Market is one of London's oldest street markets, and is still held every Thursday and Saturday on Queen's Crescent in Kentish Town, Camden. The market sells food, discounted clothing and a wide variety of household products. It has capacity for more than 90 stalls.[1]
Many traders run stalls that have been passed from generation to generation. This is in contrast to the nearby and considerably more famous Camden markets, which primarily attract tourists and those from other parts of London (Inverness Street Market was a traditional produce market in Camden Town for a century, but in 2013 the last produce stall closed, leaving only tourist stalls like the other Camden markets[2][3]). Aesthetically Queen's Crescent market is a mixture, with pretty plain white houses sitting side by side with large council estates, some of which sit in beautifully landscaped grounds.
- ^ "Queens Crescent Market". National Market Traders Federation. Retrieved 16 November 2013.
- ^ "Camden's oldest market in Inverness Street 'could go under'". Camden New Journal. 11 February 2010. Retrieved 16 November 2013.
- ^ "Fruit & veg to be missed". Camden New Journal. 16 May 2013. Retrieved 16 November 2013.
External links[edit]


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4GB or 8GB? (for an AMD system)
I'm still thinking on how much memory I should get for my system, when I build it, that's it, I'm just doing some planning for now...
The thing is... DDR3-1333 got quite cheap here in Spain (at least) and I can get an 8GB kit of DDR3-1333 (2x4GB) @ CL9 / 1.50V from Exceleram (with the Blue Culvert heatspreaders) for around 117 euros, and around half that price for 4GB (2x2GB) on the same settings (CL9 / 1.50V).
So far, with all the games I have, no problems related to lack of memory... and I doubt the coming games like F.E.A.R. 3, Deus Ex: Human Revolution, BRINK and many others will really ask for more than 2/2.5GB of physical memory, but still...
for making a future-proof system (or as future-proof as I can) 8GB would be the ideal option, but I'm also on a relatively tight budget and I don't want to spend more than the strictly necessary with a bit of future proofing.
So... what do you think? Will 4GB suffice for some time (at least for games coming in 2011) or should I really strive for those 8GB?
Re: 4GB or 8GB? (for an AMD system)
As long as games stay mostly 32-bit, there's no need for more than 4GB of memory. Once games move on to 64-bit natively, then we'll probably need 8GB. I have 8GB of my system, and I've never been able to run the memory up above 3.5GB.
You're probably fine with 4GB at the moment.
Re: 4GB or 8GB? (for an AMD system)
I've also got 8gb in my rig and have a hard time using more than 4gb at once. That being said you are going to want to install a 64bit os, simply because the memory addressing limitations of 32bit.
Re: 4GB or 8GB? (for an AMD system)
Don't bother, because their is a filter on everything to keep everyone in choice, even among those still
on a 32 bit platform. Full 64 bit only gaming is still years ahead, and we had this question before, so the verdict is still in, stay with 4 for now.
Re: 4GB or 8GB? (for an AMD system)
Honestly- I'd max the RAM out.
Maybe I multi-task more than others, but I can quite easily fill the 4GB of RAM I have now. Which is why I'm stuck using a pagefile. :( I'm planning a rather large over haul of my rigs, and part of that is gonna' be maxing it at 16GB. I don't wanna' have to use a page file for quite some time. :D :p :lol:
Re: 4GB or 8GB? (for an AMD system)
Re: 4GB or 8GB? (for an AMD system)
You can do whatever you want with your money, I prefer to go for a cheaper setup, I don't really need 16GB as the only program justifying it would be Photoshop and for the occasional photo re-touching I do, it's not worth the money or the effort (but for me, it's perfectly ok if you want to go for it, you, Redeemed, or whoever is the one doing it).
8GB was my initial thought, and still is... 4GB is what my 'old' system had and I didn't hit the limit with any application but still... I don't want to bite the bullet, so your recommendation is essentially right... 8GB is what I'm probably going to get (as long as I can get my hands on a good offer, I'm not paying more than 150 for the whole lot).
Re: 4GB or 8GB? (for an AMD system)
I know supreme commander can quite happly eat 3.5GB (max for a 32bit application) which does not leave a whole lot for windows. Thats why i am thinking of getting either 2x1GB memory or another 2x2GB PC6400.
Re: 4GB or 8GB? (for an AMD system)
A 2Gb stick of my G.Skill just died and given the prices I just opted for 2x4Gb.
I would rather have and not need. Besides, if a stick of this kit dies I still have 4Gb left.
Redundancy ftw. :)
Re: 4GB or 8GB? (for an AMD system)
Re: 4GB or 8GB? (for an AMD system)
My dead ram will go out after I have something to replace the last stick with...see how simple that is?
Re: 4GB or 8GB? (for an AMD system)
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CHARLESTON, S.C. - Headliners have been announced for the inaugural St. Simons Food & Spirits Festival, which will be held Sept. 21-23 on St. Simons Island.
Litter is not just ugly; it has major consequences for all of our pocketbooks.
Bring your BFF out for some miniature golf during our Girlfriends Day from 11:30 a.m.-7 p.m. Aug. 24 at Cypress Creek Adventure Golf. Buy one game at regular price and your friend gets a game free. For more information, call 767-4273.
The Jubilee Choir seniors of First Baptist in Hinesville sang to the Goldenheirs during their monthly meeting July 3.
Joe Gillam of Hinesville took the Courier along as he drove more than 1,000 miles of U.S. Highway 84 from Hinesville to West Texas.
Members of the Atlanta Symphony Orchestra will join the Geechee Gullah Ring Shouters to perform "Songs of the Georgia Sea Islands" at 7 p.m. Saturday, Aug. 18, in the Archie B. Myers Sr. Fine Arts Center in Darien.
Even though it had a false start, Hinesville's annual observance of National Night Out took place Friday evening on Central Avenue without the threat of rain that forced its rescheduling Aug. 2.
HINESVILLE: Liberty Stadium Cinemas
TYBEE ISLAND, Ga. (AP) - Officials on Tybee Island are exploring the idea of using a bed tax from hotels and motels to pay for adding sand to its beach.
ARIES (March 21 to April 19) As eager as you are to take on that new challenge, it would be best to temper that spurt of "Ram"-bunctious energy until you have more facts to back up your decision to move.
The Coastal Courier traveled with Shane Amason when he attended the Billy Lancaster Forestry Youth Camp at the Georgia FFA/FCCLA Center in Covington while on summer vacation. Amason was one of 38 kids invited to attend this camp to learn more about Georgia Forestry.
Registration is underway for children selected through a lottery to attend a state-funded pre-K program at one of the two Fort Stewart Child Development Centers.
The Art of War may have ancient Chinese roots, but a new Hinesville Area Arts Council exhibit shows that some today see war strategy and depictions as a craft.
The first time I heard of figs was in church. Adam and Eve sewed fig leaves together for garments after they ate fruit from the forbidden tree. The word fig appears in the Bible 50 times.
We Americans are pretty trashy. No, I am not talking about the Hollywood celebrities who represent us so well on the global scene - although many of them are pretty trashy, too. We Americans generate a lot of garbage. Although we only represent 5 percent of the world's population, we generate more than 30 percent of the world's garbage, according to the National Recycling Coalition. Their estimates range from 4 pounds to a whopping 7 1/2 pounds of trash generated per person per day in our country. Trash is produced at an alarming rate of 1,609 pounds ...
Bobby Batson of Richmond Hill will be on the TV show "700 Club" on Tuesday to promote his upcoming movie, "90 Minutes in Heaven".
Liberty County native and musician Dakota Woods will play at 6 p.m. Sunday at Johnny Harris Restaurant on Victory Drive in Savannah as part of the Savannah Songwriter Series.
The Hinesville Downtown Development Authority recently had a food drive for the Manna House.
Every state has "cowboy toilet paper" growing somewhere in it.
Dr. Peter Martin loves animals.
In Chatham County, just outside Bloomingdale off Highway 204, there is a property with an old house, horse stables, an arena and a barn.
Daisy Jones, the city of Hinesville's Homeless Prevention Program coordinator, walked from table to table, ensuring each vendor was prepared before opening the doors of Bradwell Institute's gymnasium at noon June 6.
It started with the scanning of some old photos for safe keeping.
Last weekend's two-day radio-controlled air show in Liberty County raised more than $1,000 to support Bryan County-based Family Promise.
Clifton and Linda DeLoach recently donated a truckload of Vidalia onions to the Long County 4-H Club to be sold to as a fundraiser. DeLoach, who is a Long County commissioner, said the club is always doing good deeds for the county, and he and his wife's annual donation of onions is a small way they help support the club.
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Member since Jun 2013
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Hello Monte,
By chance are you hearing what is going on between MLB and A-Rod? That sure didn't take long.
Lol Monte, spoken like a true attorney. Of course I do not have proof. It is however common knowledge that …
No chance at all he catches Jack! The steroids and blood transfusions are a thing of the past since the …


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A ton of these periodic cicadas "emerged" in our yard two nights ago (Williamsburg, VA). Most seem to either be dead or gone by the morning today. Haven't seen any elsewhere in town. Not sure if the ones in my yard are just just a bit early (I would guess they are part of the 13-year "brood" XIX - which is due this year), of if some other odd thing is going on.
Shot with my garage sale, reversed Reversed 28mm f2.8 Series E.
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