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13 years of experience
Accepting new patients
2850 S Wabash Ave
Ste 100
Chicago, IL 60616 Phone number & directions
A medical license is required for a doctor to practice medicine in a particular state. Requirements vary by state but most require, at a minimum, post-graduate training in the doctor's specific specialty. An NPI number is a national identifier unique to an individual health care provider and is managed by the Center for Medicare & Medicaid Services (CMS).
Learn more about Dr. Robert Strugala:
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Patient Reviews
The overall average patient rating of Dr. Robert Strugala is Excellent.
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Dr. Robert Strugala, MD is board certified in Internal Medicine and Internal Medicine - Sports Medicine.
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Dr. Strugala graduated from Northwestern University, Chicago.
Dr. Strugala has 4 hospital affiliations:
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- Dr. Robert James Strugala MD is a male Sports Medicine, has 13 years of experience and practices in Internal Medicine, Sports Medicine, and Sports Medicine.
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- Dr. Robert Strugala has 5 office locations.
Dr. Robert Strugala practices Internal Medicine, Sports Medicine, and Sports Medicine near Chicago, IL.
Additional practice locations include: Hometown, IL and Evanston, IL.
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Medient Studios, Inc. Announces Reverse Split and Name Change
Medient Studios, Inc. today announced that the Board of Directors of the Company has approved a 1 for 1,000 reverse stock split of the Company's issued and outstanding common and preferred stock. The Board also approved a name change to "Moon River Studios, Inc."
The name change and reverse split will take effect upon Compliance by the Company with applicable regulatory requirements.
About Medient Studios, Inc.
Medient Studios, Inc. (PINKSHEETS: MDNT) ("Medient") is a Georgia, U.S. based film production company. In 2013, the Company entered into a lease agreement with the Effingham County Industrial Development Authority ("IDA") whereby it has beneficial ownership of 1560 acres of land in Effingham County. The Company plans to construct motion picture studios and other related amenities on the property for film production. These facilities will include sound stages, production and post production offices, editing suites, warehouses, mills and set fabrication facilities. We refer to this fully integrated film production campus as a "Studioplex."
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subset: commoncrawl


text:
A metallic pellet or seed is physically implanted into the brain in a position where a brain lesion is to be produced. The seed is composed of a metallic alloy of predetermined composition capable of being inductively heated by radio frequency energy. By virtue of the composition of the alloy, the seed reaches but does not exceed a predetermined temperature, and the desired size and degree of lesion is controlled as a function of time during which the radio frequency field is in operation.
Claims available in
Description (OCR text may contain errors)
IJnited States Patent Burton 51 Apr.4,1972
[54] PRODUCTION OF FOCAL BRAIN LESIONS BY INDUCTIVE HEATING 2! Appl. No; 82,366
[52] U.S. Cl... ..l28/303.17, 128/1 [51] Int. Cl ..A6lb l7/36, A6ln 3/00 [58] FieldofSearch ..128/l R, 1.2, 1.3,303.1,303.12,
Seeliger et al ..128/303. 1 7 X Bagley ..l28/303.17
Primary Examiner-Channing L. Pace Attorney-Charles E. Temko [5 7] ABSTRACT A metallic pellet or seed is physically implanted into the brain in a position where a brain lesion is to be produced. The seed is composed of a metallic alloy of predetermined composition capable of being inductively heated by radio frequency energy. By virtue of the composition of the alloy, the seed reaches but does not exceed a predetermined temperature, and the desired size and degree of lesion is controlled as a function of time during which the radio frequency field is in operation.
[56] References Cited 4 Claims, 11 Drawing Figures v UNITED STATES PATENTS 2,888,928 6/1959 Seiger ..128/303.l7
DD-Nl IN CAT OOQTE X PD'78.7 /o C -lO345, CENTER NOQ MAL BLOOD FLOW 6lOKl-lz 8 5 9 0 DOW E R 24 0 F MINUTES Patented C Sheets-Sheet l R THERMOCOAGULATION 430 STAINLESS STEEL IN ALBUMIN MINUTES 430 STAINLESS STEEL IN CAT COQTEX 6IOKHz NORMAL BLOOD FLOW 040345, CENTER 85 /0 DOWEQ 40o CU-Nl l600F pD-Nl Nl-FE (3|.I2) Nl-FE (3!.08)
NI 300 cm I2 00 IN AIR GIOK Hz, 85 POWED C'IO345/ CENTER 200 8 00 O 4O 60 so I00 I20 I I "30200220240 260 250 O SECONDS I600F |54O 800 430 STAINLESS STEEL IN RAT CORTEX 800 NO BLOOD FLOW 040345, CENTER 6IO KHz %POWED 400 MINUTES l 2 MINUTES Patented A ril 4, 1972 3,653,385
3 Sheets-Sheet 2 320F PD-Nl IN ALBUMIN PD-78.7 /o 25C-73.4F DD-Nl IN CAT OOQTEX PD'78.7 /o c|O34-5,CENTER v NOR MAL BLOOD FLOW 610ml 85 /0 DOWEF 24o 240F THERMOCOAGU- 203"F LATION MINUTES MINUTES PD-N| IN RAT CODTEX NO BLOOD FLOW D-78 .7 /o c-l0345, CENTER 6IO KHz 85 /O POWEQ PRODUCTION OF FOCAL BRAIN LESIONS BY INDUCTIVE HEATING This invention relates generally to the known art of radio frequency thermo-coagulation of human tissue, and more particularly to improved means and methods of thermo-coagulative neurosurgery.
BACKGROUND OF THE INVENTION With the advent of modern neurosurgery, the surgeon has gained access to the depths of the brain. In the past few decades, a great effort has been expended in the attempt to find a safe and effective means for producing controllable subcortical lesions. The need for this is as great as the spectrum of disease potentially amendable to such therapy. Such conditions include movement disorders, of which Parkinson's Disease is an example, intractable pain, focal epilepsy, various vascular malformations, and certain cancers, such as those arising from the breast and prostate, where palliation may be achieved by hypophysectomy.
Many imaginative lesion-producing techniques have been developed, but so far none has been entirely satisfactory. Most of the systems developed have necessitated physical connections from an external energy source to a probe or electrode, which could not remain in place over a period of time without the risk of infection. The major disadvantage of other systems, such as proton beam radiation, focused ultrasonics, lies in their destruction of normal brain tissue as well as that in the target area.
Induction heating is a well-established industrial method which permits the rapid and clean through-heating, melting, or precise surface hardening of metals by an external alternating electromagnetic field. This field induces currents in the metal eddy which are opposed by the resistance of the metal, resulting in the generation of internal heat. A second effect adding to the dissipation of energy as heat is the induction of hysteresis loops for the alternation of the magnetic poles within the metal. No physical contact between the source of electromagnetic energy and the metal is required.
In the present state of the art, it is known that if a small piece of appropriate metal is implanted into the brain, and the head then introduced into an electromagnetic induction field of radio frequency, the implanted metal can be heated at a frequency and power level innocuous to the body and brain tissue. In addition, it is known that the heating can be accomplished in increments over a period of time, as required to achieve the desired lesion.
A typical utilization of the known art involves the use of an industrial induction generator operating in the 300-400kc/s range with a plate power input of up to 23kw is modified for medical application, to include an elliptical single-turn onefourth inch by one-half inch water-cooled copper coil, so that human heads can be accommodated. The induction coil current flow is approximately 500 amperes. Insulation of the coil is required to prevent radio frequency burns, and a suitable plastic resin compound is utilized for this purpose and applied in dip coats.
In the industrial use of induction heating, in which the mass of metal is large and lies in close approximation to the coil, the efficiency of the system approximates 60 percent, owing to a relatively efficient coupling". In neurosurgical applications, the efficiency of the system ranges from 0.1 percent to 0.001 percent because of the small mass of the implant and its distance from the coil.
When an alternating current is induced in metal, the unique properties of induction heating apply. One of these properties is the skin-effect phenomenon where the current flow and heating are concentrated near the surface of the metal and fall off exponentially toward the center. This skin-effect is enhanced at higher frequencies. In a 300-400 kc/s range, an intense, fast, and localized heat pattern can be produced. This frequency, at the power level used, is innocuous to living tissue. In the evaluation of lesions in over 200 experimental animals and 12 human beings, there has been no observable effect of the RF induction field on anything other than the implant.
The ideal metallic implant, which can be termed an electroseed, must be composed of a material that will beat well, but neither react nor cause reaction in brain tissue, and be of suitable size and shape for surgical implantation. It is known that some intracerebral missile fragments tend to migrate through the brain over a period of time, but in the case of electroseeds, this behavior does not occur. Unheated electroseeds have been observed to remain in position after follow-up periods as long as two years. After the production of a lesion, pathologic examination reveals that the electroseeds are quite anchored by surrounding thermo-coagulated protein.
Subcortical implantation is a simple surgical procedure which is usually perfonned under local anesthesia through a small twist drill hole in the skull. A No. 14 gauge needle is guided freehand or by stereotaxis to the target area. The needle stylet extends beyond the distal end of the needle so that when it is withdrawn, a tissue defect is created. Needle position is verified by polaroid X-ray films or by a fluoroscopic image intensification unit. Air may be injected into the ventricular system to serve as a point of reference. The electroseed is then dropped into the needle and extended from the distal end thereof into the preformed tissue defect.
Following a survey of ferromagnetic metals, iron was found to be the most readily available material for an electroseed. Carbon steels have excellent heating properties, but caused too much tissue reaction. Although this reaction could be alleviated by coatings of teflon enamel or gold, the possibility remains of scratching the protective coating during the implantation. Even alloy steels with a chromium content of over 1 1 percent (stainless steels) undergo a typical rusting reaction if the oxide coat is disturbed ornot allowed to form. The most satisfactory material known in the prior art is type 430 stainless steel having a chromium content of 17 percent. Heating properties have been enhanced by pot annealing the steel at a temperature of 1,600 P. with very slow cooling. Because the electroseed is implanted by extrusion through a needle, it requires a cylindrical or spherical configuration. Experimentation has indicated that solid cylinders with length-to-diameter ratios greater than unity heat more rapidly than spheres, hollow cylinders, or cylinders composed of rolled foil.
In the determination of electroseed parameters related to maximal heating in a radio frequency induction field, the fundamental assumption was made that an electroseed heating in air would bear a constant relationship to one heating in-vivo. Prior to clinical experimentation on human beings, electroseeds have been tested in dummy heads constructed of plastic and filled with gelatin. Heating of the implanted seeds is accomplished by placing the head within the RF-induction coil.
It is known that brain neurons are quite heat sensitive, and that point of contact temperatures over 120 F. destroy the cells. It is therefore essential to produce lesions at contact temperatures high enough to destroy the neurons and coagulate protein, but not so high as to cause liquification of brain tissue. Unfortunately, it is not possible in the present state of the art to accurately predict lesion size and shape, although it is possible to gradually increase the lesion size until the desired clinical result is obtained. In this fashion, patients with intractable pain and motion disorders have been successfully treated.
Several factors influence heat production in the electroseed. Theoretical calculations indicate that the rate of heat generation in electroseeds increases with the diameter of the same under all conditions investigated. The rate of heating increases linearly with the length of the electroseed in the practical range of from 0.5 to l.0cm. There is a consistent increase in the rate of heat generation with increase in magnetic permeability of the metal comprising the electroseed. The rate of heating may increase or decrease with an increase in resistivity, depending upon the combination of other parameters, such as permeability, radius and frequency. Although one might expect that increasing hysteresis loop area would increase electroseed heating, it has been found that following pot annealing with its concomitant decreased hysteresis loop, heating is enhanced. Hysteresis heating is not as significant as that due to eddy currents.
Experimental in-air determinations of electroseed heating in regard to angular orientation of the plane of the coil and radial position in the coil, have been made. It has been determined that heating rate is maximum when the long axis of the electroseed is at an angle of 90 to the plane of the coil, and degrades rapidly to at which time heat production is nil.
BRIEF DESCRIPTION OF THE PRESENT INVENTION One of the principal problems encountered in the practice of the above described therapy is the obtaining of accurate control of the degree of and extent of the coagulation produced in tissue being treated. Since the degree of coagulation obtained is a function of the degree of heat produced by the electroseed, and the amount of time for which the heat is transmitted to the area to be coagulated, it is apparent that the electroseed ideally should be capable of maintaining a reasonably fixed temperature over a substantial period of time, once it has been initially heated from body temperature. Where this is not the case, the heat produced by the electroseed over a given period of time is not only a function of the radio frequency energy supplied and the amount of time over which the energy is supplied, but also a function of how long the seed is heated for a given exposure.
Type-430 stainless steel has been the material used in the past, being the most satisfactory material known. However, it continues to heat with increased power to approximately 2,000 F. in air. The ideal temperature for producing coagulation varies between 150 to 200 F. Since the degree of coupling between the radio frequency generator and the thermoseed is less than 1 percent, it will be readily appreciated that controlling the heat ofthe thermoseed by regulating power supplied by the radio frequency generator is extremely difficult to do in practice.
It is, therefore, among the principal objects of the present invention to provide a thermoseed which will heat only to the desired range in a surplus of radio frequency energy supplied.
Another object of the invention lies in the provision of an improved thermoseed of the class described which will possess all of the advantages of known stainless steel thermoseeds, and which may be fabricated using known techniques.
A further object of the invention lies in the provision of an improved thermoseed of the class described formed from alloys having a predetermined Curie point within the desired range for effecting coagulation.
In the drawings,
FIG. 1 is a graph showing the heating with time of electroseeds formed from various alloys in air in the presence of excess radio frequency power.
FIG. 2 is a graph showing the heating of type 430 stainless steel in albumin.
FIG. 3 is a similar graph showing the heating of type 430 stainless steel in rat cortex.
FIG. 4 is a similar graph showing the heating of type 430 stainless steel in cat cortex with normal blood flow.
FIG. 5 is a graph showing the heating of a palladium nickel alloy in albumin.
FIG. 6 is a similar graph showing the heating of the same alloy in rat cortex with no blood flow.
FIG. 7 is a similar graph showing the same palladium-nickel alloy heated in cat cortex with normal blood flow.
FIG. 8 is a similar graph showing the heating of a copper nickel alloy in albumin.
FIG. 9 is a similar graph showing the heating of a nickelchromium alloy in albumin.
FIG. 10 is a similar graph showing the heating of a nickeliron alloy in albumin.
FIG. 11 is a similar graph showing a slightly different nickeliron alloy heated in albumin.
Referring to FIG. 1 in the drawing, it will be understood that the illustrated examples are for purposes of illustration only, and not to be construed as limiting with respect to the extent of the present invention. It will be observed that when heated in air, the Curie points of each alloy are reached within a range of 60 to 200 seconds after the supply of power is initiated, and in each case is above 300 F., or far in excess of the desired operative temperature of to 200 F. Although the initial rise in temperature is relatively rapid, it will be apparent from a consideration of the graph that the total amount of heat transmitted for purposes of coagulation is much less during the first 20 seconds than during the second 20 seconds in each case. Excess operating temperature is reached in each case within the first 20 seconds. The highest temperature reached is 400 F., with the copper-nickel alloy.
This performance can be contrasted with the showings in FIGS. 2 to 4 in the drawings. Type 430 stainless steel, the most widely used of the known materials in the art, heats almost instantaneously to 800 F., and within a minute reaches l,500 in albumin, a protein material. Using the same material in rat cortex and cat cortex, heats as high as l,900 are obtained within 3 minutes.
FIG. 5 illustrates a similar experiment substituting a thermoseed formed of an alloy consisting of by weight 78.7 percent palladium, and the remainder nickel. When immersed in albumin, the Curie temperature of approximately 230 F. is reached in 20 seconds, and the temperature remains substantially constant thereafter, until 2 minutes has elapsed.
In FIG. 6, placing a thermoseed of this alloy in rat cortex with no blood flow, results in a substantially constant Curie temperature of 206 F., a very usable value.
As seen in FIG. 7, in cat cortex, with normal blood flow, a still more usable value of 203 F. is obtained.
FIG. 8 illustrates the heating of a copper-nickel alloy thermoseed, the copper forming 25.8 percent by weight of the alloy. It will be observed that heating in this case to the Curie point requires 3 minutes, and a maximum of approximately 290 is reached at that point. However, because of the lack of flatness in the heating curve, this alloy is less desirable than other alloys described herein.
FIG. 9 illustrates a nickel-chromium alloy, in which nickel comprises 93.75 percent by weight of the alloy. Here, the albumin test reveals that the thermocoagulation temperature is reached after approximately 1 minute, and the temperature continues to rise relatively slowly thereafter until approximately 10 minutes, at which point the temperature exhibits a marked drop.
FIG. 10 illustrates a nickel-iron alloy, nickel comprising 31.12 percent by weight of the alloy. Coagulation temperature is reached in approximately 30 seconds, and maximum temperature is approximately 300, again in albumin, a sharp drop again being exhibited after 5 minutes.
FIG. 11 illustrates a slightly modified nickel-iron alloy, in which the nickel comprises 31.08 percent by weight. Here thermocoagulation temperature in albumin is reached almost instantaneously, and maximum temperature of approximately 330 is reached after 9 minutes. However, the rise in temperature is erratic, exhibiting heat loss between 3 and 4 minutes, and between 6 and 8 minutes over somewhat similar patterns.
In the determination of electroseed parameters, related to maximal heating in an RF-induction field, the fundamental assumption was made that a given electroseed heating in air would bear a constant relationship to one heating in-vivo. Early comparative in-air testing was performed using a simple alcohol thermometer to record temperature. The more precise determinations of variation in heating in albumin and rat and cat cortex were performed using a 35 gauge spirally wound copper-constantan thermocouple connected to a grass model 5 polygraph with a Model 5 PSC dc preamplifier. The thermocouple itself was not heated by the RF field. Prior to clinical experimentation on human beings, electroseeds were tested in dummy heads constructed of plastic and filled with gelatin.
Thus, the pattern of heating of the alloys illustrated in FIGS. 8 through 111, inclusive, may be reasonably expected to be duplicated at substantially lower temperatures in cortex, with reasonable utility from the standpoint of obtaining relatively flat portions ofcurves in the desired thermocoagulation temperature range. With ,the temperature of the thermoseed maintained at a useable level, the control of the formation of the lesion is more closely regulated to the exposure time within the RF field, a value which can be simply determined by stop-watch, and controlled by interrupting the flow of current to the RF generator. Operating in this manner, the RF generator may be allowed to supply an excess of power to the thermoseed, and the presumption is made that the thermoseed will very quickly be operating at its Curie point.
For practical and convenient testing, I have found that operating the thermoseed in albumin maintained at 30 C. (78.75 F.), a very close approximation can be made of its behavior in brain cortex with normal blood flow. This may be conveniently done by immersing a basin containing the albumin in a temperature controlled bath. Comparing FIGS. 5, 6 and 7 in the drawing, using a palladium-nickel alloy, it will be observed that the Curie point in albumin is approximately 238 F, The Curie point in rat cortex with no blood flow is 206 F and in cat cortex with normal blood flow is 203 F. Thus, the actual difference is approximately 30 F., which can be taken into account insofar as the predicted Curie temperature in brain cortex with normal blood flow is concerned. This relationship has been firmly established in multiple experiments and designates the albumin standard as a basis for accurate detennination of thermoseed heating in brain tissue.
I wish it to be understood that I do not consider the invention limited to the precise details shown and set forth in this specification, for obvious modifications will occur to those skilled in the art to which the invention pertains.
I claim:
ll. In the method of producing a lesion in living brain tissue by inserting a thermoseed into the tissue in the area where the lesion is required, and subjecting said thermoseed to an externally produced radio frequency field, the improvement comprising: implanting in living brain tissue an electroseed formed of a metallic alloy having a physiologic Curie point of approximately 238 F. as measured in an albumin standard solution, and utilizing this implant .to produce coagulative lesions in brain tissue in a temperature range of 1 10 through 212 F.
2. As a new article of manufacture, a brain implant for producing coagulative lesions composed of a metallic alloy, said alloy comprising at least 18 percent nickel by weight and the balance selected from the group consisting of chromium, palladium iron and copper and having a Curie point in air between 250 and 300 F.
3. A brain implant in accordance with claim 2, composed of an alloy comprising 18 to 24 percent by weight of nickel.
4. An electroseed in accordance with claim 2, composed of an alloy consisting of approximately 78.7 percent palladium by weight, and the balance nickel.
Patent Citations
Referenced by
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Welcome to our 1830 historic manor in the heart of the Shenandoah Valley! Come visit our bed and breakfast and enjoy modern updates while cherishing the unique history and the fine antiques the house has to offer.
Score Breakdown based on
15 Reviews
5 on April 21, 2015
Our stay at Cave Hill Farm was great! The bed was comfy, room and bathroom were clean. Breakfast was simple and home cooked with fresh fruit. The home is beautiful and filled with history. Hannah and Omar were very polite and friendly as well. We plan to go back next winter! Thanks for everything!
5 on April 06, 2015
Lots to love! We were looking for a nice place somewhat close to JMU and the wineries to the east, and this was - without being too close. The farm looked lovely, and the historic home was full of interesting artifacts, photos and stories. Take a look in the basement for all sorts of interesting antiques! Lots of history here. Food - very nice breakfast and excellent service. Omar and Hannah we very accommodating. Take a drive, come relax and enjoy the nearby hikes, wineries anr more!
4.4 on February 19, 2015
Thank you for the hospitality. Charming home, comfortable room, delicious breakfast- this was a great place to stay before our JMU tour- close by and the price is right.
3.4 on March 18, 2014
Our hostess was sweet. Was surprised we had to ask for "goodies" on our arrival. Breakfast was good, but at first we were served sour creamer to put in our coffee- when pointed out she had "good stuff" for replacement readily available
5 on February 28, 2014
This was the first time we stayed at this particular B&B. We had a wonderful but too short visit. The home is beautiful and Hannah and Omar are very nice. We definitely hope to return sometime. Diane
5 on January 22, 2014
It is a fine line to walk when running a bed and breakfast: hard to make rooms sophisticated and comfortable and private, easy to make rooms cluttered and kitschy and noisy. Cave Hill Farm succeeds where many do not. Our stay was perfect. The rooms were spacious and full of atmosphere, without being fussy and crowded. Rooms were all with a private bath, and the bathroom had heaters, great showers, wonderful fittings. The bed was big and had a wonderful mattress, great pillows and covers, and felt modern, not soft and squeaky. The setting for the house is beautiful and rural, but still convenient to restaurants and highways. Our breakfast was prepared by a kind young couple who knew when to offer assistance and when to leave us alone. All in all, I would recommend this bed and breakfast highly, and would go back. most sincerely, Lee Lawrence
4.6 on December 27, 2013
My husband and I enjoyed a fantastic stay at Cave Hill Farm Bed and Breakfast around the Christmas holiday. It was very convenient to the activities available at both Massanutten Resort and in Harrisonburg, VA but was located in a tranquil setting. The innkeepers made us feel very welcome and were lovely to chat with each morning over breakfast. We would absolutely stay here again!
4.6 on September 02, 2013
My fiance and I stayed here in July. We just moved to Virginia and weren't aware of the "good spots" as far as B&Bs. This is definitely one of them. I can't remember the last time I slept that well - thanks to the solitude of being on the farm in the middle of what seems like nowhere. Katie and Ryan were more than accommodating and extremely friendly. I was planning my next trip before we even left. This would be great for couples but also if you want to have a "you time" weekend. I want to come back time and time again. It was absolutely beautiful. And the food was ah-mazing. Thanks Katie and Ryan!
5 on August 25, 2013
My fiance and I stayed found this adorable B&B nestled in the foothills of the Shenandoah mountains for a small romantic getaway. We had originally picked it due to the location. It is very convenient to Skyline drive, where we were hiking, along with Grand Caverns and the town of Harrisonburg (I am a JMU graduate who likes to visit). After arriving, we couldn't have been more impressed. The house is very private with a beautiful view of the mountains even though it is located just off Rt 33. Every room is filled with history and gorgeous antiques. Our every need was taken care of including a pleasant surprise of complementary wine available in the kitchen. The small amenities such as bath salts were a great touch and much appreciated after a strenuous hike. The hosts are an unusually accommodating and charming young couple. Breakfast was above and beyond any expectation! Ours included french toast, fresh fruit, and bacon. We will definitely be back for a longer stay in the future. This B&B is an amazing find!
3.2 on July 17, 2013
This is a nice place to stay. Such beautiful surroundings, ancient trees (one of my personal favorites), and history abounds. It's interesting to realize that people have been sleeping and living here for two hundred years. A lot has happened during that extended period, and the house has testimonies scattered throughout which make for very interesting reading. You really do get a sense of life in those early colonial days, as well as the march of time since then. Fascinating stuff. Being an amateur keyboard player, I even played the beautiful wooden pump organ they have in the "living room;" an experience not to be had in too many places. :-) Beautiful grounds, beautiful views, and beautiful period accommodations. Hats off to Ryan, Katie, and Mr. Hopkins. Glenn D. Reuther
1790 English-made mahogany canopy queen bed
Massive mahogany armoire and fireplace
Full bath with jacuzzi, pedestal sink and view of mountains
Silk damask bed linens, featherbed & down comforter
Cable TV, VCR, telephone
Nightly Rate: $159 - $159
Grandmother's Room - $159 Make A Reservation
Amish-made queen bed
Exquisite antique cherry furnishings
Silk and lace bed linens, down comforter
Cozy fireplace, cable TV, telephone
Full bath with pedestal sink and tub/shower
Nightly Rate: $109 - $109
The Gold Room - $159 Make A Reservation

Spectacular views of Blue Ridge Mountains
Queen size Amish-made bed
Gold silk damask duvet cover & down comforter
Fireplace, cable TV & VCR, telephone
Full bath with pedestal sink and tub/shower
Nightly Rate: $109 - $109
Uncle Charlie's Room - $159 Make A Reservation

Four windows with views of Blue Ridge Mountains
Queen Amish-made bed with massive headboard
Navy blue & cream color scheme, down comforter
Large full bath with tub/shower combination
Nightly Rate: $109 - $109
Aunt Emma's Room - $159 Make A Reservation
Queen size Amish-made bed
Antique mirrored oak armoire
Cozy corner fireplace
Full bath with pedestal sink and tub/shower
Nightly Rate: $109 - $109
Airport, Countryside, Mountains, Ranch, Wine country
Antique Shopping, Gourmet/Fine Dining, Historical interests, Movie Theater, National/State parks, Performing Theater, Religious Services, Ski area, Vineyard, Winery
Bed and Breakfast
BBQ grill, Wedding Facilities
Air conditioning, Ceiling fans, Coffee/Tea facilities, Fireplace, Satellite/Cable TV, TV, Telephone, Wi-Fi, Wired internet
Canoeing, Downhill Skiing, Fishing, Golfing, Hiking trails, Horseback riding, Kayaking
Omar and Hannah
English, Spanish


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Leadership team
Adrian Scholes
Vice President of MarketingAdrian is responsible for Newforma's corporate branding and integrated marketing efforts worldwide. After beginning his career at Rolls-Royce in the UK, Adrian realized his passion for high-tech marketing and has enjoyed positions with DataXu, PTC, CA Technologies, and Siemens. An early adopter of social media, automation, and data-driven marketing, Adrian's customer-centric approach ensures strong connections by delivering the relevant information prospective buyers need to make informed decisions.
Alan Facey
Chief Customer OfficerAlan is an expert in scaling fast-growth software companies of global scope. He has held senior positions at companies such as Black Duck Software, Lumigent Technologies (acquired by BeyondTrust), and Progress Software. At Newforma, Alan manages all customer-facing activities, including global sales, distribution, services, and support. Alan has lived in seven countries in the course of managing operations in Europe, the Middle East, Africa, the Asia Pacific region, and the United States.
Allen Patrick
Vice President of North American SalesAllen has a background in enterprise software that optimizes processes and maximizes effectiveness. His career includes senior management roles at QAD (an enterprise resource planning provider), where he was responsible for global strategic accounts, and RCM Technologies, where he led a business unit that provided solutions to improve operational performance and supply chain efficiency. His knowledge of lean principles is just one resource he calls upon to help companies operate more effectively.
Alexandre Tartas
Vice President of Europe, Middle East and AfricaAlexandre has acquired deep insights into the needs of international technology consumers through his work with GRAITEC, Dassault Systèmes – SolidWorks Corp., and PTC (Parametric Technology Corporation). Alexandre holds a master's degree in business and administration from INSEEC Business School.
Allen Preger Cofounder
Vice President of Global Accounts
Allen has led the design, validation and product management of Newforma's project information management solution since co-founding the company. Prior to Newforma, Allen has been a partner at the consulting firm Marinsoft, a product marketing manager at Autodesk, the Asia Pacific regional director for Softdesk, and an account executive at Archsoft Group (ASG). Allen holds a bachelor of science degree in economics and mathematics from Occidental College.
Andrea Kokolis
Vice President of Human Resources
In the course of her career, Andrea has been part of management teams involved in nine mergers and acquisitions! She combines operational experience with expertise in the human resources demands of fast-growing companies. Andrea's connection to the University of New Hampshire includes a bachelor of arts degree in political science, a master of business administration degree, and contributions as an adjunct faculty member.
Bob Batcheler Cofounder
Executive Vice President of Strategy
Bob's career as a professional engineer includes time at Black & Veatch and Bechtel Power Corporation. His AEC technology background encompasses a variety of roles at Autodesk and Softdesk. Bob earned bachelor's and master's degrees in civil engineering from Lehigh University, and qualified as a registered professional engineer in Maryland.
Chad Ames
Vice President of EngineeringChad has been successfully developing software for the AEC industry since the mid-1990s. Prior to Newforma, Chad was a pioneer in building information modeling at Autodesk, where he led the development of Autodesk Architectural Desktop. Chad holds a bachelor of science degree in computer science from the University of New Hampshire.
Dan Conery
Vice President of Construction & Owner Solutions
Dan has held a number of positions for Newforma since the earliest days of the company. Before Newforma, Dan was with Primavera Systems, where he held a variety of positions revolving around Expedition project controls solutions for contractors and owners. Dan holds a bachelor of science degree in mechanical engineering from the University of Rochester, a master of science degree in mechanical engineering from the University of New Hampshire, and a master of business administration degree from the Whittemore School of Business and Economics at UNH.
Dave Plunkett Cofounder
Executive Vice President of Development
Dave is a former director of desktop development for Autodesk and cofounder of the software development company CadZooks. He is the founder and chief technology officer for BugSplat Software. Dave holds bachelor's and master's degrees from Purdue University.
Ian Howell
Chief Executive Officer
Ian is an Australian architect by training, with professional experience as managing director of the Sydney office of The Buchan Group. His AEC software industry experience includes positions with Autodesk, Citadon, Alias Research and Rucaps Australia. Among his contributions to the AEC software industry, Ian was a founder of the International Alliance for Interoperability (now the buildingSMART Alliance).
Jim Forester, P.E. Cofounder
Vice President of Customer Satisfaction
Jim began his career at the building services engineering firm Syska & Hennessy before holding key technology and software development leadership roles with the Archsoft Group and Softdesk. He then founded Marinsoft, which delivers engineering software, design content and consulting services to the AECO industry. He is a founding member of AEC3, an international technology consulting company. He is involved in data modeling activities for industry standards initiatives, including buildingSMART International and ASHRAE Technical Committees. Jim holds a bachelor of science degree in mechanical engineering from the University of California, Los Angeles.
Joseph Santiago
Vice President of Finance
Joseph has been a financial executive at high-tech global companies such as Cedar Point Communications, Telcordia Technologies and Granite Systems. He began his career as an audit manager with Ernst & Young. Joseph holds a bachelor of science degree in accounting from Bentley University, and is a certified public accountant.
Ray DeZenzo
Chief Financial Officer
Ray guides Newforma's strategic financial planning and reporting. He has held chief financial officer and/or operational vice president roles at a wide range of companies, with an emphasis on the technology industry: Empirix (acquired by Thoma Bravo), Quallaby Corporation (acquired by Micromuse), and Cadia Networks (acquired by FORE Systems) among them. Ray holds a bachelor of science degree in accounting from Central Connecticut State University.
Shari Zedeck
Vice President of Product Management
Across technology companies serving diverse markets, Shari has ensured that product offerings address the rapidly-changing demands of technology and business users, whether individuals or organizations. Shari's background includes roles with Compuware/Dynatrace, NaviNet, Chordiant, Mindreef, Progress Software, NuMega Technologies, Hewlett-Packard, Apollo Computer and Raytheon. Shari holds a bachelor's in computer science from Binghamton University and a master's in business administration from Boston College.
Tim Bates
Director of Europe, Middle East and Africa Operations
Prior to joining Newforma, Tim was technical director of Excitech, Autodesk's largest systems centre and reseller partner in the UK. (Excitech's consultancy team supported several strategic BIM projects including BAA Heathrow Terminal 5 and HOK's Barts and The Royal London Hospital.) Before that, Tim founded and managed his own Autodesk dealership, T B Design Systems, based in Bristol, England. Tim holds a bachelor of science degree in physics from the University of Bristol.
Ved Narayan
Vice President of Asia Pacific Operations
Ved brings to Newforma more than 24 years of information technology experience. In his role as vice president of Asia Pacific operations, Ved is responsible for overall business growth and operations in the region. Prior to joining Newforma, he served as vice president of Asia Pacific operations for Dassault Systemes SolidWorks. Ved has held leadership roles in Asia and the United States for companies such as DEC, PTC, Software Emancipation Technology, and Synchronicity. He holds a masters of business administration degree from the University of Chicago Booth School of Business, and a bachelor of engineering in computer science from the Birla Institute of Technology, Mesra, India.
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The location, amenities, and service are great, especially for the price! I met a couple on my shuttle ride over to the hotel and they love the hotel so much, they only stay at the Sugar Palm when in Phuket. I made the mistake of trying out another hotel in Kata and was severly disappointed. The breakfast was delicious and though not located on the beach, it's close enough.
- Reservation Options:
- TripAdvisor is proud to partner with Expedia, Travelocity, Booking.com, Orbitz, Cheap Tickets, Priceline, Odigeo, Asiatravel.com Holdings, Hotels.com, Agoda and HotelTravel.com so you can book your Sugar Marina Resort - FASHION reservations with confidence. We help millions of travelers each month to find the perfect hotel for both vacation and business trips, always with the best discounts and special offers.
- Also Known As:
- Sugar Palm Hotel Kata Beach
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- Sugar Marina Resort - FASHION Phuket/Kata Beach


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- Horoscopes
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A man already charged with carrying out a home invasion burglary on Marla Drive in Ledyard in October 2011 was charged Thursday with a home invasion in Montville around the same time.
Vincent A. Sebastian III, 21, was charged with home invasion/robbery and threatening Thursday during a court appearance stemming from the Ledyard crime. Sebastian's alleged accomplices, Louis Seignious, 23, and Dawayne Sebastian, 20, have also been charged in both home invasions.
According to an arrest warrant affidavit, the three men knocked on the apartment door at 52 Sunny Hill Drive in Montville on Oct. 3, 2011 at about 9 a.m. Kyle Dubicki, 18, who had slept on the couch after a night of video games and drinking, answered the door. One of the robbers held a knife to Dubicki's throat and demanded that he rouse a man sleeping in the bedroom, according to the affidavit. While the one man held Dubicki in a chokehold with the knife close to his neck, the other two men robbed the occupant, 24-year-old Joseph McCormick, according to the affidavit. The three men left the apartment saying they would return with a gun if police were called.
McCormick said the men forced him to open a safe and hand over $900 in cash. McCormick's 25-year-old housemate, Christopher Floyd, told police that he was asleep in his own bedroom during the incident.
Seignious, who eventually spoke with police about multiple crimes that had occurred in the region during the month of October 2011, said he and the Sebastians had taken 7½ ounces of marijuana and no cash during the Sunny Hill Drive robbery.
McCormick did not report the crime until the next day, according to the affidavit. He said that as he and Dubicki were leaving to report the crime, they saw one of the men from the robbery, later identified as Seignious, sitting in a green Pontiac in the parking lot of the apartment complex. Seignious lived at nearby 65 Sunny Hill Drive.
Seignious and the Sebastians are all being held in prison in connection with the Oct. 14, 2011, home invasion at 13 Marla Drive in Ledyard. State police said they entered the residence armed with handguns and robbed the victims of cash and jewelry.
Seignious, whose bonds total $753,000, cash or surety in the Marla Drive case, was arraigned on the new charges of home invasion and second-degree threatening when he appeared last month in New London Superior Court.
Judge Susan B. Handy set an additional bond of $25,000 and continued the case to Jan. 7.
Dawayne Sebastian, who was charged in October in the Sunny Hill Drive case, is being held in lieu of bonds totaling $500,000. Vincent Sebastian, whose bond is $825,000 for the Marla Drive incident and another robbery case, was held on an additional $150,000 bond in the Sunny Hill Drive case.
Portion of Ocean Avenue in New London is closed after car snaps utility pole
Once again, there's a few sports parents who could use some decaf
New London middle school to get nearly $3 million to fund new programs
The Rev. Michel Belt set to retire from St. James Episcopal Church later this summer
Eastern Pequot chairman vows to fight new tribal recognition rule
Newly signed state budget changes funding for cities and towns
High Hopes offers equine experience to Camp Harkness campers
Police: Maine man shoots off fireworks mortar tube from top of his head, dies
New London man charged with failing to safeguard gun discharged at middle school
Former East Lyme couple accused in string of residential burglaries
Huge crowds clog region's beaches as holiday weekend draws to close


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H.R.1911 - Protecting Veterans' Homes Act112th Congress (2011-2012)
|Rep. Braley, Bruce L. [D-IA-1] (Introduced 05/13/2011)
|House - Veterans' Affairs
|Latest Action:
|07/21/2011 Forwarded by Subcommittee to Full Committee by Voice Vote .
This bill has the status Introduced
Here are the steps for Status of Legislation:
- Introduced
Subject — Policy Area:
- Armed Forces and National Security
- View subjects
Summary: H.R.1911 — 112th Congress (2011-2012)All Bill Information (Except Text)
There is one summary. Bill summaries are authored by CRS.
Shown Here:
Introduced in House (05/13/2011)
Protecting Veterans' Homes Act - Amends the Servicemembers Civil Relief Act to extend from 9 to 12 months after military service the period of protection against mortgage sale or foreclosure, as well as the stay of proceedings, in the case of an obligation on real property of a servicemember that originated before the period of military service.
Amends the Housing and Economic Recovery Act of 2008 to repeal the sunset date for such periods of relief.


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Hello all,
I am considering requesting a delete on an account that is one oldest accounts listed. It was a Chase credit card that went delinquent for several months. I ended up paying it off, it never went to collection, but I feel its worth getting deleted. Just wondering if the risk of lowering my AAoA is worth the delete.
Chase card opened 11/2005
best buy 3/2006 now in collections
student loans from 12/2005 Baddies now consolidated through the govt
wachovia 8/2005 charge off repo
good standing
Cap1 4/2007
target 4/2007
first premeire 5/2006 closed by me
My credit history is not so long to begin with but I thought deleting this might do more good than having it on there.
Any thoughts?
How bad were the lates on this account ? Were they worse than 30 or 60 days late ? Also, what is your AAoA now, is it around 5 years ?
"How bad were the lates on this account ? Were they worse than 30 or 60 days late ? Also, what is your AAoA now, is it around 5 years ?"
Hey thanks for the reply. To answer your questions, It got as as bad as 120 days in order as this: [in consecutive months: (30,60,60,90,120,90)]
My AAoA is about 5.5 years. I could not find the thread to get an exact or comprehensive AAoA so I just added all the years and months(converted those months to years) and then divided by my total accounts. I got 5.45-
02-21-2012 03:07 PM - edited 02-21-2012 03:08 PM
Do the same calculation without the account, and compare.
AAoA is only part of a 15% scoring category. Other criteria such as oldest TL and new credit are also included.
If this is also your oldest TL, that will also be affected. So lenght of credit impact could be near 15% of your total weighting.
Payment history is 35%, so weighted much higher. A 120 late is a major derog. The big factor, in my mind, would be how long ago this delinquency occured.
If relatively recent, I would suspect that its deletion would offset the loss in length of credit, but that is speculative. If old, then the lenght of credit impact might be more.
The bottom line is that account deletion is only at the perogative of the creditor. What will be your stated reason for convincing them to delete prior, accurate reporting?
Why not request deletion of only the delinquency, and not of the entire TL?
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The Portland folk rockers' latest album is due out June 8, but you can stream it right now over at NPR. (And there's still a free Destroyer of the Void MP3 available at Pitchfork.)
Update: There's another free MP3 available on the band's own site.
Hear Blitzen Trapper's New Album, Destroyer of the Void
The Portland folk rockers' new album is streaming at NPR.


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Sarcasm comes to mind, and I don't use it sparingly. Unfortunately that makes me look like an asshole, but that's my sense of humor, take it or leave it. I'm very driven with what I'm doing in my life at the moment and can't wait to move on to the next step, wherever the hell that takes me (hopefully to me owning a visual effects studio).
I have 5 tattoos, each with a specific reasoning behind them and a meaning they hold for me. If you wanna know what they are ask, don't really feel like digging up pictures to post them here.
That's all I can think of for now, so feel free to ask questions!


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That is the question Don Graves asks in his hard-hitting lead letter printed in this morning's Star. Enjoy. I look out my window and see sunshine and vibrant signs of approaching spring. There's even a Toronto sports franchise winning games.
But when I turn to the news media I read or hear about a glass half empty, half full, a glass smashed, a glass we can no longer afford because we are in so much provincial/federal debt and not to forget the growing number of Canadians who can no longer afford to buy a glass, full, half empty – or (Read more…)


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Choo, choo into Halloween in the Officially Licensed Thomas the Train Deluxe Toddler Costume. Your little engine will be the most stylish train on the tracks in this 3-D Thomas graphic tabard, conductor's hat and red scarf.
Chugga Chugga Chugga Chugga… (You know the rest) in this Thomas the Tank Engine infants costume your little one can round the bend in comfort and style. Get on the right track for Halloween with this character based foam apron train costume and engineer cap.
Have a cheeky Halloween and get on track for big fun when you wear this officially licensed Thomas the Tank Percy child costume. The green, red, white and black foam train character overlay comes complete with a green and black engineer cap.
Train as a warrior to help defeat the evil Queen Ravenna. Dress in this officially licensed Snow White & the Huntsman Snow White Armor tween costume and defeat all enemies on Halloween. The silver and gray shirt comes complete with EVA molded chest armor, shoulder pieces, gauntlets, skirt and…
Use this Pumpkin Reaper Kid Airblown Inflatable to decorate the yard on Halloween. This reaper in training features reaching arms along with a pumpkin head. Add his giant father and make it a family affair!
Take control of the tribe when you decide to wear the officially licensed How to Train Your Dragon 2 Hiccup Child Costume. This brown top features armor details and comes complete with pants and attached boot covers, arm gauntlets and wings. Fly high on Halloween!
Be Queen of the Snakes in the Medusa Women's Costume. This long dress featuring a reptilian print and a train reminiscent of a snake's slithery tail adds a sultry flair but the elaborate headpiece decorated by a bronze snakes will cause serious envy.
Create or complete your Hunger Games costume with this officially licensed Hunger Games District 12 Training Shirt costume. The black, red and gray garment features a half front zipper opening and unisex straight fit.
Walk down the aisle or into the party in this Marry Me Dead Zombie Bride adult womens costume. The tattered, stitched and shredded wedding dress of this zombie costume comes complete with a train and veil with bow. Face it - you're only marrying him for his brains!
Give your little one some wizard training when you dress them up in this officially licensed Mike the Knight Evie Deluxe Toddler Costume. The purple dress comes complete with a jacket and attached satchel along with tights, boot covers and a matching hat.
Everyone's going to be asking who the newest star is when you wear the Hollywood Diva Child Costume. Your little star will be camera ready in this black gown with sheer train, furry white stole, sparkling tiara and large sunglasses.
Your little princess will be the perfect princess-in-training in the Officially Licensed Sofia the First Prestige Toddler Costume. Features a lilac, satiny colored dress with a full skirt and puffy sleeves; a princess tiara tops off the look.
Look into the depth of the magical realm this Halloween with Harry Potter Glasses. An officially licensed replica, this finely crafted accessory provides you with Harry's signature touch. Add the robe and the wand (both sold separately) to fully transform into J.K. Rowling's famous…
…gentleman you see will gladly give their heart to you when you decide to wear the Heart Breaker Adult Women's Costumes. This black, red and gold dress is fit for royalty and features an attached petticoat and heart details on the skirt and collar, complete with a detachable black and red train.
Who says vampires can't be stylish? In this runway-worthy Vampira child costume you'll be the hit of Transylvania. The red, black and gray dress comes complete with bell sleeves, belt and train. Wear it, but stick to the shadows - your fair skin does not do well in the sun.


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To increase the efficiency of a pipelined microprocessor, branch prediction is often implemented. Many branch instructions are used to implement program loops with a fixed number of iterations. To accurately predict the branching behavior of branch instructions used to implement program loops a counter based branch prediction system is suggested. The counter based branch prediction system is based on acquiring a final loop count at run time. The final loop count specifies the number of iterations the loop will perform such that the final loop count is used to predict the branching behavior of the branch instruction used to implement the program loops. Three methods for acquiring a final loop count are proposed. Using the suggested counter-based branch prediction method improves the branch prediction rate of the loop related branch instructions and the overall average prediction rate. As a result, this enables the design of higher performing computer pipelines.
1. A method improving the prediction of branch instructions with program loops in a pipelined computer microprocessor, said microprocessor containing a branch prediction mechanism that predicts which instructions should be fetched after a branch instruction, and said mechanism utilizing a branch target buffer, wherein sad method comprising the steps of:
determining a final loop count for a loop based branch instruction, said final loop count comprising a number of loop iterations;
storing said final loop count in a branch target buffer;
clearing a loop count in said branch target buffer;
modifying said loop count when said loop based branch instruction is encountered;
comparing said loop count to said final loop count;
predicting said loop based branch instruction taken when said loop count does not equal said final loop count; and
predicting said loop based branch instruction not taken when said loop count equals said final loop count.
2. The method as claimed in claim 1 wherein said step of determining a final loop count comprises dynamic run-time determination of said final loop count.
3. The method as claimed in claim 1 wherein said step of determining a final loop count comprises run-time determination of a memory location containing a final loop count.
4. The method as claimed in claim 1 wherein said step of determining a final loop count comprises using a hint bit that identifies a branch instruction as implementing a program loop, wherein said hint bit informs the branch target buffer that said branch instruction is best predicted by a counter based prediction scheme.
5. The method as claimed in claim 1 wherein said step of determining a final loop count comprises identifying a branch instruction as implementing a program loop with a hint instruction.
6. A branch target buffer for predicting branch instructions, said branch target buffer comprising:
a tag address field, said tag address field identifying location of a branch instruction in memory;
a target address field, said target address field specifying address that program will branch to if said branch instruction is predicted taken;
a final loop count field, said final loop count field containing a number of loop iterations; and
a counter field, said counter field storing a current number of loop iterations.
7. The branch target buffer as claimed in claim 6 further comprising:
a branch history field, said branch history field storing a history of branch results; and
a branch type field, said branch type field specifying if said branch instruction implements a program loop.
This invention relates to the field of branch prediction mechanisms for computer processors. Specifically, the invention relates to a branch prediction mechanism that maintains a counter of loop iterations.
Early microprocessors generally processed instructions one at a time. Each instruction was processed using four sequential stages: instruction fetch, instruction decode, execute, and result writeback. Within such microprocessors, different dedicated logic blocks performed each different processing stage. Each logic block waited until all the previous logic blocks complete operations before beginning its operation.
To improve efficiency, microprocessor designers overlapped the operations of the fetch, decode, execute, and writeback processing stages such that the microprocessor operated on several instructions simultaneously. In operation, the fetch, decode, execute, and writeback processing stages concurrently process different instructions. At each clock tick, the result of each processing stage is passed to the following processing stage. Microprocessors that use the technique of overlapping the fetch, decode, execute, and writeback stages are known as "pipelined" microprocessors. Some microprocessors further divide each processing stage into substages for additional performance improvement. Such processors are referred to as "deeply pipelined" microprocessors.
In order for a pipelined microprocessor to operate efficiently, an instruction fetch unit at the head of the processing pipeline must continually provide the pipeline with a stream of microprocessor instructions. However, conditional branch instructions within an instruction stream prevent the instruction fetch unit from fetching subsequent instructions until the branch condition is fully resolved. In pipelined microprocessor, the branch condition will not be fully resolved until the branch instruction reaches an instruction execution stage near the end of the microprocessor pipeline. Accordingly, the instruction fetch unit of the microprocessor will stall because the unresolved branch condition prevents the instruction fetch unit from knowing which microprocessor instructions to fetch next.
To alleviate this problem, most pipelined microprocessors implement a branch prediction mechanism that predicts the existence and the outcome of branch instructions within an instruction stream. The instruction fetch unit uses the branch predictions to determine which instructions should be fetched after a branch instruction. For example, Yeh & Patt introduced a highly accurate two-level adaptive branch prediction mechanism. (See Tse Yu Yeh and Yale N. Patt, Two-Level Adaptive Branch Prediction, The 24th ACM/IEEE International Symposium and Workshop on Microarchitecture, November 1991, pp. 51-61)
To predict the outcome of branch instructions, most branch prediction mechanisms collect branch "histories" that store the outcome of recent occurrences of each branch. For example, a branch prediction mechanism may store the outcome (taken or not-taken) of the last k occurrences of a particular branch. The branch history is stored in a branch target buffer along with a tag address for identifying the location of the branch instruction and a target address for identifying the branch target destination.
When a branch prediction mechanism predicts the outcome of a branch instruction and the microprocessor executes subsequent instructions along the predicted path, the microprocessor is said to have "speculatively executed" along the predicted instruction path. During speculative execution the microprocessor is performing useful processing only if the branch instruction was predicted correctly. However, if the branch prediction mechanism mispredicted the branch instruction, then the microprocessor is speculatively executing instructions down the wrong path and therefore accomplishes nothing useful. When the microprocessor eventually detects that the branch instruction was mispredicted, the microprocessor must flush all the speculatively executed instructions and restart execution at the correct address.
Since the microprocessor accomplishes nothing when a branch instruction is mispredicted, it is very desirable to accurately predict branch instructions. This is especially true for deeply pipelined microprocessors wherein a long instruction pipeline will be flushed each time a branch misprediction is made. This presents a large misprediction penalty.
Studies of branch behavior have indicated that program loops are not predicted well by history pattern based predictors. It would therefore be desirable to have an improved branch prediction mechanism that would predict the behavior of branch instructions in program loops.
It is therefore an object of the present invention to provide a branch prediction mechanism targeted at branch instructions that implement program loops.
This and other objectives are achieved by the counter-based branch prediction system of the present invention. The counter based branch prediction system acquires a final loop count for each program loop to be predicted. The final loop count specifies the number of iterations the loop will perform such that the final loop count is used to predict the branching behavior of the branch instruction used to implement the program loops. Three different methods for acquiring a final loop count are proposed: dynamic run-time loop determination, run-time detection of a final loop count location, and architectural support via hint instructions.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.
The objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiment of the invention with references to the following drawings.
FIG. 1 illustrates a flow diagram of a common program loop that counts upwards.
FIG. 2 illustrates a flow diagram of a common program loop that counts downwards.
FIG. 3a illustrates an embodiment of the branch target buffer of a branch prediction mechanism with a counter based loop predictor. FIG. 3b illustrates another embodiment of the branch target buffer of a branch prediction mechanism with a counter based loop predictor.
FIG. 4a lists a count up program loop.
FIG. 4b lists a count down program loop.
FIG. 5a lists a count up program loop that counts by adding a constant.
FIG. 5b lists a count down program loop that counts by subtracting a constant.
FIG. 6 illustrates the method of predicting branch instructions.
Methods and apparatus for implementing counter based branch prediction for loops are disclosed. In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required to practice the present invention. In other instances, well known circuits and devices are shown in block diagram form to avoid obscuring the present invention unnecessarily.
FIG. 1 illustrates a flow diagram of a typical program loop. The first step, step 110, is to clear a loop counter. The loop counter will be used to count the iterations of the loop. The next step is to perform the loop commands at step 120. The loop commands consist of a set instructions that the programmer wants executed multiple times. Then, at step 130, the loop counter is incremented. At step 140, the loop counter is compared with some value indicates the number loop iterations to be performed. If the loop counter equals the number of loop iterations, then the loop is done. Otherwise, the program control branches back up to step 120 where the loop commands are executed again.
Program loops come in many variations. FIG. 2 illustrates a common variation of a program loop. In the program loop of FIG. 2, a loop counter value is loaded with the number of loop iterations at step 210. Next, the set of loop commands are performed at step 220. After the loop commands have been performed, the loop counter is decremented at step 230. The loop counter is tested at step 240 and if the loop counter is not zero, then program control loops back up to step 220 to perform the loop commands again. When the loop counter reaches zero, the program continues along a straight path.
Program loops such as those illustrated in FIG. 1 and FIG. 2 occur many times within most computer programs. To improve branch prediction in a microprocessor, the present invention suggests a dedicated loop based branch prediction scheme. Specifically, a loop based branch prediction mechanism would maintain a final loop count value that consist of the number of iterations a loop performs and a loop counter that would count the iterations of a loop as it occurred. The potential of the counter based prediction scheme is based on the assumption that for a given program loop, the loop count is invariable in a large percentage of the instances of the program loop.
Most existing branch prediction mechanisms collect a limited history of previous branch outcomes and make branch predictions based upon the collected branch history. The branch history pattern-based Tse-Yu branch predictor effectively handles only loops with very short loop counts, depending on the number of history bits used. Loop counts of up to the number of history bits plus one are perfectly predicted if the loop count does not change. For example, a 4 bit history register can predict loops with a loop count of up to 5. Longer loops incur a single misprediction on the loop exit. If this single misprediction is amortized across a large number of loop iterations per instance, the overall prediction rate is still very good. However, if the loop count is larger than the length of the history pattern but not very large, the prediction rate is quite low. In 4 bit history predictor, a loop executing 6 times has a prediction rate of 83.3%, even if the loop count is fixed. The prediction rate for loops longer than the history pattern the same as the static prediction rate, and is easily calculated by:
Prediction rate=(Loop-- count-1)/Loop-- count
A counter based predictor aims to augment the pattern-history predictor for loop related branches. A counter based predictor may static prediction for the first instance of a loop, incurring one misprediction when the loop is exited. Alternatively, some implementations of a counter based branch prediction system may determine the number of loop iterations even before a program loop is first executed.
After obtaining the number of iterations a loop will make (final loop count), the counter based predictor has perfect prediction when the loop count of the current instance is equal to the loop count of the previous instance of the same loop. If the loop count of the current instance is larger than the previous loop count, two mispredictions will occur: once when the counter reaches zero and the loop exit is incorrectly predicted and another one when the real loop exit is finally reached. Branch instructions within loops with a loop count shorter than the previous count will incur a single misprediction upon the loop exit. Thus, branch instructions within loops with a loop count shorter than the previous count have the same prediction rate as branch instructions that are predicted using static prediction.
The following table lists the branch prediction rates for a branch history pattern-based branch prediction system, a counter-based branch prediction system, and a static branch prediction system.
______________________________________ Pattern mispredic-Prediciton rate for different tions eliminatedSPEC Branch Prediction Mechanisms by a counter-Program counter-based pattern-based Static based scheme______________________________________compress 83.39% 83.94% 83.87% -3.42%eqntott 99.64% 97.13% 94.03% 87.46%espresso 98.84% 96.60% 86.67% 65.88%gcc 93.07% 92.11% 85.95% 12.17%li 68.67% 68.74% 48.07% -0.22%sc 99.56% 92.29% 84.34% 94.29%ear 100.00% 98.48% 98.48% 100.00%alvinn 100.00% 97.57% 97.57% 100.00%mean 89.75% 87.87% 78.73% 15.50%______________________________________
As illustrated by the preceding table, loops in integer programs are not well predicted by existing pattern-based branch prediction mechanisms or static predication. Storing final loop count is a more efficient encoding of the history of loop based branches than a stream of taken/not taken bits used in the branch history pattern-based (Tse-Yu) algorithm. However, the counter based loop branch prediction system is best used only for loop related branches such that a counter based loop prediction mechanism should be used to augment a pattern based prediction mechanism instead of replacing it.
FIG. 3a illustrates the entries for one embodiment of a branch target buffer that performs both branch history pattern-based (Tse-Yu) branch prediction and counter based branch prediction. The first field is a tag address. The tag address is used to identify the location of an associate branch instruction in memory. The second field is a branch type field. If the branch instruction is determined to be from a program loop, then the branch type is set such that the branch history is ignored and the final count and counter are used to make branch predictions. The third field is a branch target address. The branch target address is the address that the program will branch to if the branch instruction is predicted taken. The fourth field is a branch history field The branch history field stores the taken/not-taken history for the last n instances of that branch instruction. The fifth field is a final count field. The final count is the number of iterations the loop last performed. The sixth field is the counter field. The counter field is used to store a temporary loop counter while a loop is being executed.
FIG. 3b illustrates a second embodiment of a branch target buffer that performs both branch history pattern-based (Tse-Yu) branch prediction and counter based branch prediction. In the embodiment of FIG. 3b, the final field either stores a branch history or a final count and counter. If the branch type indicates a program loop, then the final field contains a final count and counter. Otherwise, the final field contains a history of the previous occurrences of the branch instruction.
When the branch type field is not set to loop, then the branch target buffers of FIGS. 3a and 3b operate like existing pattern-based branch prediction mechanisms. A description of a pattern based branch prediction mechanisms can be found in the patent entitled "Method and Apparatus for predicting Branches in a CISC processor", Ser. No. 08/177,155, filed Jan. 4, 1994. issued Nov. 12, 1996, U.S. Pat. No. 5,574,871.
When the branch type field indicates a program loop, the branch target buffer of FIGS. 3a and 3b predicts the behavior of the branch instruction using the final count and counter fields. When the number of iterations that the loop performs is first determined, that "loop count" is stored in the final count field, the branch type is set to indicate a loop, and the counter field is cleared. (The methods for determining the loop count will be explain in the next section). The next time the branch instruction that is part of a loop is encountered, the counter will be incremented. If the counter in the counter field is less than or equal to the value in the final count field, then the branch prediction mechanism branches to the address specified in the target address field. Otherwise, if the counter exceeds the value in the final count field, then the processor proceeds to the instruction after the branch instruction and clears the counter in the counter field. Both the counter incrementing and the comparison are done in the early stages of a microprocessor pipeline such that the outcome of the loop branch instruction can be predicted without creating gaps in the instruction stream within the microprocessor pipeline.
If a misprediction is detected when using counter-based branch prediction, then the loop count may be adjusted. Alternatively, the branch type for that branch target buffer entry will be changed such that pattern-based branch prediction will be used.
As previously mentioned, the number of iterations that a program loop performs must be determined for a loop counter based prediction mechanism to operate. The present invention proposes three different methods for determining the final loop count for a loop: previous loop occurrences, run-time loop detection, and loop count location with architectural support. Using any of these methods, the final loop count can be found and placed into the final count field of FIG. 3. As explained above, the final loop count is used to predict the outcome branch instructions that implement loops by counting loop iterations and comparing the intermediate loop iteration count (counter) with the known final loop count.
1. Dynamic Determination of Final Loop Count from Previous Loop Instances
The first method of determining the final loop count is to identify existence of a program loop and then determines the number of iterations that occur for that program loop. Determining a final loop count from a previous instance of a loop and using the final loop count to predict future occurrences of the loop count is based on the assumption that for a given program loop, the loop count is remains constant for a large percentage of the program loop instances.
Determining a final loop count from previous loop instances operates as follows. When a conditional branch instruction with a taken backward branch is first encountered, the loop identifying circuitry is activated. The loop identifying circuitry determines if the final count in the branch target buffer is 0. If it is zero then the loop counter is cleared and 1 is added to it and the branch is taken back. Each time the conditional instruction branches backwards, the processor should add 1 to the loop counter. When the loop has terminated (all loop iterations have executed), the counter that was counting loop iterations is stored into the branch target buffer as the final loop count for the next loop instance and the branch type is set to indicate a loop.
To augment the dynamic method of determining a final loop count, Architectural support can be added the hardware. For example, a hint could be placed in the instruction stream, indicating a specific branch to be loop related. The hint would enable the implementation to apply the counter based predictor circuitry to that branch instruction.
There are a number of benefits in having architectural support. For example, a the branch type would only indicate a loop for branch instructions that are better predicted by counter based loop predictor. In an alternate embodiment where the loop branches are stored separately, then the entries in the loop branch target buffer prediction mechanism are not consumed by branches that do not benefit from it, leaving more space for branches that do. Furthermore, architectural support allows accumulating loop count history from the first instance of that loop.
2. Run-Time Detection of a Final Loop Count Location
Dynamic run time detection of a memory location containing a final loop count is feasible. The location of the final loop count can be deduced from run-time hardware analysis of the instruction stream. Specifically, identifying certain instruction sequences can reveal the location of a value that stores the number of iterations of the loop. By capturing the value from that location, the final loop count field of the branch target buffer can be filled.
Frequent sequences of 2-3 instructions that modify the loop counter, check the loop exit condition and branch accordingly can be identified at run time, by hardware. FIGS. 4a and 4b, illustrate examples of simple program loops written in a hypothetical assembly language. The loop program of FIG. 4a represents a count up program loop. Specifically, a register that will serve as a loop counter is cleared at the beginning of the loop. Near the end of the loop, the register is incremented and compared with an immediate value. If the register does not equal the immediate value, then the program loops back for another iteration. In this simple loop program, the immediate value that is compared to at the end of the loop can be used as the final loop count value.
FIG. 4b illustrates a similar case except that FIG. 4b represents a count down program loop. In the loop of FIG. 4b, a register is loaded with a loop iteration value. Then, near the end of the loop, the register is decremented and tested to see if it is zero. If the register is not zero, then the program loops back for another iteration. In this loop program, the value that is loaded into the loop counter register at the beginning of the loop can be used as the final loop count value.
Many variations on the loops of FIGS. 4a and 4b exist. FIGS. 5a and 5b illustrate two possible variations. The program loops of FIGS. 5a and 5b add and subtract, respectively, a constant K from the register used as the loop counter. To fill in the final loop count field with such program loops, the final count should be set as follows ##EQU1## Where LOOP-- COUNT is the immediate value used to compare the register to when performing the loop end check and K is the constant that is added to or subtracted from the loop counter register.
Examples of such instruction sequences taken from compiled Intel Architecture programs are listed below:
inc % edi; 1. cmp % ebp, % edi; j1 .L5
addl $4, % edi; j1 .l2
addl $4, % edx; cmpl $40, % edx; jb .L4
One or more of these typical instruction sequences can be looked for in program code. These would be either the most common existing loop code sequences or loop code sequences that would be recommended by the processor manufacturer for efficient loop code generation. Compiler designers could develop compilers that would use the recommend loop instruction sequences.
3. Loop Count Location with Architectural Support
Determining the current loop count by specifically identifying a location of a loop count value using architectural support was also examined. If the location of the loop count is known prior to loop execution, then the loop count is available up-front and the exit condition of the loop can be calculated in advance such that no branch mispredictions will occur for the sequence of loop instructions.
Since this approach would benefit only loops that are counter based, our study of the SPEC benchmark programs measured the percentage of counter-based loops among all loops using compiler generated instrumentation. The results are provided below:
______________________________________Percentage of counter based loopsSPECProgram all loops all branches______________________________________compress 42.64% 6.68%eqntott 97.09% 35.36%espresso 71.15% 14.27%gcc 49.71% 7.08%li 0.00% 0.00%sc 17.61% 1.31%ear 99.70% 17.95%alvinn 100.00% 0.11%mean 46.37% 10.78%______________________________________
As can be seen from the preceding table, about 50% of the loops in C language integer codes are counter based. Thus, a counter based branch prediction system would provide great improvement to an existing branch prediction system.
Two different method of architectural support have been proposed: a compiler generated hint bit and a specific hint instruction. Each scheme was examined and the results are summarized below.
Providing a compiler generated hint bit involves informing the hardware that a specific branch ends a loop and is thus predicted best by a counter based scheme. The results of testing a hint bit based scheme did not significantly improve the prediction beyond the numbers above. In our measurements we used the compiler to identify loops, so we already had that information, and could apply it only to loops.
A hint instruction providing the loop count location has more potential than a single hint bit. A hint instruction, generated by the compiler and inserted before each counter based loop can provide the location of the loop counter and enable near perfect prediction for the loop. As can be seen from the table above, about 50% of the loops in C language integer codes are counter based. However, given the small percentage of branches that are loop related (8.5% for single exit loops, 17.64% for all loops), even perfect prediction on counter based loops will yield an improvement of less then 0.5% in the overall prediction rate.
Different methods can be used to implement a hint instruction for capturing the loop count via information provided explicitly in the instruction stream. Each method will be examined individually.
A specific hint instruction that provides either the location or the value of the loop count can be added to the processor instruction set. This type of instruction is very explicit and easy to implement. However, it adds an instruction to the instruction stream that does nothing more than provide the branch prediction mechanism with a hint.
A specific loop branch instruction with loop count information can be added to the processor instruction set. This instruction would perform the combined task of hinting the branch prediction mechanism and branching back.
Semantic meaning can be added to another (for example--compare) instruction that is involved in a program loop. For example, a bit can be added to an instruction.
This technique of adding a hint instruction to the instruction set has the potential of providing the most accurate indication of the loop count. Since both the location and thus the value of the loop count for the current instance are precisely known, there is no reliance on a previously used count. It can be inserted in places where the potential penalty of a mispredicted branch outweighs the cost of handling an additional instruction.
The proposed architectural support should not be confused with specific loop instructions that exist in various architectures and combine management of the counter and a conditional branch in a single instruction. Instructions such as the Branch on Lcc and Add (BLA) in the instruction set of the Intel i860� Architecture, the Branch Conditional to Count Register (BCCTRx) in the instruction set of the Motorola PowerPC� Architecture, and the Loop instruction in the set of the Intel 80x86 Architecture are typical examples. While these instructions help in reducing the path-length, they do not obviate the need for predicting the loop exit condition. As the exit condition is resolved at the execution stage of the pipe, a pipeline bubble is in most cases unavoidable without branch prediction. They can however aid the counter based predictor in locating the loop count location. As such they fall under either the second or the third scheme since they can be looked at as either an easily detected instruction sequence or as containing a branch hint.
FIG. 6 illustrates the method of predicting branch instructions. The first step, step 610, is to determine a final loop count. The final loop count is the number of iterations a loop performed during an earlier loop execution. The next step is to store the final loop count in the branch target buffer at step 620. The final loop count will be used during the next branch execution. Then, at step 630, the loop count in the branch target buffer is cleared. At step 640, the loop count is modified when the branch instruction is encountered. The loop count is used during branch execution to count the number of iterations that have occurred. The loop count is compared to the final loop count at step 650. This comparison allows the branch prediction mechanism to determine whether the loop has performed the predicted number of iterations. Then at step 660, the branch prediction mechanism predicts the branch instruction taken when the loop count is not equal to the final loop count. If the loop count and final loop count are not equal, then the loop has not completed the predicted number of loop iterations and the loop continues to execute. At step 670, the branch prediction mechanism predicts the branch instruction taken when the loop count is equal to the final loop count. If the loop count and final loop count are equal, then the loop has completed the predicted number of loop iterations and the loop is exited.
Although the present invention has been described in terms of specific exemplary embodiments, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.
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