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Help - potential DOCS situation
Started by opethmum , Jan 10 2013 05:10 PM
16 replies to this topic
Posted 10 January 2013 - 05:10 PM
Ok this happened this afternoon.
I was minding my own business and got on my bus route and some lady was jabbering quite loudly on her phone about trying to get her kids back from foster care and she was saying that her children were not happy at all. I was quite sad for her having to plead on the phone to whoever was on the phone to have her case looked at by the courts, she then proceeded to hang up. She then proceeded to make another phone call.
It went a little like this, she told the other person on the line that she wanted to kill with knives and do harm upon them on her next visit to the foster carers and those involved in taking her children away, she wanted their eyes to be bathed in the blood of the innocent, she wanted those responsible to make their souls clean and wanted to kill the police workers and damn their souls in everlasting hellfire. She wanted to cause everlasting harm to the judges and the courts and kill them in their sleep.
She was really freaking me out and I could not believe what I was hearing.
Should I take my concerns to the police or should I just stay out of it?
Posted 10 January 2013 - 05:14 PM
Perhaps the mental health issues that made her say those things are well known to the team involved in her case and could even form part of the reasons she does not currently have care of her children?
Posted 10 January 2013 - 05:18 PM
It went a little like this, she told the other person on the line that she wanted to kill with knives and do harm upon them on her next visit to the foster carers and those involved in taking her children away, she wanted their eyes to be bathed in the blood of the innocent, she wanted those responsible to make their souls clean and wanted to kill the police workers and damn their souls in everlasting hellfire. She wanted to cause everlasting harm to the judges and the courts and kill them in their sleep.
She was really freaking me out and I could not believe what I was hearing.
that is probably why she hasnt got her children, do you even know her name??
This is a surefire way to go about threatening people with this sort of stuff that isnt going to help her case. I feel sorry for any of the workers who have to deal with this person and her children.
Posted 10 January 2013 - 05:19 PM
I don't know tbh - I mean, how easily identifiable would she have been? It sounds like a very very sad situation, but I don't know if you'd be able to give them much to go on really...
Posted 10 January 2013 - 05:19 PM
I would. The worst that could happen is they'll laugh at you. The best is worth it.
If it made you uncomfortable listening, then there was a reason for it.
Posted 10 January 2013 - 05:21 PM
I don't have her name unfortunately and I am worried about the foster carers, who knows if she will carry through her threat.
Posted 10 January 2013 - 05:22 PM
She sounds very unwell and I'm sure the people involved are aware of it. If it would put your mind at ease, make a report to crime stoppers.
Posted 10 January 2013 - 05:28 PM
As a foster parent Ive heard this many times, Bio parents vent in many ways. Could be a mental health issues or not Im sure the Dept have already heard her wishers and are dealing with it.
Posted 10 January 2013 - 05:28 PM
As a previous DoCS worker I would say that these are pretty stock standard things that are said. It is a sad situation, however, many parents can not take responsibility for their behaviour and therefore blame all the other people involved for their situation and then threaten to do harm. I think there is little that you can do in this case seeing as though you don't have her name and I am sure that DoCS are probably aware of her situation.
Posted 10 January 2013 - 05:28 PM
You know what, I would call DOCS in your area and tell them. Give them as MUCH detail as possible even a description of the lady. (If you know which bus st she got on, or off)
They MAY be able to work out who she is, if its a repeat of past behavior based on description, locations etc. and you know what, even if they can't you can rest easier at night knowing you did something.
I've made a report about someone I didn't know based on what a family member said ( as the family member wasn't going to do anything) I told them what I knew (which wasnt much) and they were very greatful. I thought they would think I was stupid reporting hearsay but I was very worried about what was said. I didn't even know the mother last name or address.
I say do it, it REALLY can't hurt, but it certainly CAN help.
Posted 10 January 2013 - 05:43 PM
QUOTE (opethmum @ 10/01/2013, 06:21 PM) <{POST_SNAPBACK}>
I don't have her name unfortunately and I am worried about the foster carers, who knows if she will carry through her threat.
OP, it sounds like she's very mentally unwell and if I were you I'd call the DOC's number in your State and give a description of her when reporting it. The woman may not have been a foster carer through DOC's (perhaps a private agency) but at least you've tried. I'd call the police too.
As a foster carer, I have been on the receiving end of bio-parents with serious mental health issues and threats of abduction or violence. I had to have sensor lights installed at my old house as a precaution and my kid's case manager would call me when the dad was having an "episode". I totally agree that the child protection system is broken in many ways and is a damaging process for all side: the carers, the bio-parents and the poor kids. At the same time, I also know that carers can feel like "sitting ducks" when they have kids in their care and the bio-parent is making threats.... the police and DOC's won't do much until after the fact....
Posted 10 January 2013 - 05:47 PM
Meh - stay out of it. Go and google 'DoCS NSW name and shame', you'll get a taste there for the type of nutbag you'd be dealing with (kids obviously taken off her for good reason!).
Anyway, to do harm to the foster carers she'd have to find out who they are first.
Edited by Tigerdog, 10 January 2013 - 05:47 PM.
Posted 10 January 2013 - 06:28 PM
QUOTE (Tigerdog @ 10/01/2013, 06:47 PM) <{POST_SNAPBACK}>
Anyway, to do harm to the foster carers she'd have to find out who they are first.
In my case, DOC's told me that the bio-parents had the right to know where their children were placed so our location was not confidential. I was furious when I found out that my address (not my name) had been given to the dad but when I escalated it to my case worker's manager, I was told in no uncertain terms that I had no right to confidentiality and that almost all bio-parents are advised of the address that their kids are placed at. I was fuming. And also scared when the dad started making terrible threats against the kids and me.
Posted 10 January 2013 - 07:19 PM
Thanks ladies, I will call DOCS and report her. Thanks for giving me additional things I was not aware of! Take care for now
Posted 10 January 2013 - 07:27 PM
Maybe she knew you were evesdropping and said all that stuff to scare the crap out of you. I think mind your own business would be a good thing. I'm sure if the kids are in foster care they are already been looked after and DOCS are involved.
Posted 10 January 2013 - 08:22 PM
Trust me I was not eavesdropping, I had my 6 mo son with me and I needed to keep him occupied,
Posted 10 January 2013 - 08:23 PM
She may be someone who likes to say things like that when she's angry. It doesn't necessarily mean anything.
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text:
A method of testing the interconnections between integrated circuits in a circuit uses latches, respectively connected to the terminals of the integrated circuit, which are connectable in series as a shift register so that a test pattern of bits can be entered into the latches. The pattern of bits is transmitted through the interconnections to other latches and then shifted out of the circuit along the shift register. Discrepancies between the input and output patterns indicate malfunctioning interconnections. The method is extended to apply to a microprocessor in the circuit, the microprocessor having a program that enables it to use its RAM to act as the latches of the other integrated circuits. The program may be stored in on-chip memory in the microprocessor and where that memory is RAM. EPROM or EEPROM it may be erased therefrom after successful testing of the circuit.
1. A method of using a microprocessor chip having a plurality of ordinary microprocessor terminals but lacking predetermined dedicated boundary scan test bus terminals and boundary scan test circuits normally required to support a boundary scan test, to support and participate in a boundary scan test of component interconnections when installed in a product circuit with connections to other components having dedicated boundary scan test bus terminals and boundary scan test circuits, comprising the steps of:
restricting a first subset of the ordinary microprocessor terminals to use as terminals connectable to a JTAG test bus for the boundary scan test;
designating a second subset of the ordinary microprocessor terminals as testable as if provided with dedicated boundary scan test circuits; and
loading and running a simulation program in the microprocessor instructing the microprocessor to (i) operate the first subset of terminals to simulate the predetermined dedicated boundary scan test bus terminals, and (ii) operate the second subset of terminals to simulate their being additionally provided with the predetermined dedicated boundary scan test circuits.
2. The method of claim 1 wherein the microprocessor chip has a non-volatile memory and the simulation program is stored in the non-volatile memory when the microprocessor chip is manufactured.
3. The method of claim 2 wherein the non-volatile memory is a ROM memory on board the microprocessor.
4. The method of claim 2 wherein the non-volatile memory is an EPROM memory on board the microprocessor.
5. The method of claim 4 wherein the simulation program is adapted to respond to erase itself in response to a predetermined instruction received via the terminals connectable to a JTAG test bus, whereby after the product circuit passes a boundary scan test of its component connections the space the simulation program occupies in the microprocessor's EPROM can be used to store other data.
6. The method of claim 2 wherein the microprocessor is manufactured with a non-volatile memory for storing microcode instructions and the simulation program is stored in the same memory during manufacture.
7. The method of claim 1 wherein the microprocessor has a RAM memory and address, data, and control buses coupled to terminals of the product circuit by which the simulation program is loaded in the microprocessor's RAM memory at the time of the boundary scan test.
8. The method of claim 1 wherein the boundary scan test is a JTAG test.
9. In a microprocessor chip having a plurality of ordinary microprocessor terminals but lacking predetermined dedicated boundary scan test circuits and test bus terminals normally required to support a boundary scan test, the improvement comprising:
a first subset of the ordinary microprocessor terminals programmable as terminals connectable to a JTAG test bus for the boundary scan test;
a second subset of the ordinary microprocessor terminals programmable as testable as if provided with dedicated boundary scan test circuits;
a non-volatile memory; and
a simulation program stored in the non-volatile memory enabling the microprocessor to (i) operate the first subset of terminals to simulate the predetermined dedicated boundary scan test bus terminals, and (ii) operate the second subset of terminals to simulate their being additionally provided with the predetermined dedicated boundary scan test circuits;
wherein the microprocessor chip can support and participate in a boundary scan test of component interconnections when installed in a product circuit with connections to other components having dedicated boundary scan test circuits and terminals.
10. In a microprocessor chip having a plurality of ordinary microprocessor terminals but lacking predetermined dedicated boundary scan test circuits and test bus terminals normally required to support a boundary scan test, the improvement comprising:
a first subset of the ordinary microprocessor terminals programmable as terminals connectable to a JTAG test bus for the boundary scan test;
a second subset of the ordinary microprocessor terminals programmable as testable as if provided with dedicated boundary scan test circuits;
a non-volatile memory; and
a simulation program stored in the non-volatile memory enabling the microprocessor to (i) operate the first subset of terminals to simulate the predetermined dedicated boundary scan test bus terminals, and (ii) operate the second subset of terminals to simulate their being additionally provided with the predetermined dedicated boundary scan test circuits.
This application is a Continuation, of application Ser. No. 08/527.991, filed Sep. 13, 1995 , now abandoned, which is a Continuation of application Ser. No. 08/106,158, filed Aug. 13, 1993, now abandoned.
1. Field of the Invention
The present invention relates to the testing of circuit boards, in particular to the boundary scan testing of a circuit board including a microprocessor.
2. Description of the Prior Art
Manufacturers of electronic circuits commonly produce their circuits in the form of printed circuit boards having mounted on them a plurality of integrated circuits as well as other components. The components are interconnected by conductors or metallic tracks printed on the board with electrical contact between the leads or pins of the components and the tracks made using solder joints. The interconnections may be imperfect and may display short- or open-circuit connections that are erroneous, the errors possibly arising from faults of either the solder joints or the tracks.
Once a circuit board is completed it would, of course, be possible to operate the circuit as a method of testing it but with the complexity of many such boards it would be both difficult and time consuming to test it thoroughly to check that all interconnections were correctly made. Boundary scan testing is a method of testing the interconnections between integrated circuits on a circuit board which enables the test to be carried out more quickly. A system of boundary scan testing is defined by IEEE standard 11491.1-1990 "Standard Test Access Port and Boundary Scan Architecture" also known as JTAG. To support JTAG boundary scan testing an integrated circuit will have specially provided for each of a number of its pins a boundary scan cell, for example, an input latch, an output latch or both of those or a combined input-output latch, for transmitting and receiving signals via the particular pin. In addition a boundary scan cell may include a control latch. The latches may each comprise a shift register latch and a shadow latch. The shift register latches can be joined with others, from the same and other boundary scan cells, to form a long shift register joining up all the input and/or output terminals of the integrated circuits. The cells can therefore be loaded serially with data supplied to an dedicated test data input pin on each integrated circuit. Data already in the shift register latches is shifted out via a dedicated test data output pin of the integrated circuit when the shift register is operated. From time to time data can be transferred between the shift register latches and their corresponding shadow latches.
In a circuit having more than one JTAG integrated circuit the shift registers of each circuit can be joined serially to form one long shift register known as the scan path.
To perform a test of the interconnections between integrated circuits on a circuit board test data appropriately interspersed with control data is fed along the scan path and is loaded into the input and output latches of the integrated circuits. Each boundary scan cell will either be an input cell or an output cell depending on the value loaded in its control latch if it has one; if a cell has no control latch then it will have been built as an input cell or an output cell. Next, each output cell transmits the test data held in its output latch over the interconnections via its pin and each input latch receives test data from the interconnections via its pin and stores it. The resulting pattern of data in the latches can then be shifted out along the scan path for analysis to find out whether the interconnections are functioning correctly. Note that the data held in the shadow latches actually determine whether the boundary scan cells are inputs or outputs and the values to be output on the cells' pins are directly responsive to data supplied to the pins.
Usually the test patterns are generated by a computer which also analyses the resulting patterns. Normally the computer is given a description of the integrated circuits on the scan path, for example which cells have input latches and which have output latches, and a description of the interconnections on the board between the pins. From those descriptions the computer generates a number of test patterns, and after running the test the resulting patterns are analysed to see whether the circuit board has the described interconnections and, if not, to indicate in what way it might be faulty.
Boundary scan testing does provide a quick and reliable method of testing a circuit board; however it does require that the integrated circuits are constructed to include the necessary hardware; this includes not only the latches described above but the means to join them in a shift register and the means responsive to the necessary control signals.
Boundary scan testing is at its simplest and most effective when all the integrated circuits on a circuit board support it. If only some of the integrated circuits support it, then there are a number of things that can be done. The manufacturer of the integrated circuits can redesign the integrated circuits to include the hardware to support boundary scan testing; this takes some time, increases the silicon areas of the devices and hence their cost, and means that the new integrated circuits will not be compatible with the old ones and hence cannot directly replace the old ones since dedicated control pins and test data pins must be provided on the new ones. The manufacturer of the circuit board can add buffers that do support boundary scan testing between the integrated circuits that do not and the rest of the circuit but that increases cost and may affect the performance and timing of the circuit, and will introduce further interconnections that cannot be tested. As a last resort the corrections to the non-supporting integrated circuits can be ignored by the test, so reducing the coverage of the testing; the effects of that can to some extent be reduced by more lengthy and elaborate boundary scan test procedures, such as those described by Robinson and Deshages in a paper entitled "Interconnect Testing of Boards with Partial Boundary Scan" published by Gen Rad, Inc., of 300 Baker Avenue, Concord, Mass. USA.
The disadvantages of these approaches are increased when the non-supporting integrated circuit is a microprocessor, for example a microcontroller, since such devices are usually the centre of functionality of any circuit in which they are included and consequently are connected to many of the other components.
Addition of the necessary JTAG hardware to a microcontroller can involve a considerable amount of work due to the complexity, type and number of input and output pins normally associated with them. Consequently, there is a reluctance to modify existing microcontroller designs to incorporate this feature.
It is an object of the present invention to provide a method of boundary scan testing a circuit, which includes a microprocessor that overcomes at least the difficulties described above.
According to the present invention there is provided a method of testing interconnections of a circuit having a plurality of integrated circuits
at least some of the integrated circuits including
storage elements respectively associated with some of the terminals of the integrated circuit and means for joining the storage elements into at least one shift register chain,
the method including
entering an initial test pattern of bits serially into the storage elements, along the shift register chains,
transferring certain of the bits of the initial test pattern from the storage elements into which they were entered, via the terminals and interconnections, to others of the storage elements,
retrieving the resulting pattern of bits serially from the storage elements along the shift register chains, and
comparing the initial test pattern and resulting pattern to derive information about the interconnections,
characterised in that
at least one of the plurality of integrated circuits is a microprocessor having internal memory and stored therein a test program which causes the microprocessor to perform a number of operations including
entering part of the initial test pattern of bits into the internal memory,
reading certain of the bits stored in the internal memory and producing corresponding output signals on terminals signals of the microprocessor connected to particular interconnections,
reading bits via the particular interconnections at terminals of the microprocessor and storing the received bits in the internal memory, and
producing as an output in serial form the received bits stored in the internal memory, so as to enable interconnections connected to terminals of the microprocessor to be tested.
The JTAG standard will now be described with reference to FIGS. 1, 2 and 3, followed by a description of a method of boundary scan testing a circuit board including a microprocessor, by way of example only. Reference will be made to the accompanying drawings, of which:
FIG. 1 is a circuit diagram of a circuit having three integrated circuits, all of which support boundary scan testing according to the JTAG standard;
FIG. 2 is a diagram of an integrated circuit that supports boundary scan testing according to the JTAG standard;
FIG. 3 is a state diagram for the test access port controller of FIG. 2;
FIG. 4 is a block diagram of one example of a microcontroller; and
FIG. 5 is a diagram of a circuit including the microcontroller of FIG. 4 that can be arranged to provide for boundary scan testing.
FIG. 1 is a circuit diagram of a circuit having three integrated circuits 21,22, 23 all of which support JTAG boundary scan testing. Each integrated circuit has twenty pins 1-20 of which 1 and 20 are connected respectively to test mode select (TMS) and test clock (TCK) signal lines of JTAG bus, pins 10 and 11 are connected to the power supply, and application pins 3-9 and 12-18 are connected via various of the interconnections 25,26,27,28 to pins of others of the integrated circuits 21,22,23 or to terminals 24. For each of the pins 3-9 and 12-18 there is provided in the integrated circuit a boundary scan cell 29 having a combined input/output latch and a control latch. The boundary scan cells of all the integrated circuits are on a scan path 30 which starts at the terminal TD1, enters integrated circuit 21 at pin 2, passing through the boundary scan cells of that integrated circuit, and then leaves via pin 19 continuing through the integrated circuits 21,22 in a similar way in turn and finishing at terminal TD0. The scan path 30 can operate as a shift register driven by clock signals TCK.
To test, for example, the interconnects 26 between the pins 12-18 of the integrated circuit 21 and the pins 3-9 of the integrated circuit 22, test data and interspersed control data is passed along the scan path 30, under the control of the signals on the TMS and TCK lines, into the input and output latches of the boundary scan cells 29. The input and output latches of the cells for pins 12-18 of the integrated circuit 21 are set up to be outputs and those for pins 3-9 of the integrated circuit 22 set up to be inputs. The important values of the test data are those provided for the pins 12 to 18 of the integrated circuit 21 since it is these that are transferred across to the input latches of the integrated circuit 22, once all the data has been shifted in along the scan path. The data latched across are subsequently shifted out and analysed to check whether the interconnections 26 are all functioning correctly.
As a particular example, a test pattern might be LOW in all of the output latches for pins 12 to 18 except for a HIGH in the latch for pin 15. In the diagram it can be seen that if there were no fault a HIGH would be latched across to the input latch of pin 8 of the integrated circuit 22, the others of pins 3-9 receiving LOWs. If, for example, the interconnect from pin 15 to pin 8 was shorted to that from pin 14 to pin 4, then a HIGH would be received at the latch for pin 4, assuming that the latch for pin 15 was able to drive those interconnections HIGH while the latch for pin 14 was trying to drive them LOW. This extra HIGH in the resulting pattern shifted out along the scan path 30 would be detected by the computer performing the test which would produce an output indicating the nature of the fault detected.
It is clear that fully to test the interconnections for open and short circuits many operations of shifting in data, latching across and shifting out will be required. Test patterns are normally generated by the computer running the test under the control of software, such as the ASSET system of Texas Instruments Incorporated. More complicated interconnects than the one pin to one pin interconnects 26, for example the interconnects 27, can also be tested. Interconnects to terminals 24 could be tested by connecting them to other integrated circuits supporting JTAG off the circuit board under test, but included in the scan path.
FIG. 2 is a diagram of an integrated circuit 39 that supports JTAG similar to those of FIG. 1. In addition to boundary scan cells 29 on the scan path 30, the application pins 31 and pins 2,19 to connect to the scan path 30, pins 1,20 to receive the control signals, TMS, TCK and pins 10,11 to connect to the power supply, FIG. 2 shows application circuitry 32, a test access port (TAP) controller 33, a bypass register 34, an instruction register 35, multiplexers 36,37 and a tristate latch 38. In the JTAG standard the bypass register and the set of boundary scan cells are known as data registers. In a full implementation of the standard there are other data registers provided but their operation is not relevant to the present invention and they will not be described.
The application circuitry provides the normal functions of the integrated circuit when it is not in test mode. During those times it communicates freely with other components via the application pins 31 unhindered by the latches of the boundary scan cells. Note that in practice it may be required that the inputs and outputs of the application circuitry are latched and in that case the latches of the boundary scan cells could be used for that purpose.
The bypass register 34 and the instruction register are alternative scan paths to the boundary scan cells through the integrated circuit 39. Multiplexers 36 and 37 recombine those paths into a single one and latch 38 simply increases the length of each path by one step. The test access port controller is responsive to the TCK and TMS signals of the test bus and also to the value stored in the instruction register; it controls the operation of the rest of the test logic.
The bypass register 34 and the instruction register 35 like the boundary scan cells not only have latches which form a shift register when data is scanned through them but also latches shadowing those latches to and from which values can be transferred from time to time.
FIG. 3 shows a state diagram for the test access port controller 33 of FIG. 2, which conforms to the JTAG standard. The test access port controller examines the TMS signal at each positive going edge of TCK and changes to a new state depending on the value of TMS. This is shown in the diagram by arrows labelled 1 and 0 indicating the values of the TMS signal. The two parts of the diagram enclosed in dotted rectangles are for manipulating respectively a data register and the instruction register and are marked DR-SCAN 40 and IR-SCAN 39. The particular data register manipulated depends on the value held in the instruction register. It should be noted, then, that the selection of the scan path change through the integrated circuit 39 involves both the control signals, TMS and TCK, and the value in the instruction register 35. Moving around the state diagram allows boundary scan tests such as those described above to be carried out.
A full description of the functions of these states can be found in the JTAG standard. Some functions are not implemented in the device described below and only a brief description of the relevant states will be given.
The TEST-LOGIC-RESET state is the state on power up. In this state the test logic is inactive and the integrated circuit 39 performs its normal function using the application circuitry 32.
The RUN-TEST/IDLE state is used in the full standard for some special test functions; those are not implemented in the device described below but the state is provided to allow the states to change in the standard way in response to the TMS and TCK signals.
The SELECT-DR-SCAN and SELECT-IR SCAN states perform no function other than allowing other states to be reached from them.
In the CAPTURE-IR state the instruction register is loaded with a 10000001 pattern and is sent along the scan path. If the TEST-LOGIC-RESET state has been passed through since the last scan operation, the latch 38 which drives the TDO (test data output) pin 19 is enabled to output a LOW or zero, otherwise it is enabled to output the same as that which it was outputting the last time it was enabled.
In the SHIFT-IR state data is advanced through the instruction register, one step per cycle of TCK, from the TDI (test data input) pin 2 to the TDO pin 19. The 10000001 pattern in the register in the CAPTURE-IR state is shifted out and can be used to confirm that the instruction register is connected in the scan path.
EXIT1-IR and EXIT2-IR perform no operation; they allow the shifting operation to be ended.
PAUSE-IR performs no operation; the test access port controller 33 can be held in this state to allow the shifting operation to be suspended for a period of time.
In the state UPDATE-IR the value in the shift register latches of the instruction register are transferred to the shadow latches.
The functions of the states for manipulating the data registers depend on the particular register to be manipulated. They are as follows:
CAPTURE-DR; the data register selected by the value in the instruction register is placed or the scan path, and the latch 38 that drives the TD0 pin 19 is enabled in a similar manner as it is by the CAPTURE-IR instruction, except that when the bypass register is selected the latch 38 is enabled to output a low or zero level. In the case of the boundary scan cells it is during this state that the values present on the input pins and received by the shadow input latches from other boundary scan cells via the interconnects 26,27 are latched, along with data held in the other shadow latches, into the shift register latches.
In the SHIFT-DR state data held in the shift register latches of the selected register is shifted through the integrated circuit 39 from the TD1 pin 2 to the TD0 pin 19 one bit per cycle of TCK. In the case of the data register the data shifted will include control data as well as test data. In the case of the bypass register bits of the data are shifted through the integrated circuit rapidly since the register is only one bit long. This register is used, for example, when it is desired to use the boundary scan cells of other integrated circuits but not those of the particular integrated circuit.
The EXIT-DR, EXIT2-DR and PAUSE-DR states have similar functions to the corresponding IR states.
In the UPDATE-DR state the latches shadowing the shift register latches are updated from those latches. In the case of the boundary scan cells the control data latches and the output latches are given their new values.
Thus to perform the test of interconnects such as the interconnect 26,27 described above it is necessary to pass through the IR-SCAN state 39 once to shift into the instruction register an instruction which puts the boundary scan cells 29 on the scan path, and to pass through the DR-SCAN state 40 twice, once to shift into the boundary scan cells the test data and the control data and to transfer those values into the shadow latches and once more to latch across test data from other boundary scan cells to the input shadow latches, then into the shift register latches and to shift the resulting pattern out of the boundary scan shift register.
The present invention relates to enabling a boundary scan test to be performed so as to include a microprocessor, for example a microcontroller, on the scan path when the microprocessor or microcontroller does not have special circuitry to support boundary scan testing. The approach of the present invention to this problem is to program the microprocessor so that it simulates the behaviour of a JTAG integrated circuit such as those of FIGS. 1 and 2 in response to test bus and test data signals making use of the resources of the microprocessor as they are without providing any additional circuitry.
In the present invention the simulation is carried out under the control of software and the application of the invention to microcontrollers is particularly simple because many microcontrollers have, on chip, an amount of ROM or EPROM or EEPROM in which the software can be stored. Also many microcontrollers have, on chip, an amount of RAM in which the data manipulated by the software can be stored. The resulting device is therefore self-contained.
If the memory in which the test software is stored is of a kind as to permit it, for example if it is RAM or EPROM or EEPROM, the test software could be erased after a JTAG test has been successfully completed so as to release the memory space occupied by the test software for other uses.
By writing software which causes a microprocessor to simulate the hardware and protocol of the JTAG standard, a device, conforming to the standard, can be incorporated into a boundary scan test without any modifications to the device itself. In this way, no costly reengineering of an existing microprocessor is required and microprocessor-based systems can easily be made compatible with existing JTAG test and support hardware.
To simulate the behaviour of a JTAG circuit the software will have to manipulate the input and output to and from the microprocessor chip via its pins. Microcontrollers usually provide flexible methods of controlling the input and output including having pins which are individually programmable which simplifies the task of writing the software.
One example of a microcontroller, according to the present invention will now be described. FIG. 4 is a block diagram of a TMS370 CX5X microcontroller manufactured by Texas Instruments. A full description of this device can be found in the data sheet published by Texas Instruments. The program used to enable the micro-controller to support boundary scan testing is appended to this specification. The program is written in TMS 370 assembly language. The program is stored in the program memory which may be either ROM or EPROM. To simulate the JTAG boundary scan test mode the program expects the microcontroller to be operated in its single chip microcomputer mode which is achieved by applying a LOW signal level input to its MC pin. In this mode the microcontroller defaults to its unexpanded mode with its ports A,B,C,D configured as general purpose input/output ports rather than address, data and control bus connections. The program leaves the microcontroller in this mode.
The program expects the TCK, TMS, TD1 signals of the JTAG test bus to be respectively applied to the INT3, SPICLK and SPISOMI pins of the microcontroller and produces the TD0 output signal on the SPISIMO pin; of these pins, INT3, is configured to function as a maskable interrupt input and the other pins which are those of the serial peripheral interface are configured as general purpose input/output pins of the remaining pins of the microcontroller INT1 and INT2, those of the serial communications interface and those of the timers are configured as general purpose input/output pins and the analogue port is configured as a general purpose digital input port.
The program simulates the functions of the usual JTAG circuitry and in particular it simulates the functions of the test access port controller 33 and its progress through the JTAG state diagram (FIG. 3). To do this the program maintains two registers in the RAM memory of the microcontroller, which indicate the next state, one for HIGH values of TMS and one for LOW. Since the JTAG test access port controller and hence the program start off in the TEST-LOGIC-RESET state the program initialises those two registers to indicate TEST-LOGIC-RESET and RUN-TEST/IDLE respectively as the next states. The program then sets up INT3 to generate interrupts at the positive going edges of TCK. On interrupt, an interrupt handling routine checks the value of the TMS signal to see if it is LOW or HIGH and then calls one of a number of routines which perform the functions of the next state, the particular routine chosen being that indicated by the appropriate next state register. In addition to the functions of their state those routines update the next state register appropriately, so that on subsequent interrupts the states are traversed in the manner shown in FIG. 3.
Some of the states require action on the negative going edges of TCK, such action being in particular the outputting of the TDO signal ready for it to be received by another integrated circuit on the next positive going edge. The state routines handle this by resetting INT3 to generate interrupts on negative going edges and waiting for an interrupt. When an interrupt occurs the interrupt handling routine outputs the next bit of the TD0 signal and restores INT3 to generating interrupts on positive going edges.
The program maintains a register in the RAM of the microcontroller for simulating the instruction register. This register is manipulated by the state routines for the states of the IR-SCAN box 39 of FIG. 3 in a similar manner to that applied to the instruction register 35 of the JTAG circuitry. The value or instruction code in this register is then available to the state routines for the states of the DR-SCAN box 40 of FIG. 3 so that they can modify their actions accordingly.
JTAG circuitry may in general support all or only some of the instructions specified in the standard. The program appended to this specification supports only the EXTEST and BYPASS instructions. If codes for other instructions are found in the instructions register then the BYPASS instruction is performed.
When the code for the EXTEST instruction is in the instruction register maintained by the program the DR-SCAN 40 state routine manipulates a data register.
The program occupies seventeen consecutive eight-bit registers of the RAM memory of the microcontroller. A table given in the comment lines at the beginning of the appended program shows how the data register is organised. This data register corresponds to the shift register latches of the boundary scan cells 29 of integrated circuits with special JTAG circuitry provided. The register that corresponds to the shadow latches consists of the latches of the ports of the microcontroller that already exist. Those latches exist in the portion of the memory map of the microcontroller known as the peripheral file. In order that transfers between the data register and the port latches, which transfers correspond to transfers between the shadow latches and their shift register latches respectively, can be made simply, the organisation of the data register reflects that of the port latches in the memory map. Such an organisation has no disadvantages for test pattern generation and analyses systems, such as the ASSET system mentioned above, since they require no particular ordering of input/output latches control data latches and the like, but they do require that the order of these latches and the boundary scan cell or pin to which they belong, are specified to them. Therefore, to test a TMS370 CX5X microcontroller having the appended program using a system such as ASSET, that information as contained in the table will have to be specified to the system.
The transfers made between the data register and the existing port latches are made by the DR-CAPTURE and DR-UPDATE state routines. Respectively, these routines transfer data from the existing port latches to the data register and in the reverse direction. The shifting of the data register is carried out by the SHIFT-DR routine in which the bit present at the TD1 pin 2 is shifted into bit 135 of the data register (see the table at the start of the appended program), data bits already in the register are moved down one bit and bit 0 is set up to be output at the TD0 pin 19 at the next negative going edge of the TCK signal by placing it in a register in the RAM called OUTREG in the program. The bit held in OUTREG is set up by the program on the TD0 pin on a negative going edge of TCK; in this way the function of the latch 38 of JTAG integrated circuits is simulated.
From the table it can be seen that pins of the microcontroller included on the scan path variously have combined input/output latches, separate input and/or output latches and possibly a control latch. For each of those latches there is a bit of the data register. However, there are some bits of the data register marked by a dash in the "definition" column of the table that are not intended to have corresponding shadow latches. These bits lengthen the shift register and so should be specified to the pattern generation and analysis system as being present but containing no information when read by the analysis system. These bits when the other bits of the data register are transferred into their shadow latches will also, of course, be written into the peripheral file into whatever latch, if any, happens to be at that location. In the present example this has no undesired effects. However in other examples perhaps running other microprocessors this may not be so. A remedy would be to mask out these bits with appropriate values as they are written to the peripheral file or its equivalents.
When the code for the BYPASS instruction is in the instruction register the DR-SCAN 40 state routines simulate the operation of a JTAG integrated circuit having its bypass register on the scan path. In fact all instruction codes other than that for EXTEST will be treated as a BYPASS instruction. The simulation is achieved in the following way:
In the CAPTURE-DR state routine , a Low or zero is placed in OUTREG ready to be set up on the TD0 pin on the next negative going edge of TCK. In the SHIFT-DR state routine the value present at the TDI pin is read and is placed in OUTREG ready to be set up on the TD0 pin. In the UPDATE-DE state routine no operation other than to update the next state registers is performed.
The DR-SCAN 40 state routine also makes allowance, for both the BYPASS and EXTEST instructions, for the pipelining of the TMS signal.
It will be appreciated that the method of simulating the behaviour of a JTAG integrated circuit employed by the program described above is not the only possibility. For example, instead of being interrupt driven the program could poll the TCK signal, the data register could be organised differently or a different selection of the pins to which the test bus (TCK,TMS,TDI,TD0) is connected could be made. As another example, a similar program might be written for a microprocessor whose equivalents of ports A,B,C,D of the TMS 370 CX5X can only be configured as ports for data, address and control busses. In such a program it would not be so straightforward to produce the desired outputs on those pins, since for example the instruction set of the microprocessor might not allow the pins for the address and data busses to be programmed separately. However, there will be an instruction which writes a data value to a certain address and using this instruction with the desired values could be used to program the ports together. Since these values would possibly only remain on the pins for a few cycles of the microprocessor's clock, allowances would have to be made so that the period during which the data was set up on the pins included the time at which it was latched by other JTAG integrated circuits. Programming the control port at the same time as the address and data busses might not be possible, and the interconnects connected to those pins would have to be tested at different times, with allowance made for that in the test pattern generation and analysis system.
It is not necessary that the software be stored in memory internal to the microprocessor. The JTAG simulation software can be stored in many places, depending on the configuration of the system. If external ROM or PROM or EPROM is used for example, the software could reside there and be a minimal overhead to the total system memory. Conveniently the software could be transferred as a block from the external ROM or PROM or EPROM to the internal RAM of the microprocessor and run from there. Alternatively, a removable test ROM or PROM or EPROM could be used, and replaced by application software after successful testing of the printed circuit board. Many microcontrollers are intended for embedded control in mass-produced end applications. Such devices frequently use on chip masked ROM or EPROM. In the case of EPROM, the device could be erased and reprogrammed by the application software following a successful test.
A particularly advantageous solution can be achieved with microcontrollers such as the TMS370 family, which have on chip EEPROM (non-volatile memory). The JTAG software can be embedded in the device EEPROM before shipment to the manufacturer of the end equipment, and the application software provided by him on ROM or PROM or EPROM (either on-or off-chip) can read a check byte in the EEPROM at power-up which forces execution of the JTAG software.
Following a successful test, the JTAG software can be erased by the microcontroller itself, perhaps after receiving a special command word in the simulated instruction register. In this way, the JTAG software leaves no trace of its existence following the test, and the resources it had used are available to the application software in normal use. The special command word could be one of the unused codes of the JTAG standard. The EEPROM of the TMS370 family has the ability to be written to our erased by the microcontroller itself, the 12.6 volts required being generated from the supply rails by an on-chip charge pump.
If the software or the data it manipulates is not stored within the microprocessor but rather off-chip in some other memory then certain of the input and output pins of the microprocessor will be required for transferring instruction words or data words between the microprocessor and that memory. The lines requires for the TMS370 CX5X microcontroller of FIG. 4, would include ports A to D. These lines would not, therefore, be available for direct JTAG testing. However some indication of their functioning would still be provided by a JTAG test since if the program or data was not correctly transferred the test pattern generation and analysis system would not receive a proper response from the microprocessor thus indicating a fault with those lines. Although the simulation described produces a microprocessor that conforms to the JTAG protocol for boundary scan testing systems, the present invention could be applied to other systems, protocols or standards of boundary scan testing.
FIG. 5 is a diagram of a circuit including a TMS 370C756 microcontroller which has stored in its EPROM memory the program appended to this patent specification. FIG. 5 demonstrates the use in boundary scan testing of the circuit and its subsequent use in the application the circuit was designed for.
The circuit has at its centre the TMS 370C756 microcontroller 41. The analogue port pins AN0 . . . AN7 of the microcontroller 41 are connected to a set of eight DIP switches not shown, providing, depending on their positions, either a HIGH or LOW level to the respective pins of the analogue port. Many of the other pins are connected to various of the pins of the A ports of the six octal buffers, 42 to 47 of the type SN74BCT8245. These buffers have special circuitry provided to support JTAG boundary scan testing.
The circuit has terminals 48 to 53 for a JTAG connector cable which connects the circuit to a test pattern generation and analysis system. In particular there are four terminals 50-53 for connection of the test bus signals TMS,TD0,TDI,TCK. The TMS terminal 50 is connected to the TMS input pin of each of the octal buffers 42-27 and to the SPICLK pin of the microcontroller 41 which serves as its TMS pin. The TCK terminal 53 is connected to the TCK input pin of each of the octal buffers 42-47 and to the INT3 pin of the microcontroller 41 which serves as its TCK pin. Also provided in the circuit is a scan path; this starts at the TD1 terminal 52 and passes into the microcontroller 41 at its SPISOMI pin, which serves as its TCK pin. The scan path then continues on through each of the octal buffers 42-47 in turn, passing into each at its TDI pin and passing out at its TD0 pin, to arrive finally at the TD0 terminal 52.
The octal buffers 42-47 and the microcontroller 41 have suitable connections to a power supply, not shown. The microcontroller is suitably connected to a crystal 54 for controlling the frequency of its internal clock. The reset pin of the microcontroller 41 is connected through an RC network to a HIGH signal level, so that the reset pin is held at its active LOW level for a few moments after the power supply is turned on, before rising to a HIGH level and allowing the microcontroller 41 to start operating. The octal buffers 42-47 have their DIR pins connected to a HIGH level, so that the buffers are configured with their A port pins as inputs and their B port pins as outputs. Various of the B port output pins of the octal buffers 42-47 are connected to driver circuits not shown which, depending on the levels of the signal outputs of the buffer, illuminate light emitting diodes, not shown.
The microcontroller 41 having the appended program stored in its EPROM makes the testing of all the interconnections of the circuit with a JTAG test pattern generator and analysis system a straightforward matter. Firstly, the test pattern generator and analysis system is given a description of the circuit in terms of the interconnections between the integrated circuits, those being those between the octal buffers 42-47 and the microcontroller 41, and in terms of the order of, and the latches contained on, the boundary scan cells of the integrated circuits. For the microcontroller the boundary scan cells are simulated by the appended program and the information required is given in the table at the start of the program. The circuit can then be connected to the test pattern generator and analysis system.
In trials of the microcontroller with the appended program it was found that the test bus clock signal TCK could be operated at a rate of up to about 4 kHz.
The full JTAG standard requires, for an integrated circuit to conform to that standard, that the integrated circuit can be clocked at any speed from OHz to several MHz. Although clearly the maximum clock rate of 4 kHz achieved by the microcontroller in the trial does not conform to the wide ranging speed requirement of the standard, the microcontroller does conform to the JTAG protocol and therefore enables the circuit interconnections to be tested. Since the test as described above does not require redesign of the microcontroller to enable the test to be executed, the microcontroller can retain compatibility with its earlier versions.
The test now proceeds, as described above in relation to FIG. 1, with the test pattern generator generating test patterns which are fed to the integrated circuits of the circuit along the scan path. Certain of the bits of the test pattern after being latched into the integrated circuits are transferred via the circuit interconnections to other latches of the integrated circuits. The resulting pattern of bits is output along the scan path to the analysis system for analysis.
The appended program as it stands does not terminate and expects the testing to continue indefinitely. However it could be modified so that if there were an application program also resident in the EPROM of the microcontroller this could be executed while the appended program was waiting in the TEST-LOGIC-RESET state.
The appended program can be used in the following way. The program is stored in the EPROM of the microcontroller by the manufacturer of the microcontroller before the device is shipped to the manufacturer of a circuit into which it is to be assembled, for example that of FIG. 5, who installs the microcontroller in the circuit and tests the circuit wiring using boundary scan testing as described above. Once the test has been successfully completed, the program is of no further use (except perhaps if the circuit is returned for servicing by its end user), and consequently the storage space in the EPROM is wasted. The manufacturer of the assembled circuit can, if he wishes, erase the program in the EPROM and use the space to store at least part of an application program required to operate the circuit. In that way, all of the EPROM storage space can be used for application programs after the test program has been erased. In the case of the circuit of FIG. 5 such an application program might illuminate the light emitting diodes in a sequence which depends on the setting of the DIP switches .
Such rewriting of the EPROM means that a JTAG testable microcontroller has been provided not only without special circuitry being added to the design of the microcontroller but also without permanently using any of the resources of the microcontroller except for the four pins used for connection to the test bus. The latter is not a serious disadvantage because very few circuits including a microcontroller require the use of all of their pins and the program can easily be rewritten so that connection of the test bus is made to otherwise unused pins. If necessary it might be possible after testing of the circuit to reconnect the pins connected to the test bus to other interconnections by moving links or with other means. ##SPC1##
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[+] Christine and the Queens – Virgin Mobile Mod Club – presale code
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We are seeking for a search engine optimization manager to work with our stellar marketing team and focus on building new paid search campaigns, broaden our vital keyword and other pay-per-click relationships. (Ad Text optimizatiom, keywords optimization and etc) Position description:
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ambient air quality Companies in Grenada
Laboratorio de Analisis Ambiental
based in Heredia, COSTA RICA
The laboratory is dedicated to research in air and water quality. But to finance the projects we sell services to the industry (analysis, consulting, etc.).The laboratory is accredited with ISO17025:2005, and we do a lot of analysis in ambient air, indoor air quality, industrial hygiene, emissions tests, water and wastewater analysis.The laboratory also manages the air ...
Ambiente Y Tecnologia
based in Nunoa, CHILE
Manufacturer of Ambilogger, an environmental datalogger for CEMS and air quality monitoring stations. Capable to be operated by internet, performs data aquisition and validation, graphics, automatic calibrations, analyzers operation and more. It's not required any kind of software loading. Technical support is performed through internet.See www.ambilogger.net
Thermo Scientific - Air Quality Instruments
based in Franklin, MASSACHUSETTS (USA)
The Thermo Scientific portfolio of air quality products has expanded from individual gaseous criteria pollutant analyzers to encompass a broad range of particulate monitors, toxic gas sensors, VOC analyzers and completely integrated ambient and stack monitoring systems.
Ecotech Pty Ltd
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Ecotech is an Australian owned company with more than 35 years experience in servicing, maintaining, designing, manufacturing, installing and commissioning ambient air and emission monitoring systems around the world. Ecotech is ISO17025 accredited for the operation and maintenance of ambient air and continuous emission monitoring systems and was first accredited in 1999. ...
Chemisch Thermische Prozesstechnik GmbH / CTP Air Pollution Control
based in Graz, AUSTRIA
CTP (Chemisch Thermische Prozesstechnik GmbH) is one of the world`s leading companies in air pollution control for industrial applications. CTP was founded in 1985 and since then, its engineers, chemists and researchers have been developing individual technologies to serve customers worldwide, covering all industrial sectors. At CTP, we adhere to high quality standards ...
Baseline a MOCON company
based in Lyons, COLORADO (USA)
Baseline® offers the ultimate environmental measurement solutions package. With a complete line of gas analysis equipment that is ideal for Toxic Workplace Gas and Indoor Air Quality Monitoring, Environmental Source Monitoring and Ambient Air Networks. With measurement solutions for BTEX, Total Hydrocarbons, Methane / NonMethane as well as many others. The GreenLight® ...
HI-Q Environmental Products Company
based in San Diego, CALIFORNIA (USA)
HI-Q Environmental Products Company (HI-Q) has been a leading manufacturer of Air Sampling & Radiation Monitoring Equipment, Systems & Accessories since 1973. HI-Q started primarily as a manufacturer of activated carbon cartridges and high/low volume air sampling pumps intended to be used as "Record Samplers" in the collection of radioiodine and radioactive dust ...
Teledyne Advanced Pollution Instrumentation, Inc. (TAPI)
based in San Diego, CALIFORNIA (USA)
Teledyne-API, Inc. designs and builds precision gas analyzers in San Diego, California for use worldwide in ambient, CEMS, and process applications. Teledyne Advanced Pollution Instrumentation, Inc. (TAPI) is a world leader in the design and manufacture of analytical instrumentation for precision gas analysis. Known for Environmental Instrumentation. TAPI offers a ...
Cerex Monitoring Solutions, LLC.
based in Atlanta, GEORGIA (US) (USA)
Cerex specializes in the manufacture of FTIR and UVDOAS multi gas analyzers for Continuous Emission Monitoring, Process Monitoring, Ambient Air Quality Monitoring, Indoor Air Quality Monitoring, Leak Detection and Hazmat First Response. Cerex uses solid spectroscopy techniques to simultaneously monitor multiple gases in real time. Our devices are highly sensitive, ...
Tekran Instruments Corporation
based in Knoxville, TENNESSEE (USA)
Tekran Instruments Corporation is the world's leading manufacturer of advanced systems for ambient and point-source mercury monitoring. With pioneering expertise in cold vapor atomic fluorescence detection, Tekran® has become the trusted source for accurate and reliable measurement of ultra-trace mercury levels. Tekran has provided more ambient and CEM systems than any ...


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City Walk, Canberra
|This article does not cite any references or sources. (December 2009)
City Walk is a paved outdoor pedestrian area in Civic, Canberra. It was formed by the closure to traffic of Alinga Street between East Row in the east (at the City Bus Interchange) and Binara Street (near Casino Canberra) in the south-west. Pedestrians can walk almost the whole way without having to cross any roads with cars on them, except for Akuna Street.
City Walk intersects with Garema Place and Petrie Plaza. Along the walk can be found the Canberra Merry-Go-Round, the Centrepoint arcade, Canberra Centre shopping centre and the Canberra Times fountain.
City Walk often has street performers, and events such as the National Multicultural Festival.
Route map: Bing
|KML file (edit • help)


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Select Local Merchants
Arkaios CrossfitRead MoreEquipment: Sorinex rig Students should bring: towel Average class length: 60 minutes Number of Staff: 5?10 people Class location: Mix of indoor and outdoor classes Established: 2013 Registration required: Yes Good for beginners: Yes Guests allowed: Yes Parking: Parking lot Pro Tip: Come a few minutes early to fill out a liability form. Q&A with Monique, Co-owner Exercise is challenging, and people frequently give up on their fitness routines. How do you keep clients motivated? [We have] different workouts every day. We do beach workouts [and] workouts dedicated to fallen military personnel. [We] also offer kids' classes. CrossFit is a great way to meet people who have similar goals as you. What is the biggest mistake you see people make when trying to get fit on their own? Not being dedicated and understanding it will be hard work. It's hard work to change your habits, but the payoffs are worth it. Also, people tend to not have proper form when working out on their own, which can lead to injuries. Safety is our utmost concern for our members. Besides working out, what else can clients do to spend their time at your facility? Hang out, socialize and mobilize. Is there anything else you want to add that we didn't cover? We offer an unsupervised kids room. We also offer personal training, and we will have a strength room with programming as we grow.94-137 Leoleo St.Waipahu, HI US
Yoga Loft HawaiiRead MoreFor Yoga Loft Hawaii's founder, Lisa Sochocki, yoga isn't just a way to stretch and strengthen the body. It's a tried-and-true method of ridding the mind of clutter such as worries, anger, and unsolved calculus problems. Without such distractions, students can listen to the wisdom their hearts contain. To build classes that pursue this goal, Lisa and her team of instructors draw upon 400 hours of teacher training and more than a decade of posing practice. Vibrant Vinyasa flow sessions explore sun salutations, arm balances, and backbends amid soothing turquoise walls and a soundtrack of vibrant music. Here, yogis of all levels learn to link poses with deep, relaxing breaths, forming a strong foundation for challenging classes such as power Vinyasa. Yin routines highlight yoga's power to calm through lengthy poses that flex the body's connective tissue and unblock its energy pathways. The loft also hosts classes that teach kids aged 4–6 how to melt stress and potty-mouthed snow angels during classes filled with playful poses and relaxation techniques.94-547 Ukeʻe StreetWaipahu, HI US
UFC GymRead MoreIt's no secret that the UFC boasts some of the best athletes in the world. So it was only natural for the brand to expand into UFC Gym, a network of training centers that includes more than 100 locations across the country. Of course, the class schedule is rooted in mixed martial arts and strength training. Functional fitness is also a huge aspect, with Daily Ultimate Training workouts (DUTs) that keep the body challenged with changing combinations of cardio, anaerobic, and agility exercises.? With that said, UFC Gyms are not just for those interested in MMA. Its encyclopedic selection of classes includes Barre Interval to U Jam Fitness, Zumba, and Yoga Cycle, with plenty of classes for kids, as well. Personal-training sessions take place with certified UFC Gym coaches, who can both design workouts and give advice about nutrition, supplements, and which library books are heavy enough to build muscle while you read.94 Lumiaina St.Waipahu, HI US
G's Bar GrillRead MoreFor familiar food you're sure to love, head to G's Bar Grill for American-style cuisine. Pair your entree with a glass of wine or draft beer — G's Bar Grill has a fully-stocked bar to complement your meal. Shake off your workday and treat yourself to G's Bar Grill's happy hour. The noise level can often drown out conversation, so make sure your party is prepared to speak up. At G's Bar Grill, you can work your arms a little. Pick up the food yourself and carry it out. Take advantage of the quick and easy parking near G's Bar Grill. G's Bar Grill offers outdoor bike racks for cyclists. Meals at G's Bar Grill are incredibly tasty and reasonably priced around $30.94-889 Waipahu StWaipahu, HI US
Race World HawaiiRead MoreOn Race World Hawaii's track, kids of all ages race each other in tiny, rainbow-hued box cars—all of which run without fuel. Instead, the simple cars are powered by gravity, which pushes them down the track during open-track racing, field trips, and special events. All the while, track marshals supervise, making sure that drivers have the correct safety gear—including helmets, sport shoes that cover the entire foot, long pants that touch shoes for those under 18, and a ship's anchor they can drop to slow down.Kupuna Loop & Kupuohi StWaipahu, HI US
Last Stop LoungeRead MoreServing a range of tasty food and drink, Last Stop Lounge in Waipahu will have you thinking about seconds (or thirds). The food at Last Stop Lounge is high-calorie, high-flavor, and highly-rated. Dine with fellow dancing machines — the restaurant is stocked with a lively, open floor. We don't expect you to keep driving around the block to find metered parking. We've got some space for you here. Last Stop Lounge offers various parking options, including bike parking.94-226 Leoku StWaipahu, HI US


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In my Drupal 5 administrative interface, when I am administering content (Administer -> Content Management -> Content), I can only view 50 nodes per page. I have 350 PAGES of nodes which takes a long time to go through when I have to edit or delete nodes.
I am looking to display more nodes per page.


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Friday, 25 October 2013 | 26 comments
First shiitake harvest
Early this year, we inoculated some logs with shiitake spawn. Around September, we got our first one or two 'shrooms. But just this week was the first time we had enough coming in to really harvest in earnest. » Click to read more
Monday, 30 September 2013 | 15 comments
Basil flower vinegar
Now that summer's over, I took a few hours to clean up some of the herb plants in our front garden before they get frosted. I collect bundles and hang them high in the kitchen where it's typically pretty dry and well-ventilated, and where they aren't exposed to too much sun. » Click to read more
Tuesday, 11 June 2013 | 34 comments
With a pile of greens: Tortilla española
Maybe you've heard of Ruth Stout, who is quickly rising to the top of my Ideal Dinner Party Guest List (posthumously, sadly). She smashed saloon windows with Carrie Nation during temperance, and then went on to become a garden guru in the '60s and '70s. I'm reading her book called "Gardening Without Work: For the Aging, the Busy, and the Indolent". (If nothing else: such an appealing title!) Stout champions a way of gardening that essentially has one tenet: mulch the heck out of everything with straw, organic matter, newspaper, and forget about the rest. No weeding, and the organic matter of the mulch is supposed to occupy pests just as much as much as your plants themselves. The end. How she manages to fill up a book with this information, I'm not sure, but she does, and she's lovable and eccentric and I enjoy every minute of it. It comes as no surprise, I suppose, that this woman was known to garden in the nude (as if I could like her more). » Click to read more
Monday, 15 April 2013 | 19 comments
Warm potato salad with spring greens
spring is like a perhaps hand
(which comes carefully
out of Nowhere) arranging
a window,into which people look (while
people stare
arranging and changing placing
carefully there a strange
thing and a known thing here)and
changing everything carefully
» Click to read more
Monday, 4 March 2013 | 76 comments
A yellow split pea soup + some questions for you
At night, we bundle up and go down to the cellar. We decided to get hardcore about seed-starting this year and bought grow-lights. In the past, I've started seeds on windowsills, which works, sure, but the seedlings end up a bit leggy, and real estate is limited. Now, improbably, our windowless, 52-degree cellar is the home of seed-starting operations, spread across a big table with lights that shine 16 hours a day. We put on music, drink steaming tea, and get lost in the rhythm of poking holes, dropping in seeds, covering them up, watering them. All at 9 or 10 PM. It's a little counterintuitive, and lends a certain drama to the work, like we're growing something illicit in our basement.
It's that silly time of year where we're all pretty done with winter, but there's still an interminable stretch until it's honest-to-goodness spring. Even winter itself seems wan and ready to be put to bed, allowing some warming sun to poke through. On one or two afternoons, we've been able to move the garden prep outside for a few hours. But the nights still get very, very cold. The dirt still has a hard, frozen crust on its surface. I am still eating pantry-staple legumes. It is definitely not yet spring. » Click to read more


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ICICI Gsip - wrong information
1 Review
pnr on Jun 18, 2012
hi Sir!!
when customer care people called us for taking your icici pru.plan they convenced us for new plan,they told me this plan is under mediclaim plan which we required, who covers 3 lacs mediclaim with 4 family members...they gave us wrong information regarding their existed plan, they did not contact us, they didn't recd our call also,they swith off their mobile, we dont know about banch, branch manager & what is our exact policy?please help us. because of me my other friends took this policy also.they asked me always. your tel.operator always called us when they want to conye us,please tell me what to do?
tel.operators name as follows:
1.asmita 01409711506,9594719273-telecaller
2.Rohit 08692822105-who recd our cheque
In the month of Feb 2012- my mother Smt Anjali N.Raut opened new policy details as follows.
App.NoA45575769 4r
policy no.16397566
we issued cheque of Rs.6200/-
application no.45575769
instrument no.261782
Plan name:GSIP
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"A Conversation With Misty" (Misty Copeland Public Talk)
Mayoral Candidate Night
NW Ohio Conservative Coalition
Monday, August 26, 2013 from 6:00 PM to 8:00 PM (EDT)
NW Ohio Conservative Coalition
Jim Blue
(Toledo Free Press)
Mayoral Candidate Night
Meet and talk to each Candidate
Find out their plans for Toledo's future
Ask them hard questions
Monday Aug 26th
6pm to 8pm
( Presentation starts at 6:30 )
Toledo-Lucas County Public Library
McMaster Family Center (2nd floor)
325 North Michigan St.
(Library Parking garage off of Adams - Park FREE if you leave after 8pm)
Toledo, OH
* The BOE still needs to certify these candidates.
NW Ohio Conservative Coalition wishes to express our sincere gratitude to the Toledo/Lucas County Library, WNWO TV-24, WSPD 1370, and the Toledo Free Press for their assistance in making this event happen.
Join millions of people on Eventbrite.
In order to purchase these tickets in installments, you'll need an Eventbrite account. Log in or sign up for a free account to continue.


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Housewares Products Embraced As Overstock.com Valentine Gift Options
Friday October 25th, 2013 - 4:40PM
These are shortcuts to your favorite social networking and bookmark sites. Add this story to your Facebook page, del.icio.us, DiggIt, and many others!
Overstock.com says home furnishings and housewares make pretty good Valentine's Day presents. According to the e-tailer, the days of a box of chocolates and a dozen roses fulfilling romantic expectations are over, as lovers want to get something useful this Valentine's holiday.
Useful can be romantic these days, the online retailer said, and, as proof, Overstock has assembled a list of 15 Valentine's gifts that are don't bloom and are not meant to be eaten, including:
Tags: overstock • valentine's • gifts • pillow • glasses • Housewares • Cookware & Bakeware • Vacuum Cleaners/Electric Cleaning • Health & Personal Care • Home DĂ©cor • Home Environment • Small Electrics • Organization & Cleaning • Tabletop • Gadgets & Kitchen Tools • Retail •
Bradshaw, Sensio Enter Licensing Agreement For Bialetti Brand »
Sizing Up The Gourmet Housewares Market: Part 4
Klein Leaves Bed Bath & Beyond
Walmart Advances Made In U.S.A. Initiative But Faces Challenge
Evolution, Ongoing Growth Bed, Bath & Beyond Annual Meeting Themes
Walmart Working To Correct Made In USA Labeling Issues
QVC Names Singh To Lead Business Planning Group
Digital Subscription Service
Now Available
Click Here
What do the following have in common? Air cleaners. Juicers. Humidifiers. Rice cookers. Bath scales. Water filters. Kitchen scales. Home Spa. Grain Mills. What might seem to some as disparate housewares products have come together in the HomeWorld Business Health & Wellness Report.


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The last student day is Tuesday, June 16, 2015. We wish you a healthy, safe summer break. We'll see you on Wednesday, August 26, 2015.
Welcome to the Patricia A. Hannaford Career Center. Our mission is to provide high quality technical, workplace and continuing educational opportunities for the secondary and adult learners of Addison County. The Hannaford Career Center is located in Middlebury, Vermont.
Like us on Facebook!
The majority of students come from Middlebury Union High School, Mount Abraham Union High School and Vergennes Union High School. We also have students from private schools, homeschooled students, and high schools in the outlying areas.
The Hannaford Career Center offers twelve technical and six foundational programs. For more information, call (802) 382-1012. our FAX # is: (802) 388-2591.


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Respond to Review of KochSalon
by jasminetea
Review: This place mostly served meat (check out their website - you don't need to read German, the pics of the lamb chops will assure you). That said, the waiter was fine to assure us that the invigorating dishes we chose were veggie. It still maintains a small (and I mean small) amount of veg options as it used to be fully veggie and had a reputation for it. May I say the meal was very yummy..... we went with two carnivores who also chose the veggie meals. It shouldn't have gone to the 'dark side'... you'll be hard pressed to find any 100% veggie place in Vienna anyway so you might as well come here if you're not fussed about meat in the kitchen as it was very healthy and compared to say London, quite reasonably prices in my opinion.
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Search for "Home Depot" Sweepstakes
Found 6 total
Enter to win a $100 Home Depot Shopping Spree.
Enter to win Five (5) Grand Prize winners will receive one (1) $250 gift card to Best Buy, and one (1) $250 gift card to Home Depot
One (1) winner will receive a $300 gift card to Home Depot (�Prize�) , a $1,000 Visa Gift Card, and twelve (12) free Home run Inn pizza coupons. Approximate retail value (�ARV�) of the Prize: $1384.00.
Enter to win A Weber Grill EP -310 and a $5,000 Home Depot gift card (terms and conditions of gift card apply). Approximate Retail Value ("ARV"): $6,000.
During the Promotion Period, using a two-way text-messaging capable device ("Device"), text �Weber� to 30364.
Enter to win Grand Prize: $25,000 Cash
Second Prize: $10,000 Cash
Six (6) Third Prize Winners: $2,500 in Home Depot Gift Cards
Enter to win a $150 Home Depot gift card + a copy of New York Times bestselling author�s Barbara Delinsky�s new book Blueprints.


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DTMD's Toine Wants a Better Job for Better Pay on Antoine Jameson
Toine wants to break away from his current financial status, his place as an underground—and somewhat unheralded—rapper, and the D.C. region for a little while. He's made some noise, though: In 2011, Toine turned in a notable performance on Oddisee's song, "Different Now." More recently, he offered a dope verse to Sean Born and Dunc's impressive 2013 EP, Organic.
As the vocal half of DTMD with producer Dunc, Toine raps about his frustrations with the indie grind and whether he should keep on his current path. At times, Toine sounds tired of the rap game. Just as suddenly—usually within the same song—he dismisses the uncertainty and keeps moving forward.
Toine continues the narrative on his debut solo album, Antoine Jameson, but his words have more bite. You feel Toine's angst as the album plays, and find yourself pulling for him the deeper he goes. On "Slow Down," for instance: "Need a better job for a better pay/Bank account catch a comma, shit, I gotta celebrate." At his core, Toine is just a regular dude fighting for the shine he thinks he deserves. He's gonna get it his way or go down swinging.
Antoine Jameson is a light listen, which isn't surprising given the rapper's affable persona. The Largo, Md., wordsmith doesn't take himself too seriously, even if he's complaining about his 9-to-5 job or wanting to move out of his mom's house. On his cover art, Toine is passed out beside a toilet—the photo was taken after a few drinks—and his rhymes go down easy.
Jameson feels like a crew album and, occasionally, you hear Toine and his peers riffing on random topics in between songs. In all, Antoine Jameson is a lyrics-driven album in which the beats take a backseat. Toine has a lot on his mind.
Stream Antoine Jameson after the jump.


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foreclosed on and are now being listed for sale on the open market.
Some of this homes might be in bad shape and need lots of repaires
that why most lenders will not finance. But you can get a real good
deal.If you have additional questions or need an agent feel free to call and direct them to me.
My Direct # 347-813-1290.
Here is my website http://fajardodelacruz.realtors.officelive.com
or my e-mail email@example.com
Hope to hear from you soon.


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Business & FinanceAll Forums
Forums dealing with business, investing, personal finance, and career issues.
Forums focused on civic and government organizations including law enforcement, the military, scouting, and public employee unions
Forums focused on companies and workplaces, as well as customers of certain businesses or products
Forums dealing with computers, operating systems, software, coding, PC gaming, and vintage computers
Forums covering everything from graphic design to music to literature. Many of these forums are focused on message board signatures and forum themes.
Current events forums: Far left to far right and everything in between
Mostly forums for people who went to school together, but these forums also cover adult education, homeschooling, history and languages
Forums covering music, films, television and books along with communities where people gather for fellowship and fun
Forums discussing raising children, family issues, and pregnancy
Forums discussing every kind of game from board games to role-playing games to fantasy sports to trivia
Forums for people to connect with others dealing with specific illnesses and health conditions, along with communities dealing with the health care industry
Forums covering hobbies and interests ranging from stamp collecting to quilting to robotics to woodworking
Forums covering everything you do in and around the home, including cooking, pets, gardening, and more
Forums discussing everything you do online, including Web browsers, message board signatures, email, network security, social networking, HTML, and more
These forums cover a wide range of topics including dating, relationships, gay/lesbian issues, jewelry, clothing and plain old socializing
Forums discussing cars and anything with a motor
Our home for all motorcycle-related forums. Some are club forums. Some are for a specific make or model. Some are for riders in a certain location.
Forums discussing traditional religions, spirituality, atheism, and spiritual beliefs
From astronomy to extraterrestrials, from hard science to the supernatural, these forums cover a wide range of topics
Forums covering traditional sports, auto racing, horses, college and high school sports, shooting sports and more
Forums where people connect with others facing similar health conditions, life situations or hardships
Forums focused on real-time chat
Forums focused on fashion, beauty, food, and popular culture
Forums focused on a certain place -- whether it's for people who live in that place, or those that visit
Are Spring and Fall migrations signs? Where are flesh eating birds prominent in Bible prophecy?
Nothing says Summer fun like bacon wrapped meatballs! This will be a July to remember!
We mean it.
Ball, Gleason, Griffith, VanDyke: the biggest names in comedy all had tv shows. Which was the best?
Watch this scoop of ice cream vanish! (wipes mouth)
Run this security test.