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Four Grain Muffins
16 Nov 2009
|Non-stick cooking spray
|All purpose flour
|3⁄4 Cup (12 tbs)
|Rye flour
|1⁄2 Cup (8 tbs)
|Oat bran
|1⁄2 Cup (8 tbs)
|1⁄4 Cup (4 tbs)
|Firmly packed brown sugar
|3 Tablespoon
|Baking powder
|2 1⁄2 Teaspoon
|1⁄2 Teaspoon
|1% fat milk
|1 Cup (16 tbs)
|Vegetable oil
|1⁄4 Cup (4 tbs)
|1 Large, lightly beaten
|1% milk
|1 Cup (16 tbs)
1 Preheat the oven to 400° F.
Lightly coat twelve 2 1/2 inch muffin cups with cooking spray or insert cupcake liners.
In a large bowl, stir togetherthe all-purpose flour, rye flour, oat bran, cornmeal, sugar, baking powder, and salt until well combined.
With a mixing spoon, make a well in the center.
2 In a small bowl, stirtogetherthe milk, oil, and egg, then pourthe mixture into the well of the dry ingredients.
Stiruntil just combined.
3 Spoon the batter into the prepared muffin cups, filling them 2/3 full.
Bake for 20 minutes or until a toothpick inserted in the center comes out clean.
Let the muffins cool in the pan for 5 minutes, then turn them out onto a wire rack to cool.
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Four Grain Muffins Recipe


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Home Concert Tickets Country and Folk Texas Lightning
Texas Lightning Tickets
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subset: commoncrawl


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Mark 'Rizzn' Hopkins
Founding Editor of SiliconANGLE. Executive Producer of theCube.
Featured Posts
BTC News
- Bitcoin Weekly 2015 July 1: Kraken opens in Canada, Coinbase looks to Australia, itBit and Call Levels, BitTorrent loves BTC Kyt Dotson
- Bitcoin equity crowdfunding site BnkToTheFuture passes the $10m funds raised mark Duncan Riley
- Quoine/ Econtext deal delivers Bitcoin payment option to 20,000 merchants in Japan Duncan Riley
- Bitcoin Weekly 2015 June 24: Bitcoin block size scalability news, Nasdaq partners with Chain, JoyStream BitTorrent for bitcoin, Scrypt.cc hacked Kyt Dotson


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DC residents: click here to call Mayor Muriel Bowser and tell her to prioritize her constituents over the expansion of Exelon's monopoly. Exelon all-but-promises it will raise your electricity ...On May 6, 2015 / By Connor Gibson
For the second time today, Mitt Romney dodged a question about Hurricane Sandy and climate change. After standing by as his supporters drowned out a question about ...On November 1, 2012 / By Travis Nichols
Greenpeace is an independent organization that does not take money from corporations or government. We rely on individual donations from people just like you.Donate


text:
Company Overview of Zurich American Insurance Company Of Illinois
Company Overview
Zurich American Insurance Company Of Illinois offers property and casual insurance services. It provides homeowners, automobile, boiler and machinery, fire and marine, personal injury liability, workers' compensation, and miscellaneous property insurance products and services. The company was incorporated in 1973 and is based in Schaumberg, Illinois. Zurich American Insurance Company of Illinois operates as a subsidiary of American Zurich Insurance Company.
1400 American Lane
Schaumburg, IL 60196-1056
United States
Founded in 1973
Key Executives for Zurich American Insurance Company Of Illinois
Zurich American Insurance Company Of Illinois Key Developments
Zurich American Insurance Co. and Zurich American Insurance Co. of Illinois settled with the California Department of Insurance regarding the use of workers' compensation insurance agreements. Under these agreements, California employers were asked to arbitrate commercial disputes in Chicago, where Zurich is headquartered, and New York law was applied to these disputes. Under the settlement, California employers can now choose to arbitrate disputes in California under California law.
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Our data partners will research the update request and update the information on this page if necessary. Research and follow-up could take several weeks. If you have questions, you can contact them at firstname.lastname@example.com.


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I would like to see special offers for my region
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The prices shown are intended to help you choose your most appropriate journeys. The total price is subject to availability and your actual routing.
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text:
Happy 4th of July!
In honor of Independence Day the Bank of Wisconsin Dells and the Community Bank of Portage will be closed on Saturday, July 4th. We will resume normal business hours on Monday, July 6th.
Have a safe and happy holiday!
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text:
Pakistan's top bravery award winner
At one time the picturesque Swat Valley — nicknamed the Switzerland of Pakistan — was a popular tourist destination for Pakistanis. Honeymooners vacationed along the river.
Then the Taliban in 2007 began infiltrating the valley just 280 kilometers (175 miles) from the capital, eventually assuming near-total control of the region before being ejected in a massive Pakistani military operation in 2009.
The takeover, as well as the Taliban's brutal treatment of civilians in the region, shocked many Pakistanis, who considered militancy to be a far-away problem in Afghanistan or Pakistan's rugged tribal regions.
But Tuesday's attack demonstrated that the Taliban have not been eradicated from the valley and are trying to make their presence felt even three years after the offensive to oust them.
Malala was nominated last year for the International Children's Peace Prize, which is organized by the Dutch organization KidsRights to highlight the work of children around the world. She also was honored last year with one of Pakistan's highest awards for civilians for her bravery.
Image: Pakistani women, hold banners during a protest condemning the attack on schoolgirl Malala Yousufzai, in Islamabad, Pakistan on Wednesday, Oct. 10, 2012


text:
StartUpHire is the place to find Internal Auditing Manager jobs. Review the list of Internal Auditing Manager career opportunities to the left. These Internal Auditing Manager jobs represent some of the most rewarding careers available.
You can refine your job search for Internal Auditing Manager career opportunities by adding a job title, company name, or keyword to the search box above … or click the "Advanced Search" link for more options.
Don't see the employment opportunity you're looking for? Check back soon for more Internal Auditing Manager jobs, or sign up for an email alert (link below) to receive periodic updates on new Internal Auditing Manager jobs.
We are looking for a fun, creative, objective internal auditor to add value and improve our operations by bringing a systematic and disciplined approach to the effectiveness of risk management, control, and governance processes. Our ideal TubeMoguler Internal Audit Manager will6/18/2015 Emeryville, CA Save This Job
The Accounting Manager is an individual contributor, process management role directly involved in financial close, external financial audits, internal policy development, acquisitions, and other accounting and leadership areas. If you love the complexity of tech company6/7/2015 Bothell, WA Save This Job
Position Description The QA Manager is responsible for quality oversight of contract manufacturing (CMO), packaging and testing activities. Act as primary quality contact/liaison with CMO quality organizations. Serves as product quality representative on cross functional project6/7/2015 Cambridge, MA Save This Job
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Location:Columbus, MS Job Code:1250 # of openings:1 DESCRIPTION Be Part of the Next Generation of Flight Aurora Flight Sciences is a leader in unmanned aerial systems, with a fleet of innovative aircraft designed to empower small tactical units, and safeguard our borders.5/30/2015 Columbus, MS Save This Job
Position Location: Intematix Corporate Headquarters, Fremont, CA General Purpose/Objective: Plans and implements activities related to the timely, cost-effective procurement, inventory control, planning and quality control of production materials. Develops, implements, and6/22/2015 Fremont, CA Save This Job
Job description Position Description This position is primarily responsible for Quality Assurance activities to support R&D development projects - including clinical and preclinical studies. This position will mainly be focused in supporting cGMP activities and projects and6/18/2015 Menlo Park, CA Save This Job
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Responsibilities: ? Cross functional role leading compliance and security efforts across the organization ? Hands-on experience managing Zuora?s compliance efforts (PCI DSS, SSAE 16, SOC 2, HIPAA, ISO 27001, CSA Star) ? Develop and interpret company policies and procedures ?7/1/2015 Foster City, CA Save This Job
ID 2014-2148 Job Location US-CA-City of Industry - HQ Posted Date 10/8/2014 Category Audit More information about this job: Purpose Of The Job: This role will be integral in developing, implementing and maintaining an effective and efficient IT control environment at Newegg,5/4/2015 City of Industry, CA Save This Job
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Location:Audubon, PA Job Code:PACLT0515 Description The Professional Affairs Coordinator will provide administrative and data management support at the direction of the Manager, Professional Affairs Administration. This will include data entry, data verification, work activity6/7/2015 Audubon, PA Save This Job
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Position Summary: Assist Quality Management stream in the development and implementation of the evolving and existing Quality Management Systems. Provide an important oversight role by auditing and assessing projects, suppliers and processes and reporting the results. Must5/4/2015 Plymouth Meeting, PA Save This Job


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"This is hands down the best computer repair business in the Northwest! My wife has a home business that is dependent upon a data base buried inside a ..."
"Had 2 computers taken in - 1 bad Hard drive and another I just wanted to get cleaned up (although wound up replacing the hard drive). Different individuals ..."
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"They really know what they are doing and doing amazing. I don't need to emphasize on how well they are in repairing, as other users did mention. They ..."
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"CyberStreams Inc is a perfect place for anyone who needs best IT services. Staff is efficient, knowledgeable and professional."
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"If you are like me, you normally would feel helpless when computer crashes... That happened to me couple days before New Years. Taking it to a repair shop, ..."


text:
Hillary's Wiretaps
Documents from whistle-blower Edward Snowden and published by The Guardian indicate that the NSA tapped the phones of 35 foreign leaders without their knowledge or permission. The revelation comes on top of the existing controversy surrounding taps placed on the phones of German Chancellor Angela Merkel and Mexican President Felipe Calderon.
But these disclosures beg the question: Who knew about the taps? Who got the intercepts? Obviously, the Secretary of State knew, approved, and authorized the taps. At the very least, she obviously got the intercept texts and/or intelligence reports based on them.
Domestic NSA spying is President Obama's scandal.
Foreign NSA spying is Hillary Clinton's scandal.
As a potential candidate for president, Hillary owes us an explanation of her role in the decision to wiretap and why she authorized it or, at the very least, let it continue.
We know that Hillary frequently is prone to demanding extensive investigation of personal information. Early in her term as secretary of state, she ordered her staff to prepare memos on the personal habits of foreign diplomats and to provide any information they happened upon to the agency so as to develop a profile on these officials.
Snowden's revelations also suggest that "a U.S. official provided NSA with 200 phone numbers to 35 world leaders … Despite the fact that the majority is probably available via open source, the PCs [intelligence production centers] have noted 43 previously unknown phone numbers. These numbers plus several others have been tasked."
The document continues by saying the new phone numbers had helped the agency discover still more new contact details to add to their monitoring: "These numbers have provided lead information to other numbers that have subsequently been tasked."
Question: Was the official in question an employee or contractor with the State Department? Did Hillary materially aid in the eavesdropping?
Hillary must come out of hiding to answer these questions. Having resigned, she will not be at the G-8 summit when the foreign leaders grill Obama and John Kerry on the taps. But she should be, and she must answer these questions.
More to the point, the media must insist that she answer them.
This is Hillary's scandal. Let her answer for it.
Also see,
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text:
They feel bad, so they found you these other deals to make up for it.
Select Local Merchants
Slone Refrigeration Co.Read MoreSlone Refrigeration is a full service, residential and commercial food service equipment company serving the Tri-State and surrounding areas for over 50 years.2432 Greenup AveAshland, KY US
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text:
Paulthomasanderson? No kidding?
no way, I almost never see anything posted by that guy.
I'm joking. come on.
what are you getting at?
when did I start potsing 7 times a day?
Where are you posting? Is there a Gogol Bordello lounge I haven't found?
He is all about Gorillaz and Faith No More being complete locks in the rumors forum. So thats where all the posts come from.
i can't believe i made the list once. i'm not sure if i should feel proud or pathetic. man, i really need to get back to work.
funny thread, GPS.
I'm somewhat suprised that I've managed to evade the list all this time. You don't suppose the Board Reader also has me on ignore, do you?
Anything with E becomes a dance party. My vacuum cleaner becomes a dance party on E
Quick question, has anyone else here actually held a fetus? They're not very cute.
then why would PTA be on the top. he should never make the list using that rubrick, GPS. just sayin'


text:
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text:
Reporting from San Francisco — Walking across the visiting clubhouse at AT&T Park, Rafael Furcal pointed at one of the vertical support structures in the middle of the room.
"Check the lineup," he said, laughing. "I'm the only No. 3 hitter who can bunt."
This is what it had come to for the Dodgers: the leadoff hitter batting third.
But Manager Joe Torre's desperate act to awaken his slumbering lineup Sunday didn't change anything.
The Dodgers lost to the San Francisco Giants again, this time by a 2-0 margin. Their fifth consecutive defeat resulted in them falling eight games back of the first-place San Diego Padres in the National League West and 61/2 games back of the Giants in the wild-card race. They dropped into fourth place in the division, passed by the injury-riddled Colorado Rockies.
"I know we're better and I know it's going to turn around," Torre said. "The only question is when it's going to happen. We need for it to happen sooner rather than later."


text:
Possible Duplicate:
Is it possible to program iPhone in C++
iOS iPhone 4th. If I just open the Xcode 3 or 4, and write a program in c++, Xcode compile it and run?
marked as duplicate by Macmade, Robert Harvey♦ Apr 23 '11 at 17:52
This question has been asked before and already has an answer. If those answers do not fully address your question, please ask a new question.
You can create a new project by using template but they are Objective-c Moreover, unless you have a developer payed account, it will only run on the Iphone Simulator


text:
latest from Bacolod Sports
ELEVEN young footballers from Negros Occidental will again wear the Philippine colors when the 2015 Asean Football Federation (AFF) under-16 (U16) Youth Championship and the U14 Regional Asian Football Confederation (AFC) Festival of Football 2015Read more
BACOLOD City's Festa survived host-University of St. La Salle-A in three sets to capture the 2nd USLS Sepak Takraw Open Invitational title on Wednesday at the Bro. Rolly Dizon Covered Court in Bacolod City.Read more
DESPITE losing its last elimination round match against Team Ballesteros, 83-95, Team Bong Ibe kept the top spot in the standings and will enjoy a twice-to-beat advantage in the semifinals of Your Basketball Athletic Club (YBAC) 2nd Conference SatRead more
MURCIA Basketball Athletic Club (MuBac) solidified its number two spot in the 40Up category of the 2015 Sharp-Basketball Unified Sports Group Invitationals.Read more
AN EXCITING double header will be seen tonight at the STI-West Negros University gym when four teams fight for the two semifinal spots in the D-League Invitational Basketball Tournament.Read more
Current World Boxing Organization (WBO) and Ring magazine junior flyweight champion Donnie Nietes (35-4-1, 21KOs) of Murcia is ready to take on Mexican challenger Francisco Rodriguez Jr. (17-2-1,11KOs).Read more
The 2nd University of St. La Salle (USLS) Sepak Takraw Open unfurls today at the Bro. Rolly Dizon FSC Covered Court in Bacolod City.
Sixteen teams will be featured in the event held in line with USLS's 63rd year.Read more
Bacolod City's Ceres-La Salle FC continues to show its dominance in the premier division of the United Football League (UFL) with a clean 10-0 record after routing top clubs in the league with huge margins.Read more


text: Social media reacted negatively Wednesday to new "Ri5e to the Occasion" shirts that adidas began selling on its website for $24.99 a pop. The shirt references a slogan already used in Louisville team apparel, but is modified slightly to include the No. 5, that of which currently belongs to guard Kevin Ware.


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- Filed Under
SAN JOSE, Calif. -- The Red Wings ran out of rallies Thursday night in San Jose, ultimately unable to write their names into history despite a valiant effort.
They trailed by two goals after 20 minutes and couldn't recover, losing, 3-2, at HP Pavilion in the Western Conference semifinals to the San Jose Sharks, the same team that knocked them out a year ago in five games.
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text:
An integrated circuit with power-up-warning circuitry wherein time integration and voltage level testing are done sequentially instead of simultaneously. A reference voltage is generated by current sourced to a reference voltage circuit, and this reference voltage is used as follows: An inverter receives the reference voltage as an input, and switches when the power supply becomes high enough that the reference voltage appears as a "low" level. When this inverter switches, current begins to be sourced to a timing capacitor. After the timing capacitor has charged up to a predetermined level, the current source to the reference-voltage node is turned off, and the power-up-warning signal (which has been driven high by output buffers) is turned off.
1. A CMOS integrated circuit, comprising:
a first pull-up device connected to source current to a first node,
a reference-voltage current path, connected to hold the potential of said first node to at most a predetermined reference voltage,
an inverting logic stage connected to receive the potential of said first node as an input thereto;
an integration capacitor, and a second pull-up device connected to source current to said integration capacitor as soon as said inverting logic stage provides a "high" output voltage;
a thresholding logic stage, configured to initially assume a first logical state at power-up, and connected to switch from said first state to a second state whenever said capacitor has been charged to a predetermined threshold level; and
an output buffer chain, comprising one or more output buffer stages, which is operatively connected to drive a power-up warning signal line high when said thresholding logic stage is in said first state, but not when said thresholding logic stage is in said second state;
said first pull-up being operatively connected to stop sourcing current when said thresholding logic stage switches to said second state.
2. The integrated circuit of claim 1, further comprising additional circuitry which is connected to be disabled whenever said power-up warning signal is high.
3. The integrated circuit of claim 1, wherein said first pull-up device comprises a relatively strong PMOS transistor.
4. The integrated circuit of claim 1, wherein said first pull-up device consists essentially of a CMOS inverter which includes an NMOS driver and a PMOS driver which is stronger than said NMOS driver.
5. The integrated circuit of claim 1, wherein said thresholding logic stage consists essentially of an inverter.
6. The integrated circuit of claim 1, wherein said thresholding logic stage consists essentially of a CMOS inverter having approximately equal NMOS and PMOS driver strengths.
7. The integrated circuit of claim 1, wherein said reference-voltage current path consists essentially of an NMOS transistor having a gate and a drain both connected to said first node.
8. The integrated circuit of claim 1, wherein said predetermined reference voltage is approximately equal to the threshold voltage of an NMOS transistor in said integrated circuit.
9. A method for generating a power-up warning signal when power is first applied to an integrated circuit, comprising the steps of:
(a) sourcing current from a power-supply voltage to a first node, said first node being clamped to a maximum voltage which is equal, at least approximately, to a predetermined reference voltage;
(b) driving a power-up warning signal high with a chain of one or more output buffer stages as soon as the power-supply voltage is high enough to power said output buffer stages;
(c) testing the voltage of said first node, to ascertain whether the power-supply voltage has come up to a level high enough that the voltage of said first node can be recognized by a following logic gate as a "low" level;
(d) turning on a weak pull-up device,
after the voltage of said first node has been recognized by said following logic gate as a "low" level,
to supply charging current to an integration capacitor;
(e) and, after said integration capacitor has charged up to a predetermined voltage level, then
propagating a logic signal to drive said power-up signal low, and
propagating a logic signal to reduce current sourcing to said first node.
10. The method of claim 9, wherein said step (a) sources current to said first node from a strong PMOS pull-up device.
11. The method of claim 9, wherein said step (a) sources current to said first node from a CMOS inverter which includes a PMOS driver which is stronger than a respective NMOS driver thereof.
12. The method of claim 9, wherein said step (a) sources current to said first node through a resistive load.
13. The method of claim 9, wherein said chain of output buffer stages consists of an odd number of inverters.
14. The method of claim 9, wherein said chain of output buffer stages consists of an odd number of inverters, and is driven by a chain of very weak inverters.
15. The method of claim 9, wherein said chain of output buffer stages consists of an odd number of inverters, and is driven by a chain of inverters each having greater width than length in both PMOS and NMOS devices thereof.
16. The method of claim 9, wherein said chain of output buffer stages consists of an odd number of inverters, and is driven by a chain of inverters each having an NMOS driver which is stronger than a respective PMOS driver thereof.
17. The method of claim 9, wherein the voltage of said first node is regulated to be approximately one VTN above ground.
18. A power-on integrated circuit detector, comprising:
(a) a first pull-up device connecting a clamped node to a power supply;
(b) a switch powered by said power supply, said switch changing from a first state to a second state when the potential difference between said power supply and said clamped node becomes larger that a first threshold potential;
(c) a resistive pull-up device with connected between said power supply and a delay capacitor, said pull-up device turned on when said switch is in said second state;
(d) an output switch powered by said power supply, said output switch changing from a third state to a fourth state when the potential on said capacitor becomes larger than a second threshold potential, whereby the time delay from said first switch changing state to said output switch changing state depends upon the capacitance of said capacitor and the resistance of said resistive pull-up device; and
(e) a feedback from said output switch to said first pull-up device with said first pull-up device turned off when said output switch is in said fourth state, whereby to potential of said clamped node drops below the clamp level and prevents power consumption.
All of the material in this patent application is subject to copyright protection under the copyright laws of the United States and of other countries. As of the first effective filing date of the present application, this material is protected as unpublished material.
Portions of the material in the specification and drawings of this patent application are also subject to protection under the maskwork registration laws of the United States and of other countries.
However, permission to copy this material is hereby granted to the extent that the owner of the copyright and maskwork rights has no objection t the facsimile reproduction by anyone of the patent document or patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright and maskwork rights whatsoever.
The following application of common assignee contains related subject matter, and is believed to have an effective filing data identical with that of the present application:
Ser. No. 628,691, filed Dec. 14, 1990, entitled "TRANSFER CIRCUIT FOR PREVENTING COLLISION ON USER READ," (DSC-187); which is hereby incorporated by reference.
The present invention relates to low-power integrated circuits generally, and particularly to battery-backed integrated circuits.
The disclosed embodiments provide a new circuit for generating a power-up warning signal, and a new way of operating an integrated circuit (using such a power-up warning signal).
If power were suddenly applied to all parts of a complex logic circuit, the logical state of the circuit might be unpredictable. For example, a flip-flop might come up to one state on one power-up, and in a different state on the next power-up. This is undesirable for several reasons:
Self-checking operations generally require that the circuit be in a known state to start with.
It may take many cycles to force complex logic into a known state, if the starting state is unknown.
Even worse, some of the states of a complex logic circuit (unless the circuit is specifically designed to avoid this) may be "stuck" states, from which normal operation of the logic cannot recover.
A different possible problem can arise in a CMOS circuit when the supply voltage is marginally low (e.g. greater than VTM, but less than VTM +VTP). At such marginally low voltages, some of the logic nodes will typically be floating, and the logic state of other nodes may depend on the (unpredictable) analog voltage of the floating node. As the supply voltage further increases (above VTM +VTP), some of the anomalous node values which occurred in the low-voltage regime may be "frozen in," resulting, again, in an unknown logic state.
Thus, two conditions are required before the circuit can safely enter normal operation: a certain minimum time must have elapsed; and the supply voltage must have reached a certain minimum level.
To prevent such problems, many prior art integrated circuits will generate a "power-up" signal for a brief period when power is first turned on. This logic signal is connected to various gates around the chip, so that, when power has just been turned on, these gates will prevent the logic from commencing normal operation, and will force logic elements into a known state.1 After a certain minimum time delay, the logic will reliably have reached a known state. At that point, the logic can be allowed to begin its normal operation, where propagation of digital logic states is allowed.
Thus, the power-up signal is used not only for resetting circuits, but also for disabling normal operation for long enough to provide a safety margin. If the power-up signal terminates too soon, the circuit may be unreliable; if the power-up signal lasts longer than it needs to, time will be wasted on every power-up; and if the power-p signal never terminates, the circuit will certainly be operative.
As noted, two conditions must be satisfied before the circuit can safely enter normal operation. Two circuits are normally used to test for these two conditions: an integrating capacitor, with a relatively long time constant, is used to ensure that the desired minimum time has elapsed; and a reference voltage element, driven by a load, is used to assure that the supply voltage has reached the desired minimum level. The two corresponding output signals are (effectively) ANDed to assure that the power-up transition is complete.
FIG. 8 shows an example of such a previously-used circuit. Note that the pull-up resistor sources current to ground whenever the power is on.
According to the present invention, time integration and voltage level testing are done sequentially instead of simultaneously. A reference voltage is generated by a reference voltage circuit.2 An inverter receives the reference voltage as an input, and will switch when the power supply becomes high enough. After this inverter switches, current is then sourced to a timing capacitor. After the capacitor has charged up to a predetermined level, the current source to the reference voltage node is turned off, and the power-up warning signal (which had been driven high by output buffers) is turned off.
Thus, no power is consumed by this feature except during the transitional period immediately after power is applied.
In the presently preferred embodiment, several sequential stages of operation can be identified, as voltage VDD increases from zero:3
1. As VDD comes up above VTP, a strong PMOS pull-up will begin to source current to a reference-voltage node, until the reference voltage node comes up to its regulated value (VTM, in the presently preferred embodiment).4
2. A chain of very weak inverters5 is connected to drive an output buffer chain6 which provides the power-up warning signal (signal "PWRUP", in the presently preferred embodiment). The chain of weak inverters provides an output which will initially be low, so that, after the output buffer chain has been powered up, signal PWRUP will go high.
3. As the power supply comes above VTM +VTP, the inverter following the reference voltage node will begin to turn on, and eventually this inverter will switch to drive its output high.7
4. A weak pull-up will then begin to supply charging current to the integration capacitor.
5. After the integration capacitor has charged up to the following inverter's trip point (which is about 1/2VDD, in the presently preferred embodiment), two things happen:
5.1. This gate drives the chain of weak inverters which lead to the output buffer chain. Thus, after a small further delay, the power-up signal will go low.
5.2. This gate also is connected back to turn off the PMOS pull-up which is sourcing current to the reference voltage node.
Greater detail may be seen from FIGS. 1 and 2, as discussed below. (FIG. 2 is a SPICE simulation of voltages at marked nodes of FIG. 1, as the power supply VDD comes up.)
The present invention provides several advantages: First, there can be no current burn during the low-voltage analog period before device threshold voltages are reached. Second, since continuing current burn is not a problem, the resistor can be made of lower value. This saves space in the layout.
The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
FIG. 1 shows the presently preferred embodiment of a power-up circuit according to the present invention.
FIG. 2 shows a simulation of the voltages appearing at various nodes of the circuit of FIG. 1 as the power supply voltage increases from zero.
FIG. 3 shows the main elements of the serial timekeeper chip embodiment.
FIGS. 4-7 illustrate data transfer operations in the serial timekeeper chip embodiment of FIG. 3: FIG. 4 shows single byte transfer; FIG. 5 shows burst mode transfer; FIG. 6 shows write data transfer; and FIG. 7 shows a read data transfer.
FIG. 8 shows an example of a previously-used power-up circuit. Note that the pull-up resistor sources current to ground whenever the power is on.
The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment, which provides a serial timekeeping chip, which can be accessed by a user, over a serial bus, to get clock and calendar information. The disclosed innovations will therefore be described in the context of that chip. However, it must be appreciated that the disclosed innovations are not by any means limited to such a context, and this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
FIG. 1 shows the presently preferred embodiment of a power-up circuit according to the present invention, and FIG. 2 shows a simulation of the voltages appearing at various nodes of the circuit of FIG. 1 as the power supply voltage increases.
Note that inverter 120 is highly asymmetrical: its Wp 8 is 50 microns, but its WN is only 3.2 microns. (this helps to assure that node P13 will initially track the rising voltage VDD./) Thus, as the power supply voltage VDD begins to rise, inverter 120 will begin to source current to resistor 104 and NMOS depletion load 105, thereby pulling up the voltage of node A.
The presently preferred embodiment has been realized with a minimum nominal (drawn) dimension of 1.2 microns. Of course, as is well known to processing engineers, the actual dimensions may vary from the nominal dimensions, and the nominal dimensions can readily be varied according to known scaling laws.
As node A comes up to about VTM, transistor 106 will turn on and hold the node voltage reasonably constant. (See curve "a" in FIG. 2). Transistor 106 has nominal dimensions, in the presently preferred embodiment, of WN =50 μm and LN =10 μm.
Node B is driven by a gate 108, which has nominal dimensions, in the presently preferred embodiment, of WP =10 μm, WN =25 μm, LP =10 μm, and LN =10 μm. This gate is a Schmitt trigger, which also includes a feedback transistor P1 having nominal dimensions of Wp1 =10 μm and LP1 =10 μm.
Node C is driven by an inverter 110, which has nominal dimensions, in the presently preferred embodiment, of WP =20 μm, WN =3.2 μm, LP =1.2 μm, and LN =1.2 μm.
Node D is driven by weak gate 112, which has nominal dimensions, in the presently preferred embodiment, of WP =3.2 μm, WN =3.2 μm, LP =50 μm, and LN =1.2 μm. The current sourced to node D must charge capacitor 114 (which, in the presently preferred embodiment, is a MOs capacitor of about 525 μm2, with a capacitance, at 5 Volts, of about 1 Pf). The long LP of gate 112 reduces the current sourced to capacitor 114. Thus, as shown by curve "d" in FIG. 2, this node comes up fairly slowly, even after gate 112 has turned on.
Node E is driven by a gate 116, which has nominal dimensions, in the presently preferred embodiment, of WP =6.8 μm, WN =3.2 μm, LP =1.2 μm, and LN =1.2 μm. This gate is a Schmitt trigger, which also includes a feedback transistor P1 having nominal dimensions of WP1 =3.2 μm and LP1 =5 μm.
Signal PWRUP is driven, in the presently preferred embodiment, by a chain of 10 inverters following node E. Seven weak inverters 122 (each having WP =7 μm, WN =5 l μm, LP =40 μm, and LN =40 μm) are followed by successively larger inverters 124, 126, and 128, to produce signal PWRUP.
Node E is also followed by inverter 118, which drives inverter 120. Thus, when node E is driven low, node P13 will be driven low soon thereafter. (The low level on node E will also bring signal PWRUP low, after a delay determined by weak gates 122.) Thus, when the power-up transition is completed, current to resistor 104 is turned off, and essentially no DC current burn occurs.
In the case where VDD rises very slowly, the circuit shown will typically trip at a DC level of VDD =3.5 V; but the circuit trip point may be as low as 2.1 Volts (at 100� C., where processing variation has produced strong NMOS devices and weak PMOS devices) or a high as 4.5 Volts (at -55� C., where processing variation has produced weak NMOS devices and strong PMOS devices).
Note that several of these gates have asymmetrical device sizes. A CMOS gate will usually be dimensioned with WP about two to three times as large as WN, which will typically give a gate threshold voltage of about half the supply voltage. However, note that several of the gates shown depart markedly from this range of ratios.
FIG. 2 shows a detailed simulation of the voltages appearing at various nodes of the circuit of FIG. 1 as the power supply voltage VDD increases from zero. This simulation was made using SPICE, a software package which is widely used for detailed analysis of circuit behavior.
Initially (while VDD is still less than |VTN | or |VTP |), node A will be low, and node B will (approximately) follow VDD up.
When VDD exceeds |VTP |, the strong P-channel device of gate 120 will turn on and pull node P13 high.
Node A will then be pulled up (with a slew rate limited by resistor 104), until it reaches VTN. (node A is clamped at VTN by transistor 106.)
When node B reaches VTN (at approximately the same time as node A reaches VTN), it will go to ground.
Note that node C (which initially follows VDD up) starts to fall as node A starts to rise; but very soon thereafter, as node B falls, node C returns to FDD.
At about the time VDD reaches 2.2V (in this example), the PWRUP signal rises sharply. (The timing of this is largely determined by the delay of gates 122. Note that node E, which provides the input to gates 122, follows VDD up during the early stages.)
When VDD exceeds VTN plus the threshold voltage of gate 108 (about 3.5 V, in the presently preferred embodiment), gate 108 switches, and drives node B high. This drives node C low, and turns on the weak pullup transistor of gate 112. This slowly drives node D high. When node D has reached the threshold voltage of gate 116, node E goes low, and node P13 goes low. After a propagation delay (due to gates 122), signal PWRUP then goes low.
The preferred integrated circuit embodiment, in which the disclosed innovative circuitry is used to provide a serial timekeeper chip, will now be described in detail. These details merely represent a contemplated example of making and using the claimed inventions, and are not all necessary for practicing the claimed inventions.
Some distinctive features of the preferred serial timekeeper chip include the following:
Real Time clock counts seconds, minutes, hours, date of the month, month, day of the week and year with Leap Year compensation
24�8 RAM for scratch pad data storage
Serial I/O for minimum pin count
2.5 volt clock operation
Uses less than 1 μA at 3 volts
Single byte or multiple byte (burst mode) data transfer for read or write of clock or RAM data
8-pin DIP or optional 16-pin SOIC for surface mount
Simple 3-wire interface
TTL compatible (Vcc =5V)
The presently preferred best mode integrated circuit embodiment uses an 8-pin DIP package, with the following pins. An asterisk (*) represents a complemented or inverted signal.
______________________________________N.C. No ConnectionX1, X2 32.768 kHz Crystal InputsGND GroundRST* ResetI/O Data Input/OutputSCLK Serial ClockVCC Power Supply Pin______________________________________
The chip contains a RealTime Clock/Calendar, 24 bytes of static RAM, and communicates with a microprocessor via a simple serial interface. The RealTime Clock/Calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month data is automatically adjusted for months with less than 31 days, including corrections for leap Year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Interfacing the Serial timekeeper chip with a microprocessor is simplified using synchronous serial communication. Only three wires are required to communicate with the Clock/RAM: (1)RST* (Reset), (2) I/O (Data line), and (3) SCLK (Serial Clock). Data can be transferred to and from the Clock/RAM one byte at a time or in a burst of up to 24 bytes. The serial timekeeper chip is designed to operate on very low power and retain data and clock information on less than 3 microwatts.
The main elements of the serial timekeeper chip are shown in FIG. 3, namely, shift register, control logic, oscillator, real time clock and RAM. To initiate any transfer of data, RST* is taken high and eight bits are loaded into the shift register providing both address and command information. Each bit is serially input on the rising edge of the clock input. The first eight bits specify which of 32 bytes will be accessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock cycles have occurred which load the command word into the shift register, additional clocks will output data for a read, or input data for a write. The number of clock pulses equals eight plus eight for byte mode or eight plus up to 192 for burst mode.
Each data transfer is initiated by a one byte input called the address/command byte. The format of the address/command byte is shown in Table 1.
As defined, the MSB (Bit 7) must be a logical one. If zero, further action will be terminated. Bit 6 specifies a clock/calendar register if logic zero or a RAM location if Logical One. Bits one through five specify the designated registers to be input or output and the LSB (Bit 0) specifies a write operation (input) if logical zero or read operation output if logical one. To initiate any write operation, the write protect bit must be set to zero.
Burst Mode may be specified for either the clock/calendar or the RAM registers by initiating a burst mode command. Bit 6 specifies clock or RAM and bit 0 specifies read or write. There is not data storage capacity in the Clock/Calendar or in the RAM for command bytes.
Before any write operation to clock/calendar or RAM, the write protect bit must be set to zero. This operation requires driving the RST* high and the write protect command, 8EH, is loaded into the shift register followed by eight bits, 00H. RST* must be driven before any other command can be initiated. To restore write protect, drive RST* high followed by WRITE command byte, 8EH, and data byte 80H. Sixteen clock cycles are required for this operation. Complete the operation by driving RST* low.
All data transfers are initiated by driving the RST* input high. The RST* input serves two functions. First, RST* turns on the control logic which allows access to the shift register for the address/command sequence. Second, the RST* signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. All data transfer terminates if the RST input i low and the I/O pin goes to a high impedance state. Data transfer is illustrated in FIGS. 4-7; FIG. 4 shows single byte transfer; FIG. 5 shows burst mode transfer; FIG. 6 shows write data transfer; and FIG. 7 shows a read data transfer.
Following the eight SCLK cycles that input the write mode command byte a data byte is read on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur.
Following the eight SCLK cycles that input the read mode command byte a data bit is read out on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted from the clock/RAM occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst read mode capability.
The Clock/Calendar is contained in eight writable/readable registers as shown in Table 2. Data contained in the clock/calendar registers is in binary coded decimal format (BCD).
Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic one, the clock oscillator is stopped and the serial timekeeper chip is placed into a low power standby mode with a current drain of not more than 1.0 microamp. When this bit is written to logical zero, the clock will start.
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20+hours).
Bit 7 of write protect register is the write protect bit. The first seven bits (bits 0-6) are forced to zero and will always read a zero when read. Bit 7 is set to logical one on power up and before any write operation to CLK or RAM, bit 7 must be set to zero. When high, the write protect bit prevents a write operation to any other register.
The clock/calendar command byte specifies burst mode operation. In this mode the eight clock/calendar registers may be consecutively read or written.
The Static RAM is 24�8 bytes addressed consecutively in the RAM address space.
The RAM command byte specifies burst mode operation. In this mode, the 24 RAM registers may be consecutively read or written.
A register data format summary is shown in Table 2, above.
A 32,768 kHz crystal, Daiwa part No. DT26S, Seiko Part No. DS-VT-200 or equivalent, can be directly connected to the serial timekeeper chip via pins 2 and 3 (X1,X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pF.
The following tables give specific values for some of the voltage and timing parameters just referred to, as used in the specific context of the presently preferred embodiment. It must be understood that these specific values are given merely to provide a wealth of detail regarding the described chip embodiment, and do not by any means delimit necessary features of the invention.
__________________________________________________________________________ABSOLUTE MAXIMUM RATINGS:__________________________________________________________________________VOLTAGE ON ANY PIN RELATIVE TO GROUND -0.5 V TO +7.0 VOPERATING TEMPERATURE 0� C. TO +70� C.STORAGE TEMPERATURE -55� C. TO +125� C.SOLDERING TEMPERATURE 260� C. FOR 10 SEC__________________________________________________________________________PARAMETER SYMBOL MIN TYP MAX UNITS NOTES__________________________________________________________________________RECOMMENDED D.C. OPERATING CONDITIONS (0� to �70� C.)Supply Voltage VCC 4.5 5.0 5.5 VOLTS 1Standby VCC1 3.0 5.5 VOLTS 1Supply VoltageLogic 1 Input VIH 2.0 VCC VOLTS 1Logic 0 Input VIL -0.5 0.8 VOLTS 1DC Electrical Characteristics (0� to +70� C., VCC = 5V � 10%)Input Leakage ILI +500 μA 6I/O Leakage ILO +500 μA 6Logic 1 Output VOH 2.4 VOLTS 2Logic 0 Output VOL 0.4 VOLTS 3Active Supply ICC 4 mA 4CurrentStandby Supply ICC1 1 μA 5CurrentStandby Supply ICC2 100 nA 10CurrentCAPACITANCE (TA = 25� C.)Input Capacitance CI 5 pFI/O Capacitance CI/O 10 pFCrystal Capacitance CX 6 pFAC Electrical Characteristics (VCC = +5 V � 10%,0�-70� C.)Data To CLK Setup tDC 50 ns 7CLK To Data Hold tCDH 70 ns 7CLK To Data Delay tCDD 200 ns 7,8,9CLK Low Time tCC 250 ns 7CLK High Time tCH 250 ns 7CLK Frequency fCLK D.C. 2.0 MHz 7CLK Rise & Fall tF 500 nsRST To CLK Setup tCS 1 us 7CLK To RST Hold tCCH 60 ns 7RST Inactive Time tCWH 1 us 7RST To I/O High Z tCDZ 70 ns 7__________________________________________________________________________ NOTES TO THE TABLES: 1 All voltages are referenced to ground. 2 Logic one voltages are specified at a source current of 1 mA. 3 Logic zero voltages are specified at a sink current of 4 mA. 4 ICC is specified with the I/O pin open. 5 ICC1 is specified with VCC at 3.0 volts and RST*, I/O, and SCLK are open. 6 RST*, SCLK and I/O all have 40 kQ pull down resistors to ground. 7 Measured at VIH = 2.0 V or VIL = 0.8 V and 10 ms maximum rise and fall time. 8 Measured at VOH = 2.4 V or VOL = 0.4 V. 9 Load capacitance = 50 pF. 10 ICC2 is specified with VCC at 3.0 volts and RST*, I/O, and SCLK are open. The clock halt flag must also be set to logic one.
It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.
Of course, various of the logic gates which are shown as inverters in the presently preferred embodiment could alternatively be configured as NAND gates, NOR gates, or other structures. This might be done, for example, if it is desired to be able to force the power-up signal high from an external pin, in a system where some components may be powered down while others remain active.
As will be recognized by those skilled in the art, the innovative concepts described in the preset application can be modified and varied over a tremendous range of applications, and accordingly their scope is not limited except by the allowed claims.
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Gates Opens: 6:30 pm • Bands play: 7:30 to 10:30pm
The Sangre de Cristo Arts Center's renowned Festival Fridays concerts provide the opportunity to socialize with friends in a casual environment offering cocktails, food for all tastes and outstanding live musical entertainment. Join us for 5 Fridays in a row as we turn the Jackson Sculpture Garden into a live music venue.
Band Lineup
July 10 - Makeshift Funk Band made its Festival Fridays debut this Winter to rave reviews and a hopping dancefloor. The seven piece horn band from Denver specializes in funk, R&B and dance. Enjoy popular hits like "Hold On, I'm Coming" and "Into the Mystic" as the Makeshift Funk Band brings your favorites to the stage.
July 17 - Thumpin has become one of the most popular bands on the Denver music scene, drawing enthusiastic crowds and amassing a loyal following who love what this band does: provides its audiences with music that moves the body and soul. Enjoy this fun arrangement of funk, soul, and R&B with songs from The Temptations and Al Green to Bruno Mars and Prince as Thumpin' performs on the Festival Fridays stage once again.
July 24 - Bad Habitz pays tribute the Pueblo's roots as the award-winning band brings Tejano music to the Arts Center. Named 2012 Best Tejano Band in Colorado, Bad Habitz knows what it takes to get Pueblo on the dance floor.
July 31 - The Martini Shot performs the pop hits that earned their titles of "Best Cover Band" and the "Best Original and Cover Band" by readers of the Colorado Springs Independent, and "Pueblo's Best Local Band" twice by the Pueblo Business Journal. Be mesmerized as the six-piece Pop-Rock Pueblo shows you why they are continuously named the best.
August 7 - That Eighties Band brings its high energy show and proves why it's one of the most popular 80's tribute bands in America. Named "Top cover band in Denver" by CBS Denver, the group has performed for Google, Disney, Pepsi, The Denver Broncos, Colorado Avalanche, and now takes the Festival Fridays stage at the Sangre de Cristo Arts Center.
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B'day (2006)
|Artist: Beyonce
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CONDITION: Brand New
IN STOCK: Usually Ships in 1 to 2 business days
Seller Information
Learn more about B'day:
Format: CD
Manufacturer: Cbs/epic/wtg Records
Sku: 204822288
Release Date: 6/13/2007
See more in R&B / Soul
Song Listing
Disc 1
Song Title
1. Beautiful Liar ~ Beyonc?
2. Irreplaceable ~ Beyonc?
3. Green Light ~ Beyonc?
4. Kitty Kat ~ Beyonc?
5. Welcome to Hollywood ~ Beyonc?
6. Upgrade U ~ Beyonc?
7. Flaws And All ~ Beyonc?
8. World Wide Woman ~ Beyonc?
9. Get Me Bodied - (Extended mix) ~ Beyonc?
10. If ~ Beyonc?
11. Freakum Dress ~ Beyonc?
12. Suga Mama ~ Beyonc?
13. Deja Vu ~ Beyonc?
14. Ring The Alarm ~ Beyonc?
15. Resentment ~ Beyonc?
16. Listen - (From The Motion Picture 'Dreamgirls') ~ Beyonc?
Disc 2
Song Title
1. Amor Gitano ~ Beyonc?
2. Listen ~ Beyonc?
3. Irreplaceable ~ Beyonc?
4. Beautiful Liar ~ Beyonc?
5. Beautiful Liar - (Remix, remix) ~ Beyonc?
6. Beautiful Liar - (Spanglish version) ~ Beyonc?
7. Irreplaceable - (Nortena Remix, Nortena remix) ~ Beyonc?
Album Notes and Credits
Notes & Personnel Info
|Personnel: Beyonc?; Jay-Z (rap vocals); Espen Lind, Eric D. Jackson (guitar); Hanna Khoury (violin, viola); John Wittenberg, Alan Grunfeld, Ken Yerke, Michele Richards, Mario de Le¢n, Roberto Cani, Bruce Dukov, Sara Parkins, Haim Shtrum (violin); Robert Becker, Denyse Buffum, Andrew Duckles (viola); Suzie Katayama, Larry Corbett (cello); Judith Mora Arriaga (accordion); Boujemaa Razgui (nay); Allen "Al Geez" Arthur, Ronald Judge, Aaron "Goody" Goode (horns); Rudy P?rez (keyboards, programming, background vocals); Clay Perry (keyboards, programming); Tim Carmon (keyboards); Ricky Lawson (drums); Harvey Mason, Sr. (percussion); Denaun Porter (programming); Jasmin Cruz (background vocals); Keyon Harold, Tor Erik Hermanson, Alejandro Fern ndez, Mauricio Guerrero, Cori Jacobs.
|Audio Mixers: Swizz Beatz; Rich Harrison; Manny Marroquin; Jason Goldstein; Gustavo Celis; Jean-Marie Horvat; Beyonc? Knowles; Bruce Weeden.
|Recording information: Battery Studios, New York, NY; Futura Productions, Roslindale, MA; Great Divide Studios, Aspen, CO; La Marimonda, Nassau, Bahamas; Lair Studios, Los Angeles, CA; Roc The Mic Studios, New York, NY; Sony Music Studios, New York, NY; The Beach House Studios, Miami, FL; The Hit Factory, Miami, FL; The Record Plant, Los Angeles, CA.
|Editor: Clay Perry.
|Photographer: Max Vadukul.
|Arranger: Rudy P?rez.
|Beyonce had little to prove on her second solo outing, B'DAY, having already demonstrated her taste, (solo) vocal prowess, and sparkling star quality on her first post-Destiny's Child release in 2003. Nevertheless, the singer and her crack team of producers and collaborators (R&B's finest, including the Neptunes, Swizz Beats, and Rich Harrison) have come up with a collection that's at least equal to her previous triumphs, and that shows off an almost angry intensity only hinted at on earlier releases.
|The club hit "Deja Vu," with an extended rap from boyfriend/producer Jay-Z, boasts an addictive bass line that contrasts dramatically with Beyonce's emotive upper register. The haunting "Ring the Alarm" is a multilayered melodrama built around a dizzying minor-key hook that relies on Beyonce's vocal dexterity and newfound fire. Despite the appealing bravado of most of the tracks on B-DAY, the most memorable song is the beautiful lovelorn ballad "Irreplaceable," on which a wounded Beyonce protesteth too much about an errant lover's dispensability. Her nuanced and soul-deep performance suggests the tearful hurt lying at the center of all that anger.
Producer: Rich Harrison; Candice Nelson; S. Smith; Cameron Wallace; Nellee Hooper; Rudy Perez; Beyonce Knowles; Sean Garrett; Ne-Yo; The Neptunes; Swizz Beatz; StarGate; Rich Harrison
Engineer: Jamie Rosenberg; Chris Spilfogel; Aaron Renner; Roberto Almodovar; Andres Bermudez; John Weston; Geoff Rice; Robert "LB" Dorsey; Gustavo Celis; Jim Abbiss; Jim Caruana; Andy Todd; Clay Perry; Shane Woodley
Musical Guests
Compilation Appearances
Associated Artists and Works
|Beyonce Tribute Band
|Gaga, Lady
|Original Soundtrack
|Slim Thug
Technical Info
|Release Date : 04/03/2007
|Original Release Date : 2006
|Catalog ID : 9492
|Label : Sony Music Distribution (USA)
|Number of Discs : 2
|Studio/Live : Studio
|Mono/Stereo : Stereo
|SPAR Code : n/a
Professional Reviews
Rolling Stone (p.69)
- 3 stars out of 5 -- "[T]here is endless pleasure in the gliding transitions from Jay-Z's staccato rhymes to Beyonce's own honeyed flow..."
- 3 stars out of 5 -- "[T]here is endless pleasure in the gliding transitions from Jay-Z's staccato rhymes to Beyonce's own honeyed flow..."
Entertainment Weekly (p.158)
- "[T]he songs arrive in huge gusts of rhythm and emotion, with Beyonce's voice rippling over clattery beats..." -- Grade: B
- "[T]he songs arrive in huge gusts of rhythm and emotion, with Beyonce's voice rippling over clattery beats..." -- Grade: B
Q (p.149)
- 3 stars out of 5 -- "[T]he Nelly-esque 'Get me Bodied', the Neptunes-helmed 'Green Light', with its marvellously cascading chorus, and the super-taut 'Upgrade U' are turbo-charged..."
- 3 stars out of 5 -- "[T]he Nelly-esque 'Get me Bodied', the Neptunes-helmed 'Green Light', with its marvellously cascading chorus, and the super-taut 'Upgrade U' are turbo-charged..."
Q (p.118)
- Ranked #72 in Q Magazine's "100 Greatest Albums of 2006."
- Ranked #72 in Q Magazine's "100 Greatest Albums of 2006."
Vibe (p.138)
- "[A] generally exhilarating marriage of pop songcraft and state-of-the-art rhythms."
- "[A] generally exhilarating marriage of pop songcraft and state-of-the-art rhythms."
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