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Recent San Salvador Reviews
Sunset Dream: Our best winter get-away
After a six week stay in 2013, we found Sunset Dream to be very comfortable, clean and well equipped. The island, the ocean, the beaches and the people were divine so we returned in 2015 for another six week stay. We would recommend this condo to anyone interested in a tranquil vacation-long or short.
Comfy island digs!!
Thanks Sharon and Wayne for the great place to base our San Sal escape from winter. We enjoyed having the kitchen and barbeque to make our own meals and cook the yummy fish we obtained from Kim. Although we did supplement with great meals at Paradise Resto, the take out by the airport and Columbus Tavern, which we affectionately referred to as Plan B with B because it was our fav option. The house was a great space for the four of us and for entertaining our other friends who were staying at the other end of the island. Loved the beach access, the upper deck for sundowners, and the outdoor shower. Thank you so much for sharing your home with others and for checking in with us half way through the week. Also would like to give a shout out to all the friendly island folk like B and his wife, Pastor Gary, Kim, Capt. Bruce, the ladies at the grocery stores, the wintering folks that included us in their meal at the Columbus Tavern on our last night, the Research Station Manager and all the others we encountered during our week. They all helped make our stay so pleasurable. Things of note for others when they visit the island... Say yes to renting the vehicle at this property (a great way to explore all the great beaches and the spectacular cliffs); where your sandals or shoes walking around until you are clear of the vegetation (there is a grass that produces some serious sharp burrs, ouch); wear your bug dope/long pants as sunset approaches 'cause the sand flies love fresh new legs; go snorkelling with Capt. Bruce and first mate Jazzy, the dog; the resorts are generally not welcoming to folks who are not staying there, despite what the guide books say about making reservations for dinner or getting day passes to use their facilities; do take the time to stop and talk to the locals; buy Kim's sisters beautiful beach glass jewellery at the Duty Free Shop by the airport; and finally, respect this beautiful gem of an island and leave only footprints on that gorgeous sand.
Total Escape
The house was beautiful and well furnished with lots of space, a great layout and incredible views. It's also located in a perfect spot. You are pretty close to "town" but far enough away that you are not dealing with much traffic, especially on the beaches. We spent nearly every day in the water snorkeling the reefs and met the resident sea turtle, huge school of dinner-plate sized blue tangs and cuttlefish. We really missed diving due to a broken shoulder, but will get our fill on the next trip down to San Sal. We enjoyed several traditional, home-style Bahamian meals with Beverly at Paradis. Her and her mom are incredible chefs! We also took one of our first couple of days and drove all the way around the island in our rental car from Granville (which Garnel set up for us in moments upon our arrival). The drive gave us the chance to see where we wanted to spend more time throughout the week, with a focus on the beaches and reefs. Grotto beach in Columbus Landings has a pavilion with picnic tables and is pretty much deserted all the time… ask the locals how to get there and they will be happy to help. The lighthouse is a must-see. Just go on in but make sure you sign the guest book and don't wake up the lighthouse keeper. He sleeps during the day. There really are no U.S. style "convenience" stores on the island, so make sure you bring drinks/food if you go out exploring until you get used to the hours of operation. We packed a soft cooler and it worked out wonderfully. It was also handy for picnic lunchs at the beaches. Stores keep business hours but when we visited Jake Jones' store on Sunday, the locals recommended we knock on the owner's door. She was happy to open up and let us shop. The island does run based on the mailboat and fuel barge deliveries every week. If they are delayed for some reason, talk to Garnel and she'll help you find what you need. Garnel stopped by almost every day to make sure we were outfitted with everything we needed, answer any of our questions and just be a huge help. Her help and oversight helped to make our vacation perfect. All in all, the Blue House was perfect for our escape from daily life and a comfortable, relaxing vacation home. Thanks for everything, Flavia! We'll be back!


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Table Mountain hotels
Table Mountain
For hundreds of years people have looked at the majestic Table Mountain and dreamed of standing at its apex. The first to do so was a 16th century Portuguese explorer and since then millions of visitors have seen the panoramic views of Cape Town from Table Mountain's level plateau. Although many visitors still hike to the top, most now take the Table Mountain Cableway from Tafelberg Road to the top of the mountain where they are treated to unmatched views of Table Bay, Robben Island and the Atlantic Ocean. The plateau makes an imposing and beautiful backdrop for this beautiful city.
- Ascend Table Mountain from the Atlantic Ocean side on the Kasteelspoort trail, with beautiful views of the affluent Cape Town suburb, Camps Bay.
- Rock climb on the cliffs below the upper cable station for an exhilarating rush and death defying views of Cape Town.
- Explore the Wynberg Caves, a system of sandstone caves located on the Back Table, and a favourite among cavers.
There are many ways to get to Table Mountain from the city, whether you want to go to the top or just look up from the base. The Hop on Hop off bus service leaves from Cape Town's city centre and takes passengers to Table Mountain with stops at the sights along the way. Some people choose to take hired car or taxi and many taxis will wait at the base to get the return fare. There is a shuttle bus that goes directly from the Cape Town International Airport to the Civic Centre Station for those arriving by plane.
- Cape Town hotels (105 hotels)
- Durban hotels (19 hotels)
- Sandton hotels (7 hotels)
- Sea Point hotels (2 hotels)
- Melville hotels (1 hotel)
- Kempton Park hotels (3 hotels)
- Fourways hotels (3 hotels)
- Bloemfontein hotels (3 hotels)
- Pretoria hotels (12 hotels)
- Knysna hotels (4 hotels)
93 hotels near Table Mountain
1 The Bay Hotel
69 Victoria Road, Camps Bay Map
The Bay Hotel Cape Town offers quality accommodation and professional services for an enjoyable vacation. Guests can explore the city's points of interests such as Two Oceans Aquarium, Bakoven... More
2 Kensington Place
38 Kensington Cescent Map
Showcasing a scenic vista of Table Mountain, Kensington Place Hotel Cape Town is a boutique sanctuary offering style and comfort for holidaymakers wanting to enjoy the attractions of Cape Town.... More
3 The Crystal Camps Bay
35 Medburn Road Map
The Crystal Camps Bay Cape Town delivers deluxe accommodations in an idyllic location. The luxurious property offers breathtaking views of the Atlantic and the surrounding area. Guests can explore... More
4 Camps Bay Retreat
7 Chilworth Road Map
Overlooking the Atlantic Ocean along the peaks of the Twelve Apostles Mountain Range, Camps Bay Retreat Hotel Cape Town provides quality accommodation and professional services for an enjoyable... More
5 Camps Bay Resort
32 Camps Bay Drive Map
Featuring a central location and offering comfortable accommodation along with personalised services, Camps Bay Hotel Cape Town is a perfect place to reside for both corporate and leisure... More
Set amongst a wooded area, The Glen Apartments Camps Bay provides luxurious serviced apartments for travellers. This property has views of the ocean, Twelve Apostles mountain range and Lion's Head.... More
7 Twelve Apostles Hotel and Spa
Victoria Road Map
Perched on the edge of a cliff amidst the Atlantic Ocean and Twelve Apostles mountain range, The Twelve Apostles Hotel & Spa Cape Town offers a suitable and elegant base for discerning travellers... More
8 Belmond Mount Nelson Hotel
76 Orange Street Map
With a reputation for elegance, comfort and service, Belmond Mount Nelson Hotel, an oasis of calm in the heart of the city, is one of Cape Town's most elegant properties offering unparalleled... More
9 Lady Hamilton Hotel
10 Union Street Map
The Lady Hamilton Hotel Cape Town offers comfortable, family-friendly accommodations, just a short distance from Cape Town's best attractions. Guests enjoy easy access to Table Mountain, the... More
10 Villa Simona
29 Theresa Avenue Map
With its comfortable accommodations and picturesque views of the ocean and Table Mountain, Villa Simona Cape Town makes for a suitable base for travellers while in Cape Town. This cosy... More
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subset: commoncrawl


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Hollywood & Swine
Hollywood & Swine: Fake news with a wink and a wry grinComment
Today's perusal of the pop-culture news stand finds fake-but-funny missives, a death threat, an oddly placed tattoo, many other items, and the mystery music video.
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Together, our team of professional engineers has more than 65 years of experience of designing, installing, repairing, servicing and maintaining electric gates and automated gates in London, Surrey, Berkshire, Hampshire and Buckinghamshire.
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Bring style and security to your home or business – contact Windlesham Gates and find out how our electric gates and automated gates can enhance your life and your property.


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An improved instruction decoder is described which uses parallel stages which operate in a pipeline fashion. The decoder is particularly useful in a microprocessor which has variable length instructions. The first stage decodes the OP code and register and address mode specifier fields while the second stage directs the sequencing of address calculations. The first two lines of microcode are provided by the first stage as well as a look up to microcode in the microcode memory.
1. In a microprocessor having storage means for storing prefetched a plurality of instructions, decoding means for decoding the plurality of instructions from said storage means where at least two of the plurality of instructions are of different lengths and an execution unit for executing the plurality of instructions, wherein each of said plurality of instructions comprised of a plurality of bytes and has at least a first and second field, an improvement wherein said decoding means includes at least two sections,
the first of said sections coupled to receive n-bytes of said plurality of instructions and decoding a first field of one of said plurality of instructions from said n-bytes, said first field having information used by said first section to provide a first pointer to said storage means for selection of the second field of said one of said plurality of instructions from said storage means and to provide a second pointer to said storage means for selection of the first field of the instruction following said one of said plurality of instructions, said second field having information used by said second section for address generation, wherein said first section includes means for indicating to said second section the type of address calculation to be performed for said one of said instructions; and
said second section being coupled to receive m-bytes of instruction data from the storage means as indicated by said first pointer and to cause said setting up of said one of said instructions with said second field from said storage means, wherein said second section controls address calculations in response to said first section indicating the type of address calculation to be performed for said one of said instructions so that address calculations are sequenced, such that while said second section causes said setting up of said one of said instructions, said first section is decoding said first field of said instruction following said one of said plurality of instructions, and
wherein said second section includes means to synchronize results from said first section and from said second section, such that said one of said plurality of instructions is provided after decoding to said execution unit for execution while said second section sequences address calculations for the instruction following said one of said plurality of instructions, such that the first of said sections, the second of said sections and said execution unit operate synchronously.
2. The improvement defined by claim 1 wherein said first field includes the OP code and register and address mode specifier.
3. The improvement defined by claim 1 wherein said microprocessor uses microcode and includes memory for storing at least some of said microcode, said first section providing a look-up for said microcode.
4. The improvement defined by claim 3 wherein said first section for certain of said instructions provides at least one line of microcode.
5. The improvement defined by claim 1 wherein said first section providing at least a first line of microcode for some of said instruction and a look up to other microcode.
6. In a microprocessor having an instruction decoding unit, a register for storing a plurality of instructions which are coupled to said unit, and an execution unit for executing said plurality of instructions, each of said plurality of instructions having a plurality of bytes, said microprocessor operating upon instructions of different length, an improvement comprising:
said unit having a first and second stages, said first stage receiving a plurality of instruction bytes and decoding the OP code, and register and address mode specifier (first field) of one of said plurality of instructions during a first computer cycle, said first stage also signaling said second stage to the address displacement or immediate data field of said one of said plurality of instructions and determining the location of the OP code and register and address mode specifier (first field) of the instruction following said one of said plurality of instructions, wherein data in the address displacement or immediate data field of said one of said plurality of instructions are received by the second stage directly from the register, and further wherein said first stage includes means for indicating to said second stage the type of address calculation to be performed for said one of said plurality of instructions,
said second stage controlling use of said address displacement or immediate data field (second field) of said one of said plurality of instructions and responsive to said first stage indicating the type of address calculation to be performed for said one of said plurality of instructions during a second computer cycle, said second cycle following said first cycle in time, such that address calculations are sequenced during said second cycle while said first stage is decoding the OP code, and register and address mode specifier (first field) of the instruction following said one of said plurality of instructions, and
wherein said unit includes means to synchronize results from said first stage and from said second stage, such that said one of said plurality of instructions is provided after decoding to said execution unit for execution while said second stage sequences address calculations for the instruction following said one of said plurality of instructions, such that said first and second stages and said execution unit operate synchronously.
7. The improvement defined by claim 6 wherein said first stage is coupled to receive said first field under control of a first pointer and said second stage is coupled to sequence use of said second field under control of a second pointer, said first and second pointers being generated by signals from said first stage.
8. The improvement defined by claim 7 wherein said first stage initiates execution of certain of said instructions.
9. The improvement defined by claim 6 wherein said microprocessor uses microcode and includes memory for storing at least some of said microcode and said first stage providing a look-up for said microcode through a latch.
10. The improvement defined by claim 9 wherein said first stage for certain of said instructions provides two lines of microcode.
11. The improvement defined by claim 10 wherein said second stage controls bus cycle initiation.
This is a continuation of application Ser. No. 07/863,148, field Apr. 2, 1992, now abandoned, which is a continuation of application Ser. No. 07/335,186, filed Apr. 7, 1989, now abandoned.
1. Field of the Invention
The invention relates to instruction decoding apparatuses, particularly those employed in microprocessors.
2. Prior Art
Microprocessors, as well as other computers, must often employ a decoder which decodes macro level instructions. In effect, the instruction is interpreted by the decoder and the decoder determines what must be done in the processor to execute the instruction. In many cases the microprocessor includes a memory for storing micro level instructions (microcode) and the decoder provides a look-up to the microcode.
In some microprocessors, macro level instructions are of fixed length (e.g., 32 bits) while in others, instructions can be of different lengths. It is a much easier task to decode instructions of fixed length, since for instance, the decoder knows where to find certain fields in the instruction. In contrast, with variable length instructions, an immediate data field, for example, may or may not be present and its starting point in the instruction will vary.
The Intel 386 microprocessor (Intel and 386 are trademarks of Intel Corporation) is an example of a microprocessor with variable length instructions. An instruction can be one byte wide, such as some MOVE instructions. Instructions can be up to 8 bytes wide (with no prefix). Moreover, with an instruction prefix or override, the length of the instruction can be substantially longer (e.g., 15 bytes). A single decoder to decode these variable length instructions in a single pass would be relatively complex, and perhaps more importantly, would consume a relatively large substrate area.
In the Intel 386 the variable length instructions are decoded over the course of several computer cycles. First the instruction prefix is examined followed by other fields. Execution of the instructions begins after complete decoding. With many instructions, the Intel 386 requires several cycles for decoding; for example, LOAD requires four cycles for the instruction to be decoded, STORE requires two cycles; JUMP, three cycles to 4.25 cycles. On the average approximately three cycles are required before an instruction is fully decoded. As will be seen with the present invention, these times are greatly reduced because of pipelining and the manner in which the instruction is decoded. Decoding time drops to an average of approximately 1.8 cycles.
The present invention is intended to be used in a microprocessor which is an improved version of the Intel 386 microprocessor. The Intel 386 microprocessor is described in numerous printed publications. The programming for this microprocessor is described in Programming the 80386, by Crawford and Gelsinger, published by SYBEX, 1987.
An improvement is described for a microprocessor which has the storage means for storing prefetched instructions and decoding means for decoding the instructions where the instructions are of different lengths. The improvement comprises the use of a decoding means which includes two stages or sections. The first of the sections decodes a first field of one instruction simultaneously while the second of the sections is setting up execution based on a second field of the preceding instruction. Put another way, the first and second sections pipeline the instructions and operate on them in parallel.
In the currently preferred embodiment, the first section decodes the OP code, and bits representing the address mode, scaling factor, and base and index registers. The second section controls use of the address displacement and immediate data field. The first section generates pointers to the storage means which allows each of the sections to receive the correct fields of the instructions. Each section can receive any byte from the storage means.
Other aspects of the present invention will become apparent from the detailed description of the invention.
FIG. 1 is a general block diagram of the microprocessor in which the present invention is used.
FIG. 2 is a block diagram showing the instruction decoding unit of the present invention and its connection to the prefetcher and a segmentation unit.
FIG. 3 illustrates the most general format of an instruction decoded by the invented apparatus.
FIG. 4 is a more detailed diagram illustrating the format of an instruction and illustrates the variable length fields of instructions.
FIG. 5 is a diagram used to illustrate the timing and pipeline flow associated with the present invention.
FIG. 6 is a more detailed diagram illustrating the timing and instruction flow associated with the present invention.
An instruction decoding unit for a microprocessor particularly useful in conjunction with prefetched instructions is described. In the following description, numerous specific details are set forth such as specific number of bits, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing techniques, decoding techniques and circuits have not been set forth in detail in order not to obscure the present invention in unnecessary detail.
The present invention resulted during the design of the next microprocessor in the Intel 286 and 386 family of microprocessors. For this reason, an understanding of the Intel 386 microprocessor may be helpful in fully appreciating the significance of the present invention. In addition to the numerous publications available on this microprocessor, its operation is described in Programming the 80386, by Crawford and Gelsinger, published by SYBEX, 1987.
The microprocessor in which the present invention is embodied is a 32-bit microprocessor fabricated with complementary metal-oxide-semiconductor (CMOS) technology. It includes on a single substrate not only those units associated with a central processing unit (CPU), but additionally a cache memory and floating point unit. In part because of the improvements obtained by the instruction decoding unit of the present invention, single cycle instruction execution is realized for many instructions.
Referring to FIG. 1, the main units of the microprocessor are illustrated such as the bus interface unit 10. This unit provides the necessary interface between the internal buses of the microprocessor, and in particular the cache memory 11 and prefetcher 12 and the external buses responsible for fetching data from the external data memory system. External 32-bit address bus and 32-bit data bus are used. The particular interface unit 10 used in the currently preferred embodiment of the microprocessor is not critical to the present invention. This unit is described in copending application, Ser. No. 227,078, filed Aug. 1, 1988, entitled Microprocessor Bus Interface Unit, now U.S. Pat. No. 5,073,969 assigned to the assignee of the present invention. For purposes of the present invention it should be noted that prefetched instructions stored in the prefetcher 12 can be communicated to this prefetcher from the bus interface unit 10 or from a cache memory 11.
The paging unit 13 and segmentation unit 15 generally are similar to those employed in the Intel 386. The timing has been changed, however, to support one clock execution. The interconnection of a segmentation unit with the prefetcher 12 and other relationships with the instruction decoder unit 14 are described in conjunction with FIG. 2.
In general, the instruction decoding unit decodes the incoming instructions, and as will be seen, is different from the instruction decoding unit of the Intel 386 in that it provides parallel decoding and pipelining. It is implemented with two stages or sections of pipeline decoding to yield one decoded instruction per computer clock cycle for most instructions. The first section basically decodes the Op code, address mode, scaling factor and base and index register bits (collectively sometimes referred to as the register and address mode specifier), while the second stage primarily directs use of the address displacement or intermediate data fields.
The control unit 19 contains a memory which stores the microcode instructions (microcode) for the microcomputer. It shares control of the microprocessor with the instruction decoding unit since as will be described, the first line of microcode is provided by the instruction decoding unit 14. The control unit 19 is responsible for instruction boundary processing, such as interrupt/exception arbitration, and the halting of the instruction decoding unit 14 when necessary. The control unit 19 handles most of the freeze conditions, such as cache memory miss, etc.
The data path unit 17 is the main execution data path for the microprocessor. It contains the arithmetic logic unit, register file, barrel shifter, constant ROM and flags.
The microprocessor also includes a floating point unit 18. This unit contains logic to execute the floating point instructions.
The instruction decoding unit 14 of FIG. 1 is generally shown in FIG. 2 between the dotted lines 46 and 47. This unit and certain circuitry in the prefetcher 12 operate together to provide the advantages of the present invention.
The prefetcher 12 includes three major sections: register 26, multiplexer 27 and associated logic 28. The register or latch 26 receives prefetched instructions either from the cache memory or the bus interface unit. This is shown generally in FIG. 2 by bus 48. The register 26 is 32 bytes wide in the currently preferred embodiment. The instructions stored in the register 26 can be coupled either to bus 29 (K1Q) or to bus 30 (K2Q). These instructions are coupled to these buses through the multiplexer 27. Any adjacent three bytes in register 26 may be coupled to the bus 29. Any adjacent four bytes may be coupled to the bus 30.
The signals on lines 44 from the code control circuit 36 provide a pointer (K1P) to the first byte of the 24-bit field coupled to bus 29. The "(5)" following "KIP" indicates five bits rae used to designate this pointer since this is what is needed to designate a single byte of the 32 bytes stored in register 26. A second pointer (K2P) coupled to the prefetcher 12 on lines 43 points to the first byte of the 32-bit field coupled to bus 30. As will be described later, the fields coupled to buses 29 and 30 can overlap, that is, bytes initially coupled to the bus 29 during one clock cycle may in a subsequent clock cycle be coupled to bus 30.
The 5 bits coupled to the prefetcher 12 on lines 41 (K1PJ) provide a jump pointer to the code control circuit 36. This occurs after new instructions (following a JUMP command) have been loaded into the register 26. This pointer indicates to the control circuit 36 the starting byte of the new instructions. The signals on lines 42 (K1V and K2V) indicate whether the K1Q data and K2Q data is valid. The signals on lines 40 (isx8 and izx16) are control signals for controlling coupling of intermediate data fields.
The decoder 31 is an ordinary programmed logic array (PLA) circuit (which includes logic gates) programmed to do ordinary decoding. As will be seen, the OP code and register and address mode specifier are always coupled to the decoder 31 from register 26 (except when the instruction included a prefix). From this data the decoder 31 through the code controller 36 determines the length of the fields actually needed by the decoder 31 and hence, the point at which the pointer for the K2Q bus should point within the register 26. The decoder always receives 24 bits, even when an 8 bit instruction resides in register 26. The decoder 31 couples signals to the execution set up stage 34 which identifies the type of address needed to satisfy the instruction. As will be seen, the decoder 31 and execution set up stage 34 operate in parallel, however, decoder 31 operates on one instruction while the stage 34 is operating on the preceding instruction.
The latches 35 which are coupled to the output of the decoder 31 allow signals resulting from the decoding to be clocked through the latches 35 and timed with subsequent "decoding" being performed by stage 34. The latch output includes the specific ALU control signals and source/destination register enable signals. The output of the latch includes the entry point (look up) of the "first" line of microcode in the microcode memory of unit 19.
In reality, however, the entry point points to the third effective line of microcode since the decoder 31, with the latch 35 provides the first two lines of the microcode. For example, this occurs for a store instruction or when the decoder 31 sets up an address calculation during one cycle. During the following clock cycle the second line of microcode is provided by the latch 35 to initiate a bus cycle (receive from memory). For the next clock cycle the third line of code is provided by the microcode memory (control unit 19 of FIG. 1). This third line of code is selected based on an entry point provided by the latches 35 at the time when the latches 35 is providing the first line of microcode.
As currently implemented, all instructions use at least one line of microcode from the control unit 19. In some cases, this microcode simply indicates the completion of an instruction cycle. Also in many cases the first line of microcode from the decoder 31 is a "NOOP".
Execution set up stage 34 which may be looked at as the second stage of decoding, as mentioned, primarily controls address generation, or more specifically, the sequencing for the address generating. For this reason, it is implemented primarily as a state machine. The actual address calculations occur within the segmentation unit 15. The decoder 31 provides the linear address requirements to the stage 34 and from this stage 34 determines how many cycles will be needed for the instruction. In general, one cycle is needed if there is only a base and displacement, and two cycles are needed if there is a base, factor for scaled index address and displacement. A load signal and field sizing signals are coupled to segmentation unit 15 via the control circuit 36.
The code control unit 36 includes a state machine, adder and counter and associated logic. Signals are coupled from the decoder 31 to the circuit 36 to indicate the type of instruction which has been decoded. From this information, the code control unit 36 determines through the adders and counters where the pointers K1P and K2P should point. The control performed by circuit 36 will become more apparent when the pointers are discussed in conjunction with FIG. 6.
The code control circuit 36 also performs other functions in the currently preferred embodiment, for instance, violation bits which would indicate segmentation violations, or other violations are detected by the prefetcher 12 and coupled to the control unit 36. The control circuit 36 may also in some instances, determine the nature of the violation.
The pipeline control circuit 37 is also a state machine which provides overall control of the pipelining to the instruction decoding unit. This circuit recognizes from signals coupled to it from decoder 31 when an instruction includes a prefix, then determines the number of additional cycles needed to handle the particular instruction. For instance, as will be described in conjunction with FIG. 5, several cycles may be needed. The circuit 34 controls these additional cycles. The pipeline control circuit 37 on lines 49 provides a "advance signal" to the decoder 31 and execution set up stage 34, a "flush pipeline" or reset signal, and a signal to indicate when a particular stage has completed operation on an instruction.
The entire circuit of FIG. 2 is realized with ordinary circuits. Control signals not required for an understanding of the present invention are not illustrated in FIG. 2. Additionally, functions not required for an understanding of the present invention (e.g., test functions) are not shown in order to facilitate an understanding of the invention.
FIG. 3 illustrates the general format of instructions for the Intel 386, these being the instructions decoded in the currently preferred embodiment of the invented decoding apparatus. Instructions include an OP code and in some cases a separate address field 50, displacement field 51 and immediate field 52. The lengths of these fields vary as will be discussed in conjunction with FIG. 4. In some cases, an additional prefix 55 is used.
In FIG. 4, a typical instruction is illustrated. The OP code field may be either one or two bytes in length. In some cases, the entire instruction consists of only a single byte where, for example, the first five bits indicate a MOVE and the last three bits, a register designation. A typical OP code is shown as having two bytes, 57 and 58, in FIG. 4. The address mode byte 59 indicates the address mode and "register/memory"; byte 60 includes the scale factor for scaled index addressing modes (SS), the general register to be used as an index register (index) and the general register to be used as a base register. The bytes 59 and 60 are referred to as the register and address mode specifier. The field 61 is the address displacement and this field may not be present in all instructions, or it could be 1, 2 or 4 bytes long. Similarly, the immediate data field 62 may not be present in all instructions and this field may be 1, 2 or 4 bytes long. Other variations occur, for instance, segment register specifiers for certain registers may occur within the OP code fields, or bits may be used for conditional instructions to specify a condition asserted or a condition negated.
Importantly, from FIG. 4 it should be noted that the first three bytes of all instructions (except of those having a prefix) contain sufficient information to determine the instruction being requested and the total length of the instruction. In each case, these three bytes are coupled to the decoder 31. From the remaining bytes of each instruction, an address can be calculated by the segmentation unit 15 of FIG. 2. The first three bytes contain the information needed for the decoder 31 to determine the address mode and how many cycles will be needed to compute the address. For instance, it was noted that if a base, index and displacement are present, generally two cycles are required.
The general pipelining of the invented apparatus can be generally understood from FIG. 5. Across the top of the chart the cycle is shown. Each cycle corresponds to a computer clock cycle. For example, the internal clock cycles for the microprocessor may occur at a rate of 25 mHz. The lefthand column indicates the stages in the pipeline. The numbers contained in the chart represent an instruction number. For instance, during cycle 1, instruction 11 is transferred from the prefetcher 12, that is, it is coupled to the decoder 31 of FIG. 2. During the same cycle (that is, simultaneously with this transfer) the decoder 31 is decoding instruction 10, the instruction that preceded instruction 11. Similarly, during this period of time the execution set up stage 34 of FIG. 2 is controlling the sequencing of address calculations for instruction 9. At the same time execution is occurring for instruction 8 and write back is occurring for instruction 7. (Not all instructions have a write back, however, some single byte instructions do require write back.) As can be seen during cycle 2; transfer to decoder 31 occurs for instruction 12, decoder 31 is decoding instruction 11, and the execution set up unit is operating on instruction 10.
In some cases, as mentioned, a prefix (prefix 55 of FIG. 3) may be present. Assume that the decoder during cycle 3 upon decoding the first 24 bits of instruction 13 determines that a prefix is present. This information is communicated to the pipeline control circuit 37 and this circuit then determines how many cycles will be required to transfer the entire prefix, OP code, and register and address mode specifier to the decoder 31. As illustrated in FIG. 5, it is assumed that this occurs during cycles 3, 4 and 5. Decoding occurs during cycles 4, 5 and 6 and execution set up occurs during cycle 7. Execution is shown occurring for this instruction during cycle 8. During cycles 5 and 6, the execution set up stage 34 is inoperative; similarly, the execution stage is shown as inoperative during cycles 6 and 7.
Instruction 14 is shown as being transferred to decoder 31 during cycle 6, decoded by decoder 31 during cycle 7, but then requiring two cycles, 8 and 9, for address calculation. This, as mentioned, would occur where the address includes a base, index and displacement. Since two cycles are required, as indicated during cycle 8, no transfer occurs to the decoder 31, however, during cycle 9, instruction 16 is transferred to the decoder.
In FIG. 6, a portion of the register 26 of FIG. 2 illustrated. It is assumed that several instructions are stored in this register, specifically, instructions one through four. Instruction one is assumed to have a two byte OP code and register and address mode specifier. (For purpose of FIG. 6, the designation "OP" indicates both the actual OP code and register and address mode specifier fields of FIG. 4). Instruction one also has an 8 bit immediate field. Instruction two has a 16 bit OP code and a 32 bit immediate field. Instruction three has only an 8 bit OP code. Instruction four has a 24 bit OP code, and 32 bit displacement field. Initially, the K1P pointer applied to the prefetcher 12 (pointer 67) points to the first byte in the register 26. The first 24 bits in the register are therefore transferred to the decoder 31. This field is indicated to the right of cycle 1 by the number 68. Decoder 31 upon decoding this field determines that the first 16 bits are the OP code and provides the appropriate signals to initiate the execution of this code (generally to the latch 35). Through the code control circuit 36 it is determined that the 1K2P pointer 69 should point to the beginning of the immediate field in instruction one. This pointer causes the four bytes following this field to be transferred under control of the set up stage 34. The field is indicated by bracket 70 to the right of cycle 2 in FIG. 6. The code control circuit 36 also provides pointer 71 so that during cycle 2 the 24 bits following pointer 71 are transferred to the decoder 31. This field is generally indicated by the number 72. Note once again that 8 bits of the immediate field of instruction 2 are transferred to the decoder but these bits are, in effect, ignored. During the next cycle, the entire immediate field for instruction two is transferred since the pointer 73 is set at the beginning of this field. (Displacement fields are transferred to the segmentation unit and immediate fields are transferred within the cache unit.) The field is shown for cycle 3 with the number 76. The control circuit 36 next provides pointer 74 causing the 24 bits following pointer 74 to be transferred during cycle 3 to the decoder 31. Since this instruction has no intermediate field or displacement field, a 1K2P pointer for instruction three is not needed. This is generally indicated by the number 75 for cycle 4. This process continues as shown in FIG. 6 for instruction four with the control circuit 36 providing the pointers and with the appropriate fields being transferred.
In the lower part of FIG. 6 the execution of the instructions is shown. During cycle 3, instruction one is executed. During cycle 4, instruction two is executed, etc.
Thus, an improved instruction and decoding apparatus has been disclosed which provides improved performance particularly for a microprocessor that uses variable length instructions.
Patent Citations
Referenced by
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text:
Intel Capital Invests in CrowdStar, iStreamPlanet, Music Mastermind, and PerspecSys
Intel Corporation's global investment organization announces US$24.5 million in U.S. computing investments.
Intel Capital announced investments in four companies with services ranging from social games to cloud data security. CrowdStar develops social games on Facebook and mobile platforms; iStreamPlanet provides online media solutions; Music Mastermind, creator of cloud-based SoundBetter platform, is an independent entertainment and technology company; and PerspecSys is a cloud data security provider.
"With the four new investments announced today, along with recently announced deals in China and India, Intel Capital has surpassed $10 billion in total investments since its inception," the announcement says.
Intel Capital's extensive investment portfolio also includes Adaptive Computing, Black Duck Software, Collabnet, GigaSpaces, Likewise, Parallels, and VMware.
Issue 175/2015
Buy this issue as a PDF
Code.org and College Board Team Reach Out for Talented High School Coders
New partnership will bring more and better CS training to US schools
A Peek Inside TeslaCrypt Ransomware
Criminals offer online help over Tor network
Mumblehard Still Spams
Sophisticated malware is still present on Joomla and WordPress sites around the world.
Launchpad Gets Git
Future versions of Ubuntu's code service will support the popular Git version control system used with Linux and other open source projects.
AMD Posts Code for Linux GPU Driver
New release marks the arrival of AMD's unified driver strategy.
30 Percent of New Server Equipment Goes to Cloud Infrastructure
A new study by IDC charts big changes in the big hardware market.
Windows Might Go Open Source
Azure CTO says Redmond has already considered the unthinkable.
Linux Mint Will Stay with Ubuntu
Lead developer quells rumors that the Debian version is slated for center stage.
Microsoft Frees Code for .NET Build Engine
MSBuild is now just another GitHub project as Redmond continues its path to the light.
Researchers Demonstrate Hack by Heat
Malware could pass data and commands between disconnected computers without leaving a trace on the network.


text:
Author(s): Brennan, Jason
ISBN 10: 0691144818. See all ISBN's
Publisher: Princeton University Press
This is an eTextbook Learn More
Nothing is more integral to democracy than voting. Most people believe that every citizen has the civic duty or moral obligation to vote, that any sincere vote is morally acceptable, and that buying, selling, or trading votes is inherently wrong. In this provocative book, Jason Brennan challenges our fundamental assumptions about voting, revealing why it is not a duty for most citizens--in fact, he argues, many people owe it to the rest of us not to vote.Bad choices at the polls can result in unjust laws, needless wars, and calamitous economic policies. Brennan shows why voters have duties to make informed decisions in the voting booth, to base their decisions on sound evidence for what will create the best possible policies, and to promote the common good rather than their own self-interest. They must vote well--or not vote at all. Brennan explains why voting is not necessarily the best way for citizens to exercise their civic duty, and why some citizens need to stay away from the polls to protect the democratic process from their uninformed, irrational, or immoral votes.In a democracy, every citizen has the right to vote. This book reveals why sometimes it's best if they don't.
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ISBN 10: 0691144818, ISBN 13: 9780691144818, eISBN 10: 1400838738, eISBN 13: 9781400838738
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One of the highlights of my year used to be a four-day houseboat trip in the spring to Lake Shasta. However, in recent years, with the level of the water declining and the cost of fuel increasing, the trip became more work than it was worth. It is one thing to be able to tie up to the trees along the bank at night, but when those trees are 80 feet straight up the bank and the wind pulls out the stake hammered deep into the red clay of the Shasta Lake shore and the houseboat begins to drift into ...
During the past week, three separate incidents popped up that focused my attention on wild critters right in the middle of a city environment. First, I happened to be perusing the newspaper and came across an article about a rattlesnake being killed in someone's garage right in the middle of town. Rattlers in town? The State Capitol maybe, but a small town in central California? Whooda thunk it?
Memorial Day weekend is over, and I'm sure many of us who were out on the water have a story or two to tell.
After going dark for the Memorial Day weekend, the New Stockton 99 Speedway was supposed to return to action this Saturday night with one of its biggest events of the year: The SPEARS SRL Southwest Tour Series "Mid Valley Iron and Metals 150".
It's Monday, and I'm packing for my trip north where I will indulge in my other life that starts with coffee and breakfast with mom and ends with fish talk around a fire with friends.
About a week ago, I was stunned to see on the news that Budge Brown, founder of the Manteca waterslides, was missing on a plane flight from Nevada to his ranch in Tracy. Search and rescue units searched for several days before finding the wreckage of his plane in a rugged Sierra Canyon. My heart goes out to the Brown family and my prayers are with them.
What a crazy spring we've been having lately!
Dear Juniors,
Like most young adults, in my early 20s, I was pretty sure I was immortal and that I could hike anywhere with no problem. I would backpack into remote streams in search of the rare Golden Trout or the even more rare Paiute Trout.
The world didn't come to an end Saturday.
When I scribed about my excitement of anticipating covering the "final" meeting between East Union and Manteca High's baseball teams back on April 29 I knew they'd meet up again.
It's that time of year again when I get plenty of calls or emails from friends and family who want to go fishing.
Although the 100th running of the Indianapolis 500 is still more than a week away, this weekend's qualifying for "Greatest Spectacle in Racing" is causing quite a buzz.
My buddy Stephen posts things like, "The kings aren't going to catch themselves."
Oftentimes you hear old timers lamenting about how "the fishing ain't as good as it used to be," or the hunting, the gold panning, etc. It sort of reminds me of Will Rogers's observation that "everybody complains about the weather, but nobody ever does anything about it." Conservation of our outdoor resources, however, is a different story. You actually can make a difference. There are a host of organizations that do all sorts of projects improve our fishing, hunting and overall outdoor experience.
The dominant pitching and hitting of Tyres Harper led the Pirates to a 12-2 win over the Rangers in Northgate Little League junior division action.
The Northgate Little League Pirates beat the Nationals 12-2 behind the stellar complete-game pitching of Marcus Sequeira.
With the end of the school year in sight, all the talk around my household has been on where and when we're going camping.
The 4th of July is still two months ago, but there were plenty of fireworks in Saturday night's season opening race at the Stockton 99 Speedway.
It's been a year now since I sold my bass boat, and I can honestly say that there have been times when I wished I never would have parted with it.
Goalie Tatiana Orozco turned in an MVP performance, lifting the Benfica Red 05 girls soccer team to a thrilling third-place finish at the MFC Spring Invitational.
The Benfica White 05 girls soccer team of the Manteca Futbol Club made a splashy debut over the weekend.
Barry Bonds and Roger Clemens deserve their plaques in Cooperstown.
From now until mid-May, local fishing is at its best if you were to ask me.
As California enters its fourth year of drought, our streams and our ability to fish them is going to be seriously impacted. There will be almost no spring snowmelt and its accompanying high water.
After failing to finish in the top 10 in the opening two races of the 2015 Verizon IndyCar schedule, New Zealand's Scott Dixon reversed his early season woes by capturing Sunday's 41st running of the Toyota Grand Prix of Long Beach.
Tyres Harper hit the first home run out of the newly refurbished Morenzone Field on Wednesday to lead the Pirates to a 17-7 win over the Nationals in Northgate Little League junior division action.
Brett Lewis has a white-knuckle grip on the lead in the first-ever Coaches Bracket Challenge.
Stephen Curry closes games in the third quarter, not the fourth.
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Tips for asking a good question
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by DJEZB88
will my fairly old presario a900 be able to run the new civilisation v game, or any game come to that?
I cant find all the info about the running spec of my presario a900 and cant work out if its going to reach the minimum required.... any help in plain, jargon free english would be best!


text:
ViaSat files lawsuit against satellite builder
Carlsbad company claims patent infringement, breach of confidentiality
Jupiter is expected to launch this summer.
Under its original schedule, ViaSat-1 would have reached orbit about 16 months ahead of Jupiter. But during construction, a hydraulic line ruptured at Space Systems Loral, spilling fluid on ViaSat-1. Clear-up and re-testing delayed the launch by several months.
ViaSat-1's launch was delayed further when its solar arrays had to be re-tested. The additional work was needed because ViaSat-1's solar arrays used the same design as a Telstar communications satellite built by Loral. The Telstar satellite's solar arrays failed to fully deploy after a May launch.
Now ViaSat-1's market lead over Jupiter is about six months.
Analysts are still trying to figure out the impact of the lawsuit. "It's a big deal, but it's hard to know the outcome," said Timothy Quillin, an analyst with Stephens Inc.
"ViaSat has talked publicly over the past year and half about how they were suspicious," said Brian Ruttenbur, an analyst with Morgan Keegan. "So the timing of the lawsuit is interesting, like some piece of evidence came up. But they are not saying anything about that."


text:
The median home value in Chandler, AZ is $235,400.
This is
higher than
the county median home value of $191,700.
The national median home value is $170,100.
The average price of homes sold in Chandler, AZ is $235,400.
Approximately 58.84% of Chandler homes are owned,
compared to 32.12% rented, while
9.05% are vacant.
Chandler real estate listings include condos, townhomes, and single family homes for sale.
Commercial properties are also available.
If you see a property you're interested in, contact a Chandler real estate agent to arrange a tour today!
Learn more about Chandler Real Estate.
Finest estate in Arizona. Custom home at 15,198 sf, overlooks 10+ acres, running creek passing the house & guest house. 1.5 acres Lake for Jet Ski & etc, A full-size Tennis Court. Inside this home provides Theater room, English Bar(pool table,TV,etc). Workout room, full gym. Garage will hold 25 cars or RV with butlers home above garage. Security gates will open you to a wonderland--Entertainers' Dream!
Located on a full-diamond interchange with excellent frontage and signage. Close proximity to major employment hub with Intel, Motorola, OrbitalScience, Wells Fargo etc.
The subject property is contiguous to IPA's new Liv Avenida multifamily project and adjacent to the forthcoming Camden multifamily site. Significantoff-site improvements have been completed. Pulte Homes and KB Homes also located at intersection.
Design, Details and Technology of this Aviation Estate are Extraordinary. Imagine Parking 30+ Cars or Storing Multiple Planes, Helicopters, RV's, Boats & Enjoying It At Home! Massive On Site 5200+ s/f Commercial-Style Airplane Hangar with 75'x 17' Schweiss Bi-Fold Door, Tiled Floors, A/C and RV Door Stores the Toys. . Unique Living Spaces include Stunning Family Room, English Hunt Room Clad in Mahogany, Sun Drenched Morning Room, Lavish Master Suite, Exercise Studio and a Walnut Office. Billiards/Poker Room, Full Bar & Theatre for 20 are Sensational for Entertaining. Fly-In Guests will Enjoy Lavish, Full 2 Bedroom Guest House. Resort Backyard Offers Tiered Heated Pool, Spa, Outdoor Kitchen & Ramada. 5-Car Garage & Gated Motor Court. 18,000 + s/f of Luxury Under Roof. Live The Dream
Location, Location, Location!!! Great equestrian center on 12 acres right in the heart of South Chandler in a county island. This property has so much to offer. 2 Residential homes, 2 Barns, Mare Motel, Store, Office, 4 arenas(2 fully lighted, 1 partially lighted), 2 Round Pens, 7 Turnouts, a total of 112 stalls, tack sheds, wash racks lots of parking and plenty of room for more. The property is completely fenced and has it's own private well. NO HOA. Currently zoned RU-43.
Fly home to Stellar Airpark where you can purchase a stunning 7,400 SF estate home and a 5,500 SF air conditioned hangar for your planes, helicopters and RVs. The home truly has it all with an open floor plan, custom cabinetry, travertine and stone finishes and incredible entertaining spaces, 4 fireplaces. Gourmet kitchen with all the upgrades. Master suite has luxurious bath and walk-in closet. Private office. Two guest rooms in main house + guest house with two bedrooms, large bath, full kitchen and great room. Backyard has outdoor kitchen, pool, spa and firepits. 3 garage spaces. 5500 SF hangar has a/c, open family room, private office, half bath, extra laundry, RV hook up, covered storage, and direct access to the runway. Only in Stellar Airpark can you truly lock leave & travel.
Award winning lakefront custom home in gorgeous private gated community. Rare opportunity to live in Oakwood Hills on premium lot with pond and running creek. Featured on MTV Cribs, HGTV Extreme Homes & numerous publications. Voted #1 Cool Home for kids by AZ Central. Original owners. 5 en suite bedrooms + 3 more baths, theater room, playroom (only room upstairs) with 3 fireman poles to lower level bedrooms. Separate master wing. Home office w/ outside entrance, 6 fireplaces, 6 car garage, home automation, surveillance system. 4,000sq. ft+/- of covered patio, huge grass yard with sportcourt, diving pool, N/S exposure. Gourmet kitchen with 2 dishwashers, 2 microwaves, 6 burner gas range, dbl ovens, warming drawer,full size SubZero fridge /freezer, ice cream sundae station. Owner / Agent
Spectacular Location for Church, School, or Daycare. 3.11 Acre Parcel on County Island. Current configuration of 5 Buildings totaling 17,350 sf with the Main Sanctuary able to seat almost 400. Includes one acre parcel for future growth. Location less than half a mile from 101 and Warner Road. 283' of Frontage on Warner Road and approximately 477' of Frontage along the west side of 91st Place.
Fratantoni luxury estates, a prominent and active builder in Fulton ranch, is now designing plans for a 6,702 livable formal Mediterranean masterpiece! Many intimate courtyards along with large building envelope. Fratantoni interior designers is creating a full spec package for viewing all that is included with this spectacular home! This home won't last long on the market as it is reasonably priced due to low construction costs today. Buyers may modify plans and spec's at this early stage in the process. Contact listing agent for more information and to arrange a private meeting with the builder. Pictures in listing are from a previous home built and is an indication of the quality and style of home.
Real Living Property For You
7337 West Bell Road
Peoria, AZ 85382
Email Us | Visit our Real Estate Website


text:
Kiptopeke State Park
Boy Scout, 13, rescued after sailboat capsizes in Chesapeake BayComment
The Coast Guard says boaters rescued a 13-year-old Boy Scout whose sailboat capsized in the Chesapeake Bay. The boaters took the teenager back to shore at the Kiptopeke State Park.
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News-Star sues education department for information
The News-Star newspaper in Monroe has sued the Louisiana Department of Education over a denied Freedom of Information request.
The News-Star reports that it took the legal action after the Education Department first ignored and then denied the request, claiming the governor's exemption of deliberative process.
The complaint was filed Friday. It gives only one side of the legal argument.
The newspaper said it submitted the request on June 4 for Department of Education employee e-mails about the process of approving schools to participate in the state's scholarship program.
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Wind powered vehicle speeds much faster than wind; downwind!
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For those of you who have a working knowledge of trigonometry the explanation for this is 'astoundingly simple' and elegant .... you (the fan blades) are essentially dividing by the sine of 'close to zero' which by mathematical solution approaches 'infinite force'.
In common laymans terms you can do the same thing with a slippery 'pumpkin seed' between two fingers: you press your thumb and forefinger together onto the slippery pumpkin seed, and the pumpkin seed 'rockets' out between your fingers as a result. In the case of the fan blades, the pitch angle of the blades is soooooo close to zero that any input/energy from the moving wheels gets 'magnified' by literally hundreds of times as an effect onto the 'blades' (less the friction of the transmission system), and the greatly magnified speed of the blades coupled with precise aerodynamics .... moves the vehicle MUCH faster than the speed of the wind .... all because the blades pitch angle is 'dividing the energy input by the sine of the pitch angle of the blades'.
Its all due to the BRILLIANT 'application of elemental trigonometry' (aka: *pumpkin seed effect*). If you would have actually understood your high school trigonometry teacher, the valid explanation of why this vehicle is covered in the early session of a simple HS trigonometry class.
The folks who did this are profound MATHEMATICIANS. Sadly, understandable mathematics isnt taught anymore in the USA; hence, the misperceptions and doubts that are being stated about this brilliant and yet simple accomplishment simply by the application of very basic engineering and mathematical fundamentals. Elegantly profound, extremely simple !!!!!
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TIME WARP!!! Dance your cares away with Gobo, Mokey, Red, Wembley and Boober when Fraggle Rock's fourth and final season comes out on DVD November 3rd. Envisioned in the mind of Jim Henson, creator of Sesame Street and The Muppet Show, Fraggle Rock debuted on January 10, 1983, broadcast in the US, Canada, and the United Kingdom. It soon became an international phenomenon, with the "Fraggle Rock Theme" reaching number thirty-three on the British charts. Of all Henson's series Fraggle Rock was the most conceptually rich, with Gorgs, Doozers, and the Silly Creatures of Outer Space all comprising the family-friendly syndicate. The magical world of Fraggle Rock will enchant anyone who is a kid at heart. Here's Fraggle Rock's version of "We Are the World," with "Children of Tomorrow" (queue warm, fuzzy feelings):
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Hozier + Death Cab for Cutie + Rock Radio 104.5's Birthday Show (Photo Gallery)
// Notes from the Road
"Radio 104.5's birthday show featured great bands and might have been the unofficial start of summer festival season in the Northeast.READ the article


text:
This invention discloses novel device structures for fill color flat panel displays utilizing pseudomorphically cladded quantum dot nanocrystals. Different colors are obtained by changing the core size and composition of the quantum dots while maintaining a nearly defect-free lattice at the core-cladding interface. Light emission from the quantum dot core is obtained either by injection or by avalanche electroluminescence. A nanotip emitter device is also presented. These generic devices can be addressed using a variety of conventional display drivers, including active and passive matrix configuration.
1. A p-n-p configuration electroluminescent (EL) device, comprising successively layers of:
a p-type silicon layer on an insulator substrate, comprising thin doped Si p/p+ regions separated by insulating regions wherein said p+ regions are contacted to form bottom electrodes;
a thin-layer of Si which allows further epitaxial growth;
a p+-type Si layer, having addressing contact electrodes;
a thin (about 10 nm) SiO2 layer deposited and patterned with a pitch of about 0.1 microns;
a n-Si layer forming nanotips;
an n-type wide energy gap layer selected from the group of semiconductors consisting of ZnaMg1−aSe, ZnaMg1−aS, ZnaMg1−aSbS1−b, ZnaBe1−aSbS1−b, AlcGa1−cN, ZnMgBeSe, and AlInN, stacked on layer with nanotips;
a layer comprising cladded quantum dots;
a p-type wide energy gap semiconductor layer selected from the group of semiconductors consisting of: ZnaMg1−aSe, ZnaMg1−aS, ZnaMg1−aSbS1−b, ZnaBe1−aSbS1−b, AlcGa1−cN, ZnMgBeSe, and AlInN; and
a layer forming contact electrodes, wherein said set of electrodes being appropriately biased and addressed to create a two-dimensional display.
(1) Field of the Invention
This invention relates to color display devices, in particular to pseudomorphic cladded quantum dot nanophorphor thin film color display devices.
(2) Description of the Related Art
Cladded quantum dots have been extensively reported in the literature as a way of improving light emission intensity in quantum dots.[Ref.1,2] For example, cladded nanocrystals (CNCs) having CdSe core and ZnS cladding (or shell) have been used to produce high photoluminescence efficiency quantum dots.[Ref 3,4] These dots however, suffer from appreciable lattice mismatch between the core and cladding layer(s) that in turn contributes to a number of undesirable features such as:
i) Introduction of interfacial states responsible for photoluminescence (PL) and electroluminescence (EL) quenching.
ii) Limitation in growing thick cladding layers, as a result of lattice mismatch which becomes more pronounced in luminescence quenching as the cladding thickness increases. [Ref.4]
iii) The blinking behavior of these CNCs, closely related to exciton confinement in these nanoparticles, is greatly affected by defects such as that introduced by the lattice mismatch between core and cladding layer(s).[Ref.5]
Quantum dot devices require incorporation of dots in thin film forms that can be used for electronic excitation. The size distribution, composition variation and non-periodic placement of these quantum dots greatly affect the emitted wavelength, and overall device performance, especially for lasing.[Ref.6] Growth of quantum dots by self-organization has been reported to demonstrate lasing.[Ref.7] However, these devices do not yield the expected improvement in the threshold current density predicted for quantum dot lasers.
Liquid phase (solution) grown nanocrystals possess certain limitations in creating core-shell architectures with improved lattice-matching.[Ref.8] Although the lattice mismatch of ZnS cladding is significant to that of the CdSe core, these CNCs emit brighter than their uncladded counterparts.[Ref.2] Cladding with CdS produces less strained lattices. This in turns makes the CdSe/CdS core/shell CNCs to photoluminescence brighter than the CdSe/ZnS CNCs. Restricting the cladding layer thickness to only few monolayers provides one way to reduce the interfacial defects (via strained layers). Once the thickness of the cladding is increased, the photoluminescence quantum efficiency of these CNCs plummets as a result of strain-induced defects, which become dominant. Therefore, the present state of the art is based on thinly cladded CNC nanocrystals. These CNCs are further coated with surface passivation organic surfactant layers, which in turn play a major role to the photoluminescence efficiency of these nanocrystals. Nanocrystals prepared this way, when incorporated in electroluminescent (EL) devices, utilizing carrier injection invariably yields poor EL efficiencies.
A layer of trioctyl phosphine oxide (TOPO) is presently one of the best surface passivating agent used in the liquid phase growth of these CNCs.[Ref.2,4] TOPO in conjunction with TOP (trioctyl phosphine) passivates both cationic (Cd2+, Zn2+, Te2+, etc.) and anionic (Se2−, S2−, O2−, etc.) surface species respectively. FIG. 1(a) shows a typical liquid phase grown cladded nanocrystal with a core (1) and a thin cladding (2). The outer cladding layer (3 comprises of both TOPO and TOP. FIG. 1(b) shows a single pixel EL structure utilizing these nanocrystals in the form of a thin layer (7) sandwiched between a hold transporting organic layer (6) and top metal electrode layer (8). The hole-transporting layer 6 is realized on a thin transparent ITO (indium tin oxide) electrode (layer 5), supported on a substrate (4). Poly (p-phenylenevinylene) along with other hole injecting organics has been used with limited success (Rdf.8).
Once the organic passivation agent(s) are partially removed or somehow degrade during device operation, the emission characteristics and brightness of these CNCs are significantly impaired. In addition, the natural inability of the organic phase towards dielectric breakdown poses a significant limitation for these CNCs to find application in field-assisted electroluminescent devices.
An alternate technology is the use of doped nanocrystals, DNCs, [Ref.9] where a dopant is introduced in the quantum dot, such as Mn in ZnS. These DNCs are incorporated in the form of thin films and used for electroluminescence or cathodoluminescence device applications.
Use of cladding layer material that has a higher band gap than the core with similar lattice constant results in a pseudomorphic cladded quantum dot. In this arrangement, the core-cladding lattice mismatch is accommodated as tensile or compressive strain. Having a small mismatch permits the growth of thicker cladding layers as has been shown in pseudomorphic strain layer quantum-wells. This improves the confinement of holes, electrons and excitons inside the core. In addition, these CNCs are less affected by the environment of the outer surface of the cladding layer, thus putting less stringent requirements on additional surface modifying layers. In particular, the known susceptibility of chalcogenides and other semiconducting materials to form oxides in the presence of atmospheric moisture and oxygen justifies the growth of compatible surface passivation layer(s) to further improve their environmental stability. Alternatively, one can use a compatible higher energy gap semiconducting layer before applying the outer passivation layer. Depending on the device structure, the outer layers could be semiconducting or conducting.
Quantum dots have been used to realize nanophosphor for a variety of display, lasers and luminescent-based diagnostic applications. The luminescent properties of these dots however, are strongly influenced by surface states. Cladding layers have been used to reduce these surface states, although the lattice mismatch in the materials for core and cladding creates undesirable quenching defects. In addition, the cladding layer prevents the injection of carriers, with the holes especially, hindered in reaching the core of these nanophosphors.
An object of this invention is to fabricate a high resolution color display device. Another object of this invention is to fabricate a display device using pseudomorphic cladded quantum dot nanophosphor thin film with high brightness.
This invention describes novel device structures for full color flat panel displays utilizing pseudomorphically cladded quantum dot nanocrystals. In this approach, different colors are obtained by changing the core size and/or composition of the quantum dots while maintaining a nearly defect-free lattice at the core-cladding interface. Light emission from the quantum dot core is obtained either by injection or by avalanche electroluminescence (EL).
Injection EL involves a novel approach injecting minority carriers in the core from the wide energy gap n and p-layers, through the cladding layer. In the case of inorganic-organic hybrid device structures, hole blocking layer surrounding the CNCs creates a favorable scenario for efficient injection and recombination taking place in the core of the cladded quantum dots. Avalanche EL device structures are proposed using single crystal, polycrystalline and amorphous starting surfaces. Device structures involving epitaxial layers and non-epitaxial growth are used. The ability to grow cladded nanocrystals (CNCs), pseudomorphically on single crystal substrates is also described. These, in conjunction with dielectric layers grown above and below the quantum dot layer(s), are expected to result in low voltage and high brightness CNC avalanche EL devices.
Variations of the disclosed structures are presented for various material systems. These generic EL devices can be addressed using a variety of conventional display drivers, including active and passive matrix configurations. In the case of avalanche/field emission EL, formation and use of nanotip structure is also presented.
FIG. 1(a) shows the basic structure of conventional cladded nanocrystals, modified at their outer surface with TOPO or TOP.
FIG. 1(b) illustrates a conventional thin-film based EL device.
FIG. 2(a) shows an EL device comprising of pseudomorphic cladded quantum dots sandwiched between thin films of wider energy gap semiconductors.
FIG. 2(b) shows a representative pseudomorphic CNC.
FIG. 3 shows an EL device having multiple layers comprising of pseudomorphic cladded quantum dots sandwiched between epitaxally grown thin films of wider energy gap semiconductors.
FIG. 4 shows a typical white light EL device vertically integrating three primary colors via layers comprising of different pseudomorphic cladded quantum dots whose core size and composition produces the desired color response.
FIG. 5 shows a red, green and blue (RGB) EL display matrix having layers comprising of deferent pseudomorphic cladded quantum dots whose core size and composition produces the desired color response.
FIG. 6 shows an avalanche, non epitaxial device where quantum dots are sandwiched on dielectric layers such as SiON, Ta2O5, BaxSr1−xTiO3, PLZT, ZnxMg1−xS, ZnxBe1−xS, etc. or their combination. The dielectric layers are grown on ITO, polycrystalline or amorphous silicon with appropriate conductivity, metals, etc.
FIG. 7 shows an injection based EL device incorporating nanophosphors utilizing a variety of amorphous or polycrystalline semiconductors or insulators layers.
FIG. 8(a) shows an injection based hybrid (organic/inorganic) EL device. The quantum dots are incorporated in between the n-type (inorganic) and hole-transporting (organic) semiconductor layers.
FIG. 8(b) shows a structure similar to FIG. 8(a) where the organic hole-transporting layer is doped with an oxidative agent.
FIG. 8(c) shows an injection based hybrid (organic/inorganic) EL device. The quantum dots are incorporated within the hole-transporting organic semiconductor layer.
FIG. 8(d) shows a structure similar to FIG. 8(c) where the organic hole-transporting layer is doped with an oxidative agent.
FIG. 9 shows a representative pseudomorphic CNC with an optional outer environmental passivation layer.
FIG. 10(a) shows an all-organic injection based EL device. The CNCs are incorporated within the p-type organic semiconductor layer.
FIG. 10(b) shows a structure similar to FIG. 10(a) where the organic p-transport medium is doped with an oxidative agent.
FIG. 10(c) CNCs are sandwiched between the hole- and electron-transporting organic semiconductor layer.
FIG. 10(d) shows a structure similar to FIG. 10(c) where the hole-transporting layer is doped with an oxidative agent.
FIG. 11 (a) shows an EL structure where a viscous, mellifluous composite (consisting of CNCs, p-type organic semiconductors, oxidative agents and viscosity modifying agents having low vapor pressure), is sandwiched between two electrodes.
FIG. 11(b) shows a display based on EL structure of FIG. 11(a) employing a passive-matrix-addressing scheme. Here, rows and columns of the bottom and top electrodes respectively are separated by an elastomeric spacer that form vesicles where the viscous composite can be inject printed with and RGB pattern.
FIG. 12 shows an EL structure employing nanotip Si emitters (realized in the p-Si base layer using the selective area epitaxy through a thin (˜10 nm) SiO2 patterned mask having around 0.1 micron spacing between oxide regions) providing minority carriers into the nanophosphor layer. The Si base layer and the nanophosphor layer is reversed biased, channeling electrons and hole in the cores of quantum dots, and subsequently emitting the desired radiation.
FIG. 2 shows an EL device comprising of pseudomorphic cladded quantum dots sandwiched between epitaxially grown thin films of wider energy gap semiconductors. A silicon/silicon oxide composite layer is realized on sapphire substrate 10, consisting of thin doped Si p/p+ regions 11, separated by SiO2 insulating regions 12. The top surface of regions 11 and 12 contain a thin-layer of Si (13) which allows to grow a wider gap semiconductors layer 14, cladded quantum dots 15, and covered with another wider gap semiconductors layer 16. Top contact electrodes 17, running perpendicular to the doped Si regions 11, are formed by metalization. In the case that layer 14 is of p-type semiconductor, layer 15 can be n-type to form to p/n junction that could operate in injection or avalanche mode depending on forward or reverse bias. In the case where layers 11, 13 and 14 are doped n-type, and if layer 16 is thin and lightly n-doped, the metalization layer 17 can form a Schottky barrier. This device can also work in injection or avalanche mode depending on forward or reverse bias. In the case of avalanche operation, the layer forming a reverse barrier junction should be thick enough to produce impact ionization that leads to avalanche multiplication of carriers.
FIG. 3 shows a variation of FIG. 2 device having layer 18 consisting of multiple layers of pseudomorphic cladded quantum dots (19), sandwiched between epitaxially grown thin film layers of wider energy gap semiconductors (20). This arrangement forms multiple quantum dot (MQD) structures. Relatively thick MQD structures are suitable for avalanche type EL devices where as few layers of MQD structures are suitable for injection EL.
FIG. 4 shows a variation of FIG. 2 device having the multiple layers comprising of CNCs stacked based on their emission color. For example, depending on the core size and composition, pseudomorphic cladded dots ZnCdSe/ZnSe or ZnCdSe/ZnSSe, emitting red 23, green 22, and blue 21 (RGB) are going to be deposited successively on top of the wider gap semiconductor layer 14, 24 and 25 respectively. If layer 24 and 25 do not include tunnel junctions, this structure would operate in avalanche mode. Insertion of p+/n+ tunnel junctions is required [Ref.10] to run it as an injection device. This structure is geared to produce stable white EL lamps, ensuring that no energy transfer takes place between different color CNCs. These white lamps are expected to retain their chromaticity characteristics during their operating lifecycle.
Ensuring that the spacing between the quantum dots is filled with wider energy gap semiconductor, channeling carriers through the embedded CNCs is expected to be particularly important to lower the driving voltage. These structures are expected to operate at significantly reduced voltages, (in the range from 5-20 V). The enhanced radiative transition rates in pseudomorphic CNCs make them suitable for fast frame rate applications. [Ref.6]
FIG. 5 shows a variation of FIG. 2 device structure, where CNCs are stacked based on their emission color to form full color pixelated devices. For example, depending on the core size and composition emitting red 23, green 22, and blue 21 (RGB) are going to be deposited successively to form rows on top of layer 14. This placement of CNC can be accomplished using a variety of deposition techniques. One of these techniques could be the electrostatic deposition of CNCs on the lower bottom electrodes (layer 12) that are appropriately biased.
FIG. 6 shows the cross-sectional schematic of an avalanche, non-epitaxial EL device structure showing only one pixel. ITO layer 27 is grown on substrate 26 forming row of electrodes (only one pixel is shown), followed by a dielectric layer 28. The quantum dots (layer 15) are deposited on the said dielectric layer 28. This is followed by the deposition of another dielectric layer 28, and a metal layer 29 forming columns of electrodes (only one electrode is shown) complete a passively addressed display matrix. The dielectric layers 28 could be of SiON, Ta2O5, BaxSr1−xTiO3, PLZT, ZnxMg1−xS, ZnxBe1−xS, etc. or their combination. The electrode layer 27 could be of ITO, or polycrystalline or amorphous silicon with appropriate conductivity. For actively address displays, the polycrystalline or amorphous Si could host thin film transistors. The top electrode could be comprised of metal of ITO electrodes.
FIG. 7 shows the cross-sectional schematic of an injection based EL device incorporating nanophosphors utilizing a variety of silicon-layer 31-on-insulator 30 substrates. Layer 31 is used to form pixelated electrodes similar to that of FIG. 2. A thin layer of p-type semiconductor 32 with gap wider than that of CNCs layer 33 is grown to inject holes into the cores of CNCs. A thin hole-blocking layer 34 with a gap wider than CNC semiconductor core is grown on top of these CNCs, followed by a metal electrode 35. Hole blocking can be achieved by thin layers of semiconductors or insulators such as Ta2O5, ZnxMg1−xS, ZnxBe1−xS, etc. or their combination.
FIG. 8 shows a hybrid (organic/inorganic) injection EL device. The p-type wider energy semiconductor layer 44 comprises of a hole-transporting (undoped) organic layer where its ionization potential is high enough to inject holes to CNCs (e.g. carbazole based derivatives, such as polyvinylcarbazole (PVK) and 4,4″-N,N′-dicarbazole-biphenyl (CBP) which can be spun-coated or vacuum deposited, respectively).
In FIG. 8(a), the CNCs (layer 43) are spun coated on top of n-type wide-energy inorganic semiconductor layer 42 (e.g. ZnxMg1−xS, ZnxBe1−xS) which is grown epitaxially on a thin n+ silicon layer 41 supported on a compatible substrate 40 (e.g. Si, sapphire). A thin layer of the hole-transporting organic semiconductor 44 is then grown on the CNC layer 43, followed by a conductive organic layer 45, which facilitates formation of ohmic contact with the top electrode 46.
In FIG. 8(b), layer 47 comprises of the hole-transporting organic semiconductor which is lightly doped with an oxidative agent such as (FeIIIcitrate or FeIIIoxalate). The oxidation agent is selected such as not to dissociate away from its counter ion. For example, the FeIIIcitrate is stabilized by multiple chelation. Building controllable thickness organic shells around the oxidation agent avoids permanent adsorption of oxidizing agent at the surface of CNCs. If this adsorption takes place (e.g. using FeCl3) then the photoluminescence of CNCs is quenched. Therefor a thin shield is constructed around the oxidizing agent or CNC utilizing appropriate counter ions, chelating agents, surfactants and dentrimers. When such a carefully-designed oxidizing agent is introduced in the vicinity of CNCs, it controllably extracts one electron from the CNC, leaving a hole which can recombine with an injected electron to produce a photon.
In FIG. 8(c), the hole-transporting organic acts as host to forms the matrix for CNCs (layer 48). Such composites can be easily spin coated.
FIG. 8(d) shows a structure similar to FIG. 8(c) where the composite of CNCs and the organic hole-transporting layer is doped with oxidative agent(s) discussed above, forming layer 49.
The profound permeability of organic compounds to moisture and oxygen requires the grown of a protective outer passivation layer on the CNCs. This is shown in FIG. 9, where the CNC, comprising of the core (50) and the pseudomorphic cladding (51), is coated with a passivation layer 52, (e.g. ZnO, SiOx, SiON, Ta2O5, etc.).
FIG. 10(a) shows an all-organic CNC-based injection EL device. A substrate (60) supports an ITO layer 61. With the help of an organic conductive layer 62, holes are easily introduced to a composite layer 63, comprised of CNCs and an organic hole-transporting agent. Subsequently, an electron transporting organic layer 64 is deposited. This is followed deposition of a thin (8-20 Å) tunneling layer 65, which is contacted with a top electrode (66). The organic conductive layer 62 may be realized by polyaniline or polythiophene based conductive polymers. The electron transporting layer 64 may be realized by bathocuproin, BCP, (a material with a 3.5 eV band gap, capable of injecting electrons in CNCs and blocking hole transport to the cathode). The electron-transporting layer could be combination of two layers having two different energy gaps such as CBP and aluminum (III) quinoline (Alq3). The thin tunneling layer 65, may be composed from materials such as CsF, LiF, Al2O3, etc. The top electrode 66, may be realized by metals (e.g. Al) or a thin-transparent metal layer covered with ITO.
FIG. 10(b) shows a structure similar to FIG. 10(a). Here, the layer 67, consisting of CNC and organic hole-transporting agent is doped with oxidative agent(s) described above.
FIG. 10(c) shows a structure similar to FIG. 10(a) where the CNC layer 68, is sandwiched between the hole-transporting layer 69 and electron transporting layer 64.
FIG. 10(d) shows a structure similar to FIG. 10(c), where the hole-transporting layer 70, is doped with an oxidative agent.
FIG. 11(a) shows an EL structure where a viscous, mellifluous composite layer 74, is sandwiched between two electrodes (72) supported on their respective substrate (71). The thickness of layer 74 is determined by the spacers (73). The viscous composite may consists of CNCs, hole-transporting organic semiconductors, oxidative agents, soluble salts (e.g. lithium triflate, lithium acetate, etc.) and low vapor pressure viscosity-modifying agents (e.g. dioctyl phthalate, low molecular weight polyethylene oxide, etc.). The spacers (73) may comprise of monodispersed glass microspheres.
FIG. 11(b) shows an EL structure similar to that on FIG. 11(a). Here the 3-dimensional view of a display employing passively-matrix-address scheme is illustrated. Rows and columns of the bottom and top electrodes respectively are separated by an elastomeric spacer 75 (e.g. polyurethane, polysiloxane elastomer).
With a help of a microlithographically defined 3-D mold, monomeric or oligomeric precursors are squeezed and polymerized in place between the bottom substrate and the mold. Subsequently, the mold is removed and the viscous composite (74) comprising of CNCs, hole-transporting organic semiconductors, oxidative agents, soluble salts and low vapor pressure viscosity-modifying agents is either screen-printed or ink jet printed to fill the cavities within the elastomeric spacer (75). Red, green and blue RGB CNCs are used to define the three colors in the viscous composite (74R, 74G, 74B) to realize full color pixelated displays. The final step seals the structure by placing the cover (top substrate (77) and contacts (76)). Such structures are expected to be mass-produced adapting techniques known in the prior art.
FIG. 12 shows an EL structure employing nanotip Si emitters (realized in the base region using the selective area epitaxy through thin SiO2 masks) providing minority carriers into the nanophosphor layer (85). The p-Si base layer (81 and 83) and nanophosphor layer along with n-type wide energy gap outer layer (86) forming the p-n junction are reversed biased. Collected electrons [which are injected from the n-layer (81) underneath the pSi layer 81] are introduced in the cores of nanocrystals where they recombine with holes (supplied by the top contact electrode (87). A typical fabrication methodology to realize this structure is described below.
A silicon/silicon oxide composite layer is realized on sapphire substrate 10, consisting of thin doped Si n/n+ regions 11, separated by SiO2 insulating regions 12 (the spacing between the oxide regions forms a pixel which may be between 10-50 micron in extension). The top surface of regions 11 and 12 contain a thin-layer of Si (13), which allows the growth of a p-Si layer 81. A thin (about 10 nm) patterned SiO2 layer 82 is deposited, which in turn is used to deposit p-Si layer 83 consisting of nanotips (e.g. using selective area epitaxy through 0.1 micron wide pattern [Ref. 11]). This is followed by the deposition of a wide energy gap layer 84 (e.g. ZnMgS etc), followed by deposition of a layer comprising of cladded quantum dots 85, and covered with another wider gap semiconductors layer 86. Top contact electrodes 87, running perpendicular to the doped Si regions 11 (contact shown as 89), are formed by metalization. The p-type semiconductor layer 81 is ohmically contacted via electrodes 88. Here, one can forward bias the n-p junction formed by layers 13 and 81, and reverse bias the junction formed by the p-Si nanotips 82 and n-type layer 84. The collected electrons from the nanotip layer are accelerated in layers 84, 85, and 86. They form electron-hole pairs, which in turn migrate to the cores of the cladded pseudomorphic quantum dots. Thus contacts 88 and 87 are reversed biased and contact 89 and 88 are forward biased.
This device structure permits active addressing via the biasing of contacts 89 and 88, or the emitter and base junction, viewing the device as an n-p-n structure. In a modified version, one can envision eliminating the emitter-base junction (formed between layers 13 and 81), and having nanoemitters directly providing carriers into phosphor via a reverse biased junction. The nanoemitters could be in the form of ridges or pyramids. There pointed tips that create higher values of electric field for a given reverse bias, result in the acceleration of collected carriers in the wider gap layer and the nanophosphor layer. This would result in introduction of carriers at much lower voltages than is anticipated in conventional field emission devices (FEDs).
While the preferred embodiments of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made in the embodiments without departing from the spirit of the present invention. Such modifications including lattice-matched or pseudomorphic cladded quantum dots, quantum dots with coupled cores are all within the scope of this invention. We have described p-n structures sandwiching quantum dot layer(s) for injection or avalanche type EL displays, Schottky barrier contacts can also be used. Wider energy gap semiconductor layers, dielectric layers, as well as quantum dots -can be selected and patterned (in order to facilitate various addressing schemes, such as passive and active matrix) from a wide ranging material list. In addition, electrodes can be isolated via oxide regions (as shown in figures), reverse biased junctions, and other standard methods.
Although we have described EL devices, the structure is adaptable to cathodoluminiscence devices which are addressed by electron beam replacing the regular phosphor by quantum dot based nanophosphor. Various organic structures showing hole transport and electron transport layers can also be realized with variations in materials selected. We have not shown active matrix addressing. In Si on Insulator substrates, one can implement transistors in the top Si layer. Other logic devices can be integrated if needed.
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