text:
I've been a member of the theme forest community for 4 years and I have tried time after time to get my theme accepted and still no luck. I will admit when first starting my websites were not that good but hey others were not in their files was accepted. Reviewers files were accepted though they were not up to par.
This year I have worked on a music theme and have fixed all bugs, gotten feedback on forrst, posted pics on dribbble and still rejected. What is the problem? Why is this file a soft reject but when I fix it and resubmit it It gets denied. If you have 3minutes can you tell me what I can improve on my file.
Imho. you should work more on typography and design.
Can you go into details? I have included Google fonts for more typography options and line height, font spacing, etc seemed to be corrected since getting feedback on forrst.
It doesn't matter you have a lot of fonts. You should have everything more spaced. Make the theme so it can "breathe". Eg. look at the social icons, they are too crowded. The same for the elements in the page, buttons, text, etc…
Thanks I will work on it now to make it less cluttered and less of a box like feel.
Seriously change the typography, that font is ugly! in here, Oswald is meant (In my opinion) to be used creatively. Try Open Sans, PT Sans, Raleway (Find a beautiful font, seriously, typography is everything.)
In the end, not sure if this is worth the effort, but overall try to improve spacing and don't use something unless it's really really good looking! (Even if it doesn't serve any purpose, if that makes the users say "Wow", that's amazing..but don't cut from performance.. Like don't load 50 fonts in the header just because it looks good, use these 50 fonts and make an image.)
Hope that helps.
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About the bill
- Full Title
To require operators of Internet websites that provide access to international travel services and market overseas vacation destinations to provide on such websites information to consumers regarding the potential health and safety risks associated with traveling to such vacation destinations, and for other purposes.
Legislative action may be ocurring on one of these bills in lieu of or in parallel to action on this bill.
Referred to Committee
Last Action: Oct 20, 2011
Referred to Committee
Last Action: Mar 16, 2011
- What is a bill?
The "H.R." in "H.R. 3241" means this is a House of Representatives bill in the United States Congress. A bill must be passed by both the House and Senate in identical form and then be signed by the President to become law.
The bill's title was written by its sponsor.
- Cosponsors
1 cosponsors (1D) (show)(joined Oct 24, 2011)
- Committee Assignments
The committee chair determines whether a bill will move past the committee stage.
- Votes
There have been no votes related to this bill.
- Subject Areas
- Find Similar Bills
Search for similar bills.
Links & tools
- Primary Source
THOMAS.gov (The Library of Congress)
GovTrack gets most information from THOMAS, which is updated generally one day after events occur. Activity since the last update may not be reflected here. Data comes via the congress project.
Click a format for a citation suggestion:
Civic Impulse. (2015). H.R. 3241 — 112th Congress: International Travelers Bill of Rights Act of 2011. Retrieved from https://www.govtrack.us/congress/bills/112/hr3241
"H.R. 3241 — 112th Congress: International Travelers Bill of Rights Act of 2011." www.GovTrack.us. 2011. May 24, 2015 <https://www.govtrack.us/congress/bills/112/hr3241>
{{cite web
|title=H.R. 3241 (112th)
|accessdate=May 24, 2015
|author=112th Congress (2011)
|date=October 24, 2011
|quote=International Travelers Bill of Rights Act of 2011

subset: commoncrawl


text:
Glasgow Int'l airport hotels
Top 5 Glasgow International Airport Activities
Hotels near Glasgow International Airport allow visitors to take a short trip from the arrivals area to their accommodations. This can be especially convenient if you're in Glasgow for a short trip, or if you are not at all familiar with the city. Thanks to the proximity of these hotels, travellers don't have to waste any time getting from their plane to their bed once they have reached Scotland.
Glasgow International Airport has some excellent facilities. Here are some of the best activities available:
- Sit back and relax with a drink at the Sky Lounge
- Watch what happens on the international runways from the J&R Tennent Pier Bar
- Treat yourself to a massage at the Relaxation Station
- Buy souvenirs to take home with you from the World Duty Free Shop
- Check out current fashions at A Bientot
There are several restaurants near the international airport in Glasgow that offer a variety of fare at various price levels. Here's a short list:
- Caffe Nero
- The Drum & Monkey
- Frankie & Benny's
- Greggs
- Harry Ramsden's
- O'Briens
The convenient hotels near Glasgow International Airport allow you to use all your time in a positive way. No time is wasted upon arrival in travelling to your accommodations. There are plenty of travel options available from the airport into the city. These hotels are ideal for short stay breaks and for busy business travellers.
- London hotels (789 hotels)
- Edinburgh hotels (138 hotels)
- Manchester hotels (96 hotels)
- Birmingham hotels (80 hotels)
- Glasgow hotels (69 hotels)
- West Drayton hotels (1 hotel)
- Brighton hotels (30 hotels)
- Liverpool hotels (55 hotels)
- Plymouth hotels (15 hotels)
- Leeds hotels (38 hotels)
72 hotels near Glasgow Int'l airport
1 Ramada Glasgow Airport
Marchburn Drive Map
The Ramada Hotel Glasgow Airport gives you the opportunity to enjoy a night's sleep and a mouth-watering meal, without the worry of missing your flight. GeneralThe hotel provides 4 conference... More
2 Holiday Inn Express GLASGOW AIRPORT
St. Andrews Drive,Glasgow Airport Map
TheHoliday Inn Express Glasgow Airport could not be more convenient for air passengers being just a two minute walk - via a covered walkway - from Glasgow International Airport. Nearby attractions... More
3 Holiday Inn GLASGOW AIRPORT
Abbotsinch Paisley Map
The Holiday Inn Glasgow Airport is situated just steps from the main terminal ideal for a stopover and also close to Glasgow city's main attractions. Braehead Shopping Centre is only four... More
4 Campanile Glasgow Airport
2 Row Avenue, Braehead Map
Featuring comfortable accommodations within convenient distance from the airport, Campanile Glasgow Airport Hotel makes for a suitable starting point for travellers exploring this part of the... More
5 BEST WESTERN Glasgow North
1710 Great Western Road Map
The BEST WESTERN Glasgow North Hotel is a 'Retro' Retreat, set up on a hill north of the Glasgow town center and on the main tourist route to the Highlands. Scottish hospitality and Best Western... More
6 Glasgow Pond Hotel
Great Western Road Map
Situated in Glasgow's lively West End, the Glasgow Pond Hotel has the city's amenities on its doorstep. Guests can stroll to attractions such as beautiful Glasgow Botanic Gardens, wander around... More
7 Fraser Suites Glasgow
1-19 Albion Street Map
Fraser Suites Glasgow invites discerning tourists to self-catering accommodations housed in a historic building with traditional Scottish setting located in central Glasgow. This modern property... More
8 Carlton George Hotel Glasgow
44 West George Street Map
The Carlton George Hotel Glasgow is located in the heart of the city - and is an ideal base for sightseeing, as well as being close to all business districts. The hotel is an easy walk from... More
9 Jurys Inn Glasgow
80 jamaica street Map
The Jurys Inn Glasgow is the perfect base for a city break or business trip, being located right in the centre of Glasgow, close to transport links and main shopping and financial districts. The... More
10 Alexander Thomson Hotel
320 Argyle Street Map
The Alexander Thomson Hotel Glasgow, named after the famous Scottish architect, is a traditional Victorian property, located in Glasgow city centre. Guests can walk to attractions including the... More
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The Walrus Hostel
Real Reviews
Real reviews from fellow travellers
These are trusted reviews from guests who have actually stayed here. We hope you find them helpful.
Note: we only give a property a rating once it has received a minimum of 3 reviews.
- " we loved it, friendly people an profesional, we already recomended it, congratulations "
- 15 May 2015 Anonymous Mexico
- " Great hostel, staff were professional and you can tell they wanted you to enjoy yourself.wasfun having them as your bartenders in the pub as well. Only complaint was the showers were pretty bad. "
- 29 Apr 2015 Anonymous Canada
- " Something should be done to keep out the noise from the trains. "
- 15 Apr 2015 Anonymous England
- " The walrus staff is amazing. They help me on everithing i need! "
- 09 Apr 2015 Anonymous Argentina
- " The staff was superb! They made us feel like home from the minute we stepped in until the very end of our stay. The toilets weren't in such a good condition. Sometimes we had to go through several toilets to find one that wasn't blocked. All in all a great experience, anyways! "
- 19 Mar 2015 Hanna Finland
- " Great place! "
- 05 Feb 2015 Nina Switzerland
- " the localization is perfect! 5 min to Big Ben and Westmister Abbey and 10 min to Trafalgar square,it's hard to find any other hostel or hotel In this region. The Rooms are very small,and there is a train station behind ,so the noise can be a problem "
- 08 Jan 2015 Anonymous Brazil
- " Great location. I was able to walk almost everywhere which saved me a good amount of money. I wish there was a lounge of some sort to hang out and meet other people from the hostel. The only places you could really hang out is in the big rooms and people were often trying to sleep at that time. The kitchen is super tiny and gets pretty crazy when more than three people are in there. "
- 26 Dec 2014 Anonymous USA
- " a genuine British Pub and a hostel in the same space. the staff was very kind, given all the details we ask and providing additional information. the room ( 4 bed dorm room) was too small and the toilet and shower are located out side the dormitory. the good part is that the hostel is located 5 minutes walking from Waterloo Station, and you have the pub just down the stairs. "
- 08 Dec 2014 Eryel Italy
- " Just an horrible location, thanks to trainstation near, water bathrooms are very often cold. Staff is very cool, thanks to them. "
- 17 Nov 2014 Brice France


text:
IU Health Ball Memorial Listing
Orthopedics earns Joint Commission accolades09/06/2011 | IU Health Ball Memorial Hospital
MUNCIE--Indiana University Health Ball Memorial Hospital is one of three hospitals in the state to earn The Joint Commission's Gold Seal of Approval™ for both their Total Knee Replacement Program and Total Hip Replacement Program. The certification recognizes Indiana University Health Ball Memorial Hospital's dedication to continuous adherence with The Joint Commission's state-of-the-art… Read More
Cancer Center oncologists to remain in Muncie08/18/2011 | IU Health Ball Memorial Hospital
MUNCIE--Officials announced, that Medical Consultants, PC, the Medical Consultants oncologists practicing at the Indiana University Health Ball Memorial Cancer Center and the Hospital have reached an agreement to allow the oncologists to continue practicing in Muncie. The terms call for the oncologists to become IU Health Ball Memorial Employees. "We are pleased to announce that these highly-skilled… Read More
Not too late to sign up for Safe Sitter courses08/01/2011 | IU Health Ball Memorial Hospital
MUNCIE--Indiana University Health Ball Memorial Hospital will host two more Safe Sitter classes during summer vacation for children ages 11-13. Two-day sessions are August 3-4 and August 8-9. Classes are held from 8:30 am-3:30 pm on respective dates in the Outpatient Medical Pavilion rooms 6, 7 and 8. This class will familiarize participants with responsibilities of caring for young children, including… Read More
Hospital employees helping kick off Kindergarten Countdown in Muncie and Hartford City07/28/2011 | IU Health Ball Memorial Hospital
MUNCIE – Children in Delaware County and Blackford County this summer are getting a jump start on kindergarten thanks to a partnership aimed at helping at-risk children transition successfully into school. Indiana University Health Ball Memorial along with United Way of Delaware County as well as IU Health Blackford Hospital and the United Way of Blackford County have teamed up to offer "Kindergarten… Read More
Free Joint Pain Seminar July 2107/19/2011 | IU Health Ball Memorial Hospital
MUNCIE – Indiana University Health Ball Memorial Hospital and Central Indiana Orthopedics are hosting a free Joint Pain Seminar, 6 pm, Thursday July 21. Marshall Trusler, MD, orthopedic surgeon with Central Indiana Orthopedics and a member of the IU Health Ball Memorial medical staff, will be discussing shoulder pain and strategies to decrease and eliminate joint pain. The session will last one… Read More
Expert physicians backed by national rankings07/19/2011 | IU Health, IU Health Arnett Hospital, IU Health Ball Memorial Hospital, IU Health Blackford Hospital, IU Health Bloomington Hospital, IU Health La Porte Hospital, IU Health Methodist Hospital, IU Health North Hospital, IU Health Starke Hospital, IU Health Tipton Hospital, IU Health University Hospital, IU Health West Hospital, IU Health White Memorial Hospital, Riley Hospital for Children at IU Health
For the 14th consecutive year, Indiana University Health-Indiana University School of Medicine specialty programs have ranked among the nation's top programs in U.S.News Media & World Report's 2011-2012 Best Hospital rankings, available online at www.usnews.com/besthospitals… Read More
IU Health Ball Memorial meets LGBT criteria07/08/2011 | IU Health Ball Memorial Hospital
MUNCIE— As an example of Indiana University Health Ball Memorial Hospital's commitment to treat all persons with respect, the hospital has been recognized as a safe place for lesbian, gay, bisexual and transgender patients (LGBT) to receive care, according to a national report released by the Human Rights Commission (HRC). Results of the Healthcare… Read More
Free clinical breast exams offered locally07/08/2011 | IU Health Ball Memorial Hospital
MUNCIE--The Indiana University Health Ball Memorial Breast Center provides clinical breast exams and digital mammography throughout the year at no cost for uninsured or underinsured patients. The next opportunity to participate in the exam will take place on July 13, at IU Health Ball Memorial Breast… Read More
Cooking Class for Teens Emphasizes Healthy Choices07/05/2011 | IU Health Ball Memorial Hospital
MUNCIE--Indiana University Health Ball Memorial Hospital Dietetics will host a class 9 am – 1 pm, July 16 for teens aged 13-16 to help them learn to safely prepare meals and snacks on their own. Topics include kitchen safety, proper use of a kitchen knife, preparing balanced healthy meals including items from all food groups, kitchen emergencies and more. The class is facilitated by Caleb Churchill,… Read More
IU Health Ball Memorial names new Chief Financial Officer06/30/2011 | IU Health Ball Memorial Hospital
MUNCIE - Carol Seals has been named Chief Financial Officer at Indiana University Health Ball Memorial Hospital. Since the merger of IU Health and Ball Memorial, Carol has been a member of the Financial Services Group serving as Director of Finance for the hospital. In this role she was responsible for the integration and transition of the business systems and processes onto Shared System Services… Read More


text:
Two local bands will join the Allman Brothers Band, the Zac Brown Band and others on the main stage at the Peach Music Festival this weekend at the Toyota Pavilion at Montage Mountain.
Kicking off the entire festival at 4 p.m. today will be Cabinet, the old-timey bluegrass and acoustic music six-piece consisting of Pappy Biondo (banjo, vocals), J.P. Biondo (mandolin, vocals), Mickey Coviello (acoustic guitar, vocals), Dylan Skursky (electric bass, double bass), Todd Kopec (fiddle, vocals) and Jami Novak (drums, percussion).
MiZ, the band led by guitarist and singer-songwriter Mike Mizwinski, will play at 12:30 p.m. tomorrow, also on the main stage, which has been dubbed the "Peach Stage" for the occasion. (The festival's second stage, dubbed the "Mushroom Stage," will be at neighboring Sno Mountain.)
"I'm not really sure how we got the gig," Coviello of Cabinet said in an interview with The Times Leader a few days before his band's main-stage debut. "I could make something up to make it sound better, but whatever, it's amazing.
"Ever since I was a kid, I was going to shows there, and never once did I ever imagine I would get a chance to play on that stage," the Moscow native said. "It's pretty good, man."
Coviello said the band has played previously with some of the bands on the bill, including Railroad Earth and Blackberry Smoke, and he is probably looking forward to seeing Zac Brown Band the most.
"I was introduced to his music because one of my guitar heroes, Tony Rice, played on one of his albums," Coviello said. "So I am most interested in his set, to see him play and to see how much bluegrass as opposed to country he plays."
Coviello also recommended Toubab Krewe, who will play the Mushroom Stage at 2:30 p.m. Saturday. "And, of course, the Allman Brothers Band as well," he said. "It will be great to see them up close."
Mizwinski, who grew up in Pittston and now resides in Scranton, also will play the main stage at Montage for the first time when his band performs tomorrow afternoon.
"When we heard about the festival, our agent reached out to them, and we didn't hear anything back for the longest time," Mizwinski said. "So then we put something on Facebook, telling people to let LiveNation know that they wanted to see MiZ play at the Peach, and they did.
"Over 300 people posted, and less than 24 hours later, we found out we were going to play 45 minutes on the main stage," he said. "It's the childhood dream of every musician in the Wyoming Valley to play on that stage, so we're really excited.
"Our goal is to play really high-energy, fun stuff," Mizwinski said. "There will be one cover; it's really cool, but I won't say what it is and spoil the surprise.
"And the rest will be a sort of MiZ greatest-hits set," he said with a laugh. "It will be great to get our music out there for so many people."
What: Local bands play The Peach
Who: Cabinet
When: 4 p.m. today on the main stage
Who: Miz
When: 12:30 p.m. tomorrow on the main stage


text:
VLC is a free and open source cross-platform multimedia player and framework that plays most multime...
Essential plugin for firefox users, open Microsoft formats directly in Firefox.
DigitByte Studio
A small application to capture video from devices like a webcam or TV Tuner card.
Webcam Simulator
Capture webcams, streaming video, full screen, part of the screen.
Webmaster Media Maker
Christopher Clark
Website Capture Plugin is used to take a screenshot of a web page.
Capture streaming video from any capture device like a TV tuner card or webcam.
Extracts audio from a video file and saves as WAV, WMA, MP3 and OGG formats.
Two Pilots
Adobe Premiere plugin for color correction of digital video.
ZeallSoft LEE
It is designed to help you capture streaming video and snapshots.
Color7 Tech Inc.
Power Video Capture allows you to capture video and image in real-time.
Applian Technologies Inc.
It is a program that enables you to record streaming and online video.
Aritrim Basu
EasyFLV Streaming Video Software - Add streaming video to your website.
SVSoftware, LTD.
Save Video plugin for IE is a suite of compact programs for downloading videos.
Best Game, Video and Desktop Recording software - much less Lag/CPU/HDD usage.
CuteFLV Streaming Video is a easyt-to-use video streaming software.
Movavi Video to Flash Plugin cannot be used as stand-alone.
Viscom Software
web cam,video mixing for two video devices.
Replay Video Capture v6.0.3
The plugin enables you to add the TV Ratings to the top of your home videos.
It is a free program that enables you to start a video chat session.
Video Essentials VII is a plugin collection with 10 sophisticated plugins.


text:
2013 JAINA Budget Questionnaire Response I Jiv Daya Group Page
Jiv Daya
Check / Draft should be drawn in favor of "JAINA",
With memo note "JIVDAYA".
Please mail checks to: 5308 E. 80th Place, Tulsa, OK 74136
Our Mission
Jaina's Jivdaya committee's main goal is to save animals from the slaughter house, and to provide nutrition, water, and healthcare for animals staying in panjarapoles. The Jivdaya committee also helps to build new sheds and to maintain existing sheds of panjarapoles. Each year, the Jivdaya committee receives appeals from panjarapoles all across India.
The Jivdaya committee requests your support in taking care of these animals. The impact of even a small donation makes a big difference in the lives of these animals. Since August 2012, the Jivdayacommittee has distributed $17,200 tovarious panjarapoles, saved 30 animals from slaughter houses in India, and distributed $2000 in the USA. We are in the process of sending an additional $12,130 to various panjarapoles and to save 61 animals. Details of 2012-2013 donations are listed below. Our goal is to collect $20,000 for 2013 during Paryushan & Dash Lakshana with your support.
To put it this in perspective, in India, the average cost of saving a cow from the slaughterhouse is $100. To provide food, shelter, and medical care for a one cow for one year is only $180.
For $51, one hundred animals can be fed for a day.
We are counting on your generous support for the purposes of Jivdaya. Donations made through JAINA are tax-deductible. Please contact any of the Jivdaya committee members if you have any questions.
Contact details for Chair Person & Committee Members
215 561 0581
Notable Achievements undertaken in the past five years
Past Projects:
12/10/2008 Sanjivani Bharti Education Social & Gram Vikas Pratisthan
Remember Me
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5/25/2015Memorial Day 2015 - Remembering Those Who Have Served.
4/30/2015Celebrate "Live and Help Live"
4/28/2015SUPPORT Nepal Earthquake Victims Relief Fund
The upcoming calendar is currently empty.
Click here to view past events and photos »


text:
Lake Park Apartments549 Arbor Hill Rd., Kernersville, NC 27284 View On Map (336) 310-1909
Pricing starts at $625.00/month on select units! - Two bedroom, two full bath 925sq feet with washer/dryer connections! Welcome home to convenience and relaxation at Lake Park Apartments!
Limited availability! Lake Park Apartments located in Kernersville, the heart of the Triad. A quick and easy commute to High Point, Winston-Salem, and Greensboro! Great shopping and entertainment are all close by. Stop in today to see for yourself why Lake Park Apartments is a great place to call home. Pricing is based upon availability...call for more details!
Lake Park is located in the Greensboro Area in the 27284 zip code. View this apartment on a map.
Pricing & Floor Plans
|Floor Plan
|Price Range
2 Bedroom 2 Full Bath
|Check Availability
Office Hours
- Monday - Friday 9:00 - 5:00
- Saturday 10:00 - 2:00
Why You'll Love Us
Love your life by the Lake! You'll love the lake setting nature views of our apartment homes. You'll also love our convenient location and great prices! We're less than a one-minute commute to Business 40 and 15-20 minutes from Winston-Salem and Greensboro. Enjoy the surrounding neighborhood, which includes Century Park Lake where you can spend the weekend fishing, cooking out, and enjoying nature! Spend time relaxing by our pool or enjoying the close-knit community. Make the short commute to Greensboro or Winston-Salem for dining and nightlife.
Features & Amenities
- Energy Efficient
- Pets Conditional
- Balconies
- On-Site Laundry Room
- Trash
- Copy and Faxes For Residents
- On-Site Management
- Swimming Pool
- Cable Ready
- Patios
- Wal to Wall Carpeting
- Excellent School District
- 24 Maintenance Emergency
- Vaulted Ceilings (3rd floor)
- Corporate Option
- Individual Lockable Storage
- On Site Maintenance
Floor Plan Features & Amenities
- Washer/Dryer Connections
- Refrigerator w/ Icemaker
- * Handicap Accessible Select Units
- Extra Storage on Patio/Balcony
- Ceiling Fans / Mini Blinds
- Disposal
- Private Patio / Balcony
- Dishwasher
- Air Conditioning
Maps & Directions
About Us
Professionally Managed By: Foster Management
Also visit us here: Be our Fan on Facebook
General Policies
Flexible Lease Terms (6-14 Months)
Pet Policies
Pets Conditional


text:
Our Bureau
New Delhi, Sept 6
THE employees unions of LIC would oppose any plans to bring about a voluntary retirement scheme (VRS) to reduce its staff strength.
"We are totally opposed to it," Mr B.S. Rawat, Joint Secretary, All India LIC Employees Federation, said, reacting to reports quoting the Chairman, Mr A.K. Shukla, as saying that the state-owned insurer was planning a VRS.
He said that LIC could take care of all its staff through aggressive growth plans. "We have had no discussions with the management for VRS," Mr Rawat said.
XThese are links to The Hindu Business Line suggested by Outbrain, which may or may not be relevant to the other content on this page. You can read Outbrain's privacy and cookie policy here.


text:
Mon-Fri: 7am-1am EST / Sat-Sun: 7am-11pm EST
ApplianceLG Dryer
Level of DifficultyA Bit Difficult
Time to do repair30 - 60 mins
Age of Appliance5 - 10 years
Screw drivers
I accessed the thermostats by removing the exhaust pipe and a plate where the exhaust can be ported on the side as an alternative. You need to get two hands inside to work. I struggled a bit before I noticed the removable access plate on theside. Took about 40 mins to get all three thermostats replaced. not too bad, but it is a tight working space.
Help other customers find the most helpful instructions.
Were these instructions helpful?
Part Number: PS3530481
Part Number: PS3530483
Part Number: PS3530485
All brand logos are trademarks of their respective owners.
The PartSelect logo is a Registered Trademark of Atlantic Laundry Centres, Ltd.
Copyright © 1999-2015 , Eldis Group Partnership. All rights reserved.


text:
Nadal advances at Indian Wells
INDIAN WELLS — Second seed Rafael Nadal routed Leonardo Mayer of Argentina 6-1, 6-3 in the second round of the WTA/ATP Indian Wells tournament on Sunday.
Nadal advanced to the third round, where he will face fellow Spaniard Marcel Granollers, who beat Tommy Haas of Germany 6-3, 2-6, 6-3.
Get Inquirer updates while on the go, add us on these apps:
Disclaimer: The comments uploaded on this site do not necessarily represent or reflect the views of management and owner of INQUIRER.net. We reserve the right to exclude comments that we deem to be inconsistent with our editorial standards.
To subscribe to the Philippine Daily Inquirer newspaper in the Philippines, call +63 2 896-6000 for Metro Manila and Metro Cebu or email your subscription request here.
Factual errors? Contact the Philippine Daily Inquirer's day desk. Believe this article violates journalistic ethics? Contact the Inquirer's Reader's Advocate. Or write The Readers' Advocate:
c/o Philippine Daily Inquirer Chino Roces Avenue corner Yague and Mascardo Streets, Makati City,Metro Manila, Philippines Or fax nos. +63 2 8974793 to 94


text:
Mon-Fri: 7am-1am EST / Sat-Sun: 7am-11pm EST
ApplianceKitchenAid Refrigerator
Level of DifficultyEasy
Time to do repair1- 2 hours
Age of Appliance5 - 10 years
NutdriverPliersScrew driversSocket set
I incorrectly ordered the ice dispenser door motor when I needed the ice dispenser auger motor which I subsequently ordered. I installed both the auger motor and ice dispenser motor with new replacement parts. Sourcing my own replacement parts and doing the work myself saved at least $100 to $150.Tip: I photographed each stage of the repair, e.g., whenever I removed a component, or disturbed the wiring, I photographed the work area layout. Then followed the photos in reverse to reassemble everything and dress the wiring just as it originally was. I did not trust any part of the remove and replace operation to memory and double-checked everything against the photos I took at each stage of the repair going in.
Help other customers find the most helpful instructions.
Were these instructions helpful?
Part Number: PS2352160
All brand logos are trademarks of their respective owners.
The PartSelect logo is a Registered Trademark of Atlantic Laundry Centres, Ltd.
Copyright © 1999-2015 , Eldis Group Partnership. All rights reserved.


text:
Pronunciation: darnos
Added on: 2010-01-21 Listened: 3 timesin: Add categories to darnos
Pronunciation in Spanish [es]
- Pronunciation by gmaranca (Male from Argentina)
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Could you do it better? different accent? Pronounce darnos in Spanish
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- Random word: Oviedo
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text:
A non-volatile SRAM cell including (i) a nonvolatile memory element, (ii) a volatile memory element coupled to the nonvolatile memory element and (iii) a gate circuit coupled to the nonvolatile memory element. The gate circuit is configured to transfer data to and from a first input/output line into the volatile memory element.
1. A non-volatile SRAM cell, comprising:
a nonvolatile memory element;
a volatile memory element coupled to said nonvolatile memory element;
a gate circuit coupled to said nonvolatile memory element, wherein said gate circuit (i) is configured to transfer data to and from a first input/output line into said volatile memory element and (ii) comprises (a) a first transistor coupled between said first input/output line and said non-volatile memory element and (b) a second transistor coupled between said first input/output line and said volatile memory element.
2. The non-volatile SRAM cell according to
3. The non-volatile SRAM cell according to
4. The non-volatile SRAM cell according to
5. The non-volatile SRAM cell according to
6. The non-volatile SRAM cell according to
7. The non-volatile SRAM cell according to
8. The non-volatile SRAM cell according to
9. The non-volatile SRAM cell according to
10. The non-volatile SRAM cell according to
11. The non-volatile SRAM cell according to
12. The non-volatile SRAM cell according to
13. A circuit comprising:
volatile means for storing data;
non-volatile means for storing said data upon a power fail event, coupled to said volatile data storing means; and
means for recalling said data from said non-volatile data storing means into said volatile data storing means when power is reapplied to a device containing the circuit, wherein said recalling means comprises (a) a first transistor coupled between a first input/output line and said non-volatile means and (b) a second transistor coupled between said first input/output line and said volatile means.
14. A method for recalling data previously stored in a volatile memory, comprising the sequential steps of:
storing said data in a non-volatile memory element coupled to said volatile memory upon a power fail event; and
recalling said data from said non-volatile memory element into said volatile memory in response to an application of power to a device containing both the non-volatile memory element and the volatile memory, wherein said non-volatile memory comprises (a) a first transistor coupled between a first input/output line and said non-volatile memory element and (b) a second transistor coupled between said first input/output line and said volatile memory.
15. The method according to
writing a predetermined digital logic value into said volatile memory, and
reading said non-volatile memory element.
16. A circuit comprising:
a memory storage element;
a true bitline and a complement bitline configured to write data to and read data from said memory storage element; and
a floating gate device (i) coupled between said true bitline and said memory storage element and (ii) configured to store data from said memory storage element during a power down condition.
17. The circuit according to
a second floating gate device (i) coupled between said complement bitline and said memory storage element and (ii) configured to store data from said memory storage element during said power down condition.
This application claims the benefit of U.S. Provisional Application No. 60/233,957, filed Sep. 20, 2000 and is hereby incorporated by reference in its entirety.
The present invention relates to SRAM cells generally and, more particularly, to a non-volatile SRAM cell that can be manufactured using a conventional floating-gate (e.g., EPROM, EEPROM or flash) or floating charge storage layer (e.g., SONOS or MNOS) technology. The present non-volatile SRAM cell may also function as a combination ROM-RAM cell (e.g., where the cell provides a ROM function on power-up and a RAM function under normal operating conditions).
One example of a conventional non-volatile SRAM cell can be found in U.S. Pat. No. 5,488,579, which is hereby incorporated by reference in its entirety. The cell of the 579 patent includes a three transistor non-volatile stack (i.e., with source-drain terminals in series), but does not shunt the SRAM pass transistor. The pass transistors also receive a second positive supply voltage, Vdd2, that differs from a conventional first positive supply voltage (e.g., Vcc or Vdd1). The stack is made up of PMOS transistors, with a PMOS SONOS device occupying the middle position.
The 579 patent has one or more of the following disadvantages: (i) a two-cycle cell that requires CLEAR and STORE non-volatile operations on power-fail in the worst case scenario, (ii) the cell is less suitable for combination ROM/SRAM due to potential finite disturb problems, and/or (iii) the cell has little margin for error (e.g., one must take significant care on RECALL to weaken the volatile latch for correct transfer of non-volatile data).
The present invention concerns a non-volatile SRAM cell, comprising (i) a nonvolatile memory element; (ii) a volatile memory element coupled to the nonvolatile memory element; and (iii) a gate circuit coupled to the nonvolatile memory element, wherein the gate circuit is configured to transfer data to and from a first input/output line into the volatile memory element.
Another aspect of the present invention concerns a method for recalling data previously stored in a volatile memory, comprising the sequential steps of: (a) storing the data in a non-volatile memory element coupled to the volatile memory upon a power fail event; (b) applying power to a device containing both the non-volatile memory element and the volatile memory; and (c) recalling said data from said non-volatile memory element into said volatile memory. In one embodiment of this aspect, the method recalling step comprises the steps of: (c-1) writing a predetermined digital logic value into the volatile memory, and (c-2) reading the non-volatile memory element.
The objects, features and advantages of the present invention include a non-volatile static memory cell that comprises a conventional SPAM cell and control circuitry, with (i) only one or two additional non-volatile transistors, (ii) only two extra control lines and a controlled power/voltage supply, and/or (iii) non-volatile memory elements that do not interfere with normal SRAM operation.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
FIG. 1 is a schematic diagram of a first embodiment of the present invention;
FIGS. 2(A), 2(B) and 2(C) are cross-sections, respectively depicting three operational modes of the non-volatile/floating gate transistor of FIG. 1;
FIGS. 3(A), 3(B) and 3(C) are cross-sections depicting the three operational modes of an alternative non-volatile/floating gate transistor to that of FIGS. 2(A), 2(B) and 2(C);
FIG. 4 is a schematic diagram of a second embodiment of the present invention;
FIG. 5(A) is a cross-sectional view depicting part of the circuit of FIG. 4, and FIG. 5(B) shows a timing diagram relating to one or more operational aspects of the embodiment of FIG. 4;
FIGS. 6(A) and 6(B) are timing diagrams showing other operational aspects of the embodiment of FIG. 4;
FIG. 7 is a flow chart exemplifying one set of NV-RECALL operations for the embodiment of FIG. 4;
FIG. 8 is a schematic diagram of a third embodiment of the present invention; and
FIGS. 9(A)-9(D) are a series of exclusive OR gates (XORs) useful in one embodiment of a NV-RECALL operation in which initially recalled data may be inverted.
FIG. 1 shows a diagram of a non-volatile SRAM (NVSRAM) cell 100 in accordance with a preferred embodiment of the present invention. The cell 100 generally comprises a gate 110, a nonvolatile memory element (NVM) 120 coupled to the gate, and a static random access memory element (SRAM) 130. Gate 110 receives and/or provides one or more data signals and receives one or more control signals enabling (i) data to be read from or written to SRAM 130, as well as (ii) operations affecting NVM 120. NVM 120 receives one or more control signals enabling programming, erasing and/or reading the NVM, and is configured to receive data from SRAM 130. SRAM 130 is configured to receive data from and/or provide data to input/output (I/O) busses (e.g., BL and BLB and/or circuitry coupled thereto) directly through gate 110 (e.g., through T1 and T2) and/or indirectly through NVM 120 (e.g., through FG1 and S1).
In the embodiment shown in FIG. 1, gate 110 may comprise first and second gate transistors T1 and T2 coupled to SRAM element 130 and receiving a first control signal (e.g., WL) at their gates, and a select transistor S1 coupled to nonvolatile memory element 120 and receiving a second control signal (e.g., NVSEL) at its gate. When cell 100 is single-ended (i.e., receiving data from and/or providing data to only a single bus), second gate transistor T2 may be absent.
As shown in FIG. 1, SRAM element 130 may comprise first and second load transistors P1 and P2, and first and second pulldown transistors N1 and N2. The transistors P1, P2, N1 and N2 may form a latch, but in alternative embodiments, load transistors P1 and P2 may be replaced with one or more resistors, or they may be completely absent (e.g., using a four_transistor SRAM cell such as that disclosed in U.S. Pat. No. 5,835,401; "A 16 Mb 400 MHz Loadless CMOS Four_transistor SRAM Macro," ISSCC 2000, p. 264; "A 1.9 um2 Loadless CMOS Four_transistor SRAM Cell in a 0.18 um Logic technology," IEDM 98, p. 643; and/or "A 0.99 um2 Loadless Four transistor Sram cell in a 0.13 um Generation CMOS technology," IEDM 99, the relevant portions of which are incorporated herein by reference).
Also as shown in FIG. 1, non-volatile memory element 120 may comprise a floating gate transistor (e.g., FG1), but may also comprise any type of readable and writable (or electrically erasable and programmable) nonvolatile transistor. FIGS. 2(A)-2(C) show a cross-sectional view of FG1, in which the floating gate transistor is fabricated on a P-doped substrate. Conventional N+ implants may form the source/drain terminals, and a conventional deep or directional N implant may form a "tip" implant at the source/drain terminal coupled to select transistor S1. This "tip" implant may be advantageous for electrically programming and/or erasing a FG transistor. The NV transistor (FG1) may further comprise (i) a floating gate (e.g., FG in FIGS. 2(A)-2(C)), separated from the substrate by a gate oxide layer having a thickness of 20-150 Å, preferably 50-100 Å, and in one embodiment about 80 Å, and (ii) a control gate (e.g., CG in FIGS. 2(A)-2(C)), separated from the floating gate by an interpoly oxide layer having a thickness of 40-300 Å, preferably 100-250 Å, and in one embodiment about 180 Å.
From an alternative perspective, gate 110 may comprise one or more pass gate transistors (e.g., T1 and T2), and NVM 120 may comprise select transistor S1 in series with transistor FG1, as an additional, parallel path to the gate, between an I/O line (e.g., BL) and the SRAM 130 (and more specifically, node D1 of the latch). The cell 100 may thus be implemented as a compact SRAM cell with non-volatile (NV) shadow memory. This combination RAM-NVM cell may be manufactured using conventional floating-gate of floating charge storage layer processing technologies. The non-volatility of this cell, by which the data stored in SRAM cell 130 is saved in NVM 120 when it might otherwise be lost, may be achieved with only the transistor FG1, with a minimal use of extra control lines. The cell 100 may thus be ideal for use in a data-save on power-down type application. A number of cells 100 may be combined to form an array.
From the alternative perspective, cell 100 may thus comprise a conventional 6-transistor SRAM cell with the transistor FG1 added for NVM storage and for recall. The select transistor S1 generally isolates the transistor FG1 from the effects of the I/O line(s) (e.g., BL) and SRAM cell 130 during normal operation of the SRAM.
A plurality of the present non-volatile SRAM cells, or a plurality of blocks of the non-volatile SRAM cells, may form an array. The array, or any blocks thereof, may independently comprise a matrix of n by m cells, wherein n and m respectively designate the number of rows and columns of the array or block, and n and m are each independently an integer of at least 2, preferably at least 4, and more preferably at least 8. Although there is no upper limit to the size of the array, as a practical matter, the array or block thereof may have a maximum of about 20 megabits (20 Megs), preferably about 10 Megs, more preferably about 4 Megs.
Table 1 below shows the node voltages/data states for various modes of operation: NV-CLEAR, NV-STORE, NV-RECALL and normal volatile SRAM operation, where X denotes a Don't Care" state. Data and its complement ("datab") are either VCC or 0 and are generally at opposite states.
TABLE 1 shows NV-CLEAR and NV-STORE operations, as well as two different NV-RECALL and NV-READ operations (one which writes all "0"s, providing "true" [non-inverted] data, but which includes, adjusting the supply voltage to the array; and one which writes all "1"s, providing inverted data, but which needs no array supply voltage adjustment). In general, NV-STORE is preceeded by NV-CLEAR to ensure adequate margins (and thus success) for NV-STORE. In one aspect of the present invention, the combination of NV-CLEAR and NV-STORE operations may be considered "programming" the NVM with the SRAM data. NV-RECALL does not have to be followed immediately by NV-CLEAR, but under certain conditions, or in certain embodiments, it may be advantageous to do so.
The following is a detailed operational description of the cell 100 of FIG. 1. Exemplary NV operations of NVM transistor FG1 in FIG. 1 are shown on the cross-sections in FIG. 2. As described above, the cell 100 may comprise a six-transistor (6T) SRAM cell, which is fully symmetrical for conventional SRAM operations (e.g., READ and/or WRITE). In addition, the floating gate transistor FG1 is typically used only for NV-STORE and NV-RECALL operations. "Soft" NV-STORE (e.g., independent of power decreases or failures) and "soft" NV-RECALL operations are feasible, and may be controlled by conventional logic circuitry adapted to store and recall NV data in accordance with the description(s) herein.
When the power supply to a device containing the present NVSRAM drops below a predetermined value (e.g., from 50% to 95%, preferably from 75% to 90%, of the nominal value), conventional power or voltage detection circuitry (e.g., comprising a conventional voltage comparator) may detect a power loss or power failure (or that such an event may be imminent). In any case, such power loss, power failure, detection thereof or detection that such event may be imminent may be considered to be a "power fail event". A control signal may be generated by such detection circuitry (which may further comprise conventional logic circuitry configured to generate such a signal), which in turn, will generate appropriate signals with appropriate digital or analog values to perform the NVM functions described herein.
As described above, typically, the first NVM function that occurs on detecting a "power-fail" event or condition is clearing any data stored in the NVM (e.g., "NV-CLEAR"). This helps ensure that volatile data can be read from the SRAM element 130 and written into NVM element 120 using a minimal amount of power.
During a NV-CLEAR operation, the floating gate of FG1 is at a negative potential (e.g., about one-half of the voltage on the control gate) and the n+ diffusion on the bit line side (e.g., coupled to S1) is at Vcc. The threshold voltage Vt of FG1 is then pulled low by discharge of electrons from the floating gate (FG) to the n+ diffusion common to it and select transistor S1.
There may be a band to band tunneling current (IBBT) flowing from the bit line which is biased at Vcc to the P substrate at zero bias. Since NV-CLEAR is typically done when Vcc is at or near its nominal value, supplying IBBT is generally not a problem. The control gate CG is at negative potential (e.g., VNN, which may be from about −5V to about −15V, preferably from about −7V to about −12V, and in one embodiment is about −8V), and the transistor FG1 is non-conducting. Therefore, the SRAM latched state is not disturbed by NV-CLEAR.
More specifically, as shown in FIG. 2(A), an NV-CLEAR operation may comprise applying a negative potential (VNN; e.g., any of the negative potentials described herein or a range such as −7 to −11V) to the control gate CG. In such a state, the bit line voltage VBL (and, optionally and independently, the complementary bit line voltage VBLB) may move to VCC. The wordline voltage VWL may move (or preferably be pulsed, optionally using a conventional charge pump circuit; see, e.g., CY refs: CD98018 and CD98019) to a positive potential>VCC to pass the supply voltage VCC to the source/drain terminal of FG1 coupled to select transistor S1 (i.e., opposite that source/drain terminal coupled to node D1 of the SRAM latch).
The NV-CLEAR operation may apply such voltages to such nodes for a time ranging from 1 to 100 ms, preferably 1-10 ms, although it may be>100 ms or<1 ms, as long as the conditions result in a low threshold voltage Vt for FG1.
After data is cleared from NVM 120, the data held at that time in SRAM 130 may be written into NVM 120 (a programming operation, or as used herein, "NV-STORE"). NV-STORE operations may be initiated in at least two modes: (i) when a power loss or failure (or a condition indicating that such power loss or failure is imminent) is sensed, or (ii) when the current array data is to be stored, independent of power loss: or failure (e.g., a "soft" store). The latter mode may be particularly advantageous, in one example, when including the present NVSRAM array in a PLD (programmable logic device; e.g., a simple PLD [SPLD], complex PLD [CPLD], field programmable gate array [FPGA], etc.), a programmable clock generator, a microcontroller (e.g., a programmable general purpose microcontroller, a Universal Serial Bus microcontroller, etc.), a microprocessor or digital signal processor, etc. In such devices, new programming or configuration information may be loaded or downloaded into the volatile memory for immediate use and fastest (down)loading speed, then stored in the nonvolatile memory at a more convenient time.
Specifically with regard to the circuit shown in FIG. 1, during a NV-STORE operation, the transistor S1 is off and the bit line BL is isolated from the transistor FG1. The control gate CG of transistor FG1 may be at a high positive potential Vpp. If D1 is at 0V, the FG1 channel is at 0V, and electrons are injected by Fowler-Nordheim (FN) tunneling (preferably uniform FN tunneling) from the channel into the floating gate (FG); and the Vt of transistor FG1 goes high. If D1 is at YCC, the potential difference between the channel which is at VCC and the FG is not high enough for any substantial electron injection, and Vt of FG1 remains low.
Since the control gate voltage (VCG) is generally at a negative potential VNN, both of the transistors FG1 and FG2 may be non-conducting and the SRAM latched state is not disturbed. At the end of programming, the wordline voltage VWL is generally first brought to zero before the negative supply voltage VNN is removed.
A write operation may occur when the control gate voltage VCG=VCC and the transistors FG1 and FG2 are conducting. The regular SRAM Write/Read operations are generally performed through the wordline voltage VWL, the bit line voltage VBL and the bit line voltage VBLB as indicated in TABLE 1.
The time required for the NV-STORE operation is typically 1-20 msec, depending on the number of bits in the array, the supply voltage, the available maximum current, etc. Because NV-STORE may involve uniform FN tunneling, there may be no band-to-band (BTB) current, and in such a case, the power consumed is only the power used to charge up the floating gates (a negligible amount). Therefore, the NV-STORE operation in the present invention is ideal for the case of storing data in nonvolatile memory during power loss or failure.
For transistor FG1, since transistor S1 is off, an inversion channel, created when the control gate voltage (VCG) is at VPP, is at the voltage present on node D1 (VD1). When the SRAM cell stores a "1", VD1=VCC, and the voltage difference between the channel and the floating gate may not be large enough to cause FN tunneling of electrons through the tunnel region. Therefore, when the SRAM stores a "1", the threshold voltage Vt of the transistor FG1 generally remains low.
However, when the volatile memory element stores a "0" state (VD1=0V and VD2=VCC), at the end of NV-STORE, the threshold voltage Vt of the transistor FG1 is high. The SRAM cells are not generally disturbed during a NV-STORE operation because the pass transistors T1 and T2 are off (since the wordline voltage [VWL]=0V).
At this point, the data in the volatile memory has been safely stored in NVM. Should power to the device containing the present NVSRAM fail completely, the data that was in volatile memory at the time of the power failure may be simply recalled from NVM when power is reapplied to the device. To recall data stored in the NVM 120, one may perform an NV-RECALL operation, which may comprise a PRESET operation followed by a NV-READ operation, and which may be performed, for example, according to either of the two following methods:
Recall Method 1
Set the array voltage VARRAY=VA1>VCC, and write 0's into the SRAM array to pre-set the SRAM cells to all 0's. The voltage VA1 is generally chosen to be sufficiently low that cells in which transistor FG1 has a low threshold voltage (Vtlow) will overwrite a "1" that may be stored in the cell.
Thereafter, appropriate voltages are applied to the select and NVM transistors to enable reading the NVM data from NVM 120 into the SRAM cell 130 (see, e.g., Table 1 above). Exemplary voltages applied to various nodes in and around FG1 for in the NV-READ step of this recall method are shown in FIG. 2(C). The voltage applied to CG (VCC) is exemplary. One may apply any positive bias greater than the natural (unprogrammed) threshold of the NVM transistor to CG, but preferably, a voltage of from VCC/2 to VCC is applied, and in the embodiment of FIG. 2(C), VCC is applied. The voltage at D1 (0V) results from writing a "0" into the SRAM cell in the preceding step.
Recall Method 2
1. Write 1's by setting the bit line voltage VBL=VCC, the bit line voltage VBLB=0 and the wordline voltage VWL=VCC.
2. Write 0's into cells whose floating gate threshold voltage Vt=Vlow by passing the bit line voltage VBL=0 through the transistors S1 and FG1.
3. Since the recalled state in this latter method will be the inverse of the stored state, restore the original polarity of the data by either:
a. repeating the NV-STORE and NV-RECALL operations (or performing a "dummy store and recall"; see the description of the embodiment of FIG. 4 infra); or
b. inverting the output from the I/O buffer and/or the sense amplifier corresponding to the cell by, for example, passing that output through an inverter or inputting that output along with a reference signal corresponding to the FG1 threshold state into an exclusive OR circuit as shown in FIGS. 9(A)-9(D) (vtlow corresponds to REF=1, and Vthigh corresponds to REF=0), then passing the inverted data through a gate responding to, e.g., a NV-REINVERT control signal (generated using conventional logic from the [control] signals generating the NV-RECALL and/or NV-READ states described above and in Table 1) back onto the bit lines for storing in the SRAM 130.
In this recall method, the reference signal may be stored in a reference NVSRAM cell, whose output=0 for cells whose NVM has a high threshold voltage. When the recalled state is inverted, the reference NVSRAM cell output may also be inverted. An XOR circuit may now invert the recalled inverted state, leading to correct polarity.
The preferred recall for non-inverted data is "cells preset to all 0's" in Table 1 above. Data inversion on RECALL (as disclosed in the 579 patent) is not necessarily an ideal mode of operation, since data tracking and re-inversion circuitry is required. Nonetheless, under certain conditions (e.g., where it is not convenient or possible to reliably adjust or lower the voltage to the array or write all 0's into the SRAM array), data inversion is perfectly appropriate and may even be preferred.
When using the "write all 1's" NV-RECALL method, the supply voltage to the NVSRAM cell array (e.g., VARRAY) may be decreased to weaken the latch so that the non-volatile data can be written into the SRAM, even at a typical end-of-life NVM charge retention state (e.g., 10 years or more). With VARRAY held at this low value, the bit line BL and the control gate CG are kept to VCC (not decreased) and, ideally, the signal NVSEL is taken sufficiently above VCC to enable passing VCC from BL to FG1, but not so much above VCC to risk breakdown of the select transistor gate oxide.
In a preferred embodiment, VARRAY is decreased to a worst case maximum value of the PMOS and/or NMOS thresholds in the SRAM element, so that volatile data may be written from the non-volatile transistor and/or held (however weakly, either without overwriting or once written from NVM). A threshold mismatch may advantageously allow data to be maintained by the MOS devices (which may be a slight weak-inversion) even if VARRAY decreases below the worst case maximum value of the SRAM transistor thresholds.
The FG1/S1 chain may pull the D1 node high if cell 100 recalls a cleared state (FG Vt=low). Therefore, the VARRAY decrease is generally selected to differentiate successfully between a cleared floating gate FG1 (Vt=low, NVM data=0), on the one hand, and a programmed floating gate FG1 (Vt=high, NVM data=0), on the other hand. The control gate CG may also be taken to a non-VCC value, depending on the end-of-life characteristic requirements of the non-volatile floating gate FG1.
An alternative embodiment of the NVSRAM cell 100 may replace the select transistor S1 with a PMOS transistor. The voltage on node NVSEL may be changed as follows while all other signals are same as in TABLE 1.
All the other biases are the same as in Table 1. The advantage of this alternative cell is that the gate of PMOS transistor S1 does not need a bias>Vcc.
When the cell 100 saves data in the NVM on power loss or failure (e.g., during a "power fail" condition), an external supply voltage support (e.g., a battery) may be advantageous for both NV-CLEAR and NV-RECALL cycles. If a CLEAR cycle is executed just after a RECALL cycle, a power decrease or failure may interrupt the CLEAR process, and data in NVM could be lost. Under these circumstances, a CLEAR cycle would generally have to be complete before a NV-STORE operation takes place to re-capture the data, and an external battery may supply sufficient power to enable
successful NV-CLEAR, NV-STORE and NV-RECALL operations. The cell 100 does normally consumes little or no additional power during the NV-CLEAR and/or NV-STORE cycles.
In one example, the cleared state will not be disturbed by the volatile data, and may be supported when the volatile data is in a particular state (e.g., a D1 "logic high" state). The programmed state may suffer some risks due to potential SRAM data disturbance, depending on the technology and the VCC supply voltage level. However, the programmed state (e.g., after NV-STORE, FG1=Vthigh) of the cell 100 will largely exist and be maintained, even in power-down mode. Threshold voltage disturbances may be controlled by applying a predetermined bias voltage on the control gate CG (which is preferably one that, in the example of FIG. 1, maintains FG1 in a non-conducting state) and by selecting a minimal voltage supply to the array.
The NVM may be programmed (i) the first time the cell 100 is powered up and (ii) after each NV-RECALL cycle. One design objective may be to simultaneously lower the threshold voltage Vt of the nonvolatile transistor FG1 when the control gate voltage VCG=VCC and the transistor FG1 is in a conducting state.
Switching of the state of latch draws a current through VARRAY. To minimize this current, recall operations may be done on selected groups of word lines sequentially, instead of on the whole array simultaneously.
During normal SRAM write/read operations, Vt disturbances of the NV transistor FG1 by the potential at node D1 can be minimized by a careful choice of bias (e.g., between 0 to Vcc) on the control gate CG so that the FG1 Vt can meet the end of life characteristic requirements for either Vtlow (an NV-CLEARed state) or Vthigh (NV-STOREd state). For "back up on power fail" applications, the NV-CLEARed state should be supported for NVM "end-of-life" conditions.
The NV transistor shown in FIG. 2 is shown as an n-channel floating gate transistor that uses FN tunneling for NV-CLEAR and NV-STORE operations to put its Vt in low and high values, respectively. However, the NV transistor can also be a p-channel floating gate transistor, fabricated in an N-well, as depicted in FIG. 3.
During NV-CLEAR, for example, electrons may be injected into the floating gate by band to band tunneling (BBT). The injection of the electrons into the floating gate may make the Vt of the floating gate p-channel transistor positive (i.e., conducting when the bias on CG=0). During NV-STORE, if node D1 is at VCC, then electrons would be discharged to the N-well by FN tunneling, making the Vt of the p-channel floating gate transistor negative or non-conducting. A high threshold voltage Vt may be achieved by hot electron injection into the floating gate due to BBT. Discharge of electrons may be achieved by FN tunneling.
Referring now to FIG. 4, an alternate seven-transistor ("7T") NVSRAM cell 200 is shown. The 8T NVSRAM 100 of FIG. 1 may be functionally replaced by 7T NVSRAM cell 200. The 7T NVSRAM cell 200 comprises a gate 210, a nonvolatile memory element (NVM) 220 coupled to the gate, and a static random access memory element (SRAM) 230, just as for the 8T PNVSRAM 100 of FIG. 1. The primary difference between 7T NVSRAM cell 200 and 8T NVSRAM cell 100 is that gate 210 has one less transistor than gate 110 (or, alternatively, that NVM 220 is not directly coupled to I/O line BL and has one less transistor than NVM 120).
In FIG. 4, the bit line BL may be connected to D1 through a series combination of pass transistor T11 and floating gate transistor FG11, configured such that this series combination is approximately equivalent to the transistor T1 of cell 100 during conventional SRAM READ/WRITE operations, but is equivalent to the series combination of select transistor S2 and floating gate transistor FG1 of cell 100 during NVM operations.
While the 8T NVSRAM cell 100 of FIG. 1 may be coupled to a single word line, the 7T NVSRAM cell 200 of FIG. 4 may be coupled to divided first and second SRAM word lines (e.g., WL1 and WL2). The operation of cell 200 can be explained with reference to the TABLE 3 below (where X=don't care).
Similar to cell 100, cell 200 stores data from SRAM cell 230 into NVM 220 on a "power fail" condition and recalls the data from NVN 220 back into SRAM 230 when power is reapplied (a so-called "power-up" condition). In the cell 200, floating gate transistor FG11 is generally in series with the pass transistor T11. NV-CLEAR, which may be done upon power loss and which generally is performed after each recall (and generally prior to normal SRAN operations), brings the Vt of FG11 low and enables fast, efficient SRAM READ and WRITE operations in all cells. The description of the other operations of the cell 200 may be similar to those of the cell 100, including decreasing VARRAY during recall. However, for the circuit 200, the bias on the control gate CG during SRAM READ and WRITE operations is at least about VCC, and preferably is about VCC (to minimize power consumption).
Performing NV-CLEAR after NV-RECALL also ensures that the array data can be stored in the NVM elements at the next "power-fail" event. During NV-CLEAR (a global clear or erase operation on all NVM elements in the array), the threshold voltage Vt of the floating gate transistor FG11 may be lowered to a low value (e.g., less than or equal to about 0V). During NV-CLEAR, electrons may be removed from the floating gate of FG11, which may be at a negative potential compared to the node VBL1, which will generally be about or above VCC. By applying a negative VNN pulse to the FG11 control gate, raising or pulsing the voltages on BL (VBL) and WL1 (VWL1) to slightly greater than VCC (typically about from about [VCC+VtCMOS] to about [VCC�2], where VtCMOS is the threshold voltage of a PMOS or NMOS transistor, preferably [VCC+(N�VtCMOS)], where N is a number of from 1 to 4, more preferably from 1.2 to 2.5), T11 can pass a voltage of from VCC to VBL to FG11, thereby providing a source of band-to-band tunneling current for FN programming of FG11. During NV-CLEAR, the voltage on WL2 is held to about 0V, and the transistor T12 is thus off (or non-conducting).
A cross-sectional view depicting the removal of electrons from FG11 is shown in FIG. 5(A), and timing diagrams relating to the NV-CLEAR operation for cell 200 are shown in FIG. 5(B). At the end of NV-CLEAR, the threshold voltage Vt of FG1 is preferably at a low state, so that FG11 will be in a strong conduction state when the control gate voltage is at VCC (for subsequent SRAM READ/WRITE operations). Furthermore, when the FG11 Vt is low, the drain to source voltage (VDS) of FG11 will also be low.
The transistor T11 is generally turned on by applying a clearing voltage (VWCLR) to the word line WL1. The clearing voltage on word line WL1 is sufficiently greater than VCC to pass the voltage from input/output (I/O) line BL, which is generally about or slightly above VCC, to the n+ diffusion of the floating gate transistor (see, e.g., VBL1 in FIG. 5(A)). In a preferred embodiment, the voltages in excess of VCC (e.g., on word line WL1 and/or bit line BL) may be provided by a conventional charge pump. A bit line voltage higher than VCC may enable a faster clear, or alternatively, a less negative voltage VNN on the control gate.
A combination of positive voltage on the n+ diffusion and a negative voltage on the floating gate may increase the n+ to leakage current due to band to band tunneling ("IBBT" in FIG. 5(A)), which can occur when VCC is at its nominal value. The sum of all IBBT's for the array may be reduced by (i) implementing a slow ramp (rate of change) of Vnn and/or the voltages on BL or WL1, and/or (ii) partitioning the array (or portion thereof to be cleared) into sub-blocks by applying VWCLR to selected groups of the word lines WL1.
An exemplary timing sequence of the various voltages and/or pulses applied to the cell 200 in order to clear NVM 220 is shown in FIG. 5(B). The three waveforms, from top to bottom, respectively represent the voltages (Y-axis) on BL, WL1 and the control gate of FG11 (Vcg; also see FIG.4) as a function of time (X-axis). The voltages on BL and WL1 are raised at substantially the same time, and thus, a single control signal may initiate these sub-operations. However, the negative pulse generally applied to Vcg (assuming FG11 is an n-channel transistor; a positive overvoltage is applied when FG11 is a p-channel device, see FIG. 3(A)), which may be initiated before, at substantially the same time as, or even later than the BL and WL1 pulses, takes longer to reach its effective value. Consequently, the timing of the three signals/pulses must be arranged such that their pulse widths (tpw) overlap at their effective voltages for a length of time effective to clear the NVM or substantially remove the electrons from the floating gate or charge storage layer of the NV transistor. Generally, this length of time is on the order of 1 ms (e.g., from 100 ns to 10 ms, preferably from about 500 ns to about 5 ms).
After NV-CLEAR, standard SRAM READ/WRITE operations may be performed by setting the voltage on the FG11 control gate (VCG) to about, equal to or greater than VCC. Since FG11 will generally be conducting strongly in this operational mode, the drain to source voltage drop (Vds) across the floating gate transistor channel will generally be quite small, and the effect of FG11 on SPAM cell operations should be minimal. The width-to-length ratio W/L of pass transistor T11 may be larger than the width-to-length ratio W/L of pass transistor T12 to minimize the FG11 Vds effect on the operation of the cell 100. When the n+ source/drain diffusions of FG11 are at or about VCC, the (drain) disturb is generally minimal since VCG should also be at or about VCC.
On detection of a power loss or failure during normal SRAM READ and WRITE operations, an NV-STORE operation may save the volatile data in SRAM 230 (which would otherwise be lost) in NVM 220. NV-STORE may comprise turning off the gate transistor to the true data I/O line (e.g., T11), for example by setting the corresponding word line (e.g., WL1) voltage to 0V. When FG11 is an n-channel device, VCG may be raised or pulsed to a positive overvoltage Vpp (e.g., from about 12V to about 18V, and in one embodiment, about 15V) for a time of from approximately 0.1 to 100 ms, preferably from about 1 to about 10 ms. When FG11 is an n-channel device, VCG may be lowered to a negative "overvoltage" (e.g., Vnn), as shown in FIG. 3(B).
For those SRAM cells storing a logic "0" state (i.e., the voltage at node D1 is approximately 0V), the inversion channel under the FG11 floating gate is generally at zero potential, and the coupling of VCG (at Vpp) to the floating gate is sufficient to charge the floating gate with electrons by FN tunneling from the inversion layer. At the end of a NV-STORE, floating gate transistors connected to SRAM cells with D1 at 0V generally have a high threshold voltage (Vthigh), where Vthigh≈VCGRAM (where VCGRAM is the control voltage VCG during SRAM READ/WRITE operations).
For those SRAM cells 230 storing a logic "1" state (i.e., the voltage at node D1 is approximately VCC), the inversion channel under the floating gate will generally be at the supply voltage VCC. In such a condition, the voltage difference between the floating gate and the channel is generally insufficient for substantial FN tunneling, and the Vt of the floating gate transistors connected to the SRAM cells storing a 1 generally remain low (i.e., Vtlow, which in one embodiment is about 0V).
In general, the entire channel of the floating gate transistors may be at a uniform potential for either SRAM data state, and there is generally no BBT current involved in the NV-STORE operation. Therefore, in the present invention, NV-STORE is an extremely low power operation, which may be important when an impending power failure is sensed. For increase the likelihood of success, NV-STORE generally consumes a minimum amount of power.
The array voltage (VARRAY) may also be pumped to maintain VARRAY at greater than or equal to the nominal value of VCC (VCCNOM), to compensate for the decrease in VCC during the NV-STORE operation. Such pumping may be desirable to inhibit FN tunneling of the NVM cells in a 1 state.
Once the SRAM data is safely stored in the corresponding NVM cells (or transistors), power may fail or be lost without loss of the data. When power is reapplied to the circuit, a NV-RECALL operation may be conducted to restore the data stored in NVM back into the corresponding SRAM cells. NV-RECALL may be conducted by the following sequence, illustrated by the waveforms in FIGS. 6(A)-(B):
1. Assuming the power applied to the circuit is initially 0V, raise VARRAY to a voltage<VCC, but large enough for data retention in SRAM 230. A lower VARRAY will reduce the currents generated in those SRAM cells in which the data state changes, relative to a VARRAY=VCC. A VARRAY value<VCC may be maintained (if necessary or desired) by conventional voltage translation or reduction circuitry (e.g., a diode stack, a conventional buffer receiving the reduced voltage at a source/drain terminal thereof, etc.).
2. Write a single logic state (either all 1's or all 0's) to either the whole array or to blocks thereof (e.g., portions of the array determined by groups of word lines WL2) by:
a) raising WL2 to VCC; and
b) setting the complementary bit line voltage (VBLB) to VCC (to write, or PRESET, a "0") or 0V (to write, or PRESET, a "1"). FIG. 6(A) shows a timing diagram for the WL2 and BLB pulses when writing a "0" to SRAM cell 230. The voltage at node D1 is now about 0V and the voltage at node D2 is now about the same as the value of VARRAY. At the end of a predetermined period of time t1 (e.g., 1-10 ns, preferably 2-5 ns, if VARRAY=VCC), the WL2 voltage may be brought down to 0, as shown in FIG. 6(A).
3. As shown in FIG. 6(B), raise Vcg to VcgRAM (preferably a value of from [0.9�VCC] to [1.1�VCC], or about VCC), and approximately simultaneously, raise the true bit line voltage to VCC. A short time thereafter (e.g., a time sufficient to enable the data in NVM 220 to write itself into SRAM 230, which in certain embodiments may be from about 0.5 to 1000 ns (preferably from 1 to 200 ns, more preferably from 10 to 100 ns), raise WL1 to VCC, for a length of time tpulse. For those NVM cells storing a "1, the FG11 Vt will be low, VCC (or slightly less than VCC) from BL is passed to D1, and the SRAM cell 230 switches to a "1 state. For NVM cells storing a "0, the FG11 Vt is high, and no voltage from BL will generally be passed into the SRAM cell 230, thereby maintaining a "0" in SRAM cell 230 (consistent with the example shown in FIGS. 6(A)-(B)). The time tpulse is generally selected to be that length of time that is sufficient to switch the SRAM cell 230 in a cell 200 having a Vtlow NV transistor from a preset "0" to a "1 state, but insufficient to switch the SRAM cell 230 in a cell 200 having a Vthigh NV transistor from a preset "0" to a state "1.
4. Increase VARRAY to VCC.
In addition, during NV-RECALL, VCG may be lowered below VCC to make sure that the NV transistor leakage in the Vthigh state is low enough that cells at a "0 state are not erroneously switched to a "1 state.
Since NV-RECALL does not generally affect the Vt of the NV transistors, NV-RECALL may be performed in a few ns (e.g., 1-10, preferably 2-5 ns) for a block of NVSRAM cells. In order to minimize current consumption (Icc) during NV-RECALL, the array may be subdivided into blocks, then a separate and/or independent NV-RECALL operations (PRESET and/or NV-READ) performed on each block. The blocks need not be equal in size because Icc may be higher when WL1 is at VCC (as compared to when WL2 is at VCC). Therefore, a block of WL2s may be selected for PRESET that is larger than the block of WL1s that are selected for the corresponding NV-READ.
During NV-RECALL, VARRAY is generally<VCC to enable SRAM cells to switch to a "1 state when: (i) PRESET has written all 0's into the SRAM cells, (ii) BL is at or about VCC, and (iii) FG11 is conducting. In one embodiment of cell 200, pulldown transistors N11 and N12 may independently have a larger drive capability (e.g., W/L) than the corresponding pass transistors T12 and T11. In order to provide a larger current through T11 and FG11, VARRAY is generally kept at<VCC ("VA1", which in one embodiment, may range from (Vt+0.1(VCC−Vt)) to 0.9�VCC; in another embodiment, VA1 may range from (VCC/4) to (3/4)VCC; in yet another embodiment [where VCC=5V], VA1 may range from 0.8V to 4.0V, preferably 1.0V to 3.0V). The n-well enclosing the PMOS transistors P11 and P12 is generally biased at or about VCC to prevent forward biasing the P+/n-well drain junctions of the transistors P11 and P12. This may mean that the P11 and P12 n-wells, on the one hand, and the VARRAY bus(ses), on the other hand, may not share common contacts. At the end of a NV-RECALL operation, VARRAY is generally ramped from VA1 to VCC.
The following may summarize key aspects of the NV-RECALL operation, in particular for the cell 200 of FIG. 4 and the case where all SRAM cells 230 are PRESET to a digital logic "0":
1. Keep VARRAY=VA1, where VA1 is kept low (<VCC), but high enough for data retention.
2. Write "0 s to all cells in the array (PRESET to all 0's) by raising BLB and WL2 to≧VA1 (preferably near or about VCC).
3. Raise BL to VCC and Vcg to≈VCC. Apply VCC to WL1. Sequencing groups or blocks of word lines may keep the Icc low.
The cells 200 which stored a "1 during NV-STORE will have a conducting floating gate transistor FG11 (and transistor T11). In such cells, SRAM 230 may be switched to a "1 state, but where the voltage at D1 is generally about VARRAY.
4. Raise VARRAY to VCC.
As diagrammed in FIG. 7, an alternative NV-RECALL operation presets all SRAM cells 230 to a digital logic "1" prior to NV-READ. This alternative method may be preferred when pullup PMOS transistors P11 and/or P12 are weak (e.g., small current drive relative to gate transistor T11 and/or pulldown NMOS transistors N11 and/or N12). In such a case, it is generally easier to pull down D1 towards 0V through T11 and FG11.
In this embodiment, NV-CLEAR and NV-STORE may be as previously described, but VARRAY may be about or equal to VCC during
both NV-RECALL steps, thereby avoiding any voltage translation circuitry used to decrease VARRAY in the "all 0s" PRESET step. However, the recalled data in the "all is" method are inverted from their original state in SRAM 230 just prior to NV-STORE. This "all is" NV-RECALL operation is summarized in Table 4, where "X"=don't care.
Of course, the recalled inverted data must be re-inverted to get back to its original state. FIG. 7 shows two methods of re-inverting the recalled inverted data, one of which was described generally for NVSRAM cell 100, and one which now will be described for NVSRAM cell 200. However, any method of data inversion that works under the operational conditions of the integrated circuit containing the present NVSRAM array will be acceptable.
In a first option, the entire NV-CLEAR, NV-STORE and NV-RECALL sequence is repeated (a so-called "dummy STORE and RECALL"). As for the first such sequence, NV-CLEAR sets the FG11 Vt low. A "dummy" NV-STORE operation maintains a low FG11 Vt for those cells in which the inverted SRAM data is a digital "1", and changes the FG11 Vt to high if the inverted SRAM data is a digital "0." NV-RECALL then comprises PRESETting all SRAM cells to a digital "1", then NV-READing the cells to re-invert the data therein.
In a second option, the integrated circuit may have two output paths from the sense amplifiers receiving data signals from particular columns, or blocks of columns, in the array. One output path includes an inverting output buffer (e.g., for data inversion after NV-READ), and the other includes a non-inverting buffer (e.g., for normal SRAM operations). Appropriate logic circuitry (e.g., a switch or mux) toggles between these paths, depending on the operation being performed.
An alternate embodiment of the 7T NVSRAM cell 200 is one in which the NMOS pass transistors T11 and T12 are replaced by PMOS transistors. Similarly, in the 7T NVSRAM cell 200 shown in FIG. 4, the N-channel FG transistor FG11 may be replaced by a P-channel FG transistor, like that shown in FIG. 3. The operation of the alternative 7T NVSRAM cell with a P-channel FG transistor would be similar to the one with the N-channel FG transistor, but for appropriate changes in the BL voltages for the p-channel floating gate transistor operation (see, e.g., Table 2 above).
The band widths, or margins for error, when transferring data between NVM and SRAM elements in the present invention is remarkably large, compared to conventional "shadow" NVM that communicates with a corresponding SRAM through a bus. This relatively large margin becomes particularly important when transferring data upon a power loss or failure.
Referring now to FIG. 8, a third embodiment of the present NVSRAM cell is shown. NVSRAM cell 300 is similar to NVSRAM cell 200, except for an extra NV transistor between gate transistor T22 and the SRAM cell (latch) 330, and one less word line to control transistors in gate 310. One advantage of the cell 300 is the addition of only one global control signal VCG and two floating gate transistors FG1 and FG2 to a conventional 6T SRAM cell.
The NV-CLEAR, NV-STORE and NV-RECALL operations are quite similar to those of the other NVSRAM cells described herein, and may be summarized in TABLE 5 below.
One advantage of the NVSRAM cell 300 is the addition of only one global control signal VCG and two floating gate transistors FG1 and FG2. Several differences in the operation of NVSRAM cell 300 should be noted.
For example, to clear the NV transistors, both I/O lines (BL and BLB) are raised to VCC. When Vcg is at VNN, both NV transistors are non-conducting, and any data in SRAM 330 will not be disturbed. At the end of the NV-CLEAR operation, it may be advantageous to first turn off the gate transistors (e.g., bring WL to 0V for the circuit in FIG. 8) before removing VNN from Vcg.
After NV-STORE and during NV-RECALL, one NV transistor will have a high Vt, while the other will have a low Vt. This may help improve the stability of the data transferred back into SRAM 330 from NVM 320, relative to 7T NVSRAM cell 200.
The general objective of the NV-RECALL operation is to restore the state of the SRAM array (e.g., the latched data) that was saved during the NV-STORE operation. The operation may have the following sequence:
a. With the initial state of the word line (WL)=0V, raise both the BL and BLB voltages to VCC.
b. Raise the WL and Vcg voltages to VCC. If the saved state corresponds to a "1" (e.g., the voltage at node D1 is about VCC and the voltage at node D2 is about 0V), the Vt of FG1 (e.g., Vt1) is low, and VCC on BL is passed to D1. The Vt of FG2 (e.g., Vt2) is high, and VCC from BLB is not passed to D2.
c. Ramp VARRAY to VCC. (Vss=0 for all operations.)
The SRAM latch now has a "1" state, and the SRAM data has been restored. The recall operation is generally performed after power up following a power fail or to restore the saved SRAM state.
As for the other embodiments, NVSRAM cell 300 may include p-channel gate transistors, in which case the array oerations are as shown in Table 6 below.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
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The words Trinamool Congress chief Mamata Banerjee was using against BJP Prime Ministerial candidate Narendra Modi was not permitted by law and spoke of her desperation, BJP leader Ravi Shankar Prasad said today.
"As per law, a Chief Minister of one state can't use such words against another Chief Minister and Mamataji should not use such words against a person who is going to become the Prime Minister of India," he said.
"Mamataji normally doesn't use such words, but her choice of words shows her desperation. The kind of words she is using shows her desperation with the rise of BJP in Bengal," he claimed.
He alleged that the Trinamool Congress represented scams in West Bengal just as the "Congress-led UPA is representing scam India".
Prasad also asked the West Bengal Chief Minister to check her facts and figures before commenting about Modi.
He said 25 parties had extended support to BJP and Modi, and BJP's parliamentary board and national executive had given the nod to the decision of anointing him as BJP's prime ministerial candidate.
Commenting on the performance of the EC, he said, "I am pained with the EC. I am sharing the pain of the people of Bengal. It is an acid test of EC as entire India is looking at India's general elections."
Told that Banerjee was opposed to a CBI enquiry into the Saradha scam, he said, "Then the law will take its own course through court proceedings."
Asked whether a CBI enquiry into the ponzi scheme would take place in the event of BJP coming to power at the Centre, he said, "If Mamataji honestly wants a proper enquiry to bring out the truth, let her write to the Centre that she wants a CBI enquiry. I can assure that it will be a free and fair enquiry."
Asked whether BJP would provide a financial package to debt-ridden Bengal, Prasad said, "We will give special attention to states of eastern India.
"Narendra Modi and BJP will never mete step motherly treatment to any state based on their political colour.
Neither Vajpayee has done it nor will Modi," he said.
Prasad claimed that the NDA would cross the 300-plus mark on the day of counting on May 16, when asked about a tie up with the TMC.


text:
I Don't Eat Green Things
It's like Health Food D-Day around here. D being D-I-E-T.
My doctor has put me on a 30 day strict diet. No sugar, no wheat, no flour, no yeast, no vinegar, no nothing. Just meat. Vegatables. Water. I'll spare you the why's of it all, but he swears when I'm done I'll be a new woman. Can't I keep my cheeseburgers and ice cream and be a half-way improved woman?
Anyway, it's gonna be tough. I would appreciate any prayer on my behalf. I am not strong in the will power department. And as for Christmas day? Well, forget it. That's a guaranteed cheat day. Why pretend otherwise? I don't think baby Jesus would want it any other way.
So I've been trying to mentally prepare for this 30 day sojourn into tasteless and healthy. I've been stopping by some of my favorite fast food restaurants and having my last meal (s). Yesterday morning I went to McDonald's for breakfast. I choked up a bit at the window. "You won't see me for a while. I just wanted to say….goodbye. Be strong without me. " And then my Egg McMuffin and I spent some quality time together on the interstate weaving in and out of slow drivers in the passing lane. I said, "Egg McMuffin, I want to tell you and your brother Sausage Burrito (hold the salsa) that just because I have to go away for a little while doesn't mean that I don't love you. I'll think of you often. And though you are nine minutes and seventeen seconds away, you'll never be far from my heart." And then we sang Precious Memories. (Okay, no we didn't. I sang that Paparazzi song by Lady GaGa, but I only hummed the chorus because you can't sing P words with a mouth full of egg and muffin.)
I have no idea what I'm going to eat today. I'm already stressed about it. Breakfast isn't that hard. But lunch and dinner? Ugh. What is the point? This would be much easier if I liked vegetables. But unless they're covered in Ranch or something in the color scheme of Nacho, I do not. What I like is Ben and Jerry's, but that's not on the acceptable foods list. Pretty much nothing is.
So gimme some tips, friends. What is your favorite healthy thing to eat? Mine is a salad, but salad dressing is on my no list. I also like homemade sweet potato fries–which are healthy. (Not the store bought kind or the kind you get at restaurants with that stuff like donut glaze on them.) Do green beans make your heart flutter? Maybe beets (gag) inspire you to poetic haikus. Or perhaps tofu makes you weak in the knees? Let me hear what your favorite healthy thing to eat is. And first one who gets cute and mentions ice cream will get a character named in their honor in a future book. A mean, snaggle-toothed, cellulite-ridden, character who spits when he/she talks and smells like pickles.
Have a great rest of the week.
Yours in healthy misery,
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18 Comments so far
Jenn December 9th, 2009 6:58 am
I feel your pain!! Due to food allergies, I can honestly say been there, done that. Not to make it sound worse, but you'll actually start to feel better in a couple weeks or less-though the craving is worst in the first week:) Favorite healthy food would be romaine lettuce or baked sweet potatos. Praying for the healthiness of you
Heather December 9th, 2009 9:13 am
I'm so very sorry! My heart (and my stomach) go out to you! My favorite healthy thing to eat is grilled salmon or chicken with vegetables. Not all that exciting, but it's really good and makes you forget that you're being healthy. I like butter with mine, but since I doubt you can eat butter, I'd say to use the I Can't Believe It's Not Butter Spray (if that's allowed). Good luck my friend. I'll try not to eat around you for at least 30 days…or maybe I should actually join you…might do me some good!
Tammy December 9th, 2009 9:20 am
How horrible!! I would die if I couldnt have my chocolate fix!
But if I had to choose on what healthy food to eat it wouldve brocolie, those little green trees can be pretty tasty!!
Stay strong!!!!
Laura G. December 9th, 2009 10:26 am
I've gotten pretty attached to steamed broccoli since I've recently been eating more veggies…good luck!
Natalie December 9th, 2009 10:26 am
Jen, I've been eating healthier over the past 12 months. I can share some recipes with you. Will send to your email.
Jenny B. Jones December 9th, 2009 10:30 am
Jenn, I love baked sweet potoatoes. It's a new veggie for me. But sadly for the next month I can't have potatoes either. LAME!
Heather, I am gonna branch out and try salmon. In the past I haven't enjoyed it, but I'm gonna try again. I"m a tilapia girl myself.
Tammy, my little nephew used to call broccoli trees. : ) Exactly what they look like.
Laura, steaming is the way to go. Great tip.
Natalie, you're my role model! Thanks for any recipes.
Sarah December 9th, 2009 10:50 am
My mom keeps telling me I did to cut out wheat in my diet-UGH!
I hated veggies as a kid, and then in college I was a vegetarian for awhile-I still don't really care for red meat, but I will eat chicken now. I like green beans and spinach mostly. And Hominey is the only kind of corn I eat-it's good if you don't like corn. I started liking veggies because I ate veggie lasagna-I don't know if you could make that, but it's yummy. Steamed veggies are the way to go.
Also, I don't know if you can have these, but True North makes really good nut crackers (sounds weird, but the cranberry ones are yummy-it's like Christmas!) that I really like as snacks at work.
Susan Hollaway December 9th, 2009 1:31 pm
You might try juicing. But if you can't have any fruit, it might not be so palatable. Steamed broccoli, carrots (can you have carrots?), and cauliflower are good together. Try salad with lots of different kinds of lettuce. They actually have different tastes. Then throw in different fresh veggies to shake things up a bit to make them different. But I hear what you're saying ….. boring! Why is it that some things that taste SO good are SO bad for us? Bummer!
Merrie Destefano December 9th, 2009 3:07 pm
I can totally relate to what you're going through. I had to go on this diet too, and really should be on it all the time. About 10 years ago I gave up sugar. Ouch. And white flour. Big Ouch. But I never could bring myself to eat avocado or broccoli–which were on my "eat these" list. The yeast and vinegar were easier. Lemon was a good substitute for vinegar and I like flat bread. Eventually I was able to eat flour again, but never went back to sugar. You will feel better after you're been on it for 30 days. I'll be praying for you, Jenny!
Hannah December 9th, 2009 3:21 pm
Ah, groan! I know what you mean. Couldn't your doctor have had a little grace and waited until January? That's when all diets reach their heights anyway.
Avocados are good — as long as you can spread them on a steak, or salmon, or the like. I loooove sweet potatoes; home made SP fries are good. I have a thing for squash sauteed in olive oil with garlic. Major yum. And baked onions are good if you have something with it. (Meat'll work.) Will be praying for you!
lorilie December 9th, 2009 8:15 pm
Its not the whole food thing that bothers me so much… ok it does… well for me its the excerising of a get-fit sorta thing.
well i read just between you and me.
i loved it. if i ever become a movie maker person- id make a movie of it, i'd be rich, you'd be rich….
but reality is, i dont think im going to be a movie maker person.
Heather aka Dynamic Uno December 9th, 2009 8:39 pm
Healthy food? Is that some new fangled thing? Okay, so I actually like lima beans. (Of course they're better with tons of butter and some pepper on 'em, but that may not be an option for you.) Good luck and may the force be with you.
Caroline December 9th, 2009 8:46 pm
Yuck! Healthy food for 30 days!!??!! I'm so sorry!!! I have a diabetic friend in my class at school and we made food for math class (like to study fractions) and this is what I made: Chicken Tortilla Roll-Ups
-1 package light cream cheese,softened
-1/4 cup light mayo (I don't like the mayonaise but you may)
– 2 tablespoons mustard (optional)
– 1/2 teaspoon black pepper
– 6 flour tortialls
– 2 cups finely chopped cooked chicken
– 1 1/2 cups shredded or finely chopped carrot
– 1 1/2 cups finely chopped green bell pepper
1. Combine cream cheese, mayo, mustard and black pepper in bowl; stir until blended
2. Spread cream cheese mixture evenly onto each tortilla leaving 1/2 inch border. Divide chicken, if desired, carrot and bell pepper evenly over cream cheese leaving 1 1/2 inch border on cream cheese mixture at one end of each tortilla.
3. Roll up each tortilla jelly-roll style. Refrigerate until served. Cut each roll into 1 1/2 inch thick slices.
Amy December 10th, 2009 6:34 pm
Oh, Jen, I'll be praying for you as you make this 30-day transition.
Cara December 11th, 2009 10:08 pm
Wow, that's harsh. Stay strong!
One of my favorite veggie dishes is cooking green beans with mushrooms and olives. SO GOOD. Also, grilled asparagus, with a little olive oil, salt, and pepper, is so much better than steamed! Tons of flavor in it
Sam Harris December 12th, 2009 11:52 am
Carrots. Thats about the only veggie I like. Also I like pickled Okra, but I doubt that with out the pickle juice they'd be very good. 😛
I feel really bad for you. I had a ginger bread party last night at my house and one of my friends need to drop a pound and a half by the next morning (for his weight to be in the right "class" or whatever you call it for wrestling) so he wasnt able to eat any of the sweet treats surrounding him. It was absolutely so sad to watch. :'( I on the other hand had so much junk that I now want to run the length of my 2 mile neighborhood. OK. No I don't. I just like to think that I could. Mk, I am incredibly sorry for you Jenny, But there is a lot of healthy and yummy foods out there! Do not give up! You can do it! Resist the temptation!
REMEMBER: Luke 1:37 "For nothing is impossible with God." Prayer will be a giant help to you throughout this troubling time my friend. 😉
Stay strong Jen! Stay strong!
WordVixen December 16th, 2009 12:07 am
If I'm right in thinking that he mainly wants you off carbs, and that actual calorie/sodium/fat isn't the issue, then there are a few things you can do.
I cook chicken breast in a pan with about 1/4-1/2″ water in the bottom, and cover the pan. When it's cooked, pour out the water and add some red Sofrito. It's high in sodium, but nummy. You can also cook chicken in cream of mushroom soup, or golden mushroom soup, though I think they both use flour to thicken…
Also, season steak (a good cut) with Montreal Steak Seasoning, and cook it in a frying pan on the stove, make some home made sweet potato fries (I love them too- and agree that smothering them in sweet stuff actually ruins it), and maybe some fresh cooked green beans.
I cook green beans, baby carrots, and/or asparagus all the same way. About 1/4″ water in the bottom of a sauce pan, salt and pepper the water, add the veggies, cover and cook on medium until the color brightens (greens will get greener, carrots more orangey), then remove the lid and turn the heat up to high. Hover over the pan, and JUST as the water finishes evaporating, throw in a pat or two of butter, cover, toss, and remove the cover again (otherwise the steam will build up and they'll end up watery again).
Also, you can fry parsnips like you would sweet potatoes, but since they're shaped like carrots, they're a little awkward to slice that way. You COULD actually take a potato peeler and peel the whole thing and fry the peelings sort of like chips.
Tana December 18th, 2009 1:16 pm
I'll take whatever I can get if it means getting my name in a book.
snicker 😉
anyway, a yummy (yes, suprisingly yummy) healthy food is SMOOOOOTHIES. Basically just a bunch fruit and juice, some water and yougurt. you can add a couple baby-peeled carrots and spinach, those two things are tasteless and de-lish. trust me, my picky-twinkie-lover brothers actually LIKE these smoothies. course i prefer sugary slushies, but those are kinda rare here in Healthy-Food-Land.
ttyl and xoxo


text:
1 EDI Source Announces Date for Second User Conference
The 1 Conference 2014 is slated for August 3-6 in Orlando, Fla. and will include multiple keynotes, EDI software training, workshops and sessions on industry trends.
Cleveland, Ohio (PRWEB) December 17, 2013
1 EDI Source, Inc., the leading provider of electronic data interchange (EDI) software and Software-as-a-Service (SaaS) solutions, today announces its second user conference, The 1 Conference 2014, will be held August 3-6, 2014 at the Renaissance Sea World in Orlando, Fla.
Nearly 100 attendees joined 1 EDI Source in Florida for its first annual user conference which featured both introductory and advanced EDI software workshops, one-on-one guidance and support, and EDI mapping training sessions. The conference also included product roadmap discussions, networking opportunities and a planning session to launch the company's very first user group. Sponsors of the event included Commport Communications, DadeSystems, Exact Macola, Exact JobBoss and McAna EDI.
"We were absolutely blown away by the response we received for our first annual conference," said Tera Mitter, director of sales. "We thank our users, partners and staff who willingly shared their ideas to help us continue to offer industry-leading EDI software solutions. I am proud to say that the very first 1 EDI Source User Group was born from the innovation, energy and commitment of all who attended the event. I am excited to see the positive changes that come from The 1 Conference 2014!"
After the success of the first annual user conference, The 1 Conference is returning to sunny Florida August 3-6, 2014. The event will once again feature presentations from EDI software users, partners and 1 EDI Source staff, and offer a unique and balanced insight on industry trends from both user and vendor perspectives.
With representatives from 1 EDI Source's development, implementation, support, sales and management teams, The 1 Conference 2014 will also offer an excellent forum to share experiences and explore the latest on the benefits of EDI software and how to make the most of 1 EDI Source products. A formal EDI training workshop will also be held in Florida on August 7-8.
Please contact Bess Matuszewski, events marketing manager, 1 EDI Source at bmatuszewski(at)1edisource(dot)com for more information about The 1 Conference 2014.
About 1 EDI Source, Inc.
1 EDI Source, Inc. is the leading provider of EDI software and Software-as-a-Service (SaaS) solutions. For more than 20 years, the company has served the needs of businesses ranging in size from single-person operations to Fortune 500 corporations. Clients spanning various industries including health care, manufacturing, transportation and retail rely on 1 EDI Source for proven, easy-to-use software, cloud-based solutions, data mapping applications, and comprehensive consulting and outsourcing services. Visit http://www.1edisource.com for more information.
For the original version on PRWeb visit: http://www.prweb.com/releases/1EDISource/The-1-Conference-2014/prweb11428891.htm