text:
A method of starting up a system clock that has been generated by a phase-locked loop, and circuitry for accomplishing that method. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks.
1. A method of starting a local clock signal in a digital computer system having a master clock signal, comprising the steps of:
receiving the master clock signal;
driving the input of a phase-locked loop with said received master clock signal, said phase-locked loop including a voltage controlled oscillator and a phase comparator;
driving the input of an output buffer with the output of said voltage controlled oscillator;
detecting when said phase-locked loop has locked onto said received master clock signal; and
enabling said output buffer in response to detecting when said phase-locked loop has locked onto said received master clock signal.
2. The method of claim 1, wherein said phase-locked loop is a frequency multiplier.
3. The method of claim 1, further comprising the steps of:
dividing the output of said voltage controlled oscillator;
driving the input of a second output buffer with said divided output of said voltage controlled oscillator; and
enabling said second output buffer in response to detecting when said phase-locked loop has locked onto said received master system clock signal.
4. The method of claim 1, wherein said step of detecting when said phase-locked loop has locked onto the master clock signal includes the step of monitoring instantaneous lock indications for a predetermined period of time before determining the locked condition.
5. An apparatus for providing a local system clock in a digital computer system having a master clock signal, comprising:
a phase-locked loop including a voltage controlled oscillator having a clock signal output and an input for receiving a phase difference signal for controlling oscillation frequency; a phase detector having an input for connection to the master clock signal, an input for receiving a reference signal, and a phase difference output signal provided to said voltage controlled oscillator; and means for feeding back said voltage controlled oscillator clock signal output to said phase detector reference signal input;
a lock indicator connected to said phase detector phase difference output and having a lock output, wherein said lock indicator drives said lock output active when said phase-locked loop is locked onto said master clock signal as indicated by said phase difference output; and
an output buffer having an input connected to said voltage controlled oscillator clock signal output, an output for providing the local system clock and an enable input connected to said lock output to drive said input to said output when said lock output is active.
6. The apparatus of claim 5, wherein said lock indicator further includes a delay circuit which monitors said phase difference output and provides said lock output only after said phase detection output has indicated a locked condition for greater than a predetermined interval.
7. The apparatus of claim 5 wherein said phase-locked loop is a frequency multiplier.
8. The apparatus of claim 6 wherein said delay circuit includes a counter.
1. Field of the Invention
The invention relates to computer clocking systems, and more particularly, to methods of starting up computer clocking systems that use phase-locked loops to generate local system clock signals from master clock signals. The invention further relates to devices for realizing such methods.
2. Description of the Related Art
In efforts to realize greater computing power, microprocessor developers have continuously pushed the clock speeds ever higher. As few as ten years ago, microprocessor clock frequencies of 16 MHz were rare. Today, one sees microprocessors running at frequencies of 50 MHz and even higher.
With these higher clock frequencies have come concurrent problems. Distribution of a 50 MHz clock to the various components of a digital computer system can present difficulties associated with electromagnetic interference (EMI), clock skew, and reflections of the higher harmonics of the system clock signal. Transmission of high frequency clock signals over connectors to companion boards exacerbates these problems.
Developers have sought creative solutions to these problems. One approach has been to rely on a lower frequency system clock, and then generate, on the microprocessor or peripheral chip itself, a higher frequency clock signal from that lower frequency system clock. A number of current microprocessors and peripheral chips implement such a technique, for example, the 80486DX2 by Intel Corporation. This technique has the advantage of increasing a chip's internal processing rate without requiring a corresponding increase in system clock frequency, thus avoiding the problems associated with those higher clock rates.
To generate these higher frequency internal clock signals, these chips typically use a phase-locked loop (PLL) configured as a frequency multiplier. A block diagram of such a frequency multiplier circuit is shown in FIG. 1. As is shown, a phase detector (or phase comparator) drives, through a filter, a voltage controlled oscillator (VCO). The output of that VCO, which becomes the output signal, is then divided by the desired multiplication factor, and then the phase detector compares that divided reference signal with the input signal. This feedback arrangement compensates for shifts in the phase and frequency of the input signal by a level shift to the VCO, and the output signal is thus synchronized to the input signal. Examples of PLLs that can be configured as frequency multipliers include the CD4046A by RCA Corporation and the 74LS297.
The phase detector has two main purposes. First, it forces the VCO to shift frequencies when the reference signal and the input signal are of different frequencies. Second, it forces slight corrections to the VCO output when the reference and input signals are of the same frequency but are slightly out of phase. Both of these functions are accomplished by adjusting the frequency of the VCO; it is simply a difference of the magnitude of the adjustment.
A lock-in detection circuit can also use the output of the phase detector to determine when the PLL is locked onto the input signal. Phase-locked loops and lock-in detectors are well known to those skilled in the art of electronics design. Further information can be found in "The RCA COS/MOS Phase-Locked-Loop: A Versatile Building Block for Micro-Power Digital and Analog Applications." in: RCA COS/MOS Integrated Circuits (1978), pp. 598-601, which is incorporated herein by reference.
A PLL, however, has certain characteristics that can cause their own problems. Before an input signal is applied to a PLL, its VCO runs unrestricted at a frequency known as the free running frequency. The free running frequency is typically much higher than the frequency at which the PLL will ultimately lock. In fact, the signal initially output by the unlocked PLL may be higher than what would be allowed by the system in which the PLL is to be used. Thus, at system startup, any circuit using a PLL must take this free running frequency into account.
Further, when an input signal is first provided to a PLL, the reference signal does not instantaneously lock onto that input signal. A delay known as the capture time must pass before the PLL locks. The exact length of this delay is variable, but typically the output signal will become stable after a certain maximum delay.
Microprocessors and their support chips typically have minimum and maximum allowable clock input frequencies. Driving these chips at clock frequencies outside their specifications is not only logically unpredictable, but can also physically damage these devices. Thus, if a microprocessor is rated for a 50 MHz clock rate, driving that microprocessor at 100 MHz, for example, could destroy the microprocessor. In integrated circuits using CMOS and related technology, power consumption, and thus thermal heating, is proportionally related to the clock frequency. Thermal breakdown can thus be a failure mode for driving a chip beyond its rated clock frequency.
Another problem with PLLs is that as they attempt to lock onto the input signal, their output signals can change rapidly. Many microprocessors and peripheral devices cannot accommodate such rapid fluctuations of input clock frequencies. For example, using the Intel 80486-50, the maximum allowable fluctuation in clock period for adjacent clock cycles is 0.1%, or 20 picoseconds.
So, if a PLL is used to generate a system clock, it would be desirable to prevent such a circuit from outputting a clock signal of a frequency that is outside the rated parameters of the integrated circuits that will be driven by this generated clock. Further, it would be desirable for such a circuit to avoid outputting a clock signal whose frequency is rapidly changing. Such techniques would be particularly important when the system is first started up.
The method of clock startup according to the invention uses a relatively low frequency master clock signal that is distributed to various boards of a digital computer system. A number of identical clock generation integrated circuits, constructed according to the principles of the invention, then generate the local clock signals needed by the various components of the digital computer system. These clock generation chips are typically located near those components that require the higher frequency clocks.
The clock generation chips use PLLs to generate the local clock signals. The PLLs can be configured as frequency multipliers, in which case the frequencies of the local clock signals will be a multiple of the master clock frequency. These PLLs generate the highest required frequency clocks, and then dividers generate other, lower speed, required clock signals from that high frequency clock signal. These various clock signals are then driven to the various components that need them.
At startup, the output of the PLL will be at the VCO's free running frequency. This free running frequency and the correspondingly generated clocks may be of higher frequencies than allowed by the various components of the system. Further, as the PLL locks in, the VCO output may change frequency at a rate greater than that allowed by the various components.
To prevent such high frequency and unstable signals from being driven to these components, the clock generation chips disable their clock outputs until the PLL has locked onto the master clock signal. These chips accomplish this by connecting a counter in a lock indicator circuit to the output of the phase detector in the PLL. While the PLL is unlocked, the phase detector indicates an unlocked or out-of-phase condition, so the counter is reset. When the PLL locks, the phase detector so indicates, and the counter starts running.
When the counter reaches a certain predetermined count, the lock indicator circuit enables the clock outputs of the clock generation chip. The counter thus enables these outputs a predetermined delay after the phase detector indicates that the PLL is locked in. This ensures that the output signal is locked in and stable before the clock outputs are enabled to the various devices, thus preventing those devices from trying to lock onto exceedingly high or unstable clock signals.
A better understanding of the present invention may be obtained when the detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:
FIG. 1 is a prior art block diagram of a phase-locked loop configured as a frequency multiplier.
FIG. 2 is a block diagram showing the elements of a phase-locked loop based clock generation circuit along with its startup elements according to the invention.
FIG. 3 is a block diagram showing an alternative embodiment to FIG. 2.
FIG. 4 is a timing diagram showing typical signals generated by a circuit built according to the block diagram in FIG. 2.
FIG. 5 is a schematic of a typical delay circuit used in the lock indicator of a circuit built according to the block diagram in FIG. 2.
FIG. 6 is a schematic of a typical digital phase detector used in a circuit built according to the block diagram in FIG. 2.
FIG. 7 is a combination schematic and block diagram of an integrated circuit constructed according to the invention used to generate high frequency local clocks from a master clock signal.
FIG. 8 is a schematic showing typical external circuitry used to drive the integrated circuit of FIG. 6.
FIG. 9 is a schematic and block diagram showing a number of integrated circuits as shown in FIG. 6 used in a system to generate high frequency local clock signals from a lower frequency master clock signal according to the invention.
Turning to the drawings, FIG. 2 shows a block diagram of the circuit elements of an integrated circuit constructed according to the invention. The diagram in FIG. 2 shows PLL circuitry 6 and output circuitry 8.
As an input, the signal CLKIN is provided as a master clock signal. The frequency of CLKIN is of course arbitrary, but in this embodiment is 12.5 MHz. CLKIN will typically be a square wave, but could be any periodic signal that can drive a PLL, such as a sine wave. A sine wave would typically be first passed through a buffer to convert it into a square wave.
The signal CLKIN is provided to a phase detector 10. The phase detector 10 can be constructed in a variety of ways; the circuit used in this embodiment is described later in the discussion of FIG. 5. In this embodiment, the phase detector 10 provides two signals, UP* and DOWN*. The signals UP* and DOWN* are filtered through a low pass filter 12, and then driven into an amplifier 14. The amplifier 14 provides a control voltage VD to a voltage controlled oscillator (VCO) 16, which generates a square wave signal VO. VO is then divided by a divider 18. The divider 18 can conceivably divide VO by any integral value, but in this embodiment divides the signal VO by four. This divided signal then becomes the reference signal VREF, which is fed back as a reference input signal into the phase detector 10.
In operation, the phase detector 10, low pass filter 12, amplifier 14, VCO 16, and divider 18 form a PLL configured for frequency multiplication. When the PLL is locked, the output signal VO is in phase with CLKIN, and is an integral multiple of the frequency of CLKIN. In this embodiment VO is a 50 MHz square wave, as CLKIN is a 12.5 MHz signal.
Also associated with the PLL circuitry 6 is a lock indicator 19. The lock indicator 19 is driven by the UP* and DOWN* signals from the phase detector 10, and is described later in the discussion of FIG. 6. When the lock indicator 19 determines that the phase detector 10 indicates that the PLL circuitry 6 is locked onto CLKIN, the lock indicator 19 delays for an arbitrary amount of time and then asserts an active high lock indication signal LOCK. This delay ensures that the PLL circuitry 6 has locked in on CLKIN, that CLKIN is stable, and that the PLL circuitry is stable. When the lock indicator 19 asserts LOCK true, or high, the output circuitry 8 becomes active. At all times, VO drives the inputs of high frequency output buffers 20 and 22. The high frequency output buffers 20 and 22 are tri-state buffers and are disabled and enabled by the signal LOCK. When LOCK is asserted high, the high frequency output buffers 20 and 22 are switched from a tri-state condition to an enabled condition. The high frequency output buffers 20 and 22 are then driving the signal VO as their output signal PCLK. Of course, as few or as many output buffers as desired can be added to this design.
The signal VO is also divided by the output divider 24. This is a divide-by-two divider, and can be a flip-flop, for example. The output divider 24 provides a divided output signal VO/2, which is input to low frequency output buffers 26 and 28, which are also tri-state buffers. These buffers 26 and 28 are enabled and disabled by LOCK in the same way as the high frequency output buffers 20 and 22.
FIG. 3 shows an alternative embodiment of the block diagram of FIG. 2. FIG. 3 shows two principal differences from the previous diagram. First, high frequency AND gates 30 and 32 and low frequency AND gates 34 and 36 replace the high frequency output buffers 20 and 22 and the low frequency output buffers 6 and 28 of FIG. 2. The lock indicator 16 provides LOCK as one input to these AND gates 30, 32, 34 and 36, and thus when LOCK is low, the outputs of the AND gates 30, 32, 34 and 36 are low. When LOCK is high, the PCLK signal output from the high frequency AND gate outputs 30 and 32 tracks the signal VO, and thus is 50 MHz. Similarly, when LOCK is high, the HCLK signal out of the low frequency AND gate outputs 34 and 36 tracks VO/2, and thus is 25 MHz.
The second difference between FIG. 3 and FIG. 2 is that the signal VO/2, rather than the signal VO, is provided to the divider 18. This allows the lower frequency signal HCLK to be synchronized with the rising edge of CLKIN. In this configuration, the divider 18 divides by two rather than four, so that VREF is 12.5 MHz when VO is 50 MHz.
Of course one skilled in the art would recognize other ways to implement the outputs and the feedback in the PLL circuitry 6 and the output circuitry 8.
FIG. 4 shows a timing diagram of the various signals associated with the block diagram of FIG. 2. This timing diagram is divided into four distinct time periods: a power-on period 100, an acquisition period 102, a delay period 104, and a lock period 106. During the power-on period 100, the signal CLKIN has not yet been provided by the external circuitry, but power has been supplied to the system. At this point, the signal VO runs at the free running frequency of the VCO 16. In this embodiment, that frequency is approximately 200 MHz. As VREF is VO divided by four, VREF will be running at approximately 50 MHz. LOCK is low and thus disables the high frequency output drivers 20 and 22 and the low frequency output drivers 26 and 28. As these drivers respectively provide the signals PCLK and HCLK, those signals are kept at a tri-state level (here shown low, as being pulled down by external circuitry, for example parallel termination).
During the acquisition period 102, CLKIN is being provided by the external system. Here, CLKIN is a 12.5 MHz clock. When CLKIN is provided, the PLL circuitry 6 attempts to lock onto the CLKIN signal. This is shown as occurring in one and one-half cycles of CLKIN, but in actual practice this lock-in can take more or less time. During the acquisition period 102, VREF slows from its initial rate of 50 MHz to 12.5 MHz and VO slows from its initial rate of 200 MHz to 50 MHz. At the end of the acquisition period 102, the phase detector 10 indicates to the lock indicator 19 that the PLL circuitry 6 is locked-in.
The lock indicator 19 then provides a delay shown as the delay period 104. This is an arbitrary length of time, but for this embodiment is 10 milliseconds. If the phase detector 10 indicates for 10 milliseconds that lock-in has been maintained, then the PLL circuitry 6 and the master clock signal CLKIN should be stable. If, during the delay period 104, the phase detector 10 at any time indicates that the PLL circuitry 6 has gone out of lock, then the lock indicator 19 resets and begins a new 10 millisecond period.
After the delay period 104, the system enters the lock period 106. The lock indicator 19 asserts the signal LOCK, and that signal then enables the high frequency output buffers 20 and 22, which then provide the 50 MHz signal VO as PCLK, and enables the low frequency output buffers 26 and 28, which then provide the 25 MHz signal VO/2 as HCLK. VREF is then running synchronized to CLKIN at 12.5 MHz.
If the LOCK signal were not provided to enable and disable the high frequency output buffers 20 and 22 and the low frequency output buffers 26 and 28, then those signals would run from the time the system was turned on. In that case, the high frequency output buffers 20 and 22 would initially output a 200 MHz signal as PCLK, and the low frequency output buffers 26 and 28 would output a 100 MHz signal HCLK. As will be later described, these signals can be provided to a microprocessor and its peripheral components, and these signals could be outside the specified running clock frequencies for those microprocessors and components.
FIG. 5 shows a schematic for the phase detector 10 as used in this embodiment. A variety of circuits could be used, but the particular circuit shown in FIG. 5 has the advantages of not being dependent upon the duty cycles of CLKIN and VREF, and the advantage of providing for a very small phase shift between CLKIN and VREF. In the circuit of FIG. 5, CLKIN and VREF are provided as input signals to digital phase detection circuitry 200, which provides, through inverters 202, 204, 206 and 208, the output signals UP* and DOWN*. When the frequency of CLKIN is greater than the frequency of VREF, UP* goes continuously low, or true. Conversely, when the frequency of CLKIN is less than the frequency of VREF, DOWN* goes continuously low, or true. If the frequencies of CLKIN and VREF are the same, but CLKIN lags VREF, then DOWN* is maintained low for a time corresponding to the phase difference. Conversely, if CLKIN leads VREF, then UP* is maintained low for a period corresponding to the phase difference.
An OUT signal is used to drive the low pass filter 12. OUT can be generated by a push-pull pair of MOSFETs. The gate of a p-channel MOSFET 210 is driven by the UP* signal, while its source is connected to Vdd. The gate of an n-channel MOSFET 212 is driven by the DOWN signal, while its source is connected to ground. The drains of both MOSFETS 210 and 212 are tied together, and provide the signal OUT. When UP* goes low, a p-channel MOSFET 210 turns on, driving OUT to Vdd. When DOWN goes high, the n-channel MOSFET 212 turns on, driving OUT to ground. When neither UP nor DOWN is true, OUT is in a high impedance state. Other circuits could be used to convert the two DOWN* and UP* signals to the single OUT signal. OUT is filtered through the low-pass filter 12 and the resulting filtered signal driven into the amplifier 14. The amplified signal then adjusts the VCO 16 to maintain VREF and CLKIN at the same frequency and phase.
FIG. 6 shows a schematic of the circuitry used to implement the lock indicator 19. As inputs, FIG. 6 uses the signals UP* and DOWN* provided by the phase detector 10, as shown in FIG. 5. When UP* goes low, or true, a high signal goes to one input of a NAND gate 300 via an inverter 301 and the active low UP* signal also goes through a series of inverters 302. The series of inverters 302 functions as a delay line to the NAND gate 300 so that very narrow UP* signal pulses are filtered. These pulses are those generated by the phase detector 10 in normal operation to adjust for slight drifts in the phase of VREF. Thus, only when UP* goes low for a period of time long enough for that low signal to traverse the series of inverters 302 will the output of the NAND gate 300 go low, or true. The DOWN* signal uses corresponding circuitry. When the output of the NAND gate 300 goes low, that indicates that the PLL is no longer in lock. So, the output of a second NAND gate 304, which receives the outputs of the NAND gate 300 and the corresponding NAND gate 303 in the DOWN* circuitry, correspondingly goes high. The output of the NAND gate 304 is the UNLOCKED signal, which is provided to an inverter 305 and one input of a NAND gate 307. The inverter 305 has its output connected to the inverted clear input of a counter 306. The second input of the NAND gate 307 is connected to the output of an inverter 309, which receives the POWR or power-on reset signal at its input. This signal stays high until Vdd rises to an arbitrary voltage level, here being 2.0 volts. The output of the NAND gate 307 is connected to the inverted clear input of a flip-flop 308. So when the output of NAND gate 304 is high, the counter 306 is cleared and the flip-flop 308 is cleared after the reset period.
When UP* and DOWN* are once again both high, and thus the PLL is locked, then the NAND gate 304 output is low, and the counter 306 begins counting. The clock for the counter 306 is VO/2, which runs at 25 MHz. The counter 306 has 18 stages going into a series of 9 two input NAND gates 310. When all 18 lines of the counter 306 are true, the series of NAND gates 310 outputs are all low. The output of one NAND gate 310 is inverted by an inverter 312 and provided as one input to a NAND gate 320. The outputs of three NAND gates 310 are provided to the inputs of a NOR gate 314, whose output is connected to the NAND gate 320. The outputs of three more NAND gates 310 are provided to the inputs of a NOR gate 316, whose output is also connected to NAND gate 320. The final two NAND gates 310 are connected to inputs of a NOR gate 318. The third input of the NOR gate 318 receives the UNLOCKED signal from the NAND gate 304. The output of the NOR gate 318 is the final input to the NAND gate 320. The output of the NAND gate 320 is inverted by an inverter 322, whose output is connected to the clock input of the flip-flop 308. The D input of the flip-flop 308 is connected to a logic high level. The noninverted and inverted outputs of the flip-flop 308 are the LOCK and LOCK* signals, respectively.
As the counter 306 counts up and all the outputs are true and the PLL is still locked, the flip-flop 308 is clocked and the LOCK signal goes true. If lock is lost for greater than a minimal period, then the counter 306 and the flip-flop 308 are cleared and the LOCK signal goes false. The counter 306 thus provides a lock delay period of approximately 10 milliseconds.
FIG. 7 shows a schematic of portions of the internal circuitry of an integrated circuit actually implemented according to the invention. Shown are the phase detector 10, the low-pass filter 12, the VCO 16, the divider 18, the lock indicator 19, and the output divider 24.
Also shown are the high frequency output buffers 20 and 22 and the low frequency output buffers 26 and 28. The enables for the high frequency output buffers 20 and 22 are driven by the signal PTRI*. Similarly, the enables for the low frequency output buffers 26 and 28 are driven by the signal HTRI*. These inputs are active high in the sense that the outputs are enabled when PTRI* and HTRI* are high and tri-stated when the signals PTRI* and HTRI* are low.
The divider 18 is shown, being made up of a first D flip-flop 400, an inverting output XOR gate 402, a second D flip-flop 404, and a driver 405. The first D flip-flop 400 has as its clock input the signal VO. The inverting output of the first D flip-flop 400 is tied to its D input. Thus, the signal out of the first D flip-flop 400 is VO/2. The noninverting output of the first D flip-flop 400 is connected to one input of the inverting output XOR gate 402. The other input is connected to the noninverting output of the second D flip-flop 404. The output of the inverting output XOR gate 402 is connected to the D input of the second D flip-flop 404. The noninverting output of the second D flip-flop 404 is also connected to a driver 405. The output of the driver 405 is the signal VO/4 and becomes the reference input VREF of the phase detector 10.
In FIG. 7, an additional divider 406 is provided between the output of the VCO 16 and the line carrying the signal VO. Thus, for VO to be a 50 MHz signal, for example, the VCO 16 must generate VO times two, which is a 100 MHz signal.
The output of the additional divider 406 then becomes the signal VO and drives the high frequency output buffers 20 and 22, as well as additional high frequency buffers 412, through a NAND gate 410. The output of the additional divider 406 also drives the low frequency output buffers 26 and 28, as well as additional low frequency buffers 414, through the output divider 24, which here is a series of D flip-flops, one for each output. The output of the additional divider 406 drives the clock of each flip-flop making up the output divider 24. One inverting output of this series of D flip-flops making up the output divider 24 is tied to the D input of each flip-flop. The non-inverting outputs then are connected to the low frequency output buffers 26 and 28, as well as additional low frequency buffers 14.
Power-on reset circuitry 416 detects when Vdd goes on, and then drives an active high RESET signal to the reset input of the additional divider 406, an input of the NAND gate 410 through an inverter 418, the reset input of each D flip-flop making up the output divider 24, and the reset inputs of the first D flip-flop 400 and the second D flip-flop 404 in the divider 18. Finally, the lock indicator 19 provides the active high lock indication signal LOCK.
An integrated circuit constructed according to the invention as illustrated in the schematic of FIG. 7 is configured as shown in FIG. 8 when used in a digital computer system. Specifically, CLKIN is a 12.5 MHz system clock. The LOCK output feeds into the PTRI* and HTRI* inputs of the chip. When LOCK goes high, PTRI* is driven high, which enables the high frequency output buffers 20 and 22. Similarly, HTRI* is also asserted high, enabling the low frequency output buffers 26 and 28.
Finally, the FIL line, which is part of the low-pass filter 12, goes into an RC network consisting of a resistor 504 and a capacitor 506. This RC network assists in converting the digital OUT signal output by the phase detector 10 to an analog signal suitable for input to the VCO 16.
Finally, FIG. 9 shows how the integrated circuit constructed according to the invention as shown in FIG. 7 is used in a system. A master clock circuit 600 generates the 12.5 MHz system clock CLKIN. This clock is distributed to both an onboard clock generator chip 602 and an offboard clock generator chip 604, these chips being constructed according to the schematic and block diagram of FIG. 7. The offboard clock generator chip 604 is located on a separate board connected to the main system board by a connector 606.
The onboard clock generator chip 602 and the offboard clock generator chip 604 generate a 50 MHz clock signal PCLK and a 25 MHz clock signal HCLK. These signals are local clock signals for use by peripheral chips 608, 610, 612, 614 and 616. The generator chips 602 and 604 can be repeated as desired to provide local clock signals to other peripheral chips. Of course, according to the invention, these signals are tri-stated until the PLLs on the onboard clock generator chip 602 and the offboard clock generator chip 604 stabilize. FIG. 9 shows PCLK as being provided to peripheral chips 608 and 610, while HCLK is provided to peripheral chips 612, 614 and 616. Of course, the number of chips which require each frequency is arbitrary, and in fact one chip could receive both frequencies of clock signal.
The offboard clock generator chip 604 and onboard clock generator chip 602 are typically located physically near the chips that use their local clock signals. This prevents transmission line problems associated with transmitting high frequency clock signals over long traces. In a typical system, chips using the 50 MHz signal would include, for example, the 50 MHz 80486DX microprocessor and the 82495 cache controller, both by Intel Corporation. Examples of chips using the 25 MHz clock would be the 82490 cache SRAM, also by Intel. By delaying the provision of the PCLK and HCLK signals to these devices until the PLL in the clock generator chip 604 is stable, the devices do not receive a clock signal that is out of specification or rapidly changing. Thus the devices receive stable clocks and do not overheat.
This invention has been described in terms of particular embodiments. Obviously, modifications and alterations will be apparent to those skilled in the art in view of this disclosure. It is therefore intended that all such equipments, modifications, and variations fall within the spirit and scope of the invention as claimed.
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text:
Best Of Vince Gill
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This is a collection of best songs of Vince Gill. Install this app and enjoy beautiful music of Vince Gill. This app supports its developers by showing advertisement.
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subset: commoncrawl


text:
Coaching shakeup latest example of Cowboys dysfunction
"How 'bout them Cowboys!" has taken on a whole new meaning. As most of the football world is concentrating on the lead-up to the Super Bowl, the Cowboys are shaking...
or email email@example.com
Published: January 29, 2014 | 11:40am
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text:
15/16 Sport Calendar
Artificial Track:
Natural Track:
Member Section
Competitions Registration
Natural Track TV
FIL Media Guide 2014/2015
The FIL Luge Media Guide 2014/2015 can now be downloaded as a pdf file.
Click here to download
|Artificial Track News vom 08.07.13
|Nina Reithmayer with two torn ligaments
Innsbruck (pps) Despite two torn ligaments in her right ankle joint, Nina Reithmayer, 2010 Olympic silver medalist in Vancouver, will participate in a training camp of the Austrian Luge Federation (ÖRV) in Faak am See. According to the Austrian Federation the 29-year-old will have to wear a brace for three weeks.
Focal point of the training camp in Carinthia is the athletic training. The national red-white-red squad will stay at Faak am See until July 13.


text:
I am struggling through objects in perl, and am trying to create a 2d array and store it in a hash field of my object. I understand that to create a 2d array I need an array of references to arrays, but when I try to do it I get this error:
Type of arg 1 to push must be array (not hash element) The constructor works fine, and
set_seqs works fine, but my
create_matrix sub is throwing these errors.
Here is what I am doing:
sub new {
my ($class) = @_;
my $self = {};
$self->{seq1} = undef;
$self->{seq2} = undef;
$self->{matrix} = ();
bless($self, $class);
return $self;
sub set_seqs {
my $self = shift;
$self->{seq1} = shift;
$self->{seq2} = shift;
print $self->{seq1};
sub create_matrix {
my $self = shift;
$self->set_seqs(shift, shift);
#create the 2d array of scores
#to create a matrix:
#create a 2d array of length [lengthofseq1][lengthofseq2]
for (my $i = 0; $i < length($self->{seq1}) - 1; $i++) {
#push a new array reference onto the matrix
#this line generates the error
push(@$self->{matrix}, []);
Any idea of what I am doing wrong?


text:
DMV to Internet-less New Yorkers: Get in Line
By Jared Chausow
By Katie Toth
By Elizabeth Flock
City Hid Facts From Feds About Rikers
By Albert Samaha
Flood Wall Street Gets Pepper Sprayed and Arrested
By Anna Merlan
By Jon Campbell
Report Sheds Light on Anti-Muslim Bias
By Jon Campbell
Rikers Island Lawsuits Over Diabetic Care
By Albert Samaha
Now, sartorially at least, it's got one. Eschewing the drab threads of Jack Nicklaus-era geezers, younger PGA pros like Aaron Baadelely and Jesper Parnevik prefer their trousers the colors of Skittles, in prints too bold for even Old Navy's $5 bargain bin. Behold, the courageous golfer pant has returned. The most brazen among the pack of dandies is no doubt Ian Poulter, a veritable fashion vixen on the greens in tight Union Jack trousers or purple satin specials. He's game to rival David Beckham in loud sports hairdospairing a spikey Mohawk or multicolored coiffures with his color-coordinated visors.
Will this trend make it off the greens and onto the street, or at the very least, be subverted into Andre 3000's acid-golfer look?
Whatever. Men this bold deserve our undying respect.
Sports Illustrated, on golfer Aaron Baddeley's style: "It's not the guns on Aaron Baddeley, it's the clothes. His thick upper arms scream weight-room regular, while his retro outfits (lime-green slacks, white belt, white shoes) whisper 1970s dork. Ah, but when you're a young, blond hunk, you can pull off any look."
photo: Chris Condon/PGA TOUR/WireImage.com
Aaron Baddeley: "A friend of mine said to me 'my grandpa wants his pants back at the end of the week.' "
photo: Stan Badz/PGA TOUR/WireImage.com
Jesper Parnevik: "Golf has become a lot more rock n' roll than it was 10 years ago. It's cool to play golf now. People don't feel like they have to dress down. Alice Cooper plays."
photo: Stan Badz/PGA TOUR/WireImage.com
Parnevik wears orange here, but likes his pastels, too: "Three years ago [in 2000], when pink was in and I had a chance to win, I put on pink pants. I won the Byron Nelson and another tournament with themthey were my two-million-dollar pants."
photo: Al Messerschmidt/WireImage.com
Ian Poulter's loud pants (shown here) are matched only by his hairdos: "I've always sort of messed around with my hair. But I've only gone mad over the last couple of years, really. I like the way the visors sit on my head, and I just thought, wouldn't it be quite wacky to start putting some funky hairstyles together?"
photo: Stan Badz/PGA TOUR/WireImage.com
Ian Poulter: "You don't wear the colorful stuff on a Tuesday or Wednesday. You don't waste it. [That's for] Thursday-Friday and the weekend."
photo: Sam Greenwood/WireImage.com
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Fingerprint evidence
Identifying fingerprints may have a role not just in solving crimes but also in everyday life.
By Emily Sohn, 00:00 AM April 25, 2006
In May 2004, agents from the Federal Bureau of Investigation showed up at Brandon Mayfield's law office and arrested him in connection with the March 2004 bombing of a train station in Madrid, Spain. The Oregon lawyer was a suspect because several experts had matched one of his fingerprints to a print found near the scene of the terrorist attack.
But Mayfield was innocent. When the truth emerged 2 weeks later, he was released from jail. Still, Mayfield had suffered unnecessarily, and he's not...
Source URL: https://student.societyforscience.org/article/fingerprint-evidence


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Thoracoscopic surgery is a procedure that is done to see inside the
chest cavity and make surgical repairs. It is a less invasive surgical
technique than open-chest surgery or other similar procedures.
The surgeon makes one or more small incisions in the chest area and
places a special camera, called a thorascope, to see the area around the heart.
Guided by this camera, the surgeon inserts one or more surgical instruments
through the incisions and makes repairs where needed.
Thoracoscopic surgery usually results in a quicker recovery than
traditional open-chest surgery. But this type of surgery cannot be used to
repair many types of heart or lung problems.
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Honey-Glazed Pork Roast
Community Recipe from
Recipe Time
Cook Time:
Prep Time:
- 2 to 3 teaspoons smoked paprika or paprika
- 2 teaspoons coarse kosher salt
- 1 3- to 5-lb. bone-in pork roast, ribs removed and tied back on
- Fresh oregano sprigs
- 3 small red and/or yellow sweet peppers, stemmed, seeded, and quartered
- 1 small green pepper, stemmed, seeded, and quartered
- 1 tablespoon olive oil
- Salt and pepper
- 1/3 cup honey
- 1/4 cup lime juice
- Fresh oregano and/or thyme sprigs
- 1. Preheat oven to 350 degrees F. In a small bowl combine paprika and coarse salt.
- 2. Place pork in a shallow roasting pan, bone side down. Rub paprika mixture all over pork, pressing in lightly. Tuck sprigs of fresh oregano under the kitchen string tying the roast to the bone. Roast, uncovered, in the preheated oven for 20 to 25 minutes per pound (1 hour 10 minutes to 2 hours).
- 3. Meanwhile, place sweet pepper pieces on a baking sheet. Drizzle peppers with oil and sprinkle lightly with salt and pepper; toss to coat. Spread peppers evenly on baking sheet. Place in oven with pork the last 40 to 45 minutes of roasting until peppers are tender and begin to brown. When roast reaches 155 degrees F internal temperature, remove to a cutting board and cover with foil. Let stand 10 minutes.
- 4. While roast stands, in a small saucepan combine honey and lime juice. Bring to boiling, stirring occasionally. Boil gently, uncovered, for 2 minutes. Remove from heat and cool slightly. Season with salt and pepper.
- 5. Remove string from roast. Using tongs, turn roast on its side and pull bone away. Turn roast top-side up and slice. Serve with peppers, honey glaze, and fresh herbs. Makes 8 servings.
September 2011
This recipe is a personal recipe added by kateseats59 and has not been tested or endorsed by MyRecipes.
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No injuries reported after fire at Christus Spohn Hospital Memorial
CORPUS CHRISTI - Staff and patients were evacuated from a hospital Tuesday evening after a small fire broke out on the sixth floor.
Emergency responders arrived about 5:45 p.m. at Christus Spohn Hospital Memorial in the 2600 block of Hospital Boulevard to find smoke in a hallway and overhead sprinklers spraying, fire officials said.
No injuries were reported. Hospital staff relocated 11 adults and six teenage patients of the behavioral medicine unit to different floors, a hospital spokeswoman said.
Firefighters had flames out quickly and searched the floor for other fires. The blaze is believed to have originated in a linen basket, hospital officials said. The cause was unknown.
Hospital staff said they trained for a similar scenario with firefighters during the previous week.
"Fortunately, everything went very well," said Katy Kiser, hospital spokeswoman.
Patients will remain in new rooms until cleaning and repairs are completed, she said.
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In this issue:
- The Current State in Financial Services Cybersecurity
- Critical Infrastructure Executive Order
- Cybersecurity Legislation
- Financial Services Cybersecurity Infrastructure
- Cyberattack Overview
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- APT1 Attack Lifecycle Model
- Emerging Developments
- On the Agenda: What Financial Services Executives Should Be Discussing
- Reed Smith Cybersecurity Alerts and Blogs
- Excerpt from: Cyberattack Overview:
The Securities Industry and Financial Markets Association (SIFMA) is leading an exercise (Quantum Dawn 2) July 18, 2013, which is intended to replicate a large-scale assault on financial industry information systems and online sites. Financial institutions and government agencies will participate in order to evaluate coordination and decision-making among the participants. While this will support efforts to improve the response to a systemic attack, the threats to individual institutions and the industry come in many forms and from several directions.
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A Micro-Electro-Mechanical-Systems (MEMS) probe is fabricated on a substrate for use in a probe card. The probe has a bonding surface to be attached to an application platform of the probe card. The bonding surface is formed on a plane perpendicular to a surface of the substrate. An undercut is formed beneath the probe for detachment of the probe from the substrate.
1. A method comprising:
forming a probe on a substrate using Micro-Electro-Mechanical Systems (MEMS) processing techniques, the probe having a bonding surface to be attached to an application platform of a probe card, the bonding surface formed on a plane perpendicular to a surface of the substrate;
forming an undercut beneath the probe for detachment of the probe from the substrate;
detaching the probe from the substrate by breaking a joint located between a base portion of probe and an anchoring structure on the substrate, wherein detaching the probe from the substrate further comprises:
forming a sacrificial layer on the substrate;
forming the probe and the anchoring structure on the sacrificial layer; and
removing the sacrificial layer beneath the probe without completely removing the sacrificial layer beneath the anchoring structure.
2. The method of
3. The method of
4. The method of
a contact tip to form a contact with a device-under-test, the contact tip sandwiched between two conductive layers of the probe;
a probe body, which comprises:
a tip portion to support the contact tip;
a spring portion; and
the base portion to support the tip portion and the spring portion, the base portion having an exposed broken surface that is formed by detaching the probe with force from the substrate.
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
11. A method comprising:
forming a probe on a substrate using Micro-Electro-Mechanical Systems (MEMS) processing techniques, the probe having a bonding surface to be attached to an application platform of a probe card, the bonding surface formed on a plane perpendicular to a surface of the substrate;
forming an undercut beneath the probe for detachment of the probe from the substrate;
detaching the probe from the substrate by breaking a joint located between a base portion of probe and an anchoring structure on the substrate, wherein detaching the probe from the substrate further comprises:
forming a conductive layer on the substrate;
forming a sacrificial layer on the conductive layer, the sacrificial layer having an opening to expose the conductive layer;
forming the probe and the anchoring structure on the sacrificial layer, the anchoring structure having contact to the conductive layer through the opening; and
removing the sacrificial layer beneath the probe.
12. The method of
13. The method of
14. The method of
a contact tip to form a contact with a device-under-test, the contact tip sandwiched between two conductive layers of the probe;
a probe body, which comprises:
a tip portion to support the contact tip;
a spring portion; and
the base portion to support the tip portion and the spring portion, the base portion having an exposed broken surface that is formed by detaching the probe with force from the substrate.
15. The method of
16. The method of
17. The method of
18. The method of
19. The method of
20. The method of
At least one embodiment of the present invention pertains to Micro-Electro-Mechanical Systems (MEMS), and more particularly, to the formation of a MEMS probe.
Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common substrate, such as a silicon substrate, through microfabrication technology. While the electronics are fabricated using integrated circuit (IC) process sequences (e.g., CMOS, Bipolar, or BICMOS processes), the micromechanical components are fabricated using compatible "micromachining" processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.
A MEMS device includes small structures with dimensions in the micrometer scale (one millionth of a meter). Significant portions of the MEMS technology have been adopted from integrated circuit (IC) technology. For instance, similar to ICs, MEMS structures are, in general, realized in thin films of materials and patterned with photolithographic methods. Moreover, similar to ICs, MEMS structures are, in general, fabricated on a wafer by a sequence of deposition, lithography and etching.
With the increasing complexity of MEMS structures, the fabrication process of a MEMS device also becomes increasingly complex. For example, an array of MEMS probes may be assembled into a probe card. A probe card is an interface between an electronic test system and a semiconductor wafer under test. A probe card provides an electrical path between the test system and the circuitry on the wafer, thereby enabling the testing and validation of the circuitry at the wafer level, before the chips on the wafer are diced and packaged.
Conventionally, probes are fabricated on a single substrate that has multiple layers deep in the vertical direction (with respect to the surface of the substrate), using a sequence of deposition steps across an entire wafer. A concern with the conventional methodology is that a defect or contamination occurring in any deposition step and in any individual probe may cause the entire wafer to fail. Further, the designs of probe shapes are usually restricted by the conventional processes that deposit layers of probe materials in a direction along the longitudinal axis of the probe spring. These conventional processes create the vertical, multi-dimensional structure of a probe, using multiple lithographic steps to pile and connect every layer of probe materials. As a result, the final probe structure, including the probe spring, tends to have a jagged and uneven outline and lack smooth transitions among the layers. Thus, there is a need to improve the conventional fabrication process in order to increase the yield of MEMS probes, reduce the lead time and costs, and improve the design of the probes.
One or more embodiments of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
A technique for fabricating a Micro-Electro-Mechanical Systems (MEMS) probe on a substrate for use on another platform, such as a probe card, is described. In one embodiment, one or more probes are fabricated on a substrate using MEMS processing techniques. Each probe includes a contact tip and a probe body. The probe body further includes a tip portion, a spring portion and a base portion. The probe is formed in a "lying" position, which means that the probe body is lying on a plane parallel with the surface of the substrate. The probe is detached from the substrate by forming an undercut beneath the probe and breaking the base portion from an anchoring structure on the substrate. The probe is then attached to an application platform of a probe card. During the attachment process, the probe is lifted up to a "standing" position such that only the base portion of the probe body is attached to the application platform.
In one embodiment, a pick-and-place process is described. In a pick-and-place process, MEMS probes (or "probes") are individually detached ("picked") from a substrate, and then attached ("placed") to an application platform in an unpackaged state. This "pick-and-place" technique not only improves the yield of the probes, but also greatly increases the flexibility with respect to how the MEMS probes are fabricated and used. For example, the array of MEMS probes may be detached from the substrate concurrently, or one or more parts at a time. Each of the MEMS probes may be attached to the same or different application platforms. Further, the MEMS probes attached to the same application platform may be fabricated on the substrate in a first arrangement and then attached to the application platform in a second arrangement, where the first arrangement and the second arrangement may have different spacing between the MEMS probes, different orientations of the MEM probes, or a combination of both.
As MEMS probes are fabricated on a substrate different from the platform used for the final application, yield of the individual MEMS probes does not directly affect the yield of the final product. A selection process of acceptable MEMS probes may be performed before the MEMS probes are assembled on the probe cards. Defective MEMS probes may be discarded before the attachment process, or left on the substrate.
The term "MEMS probe" herein refers to a probe fabricated by MEMS technology. It is understood that the technique described herein can be applied to other MEMS parts (e.g., mechanical parts, optical parts, electrical parts, or the like). Typically, a MEMS part has dimensions ranging from 10�10�10 μm to 5000�5000�5000 μm. Examples of a MEMS part include a probe, a laser module, optical lenses, micro-gears, micro-resistors, micro-capacitors, micro-inductors, micro-diaphragms, micro-relays, micro-springs, waveguides, micro-grooves, and the like.
The term "substrate" herein refers to the substrate used in the probe fabrication process, without involvement in the operations of the probes and the probe card. Examples of a substrate for fabricating MEMS probes include, but are not limited to, ceramics, glasses, metal plates, plastic plates, and semiconductor (e.g., silicon (Si)) wafers. A non-silicon substrate, compared to a Si-based substrate, offers a larger number of standard sizes and is available as a thicker and non-circular standard substrate. Further, some non-silicon substrates are inert to most chemicals used during fabrication processes. Most substrates, including a Si-based substrate, can be processed with the MEMS parts thereon. Processed materials on the substrates can be later removed or dissolved without damaging the substrates. Therefore, the substrate for fabricating MEMS probes, as described herein, is a "reusable substrate," unless otherwise indicated. A reusable substrate can be reused for a next batch of MEMS probes fabrication after the MEMS probes are detached therefrom and residual substances are removed.
The term "application platform" herein refers to a part of a probe card which provides a platform to which the probes are attached, and electrically connects one or more (e.g., each) of the probes to a printed circuit board (PCB) that interfaces an electronic test system. An application platform may include, but is not limited to, semiconductor, glass, ceramics (e.g., low-temperature co-fired ceramics (LTCC), high-temperature co-fired ceramics (HTCC)), metal, other dielectric materials, organic materials, or any combinations of the above. In addition to MEMS probes, an application platform may include components such as electrical connection, electrical contact, electrical isolation, electrical grounding, integrated circuit (IC) module, application specific IC (ASIC) module, dielectric patterning, conducting opening definition, mechanical support, mechanical protection, thermal conduction, electrostatic discharge (ESD) protection, confinement for parts, and wire bonding pads.
It is understood that a probe card may include one or more MEMS probes fabricated from one or more reusable substrates. The MEMS probes attached to a probe card may be of different orientations, shapes, sizes and materials. The location of the probes on the probe card can be customized.
Referring to
Following the formation of blanket metal layer 12, a first sacrificial layer 23 is formed on metal blanket layer 12 (
Referring to
On substrate 11, probe 51 is formed in a "lying" position, which means that probe 51 is lying on a plane parallel with the surface of substrate 11.
In one embodiment, a thin metal film (e.g. gold) can be deposited at this point on the bonding surface 59 for the purpose of improving adhesion between probe base 58 to the surface of the application platform.
Frame 57 (also referred to as an "island" or an "anchoring structure") is used to anchor probe 51 to a fixed location on substrate 11. In a subsequent operation that removes first sacrificial layer 23 beneath probe 51, frame 57 becomes the only support for probe 51 to remain on substrate 11. In one embodiment, the surface area of frame 57 is greater than that of probe 51. Representatively, a surface area ratio of frame 57 to probe 51 ranges from 25:1 (or more) to 2:1 (or less). Theoretically, there is no upper bound on this surface area ratio. However, a large surface area ratio means a large frame 57 on substrate 11, and, therefore, less space for probes. Further, the surface area ratio may depend on the relative shapes of frame 57 and probe 51. For example, the surface area ratio may be greatly reduced (e.g., 5:1, 2:1, 1:1, or less) if frame 57 has a substantially round shape and probe 51 has a long and narrow shape. In some embodiments, a round-shaped frame 57 may have less surface area than a long and narrow probe 51. The surface area ratio may increase (e.g., greater than 1:1, 5:1, 7:1, 10:1 or greater) if both frame 57 and probe 51 have a substantially same shape. The surface area ratio and the relative shapes (of frame 57 and probe 51) contribute to the differential etching rates of first sacrificial layer 23 underneath probe 51 and frame 57, which is a feature that facilitates the detachment of probe 51, as will be described in detail later with reference to
Probe 51 (excluding tip base 34 and contact tip 45) and frame 57 may be formed by using a third lithographic patterned mold (not shown) that defines the shapes of probe 51 and frame 57. The third lithographic patterned mold is filled, by electrical forming, with a conductive material, such as a metal (e.g., nickel) or alloy. In some embodiments, the first, second and third lithographic patterned molds may be made of the same materials, such as photoresist, or different materials.
The third lithographic patterned mold also defines the shape of an anchoring joint 52 between probe base 58 and frame 57. Anchoring joint 52 is shaped to have deep V-cuts on both sides of the joint section that connects probe base 58 and frame 57. The cross-section of anchoring joint 52 (defined by a plane that cuts through the joint section of probe base 58 and frame 57) is a thin and narrow area. For example, anchoring joint 52 is shaped to have deep V-cuts on both sides, such that its cross-section has substantially the shape of a line, which extends along the thickness of the probe layer. As will be described in greater detail below with respect to
After the formation of probe 51, a planarization operation is performed on probe 51 to control the thickness of probe 51 (
After the planarization operation, second sacrificial layer 62 is stripped or dissolved. In one embodiment where second sacrificial layer 62 is made of the same material as first sacrificial layer 23, both of the first and second sacrificial layers 23, 62 can be selectively etched or dissolved from beneath probe 51. The selective removal creates an undercut 73 beneath probe 51 (
As mentioned above, a thin metal film (e.g., gold) can be deposited, before the planarization operation, on bonding surface 59 for the purpose of improving adhesion between probe base 58 to the surface of the application platform. In an alternative embodiment, the thin metal film may be deposited at this point instead of before the planarization operation.
After the creation of undercut 73, probe 51 is ready to be detached from frame 57 manually or with a machine. A lateral force (with respect to the surface of substrate 11) applied to probe 51 near anchoring joint 52 can separate probe 51 from frame 57 right at anchoring joint 52. Alternatively, an upward swing force can be applied to or near anchoring point 52 to separate probe 51 from frame 57. Yet another way of separating probe 51 from frame 57 is by laser cutting anchoring joint 52. Substrate 11 is left with frame 57 after all probes 51 are detached. Substrate 11 can be reused for fabrication of a next batch of probes by continuing etching or dissolving first sacrificial layer 23 until frame 57 is separated from substrate 11. Substrate 11 can then be reused with blanket metal layer 12 or the thin film at the bottom of blanket metal layer 12, which remain on substrate 11.
The detachment of probe 51 can be performed by external force at or near anchoring joint 52, with respect to the surface of substrate 11. The external force, either laterally or upward, or by laser cutting, physically breaks the narrow connection at anchoring joint 52. After the narrow connection is broken, a "broken" surface is formed on the side of probe base 58 that was previously connected to frame 57. This broken surface is distinguishable from a surface defined by conventional methods of probe formation that does not use external force to detach a probe from the substrate. In general, a surface formed by conventional methods is smooth and regularly shaped. A surface formed by forcibly breaking (such as the broken surface of probe base 58) is generally rough and substantially irregular. A person of ordinary skill in the art would be able to recognize this "signature" represented by the broken surface by examining the smoothness and shape of the surface. In a scenario where probe 51 is made of metal, the roughness and irregularity of a broken metal surface is visually discernable and distinguishable from a plated metal surface defined by photoresist or other sacrificial materials.
An alternative process to the one described in
Referring to
Spring portion 142 reacts with a buckling force to a pressure applied on tip portion 143. In one embodiment, spring portion 142 has a shape of a fraction of a circle or a deformed circle (e.g., a half circle, a half ellipse, a quarter ellipse, or a quarter circle), with one end extended to tip portion 143 and the other end anchored to base portion 141. Spring portion 142 can also be designed such that its width (shown as "W" in
The probe structure described herein is formed by at least three separate lithographic processes that form the tip base, the contact tip, and the rest of the probe body. The three lithographic processes allow the probe body to have thickness variations along its cross sections, wherein the thickness is measured in a direction perpendicular to the surface of substrate 11. For example, during the formation of the tip base, a metal or alloy material can be deposited in a recess section 150 of the probe body (
The base portion of a probe can vary in design to meet the requirements of different applications. For example, in
A person of ordinary skill in the art would appreciate that a desired buckling force can be produced by adjusting design factors such as probe height, probe thickness, stop position and stop gap (which is the gap or distance between stop 171 and spring portion of probe 170). Additional examples of probe springs include a buckling spring (
A scrubbing mark is generally characterized by the length and depth of the mark on the DUT. Referring again to
Thus, a technique for fabricating a MEMS probe on a substrate has been described. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Although the present invention has been described with reference to specific exemplary embodiments, it will be recognized that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.
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Melissa & Doug
Swivel Bridge Train Set 45 Pieces
- Color:
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Please select a size.
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Description: Toot toot? Here comes a really cool wooden railway set! Every engineer will take delight in the special features of this 45+ piece system.
- Includes ascending and descending track, track supports, a 3-car train, a covered bridge and a swivel bridge
- The traffic gates automatically open and close on the swivel bridge for extra fun!
- Compatible with popular wooden railway systems
- Measures:13" x 22¼" x 5" packaged
- Recommended for ages 3 and up
Material: Wood
Brand: Melissa & Doug
Origin: Imported


text:
Judgment call
Coincidence or not, references to the divine and religious that were made during deliberations of the Reproductive Health (RH) bill and last Sunday's shocker of a Manny Pacquiao knockout defeat are reinforced by today's date.
In the Mayan calendar, Dec. 12, 2012 or 12/12/12 is the date reckoned as the end of the world.
If that's true at all, it bodes ill for Catholics celebrating the feast of Our Lady of Guadalupe, patroness of Cebu and the unborn. And the Mayan calendar date would also spell doom for those in Congress wishing to vote for or against the RH bill.
Why the sudden mention of divine judgment and doomsday scenarios? Some Filipino Catholic leaders and their supporters saw special timing in the devastation wrought by typhoon Pablo on Dec. 4, saying this came to pass because of President Benigno Aquino III's appeal the week before for Congress allies to vote on the RH bill.
Let's not even get into Aling Dionesia's rant about her son's shift to the ranks of born-again Christians as the reason behind his ring loss, an accusation which Catholic Church leaders are wise to refuse to dignify. But if Pacquiao makes a last-minute change of mind and supports the RH bill, that would be a different story.
It's clear that the Catholic Church is moving heaven and earth to block passage of the RH bill. The endless phone calls, rallies, and forums, including today's reported plan for bishops and priests to visit Congress to witness the actual voting only underscore the importance placed in today's Congress session where the RH bill may be voted upon.
Is it a rationale and mature choice of strategy to use the typhoon season or some other natural calamity to make congressmen feel guilty about supporting the RH bill?
Would a pro-RH vote in Congress bill invite another typhoon, earthquake, or other disaster wrought as judgment from God?
Or if Climate Change throws the weather out of wack again, would members of Congress blame whatever calamities come our way on the the Mayan calendar's prediction for 12/12/12?
Whatever comes to pass today in Congress, we are reminded of another saying, this time from the heathen Romans, who declared that "let justice be done, though the heavens fall."
The RH bill debate has gone on long enough.
It's time for the Filipino people's chosen representatives in Congress to decide, as the President put it, once and for all, to vote on the measure.
Elected leaders will decide the fate of maternal care, population growth, the moral climate of generations of Filipinos, and the rest of the RH bill's full landscape of socio-political impacts, based on their grasp of issues and their individual conscience.
It's a decision borne of men, not the weather, superstition or the hand of God.
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text:
Author(s): Weyland, Kurt
ISBN 10: 0691134715. See all ISBN's
Publisher: Princeton University Press
This is an eTextbook Learn More
Why do very different countries often emulate the same policy model? Two years after Ronald Reagan's income-tax simplification of 1986, Brazil adopted a similar reform even though it threatened to exacerbate income disparity and jeopardize state revenues. And Chile's pension privatization of the early 1980s has spread throughout Latin America and beyond even though many poor countries that have privatized their social security systems, including Bolivia and El Salvador, lack some of the preconditions necessary to do so successfully.
In a major step beyond conventional rational-choice accounts of policy decision-making, this book demonstrates that bounded--not full--rationality drives the spread of innovations across countries. When seeking solutions to domestic problems, decision-makers often consider foreign models, sometimes promoted by development institutions like the World Bank. But, as Kurt Weyland argues, policymakers apply inferential shortcuts at the risk of distortions and biases. Through an in-depth analysis of pension and health reform in Bolivia, Brazil, Costa Rica, El Salvador, and Peru, Weyland demonstrates that decision-makers are captivated by neat, bold, cognitively available models. And rather than thoroughly assessing the costs and benefits of external models, they draw excessively firm conclusions from limited data and overextrapolate from spurts of success or failure. Indications of initial success can thus trigger an upsurge of policy diffusion.
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text: Richard Schofield, Publisher-photographer-hi | Lightstalkers Home Member Directory Calendar Groups Resources Publications You are not logged in. Click here to log in now. | Switch to our mobile site→ My Profile My Galleries My Networks Richard Schofield Profession: Publisher-photographer-hi Location: Vilnius , Lithuania Home base: Vilnius, Lithuania Email: •••••••• (private) Languages spoken: English, Lithuanian, tiny bit of Spanish Organization: Freelance Skype: mistersco Mobile phone: +370-6 813 82 58 Work phone .+370-5 212 29 76 Last login: about 3 years ago Member since: 19 Jul 2008 20:07 About Testimonials Subscribe via RSS→ Keywords mophone lithuania balkans furtive travel writer publisher More about sponsorship→ Search for in membersimagespostsrepliespublications searching… Discussion Assignments Events For Sale Gear Housing Tech Support Travel Other stuff Send invitations Member Directory Calendar Galleries Groups Publications Resources About Lightstalkers Manifesto Donations Corporate Sponsorship Official Gear Send this to: (email address) Translate into: 简体字 Deutsch 日本語 한국말 Français Italiano Português Español More about our partners→ Top↑ | RSS/XML | Privacy Statement | Terms of Use | email@example.com ©2004-2015 November Eleven


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on After Effects, Final Cut Pro, AVID and much more.
A blog by Premiumbeat
Posts Tagged 'Depth of Field'
Tips for Working With a Shallow Depth of Field
Give your video shots greater dimension! Follow these tips for shooting shallow depth of field.
Understanding Lenses: Aperture, F-Stops & T-Stops
Lens apertures may seem confusing but with a little practice you'll be an f-stop master.
Why Mastering Deep Depth Of Field Is Crucial For Becoming A Better DP
While DSLR technology has opened up a whole world of possibilities when it comes to capturing cinematic like images, it's also caused an overuse of extremely shallow DOF.
Smoke ConnectFX: Depth of Field Node
Adjust the focus and depth of your shots using Smoke's powerful Depth of Field node! Great for giving your footage or composites dynamic depth in post production.


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Blue Jays end nine-game skid, beat Red Sox 6-3
Jacoby Ellsbury gave the Red Sox a 1-0 lead in the second with an RBI double down the line in right but Rolen tied it with an RBI double in the third. Ellsbury restored Boston's lead with a run-scoring single in the fourth.
Toronto ended Wakefield's night with a five-run fifth, doing all its damage with two outs. Rolen started the rally with an RBI double over the head of Jason Bay in left, Kevin Millar walked, Lyle Overbay scored Rolen with a double to right, Barajas hit a two-run single and Marco Scutaro chased Wakefield with an RBI double over Ellsbury in center.
"I didn't have a clean inning today, which hurt," Wakefield said. "I got my pitch count up too high and then, in the fifth inning, I just couldn't make a pitch when I needed to."
J.D. Drew cut it to 6-3 with a solo homer to center in the seventh, his seventh.
Notes:@ Red Sox manager Terry Francona was feeling better Friday, a day after he was treated for high blood pressure following Boston's victory at Minnesota. Emergency personnel treated Francona in the clubhouse before the Red Sox left to catch their flight to Toronto. "The guy told me to relax," Francona said. "I said 'Are you (kidding) me? Do you watch this game?'" ... Boston OF Mark Kotsay (back) will play three more rehab games for Triple-A Pawtucket this weekend before being evaluated. ... Toronto voided its option on RHP Robert Ray (shoulder) and placed him on the 15-day disabled list. Ray was optioned to Triple-A last Friday. ... Toronto's Aaron Hill extended his hitting streak to 12 games with a first-inning single. ... Boston RHP Daniel Bard struck out five in 2 1-3 scoreless innings of relief.


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After Ferguson, one woman urges her fellow African immigrants to see themselves simply as black
Friday, August 22, 2014
The unrest this month in Ferguson, Mo., has many Americans thinking about where we are as a country when it comes to race. One Ethiopian-American writer is urging her fellow African immigrants to be "Ferguson strong" and identify closely with African Americans.
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"Second Chances" and its disturbing implications
View Single Post
August 26 2013, 11:56 AM
Re: "Second Chances" and its disturbing implications
T'Girl wrote:
If you take a starfish and either cut or rip it in half, the two halves will regrow a entire starfish, complete with any physical abnormalities the orginal starfish possessed. Identical in DNA too.
Okay but suppose fully sentient beings could regrow themselves like starfish, it might still be clear that one of the two "regrown" beings was actually a new duplicate being with a new consciousness while the other is a continuation of the "original" consciousness.
Consider this:
A person is sliced in half "horizontally" around the waist into two parts. The upper half person continues to function mentally and continues to maintain his consciousness. Meanwhile the lower half part, since not yet having a head/brain, is now unconscious. But it regrows the entire upper half including his head and brain. Let's say this head and brain regrew to contain all the memories of the original pre-sliced person. Well in this example clearly the upper half regrown person is the original while the lower half person is a duplicate.
Of course if you sliced the person "vertically" in half from the head downward, it becomes somewhat more difficult to determine which half is the original. This is even more so if cutting in half vertically makes BOTH halves lose their consciousness and both halves then regain consciousness at a later time once fully regenerated into whole persons. In THIS case, it is certainly a possibility then that the ORIGINAL consciousness has died and two NEW consciousness but inheriting the memories of the original have been created!
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About Therap Services
Therap is a high availability service bureau providing integrated online reporting, documentation and communication technology services for organizations working with persons with disabilities worldwide. Therap's suite of Individual, Staff and Billing support applications provides an integrated solution to the needs of the disability community. Therap applications are being used in over thirty states in the US and in Nepal and Bangladesh. For further information, please visit http://www.TherapServices.net.
|SOURCE Therap Services
Copyright©2007 PR Newswire.
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Owner Freddy Smith reveals his success story and advises new owners.
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Lustra™ Tip of the MonthRead More


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Originally Posted by wblynch
I miss those little fold up sheets that used to come in the film boxes.
Sunny-16 rules. Last summer I made a mistake of trusting my in-camera meter and a whole roll was drastically over exposed due to a dying meter battery.
I should remember the habit of sanity checking the metered settings with Sunny-16 observations.
Sunny 16 has saved me here, too. I always eyeball and compare my in-head exposure estimate with the one on the meter. If nothing else, it's good mental excersise


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Its All About Money are a collection of articles with advice on the best ways to manage and grow your money!
What is adaptive authentication & how does it help?
8, January, 2015
Benefits of using a Debit Card
24, October, 2014
Muhurat Trading & Its Myths
Are NRIs subject to Income Tax?
14, March, 2014
Internet Banking
At Axis Bank we believe in making your Money Transfers fast and simple and hence, we offer you the facility of MoneyGram, one of the leading brands in instant money transfers across the globe. MoneyGram has a global reach through a network of 233,000 local agents across 191 countries and territories – giving you real convenience and flexibility. So with MoneyGram you're never far away from a fast and easy money transfer.
The MoneyGram facility is available from Axis Bank branches in the states of Punjab, Kerala, Goa and Maharashtra (Mumbai & Thane) only. For the list of Axis Bank branches making payments, check list of MoneyGram branches.
Step 1: Visit your MoneyGram agent, taking some personal identification with you (as per the regulations in your send country).
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RBI present India's Monetary Heritage to the Public
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A little cheap looking
posted 6 years ago
These collars are okay for very, very small dogs, but they look a bit cheap, in my opinion.
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Originally written on Patriots Life | Last updated 11/18/14
Some good, some bad. That's average.A lot of people might only remember his interception return for a touchdown. However, I noticed a lot of familiar sights in the Patriots secondary yesterday, only with #31 being the victim.The interception you can't really give credit to Talib, it was caused by a Wilfork rush that forced Luck to overthrow. It was right to Talib, the return he had was amazing though.I was also impressed with his play on two plays that actually went for a 25 yard completion and also a touchdown. He was in position at least - as Greg Bedard notes in the below article.Still, he had other plays that looks like a guy that hasn't played football in awhile.Greg Bedard, Boston.comAfter that, Talib's play became more inconsistent, perhaps a sign of fatigue and rust after such a long layoff.Reggie Wayne had a back-shoulder completion against Talib for 6 yards, and then there was a 21-yard pickup by Brazill when Talib couldn't catch up on a shallow cross.Talib was beaten soun...
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*+-Tanya Somanader: Republicans in Congress and across the country are introducing a variety pack of extreme anti-abortion bills — including personhood initiatives, heartbeat bills, and fetal pain bills — that saw some success last year.
Progressive Media Advocates
-+*Treva Brandon Scharf: Can't afford a gym membership? Get bored easily by exercise? Don't want to run into your ex at Equinox? No problem! There's always the great outdoors – otherwise known as your local park.
-+*Walter Moss: There is little chance that any Republican nominee will put dealing with climate change at the center of his/her agenda, but we progressives should insure that at least the Democratic nominee does.
-+*Annette Bernhardt: The inequality debate often focuses on globalization and new technology, but we know that the decline of unions and the falling real value of the minimum wage have also played critical roles.


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DMV to Internet-less New Yorkers: Get in Line
By Jared Chausow
By Katie Toth
By Elizabeth Flock
City Hid Facts From Feds About Rikers
By Albert Samaha
Flood Wall Street Gets Pepper Sprayed and Arrested
By Anna Merlan
By Jon Campbell
Report Sheds Light on Anti-Muslim Bias
By Jon Campbell
Rikers Island Lawsuits Over Diabetic Care
By Albert Samaha
Saying she was "glad" the Voice exposed the Rev for being a "philanderer" and a "hypocrite," Samantha said: "How could you out another leader [Jesse Jackson] and then you got dirt too? You took her from her husband." All the money, she said, that "was going to support you and her habits" could have been used for "outreach in the community."
Sharpton called the show, insisting, "I fired you because you didn't do your work." But Samantha stayed on message, contending that the Harris affair was going on for four years and that Harris was "the least present person in the office." The Rev shrieked: "All comers come on, because I'm ready to deal with you."
In an appearance on WWRL, Sharpton vacillated between denying the Harris relationship and conceding it, saying, "I've never heard of an extramarital affair when you're no longer married." But his attempt to conflate four years into the present tense didn't work, with one host noting: "You're a reverend, sir."
Research assistance: Eric Cantor, Deborah S. Esquenazi, and Daniel Ten Kate
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text: A30 LOL HEADSET CRYSTAL CLEAR VOICE SCREAMING FULL STEREO LEGENDARY CARNAGE The epic battles and Champions of League of Legends come to life with the limited edition LoL A30 headset. Matte black finish and bronze accents, custom tags, a LoL Rocket Girl Tristana Champion & Skin, plus a collectors box make this the must-have headset experience for serious players and fans alike. $100 SHOP THIS HEADSET


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The Oak Ridge Institute for Science and Education (ORISE) is a U.S. Department of Energy institute focusing on scientific initiatives to research health risks from occupational hazards, assess environmental cleanup, respond to radiation medical emergencies, support national security and emergency preparedness, and educate the next generation of scientists.
Balajee named director of Cytogenetic Biodosimetry Lab at REAC/TS
May 21, 2015 - Adayabalam Balajee, Ph.D., has been named the director of the Cytogenetic Biodosimetry Laboratory (CBL), which is operated as part of the Radiation Emergency Assistance Center/Training Site (REAC/TS).
Dainiak Named Director of REAC/TS
March 6, 2015 - Nicholas Dainiak, M.D., F.A.C.P., has been named director of the Radiation Emergency Assistance Center/Training Site (REAC/TS) at the Oak Ridge Institute for Science and Education.
ORISE to support CDC infectious disease initiative
Jan. 16, 2015 - ORISE will design and carry out a needs assessment plan for the CDC's Advanced Molecular Detection and Response to Infectious Disease Outbreaks (AMD) initiative.
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Ashley Cross, an undergraduate researcher, was one of more than 6,000 students and faculty who took part in ORISE-managed research programs last year. Learn more about her research with microorganisms at Oak Ridge National Laboratory.
Research participants placed at Oak Ridge National Laboratory through science education programs administered by ORISE share how access to world-class research facilities and staff have catapulted their careers in science and technology.


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Ravitch said at a news conference that Erick Gelhaus, who has been with the sheriff's office for 24 years, acted in self-defense when he shot Andy Lopez. The boy was shot seven times in a vacant lot near Santa Rosa in October.
"The law provides for a complete defense of anyone who defends himself or others," Ravitch said.
Gelhaus and his partner said they ordered Andy to drop the pellet gun he was holding. Instead, they said, he turned towards them, still holding the gun, which did not have the orange tip required by federal law for toy and replica guns.
The FBI is investigating the shooting for possible civil rights violations, and Andy's family has filed a lawsuit in U.S. District Court.
The shooting sparked large demonstrations last year. Protesters gathered outside Ravitch's office during her news conference.


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BOULDER, Colo., Dec. 8, 2011 /PRNewswire/ -- BackJoy announced today the launch of its new Posture+ sitting device, just in time to provide welcome relief for the nearly 65 millions Americans traveling this holiday season. With 8 out of 10 Americans experiencing back pain in their lifetime, this newest addition to the BackJoy product line makes a perfect gift this holiday season to help travelers combat the problems associated with long-term sitting.
The normal seated position prevents the body's core from being engaged, but sitting on the Posture+ helps to utilize core muscles for spinal strength. Users find increased comfort in the thighs, tailbone and lower back, and many report feeling more energy and better breathing. "I was surprised the difference it actually makes when I sit in my office chair. It not only makes sitting more comfortable during the day, but it makes me feel better getting up after sitting for a while," says BackJoy customer Adam Micheli.
Posture+ utilizes BackJoy's patented Applied Postural Science™ (APS), which promotes better posture by maintaining the spine's most natural and strain-free position during sitting. Posture+ tilts the user's pelvis upright to re-shape the spine and relieve pressure while simultaneously cupping the gluteal muscles. This combined action more evenly distributes the user's body weight to prevent pressure points from developing. These revolutionary features of Posture+ recreate the same position and balance achieved while standing up.
Consumers can purchase Posture+ for themselves or a loved one for $39.99 on BackJoy's new website: http://shop.backjoy.com. All visitors to the website will receive a special holiday offer of free shipping on all web orders now until December 20th. Posture+ is available in six vibrant colors – red, blue, yellow, fuchsia, orange, and
|SOURCE BackJoy Orthotics, LLC
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2004 BEST Burrito
El Pelón Taqueria
Pictures of Mexican wrestlers, Day of the Dead skeletons, and photos of Pancho Villa bolster the authenticity of this Mexican outpost in the Fenway. Unlike at other assembly-line burrito joints, the burros here don't mush together into a single taste on the palate. Each ingredient—Mexican rice, succulent, homemade guacamole, and grilled steak, chicken, or fish—bursts with its own spicy flavor inside the symphonic whole of the roll. A word of warning: If you ask for extra hot sauce, you better mean it.
Be respectful of our online community and contribute to an engaging conversation. We reserve the right to remove impersonators or personal attacks, threats, profanity, or flat-out offensive comments. By posting here, you are permitting Boston magazine and Metro Corp. to edit and republish your comment in all media.


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