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In a multiprocessor system, at least one processor is acting as a master processor and another processor is acting as the slave or shadow processor that checks operation of the first processor. Periodically, a controller switches operating mode of a master or main processor to slave or shadow mode, and at the same time switches operation of a slave or shadow processor to main or master processing mode. The first processor is then used as a slave or shadow processor to check operation of the second processor.
1. A method of operating a fault tolerant digital computer system of the type which includes first and second processors with each such processor having a) a standalone master operating mode and b) a slave mode for monitoring the other processor, said method comprising the steps of:
running said system in one state for a predetermined time interval where said first processor is in said master mode and said second processor is in said slave mode;
running said system in an opposite state for another predetermined time interval where said second processor is in said master mode and said first processor is in said slave mode; and,
periodicly switching the operation of said system from said one state to said opposite state, and vice-versa, such that said first and second processors are in said master mode during respective time intervals which are interleaved.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
The present invention relates to fault tolerant digital computer system architecture especially with respect to ensuring proper processor operation. The present invention also relates to error detection/correction and fault detection/recovery. The present invention further relates to electrical computers and data processing systems, and more particularly to general purpose programmable digital computer systems utilizing an architecture with plural (redundant) processors and control of those processors.
System integrity, or the ability to detect incorrect system operation, is important in many areas of computer applications. Applications where human safety must be assured, such as air traffic control, aircraft control, or weapons guidance and control, are examples of systems in which errors in processing could have catastrophic effects. Other applications which have less severe consequences and yet operating integrity is highly desirable are banking and highly secure military classified computing and communications.
One method of ensuring system (or subsystem) integrity involves the checking of operation of a processor such as a central processing unit (CPU) or a local processor. In each such case where a redundant processor is used, the main and redundant processors are similarly connected to receive addresses, data, control signals and instructions. Thus, both such processors receive the same addresses, data, control signals, instructions and clock(s). One of these processors, sometimes referred to as the main processor or the master processor, provides normal processing, control, etc. such as may be needed for a particular application. The other processor, sometimes also referred to as a shadow processor or a slave processor, runs in parallel with the first processor and compares its own internal calculations with anything that the main processor sends out. To maintain synchronization between the two processors, they must operate with identical clocks. This can be accomplished by having one processor provide its clock signal to the other, or by driving the clock input(s) of both such processors with the same externally generated clock. In such a configuration, it may be desirable to give the shadow processor control over the system or subsystem when an error is isolated to the main or master processor. To maintain synchronization, it may be desirable to first halt operation of both processors, and then transfer control from one processor to the other. If the output from the main or master processor does not correspond with what is correspondingly generated internally by the slave or shadow processor, then an error is present in the system or subsystem. For fault detection purposes, the second processor is connected in parallel with the first processor, but the second processor has its outputs disabled such as by being placed in a test mode. The second processor, by comparing its outputs to the outputs of the first processor, extensively checks operation of the first processor. However, if the second processor is itself not operating properly, then faults with the first processor would not be detected. The present invention fulfills this need.
Slave or shadow processors are used in fault tolerant systems. In effect, the second processor is shadowing the operation of the first processor, and for that reason is sometimes referred to as a shadow processor. This can be accomplished in several ways, with the mode selected being dependent on the type of processors being used. For example, an external error compare circuit could be used to compare the outputs of the two processors. Other processors can shadow like processors within its own physical package without a need for external compare circuits. In the latter situation, such processors are placed in the shadow mode by activating an appropriate external pin. This causes the processor to tri-state, open-circuit or place a high impedance on its outputs. In shadow mode, the processor compares its internal output signal(s) to the corresponding external output(s) from the main processor, which is also provided to the shadow processor. Regardless of the mode used, if there is a mismatch between those signals, then a mismatch error should be indicated, by the shadow processor or by an external compare circuit. However, such a system assumes that the shadow processor is operating properly. If this is not the case, then an error in the first processor can go undetected. Furthermore, with a processor that is equipped with shadowing capability within itself, there is also a possibility that the shadow processor is working improperly or not working at all, and thus, there is no mismatch error generated. Furthermore, in a situation where it becomes necessary to transfer system or subsystem control from the first processor to the second processor, switching to a faulty or non-operating second processor could be catastrophic.
In a system or subsystem that includes a main processor and a shadow processor, the main processor performs all of the operations of some program, and the shadow processor just runs in parallel with the main processor and compares its own internal calculations with anything that the main processor sends out. Thus, the main processor and the shadow processor each receive the same instructions, data, etc., but only the output(s) of the main processor is actually used for its intended purpose by the system or subsystem it serves or where it resides. The shadow processor is utilized only for error or fault detection. For example, an identical program or set of instructions could be provided to both the main processor and the shadow processor, and both processors then execute those instructions. Both processors execute all of the instructions in that particular program. As a result of executing those instructions, the main processor eventually produces output(s) at its data output(s), and may also receive data and generate addresses. Meanwhile, the shadow processor is performing the same instructions, and so internally should be generating the same data results, but does not externally output that data. Thus, whenever a command in the program directs the processors to produce a data result, only the main processor will send that result out. That result is then received by the shadow processor, which compares that result to its own internally generated result of what the shadow processor would have sent out in response to that command. Alternatively, this comparison could be performed externally, but then care must be taken so that only the output of one processor at a time is provided to the system, subsystem or the like. If the system is operating properly, the results determined by the two processors should be equal or identical; otherwise, something is wrong with the system. The system may also include a data bus, address bus, instruction bus, etc., with the data bus for example being connected to other modules that produce or receive data to or from the main processor. For example, there could be a data memory, a data I/O module, etc. connected to the data bus. At any one instant in time, any of these could be putting out an address or data. In another instant, any of these could be receiving an address or data. The shadow processor, as its name implies, acts as a shadow, monitoring what is going on but not putting anything out on that bus or otherwise not being utilized by the system. Whenever the main processor puts something out on the bus, the shadow processor checks it against its own internal calculations. However, if the shadow processor is faulty or inoperative, then such checking likely could not be performed. In such a situation, the main processor is operating, and the user might believe that the shadow processor is checking such operation when in fact that checking is not being accomplished.
Thus, there is a need to perform in-line, real-time checking of a shadow processor. The present invention fulfills this need.
As used herein, the terms system and subsystem may be used interchangeably, and the terms slave processor and shadow processor may be used interchangeably.
Accordingly, an object of the present invention is to provide apparatus and method for checking for a malfunctioning or inoperative shadow or slave processor.
Another object of the present invention is to provide a fault-tolerant master/slave or main/shadow processor configuration.
A further object of the present invention is to provide a fault-tolerant system for processing, control, computing, etc.
Still another object of the present invention is to provide apparatus and method for switching operation or control from one processor to another.
Briefly, these and other objects of the present invention are accomplished by apparatus and method wherein two or more processors are connected in parallel to receive identical instructions, control signals, data, addresses, etc. involved with normal system operation. A controller is connected to each such processor to control which processor(s) are performing the usual computing operations or the like, and which processor(s) are instead being used for checking operation of the other processor(s). For example, one such processor could be utilized for operational purposes, and the other processor would be used for checking operation of the first processor for error or fault detection purposes. For example, a system could include only two such processors. The controller would then switch those two processors between normal and shadow operation, so that at different times each processor would be checking operation of the other processor. Such switching could be periodic (e.g. once every second), event-controlled, or both. In this manner, operation of both such processors could be checked and proper system operation could be thereby better assured. Should one of these processors while in shadow or checking mode find an error in the other such processor, then an appropriate error signal would be produced. Alternatively, the outputs of the two processors could be externally compared, and an error signal generated if there is a mismatch. If such an external error check is not provided, then after the controller switches the operating mode for the two processors, a timer can be provided so that absence of any signal from the first processor after a predetermined period of time would produce an error indication.
Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
In the drawings,
FIG. 1 is a simplified block diagram of a system including two processors;
FIG. 2 is a block diagram of a two-processor system that accomplishes fault or error detection for both processors according to the present invention;
FIG. 3 is a block diagram of one embodiment of a processor that can be utilized in the present invention;
FIG. 4 is a block diagram of one embodiment of a timer or event counter that can be utilized to determine when the mode exchange by the controller of FIG. 2 can be accomplished;
FIG. 5 is a block diagram of one embodiment of an error reporting/handling module that can be used in the system of FIG. 2;
FIG. 6 is a block diagram of one embodiment of a timer that can be utilized with the error reporting/handling module of FIG. 5 in the system of FIG. 2;
FIG. 7 is a flowchart illustrating a method of switching the two processors of FIG. 2 between master or operating mode and slave or checking mode;
FIG. 8 is a waveform timing diagram for signals that can be received or produced by the apparatus of FIG. 2 during the operation of FIG. 7;
FIG. 9 is another waveform timing diagram for signals that can be received or produced by the apparatus of FIG. 2 during another phase of operation of the apparatus of FIG. 2; and
FIG. 10 is still another waveform timing diagram for signals that can be received or produced by the apparatus of FIG. 2 during still another phase of operation of the apparatus of FIG. 2.
Referring now to the drawings, wherein like reference characters designate like or corresponding parts throughout the several views, there is shown in FIG. 1 a processing system 10 including a first processor 12, a second processor 14, memory 16, input/output module 18, and peripheral 20, all interconnected by a common bus 22. Other modules can be connected to bus 22, or any or all of modules 16, 18 and 20 can be removed, within the practice of the present invention.
A portion of the system 10 of FIG. 1 is illustrated in FIG. 2 in greater detail. System 24 of FIG. 2 includes first processor 12 and second processor 14 receiving identical signals on instruction bus 26, control bus 28, data bus 30 and address bus 32. Controller 34 controls or sets or determines the mode of operation of processor 12 and processor 14, and in turn is controlled or activated by timer/event counter 36. Timer 36 provides a switching signal SWITCH at appropriate intervals or events to cause controller 34 to exchange the operating modes of processor 12 and processor 14. In response to the switching signal SWITCH, controller 34 stops or holds operation of processors 12 and 14 using the bus request signal BREQ. Processor 12 and processor 14 each respond to the bus request signal with the bus grant signal BGNT, which is then provided to controller 34. In response to the bus grant signal, controller 34 then changes the operating mode signal TEST1 which it provides to processor 12, and changes the operating mode signal TEST2 which it provides to processor 14. For example, if processor 12 is to normally be the main processor and processor 14 is to be the shadow processor for normal operation, then it is preferred that controller 34 switch the processor operating modes at regular intervals for a period of time shorter than those intervals but long enough to determine whether processor 14 is operating properly, as will be further discussed below. However, the duration of system 24 operation with switched operating modes should be short enough (e.g. 250 nanoseconds or five clock cycles) that overall operation of system 24 and of system 10 is not affected (assuming no fault is present). Because each processor would then be shadowing operation of the other processor, at different times, it is preferred that processor 12 and processor 14 be the same model processor. Although the following description applies to use of an Am29000™ or Am29005™ RISC microprocessor as processor 12 and as processor 14, it should be understood that the practice of the present invention is not limited thereto, and that the present invention can be practiced with other processors. The Am29000™ and Am29005™ 32-bit streamlined instruction processors are produced by Advanced Micro Devices, Inc. and are described in Am29000™ and Am29005™ RISC Microprocessors User's Manual and Data Sheet Rev. 1, 1993 produced by Advanced Micro Devices, Inc., 901 Thompson Place, P.O. Box 3453, Sunnyvale, Calif. 94008-3453.
As shown in FIG. 2, system 24 also includes error reporting/handling module 38, which would receive and respond to any error indication produced by processor 12 or processor 14. For the system of FIG. 2, such error signals would be produced by processor 12 or processor 14 as error signal ERR which would be provided to error reporting/handling module 38. If necessary, as discussed below, error reporting/handling module 38 would respond with a non-maskable interrupt signal INTR to both processor 12 and processor 14 to halt and restart their operation because of a detected fault condition. During a temporary switch of operating mode between processor 12 and processor 14 by controller 34, should not even a good signal appear on error line ERR1 from processor 12, which would then be functioning as the shadow processor, during a predetermined period set by timer 40, then timer 40 would provide a signal TIME-OUT to error reporting/handling module 38. The TIME-OUT signal would then cause module 38 to generate a non-maskable interrupt INTR because generation of the TIME-OUT signal would indicate that processor 14 is not functioning.
Processing system 24 includes two processors 12 and 14 as master and slave connected together in all but a few signals. System 24 also includes an error reporting and recovery unit 38 as well as a control unit 34 for master and slave operation (shadow controller). Control unit 34 indicates which one of the processors 12 or 14 is at any one time to be the master processor and which is then to be the slave processor. Control unit 34 also switches this configuration either by an external event or at specific time intervals, as determined by module 36. This switching operation causes the current master processor to become the future slave processor, and causes the current slave processor to become the future master processor, after each switching event by control unit 34. If the current slave processor is not functioning (dead processor), then as soon as the current slave processor becomes the future master processor, error reporting and recovery unit 38 will detect the fault. Thus, the maximum duration of an unrecovered error would be one switching time interval of module 36.
As shown in FIG. 2, the two processors 12 and 14 are connected to all buses (address bus 32, data bus 30, instruction bus 26 and control bus 28) and signals except for the test inputs and ERR outputs of those processors. For this example, it is assumed that processor 14 normally serves as the shadow processor. Controller 34 is connected to the test input of processor 12 and the test input of processor 14, as well as the BREQ (bus request) inputs and BGNT (bus grant) outputs of the two processors. At the same time, controller 34 is also receiving a switching input SWITCH from a timer/event counter 36. The error reporting/recovery unit 38 receives the ERR1 signal from processor 12, and the ERR2 signal from processor 14, as inputs, and generates an INTR non-maskable interrupt signal as output to the processors. Error reporting/handling module 38 also receives as an input a TIME-OUT signal from timer 40 (in effect serving as a gross timer or dead-man timer) to indicate time-out errors. As discussed above, for example the system 24 could start with processor 12 as the master processor and processor 14 as the slave processor. As the slave processor, if processor 14 detects a mismatch in the two processors' output(s), then processor 14 will provide an error signal ERR2 at its output ERR to the error reporting/recovery unit 38. The error recovery unit 38 first logs the error. Error recovery unit 38 then tries to put the two processors 12 and 14 back in synchronization by generating a non-maskable interrupt signal INTR which is provided to the respective NMI input of each processor. This interrupt causes the two processors 12 and 14 to restart at a specific, predetermined address and thus will be synchronized once again. This restart address can usually be hardwired within most processors.
FIG. 4 shows one example of a timer/event counter that can be utilized as timer/event counter 36 in FIG. 2. The timer/event counter of FIG. 4 includes a decoder 42 connected to address bus 32 and control bus 28, a register 44 connected to decoder 42 and data bus 30, a counter 46 connected to register 44, and a zero-value detector 48 connected to counter 46. Register 44 and counter 46 also receive a suitable clock signal, which is preferably the same clock signal that is used to clock processors 12 and 4. When triggered by a control signal provided by the master processor on control bus 28, decoder 42 decodes the address signal then on the address bus. If that address is a particular address preset for this purpose, then decoder 42 will provide an appropriate signal to the load or LD input of register 44. This causes register 44 to load the value then appearing on data bus 30. This value, which is also provided by the master processor, dictates the time between switching operating mode of the two processors 12 and 14 between master and slave. Register 44 and counter 46 each have a parallel load. The master processor initially loads a value (dictating the time between switching of the two processors 12 and 14) in the register. The decode logic 42 will act on the processors addressing register 44. Since at startup counter 46 would have a zero value, zero detector 48 will provide a load signal to the LD input of counter 46. Accordingly, the value now entered in register 44 is also loaded into counter 46. The clock signal CLK then causes counter 46 to count down. When the counter counts down to a zero value, the zero detect hardware 48 will activate the SWITCH signal, which is provided to controller 34. At the same time, zero detector 48 also causes counter 46 to reload the value in register 44 back into the counter. Thus, the interval between successive switch signals from timer/event counter 36 is held constant, unless the master processor changes the value held in register 44. The length of this interval is determined by the value placed in register 44 and the speed of the clock signal applied to register 44 and counter 46. Although a zero detector 48 is shown in FIG. 4, it should be understood that, within the practice of the present invention, counter 46 can be made to count up or down between any two predetermined values.
One embodiment of an error reporting/handling module that could be utilized as error reporting/handling module 38 of FIG. 2 is shown in FIG. 5. The error reporting/handling module of FIG. 5 includes two registers 50 and 52 feeding an OR gate 54, a third register 56, an error register 58 receiving the outputs of OR gate 54 and register 56, and a decoder 60 for controlling operation of error register 58. Registers 50, 52, 56 and 58 have a common clock, preferably the clock used for processor 12 and processor 14. Register 50 receives and holds the ERR1 output of processor 12. Register 52 receives and holds the ERR2 output of processor 14. Register 56 receives and holds the TIME-OUT output of timer 40. OR gate 54 combines the registered ERR1 and ERR2 outputs into a single error signal which is provided as an input to error register 58. Register 56 provides the registered TIME-OUT signal as another input to error register 58. The master processor, via address bus 32 and control bus 28 as decoded by decoder 60, controls whether error register 58 will load the value being provided thereto onto data bus 30, or whether error register 58 would instead be cleared. An appropriate signal or value on control bus 28 from the master processor enables decoder 60 to decode the value on address bus 32. In the apparatus of FIG. 5, the two ERR1 and ERR2 signals are registered and combined together and saved into the error register. At the same time, if timer 40 produces a TIME-OUT signal, then the TIME-OUT signal is instead registered and saved into the error register. The master processor is able to read the error register 58 via data bus 30 and take proper action. The master processor would then clear error register 58 via address bus 32 and control bus 28 as decoded by decoder 60. If any of an ERR1 error, an ERR2 error or a TIME-OUT error occurs, then error register 58 generates an appropriate signal on its output INTR which is applied as a non-maskable interrupt to the NMI input of processors 12 and 14o This INTR signal would then activate the non-maskable interrupt of processors 12 and 14, which in turn resynchronizes processors 12 and 14 again. Thus, the apparatus of FIG. 5 is a self-locking mechanism.
One embodiment of timer 40 is shown in FIG. 6. The timer of FIG. 6 is similar to the timer/event counter of FIG. 4 except that the register 44 of FIG. 4 is not needed in the timer of FIG. 6. The timer of FIG. 6 includes a decoder 62, a counter 64 and a zero detector 66. The master processor 12 or 14 controls the timer of FIG. 6 via address bus 32 and control bus 28, which are provided as inputs to decoder 62. The output of decoder 62 in turn is applied to the load input LD of counter 64. Data bus 30 is connected to the data input of counter 64. Counter 64 is loaded every time that the master processor 12 or 14 writes a value to it. If the current master processor is hung and can not reload counter 64, then counter 64 reaches zero, and zero detect hardware 66 will then produce an appropriate TIME-OUT signal. The TIME-OUT signal is applied as an input to the error reporting/handling module. In FIG. 5, the TIME-OUT signal is applied to register 56. Thus, the timer of FIG. 6 ensures that the current master processor 12 or 14 is not dead. Control bus 28 controls decoder 62 by informing decoder 62 when it is to decode the address provided to the decoder by address bus 32. If the decoded value from address bus 32 is the value or values preselected for the purpose, then decoder 62 will activate the load input LD of counter 64, causing counter 64 to load what is then on data bus 30. This value in counter 64 is then counted down by the clock signal CLK. When the counter reaches a zero value, this is detected by zero detector 66 which in response generates the TIME-OUT signal. Thus, the value loaded into counter 64 determines the delay provided by the timer of FIG. 6. As discussed above, counter 64 could instead be set to count up or down between any two preset values for the same purpose.
Every time that timer/event counter 36 produces signal SWITCH, controller 34 will start to switch the operating modes between the master processor and the slave processor. This process is illustrated in FIGS. 7 and 8. As shown in FIG. 7, this process starts at step 70 with controller 34 responding to the SWITCH signal by applying an active bus request signal to the BREQ input of processor 12 and the BREQ input of processor 14. This bus request signal will stop the flow of instructions as well as data transactions within a few clock cycles of processors 12 and 14. At this time, processors 12 and 14 release all of their buses 26, 28, 30 and 32 by tri-stating them. Processor 12 and processor 14 inform controller 34 of this action by each providing an appropriate bus grant signal BGRT from their respective BGNT outputs to controller 34. Upon being so informed, controller 34 at step 72 then switches the operating modes of the two processors 12 and 14 by changing the state of their respective TEST input. In other words, at step 72 the signal previously applied by controller 34 to the TEST1 input of processor 12 is now instead applied to the TEST2 input of processor 14, and vice versa. Controller 34 at step 74 then removes the bus request signal, and processors 12 and 14 start where they left off, but with reversed roles. In other words, if processor 12 was previously the master processor and processor 14 was previously the slave processor, then at step 74 processor 12 is now instead operating as the slave processor while processor 14 is then instead operating as the master processor. Steps 68 through 74 take only a few processor clock cycles, and can be repeated as often as needed. If the current slave processor is not functioning, then after the switch provided by steps 68 through 74 it becomes the new master processor. The new master processor will then either function with a mismatch which is signalled by the new slave processor immediately, or else cannot function at all which timer 40 will catch by an appropriate TIME-OUT signal after the preset waiting time expires. The maximum time that the system 24 can be exposed to a faulty shadow processor is thus the time between switching. After the roles of processors 12 and 14 have been reversed for a predetermined period, shadow controller 34 will then unreverse the processor 12 and 14 roles using steps 76 through 82, which respectively correspond to steps 68 through 74. With step 74, the bus request signal is no longer active. When timer/event counter 36 provides another SWITCH signal to controller 34, then at step 78 controller 34 applies a bus request signal to processor 12 and processor 14 as discussed above. When processors 12 and 14 respond with the bus grant signal, controller 34 again reverses the states of the TEST1 and TEST2 signals, so that processor 12 is again the master processor and processor 14 is again the slave processor. At step 82, the switch process ends with the removal or inactivation by controller 34 of the bus request signal, which is followed by removal or inactivation by processors 12 and 14 of their respective bus grant signals (step 68).
The method of FIG. 7 can be implemented in a programmed logic device (PLD), programmed logic array (PLA), state machine or the like. FIG. 7 is a flow diagram showing what setup inputs would cause such a device to move from one state to another. FIG. 7 shows the respective inputs that cause such state changes, what happens internally in response to each such input and how the signals produced by such a device would be affected. One such device that could be used for this purpose is a 22V10 PLD device. However, the present invention is not limited to use of a 22V10; any PLD, PLA or state machine could be used for this purpose. The Boolean statements or expressions that would be implemented in such a PLD or the like to provide controller 34 is given in Table 1 below and in the following pages. These statements are written in the ABEL language.
______________________________________module SHADOW SHADOW device `b22v10`; switch PIN; bgnt PIN; breq PIN; test1 PIN; test2 PIN; q0 PIN; q1 PIN; q2 PIN; clk PIN; H,L,X,Z,CK = 1,0,.X.,.Z.,.C.;"STATE DEFINITIONS" shad-- sw = [q2,q1,q0]; M1-- S2 = [ 0, 0, 0]; "MASTER PROC1 & SLAVE PROC2" S-- SW1 = [ 0, 0, 1]; "START SWITCHING" SW1 = [ 0, 1, 0]; "SWITCH IN PROGRSS" E-- SW1 = [0, 1, 1]; "END SWITCH" M2-- S1 = [ 1 ,0, 0]; "MASTER PROC2 & SLAVE PROC1" S-- SW2 = [ 1, 0, 1]; "START SWITCHING" SW2 = [ 1, 1, 0]; "SWITCH IN PROGRESS" E-- SW2 = [ 1, 1, 1]; "END SWITCH"equations [q2,q1,q0].clk = clk;"STATE MACHINE"STATE-- DIAGRAM shad-- sw;STATE M1-- S2: if switch then S-- SW1 with breq = 1; test1 = 0; test2 = 1; endwith; else M1-- S2 with breq = 0; test1 = 0; test2 = 1; endwith;STATE S-- SW1: if bgnt then SW1 with breq = 1; test1 = 1; test2 = 0; endwith; else S-- SW1 with breq = 1; test1 = 0; test2 = 1; endwith;STATE SW1: goto E-- SWL with breq = 0; test1 = 1; test2 = 0; endwith;STATE E-- SW1: if !bgnt then M2-- S1 with breq = 0; test1 = 1; test2 = 0; endwith; else E-- SW1 with breq = 0; test1 = 1; test2 = 0; endwith;STATE M2-- S1: if switch then S-- SW2 with breq = 1; test1 = 1; test2 = 0; endwith; else M2-- S1 with breq = 0; test1 = 1; test2 = 0; endwith;STATE S-- SW2: if bgnt then SW2 with breq = 1; test1 = 0; test2 = 1; endwith; else S-- SW2 with breq = 1; test1 = 1; test2 = 0; endwith;STATE SW2: goto E-- SW2 with breq = 0; test1 = 0; test2 = J; endwith;STATE E-- SW2: if !bgnt then M1-- S2 with breq = 0; test1 = 0; test2 = 1; endwith; else E-- SW2 with breq = 0; test1 = 0; test2 = 1; endwith;end______________________________________
In Table 1, all states have been identified as has been done in FIG. 7. The state machine of Table 1 can be programmed into a programmable device such as a 22V10 manufactured by a variety of integrated circuit vendors.
Alternatively, timer 36, error reporting/handling module 38 and timer 40 could also be implemented in programmable logic devices (PLDs), programmable logic arrays (PLAs), state machines or the like.
FIG. 8 is a waveform timing diagram showing signal changes during a switch or exchange of master processor and shadow processor roles or modes. Initially, starting from the left of FIG. 8, the initial master processor is identified as processor P1, and the initial shadow processor is identified as processor P2. To cause a switch in processor modes, both processors are then halted (here using the bus request signal BREQ which is responded to with the bus grant signal BGNT) at time T1. At subsequent time T2, after operation of both processors has been halted, controller 34 then proceeds to switch processor operating modes between master and shadow by changing signals TEST1 and TEST2. Thereafter, at time T3, system 24 begins operating again, with processor P2 now being the master processor and with processor P1 now being the shadow processor. The clock is preferably the common clock described above. Signal BGNT is provided by processors 12 and 14 to controller 34. Signals BREQ, TEST1 and TEST2 are provided by controller 34 to processors 12 and 14.
FIGS. 9 and 10 are waveform timing diagrams for when an error condition is detected. FIG. 9 shows the alignment or realignment process after a mismatch error is reported to module 38. FIG. 10 shows the shadow processor reporting a bad or dead master processor. FIG. 9 shows a signal sequence when an error is detected. During operation of system 24, if the shadow processor gets a result that does not correlate with the corresponding result provided by the master processor, then the shadow processor reports this error as signal ERR1 (from processor 12) or ERR2 (from processor 14) to error reporting/handling module 38. A non-maskable interrupt INTR is then generated to resynchronize processors 12 and 14. System 24 then tries to continue operating with the hope that the detected error was just a transient error or a temporary glitch. However, if immediately or shortly thereafter (such as is shown in FIG. 10) the error signal recurs, then a faulty or inoperative master processor is indicated.
In FIG. 10, presence of a faulty master processor is indicated by repeated presence of error indications or signals on signals or lines ERR1 or ERR2 every few clock cycles. If that occurs, then the command or level for a non-maskable interrupt will remain on output line or signal INTR for at least a relatively extended duration, at least longer than is shown in FIG. 9. If system 10 is configured to be operable without a shadow processor, then it would be preferred to turn off or deactivate the bad processor, and continue system operation with only the good processor(s) operating. This can be accomplished by inserting an AND gate on the SWITCH line from timer 36 to controller 34. This AND gate would then be controlled by what is normally a master processor, which could thereby remove signal SWITCH and disable controller 34. Alternatively, the master processor could disable controller 34 by loading register 44 with a large value. However, if an operative shadow processor is needed for system 10 operation, and no backup shadow processor is available in the system, then it would be preferred to shut down all or part of system 10.
As discussed above, processor 12 and processor 14 can for example each be an Am29000/005 microprocessor. A simplified block diagram, adapted from FIG. 2--2 of the AMD manual cited above, is shown in FIG. 3. As shown in FIG. 3, each such processor includes an instruction fetch unit 84 receiving instructions from instruction bus 26, and an execution unit 86 receiving instructions from instruction fetch unit 84 and receiving or producing data on a separate data bus 30. The Am29000 microprocessor furthermore includes memory management unit 88 which produces address signals; otherwise, addresses would be sent to or produced by execution unit 86. For these AMD microprocessors, as described in the above-identified manual, bus request (input, synchronous) signal BREQ would correspond to signal BREQ described above, bus grant (output, synchronous) signal BGRT would correspond to signal BGNT described above, master/slave error (output, synchronous) signal MSERR corresponds to signals ERR1 and ERR2 described above, test mode (input, asynchronous) signal TEST corresponds to signals TEST1 and TEST2 described above, and warn (input, asynchronous, edge-sensitive) signal WARN corresponds to signal INTR described above. The bus request input allows other masters to arbitrate for control of the processor channel. The bus grant output signals to an external master that the processor is relinquishing control of the channel in response to the bus request signal. When the test mode input is active, the processor is in test mode, with all outputs and bi-directional lines, except MSERR, being forced to the high-impedance state or tri-state. The master/slave error output signal shows the result of the comparison of processor outputs with the signals provided internally to off-chip drivers of the slave processor. If there is a difference for any enabled such driver, then this line is asserted. A high-to-low transition on the WARN input causes a non-maskable trap or interrupt to occur.
However, as discussed above, the present invention is not limited to utilization of the Am29000/005 microprocessor. Instead, processors produced by Intel Corporation, Motorola Corporation, etc. running in parallel could be substituted therefor.
It is preferred that processor 12, processor 14, timer or event counter 36, controller 34, error reporting/handling module 38 and timer 40 all utilize a common clock.
The timer or event counter of FIG. 4 is a pre-loaded programmable timer, providing a repeated switching signal to switch processors 12 and 14 between master and slave modes and back. The frequency of such switching depends on the criticality of knowing promptly if the shadow processor is bad or malfunctioning. For example, a complete switching cycle between master and slave mode and back again could be done once every minute, or once every second, or each time that an input/output event occurs. Switching could occur with each I/O event for example if the master processor is calculating the physical location of received or produced data. Reading the wrong data from the wrong location, or storing data in the wrong location, are obviously not desirable. For some applications, even if the shadow processor 14 or 12 is not working, system 24 (and system 10) are not dead if the master processor 12 or 14 is still working. Knowing the status of the shadow processor immediately would then not be so critical, although reasonably prompt status information would be needed to avoid future problems. However, if for the particular application, proper operation of the shadow processor, to check the master processor, would be vital to maintaining system 24 integrity, then the frequency of switching processor modes should be increased appropriately.
Registers 44, 50, 52, 56 and 58 can for example each be a standard or ordinary register.
Some of the many advantages of the invention should now be readily apparent. For example, apparatus and method have now been provided for checking for a dead shadow processor, such as when an error is in the shadow processor so that it cannot check the master processor. Timer 36 periodically produces a switching or clock pulse, for example once every second or so, to controller 34, which in turn sends appropriate control signals to the two processors which put the main processor and the shadow processor in a hold state where they do not do anything, to maintain synchronization. Controller 34 then puts out other control signals which switch the main processor to shadow mode and the shadow processor to main processor mode. Controller 34 then instructs the two processors to start executing again. The main processor is now serving as the shadow processor, to check the processor that had, prior to this switch, been functioning as the shadow processor. If the former shadow processor is faulty or dead, and the main processor is operating properly, that situation could otherwise have continued indefinitely. However, with the operating mode exchange provided by the present invention, the main processor would now be able to detect faulty output of the shadow processor, which would then be reported to error reporting/handling module 38. A fault-tolerant master/slave or main/shadow configuration is thereby provided.
Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, the invention may be practiced otherwise than as specifically described.
Patent Citations
Referenced by
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text:
DUI last night.
Printable View
DUI last night.
What is this, strike six?
The Bengals have to just cut this kid. He's not worth the trouble. This is the 3rd or 4th time he has been arrested.
Also yesterday A.J. Nicholson was arrested for the theft that I mentioned in another thread.
Lawrence Phillips...paging Lawrence Phillips.....
Ugh... :rolleyes: I wondered why Lance lead off his segment of Sports Talk on WLW with this... didn't hear it mentioned on the news. :p:
Its a shame too, this kid has way too much upside to be throwing his talent away.:(
I'll still maintain that losing Henry hurt worse than losing Palmer in the playoffs.
Chris Henry is stupid.
Million dollar ability with a 2 cent mind. Doesn't that just frustrate you?
Why can't these numnuts just play Dungeons and Dragons in the offseason?
I guess he would rather play Grand Theft Auto.Quote:
Originally Posted by Falls City Beer
The only thing he hasnt been accused of yet is stealing someones car.
+20 cell of confinementQuote:
Originally Posted by Falls City Beer
When those contracts no longer land under his pen....Quote:
Originally Posted by CTA513
Right. :laugh:Quote:
Originally Posted by paintmered
It looks like he was +50 possessed by an Ork of Nimrod.
Strange this hasn't been reported anywhere I can find yet.

subset: commoncrawl


text:
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As one of the most succesful investors in Silicon Valley, Chris manages a ton of email. He uses Streak to power his dealflow and fundraising process. Chris keeps his inbox under control with Snooze and Thread Splitting.
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text:
Mercedes driver Lewis Hamilton hopes Red Bull's dominance would end in the upcoming Formula One season and make it the 'most exciting year' for some time.
Hamilton has reportedly admitted that he is tired of watching Sebastian Vettel keep winning for Red Bull and said that having 'your ass whopped so badly' with one team winning continuously for four years is not good for the sport.
According to the BBC, Hamilton hopes that the rule changes introduced in Formula One racing this year would make a difference in the result, as everybody wants a championship that 'goes to the wire'.
Hamilton also said that he has told people, who meet him at all the different airports he has been flying to and keep telling him that they used to watch formula one but have stopped now, to watch this year's Grand Prix as this is such a new year with so many changes, the report added.
Mercedes have reportedly been the most impressive team in pre-season testing, with Hamilton, who heads into this weekend's season-opening race in Australia as favourite, completing the most miles, while Red Bull have had a difficult time with poor reliability and lacking performance from their Renault engine.


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Monday - Friday, 6-9 a.m.
Host Tom Temin brings you the latest news affecting the federal community each weekday morning, featuring interviews with top government executives and contractors. Listen live from 6 to 9 a.m. or download archived interviews below.
Tuesday federal headlines - March 4, 2014
Tuesday - 3/4/2014, 8:33am EST
The Morning Federal Newscast is a daily compilation of the stories you hear Federal Drive hosts Tom Temin and Emily Kopp discuss throughout the show each day. The Newscast is designed to give FederalNewsRadio.com users more information about the stories you hear on the air.
- Federal agencies in the Washington, D.C., area are open this morning, but
under a two-hour delayed arrival.
Employees have the option for unscheduled leave or unscheduled telework. You
should plan to arrive for work no more than two hours later than you would be
expected to arrive. Non-emergency employees who report to the office will be
granted excused absence for up to two hours past their expected arrival time.
(Federal News Radio)
- The White House 2015 budget request will be on desks throughout
Washington by lunchtime today. It's likely to get picked over like a broiled
trout. President Obama is asking for $56 billion more than a bipartisan
Congressional agreement has already set as a spending ceiling. The President
signed that deal. Senate Democrats have already said they'll go by the agreement
and proceed directly to appropriations bills. Obama has announced a four-year,
$302 billion infrastructure spending plan. to boost spending on highways, rail
projects and mass transit. Half of the initiative would be financed through
corporate taxes, half from some spending stream yet to be worked out.
(Associated Press)
- The National Park Service says the two-week shutdown last year cost the nation
at least $414 million. The agency releases a report to prove its worth. Director Jonathan
Jarvis says the park service returns $10 for every $1 that taxpayers invest in it.
Nationwide, the park service says it supports hundreds of thousands of jobs and
generates nearly $27 billion in economic activity. The Park Service says visitor
spending supports more than 12,000 jobs locally, including Washington,
D.C., Maryland, northern Virginia and West Virginia's Eastern Panhandle.
(National Park Service)
- The Pentagon halts military-to-military engagements with Russia to pressure
Russian forces to pull out of Ukraine. Suspended activities include exercises,
bilateral meetings, port visits and conferences. But Pentagon spokesman Rear Adm.
John Kirby says the U.S. is not changing its military posture in the region. He
says the Navy is conducting routine, previously planned operations with European
partners. (Defense Department)
- Vietnam veterans sue the military over its treatment of
their post-traumatic stress. The vets say the Army, Air Force and Navy failed to
recognize that their disorders developed during their military service. They got
other-than-honorable discharges. With that black mark, they could not get
benefits. The lawsuit seeks class-action status. It accuses the Pentagon of
refusing to re-evaluate Vietnam-era vets' medical conditions, despite better
understanding of PTSD. A Pentagon spokesman says the department doesn't comment
on pending litigation. He says it has taken steps to address concerns about the
disorder, including assessing service members at military treatment facilities.
(Associated Press)
- New Mexico gives the Energy Department a deadline for dealing with nuclear waste now gathering above ground at
the federal Waste Isolation Pilot Plant. A parking area at the plant serves as
temporary storage for the containers of waste coming from federal facilities
across the country. The plant's underground dump remains closed following two
accidents. A radiation leak exposed at least 13 workers and set off an air-
monitoring alarm. Under New Mexico's plan, the Energy Department has to develop an
alternative storage plan if it keeps the facility sealed for more than three
months. (Associated Press)
- Telecom carriers are quietly pushing back against a proposed plan to have them store
metadata on behalf of the National Security Agency. Officials at AT&T, Verizon and
Sprint are telling the Obama administration they don't want to become spy data
miners. Having third party storage of phone records is one of four options the
Obama administration is considering. The NSA has been under fire from privacy
advocates for foreign surveillance it conducts using the data. The companies'
stance is a change for the carriers. Since World War II, phone and telegraph
companies cooperated with the government's requests for records. (Associated
- The Justice Department is suing Sprint Communications for $63 million.
Prosecutors say Sprint overcharged agencies $21 million for court-ordered
wiretaps. Justice is seeking treble damages. The suit alleges Sprint bilked the
FBI, the Bureau of Alcohol, Tobacco and Firearms and other agencies. A 1994 law
required carriers to upgrade their equipment so they could comply with wiretapping
orders. It took until 2006 for the FCC to rule the government didn't have to pay
for the upgrades. The Justice suit alleges Sprint charged for them anyhow from
2007 to 2010. (Associated Press)


text:
iPhone not charging? Here's how to fix it!
I have posted another article regarding a different issue for the iPhone not charging problem here: iPhone not charging
How i found my iPhone not charging
When i wokeup in the morning, i was amazed to find out that my iPhone was switched off! well, upon booting it up, another surprise was to know that the battery level was 2% only, which should not be like that usually.
Well, I connected my iPhone to my macbook and got busy in my usual routine including user comments on nabtron, but after some time, when i checked the percentage of charging done, it was still 2%! now that was creepy! maybe it was not charging ? I thought that maybe my connecting wire or usb port has got some problem or maybe iPhone has got some problem itself! Anyway i realized that my iPhone was not charging or atleast not showing any change in the battery meter even if it was trying to charge itself!
How to fix iPhone not charging issue
To fix my iPhone not charging issue, I checked which applications are running on my iPhone and didn't find any other than phone and messages. . . hmm . . . so now what? well, here it is that how did i got my problem with iPhone as it was not charging the battery:
Simply hold the home and power button for couple of seconds until it restarts, for around 10 seconds. If it by chance goes into recovery or dfu mode, don't, repeat! DoNOT attempt to recover it by any method, simply restart it again, we just need to restart and boot the OS fresh. And when it restarted, it had 100% charging dramatically instead of that 2% !
This will solve the problem hopefully! Some one mentioned that if we do up down to the silent/mute button four times before pressing home and power button on the iPhone, then it works to solve the iphone not charging issue too. . well, you can give a try to the silent / mute button too if simple reboot don't work for you!
Please let me know if your iPhone after following this tutorial is still bricked and not charging or not turning on!
If this didn't work for you, check this tutorial: iPhone not charging
You might also like
59 Responses to iPhone not charging? Here's how to fix it!
hi i have done what was said but does not work it worked for a day but reverted back to its non charging ways so what shall i do
hi i have done what was said but does not work it worked for a day but reverted back to its non charging ways so what shall i do it is iphone 2g
mah phone got switched off..,it completely stopped charging wt do i do nw?
Ok for the past two days my iPhone 5 won't charge or hold a charge all it does when I put it on the charger is show the charging signal and constantly blinks on and off even when it's charging or decides to come on I even brought a new charger still does the same any help
I found a solution for the charging problems. It's not reset, reboot, cable or charger problems. You just have to turn off the iphone and fully charge it. After that you can continue with the charge while on status on the succeeding charge
Just rebboted my iPhone and it is fine again :D
Worked for me. Thanks!
Worked for me – thanks
Worked for me too….thanx a lot nabeel!!!
guyz m in serious shit i have a 3g it wont charge have tried the hard reboot yank the sim in n out and reboot my pc with my iphone connected nothing is working the myth part is that when my phone is turned off as soon as i plug it in the wall or pc the phone starts up by apple logo showing but still wont show me if its charging and there is no churp any1 help please :( the weird part is though my iphone is showing me that its not charging the battery percentage is increasing but at a turtle's speed
Oh my gosh! Thank you so much Nabeel! This worked for me!:D
Nabeel, Thanks for the info. The reboot did the trick. It seems every time you update the firmware the phone needs to be rebooted.
worked for me thanks
Hi,my iPhone 3G haven't charging . I connect cable after again n again connect disconnect plz tell me what's problem(I purchase new cable but same problem)
This actually worked for me! Thank you so much
Many thanks – my phone suddenly wasn't charging for the past 24 hours, tired your suggestion of reboot and it worked, came up showing 100% charge, hopefully it lasts!
Hay finally some answers i was gunna get a new one wooow lucky i didnt
Hello, i have an iPhone. I just bought it today, and i plugged it into my PC. But then, the iPhone on's and offs every 4 seconds exactly. So it won't charge. I thought my PC was the problem, but then, when i plugged it in my wire sockets, it does the same thing. I thought it was flashing so it was charging, but then the next day, it was doing the same thing, and it had'nt charged a bit. Can you please help me solve this issue? Please and thanks.
In my last comment, i made a mistake. This is how it should have been:
Hello, i have an iPhone. I just bought it today, and i plugged it into my PC for it to charge. But then, the iPhone on's and offs every 4 seconds exactly while it charges. So it won't charge. I thought my PC was the problem, but then, when i plugged it in my wall sockets, it does the same thing. I thought it was flashing so it was charging, but then the next day, it was doing the same thing, and it had'nt charged a bit. Can you please help me solve this issue? Please and thanks.
how do i fix a charger problem for iphone 4g
It worked for me! Thank you xx
Hey guys! It happend to me last night, the same thing! I just conected it to mt my computer and it worked out perfecly :)
thanks dudeeeeeeeeeeeeee!
It worked!:D
thank you
ok i have done each thing the home and power and the mute then home and power i held it for 10 seconds then 20 then 30 nothing why is it doing this and how do i fix mine it is totally dead and wont charge is it done for good
iv tried to change the charger iv blown in the socket iv done absolutly everything above right now and i got all excited cause i saw the battery sign but then it said it needed to be plugged in again so i got all pissed this is really confusing some i beg of u plzhelp me this is my only phone and my iphone is 1st gen the very first one to come out in silver is the one i got i need help i cant lose it plz
It worked..!! THANKS!
I've tried rebooting and hard rebooting, nothing seems to work and I don't want to refresh the firmware, any suggestions?
My charger hasn't been working for a couple of days now, and its been so long that it has absolutely NO charge, meaning not even the "charge me" sign can come up.
This means that I can't reset it.
love that , thaaaaaaaaaaaaaaaaaaaaaaaanx its realllllly helpfull thanx thanx thanx 100% helpfull my iphone back 2 work thanx
thanks so much it worked by rebooting. i thought i have to go to a service center to have this fixed. thanks so much! :)


text:
Comment: joins?! (Score 1) 321
by sky289hawk1 (#40386843) Attached to: Give me a solder gun, and I can produce ...
Only inner and left.
The TSA's actions are completely, utterly, and without recourse illegal under the laws described in the US Constitution. Unfortunately, the Constitution doesn't provide average citizens with any way to punish the people in power who perform these illegal acts or who mandate that these illegal acts be performed.
See Amendment 2
Things are not as simple as they seems at first. - Edward Thorp


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Stuffing box & grease fittings
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Re: Stuffing box & grease fittings
Kenn, I just continued using the same grease that the previous owner had been using. Since he was the one who installed the thing (and he is a very experienced cruiser) I just followed his lead. All grease is "waterproof" in the sense it doesn't dissolve in water. I think that white "nautical" grease will eventually cake up inside the stuffing box. Wherever I've used the stuff it eventually ends up as a crusty white paste. Since the grease is really just to lubricate the shaft and stuffing (and fill any voids where water could accumulate) I don't see why it has to be waterproof nautical grease.
My sense is that if you install a grease gun like mine, it will deliver the grease under pressure, eventually pushing it through the flax rings and out the shaft (like in the photo). In this case, I can't see the use for the other grease nipple. My grease gun is really simple- it's a cylinder with a threaded cap with an 0-ringed "plunger" inside. You keep turning the "T" on top, forcing the grease down through the hose and into the stuffing box. I'm sure the grease gun is available and not uncommon. It's made of bronze which might mean it is a "marine" thingy. Start at a truck/tractor shop and see if they have a similar one. I think the grease should be delivered under pressure so it penetrates the stuffing box.
Vindö 50
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text:
Pogo Linux Launches New Storage Division, Pogo Storage
Storage division dedicated to helping small and mid-sized companies implement cost-efficient emerging technologies
Redmond, WA (PRWEB) June 02, 2011
Pogo Linux today announced that it has launched a separate storage division, Pogo Storage. Pogo Storage expands the company's storage offerings with cost-efficient, entry-level to mid-range enterprise solutions. The new division is dedicated to helping small- & mid-sized organizations implement emerging storage technologies and get the most from their storage budget.
Since launching as a open-source system integrator of pre-installed Linux servers and workstations in 1999, Pogo Linux has experienced exponential storage business growth. The new storage division will allow Pogo to develop sales and support resources for its storage customers, which include government, universities, media, and entertainment.
The move also allows Pogo Linux to better-position its managed solutions and appliances, including the StorageDirector Z Series line of entry-level enterprise SAN products based on the NexentaStor̢Ң open storage platform with ZFS.
"Pogo Storage was created in response to the growing demand from our customers for specific storage solutions," said Erik Logan, President of Pogo Linux. "To best meet the needs of our end users, we developed Pogo Storage to focus specifically on our storage product and support offerings. We are very excited about what this new division means for our customers."
"The LSI channel portfolio provides compatibility with an extensive ecosystem of system and storage products, allowing system integrators like Pogo Linux to deliver integrated solutions that meet the needs of end users across a broad spectrum of market segments," said Brent Blanchard, director of worldwide channel sales and marketing, LSI Corporation. "We are excited about the launch of Pogo's new storage division and the prospects of an expanded focus on LSI® storage technologies, including LSI MegaRAID® CacheCadeâ"¢ SSD caching software and the LSI WarpDriveâ"¢ solid state storage card, both built for database application acceleration."
"We are pleased to support Pogo's decision to focus a core of its business strategy on network storage to the enterprise market," said Evan Powell, CEO of Nexenta. "As a valued technology partner, we will continue to work closely with Pogo to deliver integrated NexentaStorâ"¢ certified solutions which are superior open storage alternatives to proprietary and legacy technologies."
Pogo Storage offers network-attached storage (NAS), direct-attached storage (DAS), and expansion subsystems products, in addition to managed solutions and appliances (SAN/NAS). For learn more about Pogo Storage, please visit http://www.pogostorage.com.
About Pogo Storage
Pogo Storage is a division of Pogo Linux which focuses on open source network storage system integration. From digital archive for a large video collection to a highly-available SAN, Pogo Storage helps IT departments at small- & midsized organizations dramatically reduce storage costs with a hybrid storage approach and breakout technologies, like NexentaStor̢Ң open storage platform with ZFS, and LSI WarpDrive SLP-300 PCIe solid-state storage card. For more information, please visit us online at http://www.pogostorage.com or call (888) 828-7646 (POGO) to speak with a trusted storage advisor.
LSI, the LSI & Design logo, CacheCade, MegaRAID and WarpDrive are trademarks or registered trademarks of LSI Corporation.
For the original version on PRWeb visit: http://www.prweb.com/releases/prweb2011/6/prweb8514452.htm


text:
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Barnes & NobleHell has frozen over again, perhaps for the last time, and the defining pop act of the 1970s has recorded a high-definition gem for the time capsule: Eagles Farewell Tour I - Live from Melbourne. Taped on HDTV in Melbourne, Australia's, Rod Laver Arena in November 2004, this soaring, 29-song concert DVD delivers the Eagles' considerable musical canon, from such soft-rock standards as "Peaceful Easy Feeling" and "Desperado" to the more guitar-driven hits of the Joe Walsh years, including "Heartache Tonight" and "Life in the Fast Lane." In addition to founding members Don Henley and Glen Frey, the Eagles on this tour include Walsh, who joined the band five years into its existence, in 1976, and bassist Timothy B. Schmit, who joined in '77. These Rock and Roll Hall of Fame inductees pride themselves on remaining methodically faithful to the original studio recordings, and they don't disappoint here. They also believe in serving up the hits -- which in this case also include chart-topping solo favorites from Henley ("Dirty Laundry" and "The Boys of Summer"), Frey ("You Belong to the City"), and Walsh ("Funk #49," "Walk Away," "Rocky Mountain Way"). With nearly three hours of music, two brand-new songs (Frey's "No More Cloudy Days" and Walsh's "One Day at a Time"), and bonus features, the Eagles - Live from Melbourne DVD is one for the long run.
Track Listing
Disc One
1."The Long Run"
2. "New Kid In Town"
3. "Wasted Time"
4. "Peaceful Easy Feeling"
5. "I Can't Tell You Why"
6. "One Of These Nights"
7. "One Day At A Time"
8. "Lyin' Eyes"
9. "The Boys Of Summer"
10. "In The City"
11. "Already Gone"
12. "Silent Spring" (instrumental intro)
13. "Tequila Sunrise"
14. "Love Will Keep Us Alive"
15. "No More Cloudy Days"
16. "Hole In The World"
17. "Take It To The Limit"
18. "You Belong To The City"
19. "Walk Away"
20. "Sunset Grill"
Disc Two
1. "Life's Been Good"
2. "Dirty Laundry"
3. "Funk #49"
4. "Heartache Tonight"
5. "Life In The Fast Lane"
6. "Hotel California"
7. "Rocky Mountain Way"
8. "All She Wants To Do Is Dance"
9. "Take It Easy"
10. "Desperado"


text:
Back To Berkeley Boot
Classic boot styling meets contemporary protection and stability in the Men's Back to Berkeley Boots from The North Face. The mid-cut boots feature a sturdy polyester upper, finished with a HydroSeal membrane for reliable waterproof defence, and a TNF Winter Grip rubber outsole with Ice Pick lugs that extend as temperatures lower to bite ever deeper into slick ground, keeping you moving surely and safely over snow and ice.
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FREE STANDARD UK DELIVERY on all orders 21st - 25th May 2015
Product Features
Alternatively, you might like these
Moab Rover Mid Waterproof Boot


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Buy eBook Begin reading in seconds $9.99 eBook Details
The Heavenly Man
By: Brother Yun, Paul Hattaway
Hendrickson Publishers / 2009 / Hardcover
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You've seen the headlines---government crackdowns on Chinese churches; mass arrests; human rights violations . . . but this intensely dramatic autobiography makes it real! Learn how God took a young half-starved boy from Henan Province and enabled him to stand strong on the frontlines for Jesus, braving horrific opposition and impossible odds. Life-changing! 351 pages, hardcover from Hendrickson.
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Son of the Underground: The Life of Isaac Liu, Son of Brother Yun, the Heavenly ManAlbrecht KaulMonarch Books / 2012 / Trade Paperback$9.49 Retail:4.5 Stars Out Of 5 9 Reviews
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Kisses from Katie: A Story of Relentless Love and RedemptionKatie J. Davis, Beth ClarkHoward Books / 2012 / Trade Paperback$10.49 Retail:5 Stars Out Of 5 64 Reviews
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Publisher's Description
Youve read the headlines and seen the news: government crackdowns on Chinese house churches, mass arrests, human rights violations. . . . But is it true? This intensely dramatic autobiography answers that question with the account of how God took a young half-starved boy and enabled him to stand strong for Jesus, braving horrific opposition and impossible odds.
For more than thirty years, Liu Zhenying, also known as Brother Yun, has been committed to bringing the gospel of Christ to all of China. Hunted, imprisoned, beaten, tortured, and separated from his wife and children, Brother Yun shares his story of incredible pain and sufferingand of powerful miracles and great joy. Featuring eyewitness accounts of prison escapes and healings, his words focus on the character and beauty of Jesus and challenge any reports that religious persecution is not still a daily reality for millions. Includes photos and reflections from his wife, Deling.
A life-changing true story of faith on the frontlines!
For more than thirty years, Liu Zhenying, also known as Brother Yun, has been committed to bringing the gospel of Christ to all of China. Hunted, imprisoned, beaten, tortured, and separated from his wife and children, Brother Yun shares his story of incredible pain and sufferingand of powerful miracles and great joy. Featuring eyewitness accounts of prison escapes and healings, his words focus on the character and beauty of Jesus and challenge any reports that religious persecution is not still a daily reality for millions. Includes photos and reflections from his wife, Deling.
A life-changing true story of faith on the frontlines!
Author Bio
Brother Yun (Liu Zhenying) is an internationally recognized speaker and author (LivingWater) who currently lives in Germany.
Paul Hattaway is an expert on the Chinese church and the author of Operation China, Back to Jerusalem, and Project Pearl.
Product Reviews
of customers would recommend this product to a friend.
Janice GareyDecatur, GAAge: 55-65Gender: female5 Stars Out Of 5Maximum Dedicaation Yields Bumper CropMarch 6, 2015Janice GareyDecatur, GAAge: 55-65Gender: femaleQuality: 5Value: 5Meets Expectations: 5This review was written for The Heavenly Man: The Remarkable True Story Of Chinese Christian Brother Yun.Review Title: Maximum Dedication Yields Bumper Crop (review of The Heavenly Man, the remarkable true story of Chinese Christian Brother Yun with Paul Hattaway)
Reviewer: Janice S. Garey
*****5 Stars
This book conveys an astounding testimony of one mans dedication and faith in Jesus, and the great worldwide impact his life has had for Christians. First, this is a story about loving Christ with all the heart, mind, soul, and strength. In reading you will find that it might not be what you were expecting. This book goes into extreme measures of love, sacrificial giving of all resources including physical being, and recognizing the benefits of being disciplined by the Lord through suffering. The Bible says the Lord disciplines those He loves. It is difficult to imagine the things that Yun went through as being allowed by a loving God. Yet, the book shows the other side of the punishments and sufferings he endured and the resulting unimaginable outcomes for good.
For those skeptical of miracles, this story will shake disbelief out of your mind. It affirms that God indeed has performed modern day miracles when needed under extreme situations His children face under persecution. This is a book very relevant to these days as reports of massive persecutions are witnessed on the web and television. This book will help you understand how best to pray for the persecuted.
My life and my faith have been enriched through the reading of The Heavenly Man. I will be suggesting all my Christian friends read it so they will understand the treasure of faith in Christ they have been given. I have been so touched by this book. It helps me to better understand the weaknesses of the churches in the West and why their membership has declined while the house churches in China thrived.
Thanks to bookfun.org for giving me this book in exchange for posting a review after reading it. Not a soul who reads it will go unblessed. It is hard to put down. I want to know more. I see that another book is offered on the next phase of ministry. Looking forward to the rest of the story!
ksnapierLima, OHAge: 45-54Gender: female5 Stars Out Of 5Inspiring, Touching LiveFebruary 7, 2015ksnapierLima, OHAge: 45-54Gender: femaleQuality: 5Value: 5Meets Expectations: 5This review was written for The Heavenly Man: The Remarkable True Story Of Chinese Christian Brother Yun.I was very excited to read this book as I have heard about Brother Yun but had not read his story. Brother Yun received Christ when he was a young man and from the time of his acceptance he had repeated visions from God. When he faced imprisonment and torture for his belief he would come out of it praising God all the louder.
Written from his perspective, with assistance from Paul Hattaway, this book opens the eyes of Christians everywhere of how a journey with God may not always be easy, but it is always rewarding. Thank you to Brother Yun, Monarch books and bookfun.org for allowing me to read this book in exchange for my honest review.
shanfromcanCanadaAge: 45-54Gender: female5 Stars Out Of 5Amazing hard to believe, yet true life of one man who follows Christ, no turning backJanuary 3, 2015shanfromcanCanadaAge: 45-54Gender: femaleQuality: 5Value: 5Meets Expectations: 5This review was written for The Heavenly Man: The Remarkable True Story Of Chinese Christian Brother Yun.This is the unbelievable, yet true story of Brother Yun of China and of his life, from the age of 16 when he chose to follow Christ and the many trials and tribulations that followed as well as the miracles. His times in jail were anything but easy, but in these situations Brother Yun would always be looking to God to see what He was trying to teach him during these times, and how He planned to use him. The stories, no you can't call them that, the atrocities he faced are more than a whole army should have to face, and yet he did, and counted on God, drew closer to Him and never asked God, 'Why me?'
Here in the western world Bibles are readily available, Christians often own more than one version and yet how many have the desire to get into His word, to study, to spend time with Him? We are so blessed and it for granted. Would we appreciate His Word and Him more if we had to work hard to get it?
After much prayer and believing that he would receive a Bible, he did and this is what he had to say on that gift.
"From that moment on I prayed to Jesus with faith-filled prayer. I fully trusted that the words in the Bible were God's words to me. I always held the Bible. Even when I slept I laid it on my chest. I devoured its teachings like a hungry child." pg 30
There were times of trials for his mom, his wife and later his children but all remained faithful to one another but most importantly to God.
This book contains so much, you need to read it for yourself. You will be blessed, encouraged, convicted.
Remember this next time things seem to be going against you:
"When God is blessing us, the devil is always active, doing his best to try to stop the advance of the kingdom of God. Satan tried to extinguish the fire of the Lord through persecution and hardship, but God continually poured his oil into our lamps, making our flames grow higher and brighter!"
pg 232
I was given this book by bookfun.org in exchange for an honest review. Thanks for giving me the opportunity to read such an amazing book.
BeckyOhioAge: 35-44Gender: female5 Stars Out Of 5This book has greatly changed my heart.December 27, 2014BeckyOhioAge: 35-44Gender: femaleQuality: 5Value: 5Meets Expectations: 5This review was written for The Heavenly Man: The Remarkable True Story Of Chinese Christian Brother Yun.The Heavenly Man is a wonderful book that opened my eyes to the suffering of Christians in China, understanding true sacrifice for the gospel, and realizing that as part of the western church I have much to learn about sacrifice and following the Lord. It was a book I enjoyed reading, and sometimes had to put down to really think through what Brother Yun was saying. He preaches the Gospel by his words, actions, and the choices he makes in his life. This book has greatly changed my heart.
Some quotes I liked:
"You can never really know the scriptures until you are willing to be changed by them."
"I had placed myself in the hands of the Lord of justice. I was no linger living by my own strength, but by the grace of God."
"We're not called to live by human reason. All that matters is obedience to God's Word and his leading in our lives."
"You need to realize that that any love I have in my heart for Jesus is only because of his love for me."
This is a book you must read. I am having all my kids read this book, my husband, and anyone I can talk into reading it. It is powerful. Not just because of what Yun has done and suffered for the Gospel, but on how he is open to God changing his heart. I want to be open to that kind of change. I highly recommend this book.
I received this book from the Book Club Network in exchange for my honest opinion.
ShaiNorfolk, NEAge: 35-44Gender: female4 Stars Out Of 5Calling Before ComfortDecember 10, 2014ShaiNorfolk, NEAge: 35-44Gender: femaleQuality: 5Value: 5Meets Expectations: 5The Heavenly Man is not an easy read. Its not the kind of book that youll dive into with a cup of coffee and plunge through in a day. However, it is the kind of book that will make you stop and thank God for the freedoms Hes allowed on those of us in the United States. It is the kind of story that reminds us how blessed, how privileged we are to be able to worship freely and without real persecution. Most importantly, it is the kind of story that causes us to lift prayers for our brothers and sisters around the world who suffer for the sake of preaching the gospel to the lost.
Yun tells his very painful story of being arrested, tortured and years of unspeakable horrors for the sake of the sharing the gospel. His relentless pursuit to fulfill his calling is inspirational and touching. Deling, his wife, also gives her account of the events. I loved the way they write together because the reality is, his struggles were shared with his loved ones as they prayed for his release from prison. Far from Bonnie and Clyde, this couple is considered to be criminals in their country. Their only criminal behavior was their inability to surrender Jesus for the lies their country propagated.
The Heavenly Man is an intense read but highly recommended.
I received this book from the Book Club Network in exchange for my honest opinion.
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Worldwide Writers of the Future Contest Announces Second Quarter '09-'10 Annual Winners
HOLLYWOOD, Calif., Oct. 8 /PRNewswire/ — The second quarter winners of the 2009-10 worldwide L. Ron Hubbard Writers of the Future Contest for fledgling science fiction and fantasy writers — including new authors from Australia, Ireland, and the United States — were announced today by Joni Labaqui, Author Services' contest director.
The quarterly winners are: Jason Fischer, first place, a South Australia Health Department records manager; Simon Cooper, second place, a professional gardener from Glenarm, Ireland; and Jeff Young, third place, a bookseller from Manchester, Pennsylvania.
"The Writers of the Future Contest is like 'American Idol' for writers long before there ever was an American Idol," said New York Times best-selling author and Contest judge Kevin J. Anderson (Dune prequels, Star Wars, X-Files). "It's amazing to me that a good 60 to 70 percent of the winners go on with successful careers in writing, and several have become best-selling authors themselves."
Throughout the Contest's 26-year history, more than 250 writers have been named as quarterly winners, gone on to publish over 500 novels and 3,000 short stories. Former Writers of the Future Contest winners that have appeared on the New York Times Bestseller's list include: Patrick Rothfuss, Jo Beverley, Nancy Farmer, Karen Joy Fowler, Dave Wolverton, Sean Williams and Tim Myers. Let's also mention highly popular Dean Wesley Smith (Men In Black), Leonard Carpenter (Conan), to name just a few of the winners who have entertained millions with their stories.
Each year, the Writers of the Future contest presents all winners with cash prizes, free travel and accommodations, a week-long professional writing workshop, and inclusion in the best-selling annual speculative fiction anthology, L. Ron Hubbard Presents Writers of the Future. The Grand prize winner is announced at an annual awards ceremony held next year in Hollywood.
"Our winners are judged by professional writers and illustrators from a pool of thousands of entries worldwide," Labaqui said. Well-known contest judges include multiple Nebula and Hugo Award winners and finalists such as Kevin J. Anderson, Orson Scott Card, Anne McCaffrey, Robert J. Sawyer, Larry Niven, Jerry Pournelle, Tim Powers, Dave Wolverton, Robert Silverberg and K.D. Wentworth.
Inspired by multiple New York Times' best-selling author L. Ron Hubbard, the merit-based Writers of the Future Contest was initiated 26 years ago to discover and encourage talented beginning writers of science fiction and fantasy.
For more information on the contests and a free e-book on the craft of writing from Science Fiction Grandmaster Anne McCaffrey, go to www.writersofthefuture.com
SOURCE Writers of the Future


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You know how Coachella is doing that cruise thing? Well, Stephen Colbert can top that. He announced last night that he's throwing his own all-star boat concert next Friday, August 10th, at New York's Intrepid Sea, Air and Space Museum (aka the U.S.S. Intrepid). Officially titled StePhest Colbchella '012 — RocktAugustFest, the festival will feature The Flaming Lips, Santigold, Grizzly Bear, and fun., about whom Colbert cracked, "I hear their songs are a ton of band." The legendary Grandmaster Flash will DJ, and seeing as he lives on Colbert's bookshelf these days, we wouldn't rule out a surprise appearance from Michael Stipe. Best of all, Colbchella is free. Tickets will be available today, and you can enter your email address at Colbert Nation for updates. … Read More
Grizzly Bear
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Typography geek Greg Solenström recently paired black and white photos of Brooklyn with Akzidenz Grotesk font and Jay-Z and Lil Wayne's "Hello Brooklyn 2.0″ for a fan made tribute that we think could work as an official video. Check it out after the jump, plus nine more of our favorite fan videos for artists like Radiohead, MGMT, and Grizzly Bear. … Read More
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What do you do when Grizzly Bear asks you to remix one of their songs but you think it's too perfect to touch? If you're Phoenix, you throw up an awesome little page that allows fans to make their own mashup of "Foreground" and Brian Eno's "Canon in D Major." The resulting juxtaposition is… Read More
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