text:
Freiman opened the season on the disabled list with a lumbar muscle strain before beginning his rehab assignment Monday. He went just 1 for 14 with Nashville during the rehab assignment and will continue to play at the Triple-A level, where he hit .284/.371/.506 with 15 home runs and 74 RBI in 310 at-bats last year.
Freiman played seven innings at first base before being removed from the game. He's recovering from a lumbar muscle strain in his back and could be ready to return to action soon, provided he doesn't suffer a setback during his rehab assignment.
Freiman is on the disabled list with a lumbar muscle strain but was able to play in extended spring training games in the last half of April. He hit .218/.269/.448 with five home runs and 15 RBI in 87 at-bats last season.
Freiman had four at-bats and played first base in an extended spring training game. Freiman has a lumbar muscle strain and isn't expected back until around mid-May.
According to MLB.com, Freiman played four innings and hit a home run. Before the season started, Freiman was placed on the disabled list with a lumbar muscle strain. It's still unknown when Freiman will be activated from the DL.
Freiman told reporters his back is feeling better lately after some aggressive treatment on his back. He has yet to be cleared for baseball activities.
Pomeranz is set to start Wednesday night in Houston.
"At the end of the day, we do what we do to try to help the team win," Freiman said, per MLB.com. "I was happy to be able to contribute a little bit, but ultimately, I'm here to help the team win, and unfortunately, we didn't win. It was nice to take some good swings, do some stuff to contribute, but it's going to be tough to leave a good taste in our mouths after being swept."
Freiman also homered Friday at Atlanta. He is batting .286 (4 for 14) with one double, three home runs and five RBI in five August games.
Freiman hit just four home runs in 190 at-bats during his rookie season last year, but he took no time getting on the board once given an opportunity this seaso. He's long had a solid power profile in the minors, and he owns a .277/.361/.493 line with 14 home runs and 69 RBI in 296 at-bats with Triple-A Sacramento.
Freiman is also expected to take batting practice Wednesday.
Freiman is dealing with an abdominal injury and has been out since Sept. 16.
Freiman, who last played a week ago, has hit .275/.329/.392 with four home runs and 24 RBI in 189 at-bats during his rookie season.
Freiman, who last played Monday, has hit .275/.329/.392 with four home runs and 24 RBI in 189 at-bats during his rookie season.
Freiman will hit fifth against Erik Bedard. Frieman is hitting .267/.309/.367 in 150 at-bats. Freiman has performed better against lefties, hitting .302 in 116 at-bats.
Freiman went 3 for 4 with one run scored in the game, to raise his batting average to .284.
The 26-year-old went 13 for 37 (.351) with a homer and nine RBI for the month.
Freiman, who has hits in six of his last seven games, is batting .271 with two home runs and 15 RBI overall through 70 at-bats.
Freiman has made 17 starts against left-handed pitchers and one against righties, as he continues to be utilized in a platoon with Brandon Moss.
Freiman went 2 for 3 in the game with three RBI. He added a two-run double in the fourth inning of the game. He scored twice and his three RBi gives him 10 on the year. Freiman is batting .245.
The first baseman has gone 9 for 26 (.346) in May over 10 games with a homer and five RBI.
Freiman has done most of his damage against left-handed pitchers, batting .375 (9 for 24) with one home run, two doubles and six RBI in 13 games.
"He's a right-handed bat at first base, and a power bat, and really has done a great job for us in the time that he's been in there," Melvin said, per MLB.com. "It can be difficult for younger players to have to acclimate to a role where they're not playing every day, but he's done it beautifully. He works very hard to keep himself ready, and gets the brunt of the time at first base against left-handed pitching."
"He knew about it last night," Melvin said. "Hopefully he slept ... It will be a special night."
Freiman, who had not started since April 15 against Houston, has gone 3 for 18 (.167) over nine games. He's homered once with five RBI and five strikeouts.
Freiman drew the start with lefty Joe Saunders on the mound for the Mariners, and he could continue to see regular playing time against lefties this season.
In order to clear a spot on the roster, Oakland placed relief pitcher Fernando Rodriguez on the 60-day disabled list. Rodriguez is likely done for the season and may need Tommy John surgery.
Freiman is a Rule 5 draft pick, so the A's will have to keep him on the roster all season or offer him back to the Padres.


text:
are you sure you cant spoil a baby under 1?
Btw- no, you can't spoil a baby. I don't even think that they understand that "crying" means "pick up." I think they cry because they miss you and they smile when you hold them because they love being near you. You are their world right now and there's plenty of time for the rest of the world later. And even if they are crying for you to hold them, is that really such a bad thing? I can't imagine any mother ever said "I really wish I had held my baby less and made him cry more," but I'm sure there are many who regretted not holding their babies while they are still so small, sweet and totally in love with you. One day they'll be less soft and sweet-smelling and that look of love and amazement you get every time they see you will be replaced with eye rolls. It may be frustrating at times, but it's gone way too fast.
Ditto to what MommyMagic1118 said
I'm too old for this sh*t
TK unite!
I also noticed that my lo smiles when I pop my head around his stroller, carseat, crib etc. when he can see me. I get a huge gummy grin that melts my heart. I think it is more of a, "HEY! There you are!!" type of smile.
I'm too old for this sh*t
TK unite!
Hubby & I married Sept. 10, 2005
Aries born 1/25/2005 Auryona born 5/23/2008
miscarried Angel 12/27/2011 Evelyn Belle 11-17-2012
Love is a NEED. They literally need love and comfort to develop normally.
They are incapable of manipulating, calculating or scheming.
My first baby was like that. She was super high needs baby. A walker came in soooo handy at this stage because she felt as if she could be with me. They're illegal here in Canada, but scored one at a lawn sale and it was a life saver!
And my advice is to acknowledge and give her the attention she desires. She is now 3yo and I have people not believing she was the super high-needs, clingy baby as she is very independent. She's still clingy in some areas, but we're night and day compared to how she was during her first two years.
"For this child I prayed, and the Lord has granted me my petition that I made to him."
American in Canada
I remember that all children are clingy when they are going to be approaching a new developmental phase (crawling, walking, going to school for the first time), etc. I just remind myself of that and rememeber that within a month or two she will be crawling around the house and getting into everything -- and then longing for the precrawling days, when I did not have to worry about every little things her possibly getting into.
If she can sit upright by herself, put her in a backpack carrier.
My cuddle bug spends a lot of time in my babyhawk mei tai carrier. It helps to babywear to be able to meet the needs of my toddler as well. I wouldn't trade these cuddles for anything! They are only little for such a small amount of time!
Ellen (39) and DH Brian (39) est. 2001, our sweet girls, Claire born 11/14/10 and Abigail born 11/21/12!!!

subset: commoncrawl


text:
An integrated multiport switch operating in a packet switched network provides the capability to alter VLAN tags on a port by port basis. An internal rules checker (IRC) employs a modular architecture that enables data frames to be processed simultaneously and increase data throughput. The IRC further generates a port vector, and thereby, outputs a forwarding descriptor that instructs Port Vector FIFO logic (PVF) on how to process the data frame.
1. A multiport switch configured for processing a data frame, comprising:
a plurality of ports for outputting the data frame; and
rules checker logic configured for generating in a pipeline manner a forwarding descriptor, the rules checker logic comprising a destination address engine for outputting a port vector that selectively maps a destination address of the data frame to one or more of the ports and wherein the rules checker logic further comprises an ingress rules engine, a source address lookup engine, and an egress rules engine; the ingress rules engine, the source address lookup engine, the destination address engine, and the egress rules engine being pipelined to process a different respective data frame simultaneously;
wherein the rules checker logic is configured to modify the port vector to output the forwarding descriptor, the forwarding descriptor comprising the modified port vector.
2. The multiport switch as in
performing a spanning tree check;
determining whether the data frame was received via the one of the ports;
determining whether the data frame was received via a last cascade port;
executing a trunk algorithm to load balance among a portion of the plurality of ports;
performing a VLAN egress rules check; and
determining whether the one or more of the ports is a sniffer port.
3. The multiport switch as in
4. The multiport switch as in
5. The multiport switch as in
6. The multiport switch as in
7. The multiport switch as in
8. The multiport switch as in
wherein the forwarding descriptor further comprises an untagged set field indicating which ports should remove a VLAN tag header before transmitting the data frame, and a frame pointer field indicating location of the data frame in the memory.
9. A method of forwarding a data frame in a switching system having a plurality of ports for outputting the data frame, the method comprising the steps of:
generating a port vector based upon a destination address of the data frame, the port vector designating one or more of the plurality of ports to transmit the data frame;
masking the port vector to selectively add or remove port designations for transmission wherein the step of masking is based upon the steps of:
performing a spanning tree check,
determining whether the data frame was received via the one or more ports,
determining whether the data frame was received via a last cascade port,
executing a trunk algorithm to load balance among a portion of the plurality of ports,
performing a VLAN egress rules check, and
determining whether the one or more of the ports is a sniffer port; and
outputting in a pipeline manner a forwarding descriptor that comprises the masked port vector.
10. The method as in
11. The method as in
receiving a frame header including a source address and a destination address of the frame;
determining whether the frame was received with errors.
12. The method as in
13. The method as in
14. The method as in
15. The method as in
16. The method as in
1. Technical Field
The present invention relates to data communication networking devices, more particularly, to the data frame forwarding capability of a data network switch.
2. Background Art
A multiport data network switch conventionally permits data communication among a plurality of media stations in a local area network. Each station in the network is associated with a port of the switch. Data frames, or packets, are transferred between stations by means of data network switch media access control (MAC) circuitry, or "engines," for each switch port. The network switch passes data frames received from a transmitting station to a destination station based on the header information in the received data frame. The switch can link the network to other networks through one or more predesignated switch ports. The capability thus exists for creating logical workgroups of users who may be physically separated from each other. The network switch includes switching logic for receiving and forwarding frames to the appropriate destinations. When all of the stations connected to the network are simultaneously operating, packet traffic on the shared path can be heavy with little time between packets. As the switch experiences congestion, data loss and switch latency pose a serious problem.
As a result, the system is less reliable.
There exists a need for a switching device that efficiently generates frame forwarding information for various types of data transmissions in a VLAN environment. There exists a need for a switching device that includes a decision making engine designed to support networks requiring a high data throughput. There is also a need for a switching device that employs a modular decision making engine that facilitates changes to the decision making logic. There is also a need for distributing the process of forwarding data frames to avoid processing bottlenecks in the system and to increase system reliability.
These and other needs are satisfied by the present invention, where a multiport switch includes a decision making engine used to make frame forwarding decisions, in part, by outputting forwarding information. The decision making engine is a designed in a pipelined, modular fashion so that multiple frames may be processed simultaneously.
According to one aspect of the present invention, a multiport switch is configured for processing a data frame. The multiport switch comprises a plurality of ports for outputting the data frame. The switch also includes a rules checker logic for generating, in a pipeline manner, a forwarding descriptor. The rules checker logic includes a destination address engine for outputting a port vector that selectively maps a destination address of the data frame to one or more of the ports. Moreover, the rules checker logic is configured to modify the port vector to output the forwarding descriptor. The forwarding descriptor contains the modified port vector. Because the rules checker logic possesses a modular, pipelined architecture, the data frame forwarding rate is enhanced.
Still another aspect of the present invention provides a method of forwarding a data frame in a switching system having a plurality of ports for outputting the data frame. The method comprises generating a port vector based upon a destination address of the data frame. The port vector designates one or more of the plurality of ports to output the data frame. The method also includes modifying the port vector to selectively add or remove port designations. Ultimately, a forwarding descriptor is output in a pipeline manner. This method advantageously outputs a forwarding descriptor efficiently, thereby increasing the data throughput of the multiport switch.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part may become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
FIG. 1 is a block diagram of a packet switched network including a multiple port switch.
FIG. 2 is a block diagram of the multiple port switch of FIG. 1.
FIG. 3 is a block diagram illustrating in detail the switching subsystem of FIG. 2.
FIG. 4 is a block diagram of a system including the internal rules checker (IRC) of FIG. 2 in accordance with an embodiment of the present invention.
FIG. 5 is a flow diagram of the generation of a forwarding descriptor by the IRC in accordance with an embodiment of the present invention.
FIG. 6 is a diagram showing the format of the forwarding descriptor according to an embodiment of the present invention.
The present invention will be described with the example of a switch operating in a packet switched network, such as an Ethernet (IEEE 802.3) network. It will become apparent, however, that the present invention is also applicable to other packet switched systems, as described in detail below, as well as to other types of systems in general.
FIG. 1 is a block diagram of an exemplary system in which the present invention may be advantageously employed. The exemplary system 10 is a packet switched network, such as an Ethernet (IEEE 802.3) network. The packet switched network includes integrated multiport switches (IMS) 12 that enable communication of data packets between network stations. The network may include network stations having different configurations, for example twelve (12) 10 megabit per second (Mb/s) or 100 Mb/s network stations 14 (hereinafter 10/100 Mb/s) that send and receive data at a network data rate of 10 Mb/s or 100 Mb/s, and a 1000 Mb/s (i.e., 1 Gb/s) network node 22 that sends and receives data packets at a network speed of 1 Gb/s. The gigabit node 22 may be a server, or a gateway to a high-speed backbone network. Hence, the multiport switches 12 selectively forward data packets received from the network nodes 14 or 22 to the appropriate destination based upon Ethernet protocol.
Each multiport switch 12 includes a media access control (MAC) module 20 that transmits and receives data packets to and from 10/100 Mb/s physical layer (PHY) transceivers 16 via respective reduced media independent interfaces RMII) 18 according to IEEE 802.3u protocol. Each multiport switch 12 also includes a gigabit MAC 24 for sending and receiving data packets to and from a gigabit PHY 26 for transmission to the gigabit node 22 via a high speed network medium 28.
Each 10/100 Mb/s network station 14 sends and receives data packets to and from the corresponding multiport switch 12 via a media 17 and according to either half-duplex or full duplex Ethernet protocol. The Ethernet protocol ISO/IEC 8802-3 (ANSI/IEEE Std. 802.3, 1993 Ed.) defines a half-duplex media access mechanism that permits all stations 14 to access the network channel with equality. Traffic in a half-duplex environment is not distinguished over the medium 17. Rather, each half-duplex station 14 includes an Ethernet interface card that uses carrier-sense multiple access with collision detection (CSMA/CD) to listen for traffic on the media. The absence of network traffic is detected by sensing deassertion of a receive carrier on the media. Any station 14 having data to send will attempt to access the channel by waiting a predetermined time, known as the interpacket gap interval (IPG), after deassertion of the receive carrier on the media. If a plurality of stations 14 have data to send on the network, each of the stations will attempt to transmit in response to the sensed deassertion of the receive carrier on the media and after the IPG interval, possibly resulting in a collision. Hence, the transmitting station will monitor the media to determine if there has been a collision due to another station sending data at the same time. If a collision is detected, both stations stop, wait a random amount of time, and retry transmission.
The 10/100 Mb/s network stations 14 that operate in full duplex mode send and receive data packets according to the Ethernet standard IEEE 802.3u. The full-duplex environment provides a twoway, point-to-point communication link enabling simultaneous transmission and reception of data packets between each link partner, i.e., the 10/100 Mb/s network station 14 and the corresponding multiport switch 12.
Each multiport switch 12 is coupled to 10/100 physical layer (PHY) transceivers 16 configured for sending and receiving data packets to and from the corresponding multiport switch 12 across a corresponding reduced media independent interface (RMII) 18. In particular, each 10/100 PHY transceiver 16 is configured for sending and receiving data packets between the multiport switch 12 and up to four (4) network stations 14 via the RMII 18. A magnetic transformer 19 provides AC coupling between the PHY transceiver 16 and the corresponding network medium 17. Hence, the RMII 18 operates at a data rate sufficient to enable simultaneous transmission and reception of data packets by each of the network stations 14 to the corresponding PHY transceiver 16.
Each multiport switch 12 also includes an expansion port 30 for transferring data between other switches according to a prescribed protocol. Each expansion port 30 enables multiple multiport switches 12 to be cascaded together as a separate backbone network
FIG. 2 is a block diagram of the multiport switch 12. The multiport switch 12 contains a decision making engine 40 that performs frame forwarding decisions, a switching subsystem 42 for transferring frame data according to the frame forwarding decisions, an external memory interface 44, management information base (MIB) counters 48 a and 48 b (collectively 48), and MAC (media access control) protocol interfaces 20 and 24 to support the routing of data packets between the Ethernet (IEEE 802.3) ports serving the network stations 14 and the gigabit node 22. The MIB counters 48 provide statistical network information in the form of management information base (MIB) objects, to an external management entity controlled by a host CPU 32, described below.
The external memory interface 44 enables external storage of packet data in an external memory 36 such as, for example, a synchronous static random access memory (SSRAM), in order to minimize the chip size of the multiport switch 12. In particular, the multiport switch 12 uses the external memory 36 for storage of received frame data and memory structures. The external memory 36 is preferably either a Joint Electron Device Engineering Council (JEDEC) pipelined burst or Zero Bus Turnaround™ (ZBT)-SSRAM having a 64-bit wide data path and a 17-bit wide address path. The external memory 36 is addressable as upper and lower banks of 128K in 64-bit words. The size of the external memory 36 is preferably at least 1 Mbytes, with data transfers possible on every clock cycle through pipelining. Additionally the external memory interface clock operates at clock frequencies of at least 66 MHz, and, preferably, 100 MHz and above.
The multiport switch 12 also includes a processing interface 50 that enables an external management entity such as a host CPU 32 to control overall operations of the multiport switch 12. In particular, the processing interface 50 decodes CPU accesses within a prescribed register access space, and reads and writes configuration and status values to and from configuration and status registers 52.
The internal decision making engine 40, referred to as an internal rules checker (IRC), makes frame forwarding decisions for data packets received.
The multiport switch 12 also includes an LED interface 54 that clocks out the status of conditions per port and drives an external LED logic. The external LED logic drives LED display elements that are human readable.
The switching subsystem 42, configured for implementing the frame forwarding decisions of the IRC 40, includes a port vector first in first out (FIFO) buffer 56, a plurality of output queues 58, a multicopy queue 60, a multicopy cache 62, a free buffer queue 64, and a reclaim queue 66.
The MAC unit 20 includes modules for each port, each module including a MAC receive portion, a receive FIFO buffer, a transmit FIFO buffer, and a MAC transmit portion. Data packets from a network station 14 are received by the corresponding MAC port and stored in the corresponding receive FIFO. The MAC unit 20 obtains a free buffer location (i.e., a frame pointer) from the free buffer queue 64, and outputs the received data packet from the corresponding receive FIFO to the external memory interface 44 for storage in the external memory 36 at the location specified by the frame pointer.
The IRC 40 monitors (i.e., "snoops") the data bus to determine the frame pointer value and the header information of the received packet (including source, destination, and VLAN address information). The IRC 40 uses the header information to determine which MAC ports will output the data frame stored at the location specified by the frame pointer. The decision making engine (i.e., the IRC 40) may thus determine that a given data frame should be output by either a single port, multiple ports, all ports (i.e., broadcast) or no ports (i.e., discarded). For example, each data frame includes a header having source and destination address, where the decision making engine 40 may identify the appropriate output MAC port 2, based upon the destination address. Alternatively, the destination address may correspond to a virtual address that the appropriate decision making engine identifies as corresponding to a plurality of network stations. In addition, the frame may include a VLAN tag header that identifies the frame as information destined to one or more members of a prescribed group of stations. The IRC 40 may also determine that the received data packet should be transferred to another multiport switch 12 via the expansion port 30. Hence, the internal rules checker 40 will decide whether a frame temporarily stored in the external memory 36 should be output to a single MAC port or multiple MAC ports.
The internal rules checker 40 outputs a forwarding decision to the switch subsystem 42 in the form of a forwarding descriptor. The forwarding descriptor includes a priority class identifying whether the frame is high priority or low priority, a port vector identifying each MAC port that should transmit the data frame, receive port number, an untagged set, VLAN information, vector identifying each MAC port that should include VLAN information during transmission, opcode, and frame pointer. The format of the forwarding descriptor will discussed further with respect to FIG. 7. The port vector identifies the MAC ports to receive the data frame for transmission (e.g., 10/100 MAC ports 1-12, Gigabit MAC port, and/or Expansion port). The port vector FIFO 56 decodes the forwarding descriptor including the port vector, and supplies the frame pointer to the appropriate output queues 58 that correspond to the output MAC ports to receive the data frame transmission. In other words, the port vector FIFO 56 supplies the frame pointer on a per-port basis. The output queues 58 give the frame pointer to a dequeuing block 76 (shown in FIG. 3) which fetches the data frame identified in the port vector from the external memory 36 via the external memory interface 44, and supply the retrieved data frame to the appropriate transmit FIFO of the identified ports. If a data frame is to be supplied to a management agent, the frame pointer is also supplied to a management queue 68, which can be processed by the host CPU 32 via the CPU interface 50.
The multicopy queue 60 and the multicopy cache 62 keep track of the number of copies of the data frame that are transmitted from the respective ports, ensuring that the data frame is not overwritten in the external memory 36 until the appropriate number of copies of the data frame have been output from the external memory 36. Once the number of copies output corresponds to the number of ports specified in the port vector FIFO 56, the frame pointer is forwarded to the reclaim queue 66. The reclaim queue 66 stores frame pointers that need to be reclaimed and walks the linked list chain to return the buffers to the free buffer queue 64 as free pointers. After being returned to the free buffer queue 64, the frame pointer is available for reuse by the MAC unit 20 or the gigabit MAC unit 24.
FIG. 3 depicts the switch subsystem 42 of FIG. 2 in more detail according to an exemplary embodiment of the present invention. Other elements of the multiport switch 12 of FIG. 2 are reproduced in FIG. 3 to illustrate the connections of the switch subsystem 42 to these other elements.
As shown in FIG. 3, the MAC module 20 includes a receive portion 20 a and a transmit portion 24 b. The receive portion 20 a and the transmit portion 24 b each include 12 MAC modules (only two of each shown and referenced by numerals 70 a, 70 b, 70 c, and 70 d) configured for performing the corresponding receive or transmit function according to IEEE 802.3 protocol. The MAC modules 70 c and 70 d perform the transmit MAC operations for the 10/100 Mb/s switch ports complementary to modules 70 a and 70 b, respectively.
The gigabit MAC port 24 also includes a receive portion 24 a and a transmit portion 24 b, while the expansion port 30 similarly includes a receive portion 30 a and a transmit portion 30 b. The gigabit MAC port 24 and the expansion port 30 also have receive MAC modules 72 a and 72 b optimized for the respective ports. The transmit portions 24 b and 30 b of the gigabit MAC port 24 and the expansion port 30 a also have transmit MAC modules 72 c and 72 d, respectively. The MAC modules are configured for full-duplex operation on the corresponding port, and the gigabit MAC modules 72 a and 72 c are configured in accordance with the Gigabit Proposed Standard IEEE Draft P802.3z.
Each of the receive MAC modules 70 a, 70 b, 72 a, and 72 b include queuing logic 74 for transfer of received data from the corresponding internal receive FIFO to the external memory 36 and the rules checker 40. Each of the transmit MAC modules 70 c, 70 d, 72 c, and 72 d includes a dequeuing logic 76 for transferring data from the external memory 36 to the corresponding internal transmit FIFO, and a queuing logic 74 for fetching frame pointers from the free buffer queue 64. The queuing logic 74 uses the fetched frame pointers to store receive data to the external memory 36 via the external memory interface controller 44. The frame buffer pointer specifies the location in the external memory 36 where the received data frame will be stored by the receive FIFO.
The external memory interface 44 includes a scheduler 80 for controlling memory access by the queuing logic 74 or dequeuing logic 76 of any switch port to the external memory 36, and an SSRAM interface 78 for performing the read and write operations with the external memory 36. In particular, the multiport switch 12 is configured to operate as a non-blocking switch, where network data is received and output from the switch ports at the respective wire rates of 10, 100, or 1000 Mb/s. Hence, the scheduler 80 controls the access by different ports to optimize usage of the bandwidth of the external memory 36.
Each receive MAC stores a portion of a frame in an internal FIFO upon reception from the corresponding switch port; the size of the FIFO is sufficient to store the frame data that arrives between scheduler time slots. The corresponding queuing logic 74 obtains a frame pointer and sends a write request to the external memory interface 44. The scheduler 80 schedules the write request with other write requests from the queuing logic 74 or any read requests from the dequeuing logic 76, and generates a grant for the requesting queuing logic 74 (or the dequeuing logic 76) to initiate a transfer at the scheduled event (i.e., slot). Sixty-four bits of frame data is then transferred over a write data bus 69 a from the receive FIFO to the external memory 36 in a direct memory access (DMA) transaction during the assigned slot. The frame data is stored in the location pointed to by the buffer pointer obtained from the free buffer pool 64, although a number of other buffers may be used to store data frames, as will be described.
The rules checker 40 also receives the frame pointer and the header information (including source address, destination address, VLAN tag information, etc.) by monitoring (i.e., snooping) the DMA write transfer on the write data bus 69 a. The rules checker 40 uses the header information to make the forwarding decision and generate a forwarding instruction in the form of a forwarding descriptor that includes a port vector. The port vector has a bit set for each output port to which the frame should be forwarded. If the received frame is a unicopy frame, only one bit is set in the port vector generated by the rules checker 40. The single bit that is set in the port vector corresponds to a particular one of the ports.
The rules checker 40 outputs the forwarding descriptor including the port vector and the frame pointer into the port vector FIFO 56. The port vector is examined by the port vector FIFO 56 to determine which particular output queue should receive the associated frame pointer. The port vector FIFO 56 places the frame pointer into the top of the appropriate queue 58 and/or 68. This queues the transmission of the frame.
As shown in FIG. 3, each of the transmit MAC units 70 c, 70 d, 72 d, and 72 c has an associated output queue 58 a, 58 b, 58 c, and 58 d, respectively. In preferred embodiments, each of the output queues 58 has a high priority queue for high priority frames, and a low priority queue for low priority frames. The high priority frames are used for frames that require a guaranteed access latency, e.g., frames for multimedia applications or management MAC frames. The frame pointers stored in the FIFO-type output queues 58 are processed by the dequeuing logic 76 for the respective transmit MAC units. At some point in time, the frame pointer reaches the bottom of an output queue 58, for example, output queue 58 d for the gigabit transmit MAC 72 c. The dequeuing logic 76 for the transit gigabit port 24 b takes the frame pointer from the corresponding gigabit port output queue 58 d, and issues a request to the scheduler 80 to read the frame data from the external memory 36 at the memory location specified by the frame pointer. The scheduler 80 schedules the request, and issues a grant for the dequeuing logic 76 of the transmit gigabit port 24 b to initiate a DMA read. In response to the grant, the dequeuing logic 76 reads the frame data (along the read bus 69 b) in a DMA transaction from the location in external memory 36 pointed to by the frame pointer, and stores the frame data in the internal transmit FIFO for transmission by the transmit gigabit MAC 72 c. If the forwarding descriptor specifies a unicopy transmission, the frame pointer is returned to the free buffer queue 64 following writing the entire frame data into the transmit FIFO.
A multicopy transmission is similar to the unicopy transmission, except that the port vector has multiple bits set, designating the multiple ports from which the data frame will be transmitted. The frame pointer is placed into each of the appropriate output queues 58 and transmitted by the appropriate transmit MAC units 20 b, 24 b, and/or 30 b.
The free buffer pool 64, the multicopy queue 60, the reclaim queue 66, and the multicopy cache 62 are used to manage use of frame pointers and re-use of frame pointers once the data frame has been transmitted to its designated output port(s). In particular, the dequeuing logic 76 passes frame pointers for unicopy frames to the free buffer queue 64 after the buffer contents have been copied to the appropriate transmit FIFO.
For multicopy frames, the port vector FIFO 56 supplies multiple copies of the same frame pointer to more than one output queue 58, each frame pointer having a unicopy bit set to zero. The port vector FIFO 56 also copies the frame pointer and the copy count to the multicopy queue 60. The multicopy queue 60 writes the copy count to the multicopy cache 62. The multicopy cache 62 is a random access memory having a single copy count for each buffer in external memory 36 (i.e., each frame pointer).
Once the dequeuing logic 76 retrieves the frame data for a particular output port based on a fetched frame pointer and stores the frame data in the transmit FIFO, the dequeuing logic 76 checks if the unicopy bit is set to 1. If the unicopy bit is set to 1, the frame pointer is returned to the free buffer queue 64. If the unicopy bit is set to zero indicating a multicopy frame pointer, the dequeuing logic 76 writes the frame pointer with a copy count of minus one (−1) to the multicopy queue 60. The multicopy queue 60 adds the copy count to the entry stored in the multicopy cache 62.
When the copy count in multicopy cache 62 for the frame pointer reaches zero, the frame pointer is passed to the reclaim queue 66. Since a plurality of frame pointers may be used to store a single data frame in multiple buffer memory locations, the frame pointers are referenced to each other to form a linked-list (i.e., chain) of frame pointers to identify the stored data frame in its entirety. The reclaim queue 66 traverses the chain of buffer locations identified by the frame pointers, and passes the frame pointers to the free buffer queue 64.
The foregoing description of the switch architecture provides an overview of the switch operations in a packet switched network. A more detailed description of the features of the present invention as embodied in the multiport switch 12 will now be provided. First, the architecture of an exemplary expansion port 30 will be discussed, followed by the details for transferring data between switches 12.
The present invention is directed to a network switch with capability to support VLANs through the use of an internal rules checker 40 (IRC) to provide high data throughput. As described previously, the switch subsystem 42 provides the switching logic for receiving and forwarding frames to the appropriate output port(s). The forwarding decisions, however, are made by the IRC 40 located on the multiport switch 12.
As previously indicated with respect to FIG. 3, the IRC 40 is responsible for making frame forwarding decisions, in part, by generating a forwarding descriptor. Towards this end, the IRC 40 contains an address table for MAC addresses (which may be unicast, or multicast ), along with VLAN associations and port vectors. Upon receipt of a frame header from one of its input ports, the IRC 40 searches the address table for matching MAC addresses and learns the network configuration based upon a MAC source address (SA) with receive port number and VLAN lookup. The forwarding decision is then made according to the DA and the VLAN association, resulting ultimately in the output of a forwarding descriptor. The IRC 40 passes the generated forwarding descriptor that includes the frame type and an operational code (opcode) to PVF 56 (FIG. 3). The PVF 56 is responsible for creating a new opcode that instructs the dequeuing logic 76 to add, remove, modify the VLAN tag, or send the frame unmodified. VLANs provide "broadcast domains" whereby broadcast traffic is kept "inside" the VLAN. For example, specific VLAN may contain a group of users at a high level of an organization. When sending data to this group of users, the data may include a specific VLAN identifier associated with this particular group to ensure that only these users receive the data.
According to the exemplary embodiment of the invention illustrated in FIG. 4, the IRC 40 includes four functional logic blocks, namely an ingress rules engine 101, a source address (SA) lookup engine 103, a destination address (DA) lookup engine 105, and an egress rules engine 107. In the exemplary embodiment, the four engines 101, 103, 105, and 107 are employed as separate logic devices. In other words, each engine is designed in a modular fashion to receive input from other devices and to perform its particular functions without relying on processing logic from another logic engine. Advantageously, this modular architecture allows changes to be made to any of the particular logic engines without affecting other parts of the decision making process. However, in alternative configurations, the individual functions performed by each logic engine, discussed in detail below, as well as the particular number of logic engines may be modified, based on the particular network requirements.
The IRC 40 also includes address table 84. In alternative embodiments, the address table 84 may be located outside the IRC 40 within another part of the multiport switch 12 or even external to the multiport switch 12. However, in the exemplary embodiment, the address table 84 is located within the IRC 40 and is coupled to the SA lookup engine 103 and the DA lookup engine 105. According to this exemplary embodiment, the address table 84 supports 4096 user addresses and capabilities for 64 unique VLANs. However, the number of addresses and VLANs supported may be increased by expanding the table size.
As shown in FIG. 4, the host CPU 32 functions as the management entity and is connected to the IRC 40 via the CPU interface (IF) 50. Alternatively, a management MAC may be connected to the CPU IF 50 to function as the management entity. The CPU IF 50 allows the host CPU 32, among other functions, to directly access the configuration and status registers 52 and permits communication between the IRC 40 and the host CPU 32. The IRC 40 is responsible for initializing the values in the address table 84. The IRC 40 uses the specific fields of the address table 84 to make frame forwarding decisions when frames are received in the switch 12. More specifically, the DA lookup engine 105 searches the address table 84 for frame forwarding information. From the information found in the address table 84, the IRC 40 creates a forwarding descriptor, which includes the frame pointer, the forwarding port vector, the receive port number, the VLAN identifier (ID), the priority class and a control opcode. An exemplary format of the forwarding descriptor is described in FIG. 6. The IRC 40 then transmits the forwarding port vector to the port vector FIFO 56 for queuing, as shown in FIG. 3.
The host CPU 32 is also responsible for programming the 64 12-bit VLAN IDs in the VLAN index to VLAN ID table 86. The host CPU 32 may also assign a port-based VLAN ID to each port. Accordingly, the CPU 32 must program the VLAN Port-to-Index table 88. The IRC 40 uses VLAN Port-to-Index table 88 to assign a VLAN ID to a frame that is received without a VLAN tag.
The VLAN index field is a 6-bit field used to reference a 12-bit VLAN ID. A VLAN index-to-VLAN ID table 86, shown in FIG. 4, contains the mapping associations. The switch 12 receives both tagged and untagged frames. When the switch 12 receives untagged data frames, i.e., without VLAN tag information, the IRC 40 assigns a VLAN index from a VLAN port-to-index table 88, based on the receive port on which the frame is received. The VLAN index-to-ID table 86 and the VLAN port-to-index table 88 are located with the configuration and status registers 52. However, in alternative configurations, the tables 86 and 88 may be located within the IRC 40.
According to the exemplary embodiment, the IRC 40 also includes a logically separate 4-deep rules queue 120 allocated for each receive port, i.e., the queue corresponding to each receive port holds four frame headers. However, in alternative configurations, the rules queue 120 may be configured to store other numbers of frame headers for each port, based on the particular network requirements. The rules queue 120 "snoops" on the write bus 69 to external memory 36 to capture the first 40 bytes of frame data transferred by queuing logic 74 to the buffers in external memory 36. When a frame has been completely transferred to external memory 36, the queuing logic 74 signals the end of the transfer and provides frame status information indicating whether the frame was received at the switch 12 without errors.
The IRC 40 also includes IRC scheduler 122, as shown in FIG. 4, which monitors the signaling from queuing logic 74 and stores the frame status information in the rules queue 120 along with the corresponding frame header. When the end of frame (EOF) transfer has been signaled by the queuing logic 74, the IRC scheduler 122 enables the processing of the frame header through the ingress rules engine 101. Logic engines 101, 103, 105, and 107, as discussed previously, are separate logic devices and are able to process data frames in parallel, thereby increasing data throughput as compared to systems which employ a single decision making device. In other words, each logic engine is able to perform its respective processing on a different data frame simultaneously with the other respective logic engines. Advantageously, the data throughput of the multiport switch 12 including engines 101, 103, 105, and 107 may increase up to fourfold, as compared to a network switch that employs a single decision making device, since four data frames may be processed simultaneously. The operation of each logic engine, according to the exemplary embodiment, will be described below.
When an overflow state of any of the rules queues 120 is detected by the IRC 40, overflow logic 121 allows frame pointers to bypass engines 101, 103, 105, and 107. The overflow logic 121 comprises multiple overflow registers (not shown) that are allocated to different receive ports of the switch 12. For example, overflow registers, designated as registers 1 to 12, may be provided to support 10/100 MAC ports 1-12; overflow register 13 may be arranged for frame pointers associated with data received via the gigabit MAC port 24. Further, overflow register 14 may be assigned to the expansion port 30. Each of the entries of the overflow register is capable of storing a single 13-bit frame pointer associated with data received via the corresponding receive port. The IRC 40, thus, outputs an overflow (OVFL) descriptor based upon the frame pointers that bypassed the engines 101, 103, 105, and 107.
The ingress rules engine 101 performs a variety of pre-processing functions for each frame header. For example, ingress rules engine 101 checks to see if a data frame was received with errors by reading the frame status information stored with the respective frame headers in rules queue 120. When the ingress rules engine 101 determines that a receive error has occurred, the ingress rules engine 101 constructs a forwarding descriptor with a null port vector, e.g., a port vector with all zeros or some other predetermined value, that will cause the frame to be discarded. Optionally, frames with errors may be forwarded to the host CPU 32 for diagnostic purposes. However, in either case, the ingress rules engine 101 transmits the forwarding descriptor with the null port vector directly to the port vector FIFO 56, without processing by engines 103, 105 and 107. Advantageously, this saves processing time associated with performing searches of the address table 84 for a data frame that contains erroneous data.
The ingress rules engine 101 also checks the destination address (DA) of the frame to determine if the frame should be sent to the management entity, e.g., host CPU 32. Specifically, the ingress rules engine 101 looks for Bridge Protocol Data Units (BPDUs), Generic Attribute Registrations Protocol (GARP) frames, MAC Control Frames and frames with certain Physical MAC addresses. The ingress rules engine 101 identifies these types of frames based on their specific destination address information. When the ingress rules engine 101 detects a match with one of the above DAs, the ingress rules engine 101 constructs a forwarding descriptor identifying the management port. The ingress rules engine 101 then transmits the forwarding descriptor directly to the port vector FIFO 56, bypassing engines 103, 105, and 107.
If the SA lookup engine 103 finds an address entry whose address and VLAN index match the SA and VLAN index of the frame. If the SA lookup engine 103 does not find a match and learning is enabled, the SA lookup engine 103 constructs a new entry in the IRC address table 84 using the information from the received frame.
After the SA lookup engine 103 completes the search and adds a new entry, if necessary, the DA lookup engine 105 performs a search of the address table 84. Specifically, the DA lookup engine 105 searches the address table 84 for an address entry whose address and VLAN index match the destination address (DA) and VLAN index of the frame. The DA lookup engine 105, in an exemplary embodiment, uses a 12-bit hash function circuit (not shown) to generate a 12-bit hash key for the DA/VLAN index search. If a match is found, the DA lookup engine 105 uses the port vector field of the address entry and passes the port vector field information to the egress rules engine 107. When the DA lookup engine 105 cannot find a DA/VLAN index match, the frame must be "flooded" to all members of the VLAN. In this case, the DA lookup engine 105 sets the port vector to indicate that all ports are to transmit the frame. The port vector field is a 15-bit field that identifies each port(s) that should receive the data frame for transmission to its destination address. Bit 0 of the port vector field corresponds to Port 0 (the management port), bits 1-12 correspond to MAC ports 1-12 respectively (the 10/100 Mb/s ports), bit 13 corresponds to the gigabit port 24 and bit 14 corresponds to the expansion port 30.
FIG. 5 shows a flow diagram of the generation of a forwarding descriptor by the IRC 40 according to the present invention. In general, a port vector undergoes a series of checks that modifies the port vector so that a proper port vector is captured in a forwarding descriptor sent to the PVF 56. These series of checks are performed in a pipelined and concurrent fashion, thereby markedly reducing the number of clock cycles required to generate the forwarding descriptor over a traditional forwarding logic architecture. That is, the IRC 40 ensures that the data frame is sent out from the proper output ports. As in step 501, a port vector is output from the DA lookup engine 105. As previously discussed, the DA lookup engine 105 outputs the port vector, which reflects where the data frame should be transmitted as dictated by the destination address in the header of the data frame. Thus, the port vector begins at this state and is subsequently modified according to other criteria and parameters associated with the proper forwarding of the data frame. In step 503, the egress rules engine 107 checks the spanning tree state to determine whether frames received from the port should be filtered. Spanning tree is an algorithm that removes loops in the network for proper operation. The egress rules engine 107 determines which ports are valid "forwarding" ports, which conform with the spanning tree algorithm (e.g., IEEE 802.1d). Thus, the port vector is accordingly modified to mask out ports that fail the spanning tree check; the port vector is logically "AND" with the determined forwarding ports so as to mask the ports that have been blocked. Next, the received port, as in step 505, is eliminated from the port vector by masking the received port with the port vector. It should be noted that if the received port were part of a trunk group that is eliminated (which is discussed below), complete trunk group is also masked. This masking of the received port prevents the scenario whereby a data frame is received at a particular port and is sent out through that same port.
Steps 507 and 509 mask from the port vector a cascade port (CP) from the port vector to prevent the data frame from unnecessarily circulating among the cascaded switch module configuration (as shown in FIG. 1. In this scenario, a number of switches 12 a, 12 b, and 12 c are cascaded (FIG. 1) via their respective expansion ports 30. In step 507, IRC 40 checks whether the data frame was received at the cascade port (i.e., expansion port) and that the cascade port belongs to a switch 12c that is "last" in the cascaded loop. If this is so, as in step 509, the port vector is masked with the cascaded port.
Next, the IRC 40 checks whether the port vector conforms with the results of a "trunking" algorithm (step 511). The switch 12 supports up to 3 independent trunks, each of which can consist of two to four ports. The 10/100 Mbs ports are divided into three trunk blocks consisting of ports 1-4, ports 5-8, and ports 9-12. Within each trunk block any two to four adjacent ports, for example, can be combined into one trunk. The purpose of sing is to load balance across the trunk ports. If the DA look engine 105 determines that a frame should be transmitted through a port that is part of a trunk, the IRC 40 performs a calculation (the trunk mapping function) on the frame's address fields to determine which of the trunk links to use. This may result in a frame being forwarded through a port that is different from the port indicated by the DA lookup engine 105. If any of the bits that are set in the port vector corresponds to a trunk port, the IRC 40 masks out all bits that correspond to ports in that trunk and then sets the bit corresponding to the port selected by the trunk mapping function. In other words, the IRC 40 masks the port vector to account for redirecting the frame according to the trunking algorithm.
Steps 513, 515, and 517 execute the VLAN ingress rules check. In particular, the ingress rules engine 105 checks the VLAN member set for each output port. The IRC 40 examines the bit that corresponds to the frame's VLAN index in the VLAN member set table entry that corresponds to the output port, per step 513. If this bit is not set, the IRC 40 accordingly masks that port from the port vector (step 515). This check is performed for every port that is set in the port vector; as in step 517, the IRC 40 checks whether the bit that is being checked corresponds to the last port in the port vector. Step 517 essentially ensures that the IRC 40 checks every bit of the port vector.
The ingress rules engine 105 provides a "sniffer port", which allows a probe connected to a port to monitor network activity on the other ports. Accordingly, steps 517 and 521 account for the sniffer port in the port vector. This sniffer port may be any port within the switch 12. The sniffed ports may be any port except the port associated with management queue 68.
The remaining steps of FIG. 5 involve the generation of the other fields of the forwarding descriptor. In step 523, the IRC 40 maps the VLAN index to the VLAN ID and inserts it into the forwarding descriptor. Next the IRC 40 determines whether an overflow (OVFL) descriptor exists, per step 525. If an OVFL descriptor exists, the IRC 40 immediately sends the OVFL descriptor to the PVF 56, per step 527. Otherwise, the IRC 40 sends the forwarding descriptor to PVF 56 (step 529).
An exemplary format of a forwarding descriptor is shown in FIG. 6. The first field is a 1-bit priority class field, which indicates priority of the output queues to which the frame pointer should be sent. As previously indicated, the 15-bit port vector field is a bit map that specifies the port or ports designated to transmit the frame. The forwarding descriptor also contains, in one embodiment, a 4-bit receive port field that indicates the particular port within the switch 12 from which the frame was received. Another field includes a 12-bit VLAN ID that is associated with the frame; the dequeuing logic 76 may have to create a VLAN tag header with this identifier. In addition, the forwarding descriptor includes an operation code (opcode) field, which is 11-bits in length. The opcode field contains instructions that are used by the PVF 56 and the dequeuing logic 76 to determine operations that need to be performed on the frame before transmission. The opcode also has information used by management software to determine why a frame was forwarded to the management queue 68. Lastly, the forwarding descriptor has a 13-bit frame pointer field; this field provides the location of the frame in external memory 36.
As described above, the system and method for generating a forwarding descriptor in a network interface device utilizes logic engines 101, 103, 105, and 107, which are designed as separate logic devices and are able to process data frames independently. For example, the egress rules engine 107 may process a first frame while the DA lookup engine 105 is processing a second frame, the SA lookup engine 103 is processing a third frame and the ingress rules engine 101 is processing a fourth frame. This concurrent operation advantageously reduces switch latency. In addition, the throughput of the disclosed switch, which employs a pipelined architecture for its rules checker logic is increased largely as a result of a reduction in the number of clock cycles associated with the generation of the forwarding descriptor. Another advantage of the invention is that the modular architecture of the IRC 40 enables changes to be made to one of the logic engines without affecting the other logic engines. For example, when changes to the ingress rules engine 101 are desired, the changes may be made without causing corresponding changes to any of the engines 103, 105 or 107. Accordingly, the desired changes may be made in an efficient manner while minimizing the complexity of the changes.
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
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nForce 4 corrupting data written to HDD
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Re: nForce 4 corrupting data written to HDD
Folks, I have a HP Pavilion a1610n ( ADM dual core, 4 gig RAM) with the nVidia Corporation C51 chip, running ubuntu 8.04 and 8.10 with lots of file corruption problems (think its IDE/SATA controller). I am running the iomenu=soft and meme=1g switches from grub, still getting frequent file corruption. Every third boot, I need to run fsck on linux partitions, the files being corrupted are predictable (ie files: iso-8, gnom, multiple gnome-schema files, gnome win manager corruption). I initially just had 2 SATA drives, after reading multiple ubuntu posts went ahead and installed an IDE drive as boot disk, things got better (ie: Linux started). I started to install a second SATA controller card (VIA VT6421A), I see the migrated second SATA drive, but boot-up only recognized the drives on C51 chip (1-IDE, 1-SATA). In addition, the rev on the C51 chip appears very low (IDE & SATA - rev a1; USB Controller Rev a3 )??. I am not running raid, just simple ext3 file storage and two NTFS partitions. Under one syslog booting from the 19.24 kernel, it says I have a nForece2 chip
SO, I WANTED TO SEE IF THERE WAS A FIX TO THE C51 CHIP, MAYBE A FLASH OR UPDATE FIRMWARE. This is a key before moving ahead fully with VIA card. I am running the latest HP BIOS for the box under ubuntu 8.10, it did not help.
Any suggestions?? If it involves a patch to the kernel, pls give details instructions to follow (how apply tar/gz file) Would like to have XP patch also, have dual boot OS's here.
NOTE: I think the chip issues and heavy disk load factor was pointed out in the past by an IBM person perhaps on the KML link above ( but how to fix?).
Nvidia, I also have a Geforce 7600GT on this box with dual screen, I FELL THE PAIN on both sides here. I can not get the 180 for 185 video drivers working under Ubuntu, but the 177 drivers did work fine. Why you folks and ubuntu people cannot streamline these video install is beyond me; restricted drivers, tainted kernel, Xorg.conf conflicted settings...blaahh..blaahha. (who else is buying your high end video card, besides linux uses; Mac use have them already, MS users deaf and dump...maybe Xbox folks?). Look at this Ubuntu forum posting #7446864, its 90 pages long!
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Limited Brands Reports January 2013, Fourth Quarter 2012 And Fiscal Year 2012 Sales; Updates Fourth Quarter Earnings Guidance PR Newswire COLUMBUS, Ohio, Feb. 7, 2013 COLUMBUS, Ohio, Feb. 7, 2013 /PRNewswire/ --Limited Brands, Inc. (NYSE: LTD) reported comparable store sales for the five weeks ended Feb. 2, 2013 increased 9% compared to the five weeks ended Feb. 4, 2012. The Company reported net sales of $986.4 million for the five-week period ended Feb. 2, 2013 compared to sales of $774.5 million for the four-week period ended Jan. 28, 2012. The fifth week in January 2013 represented approximately $125 million in sales. (Logo: http://photos.prnewswire.com/prnh/20020520/CLM001LOGO ) Comparable store sales for the 14 week fourth quarter ended Feb. 2, 2013 increased 5% compared to the 14 weeks ended Feb. 4, 2012. Net sales were $3.856 billion for the 14 week fourth quarter ended Feb. 2, 2013 compared to $3.515 billion for the 13 weeks ended Jan. 28, 2012. The Company reported a comparable stores sales increase of 6% for the 53 week year ended Feb. 2, 2013, compared to the 53 weeks ended Feb. 4, 2012. Net sales were $10.459 billion for the 53 week year ended Feb. 2, 2013 compared to $10.364 billion for the 52 weeks ended Jan. 28, 2012. Fourth quarter 2011 and 2011 full year sales included $13.1 million and $702.4 million attributable to the third party apparel sourcing business, which was sold in November 2011. The Company is comfortable with the current street consensus estimate for 2012 fourth quarter adjusted earnings per share of $1.73. To hear further commentary provided on Limited Brands' prerecorded January sales message, call 1-866-639-7583 (1-866-NEWS-LTD), or log onto www.Limitedbrands.comfor an audio replay. The company will release its fourth quarter earnings after the close of the market on Feb. 27, and hold its conference call at 9 a.m. Eastern Time on Feb 28. ABOUT LIMITED BRANDS: Limited Brands, through Victoria's Secret, Pink, Bath & Body Works, La Senza and Henri Bendel, is an international company. The company operates 2,619 specialty stores in the United States and its brands are sold in more than 700 company-operated and franchised additional locations world-wide. The company's products are also available online at www.VictoriasSecret.com, www.BathandBodyWorks.com, www.HenriBendel.com and www.LaSenza.com. Limited Brands b-roll footage of stores is available through our online newsroom. Safe Harbor Statement Under the Private Securities Litigation Reform Act of 1995 Limited Brands, Inc. cautions that any forward-looking statements (as such term is defined in the Private Securities Litigation Reform Act of 1995) contained in this press release or the January sales call involve risks and uncertainties and are subject to change based on various factors, many of which are beyond our control. Accordingly, our future performance and financial results may differ materially from those expressed or implied in any such forward-looking statements. Words such as "estimate," "project," "plan," "believe," "expect," "anticipate," "intend," "planned," "potential" and any similar expressions may identify forward-looking statements. Risks associated with the following factors, among others, in some cases have affected and in the future could affect our financial performance and actual results and could cause actual results to differ materially from those expressed or implied in any forward-looking statements included in this press release or the January sales call: ogeneral economic conditions, consumer confidence, consumer spending patterns and market disruptions including severe weather conditions, natural disasters, health hazards, terrorist activities, financial crises, political crises or other major events, or the prospect of these events; othe seasonality of our business; othe dependence on a high volume of mall traffic and the possible lack of availability of suitable store locations on appropriate terms; oour ability to grow through new store openings and existing store remodels and expansions; oour ability to successfully expand into international markets and related risks; oour independent licensees and franchisees; oour direct channel business; oour failure to protect our reputation and our brand images; oour failure to protect our trade names, trademarks and patents; othe highly competitive nature of the retail industry generally and the segments in which we operate particularly; oconsumer acceptance of our products and our ability to keep up with fashion trends, develop new merchandise and launch new product lines successfully; oour reliance on foreign sources of production, including risks related to: opolitical instability; oduties, taxes and other charges on imports; olegal and regulatory matters; ovolatility in currency exchange rates; olocal business practices and political issues; opotential delays or disruptions in shipping and related pricing impacts; othe disruption of imports by labor disputes; and ochanging expectations regarding product safety due to new legislation; ostock price volatility; oour failure to maintain our credit rating; oour ability to service our debt; oour ability to retain key personnel; oour ability to attract, develop and retain qualified employees and manage labor costs; othe inability of our manufacturers to deliver products in a timely manner and meet quality standards; ofluctuations in product input costs; ofluctuations in energy costs; oincreases in the costs of mailing, paper and printing; oclaims arising from our self-insurance; oour ability to implement and maintain information technology systems; oour failure to comply with regulatory requirements; otax matters; and olegal and compliance matters. We are not under any obligation and do not intend to make publicly available any update or other revisions to any of the forward-looking statements contained in this press release or the January sales call to reflect circumstances existing after the date of this press release or to reflect the occurrence of future events even if experience or future events make it clear that any expected results expressed or implied by those forward-looking statements will not be realized. Additional information regarding these and other factors can be found in "Item 1A. Risk Factors" in our 2011 Annual Report on Form 10-K. LIMITED BRANDS JANUARY 2013 Comparable Store Sales Increase (Decrease) (Comparable Calendar Basis): January January Fourth Fourth Year Year Quarter Quarter 2013 2012 2012 2011 2012 2011 Victoria's Secret 8% 17% 3% 12% 7% 14% Stores Bath & Body Works 10% (3%) 7% 3% 7% 6% La Senza 15% (8%) 0% (3%) (2%) (2%) Limited Brands 9% 9% 5% 7% 6% 10% Victoria's Secret Direct Sales (5%) 3% (1%) 3% 1% 4% Total Sales (Millions): Fourth Quarter Fourth Quarter Year 2012 Year 2011 2012 2011 (53 weeks) (52 weeks) (14 weeks) (13 weeks) Victoria's Secret $ 1,713.4 $ 1,572.2 $ 4,980.6 $ 4,563.9 Stores Victoria's Secret 534.0 518.8 1,593.2 1,557.5 Direct Total Victoria's $ 2,247.4 $ 2,091.0 $ 6,573.8 $ 6,121.4 Secret Bath & Body Works $ 1,249.6 $ 1,127.9 $ 2,902.2 $ 2,674.3 La Senza $ 102.4 $ 119.4 $ 355.5 $ 414.9 Other $ 256.2 $ 177.1 $ 627.2 $ 1,153.4 Limited Brands $ 3,855.6 $ 3,515.4 $ 10,458.7 $ 10,364.0 Total Company-Operated Stores: Stores Stores Operating Year-to-date Operating at 1/28/12 Opened Closed at 2/2/13 Victoria's Secret Stores 1,017 22 (20) 1,019 Bath & Body Works 1,587 4 (20) 1,571 Henri Bendel 19 10 - 29 Total United States 2,623 36 (40) 2,619 La Senza Canada 230 - (72) 158 Bath & Body Works Canada 69 3 (1) 71 Victoria's Secret Canada 19 7 - 26 Victoria's Secret UK - 2 - 2 Total Limited Brands 2,941 48 (113) 2,876 SOURCE Limited Brands, Inc. Website: http://www.Limitedbrands.com Contact: Limited Brands: Investor Relations, Amie Preston, +1-614-415-6704, firstname.lastname@example.com; Media Relations, Tammy Roberts Myers, +1-614-415-7072, email@example.com
Limited Brands Reports January 2013, Fourth Quarter 2012 And Fiscal Year 2012 Sales; Updates Fourth Quarter Earnings Guidance
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On September 4 1987, Madonna performed "Causing A Commotion" live via satellite from the Stadio Communale in Turin, Italy, during the "Who's That Girl World Tour" and won Best Female Video for "Papa Don't Preach" at the 4th annual MTV Video Music Awards at the Universal Amphitheatre in Los Angeles, California.
Tag Archives: Papa Don't Preach
Today In Madonna History: July 26, 1986
On July 26 1986, "Papa Don't Preach" spent its third and final week at number-one on the UK singles chart. It was certified Gold by BPI on August 1st, 1986 for shipment of over 500,000 copies, based on certification thresholds at that time. With a chart run extending for 15 weeks, the single ranked #8 overall in the UK's year-end charts tally.
The song was a massive hit across Europe, topping the Eurochart for an incredible eleven week stretch from August 2nd through October 11th, 1986 when it was finally overtaken by none other than Madonna herself with the follow-up single, "True Blue."
Although "Justify My Love" is often cited as being the first-ever video single, it is interesting to note that it was actually not the first Madonna music video to be marketed commercially as a single. Possibly an attempt to cash-in on the success and controversy surrounding "Papa Don't Preach" or more likely as a means of testing out new marketing possibilities for a hybrid laserdisc/cd format, Warner issued limited quantities of "Papa Don't Preach" as a CD Video in the US, UK and Japan containing three audio tracks along with the music video. Perhaps anticipating the limited appeal of the format, Warner did not bother modifying the track-listing to include the appropriate b-sides in either the UK ("Ain't No Big Deal") or Japan ("Think Of Me"), instead opting to issue the US b-side ("Pretender") on all three pressings. Stranger still was the release date – 1988 – two years after the standard single hit stores. Needless to say, this early attempt to market a music video single did not stir public interest the way it would in 1990, and the concept went into hibernation mode until Madonna gave audiences a video single they were willing to pay for.
Today in Madonna History: July 11, 1987
Today in Madonna History: June 30, 1986
On June 30 1986, Madonna's "True Blue" album was released by Sire Records. She worked with Stephen Bray and Patrick Leonard on the album while co-writing and co-producing all the songs.
"True Blue" was an immediate global success, reaching number one in then record-breaking 28 countries across the world, including Australia, Canada, France, Germany, the United Kingdom and the United States. It spent 34 consecutive weeks at the top of the European Top 100 Albums chart, longer than any other album in history. It became the world's top-selling album of 1986, as well the biggest selling album of the 1980s by a woman and remains one of the best-selling albums of all time with sales of more than 25 million copies worldwide. All five singles released from the album reached the top five on theBillboard Hot 100, with "Live to Tell", "Papa Don't Preach", and "Open Your Heart" peaking at number one.


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Middlesbrough defender Emanuel Pogatetz believes the ŌĆśBoro defence is to blame for conceding three goals to Bolton on the weekend.
The Austria international admitted the defensive team were down on usual performances.
ŌĆ£To concede three at home should not happen, on the defensive side it wasnŌĆÖt good enough and it was all the defenceŌĆÖs fault,ŌĆØ Pogatetz said.
ŌĆ£The defence has played well in recent games but we were to blame. It should never happen to concede three at home.
ŌĆ£I blame myself for that third goal, I take full responsibility for it and it was poor defending on my part. I should have one better.
ŌĆ£In fact the whole afternoon I wasnŌĆÖt at my best but itŌĆÖs how I react that counts. I have to work hard to get back into my normal form.ŌĆØ


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Please enter a valid mileage
Curious about the newer model? Check out the 2015 Kia Sedona
By KBB.com Editors
The Sedona minivan is a consumer's best friend and a nightmare for rival manufacturers. In just a few short years, Kia has transformed the Sedona from a middle-of-the-road minivan into a first-rate transport. With class-leading horsepower and safety ratings, seating for eight and a 10-year/100,000-mile powertrain warranty, it's hard to argue with the Sedona. Toss in a sticker price thousands less than a comparably-equipped Honda Odyssey or Toyota Sienna and the Sedona looks downright unbeatable. Of course, the Sedona's resale figures can't compare with its Japanese rivals, but if the initial bottom line is more important than what you might get come trade-in time, the Sedona should be at the top of your shopping list.
If you like saving money but won't sacrifice very much to do so, you'll be excited to see just how well the all-new Sedona stacks up against some of the category's finest.
The Sedona's up-front collection of knobs and buttons isn't as attractive as some of its competitors' and its biggest disadvantage is its mediocre (but improving) resale value.
A short wheelbase model joins the long wheelbase LX and EX models.
Driving Impressions Impressive cornering limits (which will rarely, if ever, be explored in the real world) combine with a powerful engine and smooth-shifting five-speed automatic transmission to provide an around-town eagerness that...makes the Sedona as enjoyable to drive as any minivan on the road. It's also pleasant enough on the highway, with comfortable seating and interior noise levels that allow for easy three-row conversations.
7.1 Surround Sound System
An available 13-speaker, 660-watt Infinity audio system features front- and second-row center-channel speakers and delivers impressive music and movie performance.
Sportmatic Transmission
Even though it isn't the most responsive manu-matic transmission, the ability to choose your own gears will be especially welcomed by those that also appreciate the Sedona's relatively eager handling.
The Sedona's seven-passenger layout consists of two removable, reclining captain's chairs with a one-touch fold-and-flip function that allows for easy access to a three-passenger third row; when you've got more cargo than people to transport, the 60/40-split third row folds flat into the floor. Highlights include second-row opening windows and a multitude of storage options like dual glove boxes. Shortcomings consist of a gauge cluster that's unexciting, a center control panel that's uninspired and available wood-look trim that's reminiscent of wood-paneled wagons and dens from the Brady Bunch era. That our loudest grumblings relate to relatively minor matters of interior aesthetics is indicative of just how far the Sedonaand Kiahave come.Exterior
Except for its vertical taillamps, the Sedona doesn't carry itself much differently than a Toyota Sienna, which wouldn't be impossible to mistake for a Honda Odyssey. The Kia is also about the same size as those competitors, if not a little longer, taller and wider than both. Sedona EX trims are differentiated externally from entry LX versions by 17-inch aluminum wheels (versus 16-inch covered steel wheels), fog lights and roof rails.
In addition to a 3.8-liter V6 and a five-speed automatic transmission, the base Sedona LX includes tri-zone air conditioning, power locks, power mirrors, power first- and second-row windows, dual sliding rear doors, cruise control, AM/FM/CD sound system, second-row captain's chairs, remote keyless entry, tilt steering wheel, cloth interior, 16-inch covered steel wheels and several storage compartments. An impressive list of standard safety equipment includes front, front-side and three-row side-curtain airbags, advanced anti-lock brakes (ABS), tire pressure monitoring system, electronic stability control and traction control.
Stepping up to the Sedona EX adds fog lights, power driver's seat, heated mirrors, AM/FM/Cassette/CD/MP3 stereo system, auto-dimming rearview mirror, HomeLink, leather-wrapped steering wheel and shift knob, power third-row vent windows, compass, roof rack, 17-inch alloy wheels and wood-like trim that's contained to the center of the dash. Options available only on EX models include leather seating, heated front seats, driver's position memory, sunroof, power sliding doors and liftgate, power-adjustable pedals, front-row automatic climate control, steering wheel-mounted audio controls, an Infinity 7.1 surround sound system with an in-dash six-CD changer and rear DVD entertainment system with two wireless headsets. There's also a less sophisticated rear DVD entertainment system that's available on both LX and EX models.
The Sedona's 24-valve, all-aluminum powerplant with continuously variable valve timing makes it one of the most powerful minivans on the road. Combined with a responsive five-speed automatic transmission, the Sedona merges, passes and deals with traffic with ease, whether it's on the highway or headed to the supermarket.
3.8-liter V6
244 horsepower @ 6000 rpm
253 lb.-ft. of torque @ 3500 rpm
EPA city/highway fuel economy: 18/25
To compare current market prices, check out KBB.com's car classifieds to view the new and used Kia Sedona vehicles for sale near you.
Based on 342 Ratings for the 2006 - 2014 models.Review this car
By tap58 on Monday, April 13, 2015
I own this car - My approximate mileage is 91,000overall rating 10 of 10rating details
Pros: "Great Value, great performance"
Cons: "None"
Likely to recommend this car? (1-10): 10
"I totalled my first Sedona and bought an identical car to replace it. I have never been sorry. Only problems were minor (radio stopped working and bad battery) which were both replaced for free within the first year I owned the car. Since then NO issues. Both my daughters have Toyota Siennas which are great cars, but I would take the Kia over them in a heartbeat."
6 people out of 11 found this review helpful
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By Pinky on Thursday, January 22, 2015
I own this car - My approximate mileage is 156,000overall rating 9 of 10rating details
Pros: "Power/comfort drivability"
Cons: "leak / sliding door issues"
Likely to recommend this car? (1-10): 9
"Always dependable...has been to Florida & Maine without an issue. At 65 mph+ avg.26 mpg.Comfortable in all 7 seats! Good power. Moved mowers, college students and friends...plenty of room in & on this vehicle. DVD player, CD and power heated seats worked flawless for the past 8 years. Local driving only averages 19 mpg, one power sliding door was always a problem after first year and sun roof leaked in pouring rain."
14 people out of 24 found this review helpful
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By CD on Thursday, January 15, 2015
I own this car - My approximate mileage is 11,000overall rating 10 of 10rating details
Pros: "Good price, lots of whistles & bells, good gas mil"
Cons: "Rear door isn't electric"
Likely to recommend this car? (1-10): 10
"I never expected to own a van but I had no other choice in order to continue driving by myself after I needed to start using an electric wheelchair because of being on oxygen. My Sedona was retrofitted with a hydraulic lift, accessible from the rear door. By being able to use the rear row, which came with easily removable seats, I was able to maintain ample space for 4 passenger The seats in the middle row will still roll up and secure against the backs of the front seats if extra storage is needed, but they aren't removable. The backup camera is extremely useful. Especially when backing in to park when I want to access the rear door to use the lift. After driving it, I know I would be just as happy with this vehicle even if I didn't have to have a van. Some of the things I like are: cruise and stereo controls on the steering wheel, Sirius Radio, Blue Tooth, lots of storage in the dash, a tray with built in cup holders between the front seats that can be folded down when not in use, extra cup holders in the front and side doors, separate front and rear heat and cooling system, rear window wiper and defroster. I'm sure there are others I'm just not thinking of right now."
4 people out of 11 found this review helpful
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By bye bye kia on Saturday, January 10, 2015
I own this car - My approximate mileage is 110,000overall rating 6 of 10rating details
Pros: "inexpensive to buy, lots of included features"
Cons: "low resell value, poor quality, not built to last"
Likely to recommend this car? (1-10): 4
"Bye bye Kia, bye bye. i have owned two now and we are done. While I like the value paid for the features provided, the overall quality of the car is not built to last, not to mention the resell value or lack thereof. My high level advice, figure on getting a hundred thousand miles out of it and then get rid of it. Why? Because stuff will start breaking left and right after that, it will always be something. The car becomes a bit of a money pit and a major inconvenience. The parts for it are not cheap either. I can't tell you how many times I have replaced the headlight bulbs at $25 a pop, and I'm also tired of the different size wiper blades."
21 people out of 42 found this review helpful
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By Jan on Tuesday, January 06, 2015
I own this car - My approximate mileage is 81,000overall rating 10 of 10rating details
Pros: "very comfortable as a van or roomy like a truck"
Cons: "Problem w/horn. Took long time for them 2 find&fix"
Likely to recommend this car? (1-10): 10
"Have had 1 or 2 recalls which were performed at no charge at dealership. Had problems with horn, which they had a hard time locating the problem but it was taken care of under warranty. It turned out to be a loose screw that was located (I think) near the motor mount or something. Have had no problems at all with this vehicle but just some maintenance expense. I love this vehicle. It is the most comfortable vehicle that I have ever had. The motor is so quiet, you hardly notice it is running. I can remove middle two seats and fold rear seats into floor to make huge cargo space. It is like having a truck.More cupholders than a person will ever use. @ 2 glove compartments, tinted windows, back windows roll down. has 4 doors, plus hatchback. Seats 7 very comfortably"
9 people out of 13 found this review helpful
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By Pilgrim on Monday, November 17, 2014
I own this car - My approximate mileage is 105,000overall rating 9 of 10rating details
Pros: "Comparable to the Toyota Sienna in dependability"
Cons: "Inferior carpet."
Likely to recommend this car? (1-10): 10
"It accelerates well, corners well, has roomy interior, nice sound system with USB port which is really nice. It has three 12 volt sockets, two up front and one in the rear, easy fold down seats with a deep well in the very rear for groceries or other purchases. I've gotten as much as 25 mpg on the highway with just two adults, but average city and highway, averages about 17+ mpg (we often carry 6 passengers). We rented a 2014 Dodge van and aside from the automatic doors, we were glad when we got back home into our KIA, which accelerated, stopped, and handled much better than that new Dodge."
33 people out of 59 found this review helpful
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The Surry Runnin' Patriots girls basketball team had four players earn all-conference honors this season.
Sydney Bedsaul, Kaylee Paris, Jessica Boyd and Kesley Cave were recognized for the Patriots, who posted a 17-8 record during the regular season. Surry is part of the N.C. Home Educators Athletic Association.
Bedsaul moved over to the point guard position from the No. 2 spot last year. She averaged 13.8 points, 2.8 assists, 4.8 rebounds and 2.4 steals per game.
Coach Todd Hill said Bedsaul's assist-to-turnover ratio has improved from last season.
"She is playing calmer when things go wrong, and has shown much more patience," Hill said. "She's had more pressure on her, and she's handled it well."
Paris, the team's shooting guard, came back strong after rolling her ankle midway through the season. She averaged 12.7 points, 6.7 rebounds, 3.0 assists and 3.2 steals per game.
"She goes to the rim much stronger than she did early in the year," Hill said. "She led the team in free-throw attempts and she can hit the 3-point shot."
Boyd is listed as a forward/guard, but Hill said she is capable of playing all five positions on the floor. Boyd averaged 12.5 points, 11.3 rebounds, 2.5 assists and 3.8 steals per game. She hit 81 percent from the foul line and drew nine charges this season.
"When (teams) come to the rim, Jessica is going to be there," Hill said. "She sends a message, 'We do protect the paint.'"
Cave played the five position and averaged 9.5 rebounds and 2.0 assists for the Patriots. Cave might not fill up the stat sheet, but she is a huge part of Surry's success on the court.
Cave set a team record for rebounds in a game this year with 24.
"Her nickname is 'Tractor' because she does the work," Hill said. "We ask her to guard the other team's biggest player, and she's 5-foot-8. She's second on the team in charges this year. She anchors our 55 defense. In the zone offense, the more she touches it, the better off we are. She does a good job getting the ball to the wings."
Up next for the Patriots is the East Coast Homeschool Championships in Lynchburg, Va., March 12-15. Surry will play three games in pool play, with the top eight teams out of 32 moving into the tournament round. The Patriots will compete in a pool with Crown Athletics (Ga.), Spirit Athletics (Va.) and Titan TeamSports (Tenn.).
Surry's varsity boys team is also scheduled to compete. They will be in a pool with Easley Guardians (S.C.), Fredericksburg Victory (Va.) and Lynchburg Patriots (Va.).


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BERLIN (AP) — German shipbuilders say Disney's latest cruise ship, the Dream, is leaving their building docks for its harbor where the craft, the largest built in Germany, will undergo testing.
Meyer Werft shipbuilders said Saturday the 1115-foot-long ship is to depart for the Atlantic ocean early next month. The Dream is the first of two crafts to be built for the U.S.-based Disney Cruise Lines.
Measuring 121 feet (37 meters) across, the ship features a water coaster wrapped around the perimeter of its top deck, virtual portholes that offer live views of the sea and sky from video cameras mounted around the ship and a series of lounges for young and adult.
The Dream can hold up to 4,000 passengers and is due to launch in Jan. 2011 and be based out of Port Canaveral.
Disney Dream cruise ship gets first taste of water
In this handout image provided by Disney, the new Disney cruise ship, the Disney Dream, made its very first public appearance Oct. 30, 2010, when it was pulled by tugboat out of the enclosed shipyard building where it was constructed at the Meyer Werft shipyard in Papenburg, Germany. Thousands of local residents gathered for the ceremony which was highlighted by fireworks and Disney characters. (HANDOUT, GETTY IMAGES / October 31, 2010)
- Pictures: Disney Dream cruise ship
- Pictures: Interactive features aboard the Disney Dream
- Disney Cruise Line unveils new stage show, entertainment for Disney Dream
- Pictures: Disney Fantasy cruise ship
- Disney Cruise Line's Castaway Cay
- Pictures: Interactive features aboard the Disney Fantasy
See more photos »
- Cruises
- Tourism and Leisure
- Shipbuilding
See more topics »


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TRS chief's conditional offer to sail with ruling party evokes mixed response
Nizamabad MP Madhu Yaskhi welcomes KCR's statement
Palvai Goverdhan Reddy feels Congress should not ally with TRS
HYDERABAD: Finding themselves without political allies in the run-up to the elections, Congress leaders have reacted cautiously to Telangana Rashtra Samiti president K. Chandrasekhar Rao's statement that he was willing to sail with the ruling party if it came out in support of a separate State.
Amid the moves of the TRS and the TDP to forge an alliance in the next elections to oust the Congress, the latest comment by Mr. Rao has evoked a mixed response.
Some leaders from the region have dismissed as yet another political ploy by the TRS chief and expressed doubts whether he would stick to his stand, while some others have welcomed it.
Those pitching hard for an early solution to the Telangana issue felt that the latest assertion would give a chance for the two parties to revive their ties.
AICC secretary and Nizamabad MP Madhu Yaskhi, who has repeatedly raised the issue of statehood for the region, welcomed the statement.
"We are natural allies and people will believe us rather than the TRS-TDP combine," he observed.
APCC spokesperson B. Kamalakar Rao said if the two parties came together the successful formula of 2004 elections would be replicated. Rajya Sabha member V. Hanumantha Rao wanted APCC president D. Srinivas to meet the high command on the issue.
However, a couple of senior leaders cautioned the party to be wary of the TRS president's double-speak.
Veteran Congress leader Palvai Goverdhan Reddy, who has been critical of Mr. Rao, felt that the Congress should not join hands with him.
AICC secretary P. Sudhakar Reddy questioned the sincerity of Mr. Chandrasekhar Rao's commitment.