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The present invention is directed to improvements to the processor architectures, and more specifically the x86 architecture, to correct shortcomings in processor virtualization. Several embodiment of the present invention are directed to the utilization of at least one virtualization control bit to determine whether the execution of a specific instructions cause a privilege-level exception (e.g., GP0) when executed outside of a privilege ring (e.g., outside of ring-0). Several additional embodiments are directed to the utilization of a virtual assist register to implement at least one virtual assist feature. And several additional embodiments are also directed to utilization of a bit for enabling a virtual protected mode that, when a processor in running in a protected mode, causes said processor, which is otherwise executing as if it is running in protected mode, to execute normally with exceptions to handle special virtualization challenges.
1. A method for improved processor virtualization, said method comprising the utilization of at least one virtualization control bit to determine whether the execution of a specific instructions cause a privilege-level exception (e.g., GP0) when executed outside of a privilege ring (e.g., outside of ring-0).
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6. A system for improved processor virtualization, said system comprising a processor that utilizes at least one virtualization control bit to determine whether the execution of a specific instructions cause a privilege-level exception (e.g., GP0) when executed outside of a privilege ring (e.g., outside of ring-0).
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11. A computer-readable medium comprising computer-readable instructions for improved processor virtualization, said computer-readable instructions comprising instructions for the utilization of at least one virtualization control bit to determine whether the execution of a specific instructions cause a privilege-level exception (e.g., GP0) when executed outside of a privilege ring (e.g., outside of ring-0).
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16. A hardware control device for improved processor virtualization, said device comprising the utilization of at least one virtualization control bit to determine whether the execution of a specific instructions cause a privilege-level exception (e.g., GP0) when executed outside of a privilege ring (e.g., outside of ring-0).
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21. A method for improved processor virtualization, said method comprising the utilization of a virtual assist register to implement at least one virtual assist feature.
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26. A system for improved processor virtualization, said system comprising a processor that utilizes a virtual assist register to implement at least one virtual assist feature.
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31. A computer-readable medium comprising computer-readable instructions for improved processor virtualization, said computer-readable instructions comprising instructions for the utilization of a virtual assist register to implement at least one virtual assist feature.
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36. A hardware control device for improved processor virtualization, said device comprising a virtual assist register to implement at least one virtual assist feature.
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41. A method for improved processor virtualization, said method comprising the utilization of a bit for enabling a virtual protected mode that, when a processor in running in a protected mode, causes said processor, which is otherwise executing as if it is running in protected mode, to execute the following elements:
an external interrupt is not masked but instead cause an virtual machine monitor (VMM) exception to occur;
an attempt to execute an exception instruction causes a virtual machine monitor exception to occur, wherein an exception instruction is one of a set of exception instructions comprising at least one of the following: MOV to CR; MOV from CR; MOV to DR; MOV from DR: INVLPG; LMSW; SMSW; RDMSR; WRMSR; RDPMC; RSM; RVPM; CPUID; RDTSC; PAUSE; HLT; IN; INS; OUT; and OUTS;
a hardware exception or a software interrupt results in a VMM exception if, in regard to an exception bitmap where each bit corresponds to an IDT entry, when the bit in the bitmap is set to a first value (e.g. 1); and
when an IF is set through the use of an IRET, STI, POPF, POPFD or a task switch, an exception is generated if a virtual interrupt is pending;
where a VMM exception causes the processor state to be stored in at least one model-specific register (MSR).
42. A method for improved processor virtualization, said method comprising means for simulating virtual exceptions and interrupts via the use of a model-specific register (MSR).
43. A method for improved processor virtualization, said method comprising means for virtualizing a real mode by redirecting at least one GP or SS exception to a virtual machine monitor exception handler.
This application claims benefit of U.S. Provisional Application No. 60/508,747, entitled "SYSTEMS AND METHODS FOR IMPROVING THE X86 ARCHITECTURE FOR PROCESSOR VIRTUALIZATION, AND SOFTWARE SYSTEMS AND METHODS FOR UTILIZING THE IMPROVEMENTS", filed Oct. 3, 2003 (Atty. Docket No. MSFT-2841), the entire contents of which are hereby incorporated herein by reference.
The present invention relates to the field of processor virtualization and corresponding hardware and software. More specifically, the present relates to improvements to the x86 architecture to correct shortcomings in said architecture regarding processor virtualization, and even more specifically to software that utilizes these improvements to the x86 architecture.
Many technologies originally developed for mainframe systems have recently been resurrected for use in personal computers. Examples include multi-processor implementations, vector (SIMD) instruction sets, internal error checking and reporting, error correction and redundancy, and hot-swappable hardware components. Another mainframe-derived technology that is becoming more important in the PC world is the concept of a virtual machine (or VM for short).
VMs are resurfacing in the PC world for several reasons. First, modern PCs and PC-based servers are highly capable machines that are often underutilized. Second, as PC users adopt next-generation operating systems, they are looking for backward-compatibility solutions that preserve their prior investments in software and computing infrastructure. Third, in an environment where all PCs are connected to the Internet, security threats become an increasing concern, so users are looking for ways to isolate potentially dangerous software. And fourth, software developers are realizing that their capacity to deliver increasingly complex systems is bottlenecked by testing resources and capabilities. VMs can be used to streamline testing processes and increase capacity for automated test execution.
Gerald Popek, an early pioneer in VM research, defined a virtual machine as "an efficient, isolated duplicate of a real machine." The latter requirement of isolation dictates that each virtual machine possess its own set of hardware (including I/O channels, peripheral devices, hard drives, etc.). This can be accomplished by dedicating specific hardware components (buses, memory, drives, etc.) to each VM. Alternatively, virtual hardware devices can be written in software and implemented using shared resources on the host machine. In contrast, however, the VM requirement for efficiency requires good processor virtualization which, in the x86 (IA32) architecture, is largely absent. Therefore, what is needed are techniques and improvements for good processor virtualization in the x86 architecture, and the invention herein discloses such techniques and improvements for efficient processor virtualization and better accommodating efficient virtualization in the x86 architecture.
The present invention is directed to improvements to the processor architectures, and more specifically the x86 architecture, to correct shortcomings in processor virtualization. Several embodiment of the present invention are directed to the utilization of at least one virtualization control bit to determine whether the execution of a specific instructions cause a privilege-level exception (e.g., GP0) when executed outside of a privilege ring (e.g., outside of ring-0). Several additional embodiments are directed to the utilization of a virtual assist register to implement at least one virtual assist feature. And several additional embodiments are also directed to utilization of a bit for enabling a virtual protected mode that, when a processor in running in a protected mode, causes said processor, which is otherwise executing as if it is running in protected mode, to execute normally with exceptions to handle special virtualization challenges.
The foregoing summary, as well as the following detailed description of preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings exemplary constructions of the invention; however, the invention is not limited to the specific methods and instrumentalities disclosed.
The inventive subject matter is described with specificity to meet statutory requirements. However, the description itself is not intended to limit the scope of this patent. Rather, the inventor(s) have contemplated that the claimed subject matter might also be embodied in other ways, to include different steps or combinations of steps similar to the ones described in this document, in conjunction with other present or future technologies. Moreover, although the term "step" may be used herein to connote different elements of methods employed, the term should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.
Computer Environment
Numerous embodiments of the present invention may execute on a computer.
As shown in
A number of program modules may be stored on the hard disk, magnetic disk 29, optical disk 31, ROM 24 or RAM 25, including an operating system 35, one or more application programs 36, other program modules 37 and program data 38. A user may enter commands and information into the personal computer 20 through input devices such as a keyboard 40 and pointing device 42. Other input devices (not shown) may include a microphone, joystick, game pad, satellite disk, scanner or the like. These and other input devices are often connected to the processing unit 21 through a serial port interface 46 that is coupled to the system bus, but may be connected by other interfaces, such as a parallel port, game port or universal serial bus (USB). A monitor 47 or other type of display device is also connected to the system bus 23 via an interface, such as a video adapter 48. In addition to the monitor 47, personal computers typically include other peripheral output devices (not shown), such as speakers and printers. The exemplary system of
The personal computer 20 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 49. The remote computer 49 may be another personal computer, a server, a router, a network PC, a peer device or other common network node, and typically includes many or all of the elements described above relative to the personal computer 20, although only a memory storage device 50 has been illustrated in
When used in a LAN networking environment, the personal computer 20 is connected to the LAN 51 through a network interface or adapter 53. When used in a WAN networking environment, the personal computer 20 typically includes a modern 54 or other means for establishing communications over the wide area network 52, such as the Internet. The modem 54, which may be internal or external, is connected to the system bus 23 via the serial port interface 46. In a networked environment, program modules depicted relative to the personal computer 20, or portions thereof, may be stored in the remote memory storage device. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers may be used.
While it is envisioned that numerous embodiments of the present invention are particularly well-suited for computerized systems, nothing in this document is intended to limit the invention to such embodiments. On the contrary, as used herein the term "computer system" is intended to encompass any and all devices comprising press buttons, or capable of determining button presses, or the equivalents of button presses, regardless of whether such devices are electronic, mechanical, logical, or virtual in nature.
Brief Overview of Registers
In general, registers are small data holding places that are a typical part of a computer processor. A register may hold a computer instruction, a storage address, or any kind of data (such as a bit sequence or individual characters), and some instructions specify registers as part of the instruction. For example, an instruction may specify that the contents of two defined registers be added together and then placed in a specified register (overwriting whatever contents were previously stored in this destination register). In most cases, a register must be large enough to hold an instruction—for example, in a 32-bit instruction computer, a register must be at least thirty-two (32) bits in length. In some computer designs, there are smaller registers—for example, half-registers and even quarter-registers—for shorter instructions or other purposes. Depending on the processor design and language rules, registers may be numbered or have arbitrary names.
The x86 (IA32) architecture has a specific set of registers comprising the general registers, the segment registers, the EFLAG register, the control registers, and a variety of others registers.
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The system registers (not shown) comprises a plurality of control registers that are discussed later herein.
Virtual Machine Architecture
Overview of Processor Virtualization
There are two primary methods for processor virtualization: emulation and direct execution. A hybrid of these two approaches is also possible. Emulation involves the use of an interpreter or binary translation mechanism and is the only feasible choice when implementing a
VM on a system where the guest and host processors differ significantly. For example, the Connectix product Virtual PC for Mac implements an x86-based VM on a PowerPC-based Macintosh system. Emulation is also needed in some situations where the guest and host processors are the same but the processor provides inadequate virtualization support. Certain operating modes of the x86 architecture fall into this category.
While emulation is the most flexible and compatible virtualization mechanism, it is usually not the fastest. Both interpretation and binary translation impose a runtime overhead. In the case of interpretation, the overhead is often on the order of 90-95% (i.e. the resulting performance will only be 5-10% of the "native" performance). A binary translation mechanism is more complex than an interpreter, but it can mitigate some of the performance loss. A good binary translator imposes an overhead of 25-80% (i.e. the resulting performance is 20-75% of the "native" performance).
Direct execution is generally faster than emulation. A good direct-execution implementation comes within a few percentage points of native performance. Direct execution typically relies on processor protection facilities to prevent the virtualized code from "taking over" the system. In this regard, direct execution relies on the fact that most modern processors differentiate between user level and privileged level software. Software running in privileged mode is able to access all processor resources including registers, modes, settings, in-memory data structures, etc. User level mode, in contrast, is intended for untrusted software that performs the majority of the computational work in a modern system. To this end, most processors make a strict distinction between user-level state and privileged-level state, where access to privileged-level state is typically not allowed when the processor is operating at user level, which in turn allows trusted software (typically the operating system) to protect key resources and prevent a buggy or malicious piece of user-level software from crashing the entire system.
Direct execution of user-level code in a virtual machine is typically straight-forward and requires no special tricks because, when running virtualized user-level code, any privilege violations that occur on the hardware are simply passed along to the virtual machine, simulating the behavior of a non-virtualized processor running at user level. However, direct execution of privileged-level code is trickier because, for the virtual machine, this typically involves running privileged-level code in the VM at user level on the physical hardware. This can be problematic because privileged-level code is written with the assumption that it will have carte blanche access to all privileged state of the processor (afforded by the privilege-level mode) using a subset of instructions that directly or indirectly access privileged state (referred to generally as "sensitive instructions").
When a sensitive instruction is executed by the processor running at user level, the processor typically generates a privilege violation trap because code executing at the user-level is not permitted to execute sensitive instructions. This violation trap, in turn, invokes an underlying trap handler resident in the virtual machine monitor (or VMM) which, in effect, forms the virtual hardware aspect of the virtual machine. The VMM's trap handler (for handling violation traps from the physical hardware) is responsible for intercepting the violation trap and, in regard to the VM, for emulating the expected effects or results of the privileged instruction, and then for returning control back to the subsequent instruction to be executed in the VM.
Emulation of a privileged instruction in this way often involves the use of shadow state that is private to a particular VM instance. For example, if a processor architecture includes a "privileged mode register" (PMR), any attempt to read from or write to the PMR from user level code causes a trap. In this event, the VMM's trap handler would determine the cause of the trap and refer to a PMR shadow value that is private to the instance of the associated VM. Interestingly enough, this PMR value may be different from the value currently held in the host processor's PMR (that is, the PMR for the physical hardware). For continued operations, the VM would continue to access the shadow PMR while the host operating system would continue to access the real PMR.
However, depending on the frequency of trapping instructions and the cost of handling a trap, this technique may impose a significant performance penalty. Early VMMs developed by IBM and Amdahl reached a limit of 80-95% of native performance. The 10-15% performance loss was primarily due to this trapping overhead. Later implementations have overcome this limitation by effectively "inlining" the trap handling within microcode, which eliminated the need for trapping for all but the most complex privileged instructions.
Strict Virtualization
An idealized processor intended for virtualization is said to be strictly virtualizable. Several modern processors (including PowerPC and DEC Alpha) meet these requirements. Unfortunately, IA32 and IA64 do not. Simply put, a strictly virtualizable processor allows for the implementation of a direct execution virtualization mechanism that meets the following requirements:
Goldberg, who did significant early research in the field of virtual machines, formally defined several requirements for a processor to support virtualization. In less formal (and more modern) terms, a strictly virtualizable processor must exhibit the following properties.
1. Incorporates an MMU (or similar address translation mechanism).
2. Provides two or more privilege levels.
3. Divides all processor state into either privileged state or user state; privileged state should include any control or status fields that indicates the current privilege level.
4. Causes a trap when any access to privileged state (whether read or write) is attempted at user level.
5. Optionally causes a trap when user-level code attempts to access non-privileged state that should be virtualized (e.g. timer values, performance counters, processor feature registers).
6. All in-memory processor structures are either stored outside of the current address space or are protectable from errant or malicious memory accesses within the VM.
7. Any processor state at the time of an interrupt or trap can be restored to its pre-trap state after the interrupt or trap is handled.
In addition, a strictly virtualizable processor also supports the curious ability to virtualize recursively—i.e. running a virtual machine within a virtual machine.
Of course, while these required properties are necessary for correct processor virtualization, they do not guarantee efficient virtualization. Efficiency often requires additional processor facilities known collectively as "virtualization assists," and there are several historical examples of virtualization assist mechanisms.
IA32: Virtual-8086 Mode and VME
Modern x86 processors contain a mode called virtual-8086 (or v86 for short). This mode allows well-behaved 8086 real-mode code to run within a protected-mode virtual machine. A set of virtualization assists were added starting with the 486 to reduce the virtualization overhead of code running within v86 mode. These virtual-8086 mode extensions (or VME for short) provide three specific virtualization assists:
Virtual-8086 mode and VME are useful for running legacy application-level software within a protected-mode operating system environment. However, v86 mode is not flexible enough to run all real-mode code.
At the same time VME was incorporated into the IA32 architecture, a companion facility was introduced for use with protected-mode code. This facility is referred to as protected-mode virtual interrupts (or PVI for short). PVI allows a VMM to implement a shadow IF (interrupt enable flag) but, unfortunately, this shadow IF (referred to as the VIF—or virtual interrupt flag) can be read by the code that is being virtualized. Furthermore, while the processor correctly handles certain instructions that modify the IF, it does not handle others. For these reasons, PVI has proven to be an ill-conceived and poorly architected virtualization assist which, in practice, is essentially useless.
IBM 390: VM Assist in Microcode
Some implementations of the IBM 390 contained hardware support for virtualization assists. The bulk of these assists were implemented using the downloadable microcode facility of these processors, and they generally provided modified semantics for frequently-executed privileged instructions executed within a virtual machine environment. In addition, for infrequent, complex instructions, a fast trapping mechanism was provided so the underlying VMM could quickly emulate the trapping instruction.
PowerPC: MMU "keys"
Most processors (including the x86) provide multiple privilege levels within the address translation unit. This allows an operating system to mark specific pages as "privileged" and any attempt by user-level software to access a privileged page results in a page fault. However, while tying the processor privilege level to the MMU privilege level is logical, it nevertheless presents a problem for virtual machine implementations because all code within a VM runs at user level.
The PowerPC architecture solves this problem by supporting the notion of MMU "keys". A key is simply a single bit that controls whether the MMU should allow privileged memory accesses. Because a PowerPC supports two processor privilege levels, there are two independent keys. Typically, the privilege mode key is programmed in such a way that the MMU allows privileged memory accesses and the user mode key is programmed to prevent privileged memory accesses. By making the MMU setting independent of the processor mode, the VMM is able to run all of the VM code at user level but still request the appropriate MMU privilege semantics. When a mode transition occurs within the VM, the VMM simply reprograms the user-mode key.
The IA32 architecture, however, avoids the need for keys by supporting more than two privilege levels-rings 0, 1, 2, and 3 where ring 0 is a privileged-level mode and rings 1, 2, and 3 are variations of a user-level mode—where privileged-level MMU semantics are honored for privileged level ring 0 as well as user-level rings 1 and 2, but not for user-level ring 3. This allows a VMM to execute code at either ring 3 (user-level with no privileged page access) or rings 1 or 2 (user-level with privileged page access) depending on which MMU semantics are required.
PowerPC: Virtual Space IDs (VSIDs)
The MMU of the PowerPC also includes a segment translation mechanism whereby the top four bits of a logical address are used to index that address into an array of 16 segment registers. Each segment register contains a 24-bit VSID (virtual space ID) that defines the base address of a 256 MB address range within an overall 52-bit virtual address space. While PowerPC-based kernels swap out some or all of the segment registers when performing a process context switch, and because VSIDs are unique, no translation look-aside buffer (TLB) flushing is necessary because the processor's TLB is able to hold concurrent mappings from multiple 32-bit address spaces. As a result, this mechanism greatly reduces the need for TLB flushes, which not only speeds up a real PowerPC processor, but it also greatly improves performance in a virtual machine environment because TLB emulation is greatly simplified. An x86 processor, by contrast, requires that all non-global address translations be flushed from the TLB on every process context switch, and the expense of repopulating the TLB after a flush is especially high within a virtual machine because each virtual TLB miss requires a page fault at the cost several thousand cycles, thus negatively impacting performance.
PowerPC: Alignment Faults
It should be noted that the PowerPC processor does not automatically handle arbitrarily-aligned data accesses for all data types. For example, an eight-byte floating point load that is not at least four-byte aligned causes an alignment fault and the underlying operating system kernel would handle the misaligned load in software. The PowerPC helps to speed up alignment fault handling in two ways:
2. Instruction decode assistance: The PowerPC partially decodes the instruction that causes the fault, and the decode information is placed in a special-purpose register and made available to the trap handler to more quickly determine the cause of the trap and respond accordingly.
Although this software-implemented alignment fault mechanism is not in fact a virtualization assist, it does exhibit many of the characteristics of an efficient trapping mechanism used by several embodiments of the present invention to assist with virtualization.
Shortcomings of the X86 Architecture
The x86 architecture contains many virtualization "holes" and presents a number of major challenges for a VMM implementer, several of which have been analyzed and published in the art. Some of the specific shortcomings of the x86 architecture are as follows:
Separation of Privileged and User State
The x86 architecture violates the requirement of user/privileged state separation in several places. The biggest problem involves the EFLAGS register which contains both user and privileged state. The following EFLAGS fields should be considered privileged: VIP, VIF, VM, IOPL, and IF. All other fields represent user state. In operation, instructions that read and write the privileged fields of the EFLAGS register (including PUSHF/PUSHFD, POPF/POPFD and IRET) should trap when executed from user mode, but they do not. (See
More specifically, the biggest challenge for x86 virtualization is related to the PUSHF and POPF instructions which are often used within kernel (ring 0) code to save and restore the state of the IF (interrupt enable flag). Within a virtual machine, this kernel code is executed at a higher ring level (e.g. at ring 1) and the IOPL is set such that IN/OUT instructions trap. Because the OS running within the VM should not be allowed to disable interrupts on the host processor, the actual IF value is set to 1 while the virtual machine code is running —regardless of the state of the virtual IF. This means the PUSHF instruction always pushes an EFLAGS value with IF=1. Furthermore, the POPF instruction always ignores the IF field in the popped EFLAGS value.
The other area where privileged and user state are mixed is in the CS and SS registers. The bottom two bits of these registers contain the CPL (current privilege level) which is privileged state. The upper 14 bits of these registers contain the segment index and descriptor table selector. Instructions that explicitly or implicitly access the CS/SS selector (including CALLF, MOV from SS and PUSH SS) do not trap when executed from user mode though they should. In contrast, other instructions that cause CS or SS to be pushed onto the stack (e.g. INT, INTO, JMPF through call gate, CALLF through call gate) can be trapped, thereby allowing the VMM to "fix up" the pushed value.
Access to Privileged State from User Mode
There are a number of "holes" in the x86 protection model that allow user-level code to directly access privileged processor state. These include the following instructions: SGDT, SIDT, SLDT, SMSW, and STR.
For a variety of reasons understood and appreciated by those of skill in the art, shadowing of the GDT, LDT, IDT and TR are necessary for correct virtualization. That means the TR, GDTR and IDTR will point to the VMM's shadow tables, not the table specified by the guest operating system upon which the virtual machine and its guest operating system are executing. Because non-privileged code can read from these registers, there's no way to correctly virtualize their contents.
In addition, several instructions that access the descriptors within the GDT and LDT do not trap when executed from non-privileged state. These include LAR, LSL, VERR, and VERW. Because GDT/LDT shadowing is necessary, these four instructions may execute incorrectly within a VM. If they could be made to cause a trap, the VMM could correctly emulate these instructions.
CPUID Virtualization
The CPUID instruction does not trap; however, as known and appreciated by those of skill in the art, it is important to trap on the CPUID when executed from a non-privileged mode in order to simulate new processor features or disable processor features within the virtual machine.
Non-restorable State
Context switching relies on the ability to save and restore the entire state of the processor; however, the x86 architecture does not allow this. In particular, the cached segment descriptor state for each of the six segments (DS, ES, CS, SS, FS, and GS) is stored internal to the processor at the time of a segment reload. This information cannot be accessed (except through the use of an SMI or other undocumented, back-door techniques), which in turn presents a barrier to correct virtualization. For example, if a piece of code loads a segment and then modifies the in-memory descriptor corresponding to that segment, a subsequent context switch will not be able to correctly restore the original segment descriptor information. Likewise, if the processor is in real mode and then switches to protected mode, the segments contain selectors that do not correspond to descriptors within the protected mode GDT/LDT. A context switch at this point would not be able to correctly restore the cached descriptors that were originally loaded within real mode.
Another example of non-restorable state is the unfortunate behavior of the IRETD instruction when used to return control to a less-privileged ring that uses a 16-bit stack. In this case, the upper half of the 32-bit ESP register is not correctly restored by the IRETD instruction. This appears to have been an oversight or bug in the original 32-bit x86 implementation because the INT instruction correctly pushes the full 32-bit ESP value onto the stack when transitioning through a 32-bit interrupt/trap gate.
PAUSE Instruction
As known and appreciated by those of skill in the art, the PAUSE instruction (a prefixed form of NOP) was recently added to provide hyperthreaded processors hints about spin lock execution. However, within a multi-processor (MP) virtual machine, spin locks pose a performance problem. For example, one virtual processor may spin on a lock that is held by a second virtual processor. If the second virtual processor is running on a thread that is not currently executing, the first virtual processor may spin for a long time, wasting processor cycles in the process. Therefore, it would be useful if the virtual machine monitor could be notified if a VM is spinning, which would allow the VMM to schedule another VM to run or to signal a second virtual processor thread to be scheduled.
Trap & Ring Transition Overhead
Virtualization relies heavily on the use of traps. Unfortunately, the overhead for trapping on a modern x86 processor is very high. The overhead for a round trip from ring 3 to ring 0 and back (i.e. an INT instruction and an IRET instruction) is very great, with cycle counts (as measured via the TSC) as high as 1250 a Pentium 4 processor and 500 on a Pentium 3 processor. While software-initiated ring transitions can make use of the optimized SYSENTER/SYSEXIT instructions, even these paths still impose a very high overhead of several hundred cycles.
In this regard, there are two high-frequency causes for traps within a typical guest OS: interrupt flag manipulation and I/O instructions. For example, kernel-level code frequently executes CLI/STI instructions that must be trapped to correctly virtualize the IF and, for a heavy I/O load on a 1 GHz processor, Microsoft Windows 2000 may execute over 100,000 CLI or STI instructions per second which, on a 1.2 GHz Pentium 3 processor, represents a 4.2% overhead and, on a 2 GHz Pentium 4, represents a 6.0% overhead.
In addition, within a virtual machine almost every IN or OUT instruction must be trapped to correctly virtualize the associated I/O device, once again the trapping overhead limits the overall performance of the virtual machine.
VMM Protection
Because the x86 makes use of in-memory data structures that are referenced logically rather than physically, the VMM code and data need to live within the VM's logical address space even though this makes the VMM code vulnerable to memory accesses performed within the VM. Of course, with ring-3 code the VMM's pages can be protected through the use of the user/privileged bit in the corresponding PTEs; however, there is no efficient way to protect the VMM's pages when running guest ring-0 code.
Incremental Improvements to the X86 Architecture
The following sections described various embodiments of the present invention for enhancing the compatibility and performance of virtual machines, and particular those virtual machines executing on the x86 processor architecture.
Virtualization Control Bit(s)
Several embodiments of the present invention are directed to a processor that utilizes of one or more bits in a predetermined register to control whether the execution of certain specific instructions causes a privilege-level exception (GP0) when executed in a ring level greater than zero. For certain embodiments, one or more bits in CR4 (the fourth control register) of the x86 architecture are used to control whether the execution of certain instructions cause a privilege-level exception (GP0) exception when executed in a ring level greater than zero. This control could be provided by a single control bit or, in alternative embodiments, could be handled by several separate bits. For one such embodiments, the following CR4 bits (each a "virtualization control bit") are identified and utilized as indicated:
In an alternative embodiment, a separate bit (CR4_IRET16) could control the behavior of the IRETD instruction—that is, whether this instruction returns with the normal 16-bit stack segment or the entire 32-bits of the ESP register.
In another alternative embodiment, one or more of the aforementioned control bits is located in a "Virtualization Control" model-specific register (MSR).
Virtual Assist Mechanism
The EFLAGS register presents a difficult problem because it contains a mixture of privileged and user state. The most problematic field is the IF (interrupt enable flag), but other fields like the IOPL are also an issue. With this in mind, various embodiments of the present invention are directed to a "virtual assist," that is, to enabling virtualization of the IF and IOPL fields of the EFLAGS register and the CPL fields of the CS and SS registers, where the utilization of these virtual fields would be controlled through the use of a new MSR (VA_CNTRL) with fields corresponding to specific processor functionality—that is, the "virtual assist components" for "certain virtual assist features"—as illustrated in
In addition to enabling the CPL, IOPL and IF to be virtualized, this virtual assist prevents many of the traps traditionally required to virtualize the IF. Moreover, the TRP_SIFST bit is similar to the VIP bit used with VME/PVI such that, when set, TRP_SIFST causes the processor to generate a GP0 exception after the SIF transitions from 0 to 1 which allows the VMM to deliver any pending virtual interrupts.
For various embodiments, the SIF is only modified in situations where the IF would normally be modified if VA_ENBL were disabled. Normally, this test involves the CPL and IOPL value—for example, if CPL>IOPL, then IF modifications would either cause an exception or would be ignored. However, when VA_ENBL is set and CPL>0, this test is performed using the shadow versions of CPL and IOPL (i.e. SCPL and SIOPL), although for all other internal processor privilege checks, the real CPL and IOPL continue to be used.
Note that this has implications for VME/PVI. When VME/PVI is enabled along with VA_ENBL, the normal VME/PVI algorithm is used except that SCPL and SIOPL are used instead of CPL and IOPL. Thus, for several such embodiments, the SIF is modified only in cases where the real IF would otherwise be modified—in other words, if the VME/PVI algorithm dictates that an instruction should cause an exception or modify the VIF, the SIF is not affected.
For certain embodiments, any exception or interrupt (including those generated by the INT 3, INT, INTO and ICEBPT instructions) will use the real value of IF, IOPL and CPL when pushing the EFLAGS, CS and (optionally) SS onto the stack. Likewise, any IRET executed from ring 0 will restore the real IF and IOPL from the EFLAGS popped from the stack.
For various embodiments of the present invention, this virtualization assist mechanism is specifically designed with recursive virtualization in mind such that the VA_CNTRL is itself virtualizable.
Saving and Restoring State
It is important for a VMM to be able to save and restore the segment register state including the internally cached descriptor. Despite this importance, there is no solution in the art to modify the x86 architecture in a simple way to accommodate this requirement. Various embodiments of the present invention are directed to a series of registers that are used to accessed the cached descriptors. For certain embodiments, a series of MSRs are used to access the cached descriptors, where four MSRs are used for each of the six segment registers: one for the selector, one for the base, one for the limit, and one for the flags.
This solution, however, is inadequate. The CS and SS segments are implicitly loaded during a ring transition, so by the time an exception handler is invoked, the previously cached value of CS and SS have been overwritten. For this reason, it may be necessary to introduce a "previous CS" and "previous SS" MSR.
This still doesn't solve the problem of restoring the state of the CS and SS descriptors when returning from an exception.
The proposed use of MSRs introduces a host of problems involving validation of segment flags. For example, loading a segment within protected mode requires the validation of protection flags. This MSR mechanism would need to duplicate this validation process or risk a situation whereby the descriptor flags represent an illegal descriptor (e.g. a CS segment that's not marked as a "code" segment).
Trap Overhead & Exception Cause Reporting
VMMs make extensive use of traps (e.g. to virtualize IN/OUT instructions). The overhead involved in cross-ring transitions continues to rise with each new processor family. Due to the complexity of a cross-ring transition on the x86, it's understandable that trapping will be expensive. However, a thousand cycles seems exorbitant. Any effort to minimize this overhead would improve virtualization performance. It would also improve performance of kernel calls and exception processing in non-VM applications.
For extremely efficient x86 virtualization, a specialized fast-path exception vector may be required. In addition, it would be helpful if the processor were able to indicate the cause of the exception—perhaps in an "exception cause" register. Because most x86 exceptions today are all reported as GP (general protection) exceptions, the GP exception handler within a VMM is extremely complex and inefficient. In many cases, determining the cause of the exception requires hundreds of cycles.
Holistic Improvements to the X86 Architecture
Several embodiments of the present invention are directed to (a) eliminating the need to perform "ring compression" (i.e. running virtualized ring-0 code at a higher ring level), (b) eliminating the need to shadow the GDT, LDT, IDT and TSS and avoids most of the high-frequency trap sources, and (c) allowing for highly efficient recursive virtualization.
Virtual Protected Mode (VPM)
Various embodiments of the present invention are directed to the introduction of a new processor mode bit to CR0 called VPME (virtual protected mode enable). This bit, like the paging enable bit, is only valid when running in protected mode. When VPM is enabled, the processor acts as if it was running in "normal" protected mode with the following changes:
VMM Exceptions
A VMM exception is generated in response to several conditions (defined above). A VMM exception exits VPM and transfers control to the VMM's exception handler. When a VMM exception is generated, the processor does the following:
To summarize, the following new MSRs would be required:
VMM exception codes would use the following encodings:
RVPM Instruction
There are only two ways to enter VPM:
Note that it's impossible to set the value of the VMPE bit in CR0 directly. Any attempt to do so using the MOV to CR0 instruction will cause a GP0 fault.
When an RVPM instruction is executed, the processor performs the following actions:
Virtual Interrupt Delivery
If the VMM wishes to deliver a virtual interrupt to the guest environment but interrupts are currently masked, the VMM needs a mechanism by which it can be notified when the IF is next set. This is done through the use of the VMP_INT_PND bit of the VMM_CTRL MSR. When this bit is set, the processor will generate a VMM exception when the IF is set while running in VPM mode.
Because of the defined behavior of STI, the VMM exception that indicates a pending virtual interrupt should not be generated until after the subsequent instruction (i.e. the instruction following the STI) has been executed. In other words, the VMM exception should be delivered in lieu of a hardware interrupt at the same place where the hardware interrupt would have occurred.
VM Debugging
Debugging code within the guest environment requires a single-step trace mechanism that is transparent to the guest code. One way to accomplish this is through the use of another bit in the VMM_CTRL register—the VMM_TF bit. When this bit is set, the processor generates a VMM trace exception after executing one instruction in VPM.
Protecting the VMM's Data & Code
As mentioned above, the VMM's data and code is vulnerable because it must be located within the guest's address space. We propose three ways the VMM could be protected:
While the third choice is the safest option, it may be too expensive. Because VMM exceptions are high-frequency events, they need to be extremely efficient. If disabling address translation requires a flush of the processor's TLB, the overhead will be too great. In this case, the first or second choice would be preferred.
Accelerating Virtual Exceptions and Interrupts
The VPM can optionally incorporate a mechanism for efficiently simulating virtual exceptions and interrupts. There are two situations where the VMM may need to simulate interrupt/exception processing within the guest environment:
In these two cases, it would be useful if the RVPM instruction was able to simulate an exception or interrupt rather than returning directly to the specified VPM_EIP. This mechanism would involve the addition of another MSR: the VMM_EXC_ASSIST register. This register would contain the following fields:
VMM_EXC_ENBL (1 bit): If set, the RVPM instruction generates a simulated exception or interrupt. This bit is cleared after the exception is simulated to prevent additional processing.
VMM_EXC_DPL (1 bit): If set, the DPL of the IDT vector must be checked. (This bit should be cleared for external interrupt simulation.)
VMM_EXC_CODE (1 bit): If set, the exception code specified in the top half of VMM_CODE is pushed onto the stack during exception processing.
VMM_EXC_EIP_ADJ (3 bits): This field contains the value to be added to the VPM_EIP before pushing it onto the exception stack. (This value is needed for INT simulation.)
VMM_EXC_VECTOR (8 bits): This field contains the IDT vector to use when simulating the exception or interrupt.
Real mode support
Real mode can be virtualized using the VPM mechanism as long as the segment reload facility of the RVPM instruction allows v86 segments contain limits other than 0xFFFF. By indicating (through the use of the VMM exception bitmap) that all GP and SS exceptions should be redirected to the VMM's exception handler, the VMM should be able to virtualize all real-mode code using v86.
One potential modification that would speed up real-mode virtualization is the introduction of a separate VMM_CTRL bit that indicates when real-mode code is running (versus v86 code). When this bit (VMM_REAL) is set, any v86 segment reload should refrain from reloading the segment limit or flags, providing a behavior that is consistent with real mode.
Software for Utilizing Improvements to the X86 Architecture
Alternative embodiments of the present invention include software of any kind that utilizes, accesses, calls, or otherwise interacts with any implementation of the improvements characterized herein, and each specific X86 hardware improvement as disclosed herein further comprises software for utilizing said improvements.
The various system, methods, and techniques described herein may be implemented with hardware or software or, where appropriate, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. In the case of program code execution on programmable computers, the computer will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. One or more programs are preferably implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.
The methods and apparatus of the present invention may also be embodied in the form of program code that is transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as an EPROM, a gate array, a programmable logic device (PLD), a client computer, a video recorder or the like, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates to perform the indexing functionality of the present invention.
While the present invention has been described in connection with the preferred embodiments of the various figures, it is to be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiment for performing the same function of the present invention without deviating there from. For example, while exemplary embodiments of the invention are described in the context of digital devices emulating the functionality of personal computers, one skilled in the art will recognize that the present invention is not limited to such digital devices, as described in the present application may apply to any number of existing or emerging computing devices or environments, such as a gaming console, handheld computer, portable computer, etc. whether wired or wireless, and may be applied to any number of such computing devices connected via a communications network, and interacting across the network. Furthermore, it should be emphasized that a variety of computer platforms, including handheld device operating systems and other application specific hardware/software interface systems, are herein contemplated, especially as the number of wireless networked devices continues to proliferate. Therefore, the present invention should not be limited to any single embodiment, but rather construed in breadth and scope in accordance with the appended claims.
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Cops Investivating Lohan's Accident Claims
The Santa Monica Police Department is looking into whether or not Lindsay Lohan lied to police officers while being questioned about her involvement in a car accident Friday.
The Santa Monica Police Department is looking into whether or not Lindsay Lohan lied to police officers while being questioned about her involvement in a car accident Friday.
Lindsay Lohan was hospitalized Friday morning after she was in a serious car accident. She was on her way to the set of the Elizabeth Taylor movie when she rear-ended a dump truck. She totaled the rental Porsche that she was driving
Linds, have you considered hiring a driver? Just a suggestion...
Amanda Bynes has had a spate of driving-related mishaps of late, and now she's calling in the big guns to help her out: President Obama.
Lindsay Lohan's trainwreck of a mother, Dina Lohan, is finally getting her own time in the spotlight. She's doing a reality show with VH1 called 'Hollywood Exes'. She's going to be in a house with th
The cast and crew of "Glee" are apparently none too happy with Lindsay Lohan's latest shenanigans on the set the Fox series, according to sources at Us Weekly and E! Online.
File this one under "not quite." Rosie O'Donnell took to the air waves to compare trouble movie starlet Lindsay Lohan to fallen music legend Whitney Houston.
Lindsay Lohan finally signed on to play Elizabeth Taylor in her upcoming Lifetime biopic. Her names been thrown around for awhile because she was really pushing for the part, but apparently the movie producers wanted her all along
The women who populate this list aren't just your average ladies with a little ink. These women are hot, hardcore and not afraid of the stigma that comes with etching permanent markings on their bodies. W
Amanda Bynes' dad is taking up for her. He insists that she was not drunk Friday morning when she got arrested for a DUI after clipping a cop's car. Rick Bynes said, "She was not drunk. I was told that she blew a zero on theBreathalyzer. She
It has been less than two weeks since Lindsay Lohan was finally released from her probation and out of court for good, but new legal troubles are haunting her again.
This time, it is accusations of battery that have LiLo defending her innocence.
Lindsay Lohan just got off probation and she's already getting in trouble. She got into some catfight in a club on Thursday night. This woman filed a police report, saying that Lindsay attacked her for talking to one of male friends

subset: commoncrawl


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Sketches for Type
2 Comments
These look really cool! They are perfect embodiments of the qualities you outline underneath each letterform. Are you going to try to combine these two styles in one or are you trying to decide between them? I think I would go for the second one, personally, because I feel this "decay" typeface goes more with the themes of the book (the deterioration of democracy, decay of freedom and morale, etc.). It would be neat to combine both letterforms into one typeface though, because they are similar enough to unite the typeface but different enough to provide interest/variety, etc.
These are really awesome Steve... I especially like the second one with the jagged edges. It seems to have a lot of emotion. I agree with Brittany that combining the two could create an interesting typeface. I have never read this book but based on what you have written about it, I think your sketches represent it well.


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Dan's Papers Nov. 7, 2009
Dan's Papers, the 51-year-old bible of the Hamptons, is owned by Manhattan Media, a multi-media publishing company based in New York City, the Hamptons and Miami. Dan's Papers, the first resort newspaper in America, was founded in 1960 by Dan Rattiner, who is the founder and current editor-in-chief. Known for its insider and irreverent style, Dan's Papers has become the universal must-read in the Hamptons. In addition to the weekly paper, loyal Dan's readers can keep up with the Hamptons scene all-year-round at DansHamptons.com.
DAN'S PAPERS, November 7, 2008 Page 4 www.danshamptons.com 631-324-8299 1-800-646-4755 Specializing in ALLWindow Fashions I NTERIOR W INDOW T REATMENTS WE WILL BEAT ALL WRITTEN ESTIMATES! We bring the showrrom to you for accuate color coordinating and measurements 1194514 We Do It All! FROM MANHATTAN TO MONTAUK • VERTICALS • DRAPERIES • SHADES • WOOD BLINDS • WOOD SHADES • SKYLIGHTS • LUMINETTES • SILHOUETTES • THE ULTIMATE WINDOW TREATMENTS FROM 2" TO 4" LOUVERS • EXPERT INSTALLATION UPTO 60% OFF CALL US NOW! MFGSUGGESTEDRETAILPRICES! LESSTHANANYBODY! Lowest Price Guaranteed! We Even Beat Home Depot Prices! FREE FREE FREE Estimates Installation Shop of Home Service WE SPECIALIZE INMOTORIZED WINDOW TREATMENTS ! MAIN STREET OPTICS Dr. Robert Ruggiero Exams • Contacts • Emergency Service Most Extensive Selection Including Cartier • Chrome Hearts • Open 7 Days Year Round • 1194253 82 Main St.Southampton • 631•287•7898 BESTBEST BESTBEST 20072007 OF THE 1194263 BOCCOLUPOO ARTT GALLERY ROZ iss at 5522 Westt Lakee Dr.. Montauk 1147300 9 Corks New Weapon in EH Village's Campaign Against Dogs on Beach 13 Book Tour What ILearned Reading "In the Hamptons"in the Hamptons 13 Dinner at Cittanuova on Newtown Lane 15 Excellent Examining the Latest Term Uttered by Those Serving the Well to Do 15 What's That Up on Top of the Flagpole? 17 Ice Capades Buckskill,the Once & Future Rink,Wins Long Battle 17 Estate of Mind 3rd Q.2008 Stats:Keep Praying 19 "Captain Bob"Tuma,85 21 A Hope for America,& What We Learned from Big Brother 22 Hampton Subway Newsletter 25 Streisand,Benatar,Lauper:Long Island Musicians Feted 25 Who's Here:Dan Bailey,Dr THE MOST COMPLETE COMING EVENTS GUIDE IN THE HAMPTONS This week's coming events are in the following sections: Art Events – pg.40 Day by Day – pg.54 Kids' Events – pg.37 Movies – pg.40 Contents P.O.Box 630 • (2221 Montauk Highway)• Bridgehampton,NY,11932 • 631-537-0500 • General Fax 631- 537-3330 • Display Sales Fax 631-537-6374 • Our Classified office is now at 51 Hill Street,Southampton, NY,11968 • Classified Phone 631-283-1000 • Classified Fax 631-283-2896 • www.danshamptons.com • Dan's Papers was founded in 1960 by Dan Rattiner and is the first free resort newspaper in America. This issue is dedicated to Obama. VOLUME XLVII NUMBER 33 November 7,2008 A&E Feature 38 Art Commentary 38 Classified 58 Daily Specials 43 Dan's North Fork 30 Earthly Delights 36 Err,A Parent 37 Gordin's View 29 Green Monkeys 18 Hampton Jitney 7 Honoring the Artist 12 Letters To Dan 45 Police Blotter 45 Service Directory 46 Shop Til 34 Silvia Lehrer Cooks 41 Side Dish 42 South O' The Highway 10 Twentysomething 27 33 Fashionista 35 Take a Hike 39 Review:Equus 39 Back Beat WEEKLY FEATURES COMINGUP


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Guidecraft - Manipulatives - Educational ToyProduct Id: 469461 Phone Code: 1111-936C
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Animal Train Sort and Match is the perfect way to teach color-matching, shape-matching and pattern-recognition in a fun, game-like setting. Animal Train Sort and Match includes six double-sided pattern cards, 43 animal and train pieces, and a self-propping board and stand with pegs and metal backing to help guide the magnetic pieces into place. Ages 3+.
- 8 Double-sided Pattern Cards
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- Ages 3+


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MDK 9.1 - Nvidia driver still shows "Generic" after update?
Just installed the newest drivers from Nvidia in my clean install of Mandrake 9.1. The Driver installer said it completed sucessfully and I changed that "Nv" thing to "Nvidia". At boot, I see Nvidia's splash screen, but in Mandrakes hardware list, it shows my card model number (GF4 MX 440), BUT, it said "(Generic)" after it.. The only reason I'm concerned is that it said that BEFORE I udated the driver AND, a couple of the 3D games that came with MDK 9.1 dont boot now?
The "generic" string means nothing. It's just Mandrake's internal way of classifying your card.
When you say the games "don't start", what do you mean? What happens when you run them from a terminal? Post the output here.
Have not tried terminal
Still new at this, a terminal is a 'konsole', right?.. Also, it seems MDK 9.1 comes with several kinsoles, which one is the one everyone uses?
Thank you for telling me about the 'generic' thing!
I will try to run a game in a console when I get back from my errands this morning...
What is happening now when I try to start a couple of the games is that (this is in KDE, by the way) they show as a title box in the task bar, with an hour glass, and then a few seconds later the title box goes away and nothing happens... one game I can think of the name of right now is that 'Armagetron' (tron like lite cycles)game.... before I installed the new Nvidia driver that game and one or two others would start-up, but run at about 3 fps, making it impossible to play...Now they dont work at all. I dont have any other good 3d games for linux yet to test the card out.
Well I tried to start the game from a console with no luck (I dont want to wast your time) as I am still too new to linux. However I noticed another game that does it (never starts), as well as a music (midi) appplication...so maybe something else is at work here.
Does anyone know how to truly test that the card is ok? Is there an Open Gl tester I can try...? I tried to run some Open Gl screen savers and they run horribly slow (slow fps)... I have a P4 2.53 hz w/512MB DDR 400 and the last thing I though would run slow would be the screen savers... its like I'm using my old 166Mhz !!
Once again, I believe I installed the Nvidia Drivers correctly, I just want to see it in action!
Please post the logs/info requested in http://www.nvnews.net/vbulletin/show...&threadid=9614 here.
Re: Have not tried terminal
Unable to locate!
When I was talking about wasing your time, I didn't want to bother you with simple things like...
- In windows, you can right-click a shortcut and find which directory the actual program is i, and then run the EXE.. here I dont know what directory the games are in PLUS, I dont know what the list of execuables for linux are. While I was installing the linux driver, I had to type 'sh' nvidiadriver.run <enter>... I could try the 'sh' thing, but dont want to mess something up.. here is where I figured I will get a book about linux before I waste your time in the wrong forum thread.. :-) Luckily, I was around during the 'DOS' days and arent as bad off as some people...
-Not only are two of the games that came with MDK 9.1 not starting, I also discovred a MIDI music program that does the same thing also (just starts as a button in the task bar, and then goes away and never launches).... I assumed the games to be because of incorrectly installed Nvidia driver, but this other program as well? Maybe it used Open GL as well...
Anyway, If you still want to help, give me a quick lesson on opening one of these things in a console (finding the game in its directory) and the command to run it at the prompt and I'll give it a try..
Also later today or tonight I'll post the contents of my x86x?? file (above) and hopefully my settings are off.. Thank you!
Games don't get "their own directory", most of the time. Some of them will put a game-specific subdirectory under /usr/games or /usr/local/games (or /usr/share even), but that's for game-specific data, not the binaries. The Windows practice of "a separate folder under Program Files for every package installed" isn't really applicable. The reason for that is mostly because there aren't shortcuts to everything on a lot of people's machines, so the binaries get put into /usr/bin or /usr/local/bin. Most of the time.
Anyway, what games are you trying to start? You should just be able to type the game's name into a terminal, but that does depend on the game.
TuxRacer, for example, gets started by tuxracer. I'm not sure what else you have, but if you can post it, I can take a look at installing it and finding out.
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Results for due process
Traffic Cameras, Domestic Drones, and Mandatory Sentencing
Originally Posted: 06/12/2013 - 10:20am | Type: Blog
But then, there may be another problem with increased surveillance and flooding our nation's skies with drones. Let's take traffic cameras as an example. At first I had no problem ...
Hellfire from Above
Originally Posted: 06/12/2013 - 9:49am | Type: Magazine Article
Steve Holt More than 1,000 civilians have been killed by U.S. drone strikes. Obama, technology, and the myth of redemptive violence. ...
Rand Paul, Drones, and Honor
Originally Posted: 03/08/2013 - 4:54pm | Type: Blog
While I stand with Sen. Rand Paul on the question of the use of militarized spy drones in American airspace and (potentially) on Americans, I am deeply troubled by our use of these weapons in other lands, too, ...
Voices from the Web (and World): Responses to the Troy Davis Execution
Originally Posted: 09/24/2011 - 5:14pm | Type: Blog
"Continuing a cycle of violence through state-sanctioned actions does not bring justice but only creates a culture of death and retribution. " Continuing a cycle of vi ...
Scandal, Secularism, and the Politics of the Catholic Church
Originally Posted: 07/14/2011 - 8:34am | Type: Blog
It is far too easy to blame the highly publicized priestly scandal for the alienation of Catholics in Europe or the United States. It is far too easy to blame the highly publicize ...
The Global Grassroots Struggle Against Corporate and Government Corruption
Originally Posted: 07/14/2011 - 8:19am | Type: Blog
As described in the February ...
Immigration Reform: The time has come
Originally Posted: 07/14/2011 - 8:18am | Type: Blog
The time has come for comprehensive immigration reform. After several failed attempts in past years, the president has promised it and the White House is showing a clear commitment to it. ...
Hard Facts of Immigrant Detention Centers
Originally Posted: 07/14/2011 - 8:17am | Type: Blog
The <a title="http://www.washingtonpost.com/wp-dyn/content/article/2009/03/15/AR2009031501115.html" href="http://www.washingtonpost.com/wp-dyn/content/article/2009/03/15/AR2009031501115.html& ...


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Trained Gray Kitty Puts Paws Together for a Yummy Treat
When we say here on Catster that we've found a video of a "trained cat," what we really mean is we've found a cat who's duped us into thinking we've trained the cat. What these cats have actually done is figured out the most efficient way to get their favorite treats.
"Oh, if I do this cute thing (which I was already doing -- thank you very much), then I get a yummy tuna snack? All right, human, I'll play along."
It appears that this silky gray has got us in the palm of his paw. When the human offscreen gives the word, he sits up on his hind legs and clasps his paws like a little kitty angel saying grace. But if you look more closely into those darling button eyes, you'll catch a glint of truth -- kitty has got us trained.
First it starts with treats. Kitty performs, looking almost unbearably adorable, and is rewarded with a snack. But just you wait and see: The next thing you know, kitty will have his human ordering caviar and champagne for him and all his alley cat friends.
We've seen Puss in Boots -- we know the disarming look of domination when we see it!
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Famous quotes by Sir Isaiah Berlin:Sort:PopularA - Z
|Only barbarians are not curious about where they come from, how they came to be where they are, where they appear to be going, whether they wish to go there, and if so, why, and if not, why not.
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The Lego Movie is a fun way to get into the action if you're a fan, but don't spend your money if you haven't seen the movie.
With an ever-growing selection in the App Store, it can be near impossible to cut through all the cl
The accessory company unveils a 3,840x2,160-pixel monitor for less than you'd expect to pay.
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Soon you'll don a high-tech headset as easily as you reach for your controller. Watch for blockbuster launches in the year ahead that pave the way to the brave new virtual world. Facebook and Valve lead the charge.
Watch Coldplay round up your favorite and not-so-favorite characters from HBO's "Game of Thrones" as part of NBC's Red Nose Day Live Benefit Show to combat poverty.
The SteelSeries Apex and Apex Raw keyboards are a gamer's best multitool, featuring 16.8 million possible custom color combinations, a low-profile layout, and of course, macros on macros.
After months of slumping software and less-than-stellar launches, video games for the current generation of console hardware are finding their stride.
A twice-yearly Internet traffic report provides a peek at how the season premiere of the hit fantasy series boosted viewership of HBO's online services.
From older gems like Syberia to newer titles like The Novelist, this bundle of top-rated adventures is a steal at this price.
The DGL-5500 has a lot of potential, but for now isn't worth its high price.
A roundup of our favorite CNET videos from news, reviews and more.


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Product Features
- Nordic Cable
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Keep your head warm on a cold fall or winter morning with this chic cable knit beret hat from Helen Kaminski. The Helen Kaminski Alva beret is made from 100% cashmere yarn and features a hand knit Nordic cable design with a slouchy, relaxed fit and a rib knit band around the edge. This casual beret is available in one size and is detailed with a small Helen Kaminski logo accent on the side. Available in a variety of neutral and fashion colors, this hat can be easily matched with your favorite chunky sweater, winter coat, or scarf and gloves.
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Need of Wireless Headphone
Wireless means No wires and you don't have to worry about stretching, twisting, and playing with the wires anymore. You can now walk around the room, lie down on bed, or sit back and relaxed while listening to your favourite music, Thanks to the wireless headphones.
As these wireless headphones use the supra-aural designs, you can concentrate more on the sound and engrossed yourself completely in the music. Moreover, some headphones are capable of blocking the background noise to deliver exceptional quality sound. Wireless headphones are best suited for people who love watching movies till midnight and yet do not want to disturb the other sleeping members in the family. What's more, it provides the freedom of listening to whatever music you wish to by keeping it to all by yourself.
Let us look at the top 5 wireless headphones
• Sennheiser RS 220
• Sennheiser RS 120
This wireless stereo headphone offers a comfortable fit and is ideal for long listening sessions. With exceptional sound quality and balanced sound reproduction along with strong bass performance, this headphone is suitable for movie and sports lovers as well as for all modern music and TV applications. Moreover, the easily accessible control elements let you conveniently control the function without much effort.
• Tritton Warhead 7.1
This wireless gaming headphone is specifically designed for Xbox 360 and makes the experience of playing games even more enjoyable. Thanks to the 5.8 GHz wireless signal, the headphone eliminates the need of connecting it to the gaming console and ensures that you get high quality sound at a distance of 33-feet. Powered by Dolby headphone technology, this headset lets you clearly hear every minute details of the game that gives you a top advantage of locating the hostiles even before they sense your presence.
• Harman Kardon BT
Be it listening to music, watching movies, or playing games, these wireless headphones reduces the ambient noise and allows you to immerse yourself in the sound source. Besides, these wireless headphones are designed to fit on your head with utmost comfort. All these wireless headphones save you from the hassle of wires and offer an impressive listening experience with high quality performance.
Tags: Harman Kardon BT, Sennheiser RS 120, Sennheiser RS 220, technology, Tritton Warhead 7.1, Wireless Headphone


text: Home > Medical > Meds and you Meds and you All sections in Meds and You » Antibiotics » Generics » Inside the Lab » Medication » News » Using Medicines Will over-the-counter medication really help? We like to believe that there's a pill for every pain. But many of the over-the-counter medicines we reach for to treat a cold, cough, heartburn or pain simply do not work. Patients tend to listen to female doctors more Plant-based vaccines challenge big pharma Extreme medicine: The search for new antibiotics Counterfeit medicine threatens Africa See All Meds and you News » Meds and you Overview Nonsteroidal anti-inflammatory drugs What is Meds and you? Take medicine only as directed, at the right time, and for the full length of your prescribed treatment. If you are using an over-the-counter (nonprescription) medicine, follow the directions on the label unless otherwise directed by your health care professional. If you feel that your medicine is not working for you, check with your health care professional. Unless your pharmacist has packaged different medicines together in a "bubble-pack," different medicines should never be mixed in one container. It is best to keep your medicines tightly capped in their original containers when not in use. Do not remove the label since directions for use and other important information may appear on it. Take Action Ask Addictions Expert » Test Using the wrong pills? » Quiz Addicted to pills? » Join Body Talk » Medical history Medicines that changed history advertisement Antibiotics Extreme medicine: The search for new antibiotics Common bacteria becoming resistant to antibiotics Improper use causing antibiotic resistance What is an antibiotic? See All Antibiotics » Inside the lab How your medicine is made The pharmaceutical industry at a glance Inside the lab See All Inside the lab » Using medicines The interaction of grapefruit and medication Getting rid of expired medicines Here's what your doctor's prescription means Save money on meds See All Using medicines » Generics Are generics a good option? Frequently asked questions Generics: introduction What you need to know See All Generics » Medication Darifenacin Will over-the-counter medication really help? Plant-based vaccines challenge big pharma Tretinoin See All Medication » From our sponsors Why hydration is important while exercising Taking charge of your health Man, take care of your health!


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Oster 2 Speed Gold A5 - Limited Edition - Pink
A powerful 2 speed clipper which delivers 3,200 strokes per minute. These powerful clippers are recommended for heavy duty clipping – universal motor – designed for continuous use which handles both general purpose and precision clipping on any coat type.
This pink model has a break resistant housing.
Accessories include:
Size 10 blade
Blade oil
Clipper grease
Cleaning brush
These powerful workhorse clippers have the versatility to handle all your grooming jobs! Designed for commercial use. You'll be able to tackle any coat type with these clippers – thanks to the heavy duty universal motor, capable of handling everything from general purpose grooming to precision clipping.


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For a very limited time, SpiderOak is offering unlimited cloud storage on unlimited devices for just US$125 per year — but you'll need to be quick.
The Charcoal Companion Fondue Grill Set consists of a grilling platter and fondue pot. Designed for use over an open fire, the hot platter sets onto a fitted serving base.
The man behind Apple Store's success unwraps a site for buying high-end gadgets that includes house calls. His goal: "Reinvent the way people buy and enjoy technology."
The Audiophiliac auditions the Spendor S3/5R2 speakers and Naim Uniti 2 CD player/amplifier.
Crave's Eric Mack travels to the middle of the far northern ocean to track down the lost magic arts, and discovers he never wants to wear "necropants."
Visitors to the Frank Lloyd Wright Home and Studio in this swanky Chicago suburb can take an easy walking tour of many other beautiful buildings designed by the famous architect. CNET Road Trip 2013 explores the neighborhood.
The world's largest restaurant chain is in turnaround mode. It's looking to the tech industry -- and role models like Google -- as it searches for a good jump start. First stop: South by Southwest.
At the North American International Auto Show, a 1965 Shelby Cobra 427 with a difference is on display.
Technically Incorrect: A middle school basketball game carries on with the referee signaling calls one-handed. In the other, he's making a call.
Need to expand the storage on your iOS phone or tablet? Win a SanDisk gadget that adds space while working as a convenient backup device for user-generated content.


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Hyundai i10
It's cheap and cheerful, but the Hyundai i10 is also a landmark car for Hyundai. It proves the Korean firm is capable of building a great city car, as it's practical, and offers big car comfort and high-speed stability. There are two small petrol engines on offer, which both offer low running costs. The Hyundai i10's small proportions mean that the Hyundai is at home in the city, but it can also cope with longer journeys. It's easy to drive, and the simple dash is logically laid out.
Hyundai i10 hatchback
- Very comfortable
- Spacious interior
- Fun to drive
- Interior quality poor in places
- No diesel engine available
- Lack of badge appeal
The Hyundai i10 is a sleek city car that is both economical and suprisingly practical for such a small vehicle. Even better, it's fun to drive – unlike many of its rivals – and comes with Hyundai's five-year warranty. There is a choice of two petrol engines, both of which are cheap to run and insure, and six trim levels, including the SE Blue Drive model which caters to buyers looking for a particularly economical model.


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Student Highlight
2015 Novice Speaking Competition winner, Tyler Murry, explains, "I have worked with the Speaking Center on multiple occasions and have always appreciated the insight and knowledge that has been provided on each visit…I was not only able to present a speech in my class, but I was able to gain confidence in my ability to give a speech. The Speaking Center not only allowed me to feel prepared and ready for my public speaking class but also for the Novice Speech Competition."
Speaking Center Hours
The Speaking Center will be closed until the summer semester begins. We will reopen on May 26th.
Have a good break!
Staff Highlight
Congratulations to Nicole Magee! Nicole, the Speaking Center Coordinator, graduated with her Master's in Communication Studies this semester. Thank you for all that you have done for the Speaking Center over the years!


text: Glock Plastic Sights [Archive] - Glock Talk Glock Talk > Go Ask The Expert Forums > GATE Self-Defense Forum > Glock Plastic Sights PDA View Full Version : Glock Plastic Sights beetrix03-22-2011, 17:20What is your opinion of Glock plastic factory sights? Are they as bad as every says? beetrix Mas Ayoob03-22-2011, 18:16Well, they're not really HORRIBLE, but you can do better. The ones I use regularly have aftermarket sights on them, tailored to the guns' tasks, which work better for me than the sights they came with. That's probably true for most who use Glocks seriously. best, Mas vBulletin® v3.8.7, Copyright ©2000-2015, vBulletin Solutions, Inc.


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About 150 people bought $80 tickets to the event, organised
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Fresh Bluff oysters were shucked on site at the Dunedin
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Harbour Fish has held the fundraiser once before, in 2012.
That year about $2000 was raised for the neonatal intensive
care unit at Dunedin Hospital. Organisers hoped more would be
generated by yesterday's event.
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Benedict Clarke's first film role was young Severus Snape in Deathly Hallows – Part 2. He was born in London in 1996. He usually goes by the nickname "Ben." Apart from the Harry Potter series, he has acted in several short films, including Awkward Facades and In the Wake of Sirens.
He is a big fan of the BBC series Sherlock and enjoys taking photographs.
Latest News
Latest News
- "Pride", featuring Bill Nighy, Imelda Staunton, and Jessie Cave, trailer released - Excited to see the new movie "Pride" with three HP stars? We've got the newest trailer here!
- Twitter Round Up: Charitable Acts and Hippogriff Selfies - This week on Twitter, one Potter alumnus got to enjoy a rather spectacular view Hong Kong. You be mighty fine. X pic.twitter.com/rXUwVZDkCh — Jamie Campbell Bower (@Jamiebower) August 31, 2013 whilst others took the time to enjoy more modest locations. My favourite acts at #Reading were Chase and Status, Imagine Dragons, alt-j and Kodaline. — ...
"Potter" Career
"Potter" Career
Benedict appears as young Severus Snape in Harry Potter and the Deathly Hallows – Part 2 during the scenes that correspond to the chapter "The Prince's Tale." He shot his scenes during April 2010. The cast and crew alternated between shooting on set at Leavesden Studios and on location in Hertfordshire.
Benedict was sorted into Hufflepuff on Pottermore.
He attended school with Alfie McIlwain, who played young James Potter.


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Interesting Sailboats
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Re: Interesting Sailboats
Originally Posted by
capt vimes
Bora... Always good for some stress...
My favorite tough weather sailing video, even if older...
Rough Weather Sailing - BT Global Challenge 2000 - YouTube
I've never been offshore in conditions this rough, but I have raced in conditions with winds > 40 knots and big waves at night. We had the on-watch crew on the rail of a J/120, in addition to one person at the helm and one trimming main when we took a wave that swept everyone off the rail and bent a lifeline stanchion. At that point we sent everyone below except the driver (me), the main trimmer, and the bowman (who periodically went to the low side to vomit).
At dawn we finally gave up and sought refuge in the closest harbor we could fetch, where we found a number of boats that wisely bailed out much earlier than we did. Probably my scariest experience racing.
Have only run under bare poles once before, in a J/105 in 30-40 knots and 10-12 foot seas off California's Pt. Concepcion. In that case, we had torn our roller-furling jib and only had two reef points on the main (which weren't rigged because we stupidly imagined we wouldn't need them). Even under bare poles we were making about 6 knots VMG downwind (in the right direction at least), which is consistent with what it looked like the Dufour 34 "Paula" was doing in the earlier video, under bare poles. When the breeze dropped into the low 20's we put up the .75 oz A-2 and full main and continued racing. One other J/105 was dismasted that evening nearby, but motored safely to port.
I don't enjoy rough weather but I'm not nearly as afraid as I was the first few times. If you trust your boat it makes a huge difference, and J Boats are built pretty tough.
We deal in lead, friend.
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- Reviews
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Yamaha 40th Anniversary Limited Edition SBG3000
September 18, 2009
The reissued SBG3000 is a hefty axe with tone to spareRead More
All You Need is... Bass!
August 19, 2009
A pretty pile of bassesRead More
Claudio Pagelli
August 19, 2009
Four beauties to celebrate Claudio Pagelli''s 30th anniversaryRead More
Bass Collection SB401
August 19, 2009
The origins of a "Bass Collection" bass from the eightiesRead More
1935 Rickenbacker Electro Spanish
August 19, 2009
In an historical sense, the Rickenbacker Electro Spanish is certainly one of the most interesting models, as it was the first commercially produced, American-made electric guitar with a standard orRead More
Elrick Expat Series New Jazz Standard Platinum Series e-volution Single Cut 5 Bass Reviews
August 19, 2009
Two high-end boutique basses from ElrickRead More
Charvel So-Cal 1 2H Guitar Review
August 19, 2009
Charvel''s So Cal 1 2H brings American-made hot rod Strat-style at a reasonable priceRead More
Spector Euro5LX EX & NS-5H2 FM Bass Reviews
August 19, 2009
Spector''s Euro5LX EX and NS-5H2 FM offer two different sets of features for bassists to choose fromRead More
Grosh ElectraJet Standard Review
July 22, 2009
Does the Grosh ElectraJet Standard live up to the fully custom-built legacy of its predecessors? We review it to find out.Read More
Brown's Guitar Factory BGF Rock Guitar Review
July 22, 2009
We review the Rock Guitar from Brown''s Guitar Factory.Read More


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The Cyclone Spoiler II, developed along with the Torino Talladega was one of Ford's "Winged Warriors" from '69. In racing trim, the Spoiler II was... More
1951 Mercury 2 Door Coupe, same owner since 1990, well maintained and in original condition. Flathead V-8 Engine. Brakes and steering are manual. Motor... More
1968 Mercury Cougar Coupe, SHOW CAR - winner of many best paint awards - this car is a "must see"! Renovated inside and out;... More
YOU ARE VIEWING A FULLY CUSTOM 1940 CONVERTIBLE COUPE THAT HAD BEEN COMMISSIONED BY ONE OF THE TOP MOVIE COMPANIES IN THE U.S. TO... More
1955 Mercury Eight Top ZustandThis Mercury is a beautiful Classic with original details. The 2 Tone paint of mint green and dark green is... More
1964 Mercury Parklane Marauder 2dr HT CoupeThis Parklane has the 'Marauder' equipment, so he has a sporty fastback hardtop. The Mercury is equipped with... More
1976 Mercury Marquis 6.6 Liter MotorThis is a wonderful and luxurious Mercury Marquis.A Marquis can easily be compared with the luxery models from Lincoln... More
1970 Mercury Marquis CabrioThis is a wonderful and luxurious Mercury Marquis. The Marquis can be compared with ease with other luxury models such as... More
1972 Mercury Cougar XR7 ConvertibleIn 1967 this car was introduced as a more luxurious version of the Ford Mustang. Meanwhile, the Cougar is still... More
1950 MERCURY. . . . RADICAL CUSTOM LEAD SLED. . . . . .SHOW CAR. . . . THIS MERC HAS IT ALL. !!!!.... More
factory Frigiking air 110 MPH speedometer 3-speed Merc-O-Matic transmission Power steering and brakes Second year for the Monterey station wagon Ford created its Mercury line-up in 1939 to fill... More
1946 Mercury Business coupe, Back to the fifty's in an "old school" custom street rod. Frenched headlights, shaved trunk and hood. If you are... More
1974 Mercury Honoring David Pearson in the classic 1976 Richard Petty/ David Pearson Dual at Daytona. More information and pictures coming soon!! ... More
1949 Mercury Custom 2 Door Coupe, Chopped Top, car is frame off solid straight car, 351 Windsor engine, .030over w/272Crane cam, Edelbrock performer intake/650 Edelbrock carb, C6... More
Affordable fun doesn't come much more honest than this 1976 Mercury Comet. A 63,380 original mile survivor, it's the legendary little old lady special... More


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Technology News
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- Jordan, Egypt discuss ties, potential to benefit from World Economic Forum
- Haven't tried Chamomile Tea before? Here are 6 Benefits to drink it!
- Russia sends Trade Mission of 120 Firms to Egypt next Monday
- Egypt will host 2016 World Economic Forum on MENA: Sisi
- Sisi to sign Energy and Oil Agreements in Germany Visit


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Trying to lose weight? Grab a snack that works with your diet, not against it. Check out these delicious, slimming foods.
8 blood sugar-safe eats.
Your guide to safely exercising throughout your 40 weeks.
Let food be thy medicine and medicine be thy food.
Diet "do's" and "don'ts" for healthy, radiant skin.
Learn how to safely find relief from uncomfortable pregnancy symptoms.


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NEWPORT CITY – The city council Monday approved the 2012-2013 residential municipal tax rate with a three-cent per $100 of assessed value increase. At the same time, the city school has a three-cent decrease, with a final rate of 2.6826 cents, combined educational and residential.
Last year's residential rate, with the education rate, was 2.6814. This year's non-residential tax rate is 2.8530. Last year's rate was 2.8802.
HOLLAND – Local farmer Keith Gray confirmed Monday that illegal dumping is occurring on his property, and he says he doesn't allow it.
Gray was contacted Monday afternoon regarding the issue. Gray said he went up to the site, an old gravel pit on Bullis Road in Holland, Monday evening to look around. He said he found some rubbish, but it has been worse in the past.
NEWPORT - Roger Pion, the 34-year old accused of crushing seven police vehicles with a tractor, is scheduled for arraignment Tuesday, Sept. 18 at 9 a.m. on a new count: driving with a suspended license.
An Orleans Superior Court Judge has found probable cause that when Pion took a tractor and drove through Newport City streets up to the Orleans County Sheriff's Department and crushed six cruisers and a transport vehicle, he did not have a license to drive on the roads.
NEWPORT - Where were you when the sky fell on Sept. 11, 2001?
Shock and disbelief is the way many people describe their reaction to the Sept. 11 terrorists' attacks. Today marks the 11th anniversary of that horrific day.
As with the assassination of President Kennedy and the Challenger explosion, anyone old enough to understand what happened at the time remembers where they were and what they were doing when they learned about the attacks.
Newport City Fire Chief Jamie LeClair was on vacation near Windsor Locks, CT.
IRASBURG – Fire flattened a storage shed and destroyed irreplaceable memories at the Gary and Bonnie Poginy home yesterday.
The fire at Stagecoach Road property broke out at around noon. Jamie Royer, who lives at the home, arrived just as the fire broke out. He said the whole thing was gone in five minutes. The shed previously held the family's horses, but it more recent years the Royers used it for storage. Snowmobiles and family mementos belonging to deceased family members were some of the items lost the in fire.
The family did have insurance on the shed that members built together.
DERBY – Assistant town clerk Maryanne Tetreault's hours were cut earlier this year, reportedly because work was slow, and now she is behind on her duties.
Meanwhile, assistant town clerk Nancy Gosselin and Faye Morin, who was brought in by outgoing clerk Nicole Daigle to learn the office duties, are both clocking overtime.
Gosselin said Monday that she and Morin have had to work a few extra hours because the office is so busy right now with tax season. Gosselin also put in some overtime because of the recent primary.
NEWPORT CITY - With the exception of a few sniffles, not a sound could be heard in Gardner Park Saturday morning as Betty Barrett told the heartbreaking story of how her son, Michael "Guido" Narducci, lost his life to suicide.
With her second husband behind her, holding her for support, she recalled the abuse her now ex-husband gave her and family "relentless." She explained how her ex-husband referred to Michael as a loser. After their divorce, Barrett's ex-husband even lied to their children about her, she said.
VERMONT – The Vermont Department of Health (DOH) says that Vermonters are at risk for serious illness from mosquito bites.
Two people in Vermont are infected with Eastern Equine Encephalitis (EEE) and several independent sources say that one, an 86-year-old man, has died from the disease. Another hospitalized patient is thought to have West Nile Virus. Both diseases are contracted from mosquito bites.
This is the first time EEE was been found in humans in Vermont.
IRASBURG, VT - Scott Bowen, 34, of Irasburg, lost his life Friday in a two-vehicle collision at the intersection of Tree River Campground and VT RT 58 in Irasburg.
According to the Vermont State Police, Bowen was operating a Suzuki Motorcycle sometime before 6 AM, headed east towards Irasburg. At the same time, Randy Machia, 49, of Eden, was operating a 2011 Ford F350 truck and was exiting the campground.
BARTON – Erma Hathaway is bright, talkative and sharp as a tack. Hathaway, a resident at Maple Lane Nursing Home, celebrated her 102nd birthday Thursday, Aug. 30.
Hathaway was born in Delaware County in New York State. As a little girl she worked hard. Hathaway, who grew up on a farm, learned to milk cows at an early age. Her family had 60 Jersey cows.
"I ran the milking machine," said Hathaway. "That was my job principally."
Hathaway mostly milked in the evening, but did the morning chores when her family needed her.


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MLB Matchups >> Detroit vs. Toronto Preview 07/02/2013
The Detroit Tigers and the Toronto Blue Jays will both be trying to pick up a win on Tuesday when they battle at Rogers Centre.
The Tigers will pin their hopes on the pitching of righthander Doug Fister in this game. Fister has a 6-5 record and a 3.50 ERA this season.
Fister's opponent in this one will be Chien-Ming Wang. The Blue Jays righthander has a 5.24 ERA to go along with a 1-1 record this season.
Oddsmakers currently have the Tigers listed as 136-moneyline favorites versus the Blue Jays, while the game's total is sitting at 9½.
Last time out for Detroit, they were an 8-3 loser as they battled the Blue Jays on the road. Moneyline bettors who got the Blue Jays at -127 were rewarded, while the 11 combined runs moved the game OVER for totals bettors.
CURRENT STREAK:Detroit has lost 3 straight games.
TEAM RECORDS:Detroit: 43-38 SU
Toronto: 41-41 SU
DETROIT MOST RECENTLY:When playing on Tuesday are 6-4
Before playing Toronto are 3-7
After playing Toronto are 4-6
After a loss are 5-5
TORONTO MOST RECENTLY:When playing on Tuesday are 3-7
Before playing Detroit are 4-6
After playing Detroit are 3-7
After a win are 7-3
A FEW TRENDS TO CONSIDER:The total has gone OVER in 4 of Detroit's last 5 games when playing Toronto
Detroit is 6-2 SU in its last 8 games when playing Toronto
The total has gone UNDER in 8 of Detroit's last 11 games on the road
The total has gone OVER in 7 of Detroit's last 10 games
Toronto is 5-0 SU in its last 5 games at home
The total has gone OVER in 4 of Toronto's last 5 games when playing Detroit
Toronto is 14-5 SU in its last 19 games
The total has gone OVER in 16 of Toronto's last 23 games at home
NEXT UP:Toronto home to Detroit, Wednesday, July 3


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IDLEWYLDE APARTMENTS1435 Boggs Rd, Duluth, GA 30096 View On Map (770) 923-2987
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