text:
An unusual exhibit about our invasion of Iraq, ten years later
- By Thomas E. RicksThomas E. Ricks covered the U.S. military for the Washington Post from 2000 through 2008. He can be reached at firstname.lastname@example.com.
By Peter Maass
Best Defense guest columnist
Ten years ago, I rolled into Baghdad's Firdos Square with photographer Gary Knight and the Marine battalion that famously draped a flag atop a statue of Saddam Hussein before tearing it down in front of the world's television cameras. As we all know, this moment of promise was followed by a lot of pain. The last American troops have been withdrawn from Iraq, and our attention has turned away, but the invasion's 10th anniversary falls next month, offering a chance to remember and explore the still-painful aftermath.
How can we best do this?
A few years ago, I began working on a story that reconstructed the statue's toppling; it was published by the New Yorker in 2011 but the most important thing is that while reporting it I met Lt. Tim McLaughlin, whose flag was placed on the statue. Tim had left the Marines, gone to law school and was a lawyer in Boston. He shared his war diaries with me, and I realized, when I thumbed through the first pages and sand fell from them (Tim had not touched them since Iraq) that I was holding an amazing document. I had been a foreign correspondent for many years, and had seen lots of documentation about war, but this was the most original and emotional — war as seen by the combatant, in the combatant's handwriting, written in his downtime between battles. It wasn't filtered by the media, by politicians or generals, and it didn't even suffer the visual flattening of a computer font.
The content stunned me. Tim was at the Pentagon on 9/11 and was a tank platoon commander in his tip-of-the-spear battalion in 2003. His diaries contain raw descriptions of everything from the smoke-filled corridors of the Pentagon on that tragic September day to the violence of the Iraq invasion and the craziness of the toppling of the iconic statue. The agony of firing too soon and shooting civilians, and firing too late and losing a fellow Marine to enemy bullets, as well as the boredom and humor and exhaustion of the invasion–these searing things are in the diaries, in addition to Tim's evocative maps and pictures. While the diaries are remarkably personal, they reflect multiple facets of the combatant experience of war.
To cut a long story short, Gary and I discussed the idea of an exhibit centering around the diaries, and Tim readily agreed. The exhibit is called "Invasion: Diaries and Memories of War in Iraq," and it will open in New York City at the Bronx Documentary Center on March 15, just a few days before the invasion's 10th anniversary. The exhibit will feature large-format reprints of pages from Tim's diary, and on some days it will display his American flag, which has not been on public view since its Baghdad cameo. The exhibit will also feature invasion photographs by Gary, who like me was a "unilateral" journalist driving from Kuwait into Iraq in a rented SUV (mine came from Hertz). There will be a few texts by me, as well as videos that feature Tim and news footage from the time. Tim, who is president of a non-profit that provides free legal advice to veterans and the homeless, has received a 50 percent disability rating from the VA for his PTSD diagnosis, and that will be in the exhibit, too.
It's an innovative exhibit that, we hope, will get people thinking about the war and its legacy — things that are slipping into a collective memory hole. We launched a Kickstarter fundraising campaign earlier this month and we're nearing our goal but we're not yet there. If we can reach it and go further, we will start working on stage two of our project — to assemble and publish war diaries from other combatants and civilians. Yes, this post is a bit of a fundraising pitch, though we also want people to just know about the exhibit and not let the anniversary pass without remembrance. In mid-March, Foreign Policy plans to publish an online series of photos and stories about Tim's diaries.
For Tim, Gary, and me, it has been an uphill battle. Part of the backstory involves being turned down by a number of galleries and museums before the non-profit Bronx Documentary Center agreed, enthusiastically, to host our exhibit. The fancy places were not interested in Iraq — old news, time to move on, tired of war, there's no money to be made in war diaries, etc. We have been working on this as a labor of love, because we think it's a unique and provocative way to fight the tide of forgetting.
Please come visit the exhibit when it opens on March 15, and if you can help our fundraising, we would be delighted, too. Also, if you are affiliated with an organization that would be interested in hosting the exhibit after it closes in New York, please give us a shout.
Peter Maass, author of Love Thy Neighbor and Crude World, has written about Iraq and Afghanistan for the New Yorker and the New York Times Magazine. Gary Knight is a founder of the VII Photo Agency and director of the Tufts University Program for Narrative & Documentary Practice. Tim McLaughlin is a lawyer in Boston and president of Shelter Legal Services, which provides free legal advice to veterans and the homeless.
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Petraeus' Act II; A Marine lieutenant remembers Iraq; Does Hagel need a Robert Rangel?; Cyber chief: civil agencies should lead after a cyber attack; and a little more.Gordon Lubold
Gordon Lubold is a national security reporter for Foreign Policy. He is also the author of FP's Situation Report, an e-mailed newsletter that is blasted out to more than 70,000 national security and foreign affairs subscribers each morning that includes the top nat-sec news, breaking news, tidbits, nuggets and what he likes to call "candy." Before arriving at FP, he was a senior advisor at the United States Institute of Peace in Washington, where he wrote on national security and foreign policy. Prior to his arrival at USIP, he was a defense reporter for Politico, where he launched the popular Morning Defense early morning blog and tip-sheet. Prior to that, he was the Pentagon and national security correspondent for the Christian Science Monitor, and before that he was the Pentagon correspondent for the Army Times chain of newspapers. He has covered conflict in Iraq, Afghanistan, Pakistan and other countries in South Asia, and has reported on military matters in sub-Saharan Africa, East Asia and Latin America as well as at American military bases across the country. He has spoken frequently on the sometimes-contentious relationship between the military and the media as a guest on numerous panels. He also appears on radio and television, including on CNN, public radio's Diane Rehm and To the Point, and C-SPAN's Washington Journal. He lives in Alexandria with his wife and two children.| Situation Report |


text:
Re-visiting history, re-negotiating identity in two black British fictions of the 21st Century: Caryl Phillips's A distant shore (2003) and Buchi Emecheta's The new tribe (2000)
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Re-visiting history, re-negotiating identity in two black British fictions of the 21st Century: Caryl Phillips's A distant shore (2003) and Buchi Emecheta's The new tribe (2000)
Moudouma Moudouma, Sydoine
Notions of home, belonging, and identity haunt the creative minds of fiction writers belonging to and imagining the African diaspora. Detailing the ways in which two diasporic authors "re-visit history" and "re-negotiate identity", this thesis grapples with the complexity of these notions and explores the boundaries of displacement and the search for new home-spaces. Finally, it engages with the ways in which both authors produce "new tribes" beyond the bounds of national or racial imaginaries. Following the "introduction", the second chapter titled "River Crossing" offers a reading of Caryl Phillips's A Distant Shore, which features a black African man fleeing his home-country in search of asylum in England. Here, I explore Phillips's representation of the "postcolonial passage" to the north, and of the "shock of arrival" in England. I then analyse the ways in which the novel enacts a process of "messing with national identity". While retracing the history of post-Windrush migration to England in order to engage contemporary immigration, A Distant Shore, I argue, also re-visits the trans-Atlantic slave trade. In the final section, I discuss "the economy of asylum" as I explore the fates of the novel's two central characters: the African asylum-seeker and the outcast white English woman. My reading aims to advance two points made by the novel. Firstly, that individuals are not contained by the nations and cultures they belong to; rather, they are owned by the circumstances that determine the conditions of their displacement. Phillips strives to tell us that individuals remain the sites at which exclusionary discourses and theories about race, belonging and identity are re-elaborated. Secondly, I argue that no matter the effort exerted in trying to forget traumatic pasts in order to re-negotiate identity elsewhere, individuals remain prisoners of the chronotopes they have inhabited at the various stages of their passages. The third chapter focuses on Buchi Emecheta's The New Tribe. Titled "Returning Home?", it explores the implications of Emecheta's reversal of the trajectory of displacement from diasporic locations to Africa. The New Tribe allows for the possibility of re-imagining the Middle Passage and re-figuring the controversial notion of the return to roots. In the novel, a young black British man embarks on a journey to Africa in search of a mythic lost kingdom. While not enabling him to return to roots, this journey eventually encourages him to come to terms with his diasporic identity. Continuing to grapple with notions of "home", now through the trope of family and by engaging the "rhetoric of return", I explore how Emecheta re-visits the past in order to produce new identities in the present. Emecheta's writing reveals in particular the gendered consequences of the "rhetoric of return". Narratives of return to Africa, the novel suggests, revisit colonial fantasies and foster patriarchal gender bias. The text juxtaposes such metaphors against the lived experience of black women in order to demythologise the return to Africa and to redirect diasporic subjects to the diasporic locations that constitute genuine sites for re-negotiating identity.
Thesis (MA (English Literature))--University of Stellenbosch, 2009.
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Q. "If I order a thermostatic valve, do I need to purchase a volume control valve and vise versa?"
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This is an apolitical forum for discussions on the Axis nations and related topics hosted by Marcus Wendel's Axis History Factbook in cooperation with Christian Ankerstjerne's Panzerworld and Christoph Awender's WW2 day by day.
Founded in 1999.
MajorT wrote:Hi Glenn,
Even odder,
1) Nobody has claimed that the Austrian cabinet did order "the mobilization of the Russian and French armies".
2) It couldn't do so anyway.
What, exactly, is your source of misapprehension on this point?
But the world war was caused by Russia mobilizing its entire armed forces and thereby creating triggering the casus belli with Germany.
Therefore, you must think that Austria ordered the Russian mobilization. It did not, and did not wish it.
then this idea stands in defiance of all Great Power precedent between 1815 and 1913 - where such minor dust ups never once caused a world war
MajorT wrote:Hi Glenn,
What I actually wrote was:
"However, this need not prevent us from identifying who decided to risk turning yet another Balkan diplomatic crisis into a war that grew into WWI.
It was the Austro-Hungarian cabinet on 7 July, with German foreknowledge and support."
Perhaps you would care to give the date of delivery of the Austro-Hungarian ultimatum to Serbia and the date of the Russian mobilization?
MajorT, the world war occured because Russia mobilized at Germany.
The Austrian dispute with Serbia was no excuse for Russia to start a world war.
Between 1815 and 1914 not one Great Power used a minor war as a pretext to trigger a global conflict.
Or would you blame the third party that used the Boer war as an excuse, a pretext, for aggression?
Terry Duncan wrote:Far more key is the fact that Germany had decided to mobilize before she had any certain knowledge of Russian mobilization, so it cannot have been decided on because of that act.
You have made this statement before (on the HC board) and more than once. You were corrected each time
Where is your proof for this outlandish statement?
Moltke was aware that for Germany, if not for the other powers, mobilisation would mean war.
Strachan, Hew (2005-04-05). The First World War (Kindle Locations 490-495). Penguin. Kindle Edition.
The emphasis on speed of mobilization, the interaction of war plans, and Germany's central geographical position meant that a chain reaction became possible. But the interlocking sequence of mobilizations can be exaggerated; Serbia decided to mobilize ahead of Austria-Hungary; Austria-Hungary settled for general mobilization before Russia's position was known; Russia's move to mobilization preceded Germany's and yet Germany's decision was made before it was aware of the Russian position; Britain responded to Germany before it had decided to honour any commitment to France. The imperative of the alliance system was not one of altruism. But of brutal self-interest: Germany needed Austria-Hungary; France's military position was dependant on Russian support; British diplomacy was unsustainable if it allowed the Entente to shatter.
Strachan is plain wrong to state, as he does, that mobilization had been used before to buttress diplomacy.
But general mobilization by a Great Power was generally understood to mean that it had only resorted to this final step of putting the great military machine in motion, with the automatic movement of the troops to the frontier with the greatest despatch, when it had finally concluded that war could no longer be avoided."
The words of Sasonov and the Czar confirm this."
I know what it is. You mean to make war on Serbia. . . . You are setting fire to Europe. It is a great responsibility that you are assuming, you will see the impression that it will make here and in London and Paris and perhaps elsewhere. It will be regarded as an unjustifiable aggression. . . Why was Serbia given no chance to speak and why the form of an ultimatum? The monarchic idea has got nothing to do with it. . . . The fact is you mean war and you have burnt your bridges. . . . One sees how peace loving you are, seeing that you set fire to Europe.
Did you think, Terry, that you could make your threadbare canard [about this supposed German mobilization] come true by sheer force of repetition?
(BTW: Germany did not "negotiate" after the Russian mobilization.
Germany gave Russia twelve hours to suspend.
This is hardly "negotiation."
I see you have not forgotten your old trick of misquoting people.
Fay said: "Mobilization means war." He said this without qualifications of any sort.
This is so patently false that it calls into question the rest of Mr. Strachan's conclusions.
Show me a shred of evidence (other than Strachan's wrong-headed notion) that the German decision to mobilize came "before it was aware of the Russian position."
(BTW: The book to which your link points, is the same book I have on my Kindle-for-PC)
MajorT wrote:Hi Glenn,
Let's keep this clean.
You write:
"I ask you again - if the Boer War had caused a world war, do you really think it would be Britain and the Boers that were responsible? Or would you blame the third party that used the Boer war as an excuse, a pretext, for aggression?"
When did you ever ask me this before?
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A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309 a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU. The arbitration circuitry is operable to schedule access to the shared resource according to higher of the pair of priority values provided by each processor.
1. A method for prioritizing access to a shared resource in a digital system having a plurality of devices vying for access to the shared resource, comprising the steps of:
initiating an access request by each of the plurality of devices;
associating two priority values along with each access request from each device; and
arbitrating for access to the shared device by using the higher of the two priority values associated with each single access request.
2. The method of
establishing a software priority state associated with a program module;
executing an instruction from the program module on a first of the plurality of devices to form an access request to the shared resource; and
providing an access priority value with the access request that is responsive to the software priority state of the program module.
3. The method of
4. The method of
assigning address space priority values to pages of memory according to programs or data stored in each page of the memory;
storing at least a portion of the address space priority values in page entries associated with a memory management unit; and
querying the memory management unit with the address specified by the access request.
5. The method according to
selecting a higher priority value from each of the two priority values from each device; and
comparing each of the higher priority values selected from the plurality of devices.
6. The method according to
7. A digital system comprising:
a shared resource;
a plurality of devices connected to access the shared resource, wherein each device has a request output and circuitry for providing two separate variable priority values;
arbitration circuitry connected to receive a request signal from the request output of each device, wherein the arbitration circuitry is operable to schedule access to the shared resource according to the higher of the two priority values with each single access request.
8. A digital system comprising:
a shared resource;
a plurality of devices connected to access the shared resource, wherein each device has an access priority register and a request output, wherein the access priority register of each device is loaded with a value by software executing on the respective device;
a plurality of memory management units each connected to receive a virtual address from a respective one of the plurality of devices, wherein each memory management unit stores a plurality of page entries and has an output for an address space priority value contained in each page entry; and
arbitration circuitry connected to receive a request signal from each request output along with an access priority value from each access priority register and an address space priority value from each memory management unit, wherein the arbitration circuitry is operable to schedule access to the shared resource according to the access priority value and the address space priority value.
9. The digital system of
10. The digital system according to
11. The digital system according to
an integrated keyboard connected to at least one of the devices via a keyboard adapter;
a display connected to at least one of the devices via a display adapter;
radio frequency (RF) circuitry connected to at least one of the devices; and
an aerial connected to the RF circuitry.
12. The method of
determining a performance requirement of a software task being executed on the device;
selecting a software priority state according to the performance requirement of the task that is then used by the step of providing an access priority value.
13. The method of
saving the selected software priority state along with other context information in response to an interrupt; and
restoring the software priority state by using the saved software priority state after completion of the interrupt.
14. The method of
providing an access priority value with each request that is responsive to a task currently being executed by the device;
providing an address space priority value with each request that is responsive to an address specified by each access request.
15. The method of
providing a task identification (task ID) with each request indicative of the task currently being executed by the device; and
determining an access priority value from a stored table using the task ID as an index.
16. The method of
wherein the access priority value is responsive to both the software priority state of the program module and the hardware priority state of the first device.
This application claims priority to European Application Ser. No. 00402331.3, filed Aug. 21, 2000 (TI-31366EU) and to European Application Ser. No. 01400818.9, filed Mar. 29, 2001 (TI-31347 EU). U.S. patent application Ser. No. 09/932,651 (TI-31366US), now U.S. Pat. No. 6,751,706, is incorporated herein by reference.
This application is related to U.S. patent application Ser. No. 09/932,556 (TI-32850) entitled Access Priority Management, and to U.S. patent application Ser. No. 09/932,380 (TI-3 1346), now U.S. Pat. No. 6,684,280, entitled Task Based Priority Arbitration.
This invention generally relates to microprocessors, and more specifically to improvements in access to shared resources, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
Modular programming builds a computer program by combining independently executable units of computer code (known as modules), and by tying modules together with additional computer code. Features and functionality that may not be provided by a single module may be added to a computer program by using additional modules.
The design of a computer programming unit known as a task (or function) is often accomplished through modular programming, where a specific task is comprised of one module and the additional computer code needed to complete the task (if any additional code is needed). However, a task may be defined as broadly as a grouping of modules and additional computer codes, or, as narrowly as a single assembly-type stepwise command. A computer program may be processed (also called "run" or "executed") in a variety of manners. One manner is to process the computer code sequentially, as the computer code appears on a written page or on a computer screen, one command at a time. An alternative manner of processing computer code is called task processing. In task processing, a computer may process computer code one task at a time, or may process multiple tasks simultaneously. In any event, when processing tasks, it is generally beneficial to process tasks in some optimal order.
Unfortunately, different tasks take different amounts of time to process. In addition, the result, output, or end point of one task may be required before a second task may begin (or complete) processing. Furthermore, particularly in a multiple processor environment, several tasks may need access to a common resource that has a generally fixed capacity.
Accordingly, there is needed a system and method for managing task processing that takes into account task processing times, resource capabilities and capacity, and other task processing needs.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first embodiment of the invention, there is provided a digital system having several processors and a shared resource that is accessed by the processors. Each processor provides two priority values along with each request for access to the shared resource. Access to the shared device is scheduled by arbitration circuitry using the higher of the two priority values from each device.
In another embodiment, one of the priority values is provided by an access priority register on each processor that is loaded with an access priority value by software executing on the processor. A software state is established during execution of a sequence of instructions on each of the several devices. An instruction is executed on each device to form an access request to the shared resource. An access priority value is provided with each access request that is responsive to the software state of the respective device.
In another embodiment, one of the two priority values is an address space priority value that is provided by assigning address space priority values to pages of memory according to programs or data stored in each page of the memory. At least a portion of the address space priority values are stored in page entries associated with a memory management unit. For each request the memory management unit is queried with the address specified by the access request.
In another embodiment, another device vying for access to the shared resource provides one or the other but not both of the two priority values.
Particular embodiments in accordance with the invention will now be described, by way of example only, and with reference to the accompanying drawings in which like reference signs are used to denote like parts and in which the Figures relate to the digital system of
Corresponding numerals and symbols in the different figures and tables refer to corresponding parts unless otherwise indicated.
Although the invention finds particular application to Digital Signal Processors (DSPs), implemented, for example, in an Application Specific Integrated Circuit (ASIC), it also finds application to other forms of processors. An ASIC may contain one or more megacells which each include custom designed functional circuits combined with pre-designed functional circuits provided by a design library.
Referring again to
External to the megacell, a level three (L3) control block 130 is connected to receive memory requests from internal traffic control block 110 in response to explicit requests from the DSP or MPU, or from misses in shared cache 114. Off chip external memory 132 and/or on-chip memory 134 is connected to system traffic controller 130; these are referred to as L3 memory subsystems. A frame buffer 136 and a display device 138 are connected to the system traffic controller to receive data for displaying graphical images. A host processor 120 a interacts with the external resources a system traffic controller 130. A host interface connected to traffic controller 130 allows access by host 120 a to external memories and other devices connected to traffic controller 130. Thus, a host processor can be connected at level three or at level two in various embodiments. A set of private peripherals 140 are connected to the DSP, while another set of private peripherals 142 are connected to the MPU.
Similarly, MPU 102 includes a configurable cache 223 that is configured as a local memory 220 and data cache 222, and a configurable cache 224 that is configured as instruction cache 226 and a RAM-set 228, again referred to as L1 memory subsystems. The MPU is connected to traffic controller 110 via an L2 interface 230 that also includes a TLB 232. A DMA circuit 234 is also included within the MPU. Individual micro TLBs (μTLB) 236–238 are associated with the DMA circuit, data cache and instruction cache, respectively.
L2 traffic controller 110 includes a TLB 240 and one or more micro-TLB (μTLB) 242 that are associated with system DMA block 106, host processor interface 120 b for a host connected at level two, and other application specific hardware accelerator blocks. Similarly, L3 traffic controller 130 includes a μTLB controllably connected to TLB 240 that is associated with system host 120 a at level three. This μTLB is likewise controlled by one of the megacell 100 processors.
Memory Management Unit
At the megacell traffic controller level, all addresses are physical. They have been translated from virtual to physical at the processor sub-system level by a memory management unit (MMU) associated with each core, such as DSP core 105 and MPU core 103. At the processor level, access permission, supplied through MMU page descriptors, is also checked, while at the megacell level protection between processors is enforced by others means, which will be described in more detail later.
The translation look-aside buffer (TLB) caches contain entries for virtual-to-physical address translation and access permission checking. If the TLB contains a translated entry for the virtual address, the access control logic determines whether the access is permitted. If access is permitted, the MMU generates the appropriate physical address corresponding to the virtual address. If access is not permitted, the MMU sends an abort signal via signal group 244 to the master CPU 102. The master CPU is identified by the value of the R-ID field. On a slave processor such as a hardware accelerator the R-ID is equal to the R-ID of the master CPU.
Upon a TLB miss, i.e., the TLB does not contain an entry corresponding to the virtual address requested, translation table walk software retrieves the translation and access permission information from a translation table in physical memory. Once retrieved, the page or section descriptor is stored into the TLB at a selected victim location. Victim location selection is done by software or with hardware support using methods known by persons skilled in the art.
Translation Table
To provide maximum flexibility, the MMU is implemented as a software table walk, backed up by TLB caches both at the processor sub-system and megacell level. This allows easy addition of new page size support or new page descriptor information if required. A TLB miss initiates an MMU handler routine to load the missing reference into the TLB. At the Megacell 100 level, a TLB miss asserts a miss signal in signal group 244 and is routed via system interrupt router 250 to the processor having generated the missing reference or to the processor in charge of the global memory management, via interrupt signals 251, 252.
The present embodiment has a distributed operating system (OS) with several domains corresponding to each processor and therefore only a single table manager for all processors. Table update operations are limited to the corresponding R-ID for all slave processors. Access to all could be given to a super OS, such as a communication management OS. The super OS will have right to flush out entries belonging to another processor in a different OS domain. In another embodiment with several independent OSs, for example, there will independent tables. These tables can be located in a memory space only viewed by the OS that they are associated with in order to provide protection from inadvertent modification by another OS.
Translation tables and TLB cache contents must be kept consistent. A flush operation is provided for this reason.
An address reference is generally located within the μTLB or main TLB of each processor sub-system; however, certain references, such as those used by system DMA 106 or host processor 120, for example, to access megacell memories can be distributed within L2 traffic controller 110 and cached into L2 system shared TLB 240. Because system performance is very sensitive to the TLB architecture and size, it is important to implement efficient TLB control commands to flush, lock or unlock an entry when a task is created or deleted without degrading the execution of other tasks. Therefore, each μTLB and L2 cache entry holds a task-ID. During execution, the current task-ID register is compared with the μTLB entry, this also provides better security, as will be described later. During MMU operation, commands are supplied to flush locked or unlocked entries of a μTLB corresponding to a selected task.
The MMU provides cacheability and bufferability attributes for all levels of memory. The MMU also provides a "Shared" bit for each entry to indicate that a page is shared among multiple processors (or tasks). This bit, as standalone or combined with the task-ID, allows specific cache and TLB operation on data shared between processors or/and tasks. The MMU may also provides additional information, such as memory access permission and access priority as described later.
All megacell memory accesses are protected by a TLB. As they all have different requirements in term of access frequencies and memory size, a shared TLB approach has been chosen to reduce the system cost at the megacell level. This shared TLB is programmable by each processor. The architecture provides enough flexibility to let the platform work with either an independent operating system (OS) or a distributed OS with a unified memory management, for example.
The organization of the data structures supporting the memory management descriptor is flexible since each TLB miss is resolved by a software TLB-miss handler. These data structures include the virtual-to-physical address translation and all additional descriptors to manage the memory hierarchy. The list of these descriptors and their function is described in Table 2. Table 1 includes a set of memory access permission attributes. In other embodiments, a processor may have other modes that enable access to memory without permission checks.
A separate TLB entry register 330 is only one possible implementation and is not necessarily required. The separate register TLB entry register is a memory mapped register that allows buffering of a complete TLB entry (more than 32 bits). A TLB value is not written directly in the TLB cache but is written to the TLB entry register first. Because of the size of an entry, several writes are required to load the TLB entry register. Loading of a TLB cache entry is then done in a single operation "Write TLB entry". Advantageously, others uTLBs associated with other modules can continue access the shared TLB while the TLB entry register is being loaded, until a second miss occurs.
The sequence of operations to update a TLB cache entry after a miss is:
The priority on the shared TLB is managed in the same way as priority on a memory access. One or more resources can be using the shared TLB. One or more resources can program the shared TLB. The replacement algorithm for selecting the next victim location in the shared TLB is under hardware control. A victim pointer register 322 is maintained for each TLB and μTLB to provide a victim separate pointer for each. A typical embodiment will use a round robin scheme. Another embodiment may use a least recently used scheme or a random scheme, for example. Different TLBs within a single megacell can use different replacement schemes. However, in an embodiment in which the system has a master CPU with a distributed OS, this master CPU could also bypass the hardware replacement algorithm by selecting a victim entry, reading and then writing directly to the Shared TLB.
In this embodiment, each shared TLB has 256 entries. Each μTLB is generally much smaller, i.e., has fewer entries, than the shared TLB. In various embodiments, each shared TLB has 64–256 or more entries while μTLBs generally have 4–16 entries. The penalty for a miss in a μTLB is small since a correct entry is generally available from the shared TLB. Therefore, the present embodiment does not provide direct control of the victim pointers of the various μTLBs; however, direct control of the victim pointer of shared TLBs, such as 212, 232, and 240, is provided.
Each entry in a TLB has a resource identifier 301 along with task-ID 302. Resource-IDs and task IDs are not extension fields of the virtual address (VA) but simply address qualifiers. A task ID is provided by a task-ID register, such as task-ID register 344 associated with processor 340. Resource IDs are provided by a resource-ID register associated with each resource; such as R-ID register 342 associated with processor 340 and R-ID register 352 associated with resource 350. With the task-ID, all entries in a TLB belonging to a specific task can be identified. They can, for instance, be invalidated altogether through a single operation without affecting the other tasks. Similarly, the resource ID is required because task-ID number on the different processors might not be related; therefore, task related operations must be, in some cases, restricted to a resource-ID. At system initialization, all R-ID and Task-ID registers distributed across the system are set to zero, meaning that the system behaves as if there were no such fields.
In another embodiment, The R-ID and Task_ID registers are not necessarily part of the resource core and can be located in the system, such as a memory mapped register for example, and associated to a resource bus. The only constraint is that a task_ID register must be under the associated OS control and updated during context switch. R-ID must be set during the system initialization.
Referring still to
Each TLB entry also includes "shared" bit 303 and a lock bit 304. All entries marked as shared can be flushed in one cycle globally or within a task. A V field 307 indicates if an associated TLB cache entry is valid. V field 307 includes several V-bits that are respectively associated with R-ID field 301 to indicate if a valid R-ID entry is present, task-ID field 302 to indicate if a valid task-ID entry is present, and virtual address field 305 to indicate if a valid address entry is present.
TLB control register set 330 also includes a resource ID and task ID register to check that this address is allowed for a specific resource or for all and for a specific task or for all. When an address is missing from the μTLB, it searches the shared TLB. If a miss occurs in both, an interrupt is returned to the processor in charge.
Still referring to
In this illustration, a circle such as 1442 represents a task, with a task name "c" and a task priority of 12, for example. Likewise, task 1443 has a task name "r" and a priority of 15, where a lower number indicates a higher priority. If the set of tasks 1440 are assigned to three processors, then an operating system on each processor forms a ready to execute queue, such as ready queue 1446 in which task "c" is scheduled for first execution, then task "a" and finally task "b" according to priority values of 12, 15, and 50 respectively. In a prior system, access to shared resources 1432 would be based on an access priority associated with the processor on which a task is executed. Unfortunately, this scheme may result in slow execution of a high priority task on a low priority processor.
In latency timeline 502 using CPU priority, request c.12 and r.15 occur simultaneously; CPU1 has higher priority than CPU2 and request c.12 is scheduled for shared resource 1432 first. Request j.02 from CPU 3 and r.15 from CPU 2 next via for access. Since CPU2 has higher priority than CPU3, request r.15 is scheduled next and then followed by j.02 at time 510. Then, request a.15 and r.15, followed by request a.15 and x.50 are scheduled before request j.02 is scheduled at time 512.
In latency timeline 500 using task priority, request c.12 and r.15 occur simultaneously; task c.12 has higher priority than r.15 and request c.12 is scheduled for shared resource 1432 first. Request j.02 from CPU 3 and r.15 from CPU 2 next via for access. Since task j.02 has higher priority than task r.15, request j.02 is scheduled next at time 514 followed by request r.15. Then, requests a.15, r.15 and j.02 all occur at approximately the same time. Since task j.02 has the highest priority, request j.02 is next scheduled at time 516. Advantageously, latency time 524 for high priority task j.02 executed on low priority CPU3 using task priority is less than latency time 520 using CPU priority. Similarly, latency time 526 is less than latency time 522.
Referring again to
In another embodiment, only the task-id is exported with the memory access request to the traffic controller and the task-id is used to retrieve the access priority at the system level inside the traffic controller through a look-up table, using content addressable memory, for example.
One bit 1410 a of register 1410 is responsive to interrupt signal 1414 such that whenever processor 1400 performs a context switch in response to an interrupt, bit 1410 a is set to a value to indicate an interrupt service routine (ISR) is being executed.
In a first embodiment with a simple solution, portion 1410 b of register 1410 is only one bit, such that register 1410 is a 1+1 bit register (2-bits). As discussed above, bit 1410 a is set by the hardware when an interrupt (or an exception) occurs. In this embodiment, bit 1410 a is the msb of register 1410. An application program being executed by processor 1400 can configure portion 1410 b, the lsb bit, and will provide one value, such as "0," to the bit if the application must execute with a defined maximum real time limit, referred to as "hard real time" (HRT). On the other hand, an application that does not have a hard time limit or a less critical soft real time limit will provide another value, such as "1," to the bit to indicate "not hard real time" (NHRT) or leave a default low priority provided by the OS. An operating system on processor 1400 can control both bits. Thus, a 2-bit priority state code is formed as described in Table 3. In the case of an interrupt, the contents of priority register 1410 are saved during an ISR context switch.
Since there are two bits, one of the four priority states is used to differentiate an operating system (OS) kernel state from the Interrupt state to manage the shared resource access priority in a finer way. It is important to serve the OS before any application because the OS task scheduler can invert execution priorities. It is also important to differentiate the interrupt state from the kernel state so as not to leave one CPU with highest priority for a long period. Advantageously, an interrupt on a CPU can be served with minimum delay.
If several CPUs access the memory with the interrupt priority state they are served in a round-robin manner using the fixed processor resource priority. In an alternative embodiment, a hierarchical priority or round robin priority can be observed.
Memory access priority can be established in several ways. For example, Table 4 illustrates several portions of instruction code sequences in which a task is spawned and the new task establishes it's priority as it's first operation. In line 1, task "a" is active and spawns a new task, "audio" on line 3. The kernel is then invoked to instantiate the task and a default task priority of NHRT is set at line 8. At line 11, the new task is now active. Among it's first line of code at line 13 is a directive to set the task priority to HRT, making this a high priority task. If the task had done nothing, it would have remained a low priority task by default.
SetTaskAttributePriority is a system call that initializes the memory access priority (MA_priority) associated with a task, as defined in a task control block. The system call also sets the priority register associated with the task_id register.
Table 5 is an example task control block that is used to define a task. At line 4, an execution priority value is defined that is used by the operating system to schedule execution of the task. At line 9, a memory access priority value is defined that is used to set the task priority register when the task is instantiated. In some embodiment, as described later, these two fields can be combined in a single one corresponding to the OS task priority.
In other embodiments, other means than a TCB may be provided for setting task memory access priority. For example, a call can be made to a subroutine and access priority can be set by either the call or by an operation at the beginning of the subroutine.
In this embodiment, register 1410 is a portion of a status register within the CPU core, such as DSP core 105 and MPU core 103. A call is provided to allow an application program to control only a single bit of the priority register resulting in encoded state '10' or '11', as illustrated at line 13 of Table 3. In another embodiment, register 1410 may be a separate memory mapped register or other type of register that can be controlled by the associated CPU and saved during a context switch and whose outputs can be provided to arbitration circuitry for the shared resource.
In another embodiment, access priority might not be saved on a context switch and the Operating System takes the value held in the MA_priority the task control block (TCB) on each rescheduling to program the priority register, for example.
In software execution state 610, a task 1 is executing with a low access priority, NHRT.
In software execution state 612, an interrupt occurs and execution is transferred to interrupt service routine x (ISR). The access priority "11" associated with software execution state 610 is saved during the resulting context switch and access priority "00" is set by CPU hardware in response to the interrupt. Thus, a hardware state is entered in response to the interrupt and the access priority register is modified in response to this hardware state.
In software execution state 614, ISR x initiates execution of the OS Kernel scheduler by performing a system call. OS software sets the access priority to "01" by writing to priority register 1410. During this execution state, the kernel schedules task 2 for execution.
In software execution state 616, task 2 is activated as part of ISR x and has a hard real time limit. The OS sets the access priority to "11" by writing to the priority register, but the first operation of an HRT task is to set the access priority to "10" by sending a command to set the LSB of the priority register to "0" . As mentioned above, an application program cannot change the MSB of the priority register.
In software execution state 618 a second interrupt y is taken, since the interrupt priority of interrupt y is greater than the interrupt priority of interrupt x. Again, the access priority of task 2 is saved during the resulting context switch and the access priority is forced to "00" by CPU hardware.
In software execution state 620, ISR y calls the OS and the scheduler in invoked. The OS sets the access priority to "01" and during this execution state schedules task 3 for execution.
In software execution state 622, task 3 is activated as part of ISR y and has a hard real time limit. The OS again sets the access priority to "11," which is the default lowest NHRT priority, but the first operation of an HRT task is to set the access priority to "10" by sending a command to set the LSB of the priority register to "0".
In software execution state 624, task 3 performs a "return" to complete ISR y and the scheduler is again invoked.
In software execution state 626, a context switch restores task 2 and its access priority value of "10".
In software execution state 628, task 2 performs a "return" to complete ISR x and the scheduler is again invoked.
In software execution state 630, a context switch restores task 1 and its NHRT access priority value of "11".
Of course, this illustration is merely illustrative of the types of sequences that can occur during program execution.
In summary, a variable access priority is provided. The OS kernel can vary the access priority by writing to the priority register. A hardware state, such as in response to an interrupt, can change the access priority. Various program modules of an application program can change the access priority in a limited range.
In an alternative embodiment, priority register portion 1410 b is n bits, where n is generally 8-bits for a Real Time Operating System (RTOS), for example. One bit 1410 a of register 1410 is responsive to interrupt signal 1414 such that whenever 1400 performs a context switch in response to an interrupt, bit 1410 a is set to a value to indicate an interrupt service routine (ISR) is being executed. Bit 1410 a is treated as a most significant bit of priority register 1410, thus 1+n bits are provided for the access priority field register 1410. In this embodiment, a task priority corresponding to the OS-priority field in line 4 of Table 4 associated with each task is loaded in priority register portion 1410 b as each task begins execution. In this case, the same value that is used for OS scheduling, such as the value at line 3 of Table 5, can be used for memory access scheduling. Alternatively, a different memory access value of n bits can be specified by defining a value, such as at line 9 of Table 5. Advantageously, in this embodiment there is no need for an extra access priority register; the OS execution priority register is used for both functions.
In either embodiment, the 2 bits or n+1 bits are used to control the priority of accesses to shared resources 1432. In addition, each CPU resource is also assigned a priority. If two resource make a requests with identical task priority to a shared resource, then access to the shared resource is provided in a round robin manner so that the higher priority resource doesn't starve the lower priority resource. Other embodiments may use other mechanism than round robin, such as a random or a fixed order of selection, for example.
When processor 740(0) makes an access request to shared memory 750, a pair of priority values are conveyed to traffic manager arbitration circuitry 1430 along with the request. The first value is the task based priority value provided by task priority register 1410, as discussed earlier. The second value is an address space priority value provided by attribute subfield 309 a from TLB 700(0) in response to the address of the access request provided by the processor to the TLB on address bus 742(0). Arbitration circuitry 1430 evaluates both priority values of the pair and compares them to other priority value pairs from other pending requesters, such as processor 740(n). The request having the highest priority value is scheduled to have first access to shared resource 750.
For example, assume processor 740(0) is executing a task with a task priority of 5, as indicated by task priority register 1410, and requests an access to a page in shared memory 750 that has a address space priority of 15 as indicated by attribute subfield 309 a in TLB 700(0). Also assume that processor 740(n) is executing a task with a task priority of 20 and requests an access to a page in shared memory 750 that has a address space priority of 0. In this case, processor 740(0) is executing a higher priority task, but processor 740(n) is accessing a page in memory that has a yet higher priority; therefore, processor 740(n) is scheduled to access memory 750 first.
Other embodiments of address space priority mechanisms are described in co-related U.S. Pat. Ser. No. 09/932,556 (TI-32850) which is incorporated herein by reference.
In another embodiment, a TLB may not be needed to provide the physical address. In that case, address signals are provided directly from the requesting device, for example. However, in such an embodiment, priority circuitry can be provided that responds to an address from a requesting device to provide a priority value responsive to a region of address space that is being requested. In this manner, a requesting device provides both a task based priority and an address space region priority and resource allocation is based on the highest priority value.
Digital System Embodiment
It is contemplated, of course, that many other types of communications systems and computer systems may also benefit from the present invention, particularly those relying on battery power. Examples of such other computer systems include personal digital assistants (PDAs) portable computers, smart phones, web phones, and the like. As power dissipation is also of concern in desktop and line-powered computer systems and micro-controller application, particularly from a reliability standpoint, it is also contemplated that the present invention may also provide benefits to such line-powered systems.
Fabrication of the digital systems disclosed herein involves multiple steps of implanting various amounts of impurities into a semiconductor substrate and diffusing the impurities to selected depths within the substrate to form transistor devices. Masks are formed to control the placement of the impurities. Multiple layers of conductive material and insulative material are deposited and etched to interconnect the various devices. These steps are performed in a clean room environment.
A significant portion of the cost of producing the data processing device involves testing. While in wafer form, individual devices are biased to an operational state and probe tested for basic operational functionality. The wafer is then separated into individual dice which may be sold as bare die or packaged. After packaging, finished parts are biased into an operational state and tested for operational functionality.
The digital systems disclosed herein contain hardware extensions for advanced debugging features. These assist in the development of an application system. Since these capabilities are part of the megacell itself, they are available utilizing only a JTAG interface with extended operating mode extensions. They provide simple, inexpensive, and speed independent access to the core for sophisticated debugging and economical system development, without requiring the costly cabling and access to processor pins required by traditional emulator systems or intruding on system resources.
As used herein, the terms "applied," "connected," and "connection" mean electrically connected, including where additional elements may be in the electrical connection path. "Associated" means a controlling relationship, such as a memory resource that is controlled by an associated port. The terms assert, assertion, de-assert, de-assertion, negate and negation are used to avoid confusion when dealing with a mixture of active high and active low signals. Assert and assertion are used to indicate that a signal is rendered active, or logically true. De-assert, de-assertion, negate, and negation are used to indicate that a signal is rendered inactive, or logically false.
As used herein, the term "higher priority" and "lower priority" refers to a logical value and not necessarily to a numeric value. For example, higher priority can be accorded to a lower numeric value.
A shared resource is typically a memory of a cache. However, other resources may be shared and make use of access scheduling using priority values as described herein. For example, memory mapped input/output (I/O) devices and ports, shared TLBs as described with respect to
While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. For example, in another embodiment, one or more devices provide both an address space priority value and a task priority value, while in the same system other devices provide one, but not both variable priority values. In this case, arbitration circuitry still schedules access to a shared resource according to the higher priority of either a pair of priority values or a single priority value.
In another embodiment, one or more devices which access a shared resource do not provide variable priority values as described above. In this case, access for that device is scheduled according to a fixed or positional priority, such as a resource, number using a fixed hierarchical scheme or a round robin scheme, for example.
It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.
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On 11/02/2010 07:08 AM, Daniel P. Berrange wrote: > Migration just seems togo from bad to worse. We already had to > introduce a second migration protocol when adding the QEMU driver, > since the one from Xen was insufficiently flexible to cope with > passing the data the QEMU driver required. > > This patch attempts to introduce a version 3 that uses the > improved 5 step sequence > > * Src: Begin > - Generate XML to pass to dst > - Generate optional cookie to pass to dst > > * Dst: Prepare > - Get ready to accept incoming VM > - Generate optional cookie to pass to src > > * Src: Perform > - Start migration and wait for send completion > - Generate optional cookie to pass to dst > > * Dst: Finish > - Wait for recv completion and check status > - Kill off VM if failed, resume if success > - Generate optional cookie to pass to src > > * Src: Confirm > - Kill off VM if success, resume if failed Are we any closer to implementing this new migration protocol? Meanwhile, I just came up with a question - how does live migration interact with transient changes? For example, consider Osier's recent patches for things like virDomainIsUpdated which tracks whether a running guest has had transient changes that should be tracked as long as the guest runs, but which should not impact the persistent xml definition of the guest when it stops and is restarted. Does that mean that live migration has to send two XML definitions over the wire, for both the persistent definition (to be used if the guest is stopped and restarted) as well as the transient definition (to accurately reflect the running state of the guest, including currently hot-plugged devices)? Does this protocol accurately allow for the transfer of two differing XML descriptions associated with a single running domain? -- Eric Blake eblake redhat com +1-801-349-2682 Libvirt virtualization library http://libvirt.org
Description: OpenPGP digital signature


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5 Very Berry Lipglosses
Finding a rich, deep pink or berry lipgloss that doesn't settle into lip lines or look like a splotchy mess is harder than you'd think, but here are five of my top picks that won't give you such a hard time! What are your favorite deep pink and berry lip glosses?
- Revlon Adorned — a bold, fuchsia-red
- Giorgio Armani #523 — a vivid, pink-red with cool undertones
- Marc Jacobs Beauty Studded Kiss — a shimmering, muted berry
- Illamasqua Belladonna — a muted, fuchsia pink
- NARS Mexican Rose — a soft, raspberry pink
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2013 NBA All-Star
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Deputy Commissioner Adam Silver of the NBA addresses the media before... News Photo2013,Adam Silver,Basketball - NBA Pro,Basketball - Sport,Gulf Coast States,Horizontal,Houston - Texas,NBA All-Star Saturday Night,NBA All-Star Weekend,Speech,Sport,Texas,The Media,Toyota Center - Houston,USAPhotographer Nathaniel S. ButlerCollection: National Basketball Association 2013 NBAEHOUSTON, TX - FEBRUARY 16: Deputy Commissioner Adam Silver of the NBA addresses the media before State Farm All-Star Saturday Night of the 2013 NBA All-Star Weekend on February 16, 2013 at the Toyota Center in Houston, Texas. NOTE TO USER: User expressly acknowledges and agrees that, by downloading and or using this photograph, User is consenting to the terms and conditions of the Getty Images License Agreement. Mandatory Copyright Notice: Copyright 2013 NBAE (Photo by Nathaniel S. Butler/NBAE via Getty Images)


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Broccoli Soufflé Roulade
|1⁄4 Cup (4 tbs) (1/2 Stick)
|All purpose flour
|1⁄2 Cup (8 tbs)
|1⁄2 Teaspoon
|2 Cup (32 tbs)
|4 , separated
|Frozen broccoli
|20 Ounce (2 Packages, 10 Ounces Each)
|Shredded swiss cheese
|3⁄4 Cup (12 tbs)
|Swiss cheese sauce
|1⁄4 Cup (4 tbs) (Adjust Quantity As Needed)
1. Grease a 15x10x1-inch jelly-roll pan; line the pan with waxed paper; grease paper; dust with flour.
2. Melt the butter or margarine in a medium-size saucepan. Blend in flour and salt; stir in the milk. Cook and stir until mixture thickens and bubbles 3 minutes.
3. Beat egg whites until they form soft peaks in a medium-size bowl. Beat egg yolks slightly in a large bowl. Slowly beat hot mixture into egg yolks, until blended. Fold beaten egg whites into egg yolks. Spread evenly in pan.
4. Bake in moderate oven (325°) for 45 minutes, or until golden and top springs back when touched.
5. While omelet bakes, cook broccoli; drain and cut into 1-inch pieces. Reserve 1/2 cup for garnish.
6. Make Swiss Cheese Sauce.
7. Remove omelet from the pan this way: Loosen around the edges with spatula; cover it with waxed paper or foil. Place a large cooky sheet or tray on top, then quickly turn upside down. Lift pan; peel off paper.
8. Arrange the broccoli in a single layer on top; sprinkle with cheese; drizzle 1/2 cup of hot cheese sauce over. Starting at a short end, roll the omelet, jelly-roll fashion, lifting waxed paper or foil to guide it.
9. Lift roll onto platter with two wide spatulas. Drizzle about 1/2 cup more sauce over roll and garnish with reserved broccoli.
10. Cut roll in thick slices. Pass remaining sauce.


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Pay, Renew & Replace
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Castle Hill Service Centre opens Friday 29 May, 7am
The Castle Hill Service Centre will open to the public on Friday 29 May, 7am at Home Hub Castle Hill, Level 1 (South Building), 18 Victoria Avenue. The Castle Hill registry at 18 Anella Av will relocate to the new one-stop shop where customers can process over 800 NSW Government transactions including motor registry, Fair Trading and Birth, Deaths and Marriages services.
Construction commences at Service NSW Warners Bay
Minister for Finance, Services and Property Dominic Perrottet announced that construction of the much anticipated Warners Bay Service NSW centre has commenced.


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An organization of nonbelievers is threatening legal action against public schools that participate in an evangelical Christian charity that delivers Christmas toys to poor children.
The American Humanist Association [7], a national advocacy organization with 20,000 members nationwide, sent letters this week to two public elementary schools after parents complained their children were being asked to collect toys and money for Operation Christmas Child. [8]
Operation Christmas Child is a project of Samaritan's Purse, an evangelical relief organization founded by Franklin Graham, son of evangelist Billy Graham. Its stated mission is "to follow the example of Christ by helping those in need and proclaiming the hope of the Gospel."
The toys collected by Operation Christmas Child come with an invitation for recipients to accept Christianity. Since its founding in 1993, Operation Christmas Child has sent 100 million boxes of toys to poor children.
According to the humanist association, East Point Academy in West Columbia, S.C., has organized a toy drive and raised funds for the charity for at least three years. A second school, SkyView Academy in Highlands Ranch, Colo., has participated for "several years" and has acknowledged packaging 500 toy boxes in 2012.
Both schools received letters [9] from the AHA informing them their actions are unconstitutional. The same day it received the letter, East Point Academy said it would cut its ties with the charity [10] out of "an abundance of caution because we do not want to expend school financial resources defending a lawsuit."
Monica Miller, legal counsel for the AHA's Appignani Humanist Legal Center [11], said the schools are violating the First Amendment's guarantee of the separation of church and state and its ban against government endorsement of religion.
"There is also a problem of a lack of transparency," she said. "One of the parents was not aware of the Christian nature [of Operation Christmas Child] and he let his kids participate because he assumed the school would not promote religion."
In its letter to the schools, AHA described the toys as "bribes," and Miller said schoolchildren were also promised incentives for participation, such as pizza parties and free dress days.
Kelly Wells, a spokeswoman for the DeMoss Group, a public relations firm that represents Samaritan's Purse, said in an email that the organization is aware that public schools participate in its annual toy drive but does not know how many are involved.
"The project is very clear in its marketing material and website that its mission is to demonstrate God's love in a tangible way to needy children around the world," Wells wrote. "Therefore, Operation Christmas Child's goal is to to generate participation in and through local churches and like-minded groups . . . Of course, any person or group is welcome to participate in packing shoebox gifts if they so choose."
The AHA has not yet heard from the Colorado school, and Miller said the association will pursue a lawsuit if the school does not terminate its participation.
Kimberly Winston writes for Religion News Service. Via RNS [12].
[1] http://sojo.net/blogs/gods-politics
[2] http://sojo.net/biography/kimberly-winston
[3] http://sojo.net/blogs/2013/11/14/humanists-warn-public-schools-over-franklin-graham%E2%80%99s-%E2%80%98operation-christmas-child%E2%80%99#comment-covenant
[4] http://sojo.net/letter-to-web-editor?post=Humanists%20Warn%20Public%20Schools%20over%20Franklin%20Graham%E2%80%99s%20%E2%80%98Operation%20Christmas%20Child%E2%80%99
[5] http://sojo.net/donate
[6] http://sojo.net/sites/default/files/mainimages/blog/thumbRNS-GRAHAM-ATHEIST111413-427x283.jpg
[7] http://americanhumanist.org/
[8] http://www.samaritanspurse.org/what-we-do/operation-christmas-child/
[9] http://americanhumanist.org/system/storage/2/23/7/4719/letter_re_Operation_Christmas_Child_Columbia_SC.pdf
[10] http://www.americanhumanist.org/system/storage/2/30/3/4737/Operation+Christmas+Child.pdf
[11] http://humanistlegalcenter.org/
[12] http://www.religionnews.com/


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Talk about a Super Group….White Stripes Jack White has formed a second side band called The Dead Weather.
Singer with The Kills, Alison Mosshart, also plays drums in the new project. The lineup includes Jack Lawrence, the bass player with White's other pet project, the Raconteurs, and Queens of the Stoneage guitarist Dean Fertita.
A lucky bunch got to hear a few of the new tunes when White and band played at the opening of Jack White's new Nashville office. Its debut album, "Horehound," is due June 9 on White's Third Man Records imprint, but two of the songs are available now on iTunes: "Hang You From The Heavens" and a cover of Gary Numan's "Are Friends Electric?"
The Dead Weather is planning to support "Horehound" with a tour this June.


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June 5, 2012
It is difficult to capture the allure of a small stream, wild brook trout and complete solitude.
Stories this photo appears in:
Back from the ponds
Notes from the North Woods
The blackflies are back, and so are the tourists, just as the fishing season has finally hit full stride.
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The Department of Labor's Veterans' Employment and Training Services (VETS) recently issued a special announcement on its website indicating that the VETS 100/100A online reporting application is now live.
In our previous Legal Alert entitled, "DOL Extends Deadline for Second Time to Submit VETS 100/VETS 100A Reports," we reported that VETS extended the deadline for applicable federal contractors to file a VETS 100/VETS 100A Report due to technical difficulties with the online reporting application. The deadline is now December 30, 2011. VETS recently issued a special announcement on its website indicating that the VETS 100/100A online reporting application is now live. Federal contractors required to file a VETS 100/100A may now electronically submit their reports using the VETS 100 reporting application for the 2011 filing cycle.
Please see full article below for more information.
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Grimlock, the ferocious leader of the Dinobots, has joined the Autobots in their fight against the evil Decepticons! Rumble and battle with this oversized, plush Transformer that features 10 battle sounds putting you right in the middle of the fight for the universe! Requires 3 "AG13" batteries (included). Ages 3 and up. Each sold separately.
© 2015 Funrise Toy Corp. All Rights Reserved


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The Reading Life With Wendy Rodrigue And Ann Patchett
By Susan Larson
This week on The Reading Life: Wendy Rodrigue talks about her life with artist George Rodrigue in an interview about her book, The Other Side of the Painting, recorded earlier this year.
We'll also hear from writer Ann Patchett, whose new essay collection is This Is the Story of a Happy Marriage. And I'll have a few thoughts on the literary year 2013.
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Seen this trailer? I can almost guarantee that anyone who likes this film has a Tolstoy novel on their shelf that they either haven't read, or after the first 50 pages gave up when they couldn't remember whether Karpovoloskaya was the doctor, the maid, or the corporal.
After watching the trailer, my trigger finger got sweaty in a quasi-erotic… Read the rest
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Crockpot Barbacoa
Community Recipe from
Recipe Time
Cook Time:
Prep Time:
- 3 pound(s) bone in chuck roast
- 1/2 cup(s) chopped cilantro for garnish
- 3 tablespoon(s) cider vinegar
- 1/2 cup(s) finely chopped white onion
- 8 garlic cloves, unpeeled
- teaspoon(s) ground black pepper
- 1/4 cup(s) ground dried ancho chile powder
- 1 lime, cut into 6 wedges for servin
- 1. Cut a slit in the side of each garlic clove. Place them in a microwaveable bowl, cover with plastic wrap, poke holes in the top and microwave for 30 seconds on high. Cool until handleable, then slip off the papery husks.
- 2. One by one, drop the garlic cloves into a running food processor, letting each get thoroughly chopped before adding the next. Add the chile powder, cumin, black pepper, vinegar, 1 teaspoons salt and 1/2 cup water and pulse to blend.
- 3. Place the meat in a large crock pot. Scrape the marinade onto the meat, then spread it sloppily over the top and sides. Pour enough water into the slow-cooker to cover the lower 1/2 inch of roast. Cover and slow cook on high for 6 hours or until meat is tender. Carefully remove meat with a slotted spoon onto a large plate, pulling away the bones.
- 4.Degrease the cooking broth and boil it down in a saucepan to concentrate the flavors. Ladle it over the meat and garnish with the onions and cilantro.
April 2010
This recipe is a personal recipe added by raestone1007 and has not been tested or endorsed by MyRecipes.
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Crockpot Barbacoa Recipe at a Glance
- COURSE: Main Dishes
- CONVENIENCE: Quick/Easy
- CUISINE: Mexican
- MAIN INGREDIENT: Beef
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Staff Reporter
Accused found to have used duplicate keys to open locks
Coimbatore: The Coimbatore City Police have achieved a significant breakthrough in the bank burglary case by arresting the accused, besides recovering 4.170 kg of gold jewellery worth over Rs. 52.01 lakh, cash Rs. 8.3 lakhs and bank documents relating to the depositing of Rs. 2 lakh stolen cash.
Talking to reporters, the City Police Commissioner, C.K. Gandhirajan said that a burglary was noticed in the Dhanalakshmi Bank on Cross Cut Road on October 29.
The doors and windows remained intact and the burglar had used duplicate keys to gain entry into the bank premises. The bank officials reported that Rs. 10,38,600 cash and gold jewellery weighing 4.170 gm was missing.
Mr.Gandhirajan said that special police teams were formed under the Supervision of the Deputy Commissioner of Police (Crime), P. Nagarajan and the teams led by Assistant Commissioner of Police (Crime), S. Jayapandian fanned out in different directions following a vital clue that one person who was staying with the bank officials in a lodge might have been behind the burglary, since he went missing after the occurrence.
Inquiries revealed that the suspect, Raja alias Rajaram alias David Raja of Virudhunagar district, who was posing as a Vigilance Officer from the Union Government, had established friendship with the bank officials, namely Ramesh and Sethuraman.
After gaining their confidence, the accused managed to prepare bogus keys for all the locks in the bank and gained entry into the bank by using the bogus keys during the weekend.
The police traced the whereabouts of the absconding accused found to be constantly on the move and nabbed him at Erode on Wednesday night.
Commissioner said inputs on the accused by an intelligence wing team led by Inspector K. Balamurugan helped in apprehending the accused.
The police recovered four duplicate keys for the bank door locks, two original keys of the safe vault and a toy gun from his person.
On information from the accused on the whereabouts of the booty, the police recovered Rs 8.30 lakh cash, jewellery weighing 4.170 kg worth Rs 52.01 lakhs and bank deposit receipts for Rs 2 lakhs of the stolen money.
Commissioner appreciated the special police teams including the DCP, ACP and Inspectors, K. Gowthaman, T.K.K. Senthilkumar, K. Ramachandran and M. Vinod besides sub-inspectors and constables for the swift reaction, leading to a breakthrough within three days.
Mr.Gandhirajan exhorted the bankers to co-operate with the police in preventing such incidents of crime. The bankers should remain sensitive to the requests and advisories of the police in preventive efforts.
He said that every bank and ATM premises should have a security guard round the clock who should be physically agile.
There is a pertinent need to equip the bank premises and ATM kiosks with surveillance cameras and burglar alarms that are connected to Uninterrupted Power Supply (UPS) system so that miscreants could not succeed by snapping the power lines.
Through such preventive and proactive measures, these incidents could be totally curbed. Every jurisdiction police officer has been asked to visit the banks and sensitise them on the same and also to check for compliance levels.


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FERC National Action Plan for Demand Response
- Publication Date: June 2010
- Publishing Organization: U.S. Department of Energy Federal Energy Regulatory Commission
- Format: PDF
- Keywords:
Consumer Behavior,Demand Response,Standards and Interoperability,national action plan,states,localities,regions
- Summary:
As part of the Energy Independence and Security Act of 2007 the Federal Energy Regulatory Commision (FERC) was required to develop a national plan for demand response in the electricity sector. The National Action Plan is intended to be an action plan for the nation for implementation by states, localities, and regions.
Document Summary
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Mensagens e PoemasTwitter Statistics
@mpoemas - Tracking since December 16, 2009
Frases e Mensagens de Bom dia e Otimismo, Mensagens de Amor, e Saiba diariamente os dias dos profissionais e datas importantes!
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We track these Twitter stats since December 16, 2009 . You can see how many followers Mensagens e Poemas lost or gained and what the prediction is for tomorrow or the next 15 days, together with all kinds of other stats like rank compared to all Twitter users, tweets etc.
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"I just unlocked the 6-month graphs on Twitter Counter.
Find out more http://twittercounter.com/pages/you via @TheCounter #paidwithatweet"


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It will be a while before we finally get to see which character will be bumped off next. And if all the blood and gore is getting to you, and you want to focus on something more pleasant. This compilation of possible romantic pairings in the upcoming season of Game of Thrones (GOT) could be the thing. The world of GOT is all about possibilities. So why not extend that to these characters, who may or may not get together onscreen, but will have many fans rooting for them either way.
Jaime Lannister and Brienneof Tarth
We started off with hating Jaime but have come to the realisation that's he's not so bad. He proved that when he came back to save Brienne from being mauled by a bear, and risked his life so she could make it. They have been through and emotional journey, with him losing his hand, and the dangers they encountered. Jaime's bravery and Brienne's loyality would make for a good combination, and an interesting pair. They have the chemistry, but will they make it work? We would definitely want to see that in the upcoming season.
Jon Snow and DaenerysTargaryen
Jon has the morals, and Dany has the rightful claim to the iron throne. Both are walking on the path of righteousness, so it makes sense for them together and help make Westeros a better place. It would free it from the hands of the Lannisters and the Baratheons, who have only contributed to the upheaval, and restore much needed peace in the Seven Kingdoms.
Cersei Lannister and Littlefinger
Two evil minds who have manipulated situations and people to get their way. Personally, we want them together so the lives of two other people are not destroyed, though we fear the havoc these two would create if they did end up together. It would still be interesting to see who outwits each other in this game of upmanship.
Sansa and Littlefinger
As seen in the earlier seasons Lord Petyr Baelish who also goes by the name Littlefinger seems to have transferred his affections from Sansa's mother to her. While it may seem predatory, we are not sure if he has a bigger plan in mind as is always the case with Littlefinger. Nevertheless this odd pairing has immense possibilities. In her new avatar will Sansa stop playing the victim? It definitely looks that way, she lied under oath to protect Baelish, and has proved that Westeros has taught her a lot. If nothing else it has made her a convincing actress and she may just turn the tables on the wily Littlefinger.
Sansa and Tyrion
We do feel sorry for Tyrion who has been battling demons all his life. Brought up by a father who always wanted him dead, and a sister who also feels the same way, and having killed the love of his life Shea, and condemned to death even though he is innocent, you can't help but root for him everytime he manages to escape from the claws of death. While his and Sansa's marriage was just a ploy to keep power in the hands of the Lannisters, we actually hope these two end up together. Maybe Tyrion can save Sansa from the manipulative ways of Littlefinger and build a relationship with Sansa based on friendship. Though the trust issues will have to be worked out. It's a long shot, but from what we have witnessed so far in GOT, anything and everything is possible.
Unsullied leader Grey Worm and Missandei
Grey Worm and Missandei are victims of circumstances sharing a common destiny – being sold as slaves. Dany has managed to set them free. But what does the future hold for them. They clearly like each other, but can something come of it? We would like to see more of them together.


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|Property type
|Minimum Stay
|3 nights
About Vacation Rentals in Barbados
Whether your idea of an ideal holiday includes quiet relaxation by the pool or on the beach or lively night life, Vacation Rentals in Barbados, our tropical coastal locations can offer it.
We provide luxury beach front rentals at the sea's edge. Specialising in the rental of studios, one, two, three and four bedroom apartments and Penthouses on the beach at reasonable prices, each offering stunning sea views and fully air-conditioned.
With beach front locations from East to West we have affordable vacation rentals for everyone. From the rugged East coast of Barbados with cliff top location and a backdrop of the Atlantic Ocean to the calmer waters of the Caribbean Sea at our three South Coast beach front locations:
Whether you prefer beautiful Maxwell Beach with a half a mile of pristine white sandy beach, lively St Lawrence Gap, beach front condos in Hastings, or how about the unspoilt beauty of the East Coast? We have a perfect vacation rental to call home during your stay in the paradise island of Barbados.
Fabulous three bedroom penthouse with hot tubs and spacious patios. Ideal for entertaining, party goers and those that just like more space and more than a touch of luxury!!
With all these amazing properties comes exceptional customer service provided by on-site management and staff at all our locations. Our mission is to ensure you have a wonderful vacation in paradise!
Please contact me for further information or browse our site Vacation Rentals in Barbados to view our amazing selection of holiday and vacation rentals.
Barbara Trotman, at your service.
Hi Barbara,
I just wanted to thank you again for how helpful you were in booking our stay at St. Lawrence Beach Condos. We thoroughly enjoyed both condos.
I want to especially highlight Ricardo and the night watch man (unsure of his name- older gentleman). While everyone was friendly, these two were particularly accommodating and helpful to our requests- especially Ricardo. He's a gem and a real value to the property.
We had a wonderful time again staying in almost heaven. The condo is very comfortable. We did have just a couple of little issues this time. We only had one light bulb working in the bedroom. The kettle is a bit small and not that nice. The towels after the first change were a bit old and stiff as was the bedding. past from that everything was great and the location is just perfect, even if you don't go out into the Gap, once the bedroom door is closed all you can hear is the deal heaven, we'll almost!!!!!
We stayed in three different parts of the island as this was our first trip to Barbados. We found St. Lawrence Gap to be a great place if you want to walk rather than drive to many different restaurants. We stayed in apartment 8 - 'One Love' and it was romantic as described. The feeling was of peace and calm and the colour scheme of the main bedroom reflected the beautiful blue sea which it overlooks. The pool was never crowded and the tiny beach and pier were a bonus. On other parts of the island (at this time of year) the temperature we felt was higher, but there is always a breeze here.
We will certainly return to Barbados and to these lovely apartments.
P.S. Thanks to Jerry for always being so helpful!
St Lawrence Beach Apartments are all beach facing apartments overlooking the Caribbean sea, on the South coast of Barbados, in the heart of St. Lawrence Gap, the entertainment and dining spot in Barbados, 2 miles from Bridgetown. The apartments have theirs own small private beach and jetty, or Dover and Worthing beaches are a short stroll away. Go scuba diving from Half Moon Bay, or it is well worth going on a safari around the island and in addition exploring by car is both an adventure and fun. The island is so small you cannot get lost. Go to both South Point and North Point to see both ends of Barbados and see the differences the island has to offer. Bathsheba on the East Coast is particularly wild and in stark contrast to the tranquility of the West Coast and it's beaches. Oistins 'Fish Fry' on Friday night is an absolute must and just a 10 minute drive from the apartments. After dining, listen to the Reggae music or try ballroom dancing to music from the 60s at Lexies Bar
|Rate Period
|Weekend Night
Apr 15 2015 - Dec 14 2015
3 night minimum stay
Dec 15 2015 - Apr 14 2016
3 night minimum stay
|No additional mandatory fees
Rates are given for the 1-bedroom 2-bath configuration of this property. It may also be rented as a two-bedroom, two-bath apartment:
2-BR High Season: $355US/£235 nightly
2-BR Low Season: $260US/£170 nightly
Xmas 22nd Dec - 5th January $500/£335 nightly
Please note that Jul 27 - Aug 10th High Season prices apply.
Price includes maid service, utilities and wireless internet. A deposit of $400/£250 secures the booking, balance payable 8 weeks prior to departure.
Payment is usually accepted in the quoted currency (GBP) unless the currency and the amount is specifically agreed in advance with the owner / advertiser.


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Home > Security & Privacy::Other > HT System Administrator 7.2
HT System Administrator 7.2
Restict your employees' activity and internet usageCompany: Hidetools
Platform: Win2000,Win7 x32,Win7 x64,Win98,WinServer,WinVista,WinVista x64,WinXP
Size: 1759 KB
Price: USD $39.95
Release Date: 2010-04-08
Screenshot URL: http://www.hidetools.com/hsa/system_administrator.jpg
Category: Security & Privacy::Other
System Administrator is a managing tool designed to prevent unwanted PC activities. The product can block programs, websites, chats, browsers, etc. It helps the controller to restrict installer launch and protect the computer against inexperienced users. System Administrator helps prevent non-work related activities from being accessed and avoid company losses. The program is highly protected and hidden
Related keywords:
system administrator restrict access block websites block website block myspace block facebook block program block applic
HT System Administrator Related Titles:Auto Hide IP 184.108.40.206 - Hide your real IP to protect your privacy automatically on the Internet.
Mask My IP 18.104.22.168 - Mask My IP hides your real IP and protects your online security and privacy.
Real Hide IP 22.214.171.124 - Hide your IP to protect your privacy on the Internet with the click of a button.
Free Hide IP 188.8.131.52 - Hide your real IP address to protect your privacy for FREE with Free Hide IP.
Platinum Hide IP 188.8.131.52 - Hide your real IP address and give you platinum online privacy protection.
Hide IP Easy 188.8.131.52 - Use Hide IP Easy to hide your real IP address and protect your privacy easily.
Super Hide IP 22.214.171.124 - Hide your real IP and give you super privacy protection on the Internet.
Falco Watcher 6.1 - Digital video monitoring.
PKF Product Key Finder 1.3.6 - PKF Product Key Finder recovers product keys from local computer.
Botshield 1.0.0 - IDS/IPS security software protects against Hackers and Botnets
Free File Eraser 1.7.8 - Free file eraser to permanently delete any files/folders and wipe Recycle Bin.
Spyrix Keylogger Free 7.0 - Remote monitoring via web account: keylogger, screenshots, facebook, web
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Solaris 10u4, Geforce 6100,nforce 410
I cannot get the normal Solaris drivers to recognize my video controller. If somebody knows it should work, please let me know how.
I downloaded and installed the NVIDIA-Solaris-x86-100.14.19.run file and executed it. On reboot x did not start and Xerrors had a line that the glx module could not be loaded (it is not on my system). I added a line to the xorg.conf file, Option "NvAGP" "0", but then I think the error was that the xstol module could not be loaded. It does not appear that I have the right modules - what should I do?
Re: Solaris 10u4, Geforce 6100,nforce 410
Comment out the line Load "xtsol" in Section "Module" in /etc/X11/xorg.conf, like this
Section "Module"
Re: Solaris 10u4, Geforce 6100,nforce 410
If I do that it goes back to an error about the glx module. The origianl error concerned the glx module, so I commented out the "load glx" line. I still got an error about glx - I think it was a different error. I then added the 'option "NvAGP" "0"' line and the error about the xtsol module came up. If I comment out the load xtsol line, then I get an error about the glx module again.
Does anybody know if I should have a glx module with 10u4? If so what is its name?
Re: Solaris 10u4, Geforce 6100,nforce 410
If you want any OpenGL accleration, you need the glx module. You really need to generate and attach a bug report if you'd like further assistance.
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